support hot plug CPUs. This module can be copied into a CPU specific package\r
and customized if these additional features are required.\r
\r
-Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2015, Red Hat, Inc.\r
\r
This program and the accompanying materials\r
RegisterTable[Index].InitialApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;\r
RegisterTable[Index].TableLength = 0;\r
RegisterTable[Index].AllocatedSize = 0;\r
- RegisterTable[Index].RegisterTableEntry = NULL;\r
+ RegisterTable[Index].RegisterTableEntry = 0;\r
\r
RegisterTable[NumberOfCpus + Index].InitialApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;\r
RegisterTable[NumberOfCpus + Index].TableLength = 0;\r
RegisterTable[NumberOfCpus + Index].AllocatedSize = 0;\r
- RegisterTable[NumberOfCpus + Index].RegisterTableEntry = NULL;\r
+ RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;\r
}\r
AcpiCpuData->RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;\r
AcpiCpuData->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);\r
/** @file\r
Definitions for CPU S3 data.\r
\r
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
UINT32 InitialApicId;\r
//\r
- // Buffer of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be\r
+ // Physical address of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be\r
// allocated below 4GB from memory of type EfiACPIMemoryNVS.\r
//\r
- CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;\r
+ EFI_PHYSICAL_ADDRESS RegisterTableEntry;\r
} CPU_REGISTER_TABLE;\r
\r
//\r
/** @file\r
Code for Processor S3 restoration\r
\r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
for (Index = 0; Index < NumberOfCpus; Index++) {\r
- DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);\r
- ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL);\r
- CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);\r
+ RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);\r
+ ASSERT (RegisterTableEntry != NULL);\r
+ CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);\r
//\r
// Go though all MSRs in register table to initialize MSR spin lock\r
//\r
- RegisterTableEntry = DestinationRegisterTableList[Index].RegisterTableEntry;\r
for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {\r
if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {\r
//\r
InitMsrSpinLockByIndex (RegisterTableEntry->Index);\r
}\r
}\r
+ DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;\r
}\r
}\r
\r