Some AArch64 platforms have RAM and flash devices >4GB.
Update some additional Pcd entries to 64-bit, and change
the corresponding PcdGet32 calls to PcdGet64.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16325
6f19259b-4bc3-4df7-8a09-
765794883524
20 files changed:
#\r
# ARM Secure Firmware PCDs\r
#\r
#\r
# ARM Secure Firmware PCDs\r
#\r
- gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r
+ gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r
gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
- gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F\r
+ gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r
gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
\r
#\r
# ARM Normal (or Non Secure) Firmware PCDs\r
#\r
gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
\r
#\r
# ARM Normal (or Non Secure) Firmware PCDs\r
#\r
- gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
- gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
\r
#\r
gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
\r
#\r
//\r
// Get the Sec or PrePeiCore module (defined as SEC type module)\r
//\r
//\r
// Get the Sec or PrePeiCore module (defined as SEC type module)\r
//\r
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet32(PcdSecureFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);\r
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdSecureFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);\r
if (!EFI_ERROR(Status)) {\r
Status = GetImageContext (FfsHeader,&ImageContext);\r
if (!EFI_ERROR(Status)) {\r
if (!EFI_ERROR(Status)) {\r
Status = GetImageContext (FfsHeader,&ImageContext);\r
if (!EFI_ERROR(Status)) {\r
//\r
// Get the PrePi or PrePeiCore module (defined as SEC type module)\r
//\r
//\r
// Get the PrePi or PrePeiCore module (defined as SEC type module)\r
//\r
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet32(PcdFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);\r
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);\r
if (!EFI_ERROR(Status)) {\r
Status = GetImageContext (FfsHeader,&ImageContext);\r
if (!EFI_ERROR(Status)) {\r
if (!EFI_ERROR(Status)) {\r
Status = GetImageContext (FfsHeader,&ImageContext);\r
if (!EFI_ERROR(Status)) {\r
//\r
// Get the PeiCore module (defined as PEI_CORE type module)\r
//\r
//\r
// Get the PeiCore module (defined as PEI_CORE type module)\r
//\r
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet32(PcdFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);\r
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);\r
if (!EFI_ERROR(Status)) {\r
Status = GetImageContext (FfsHeader,&ImageContext);\r
if (!EFI_ERROR(Status)) {\r
if (!EFI_ERROR(Status)) {\r
Status = GetImageContext (FfsHeader,&ImageContext);\r
if (!EFI_ERROR(Status)) {\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
\r
# Stack for CPU Cores in Non Secure Mode\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
\r
# Stack for CPU Cores in Non Secure Mode\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
OUT UINTN* JumpAddress\r
)\r
{\r
OUT UINTN* JumpAddress\r
)\r
{\r
- *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+ *JumpAddress = (UINTN)PcdGet64 (PcdFvBaseAddress);\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
OUT UINTN* JumpAddress\r
)\r
{\r
OUT UINTN* JumpAddress\r
)\r
{\r
- *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+ *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
OUT UINTN* JumpAddress\r
)\r
{\r
OUT UINTN* JumpAddress\r
)\r
{\r
- *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+ *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
//\r
ASSERT (NewSize >= SIZE_128MB);\r
ASSERT (\r
//\r
ASSERT (NewSize >= SIZE_128MB);\r
ASSERT (\r
- (((UINT64)PcdGet32 (PcdFdBaseAddress) +\r
+ (((UINT64)PcdGet64 (PcdFdBaseAddress) +\r
(UINT64)PcdGet32 (PcdFdSize)) <= NewBase) ||\r
(UINT64)PcdGet32 (PcdFdSize)) <= NewBase) ||\r
- ((UINT64)PcdGet32 (PcdFdBaseAddress) >= (NewBase + NewSize)));\r
+ ((UINT64)PcdGet64 (PcdFdBaseAddress) >= (NewBase + NewSize)));\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
CopyMem (NewBase, Base, FdtSize);\r
PcdSet64 (PcdDeviceTreeBaseAddress, (UINT64)(UINTN)NewBase);\r
\r
CopyMem (NewBase, Base, FdtSize);\r
PcdSet64 (PcdDeviceTreeBaseAddress, (UINT64)(UINTN)NewBase);\r
\r
- BuildFvHob (PcdGet32(PcdFvBaseAddress), PcdGet32(PcdFvSize));\r
+ BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));\r
\r
return EFI_SUCCESS;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
// Ensure the Global Variable Size have been initialized\r
ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));\r
\r
// Ensure the Global Variable Size have been initialized\r
ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));\r
\r
- GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);\r
+ GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);\r
\r
if (VariableSize == 4) {\r
*(UINT32*)Variable = ReadUnaligned32 ((CONST UINT32*)(GlobalVariableBase + VariableOffset));\r
\r
if (VariableSize == 4) {\r
*(UINT32*)Variable = ReadUnaligned32 ((CONST UINT32*)(GlobalVariableBase + VariableOffset));\r
// Ensure the Global Variable Size have been initialized\r
ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));\r
\r
// Ensure the Global Variable Size have been initialized\r
ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));\r
\r
- GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);\r
+ GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);\r
\r
if (VariableSize == 4) {\r
WriteUnaligned32 ((UINT32*)(GlobalVariableBase + VariableOffset), *(UINT32*)Variable);\r
\r
if (VariableSize == 4) {\r
WriteUnaligned32 ((UINT32*)(GlobalVariableBase + VariableOffset), *(UINT32*)Variable);\r
// Ensure the Global Variable Size have been initialized\r
ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));\r
\r
// Ensure the Global Variable Size have been initialized\r
ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));\r
\r
- GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);\r
+ GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);\r
\r
return (VOID*)(GlobalVariableBase + VariableOffset);\r
}\r
\r
return (VOID*)(GlobalVariableBase + VariableOffset);\r
}\r
#include <Library/PcdLib.h>\r
#include <Library/DebugLib.h>\r
\r
#include <Library/PcdLib.h>\r
#include <Library/DebugLib.h>\r
\r
-#define IS_XIP() (((UINT32)PcdGet32 (PcdFdBaseAddress) > (UINT32)(PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize))) || \\r
- ((PcdGet32 (PcdFdBaseAddress) + PcdGet32 (PcdFdSize)) < PcdGet64 (PcdSystemMemoryBase)))\r
+#define IS_XIP() (((UINT32)PcdGet64 (PcdFdBaseAddress) > (UINT32)(PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize))) || \\r
+ ((PcdGet64 (PcdFdBaseAddress) + PcdGet32 (PcdFdSize)) < PcdGet64 (PcdSystemMemoryBase)))\r
\r
// Declared by ArmPlatformPkg/PrePi Module\r
extern UINTN mGlobalVariableBase;\r
\r
// Declared by ArmPlatformPkg/PrePi Module\r
extern UINTN mGlobalVariableBase;\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
OUT UINTN* JumpAddress\r
)\r
{\r
OUT UINTN* JumpAddress\r
)\r
{\r
- *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+ *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
UINTN InterruptId;\r
\r
// The secondary cores will execute the firmware once wake from WFI.\r
UINTN InterruptId;\r
\r
// The secondary cores will execute the firmware once wake from WFI.\r
- SecondaryStart = (VOID (*)())PcdGet32 (PcdFvBaseAddress);\r
+ SecondaryStart = (VOID (*)())(UINTN)PcdGet64 (PcdFvBaseAddress);\r
{\r
CHAR8 Buffer[100];\r
UINTN CharCount;\r
{\r
CHAR8 Buffer[100];\r
UINTN CharCount;\r
\r
if (FeaturePcdGet (PcdStandalone) == FALSE) {\r
\r
\r
if (FeaturePcdGet (PcdStandalone) == FALSE) {\r
\r
//\r
\r
if (ArmPlatformIsPrimaryCore (MpId)) {\r
//\r
\r
if (ArmPlatformIsPrimaryCore (MpId)) {\r
- UINTN* StartAddress = (UINTN*)PcdGet32(PcdFvBaseAddress);\r
+ StartAddress = (UINTN*)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
\r
// Patch the DRAM to make an infinite loop at the start address\r
*StartAddress = 0xEAFFFFFE; // opcode for while(1)\r
\r
// Patch the DRAM to make an infinite loop at the start address\r
*StartAddress = 0xEAFFFFFE; // opcode for while(1)\r
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);\r
SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
\r
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);\r
SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
\r
- *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+ *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
} else {\r
// When the primary core is stopped by the hardware debugger to copy the firmware\r
// into DRAM. The secondary cores are still running. As soon as the first bytes of\r
} else {\r
// When the primary core is stopped by the hardware debugger to copy the firmware\r
// into DRAM. The secondary cores are still running. As soon as the first bytes of\r
\r
if (ArmPlatformIsPrimaryCore (MpId)) {\r
// Signal the secondary cores they can jump to PEI phase\r
\r
if (ArmPlatformIsPrimaryCore (MpId)) {\r
// Signal the secondary cores they can jump to PEI phase\r
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
+ ArmGicSendSgiTo (PcdGet32 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
\r
// To enter into Non Secure state, we need to make a return from exception\r
\r
// To enter into Non Secure state, we need to make a return from exception\r
- *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+ *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
} else {\r
// We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary\r
// cores would make crash the system by setting their stacks in DRAM before the primary core has not\r
} else {\r
// We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary\r
// cores would make crash the system by setting their stacks in DRAM before the primary core has not\r
*JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
}\r
} else {\r
*JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
}\r
} else {\r
- *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+ *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
);\r
\r
SystemMemoryTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemoryBase) + (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemorySize);\r
);\r
\r
SystemMemoryTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemoryBase) + (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemorySize);\r
- FdTop = (EFI_PHYSICAL_ADDRESS)PcdGet32(PcdFdBaseAddress) + (EFI_PHYSICAL_ADDRESS)PcdGet32(PcdFdSize);\r
+ FdTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdFdBaseAddress) + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFdSize);\r
\r
// EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE\r
// core to overwrite this area we must mark the region with the attribute non-present\r
\r
// EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE\r
// core to overwrite this area we must mark the region with the attribute non-present\r
- if ((PcdGet32 (PcdFdBaseAddress) >= PcdGet64 (PcdSystemMemoryBase)) && (FdTop <= SystemMemoryTop)) {\r
+ if ((PcdGet64 (PcdFdBaseAddress) >= PcdGet64 (PcdSystemMemoryBase)) && (FdTop <= SystemMemoryTop)) {\r
Found = FALSE;\r
\r
// Search for System Memory Hob that contains the firmware\r
NextHob.Raw = GetHobList ();\r
while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {\r
if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&\r
Found = FALSE;\r
\r
// Search for System Memory Hob that contains the firmware\r
NextHob.Raw = GetHobList ();\r
while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {\r
if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&\r
- (PcdGet32(PcdFdBaseAddress) >= NextHob.ResourceDescriptor->PhysicalStart) &&\r
+ (PcdGet64 (PcdFdBaseAddress) >= NextHob.ResourceDescriptor->PhysicalStart) &&\r
(FdTop <= NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength))\r
{\r
ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;\r
ResourceLength = NextHob.ResourceDescriptor->ResourceLength;\r
ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;\r
\r
(FdTop <= NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength))\r
{\r
ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;\r
ResourceLength = NextHob.ResourceDescriptor->ResourceLength;\r
ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;\r
\r
- if (PcdGet32(PcdFdBaseAddress) == NextHob.ResourceDescriptor->PhysicalStart) {\r
+ if (PcdGet64 (PcdFdBaseAddress) == NextHob.ResourceDescriptor->PhysicalStart) {\r
if (SystemMemoryTop == FdTop) {\r
NextHob.ResourceDescriptor->ResourceAttribute = ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT;\r
} else {\r
// Create the System Memory HOB for the firmware with the non-present attribute\r
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,\r
ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,\r
if (SystemMemoryTop == FdTop) {\r
NextHob.ResourceDescriptor->ResourceAttribute = ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT;\r
} else {\r
// Create the System Memory HOB for the firmware with the non-present attribute\r
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,\r
ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,\r
- PcdGet32(PcdFdBaseAddress),\r
- PcdGet32(PcdFdSize));\r
+ PcdGet64 (PcdFdBaseAddress),\r
+ PcdGet32 (PcdFdSize));\r
\r
// Top of the FD is system memory available for UEFI\r
NextHob.ResourceDescriptor->PhysicalStart += PcdGet32(PcdFdSize);\r
\r
// Top of the FD is system memory available for UEFI\r
NextHob.ResourceDescriptor->PhysicalStart += PcdGet32(PcdFdSize);\r
// Create the System Memory HOB for the firmware with the non-present attribute\r
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,\r
ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,\r
// Create the System Memory HOB for the firmware with the non-present attribute\r
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,\r
ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,\r
- PcdGet32(PcdFdBaseAddress),\r
- PcdGet32(PcdFdSize));\r
+ PcdGet64 (PcdFdBaseAddress),\r
+ PcdGet32 (PcdFdSize));\r
- NextHob.ResourceDescriptor->ResourceLength = PcdGet32(PcdFdBaseAddress) - NextHob.ResourceDescriptor->PhysicalStart;\r
+ NextHob.ResourceDescriptor->ResourceLength = PcdGet64 (PcdFdBaseAddress) - NextHob.ResourceDescriptor->PhysicalStart;\r
\r
// If there is some memory available on the top of the FD then create a HOB\r
if (FdTop < NextHob.ResourceDescriptor->PhysicalStart + ResourceLength) {\r
\r
// If there is some memory available on the top of the FD then create a HOB\r
if (FdTop < NextHob.ResourceDescriptor->PhysicalStart + ResourceLength) {\r
\r
SystemMemoryBase = (UINTN)PcdGet64 (PcdSystemMemoryBase);\r
SystemMemoryTop = SystemMemoryBase + (UINTN)PcdGet64 (PcdSystemMemorySize);\r
\r
SystemMemoryBase = (UINTN)PcdGet64 (PcdSystemMemoryBase);\r
SystemMemoryTop = SystemMemoryBase + (UINTN)PcdGet64 (PcdSystemMemorySize);\r
- FdBase = (UINTN)PcdGet32 (PcdFdBaseAddress);\r
+ FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);\r
FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);\r
\r
//\r
FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);\r
\r
//\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
- BuildFvHob (PcdGet32(PcdFvBaseAddress), PcdGet32(PcdFvSize));\r
+ BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));\r
\r
return EFI_SUCCESS;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
// the base of the primary core stack\r
PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
// the base of the primary core stack\r
PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
- TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r
+ TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
\r
// Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
\r
// Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
// Note also: HOBs (pei temp ram) MUST be above stack\r
//\r
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
// Note also: HOBs (pei temp ram) MUST be above stack\r
//\r
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
SecCoreData.TemporaryRamSize = TemporaryRamSize;\r
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
SecCoreData.TemporaryRamSize = TemporaryRamSize;\r
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
// the base of the primary core stack\r
PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
// the base of the primary core stack\r
PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
- TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r
+ TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
\r
// Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
\r
// Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
// Note also: HOBs (pei temp ram) MUST be above stack\r
//\r
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
// Note also: HOBs (pei temp ram) MUST be above stack\r
//\r
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
SecCoreData.TemporaryRamSize = TemporaryRamSize;\r
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
SecCoreData.TemporaryRamSize = TemporaryRamSize;\r
ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r
\r
// Copy the Common and Platform PPis in Temporrary Memory\r
ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r
\r
// Copy the Common and Platform PPis in Temporrary Memory\r
- ListBase = PcdGet32 (PcdCPUCoresStackBase);\r
+ ListBase = PcdGet64 (PcdCPUCoresStackBase);\r
CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r
CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r
\r
CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r
CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r
\r
{\r
ASSERT (GlobalVariableBase != NULL);\r
\r
{\r
ASSERT (GlobalVariableBase != NULL);\r
\r
- *GlobalVariableBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) +\r
+ *GlobalVariableBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) +\r
(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) -\r
(UINTN)PcdGet32 (PcdPeiGlobalVariableSize);\r
\r
(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) -\r
(UINTN)PcdGet32 (PcdPeiGlobalVariableSize);\r
\r
copy_cpsr_into_spsr ();\r
\r
// Call the Platform specific function to execute additional actions if required\r
copy_cpsr_into_spsr ();\r
\r
// Call the Platform specific function to execute additional actions if required\r
- JumpAddress = PcdGet32 (PcdFvBaseAddress);\r
+ JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
\r
NonTrustedWorldTransition (MpId, JumpAddress);\r
ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
\r
NonTrustedWorldTransition (MpId, JumpAddress);\r
}\r
\r
// Call the Platform specific function to execute additional actions if required\r
}\r
\r
// Call the Platform specific function to execute additional actions if required\r
- JumpAddress = PcdGet32 (PcdFvBaseAddress);\r
+ JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
\r
// Initialize architecture specific security policy\r
ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
\r
// Initialize architecture specific security policy\r
switch (ResetType) {\r
case EfiResetWarm:\r
//Perform warm reset of the system by jumping to the begining of the FV\r
switch (ResetType) {\r
case EfiResetWarm:\r
//Perform warm reset of the system by jumping to the begining of the FV\r
- StartOfFv = (CALL_STUB)(UINTN)PcdGet32(PcdFvBaseAddress);\r
+ StartOfFv = (CALL_STUB)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
StartOfFv ();\r
break;\r
case EfiResetCold:\r
StartOfFv ();\r
break;\r
case EfiResetCold:\r