MdePkg/PCI: Add missing PCI/PCIE definitions

The definitions are required by certain platform initialization
code.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Reviewed-by: Amy Chan <amy.chan@intel.com>

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 0b3a785ef1e6558bb67d42fdee5a4422eb2e619e..db24a153e15e16dd004b834de003fccc813a3ffd 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -645,18 +645,6 @@ typedef struct {
   UINT8 NextItemPtr;\r
 } EFI_PCI_CAPABILITY_HDR;\r
 \r
-///\r
-/// Power Management Register Block Definition \r
-/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
-///\r
-typedef struct {\r
-  EFI_PCI_CAPABILITY_HDR  Hdr;\r
-  UINT16                  PMC;\r
-  UINT16                  PMCSR;\r
-  UINT8                   BridgeExtention;\r
-  UINT8                   Data;\r
-} EFI_PCI_CAPABILITY_PMI;\r
-\r
 ///\r
 /// PMC - Power Management Capabilities\r
 /// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r
@@ -684,7 +672,9 @@ typedef union {
 typedef union {\r
   struct {\r
     UINT16 PowerState : 2;\r
-    UINT16 Reserved : 6;\r
+    UINT16 ReservedForPciExpress : 1;\r
+    UINT16 NoSoftReset : 1;\r
+    UINT16 Reserved : 4;\r
     UINT16 PmeEnable : 1;\r
     UINT16 DataSelect : 4;\r
     UINT16 DataScale : 2;\r
@@ -693,6 +683,36 @@ typedef union {
   UINT16 Data;\r
 } EFI_PCI_PMCSR;\r
 \r
+#define PCI_POWER_STATE_D0     0\r
+#define PCI_POWER_STATE_D1     1\r
+#define PCI_POWER_STATE_D2     2\r
+#define PCI_POWER_STATE_D3_HOT 3\r
+\r
+///\r
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
+/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+  struct {\r
+    UINT8 Reserved : 6;\r
+    UINT8 B2B3 : 1;\r
+    UINT8 BusPowerClockControl : 1;\r
+  } Bits;\r
+  UINT8   Uint8;\r
+} EFI_PCI_PMCSR_BSE;\r
+\r
+///\r
+/// Power Management Register Block Definition\r
+/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef struct {\r
+  EFI_PCI_CAPABILITY_HDR  Hdr;\r
+  EFI_PCI_PMC             PMC;\r
+  EFI_PCI_PMCSR           PMCSR;\r
+  EFI_PCI_PMCSR_BSE       BridgeExtention;\r
+  UINT8                   Data;\r
+} EFI_PCI_CAPABILITY_PMI;\r
+\r
 ///\r
 /// A.G.P Capability\r
 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r

diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index 57cfab228d7385a7dde82f47c1ddc59a3d6cf313..175c82c88ee0e06ee163135574a5a773a0428a79 100644 (file)
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -1,7 +1,7 @@
 /** @file\r
   Support for the latest PCI standard.\r
 \r
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
   (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>  \r
   This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
@@ -16,6 +16,337 @@
 #ifndef _PCIEXPRESS21_H_\r
 #define _PCIEXPRESS21_H_\r
 \r
+#include <IndustryStandard/Pci30.h>\r
+\r
+#pragma pack(1)\r
+///\r
+/// PCI Express Capability Structure\r
+///\r
+typedef union {\r
+  struct {\r
+    UINT16 Version : 4;\r
+    UINT16 DevicePortType : 4;\r
+    UINT16 SlotImplemented : 1;\r
+    UINT16 InterruptMessageNumber : 5;\r
+    UINT16 Undefined : 1;\r
+    UINT16 Reserved : 1;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_CAPABILITY;\r
+\r
+#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT                    0\r
+#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT             1\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT                        4\r
+#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT                    5\r
+#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT                  6\r
+#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE               7\r
+#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE               8\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR     10\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 MaxPayloadSize : 3;\r
+    UINT32 PhantomFunctions : 2;\r
+    UINT32 ExtendedTagField : 1;\r
+    UINT32 EndpointL0sAcceptableLatency : 3;\r
+    UINT32 EndpointL1AcceptableLatency : 3;\r
+    UINT32 Undefined : 3;\r
+    UINT32 RoleBasedErrorReporting : 1;\r
+    UINT32 Reserved : 2;\r
+    UINT32 CapturedSlotPowerLimitValue : 8;\r
+    UINT32 CapturedSlotPowerLimitScale : 2;\r
+    UINT32 FunctionLevelReset : 1;\r
+    UINT32 Reserved2 : 3;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_REG_PCIE_DEVICE_CAPABILITY;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 CorrectableError : 1;\r
+    UINT16 NonFatalError : 1;\r
+    UINT16 FatalError : 1;\r
+    UINT16 UnsupportedRequest : 1;\r
+    UINT16 RelaxedOrdering : 1;\r
+    UINT16 MaxPayloadSize : 3;\r
+    UINT16 ExtendedTagField : 1;\r
+    UINT16 PhantomFunctions : 1;\r
+    UINT16 AuxPower : 1;\r
+    UINT16 NoSnoop : 1;\r
+    UINT16 MaxReadRequestSize : 3;\r
+    UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_DEVICE_CONTROL;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 CorrectableError : 1;\r
+    UINT16 NonFatalError : 1;\r
+    UINT16 FatalError : 1;\r
+    UINT16 UnsupportedRequest : 1;\r
+    UINT16 AuxPower : 1;\r
+    UINT16 TransactionsPending : 1;\r
+    UINT16 Reserved : 10;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_DEVICE_STATUS;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 MaxLinkSpeed : 4;\r
+    UINT32 MaxLinkWidth : 6;\r
+    UINT32 Aspm : 2;\r
+    UINT32 L0sExitLatency : 3;\r
+    UINT32 L1ExitLatency : 3;\r
+    UINT32 ClockPowerManagement : 1;\r
+    UINT32 SurpriseDownError : 1;\r
+    UINT32 DataLinkLayerLinkActive : 1;\r
+    UINT32 LinkBandwidthNotification : 1;\r
+    UINT32 AspmOptionalityCompliance : 1;\r
+    UINT32 Reserved : 1;\r
+    UINT32 PortNumber : 8;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_REG_PCIE_LINK_CAPABILITY;\r
+\r
+#define PCIE_LINK_ASPM_L0S BIT0\r
+#define PCIE_LINK_ASPM_L1  BIT1\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 AspmControl : 2;\r
+    UINT16 Reserved : 1;\r
+    UINT16 ReadCompletionBoundary : 1;\r
+    UINT16 LinkDisable : 1;\r
+    UINT16 RetrainLink : 1;\r
+    UINT16 CommonClockConfiguration : 1;\r
+    UINT16 ExtendedSynch : 1;\r
+    UINT16 ClockPowerManagement : 1;\r
+    UINT16 HardwareAutonomousWidthDisable : 1;\r
+    UINT16 LinkBandwidthManagementInterrupt : 1;\r
+    UINT16 LinkAutonomousBandwidthInterrupt : 1;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_LINK_CONTROL;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 CurrentLinkSpeed : 4;\r
+    UINT16 NegotiatedLinkWidth : 6;\r
+    UINT16 Undefined : 1;\r
+    UINT16 LinkTraining : 1;\r
+    UINT16 SlotClockConfiguration : 1;\r
+    UINT16 DataLinkLayerLinkActive : 1;\r
+    UINT16 LinkBandwidthManagement : 1;\r
+    UINT16 LinkAutonomousBandwidth : 1;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_LINK_STATUS;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 AttentionButton : 1;\r
+    UINT32 PowerController : 1;\r
+    UINT32 MrlSensor : 1;\r
+    UINT32 AttentionIndicator : 1;\r
+    UINT32 PowerIndicator : 1;\r
+    UINT32 HotPlugSurprise : 1;\r
+    UINT32 HotPlugCapable : 1;\r
+    UINT32 SlotPowerLimitValue : 8;\r
+    UINT32 SlotPowerLimitScale : 2;\r
+    UINT32 ElectromechanicalInterlock : 1;\r
+    UINT32 NoCommandCompleted : 1;\r
+    UINT32 PhysicalSlotNumber : 13;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_REG_PCIE_SLOT_CAPABILITY;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 AttentionButtonPressed : 1;\r
+    UINT32 PowerFaultDetected : 1;\r
+    UINT32 MrlSensorChanged : 1;\r
+    UINT32 PresenceDetectChanged : 1;\r
+    UINT32 CommandCompletedInterrupt : 1;\r
+    UINT32 HotPlugInterrupt : 1;\r
+    UINT32 AttentionIndicator : 2;\r
+    UINT32 PowerIndicator : 2;\r
+    UINT32 PowerController : 1;\r
+    UINT32 ElectromechanicalInterlock : 1;\r
+    UINT32 DataLinkLayerStateChanged : 1;\r
+    UINT32 Reserved : 3;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_SLOT_CONTROL;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 AttentionButtonPressed : 1;\r
+    UINT16 PowerFaultDetected : 1;\r
+    UINT16 MrlSensorChanged : 1;\r
+    UINT16 PresenceDetectChanged : 1;\r
+    UINT16 CommandCompleted : 1;\r
+    UINT16 MrlSensor : 1;\r
+    UINT16 PresenceDetect : 1;\r
+    UINT16 ElectromechanicalInterlock : 1;\r
+    UINT16 DataLinkLayerStateChanged : 1;\r
+    UINT16 Reserved : 7;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_SLOT_STATUS;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 SystemErrorOnCorrectableError : 1;\r
+    UINT16 SystemErrorOnNonFatalError : 1;\r
+    UINT16 SystemErrorOnFatalError : 1;\r
+    UINT16 PmeInterrupt : 1;\r
+    UINT16 CrsSoftwareVisibility : 1;\r
+    UINT16 Reserved : 11;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_ROOT_CONTROL;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 CrsSoftwareVisibility : 1;\r
+    UINT16 Reserved : 15;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_ROOT_CAPABILITY;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 PmeRequesterId : 16;\r
+    UINT32 PmeStatus : 1;\r
+    UINT32 PmePending : 1;\r
+    UINT32 Reserved : 14;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_REG_PCIE_ROOT_STATUS;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 CompletionTimeoutRanges : 4;\r
+    UINT32 CompletionTimeoutDisable : 1;\r
+    UINT32 AriForwarding : 1;\r
+    UINT32 AtomicOpRouting : 1;\r
+    UINT32 AtomicOp32Completer : 1;\r
+    UINT32 AtomicOp64Completer : 1;\r
+    UINT32 Cas128Completer : 1;\r
+    UINT32 NoRoEnabledPrPrPassing : 1;\r
+    UINT32 LtrMechanism : 1;\r
+    UINT32 TphCompleter : 2;\r
+    UINT32 Reserved : 4;\r
+    UINT32 Obff : 2;\r
+    UINT32 ExtendedFmtField : 1;\r
+    UINT32 EndEndTlpPrefix : 1;\r
+    UINT32 MaxEndEndTlpPrefixes : 2;\r
+    UINT32 Reserved2 : 8;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_REG_PCIE_DEVICE_CAPABILITY2;\r
+\r
+#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
+#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE    BIT1\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 CompletionTimeoutValue : 4;\r
+    UINT16 CompletionTimeoutDisable : 1;\r
+    UINT16 AriForwarding : 1;\r
+    UINT16 AtomicOpRequester : 1;\r
+    UINT16 AtomicOpEgressBlocking : 1;\r
+    UINT16 IdoRequest : 1;\r
+    UINT16 IdoCompletion : 1;\r
+    UINT16 LtrMechanism : 2;\r
+    UINT16 Reserved : 2;\r
+    UINT16 Obff : 2;\r
+    UINT16 EndEndTlpPrefixBlocking : 1;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_DEVICE_CONTROL2;\r
+\r
+#define PCIE_COMPLETION_TIMEOUT_50US_50MS   0\r
+#define PCIE_COMPLETION_TIMEOUT_50US_100US  1\r
+#define PCIE_COMPLETION_TIMEOUT_1MS_10MS    2\r
+#define PCIE_COMPLETION_TIMEOUT_16MS_55MS   5\r
+#define PCIE_COMPLETION_TIMEOUT_65MS_210MS  6\r
+#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\r
+#define PCIE_COMPLETION_TIMEOUT_1S_3_5S     10\r
+#define PCIE_COMPLETION_TIMEOUT_4S_13S      13\r
+#define PCIE_COMPLETION_TIMEOUT_17S_64S     14\r
+\r
+#define PCIE_DEVICE_CONTROL_OBFF_DISABLED  0\r
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\r
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\r
+#define PCIE_DEVICE_CONTROL_OBFF_WAKE      3\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 Reserved : 1;\r
+    UINT32 LinkSpeedsVector : 7;\r
+    UINT32 Crosslink : 1;\r
+    UINT32 Reserved2 : 23;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_REG_PCIE_LINK_CAPABILITY2;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 TargetLinkSpeed : 4;\r
+    UINT16 EnterCompliance : 1;\r
+    UINT16 HardwareAutonomousSpeedDisable : 1;\r
+    UINT16 SelectableDeemphasis : 1;\r
+    UINT16 TransmitMargin : 3;\r
+    UINT16 EnterModifiedCompliance : 1;\r
+    UINT16 ComplianceSos : 1;\r
+    UINT16 CompliancePresetDeemphasis : 4;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_LINK_CONTROL2;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 CurrentDeemphasisLevel : 1;\r
+    UINT16 EqualizationComplete : 1;\r
+    UINT16 EqualizationPhase1Successful : 1;\r
+    UINT16 EqualizationPhase2Successful : 1;\r
+    UINT16 EqualizationPhase3Successful : 1;\r
+    UINT16 LinkEqualizationRequest : 1;\r
+    UINT16 Reserved : 10;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_REG_PCIE_LINK_STATUS2;\r
+\r
+typedef struct {\r
+  EFI_PCI_CAPABILITY_HDR          Hdr;\r
+  PCI_REG_PCIE_CAPABILITY         Capability;\r
+  PCI_REG_PCIE_DEVICE_CAPABILITY  DeviceCapability;\r
+  PCI_REG_PCIE_DEVICE_CONTROL     DeviceControl;\r
+  PCI_REG_PCIE_DEVICE_STATUS      DeviceStatus;\r
+  PCI_REG_PCIE_LINK_CAPABILITY    LinkCapability;\r
+  PCI_REG_PCIE_LINK_CONTROL       LinkControl;\r
+  PCI_REG_PCIE_LINK_STATUS        LinkStatus;\r
+  PCI_REG_PCIE_SLOT_CAPABILITY    SlotCapability;\r
+  PCI_REG_PCIE_SLOT_CONTROL       SlotControl;\r
+  PCI_REG_PCIE_SLOT_STATUS        SlotStatus;\r
+  PCI_REG_PCIE_ROOT_CONTROL       RootControl;\r
+  PCI_REG_PCIE_ROOT_CAPABILITY    RootCapability;\r
+  PCI_REG_PCIE_ROOT_STATUS        RootStatus;\r
+  PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\r
+  PCI_REG_PCIE_DEVICE_CONTROL2    DeviceControl2;\r
+  UINT16                          DeviceStatus2;\r
+  PCI_REG_PCIE_LINK_CAPABILITY2   LinkCapability2;\r
+  PCI_REG_PCIE_LINK_CONTROL2      LinkControl2;\r
+  PCI_REG_PCIE_LINK_STATUS2       LinkStatus2;\r
+  UINT32                          SlotCapability2;\r
+  UINT16                          SlotControl2;\r
+  UINT16                          SlotStatus2;\r
+} PCI_CAPABILITY_PCIEXP;\r
+\r
 #define EFI_PCIE_CAPABILITY_BASE_OFFSET                             0x100\r
 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY          0x10\r
 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET            0x24\r
@@ -83,11 +414,37 @@ typedef struct {
 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r
 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r
 \r
+typedef union {\r
+  struct {\r
+    UINT32 Undefined : 1;\r
+    UINT32 Reserved : 3;\r
+    UINT32 DataLinkProtocolError : 1;\r
+    UINT32 SurpriseDownError : 1;\r
+    UINT32 Reserved2 : 6;\r
+    UINT32 PoisonedTlp : 1;\r
+    UINT32 FlowControlProtocolError : 1;\r
+    UINT32 CompletionTimeout : 1;\r
+    UINT32 CompleterAbort : 1;\r
+    UINT32 UnexpectedCompletion : 1;\r
+    UINT32 ReceiverOverflow : 1;\r
+    UINT32 MalformedTlp : 1;\r
+    UINT32 EcrcError : 1;\r
+    UINT32 UnsupportedRequestError : 1;\r
+    UINT32 AcsVoilation : 1;\r
+    UINT32 UncorrectableInternalError : 1;\r
+    UINT32 McBlockedTlp : 1;\r
+    UINT32 AtomicOpEgressBlocked : 1;\r
+    UINT32 TlpPrefixBlockedError : 1;\r
+    UINT32 Reserved3 : 6;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;\r
+\r
 typedef struct {\r
   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;\r
-  UINT32                                    UncorrectableErrorStatus;\r
-  UINT32                                    UncorrectableErrorMask;\r
-  UINT32                                    UncorrectableErrorSeverity;\r
+  PCI_EXPRESS_REG_UNCORRECTABLE_ERROR       UncorrectableErrorStatus;\r
+  PCI_EXPRESS_REG_UNCORRECTABLE_ERROR       UncorrectableErrorMask;\r
+  PCI_EXPRESS_REG_UNCORRECTABLE_ERROR       UncorrectableErrorSeverity;\r
   UINT32                                    CorrectableErrorStatus;\r
   UINT32                                    CorrectableErrorMask;\r
   UINT32                                    AdvancedErrorCapabilitiesAndControl;\r
@@ -289,4 +646,6 @@ typedef struct {
 \r
 #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r
 \r
+#pragma pack()\r
+\r
 #endif\r

diff --git a/MdePkg/Include/IndustryStandard/PciExpress30.h b/MdePkg/Include/IndustryStandard/PciExpress30.h
index 6e9e105da912d29b201e29e2a4313fe3381c8927..db6a427bc8749e65d55ab4e9dc7cafafcb3e298f 100644 (file)
--- a/MdePkg/Include/IndustryStandard/PciExpress30.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress30.h
@@ -3,7 +3,7 @@
 \r
   This header file may not define all structures.  Please extend as required.\r
 \r
-  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
@@ -17,16 +17,41 @@
 #ifndef _PCIEXPRESS30_H_\r
 #define _PCIEXPRESS30_H_\r
 \r
-#include "PciExpress21.h"\r
+#include <IndustryStandard/PciExpress21.h>\r
+\r
+#pragma pack(1)\r
 \r
 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID    0x0019\r
 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1  0x1\r
 \r
+typedef union {\r
+  struct {\r
+    UINT32 PerformEqualization : 1;\r
+    UINT32 LinkEqualizationRequestInterruptEnable : 1;\r
+    UINT32 Reserved : 30;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_LINK_CONTROL3;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT16 DownstreamPortTransmitterPreset : 4;\r
+    UINT16 DownstreamPortReceiverPresetHint : 3;\r
+    UINT16 Reserved : 1;\r
+    UINT16 UpstreamPortTransmitterPreset : 4;\r
+    UINT16 UpstreamPortReceiverPresetHint : 3;\r
+    UINT16 Reserved2 : 1;\r
+  } Bits;\r
+  UINT16   Uint16;\r
+} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;\r
+\r
 typedef struct {\r
   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;\r
-  UINT32                                                  LinkControl3;\r
+  PCI_EXPRESS_REG_LINK_CONTROL3                           LinkControl3;\r
   UINT32                                                  LaneErrorStatus;\r
-  UINT16                                                  EqualizationControl[2];\r
+  PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL               EqualizationControl[2];\r
 } PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;\r
 \r
+#pragma pack()\r
+\r
 #endif\r

diff --git a/MdePkg/Include/IndustryStandard/PciExpress31.h b/MdePkg/Include/IndustryStandard/PciExpress31.h
new file mode 100644 (file)
index 0000000..62f5a60
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciExpress31.h
@@ -0,0 +1,78 @@
+/** @file\r
+Support for the PCI Express 3.1 standard.\r
+\r
+This header file may not define all structures.  Please extend as required.\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _PCIEXPRESS31_H_\r
+#define _PCIEXPRESS31_H_\r
+\r
+#include <IndustryStandard/PciExpress30.h>\r
+\r
+#pragma pack(1)\r
+\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID    0x001E\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1  0x1\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 PciPmL12 : 1;\r
+    UINT32 PciPmL11 : 1;\r
+    UINT32 AspmL12 : 1;\r
+    UINT32 AspmL11 : 1;\r
+    UINT32 L1PmSubstates : 1;\r
+    UINT32 Reserved : 3;\r
+    UINT32 CommonModeRestoreTime : 8;\r
+    UINT32 TPowerOnScale : 2;\r
+    UINT32 Reserved2 : 1;\r
+    UINT32 TPowerOnValue : 5;\r
+    UINT32 Reserved3 : 8;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 PciPmL12 : 1;\r
+    UINT32 PciPmL11 : 1;\r
+    UINT32 AspmL12 : 1;\r
+    UINT32 AspmL11 : 1;\r
+    UINT32 Reserved : 4;\r
+    UINT32 CommonModeRestoreTime : 8;\r
+    UINT32 LtrL12ThresholdValue : 10;\r
+    UINT32 Reserved2 : 3;\r
+    UINT32 LtrL12ThresholdScale : 3;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 TPowerOnScale : 2;\r
+    UINT32 Reserved : 1;\r
+    UINT32 TPowerOnValue : 5;\r
+    UINT32 Reserved2 : 24;\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;\r
+\r
+typedef struct {\r
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER   Header;\r
+  PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;\r
+  PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1   Control1;\r
+  PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2   Control2;\r
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;\r
+\r
+#pragma pack()\r
+\r
+#endif\r