OvmfPkg: consolidate POWER_MGMT_REGISTER_PIIX4() on "I440FxPiix4.h" macros

All POWER_MGMT_REGISTER_PIIX4() macro invocations in OvmfPkg should use
the macros in "I440FxPiix4.h" as arguments.

Cc: Gabriel Somlo <somlo@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17435 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index c20f29930420e2265cf6986f44865cd93cfc6a91..490cf803be74ba3dc63dfa203fb542347467e8e3 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -22,7 +22,6 @@
 // Power Management PCI Configuration Register fields\r
 //\r
 #define PMBA_RTE      BIT0\r
 // Power Management PCI Configuration Register fields\r
 //\r
 #define PMBA_RTE      BIT0\r

-#define PIIX4_PMIOSE  BIT0\r

 \r
 //\r
 // Offset in the Power Management Base Address to the ACPI Timer\r
 \r
 //\r
 // Offset in the Power Management Base Address to the ACPI Timer\r


@@ -58,9 +57,9 @@ AcpiTimerLibConstructor (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r

-      Pmba       = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
-      AcpiEnBit  = PIIX4_PMIOSE;\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r

       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index 55f3572eef2f619d3c96dc3a00348dbfe6927431..50a3391b756b5b25274bb14a0219eb8bd50c378e 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -23,7 +23,6 @@
 // Power Management PCI Configuration Register fields\r
 //\r
 #define PMBA_RTE      BIT0\r
 // Power Management PCI Configuration Register fields\r
 //\r
 #define PMBA_RTE      BIT0\r

-#define PIIX4_PMIOSE  BIT0\r

 \r
 //\r
 // Offset in the Power Management Base Address to the ACPI Timer\r
 \r
 //\r
 // Offset in the Power Management Base Address to the ACPI Timer\r


@@ -56,9 +55,9 @@ AcpiTimerLibConstructor (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r

-      Pmba       = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
-      AcpiEnBit  = PIIX4_PMIOSE;\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r

       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r


@@ -114,7 +113,7 @@ InternalAcpiGetTimerTick (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r

-      Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r

       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r

diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
index 649b5c9a4d72ff972abb318a6113095668290ae9..0c42ed2c5c707a835fec155d9cb368185d8133d4 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
@@ -61,7 +61,7 @@ AcpiTimerLibConstructor (
   HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
   HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r

-      Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r

       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r

diff --git a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
index 2521ea4e6ac3965cf20e62528d56f16ca9d5b132..1eb2a8b91e0b4923f08e5a1177c82626fca09ea4 100644 (file)
--- a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -860,7 +860,7 @@ PciAcpiInitialization (
   mHostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
   switch (mHostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
   mHostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
   switch (mHostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r

-      Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r

       //\r
       // 00:01.0 ISA Bridge (PIIX4) LNK routing targets\r
       //\r
       //\r
       // 00:01.0 ISA Bridge (PIIX4) LNK routing targets\r
       //\r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 4ce358ccbca6b9931396d88f2ba34fb31cd3907d..1126c6529ae2aeea4129379599b25bc39d474a95 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -252,9 +252,9 @@ MiscInitialization (
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r

-      Pmba       = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
-      AcpiEnBit  = BIT0; // PIIX4_PMIOSE\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r

       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r