# Define if the GICv3 controller should use the GICv2 legacy\r
gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
\r
+ # Whether to implement warm reboot for capsule update using a jump back to the\r
+ # PEI entry point with caches and interrupts disabled.\r
+ gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F\r
+\r
[PcdsFeatureFlag.ARM]\r
# Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
# TRUE may be appropriate to fix performance problems if you don't care about\r
\r
#include <PiDxe.h>\r
\r
+#include <Library/ArmMmuLib.h>\r
+#include <Library/ArmSmcLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/ResetSystemLib.h>\r
-#include <Library/ArmSmcLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeLib.h>\r
\r
#include <IndustryStandard/ArmStdSmc.h>\r
\r
VOID\r
)\r
{\r
- // Not implemented\r
+ VOID (*Reset)(VOID);\r
+\r
+ if (FeaturePcdGet (PcdArmReenterPeiForCapsuleWarmReboot) &&\r
+ !EfiAtRuntime ()) {\r
+ //\r
+ // At boot time, we are the only core running, so we can implement the\r
+ // immediate wake (which is used by capsule update) by disabling the MMU\r
+ // and interrupts, and jumping to the PEI entry point.\r
+ //\r
+ Reset = (VOID (*)(VOID))(UINTN)FixedPcdGet64 (PcdFvBaseAddress);\r
+\r
+ gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
+ ArmDisableMmu ();\r
+ Reset ();\r
+ }\r
}\r
\r
/**\r