UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr0" with PatchInstructionX86()

Like "gSmmCr4" in the previous patch, "gSmmCr0" is not only used for
machine code patching, but also as a means to communicate the initial CR0
value from SmmRelocateBases() to InitSmmS3ResumeState(). In other words,
the last four bytes of the "mov eax, Cr0Value" instruction's binary
representation are utilized as normal data too.

In order to get rid of the DB for "mov eax, Cr0Value", we have to split
both roles, patching and data flow. Introduce the "mSmmCr0" global (SMRAM)
variable for the data flow purpose. Rename the "gSmmCr0" variable to
"gPatchSmmCr0" so that its association with PatchInstructionX86() is clear
from the declaration, change its type to X86_ASSEMBLY_PATCH_LABEL, and
patch it with PatchInstructionX86(), to the value now contained in
"mSmmCr0".

This lets us remove the binary (DB) encoding of "mov eax, Cr0Value" in
"SmmInit.nasm".

Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index b4ed0a56a8146d1f287b8e59cdbba8549d99971e..0b8ef70359039375161cf61e151a9ae0635d1f31 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -744,7 +744,7 @@ InitSmmS3ResumeState (
       SmmS3ResumeState->SmmS3StackSize = 0;\r
     }\r
 \r
       SmmS3ResumeState->SmmS3StackSize = 0;\r
     }\r
 \r

-    SmmS3ResumeState->SmmS3Cr0 = gSmmCr0;\r
+    SmmS3ResumeState->SmmS3Cr0 = mSmmCr0;\r

     SmmS3ResumeState->SmmS3Cr3 = Cr3;\r
     SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;\r
 \r
     SmmS3ResumeState->SmmS3Cr3 = Cr3;\r
     SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;\r
 \r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index bd07a6e4f53696b6af96b3b818188e598e1540bc..0f62fe4487125c38532b6b7690cbee817d818b91 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -24,7 +24,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 \r
 global ASM_PFX(gPatchSmmCr3)\r
 global ASM_PFX(gPatchSmmCr4)\r
 \r
 global ASM_PFX(gPatchSmmCr3)\r
 global ASM_PFX(gPatchSmmCr4)\r

-global ASM_PFX(gSmmCr0)\r
+global ASM_PFX(gPatchSmmCr0)\r

 global ASM_PFX(gSmmJmpAddr)\r
 global ASM_PFX(gSmmInitStack)\r
 global ASM_PFX(gcSmiInitGdtr)\r
 global ASM_PFX(gSmmJmpAddr)\r
 global ASM_PFX(gSmmInitStack)\r
 global ASM_PFX(gcSmiInitGdtr)\r


@@ -60,8 +60,8 @@ ASM_PFX(gPatchSmmCr4):
     rdmsr\r
     or      eax, ebx                    ; set NXE bit if NX is available\r
     wrmsr\r
     rdmsr\r
     or      eax, ebx                    ; set NXE bit if NX is available\r
     wrmsr\r

-    DB      0x66, 0xb8                  ; mov eax, imm32\r
-ASM_PFX(gSmmCr0): DD 0\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr0):\r

     mov     di, PROTECT_MODE_DS\r
     mov     cr0, eax\r
     DB      0x66, 0xea                  ; jmp far [ptr48]\r
     mov     di, PROTECT_MODE_DS\r
     mov     cr0, eax\r
     DB      0x66, 0xea                  ; jmp far [ptr48]\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index a3fd796dba4a8d6a487f13138c133f22bda86dc6..f602d86d51a141252dc1651f0ea678b0a1606b22 100755 (executable)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -128,6 +128,7 @@ UINT8                    mPhysicalAddressBits;
 //\r
 // Control register contents saved for SMM S3 resume state initialization.\r
 //\r
 //\r
 // Control register contents saved for SMM S3 resume state initialization.\r
 //\r

+UINT32                   mSmmCr0;\r

 UINT32                   mSmmCr4;\r
 \r
 /**\r
 UINT32                   mSmmCr4;\r
 \r
 /**\r


@@ -410,7 +411,8 @@ SmmRelocateBases (
   //\r
   // Patch ASM code template with current CR0, CR3, and CR4 values\r
   //\r
   //\r
   // Patch ASM code template with current CR0, CR3, and CR4 values\r
   //\r

-  gSmmCr0 = (UINT32)AsmReadCr0 ();\r
+  mSmmCr0 = (UINT32)AsmReadCr0 ();\r
+  PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);\r

   PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
   mSmmCr4 = (UINT32)AsmReadCr4 ();\r
   PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r
   PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
   mSmmCr4 = (UINT32)AsmReadCr4 ();\r
   PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 8202ce6f86824350b60335daa1ba65e7e676e5d3..8344e0653a4800091c5c1869e3bdb7cab77e7305 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -308,7 +308,8 @@ extern IA32_FAR_ADDRESS             gSmmJmpAddr;
 \r
 extern CONST UINT8                  gcSmmInitTemplate[];\r
 extern CONST UINT16                 gcSmmInitSize;\r
 \r
 extern CONST UINT8                  gcSmmInitTemplate[];\r
 extern CONST UINT16                 gcSmmInitSize;\r

-extern UINT32                       gSmmCr0;\r
+X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr0;\r
+extern UINT32                       mSmmCr0;\r

 X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr3;\r
 extern UINT32                       mSmmCr4;\r
 X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr4;\r
 X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr3;\r
 extern UINT32                       mSmmCr4;\r
 X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr4;\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 971bd118132fc7c29ef8a83e46a84f825ef9a577..1a0667bd97bae95836b7f53cce06b3c9b9d54389 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -24,7 +24,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 \r
 global ASM_PFX(gPatchSmmCr3)\r
 global ASM_PFX(gPatchSmmCr4)\r
 \r
 global ASM_PFX(gPatchSmmCr3)\r
 global ASM_PFX(gPatchSmmCr4)\r

-global ASM_PFX(gSmmCr0)\r
+global ASM_PFX(gPatchSmmCr0)\r

 global ASM_PFX(gSmmJmpAddr)\r
 global ASM_PFX(gSmmInitStack)\r
 global ASM_PFX(gcSmiInitGdtr)\r
 global ASM_PFX(gSmmJmpAddr)\r
 global ASM_PFX(gSmmInitStack)\r
 global ASM_PFX(gcSmiInitGdtr)\r


@@ -63,8 +63,8 @@ ASM_PFX(gPatchSmmCr4):
     or      ah, BIT3                    ; set NXE bit\r
 .1:\r
     wrmsr\r
     or      ah, BIT3                    ; set NXE bit\r
 .1:\r
     wrmsr\r

-    DB      0x66, 0xb8                   ; mov eax, imm32\r
-ASM_PFX(gSmmCr0): DD 0\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr0):\r

     mov     cr0, eax                    ; enable protected mode & paging\r
     DB      0x66, 0xea                   ; far jmp to long mode\r
 ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode\r
     mov     cr0, eax                    ; enable protected mode & paging\r
     DB      0x66, 0xea                   ; far jmp to long mode\r
 ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode\r