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96aace8)
signed-off-by: erictian
reviewed-by: li-elvin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12725
6f19259b-4bc3-4df7-8a09-
765794883524
\r
case EfiUsbPortPower:\r
//\r
\r
case EfiUsbPortPower:\r
//\r
- // Not supported, ignore the operation\r
+ // Set port power bit when PPC is 1\r
- Status = EFI_SUCCESS;\r
+ if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {\r
+ State |= PORTSC_POWER;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ }\r
break;\r
\r
case EfiUsbPortOwner:\r
break;\r
\r
case EfiUsbPortOwner:\r
break;\r
\r
case EfiUsbPortPower:\r
break;\r
\r
case EfiUsbPortPower:\r
+ //\r
+ // Clear port power bit when PPC is 1\r
+ //\r
+ if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {\r
+ State &= ~PORTSC_POWER;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ }\r
+ break;\r
case EfiUsbPortSuspendChange:\r
case EfiUsbPortResetChange:\r
//\r
case EfiUsbPortSuspendChange:\r
case EfiUsbPortResetChange:\r
//\r
\r
The EHCI register operation routines.\r
\r
\r
The EHCI register operation routines.\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
)\r
{\r
EFI_STATUS Status;\r
)\r
{\r
EFI_STATUS Status;\r
\r
// This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.\r
// This ASSERT needs to be removed so the BeagleBoard will boot. When we fix\r
\r
// This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.\r
// This ASSERT needs to be removed so the BeagleBoard will boot. When we fix\r
EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);\r
\r
//\r
EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);\r
\r
//\r
- // 2. Program periodic frame list, already done in EhcInitSched\r
- // 3. Start the Host Controller\r
+ // 2. Start the Host Controller\r
//\r
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
\r
//\r
//\r
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
\r
//\r
- // 4. Set all ports routing to EHC\r
+ // 3. Power up all ports if EHCI has Port Power Control (PPC) support\r
- EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+ if (Ehc->HcStructParams & HCSP_PPC) {\r
+ for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {\r
+ EhcSetOpRegBit (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), PORTSC_POWER);\r
+ }\r
+ }\r
\r
//\r
// Wait roothub port power stable\r
//\r
gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);\r
\r
\r
//\r
// Wait roothub port power stable\r
//\r
gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);\r
\r
+ //\r
+ // 4. Set all ports routing to EHC\r
+ //\r
+ EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+\r
Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);\r
\r
if (EFI_ERROR (Status)) {\r
Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);\r
\r
if (EFI_ERROR (Status)) {\r
\r
This file contains the definination for host controller register operation routines.\r
\r
\r
This file contains the definination for host controller register operation routines.\r
\r
-Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Capability register bit definition\r
//\r
#define HCSP_NPORTS 0x0F // Number of root hub port\r
// Capability register bit definition\r
//\r
#define HCSP_NPORTS 0x0F // Number of root hub port\r
+#define HCSP_PPC 0x10 // Port Power Control\r
#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
\r
//\r
#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
\r
//\r