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CommitLineData
f25c0ae1
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1/*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10#include "qemu/osdep.h"
11#include "qapi/error.h"
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12#include "hw/misc/unimp.h"
13#include "hw/arm/aspeed_soc.h"
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14#include "qemu/module.h"
15#include "qemu/error-report.h"
16#include "hw/i2c/aspeed_i2c.h"
17#include "net/net.h"
18#include "sysemu/sysemu.h"
19
20#define ASPEED_SOC_IOMEM_SIZE 0x00200000
d9e9cd59 21#define ASPEED_SOC_DPMCU_SIZE 0x00040000
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22
23static const hwaddr aspeed_soc_ast2600_memmap[] = {
347df6f8 24 [ASPEED_DEV_SRAM] = 0x10000000,
d9e9cd59 25 [ASPEED_DEV_DPMCU] = 0x18000000,
f25c0ae1 26 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
347df6f8
EH
27 [ASPEED_DEV_IOMEM] = 0x1E600000,
28 [ASPEED_DEV_PWM] = 0x1E610000,
29 [ASPEED_DEV_FMC] = 0x1E620000,
30 [ASPEED_DEV_SPI1] = 0x1E630000,
08048cbd 31 [ASPEED_DEV_SPI2] = 0x1E631000,
347df6f8
EH
32 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
33 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
34 [ASPEED_DEV_MII1] = 0x1E650000,
35 [ASPEED_DEV_MII2] = 0x1E650008,
36 [ASPEED_DEV_MII3] = 0x1E650010,
37 [ASPEED_DEV_MII4] = 0x1E650018,
38 [ASPEED_DEV_ETH1] = 0x1E660000,
39 [ASPEED_DEV_ETH3] = 0x1E670000,
40 [ASPEED_DEV_ETH2] = 0x1E680000,
41 [ASPEED_DEV_ETH4] = 0x1E690000,
42 [ASPEED_DEV_VIC] = 0x1E6C0000,
a3888d75 43 [ASPEED_DEV_HACE] = 0x1E6D0000,
347df6f8
EH
44 [ASPEED_DEV_SDMC] = 0x1E6E0000,
45 [ASPEED_DEV_SCU] = 0x1E6E2000,
46 [ASPEED_DEV_XDMA] = 0x1E6E7000,
47 [ASPEED_DEV_ADC] = 0x1E6E9000,
d9e9cd59 48 [ASPEED_DEV_DP] = 0x1E6EB000,
e1acf581 49 [ASPEED_DEV_SBC] = 0x1E6F2000,
fe31a2ec 50 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000,
347df6f8
EH
51 [ASPEED_DEV_VIDEO] = 0x1E700000,
52 [ASPEED_DEV_SDHCI] = 0x1E740000,
53 [ASPEED_DEV_EMMC] = 0x1E750000,
54 [ASPEED_DEV_GPIO] = 0x1E780000,
55 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
56 [ASPEED_DEV_RTC] = 0x1E781000,
57 [ASPEED_DEV_TIMER1] = 0x1E782000,
58 [ASPEED_DEV_WDT] = 0x1E785000,
59 [ASPEED_DEV_LPC] = 0x1E789000,
60 [ASPEED_DEV_IBT] = 0x1E789140,
61 [ASPEED_DEV_I2C] = 0x1E78A000,
55c57023 62 [ASPEED_DEV_PECI] = 0x1E78B000,
347df6f8 63 [ASPEED_DEV_UART1] = 0x1E783000,
ab5e8605
PD
64 [ASPEED_DEV_UART2] = 0x1E78D000,
65 [ASPEED_DEV_UART3] = 0x1E78E000,
66 [ASPEED_DEV_UART4] = 0x1E78F000,
347df6f8 67 [ASPEED_DEV_UART5] = 0x1E784000,
ab5e8605
PD
68 [ASPEED_DEV_UART6] = 0x1E790000,
69 [ASPEED_DEV_UART7] = 0x1E790100,
70 [ASPEED_DEV_UART8] = 0x1E790200,
71 [ASPEED_DEV_UART9] = 0x1E790300,
72 [ASPEED_DEV_UART10] = 0x1E790400,
73 [ASPEED_DEV_UART11] = 0x1E790500,
74 [ASPEED_DEV_UART12] = 0x1E790600,
75 [ASPEED_DEV_UART13] = 0x1E790700,
347df6f8 76 [ASPEED_DEV_VUART] = 0x1E787000,
3222165d 77 [ASPEED_DEV_I3C] = 0x1E7A0000,
347df6f8 78 [ASPEED_DEV_SDRAM] = 0x80000000,
f25c0ae1
CLG
79};
80
81#define ASPEED_A7MPCORE_ADDR 0x40460000
82
b151de69 83#define AST2600_MAX_IRQ 197
f25c0ae1 84
a29e3e12 85/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
f25c0ae1 86static const int aspeed_soc_ast2600_irqmap[] = {
347df6f8
EH
87 [ASPEED_DEV_UART1] = 47,
88 [ASPEED_DEV_UART2] = 48,
89 [ASPEED_DEV_UART3] = 49,
90 [ASPEED_DEV_UART4] = 50,
91 [ASPEED_DEV_UART5] = 8,
ab5e8605
PD
92 [ASPEED_DEV_UART6] = 57,
93 [ASPEED_DEV_UART7] = 58,
94 [ASPEED_DEV_UART8] = 59,
95 [ASPEED_DEV_UART9] = 60,
96 [ASPEED_DEV_UART10] = 61,
97 [ASPEED_DEV_UART11] = 62,
98 [ASPEED_DEV_UART12] = 63,
99 [ASPEED_DEV_UART13] = 64,
347df6f8
EH
100 [ASPEED_DEV_VUART] = 8,
101 [ASPEED_DEV_FMC] = 39,
102 [ASPEED_DEV_SDMC] = 0,
103 [ASPEED_DEV_SCU] = 12,
104 [ASPEED_DEV_ADC] = 78,
105 [ASPEED_DEV_XDMA] = 6,
106 [ASPEED_DEV_SDHCI] = 43,
107 [ASPEED_DEV_EHCI1] = 5,
108 [ASPEED_DEV_EHCI2] = 9,
109 [ASPEED_DEV_EMMC] = 15,
110 [ASPEED_DEV_GPIO] = 40,
111 [ASPEED_DEV_GPIO_1_8V] = 11,
112 [ASPEED_DEV_RTC] = 13,
113 [ASPEED_DEV_TIMER1] = 16,
114 [ASPEED_DEV_TIMER2] = 17,
115 [ASPEED_DEV_TIMER3] = 18,
116 [ASPEED_DEV_TIMER4] = 19,
117 [ASPEED_DEV_TIMER5] = 20,
118 [ASPEED_DEV_TIMER6] = 21,
119 [ASPEED_DEV_TIMER7] = 22,
120 [ASPEED_DEV_TIMER8] = 23,
121 [ASPEED_DEV_WDT] = 24,
122 [ASPEED_DEV_PWM] = 44,
123 [ASPEED_DEV_LPC] = 35,
6820588e 124 [ASPEED_DEV_IBT] = 143,
347df6f8 125 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
55c57023 126 [ASPEED_DEV_PECI] = 38,
347df6f8
EH
127 [ASPEED_DEV_ETH1] = 2,
128 [ASPEED_DEV_ETH2] = 3,
a3888d75 129 [ASPEED_DEV_HACE] = 4,
347df6f8
EH
130 [ASPEED_DEV_ETH3] = 32,
131 [ASPEED_DEV_ETH4] = 33,
c59f781e 132 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
d9e9cd59 133 [ASPEED_DEV_DP] = 62,
3222165d 134 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */
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135};
136
699db715 137static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
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138{
139 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
140
699db715 141 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
f25c0ae1
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142}
143
144static void aspeed_soc_ast2600_init(Object *obj)
145{
146 AspeedSoCState *s = ASPEED_SOC(obj);
147 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
148 int i;
149 char socname[8];
150 char typename[64];
151
152 if (sscanf(sc->name, "%7s", socname) != 1) {
153 g_assert_not_reached();
154 }
155
156 for (i = 0; i < sc->num_cpus; i++) {
9fc7fc4d 157 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
f25c0ae1
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158 }
159
160 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
db873cc5 161 object_initialize_child(obj, "scu", &s->scu, typename);
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162 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
163 sc->silicon_rev);
164 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
d2623129 165 "hw-strap1");
f25c0ae1 166 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
d2623129 167 "hw-strap2");
f25c0ae1 168 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
d2623129 169 "hw-prot-key");
f25c0ae1 170
db873cc5
MA
171 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
172 TYPE_A15MPCORE_PRIV);
f25c0ae1 173
db873cc5 174 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
f25c0ae1
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175
176 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
db873cc5 177 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
f25c0ae1 178
199fd623
AJ
179 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
180 object_initialize_child(obj, "adc", &s->adc, typename);
181
f25c0ae1 182 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
db873cc5 183 object_initialize_child(obj, "i2c", &s->i2c, typename);
f25c0ae1 184
55c57023
PD
185 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
186
f25c0ae1 187 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
db873cc5 188 object_initialize_child(obj, "fmc", &s->fmc, typename);
f25c0ae1
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189
190 for (i = 0; i < sc->spis_num; i++) {
191 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
db873cc5 192 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
f25c0ae1
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193 }
194
917940ce 195 for (i = 0; i < sc->ehcis_num; i++) {
db873cc5
MA
196 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
197 TYPE_PLATFORM_EHCI);
917940ce
GR
198 }
199
f25c0ae1 200 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
db873cc5 201 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
f25c0ae1 202 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
d2623129 203 "ram-size");
f25c0ae1
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204
205 for (i = 0; i < sc->wdts_num; i++) {
206 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
db873cc5 207 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
f25c0ae1
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208 }
209
d300db02 210 for (i = 0; i < sc->macs_num; i++) {
db873cc5
MA
211 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
212 TYPE_FTGMAC100);
289251b0 213
db873cc5 214 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
f25c0ae1
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215 }
216
8efbee28
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217 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
218 object_initialize_child(obj, "xdma", &s->xdma, typename);
f25c0ae1
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219
220 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
db873cc5 221 object_initialize_child(obj, "gpio", &s->gpio, typename);
f25c0ae1
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222
223 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
db873cc5 224 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
f25c0ae1 225
db873cc5
MA
226 object_initialize_child(obj, "sd-controller", &s->sdhci,
227 TYPE_ASPEED_SDHCI);
f25c0ae1 228
5325cc34 229 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
0e2c24c6 230
f25c0ae1
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231 /* Init sd card slot class here so that they're under the correct parent */
232 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
7089e0cc
MA
233 object_initialize_child(obj, "sd-controller.sdhci[*]",
234 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
f25c0ae1 235 }
a29e3e12 236
db873cc5
MA
237 object_initialize_child(obj, "emmc-controller", &s->emmc,
238 TYPE_ASPEED_SDHCI);
a29e3e12 239
5325cc34 240 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
a29e3e12 241
7089e0cc
MA
242 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
243 TYPE_SYSBUS_SDHCI);
2ecf1726
CLG
244
245 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
a3888d75
JS
246
247 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
248 object_initialize_child(obj, "hace", &s->hace, typename);
3222165d
TL
249
250 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
e1acf581
JS
251
252 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
80beb085
PD
253
254 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
255 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
256 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE);
257 object_initialize_child(obj, "emmc-boot-controller",
258 &s->emmc_boot_controller,
259 TYPE_UNIMPLEMENTED_DEVICE);
f25c0ae1
CLG
260}
261
262/*
263 * ASPEED ast2600 has 0xf as cluster ID
264 *
932a8d1f 265 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
f25c0ae1
CLG
266 */
267static uint64_t aspeed_calc_affinity(int cpu)
268{
269 return (0xf << ARM_AFF1_SHIFT) | cpu;
270}
271
272static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
273{
274 int i;
275 AspeedSoCState *s = ASPEED_SOC(dev);
276 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
123327d1 277 Error *err = NULL;
f25c0ae1
CLG
278 qemu_irq irq;
279
280 /* IO space */
80beb085
PD
281 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
282 sc->memmap[ASPEED_DEV_IOMEM],
283 ASPEED_SOC_IOMEM_SIZE);
f25c0ae1 284
514bcf6f 285 /* Video engine stub */
80beb085
PD
286 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
287 sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
514bcf6f 288
fe31a2ec 289 /* eMMC Boot Controller stub */
80beb085
PD
290 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller),
291 "aspeed.emmc-boot-controller",
292 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000);
fe31a2ec 293
f25c0ae1 294 /* CPU */
b7f1a0cb 295 for (i = 0; i < sc->num_cpus; i++) {
b7f1a0cb 296 if (sc->num_cpus > 1) {
5325cc34
MA
297 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
298 ASPEED_A7MPCORE_ADDR, &error_abort);
f25c0ae1 299 }
5325cc34
MA
300 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
301 aspeed_calc_affinity(i), &error_abort);
f25c0ae1 302
5325cc34 303 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
058d0955 304 &error_abort);
e37976d7 305 object_property_set_link(OBJECT(&s->cpu[i]), "memory",
4dd9d554 306 OBJECT(s->memory), &error_abort);
058d0955 307
668f62ec 308 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
f25c0ae1
CLG
309 return;
310 }
311 }
312
313 /* A7MPCORE */
5325cc34 314 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
f25c0ae1 315 &error_abort);
5325cc34 316 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
957ad79f 317 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
5325cc34 318 &error_abort);
f25c0ae1 319
db873cc5 320 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
5bfcbda7 321 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
f25c0ae1 322
b7f1a0cb 323 for (i = 0; i < sc->num_cpus; i++) {
f25c0ae1 324 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
85f0e0c3 325 DeviceState *d = DEVICE(&s->cpu[i]);
f25c0ae1
CLG
326
327 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
328 sysbus_connect_irq(sbd, i, irq);
329 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
b7f1a0cb 330 sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
f25c0ae1 331 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
b7f1a0cb 332 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
f25c0ae1 333 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
b7f1a0cb 334 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
f25c0ae1
CLG
335 }
336
337 /* SRAM */
338 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
339 sc->sram_size, &err);
340 if (err) {
341 error_propagate(errp, err);
342 return;
343 }
4dd9d554 344 memory_region_add_subregion(s->memory,
347df6f8 345 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
f25c0ae1 346
d9e9cd59 347 /* DPMCU */
80beb085
PD
348 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu",
349 sc->memmap[ASPEED_DEV_DPMCU],
350 ASPEED_SOC_DPMCU_SIZE);
d9e9cd59 351
f25c0ae1 352 /* SCU */
668f62ec 353 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
f25c0ae1
CLG
354 return;
355 }
5bfcbda7 356 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
f25c0ae1
CLG
357
358 /* RTC */
668f62ec 359 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
f25c0ae1
CLG
360 return;
361 }
5bfcbda7 362 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
f25c0ae1 363 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
347df6f8 364 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
f25c0ae1
CLG
365
366 /* Timer */
5325cc34
MA
367 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
368 &error_abort);
668f62ec 369 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
f25c0ae1
CLG
370 return;
371 }
5bfcbda7 372 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
347df6f8 373 sc->memmap[ASPEED_DEV_TIMER1]);
f25c0ae1 374 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
347df6f8 375 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
f25c0ae1
CLG
376 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
377 }
378
199fd623
AJ
379 /* ADC */
380 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
381 return;
382 }
5bfcbda7 383 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
199fd623
AJ
384 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
385 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
386
470253b6
PD
387 /* UART */
388 aspeed_soc_uart_init(s);
f25c0ae1
CLG
389
390 /* I2C */
5325cc34 391 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
c24d9716 392 &error_abort);
668f62ec 393 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
f25c0ae1
CLG
394 return;
395 }
5bfcbda7 396 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
f25c0ae1
CLG
397 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
398 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
347df6f8 399 sc->irqmap[ASPEED_DEV_I2C] + i);
60261038
CLG
400 /* The AST2600 I2C controller has one IRQ per bus. */
401 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
f25c0ae1
CLG
402 }
403
55c57023
PD
404 /* PECI */
405 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
406 return;
407 }
408 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
409 sc->memmap[ASPEED_DEV_PECI]);
410 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
411 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
412
f25c0ae1 413 /* FMC, The number of CS is set at the board level */
5325cc34 414 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
c24d9716 415 &error_abort);
668f62ec 416 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
f25c0ae1
CLG
417 return;
418 }
5bfcbda7
PD
419 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
420 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
30b6852c 421 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
f25c0ae1 422 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
347df6f8 423 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
f25c0ae1
CLG
424
425 /* SPI */
426 for (i = 0; i < sc->spis_num; i++) {
5325cc34
MA
427 object_property_set_link(OBJECT(&s->spi[i]), "dram",
428 OBJECT(s->dram_mr), &error_abort);
668f62ec 429 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
f25c0ae1
CLG
430 return;
431 }
5bfcbda7 432 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
347df6f8 433 sc->memmap[ASPEED_DEV_SPI1 + i]);
5bfcbda7 434 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
30b6852c 435 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
f25c0ae1
CLG
436 }
437
917940ce
GR
438 /* EHCI */
439 for (i = 0; i < sc->ehcis_num; i++) {
668f62ec 440 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
917940ce
GR
441 return;
442 }
5bfcbda7 443 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
347df6f8 444 sc->memmap[ASPEED_DEV_EHCI1 + i]);
917940ce 445 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
347df6f8 446 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
917940ce
GR
447 }
448
f25c0ae1 449 /* SDMC - SDRAM Memory Controller */
668f62ec 450 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
f25c0ae1
CLG
451 return;
452 }
5bfcbda7
PD
453 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
454 sc->memmap[ASPEED_DEV_SDMC]);
f25c0ae1
CLG
455
456 /* Watch dog */
457 for (i = 0; i < sc->wdts_num; i++) {
458 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
459
5325cc34
MA
460 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
461 &error_abort);
668f62ec 462 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
f25c0ae1
CLG
463 return;
464 }
5bfcbda7 465 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
347df6f8 466 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
f25c0ae1
CLG
467 }
468
346160cb
CLG
469 /* RAM */
470 if (!aspeed_soc_dram_init(s, errp)) {
471 return;
472 }
473
f25c0ae1 474 /* Net */
d3bad7e7 475 for (i = 0; i < sc->macs_num; i++) {
5325cc34 476 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
2255f6b7 477 &error_abort);
668f62ec 478 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
123327d1 479 return;
f25c0ae1 480 }
5bfcbda7 481 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
347df6f8 482 sc->memmap[ASPEED_DEV_ETH1 + i]);
f25c0ae1 483 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
347df6f8 484 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
289251b0 485
5325cc34
MA
486 object_property_set_link(OBJECT(&s->mii[i]), "nic",
487 OBJECT(&s->ftgmac100[i]), &error_abort);
668f62ec 488 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
289251b0
CLG
489 return;
490 }
491
5bfcbda7 492 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
347df6f8 493 sc->memmap[ASPEED_DEV_MII1 + i]);
f25c0ae1
CLG
494 }
495
496 /* XDMA */
668f62ec 497 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
f25c0ae1
CLG
498 return;
499 }
5bfcbda7 500 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
347df6f8 501 sc->memmap[ASPEED_DEV_XDMA]);
f25c0ae1 502 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
347df6f8 503 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
f25c0ae1
CLG
504
505 /* GPIO */
668f62ec 506 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
f25c0ae1
CLG
507 return;
508 }
5bfcbda7 509 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
f25c0ae1 510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
347df6f8 511 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
f25c0ae1 512
668f62ec 513 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
f25c0ae1
CLG
514 return;
515 }
5bfcbda7 516 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
347df6f8 517 sc->memmap[ASPEED_DEV_GPIO_1_8V]);
f25c0ae1 518 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
347df6f8 519 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
f25c0ae1
CLG
520
521 /* SDHCI */
668f62ec 522 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
f25c0ae1
CLG
523 return;
524 }
5bfcbda7 525 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
347df6f8 526 sc->memmap[ASPEED_DEV_SDHCI]);
f25c0ae1 527 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
347df6f8 528 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
a29e3e12
AJ
529
530 /* eMMC */
668f62ec 531 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
a29e3e12
AJ
532 return;
533 }
5bfcbda7
PD
534 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
535 sc->memmap[ASPEED_DEV_EMMC]);
a29e3e12 536 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
347df6f8 537 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
2ecf1726
CLG
538
539 /* LPC */
540 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
541 return;
542 }
5bfcbda7 543 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
c59f781e
AJ
544
545 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
2ecf1726
CLG
546 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
547 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
c59f781e
AJ
548
549 /*
550 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
551 *
552 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters
553 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
554 * shared across the subdevices, and the shared IRQ output to the VIC is at
555 * offset 0.
556 */
557 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
558 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
559 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
560
561 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
562 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
563 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
564
565 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
566 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
567 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
568
569 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
570 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
571 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
a3888d75
JS
572
573 /* HACE */
574 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
575 &error_abort);
576 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
577 return;
578 }
5bfcbda7
PD
579 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
580 sc->memmap[ASPEED_DEV_HACE]);
a3888d75
JS
581 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
582 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
3222165d
TL
583
584 /* I3C */
585 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
586 return;
587 }
5bfcbda7 588 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
3222165d
TL
589 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
590 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
591 sc->irqmap[ASPEED_DEV_I3C] + i);
592 /* The AST2600 I3C controller has one IRQ per bus. */
593 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
594 }
e1acf581
JS
595
596 /* Secure Boot Controller */
597 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
598 return;
599 }
5bfcbda7 600 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
f25c0ae1
CLG
601}
602
603static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
604{
605 DeviceClass *dc = DEVICE_CLASS(oc);
606 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
607
608 dc->realize = aspeed_soc_ast2600_realize;
609
c5811bb3 610 sc->name = "ast2600-a3";
f25c0ae1 611 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
c5811bb3 612 sc->silicon_rev = AST2600_A3_SILICON_REV;
e01b4d5b 613 sc->sram_size = 0x16400;
f25c0ae1 614 sc->spis_num = 2;
917940ce 615 sc->ehcis_num = 2;
f25c0ae1 616 sc->wdts_num = 4;
d300db02 617 sc->macs_num = 4;
c5e1bdb9 618 sc->uarts_num = 13;
f25c0ae1
CLG
619 sc->irqmap = aspeed_soc_ast2600_irqmap;
620 sc->memmap = aspeed_soc_ast2600_memmap;
621 sc->num_cpus = 2;
699db715 622 sc->get_irq = aspeed_soc_ast2600_get_irq;
f25c0ae1
CLG
623}
624
625static const TypeInfo aspeed_soc_ast2600_type_info = {
c5811bb3 626 .name = "ast2600-a3",
f25c0ae1
CLG
627 .parent = TYPE_ASPEED_SOC,
628 .instance_size = sizeof(AspeedSoCState),
629 .instance_init = aspeed_soc_ast2600_init,
630 .class_init = aspeed_soc_ast2600_class_init,
631 .class_size = sizeof(AspeedSoCClass),
632};
633
634static void aspeed_soc_register_types(void)
635{
636 type_register_static(&aspeed_soc_ast2600_type_info);
637};
638
639type_init(aspeed_soc_register_types)