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CommitLineData
093bc2cd
AK
1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK
14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879 18#include "cpu.h"
022c62cb
PB
19#include "exec/memory.h"
20#include "exec/address-spaces.h"
409ddd01 21#include "qapi/visitor.h"
1de7afc9 22#include "qemu/bitops.h"
8c56c1a5 23#include "qemu/error-report.h"
db725815 24#include "qemu/main-loop.h"
b6b71cb5 25#include "qemu/qemu-print.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
54d31236 32#include "sysemu/runstate.h"
14a48c1d 33#include "sysemu/tcg.h"
8072aae3 34#include "sysemu/accel.h"
8072aae3 35#include "hw/boards.h"
b08199c6 36#include "migration/vmstate.h"
67d95c15 37
d197063f
PB
38//#define DEBUG_UNASSIGNED
39
22bde714
JK
40static unsigned memory_region_transaction_depth;
41static bool memory_region_update_pending;
4dc56152 42static bool ioeventfd_update_pending;
ae7a2bca 43bool global_dirty_log;
7664e80c 44
eae3eb3e 45static QTAILQ_HEAD(, MemoryListener) memory_listeners
72e22d2f 46 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 47
0d673e36
AK
48static QTAILQ_HEAD(, AddressSpace) address_spaces
49 = QTAILQ_HEAD_INITIALIZER(address_spaces);
50
967dc9b1
AK
51static GHashTable *flat_views;
52
093bc2cd
AK
53typedef struct AddrRange AddrRange;
54
8417cebf 55/*
c9cdaa3a 56 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK
57 * (large MemoryRegion::alias_offset).
58 */
093bc2cd 59struct AddrRange {
08dafab4
AK
60 Int128 start;
61 Int128 size;
093bc2cd
AK
62};
63
08dafab4 64static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK
65{
66 return (AddrRange) { start, size };
67}
68
69static bool addrrange_equal(AddrRange r1, AddrRange r2)
70{
08dafab4 71 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK
72}
73
08dafab4 74static Int128 addrrange_end(AddrRange r)
093bc2cd 75{
08dafab4 76 return int128_add(r.start, r.size);
093bc2cd
AK
77}
78
08dafab4 79static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 80{
08dafab4 81 int128_addto(&range.start, delta);
093bc2cd
AK
82 return range;
83}
84
08dafab4
AK
85static bool addrrange_contains(AddrRange range, Int128 addr)
86{
87 return int128_ge(addr, range.start)
88 && int128_lt(addr, addrrange_end(range));
89}
90
093bc2cd
AK
91static bool addrrange_intersects(AddrRange r1, AddrRange r2)
92{
08dafab4
AK
93 return addrrange_contains(r1, r2.start)
94 || addrrange_contains(r2, r1.start);
093bc2cd
AK
95}
96
97static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
98{
08dafab4
AK
99 Int128 start = int128_max(r1.start, r2.start);
100 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
101 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK
102}
103
0e0d36b4
AK
104enum ListenerDirection { Forward, Reverse };
105
7376e582 106#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK
107 do { \
108 MemoryListener *_listener; \
109 \
110 switch (_direction) { \
111 case Forward: \
112 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK
113 if (_listener->_callback) { \
114 _listener->_callback(_listener, ##_args); \
115 } \
0e0d36b4
AK
116 } \
117 break; \
118 case Reverse: \
eae3eb3e 119 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
975aefe0
AK
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
0e0d36b4
AK
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
9a54635d 130#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK
131 do { \
132 MemoryListener *_listener; \
133 \
134 switch (_direction) { \
135 case Forward: \
eae3eb3e 136 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
9a54635d 137 if (_listener->_callback) { \
7376e582
AK
138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
eae3eb3e 143 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
9a54635d 144 if (_listener->_callback) { \
7376e582
AK
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 156 do { \
16620684
AK
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
9a54635d 159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 160 } while(0)
0e0d36b4 161
093bc2cd
AK
162struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165};
166
3e9d69e7
AK
167struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
753d5e14 171 EventNotifier *e;
3e9d69e7
AK
172};
173
73bb753d
TB
174static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
3e9d69e7 176{
73bb753d 177 if (int128_lt(a->addr.start, b->addr.start)) {
3e9d69e7 178 return true;
73bb753d 179 } else if (int128_gt(a->addr.start, b->addr.start)) {
3e9d69e7 180 return false;
73bb753d 181 } else if (int128_lt(a->addr.size, b->addr.size)) {
3e9d69e7 182 return true;
73bb753d 183 } else if (int128_gt(a->addr.size, b->addr.size)) {
3e9d69e7 184 return false;
73bb753d 185 } else if (a->match_data < b->match_data) {
3e9d69e7 186 return true;
73bb753d 187 } else if (a->match_data > b->match_data) {
3e9d69e7 188 return false;
73bb753d
TB
189 } else if (a->match_data) {
190 if (a->data < b->data) {
3e9d69e7 191 return true;
73bb753d 192 } else if (a->data > b->data) {
3e9d69e7
AK
193 return false;
194 }
195 }
73bb753d 196 if (a->e < b->e) {
3e9d69e7 197 return true;
73bb753d 198 } else if (a->e > b->e) {
3e9d69e7
AK
199 return false;
200 }
201 return false;
202}
203
73bb753d
TB
204static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
3e9d69e7
AK
206{
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209}
210
093bc2cd
AK
211/* Range of memory in the global map. Addresses are absolute. */
212struct FlatRange {
213 MemoryRegion *mr;
a8170e5e 214 hwaddr offset_in_region;
093bc2cd 215 AddrRange addr;
5a583347 216 uint8_t dirty_log_mask;
b138e654 217 bool romd_mode;
fb1cd6f9 218 bool readonly;
c26763f8 219 bool nonvolatile;
093bc2cd
AK
220};
221
093bc2cd
AK
222#define FOR_EACH_FLAT_RANGE(var, view) \
223 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
224
9c1f8f44 225static inline MemoryRegionSection
16620684 226section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB
227{
228 return (MemoryRegionSection) {
229 .mr = fr->mr,
16620684 230 .fv = fv,
9c1f8f44
PB
231 .offset_within_region = fr->offset_in_region,
232 .size = fr->addr.size,
233 .offset_within_address_space = int128_get64(fr->addr.start),
234 .readonly = fr->readonly,
c26763f8 235 .nonvolatile = fr->nonvolatile,
9c1f8f44
PB
236 };
237}
238
093bc2cd
AK
239static bool flatrange_equal(FlatRange *a, FlatRange *b)
240{
241 return a->mr == b->mr
242 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 243 && a->offset_in_region == b->offset_in_region
b138e654 244 && a->romd_mode == b->romd_mode
c26763f8
MAL
245 && a->readonly == b->readonly
246 && a->nonvolatile == b->nonvolatile;
093bc2cd
AK
247}
248
89c177bb 249static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 250{
cc94cd6d
AK
251 FlatView *view;
252
253 view = g_new0(FlatView, 1);
856d7245 254 view->ref = 1;
89c177bb
AK
255 view->root = mr_root;
256 memory_region_ref(mr_root);
02d9651d 257 trace_flatview_new(view, mr_root);
cc94cd6d
AK
258
259 return view;
093bc2cd
AK
260}
261
262/* Insert a range into a given position. Caller is responsible for maintaining
263 * sorting order.
264 */
265static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
266{
267 if (view->nr == view->nr_allocated) {
268 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 269 view->ranges = g_realloc(view->ranges,
093bc2cd
AK
270 view->nr_allocated * sizeof(*view->ranges));
271 }
272 memmove(view->ranges + pos + 1, view->ranges + pos,
273 (view->nr - pos) * sizeof(FlatRange));
274 view->ranges[pos] = *range;
dfde4e6e 275 memory_region_ref(range->mr);
093bc2cd
AK
276 ++view->nr;
277}
278
279static void flatview_destroy(FlatView *view)
280{
dfde4e6e
PB
281 int i;
282
02d9651d 283 trace_flatview_destroy(view, view->root);
66a6df1d
AK
284 if (view->dispatch) {
285 address_space_dispatch_free(view->dispatch);
286 }
dfde4e6e
PB
287 for (i = 0; i < view->nr; i++) {
288 memory_region_unref(view->ranges[i].mr);
289 }
7267c094 290 g_free(view->ranges);
89c177bb 291 memory_region_unref(view->root);
a9a0c06d 292 g_free(view);
093bc2cd
AK
293}
294
447b0d0b 295static bool flatview_ref(FlatView *view)
856d7245 296{
447b0d0b 297 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
298}
299
48564041 300void flatview_unref(FlatView *view)
856d7245
PB
301{
302 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 303 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 304 assert(view->root);
66a6df1d 305 call_rcu(view, flatview_destroy, rcu);
856d7245
PB
306 }
307}
308
3d8e6bf9
AK
309static bool can_merge(FlatRange *r1, FlatRange *r2)
310{
08dafab4 311 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 312 && r1->mr == r2->mr
08dafab4
AK
313 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
314 r1->addr.size),
315 int128_make64(r2->offset_in_region))
d0a9b5bc 316 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 317 && r1->romd_mode == r2->romd_mode
c26763f8
MAL
318 && r1->readonly == r2->readonly
319 && r1->nonvolatile == r2->nonvolatile;
3d8e6bf9
AK
320}
321
8508e024 322/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
323static void flatview_simplify(FlatView *view)
324{
838ec117 325 unsigned i, j, k;
3d8e6bf9
AK
326
327 i = 0;
328 while (i < view->nr) {
329 j = i + 1;
330 while (j < view->nr
331 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 332 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK
333 ++j;
334 }
335 ++i;
838ec117
KW
336 for (k = i; k < j; k++) {
337 memory_region_unref(view->ranges[k].mr);
338 }
3d8e6bf9
AK
339 memmove(&view->ranges[i], &view->ranges[j],
340 (view->nr - j) * sizeof(view->ranges[j]));
341 view->nr -= j - i;
342 }
343}
344
e7342aa3
PB
345static bool memory_region_big_endian(MemoryRegion *mr)
346{
347#ifdef TARGET_WORDS_BIGENDIAN
348 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
349#else
350 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
351#endif
352}
353
9bf825bf 354static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
e11ef3d1 355{
9bf825bf
TN
356 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
357 switch (op & MO_SIZE) {
358 case MO_8:
e11ef3d1 359 break;
9bf825bf 360 case MO_16:
e11ef3d1
PB
361 *data = bswap16(*data);
362 break;
9bf825bf 363 case MO_32:
e11ef3d1
PB
364 *data = bswap32(*data);
365 break;
9bf825bf 366 case MO_64:
e11ef3d1
PB
367 *data = bswap64(*data);
368 break;
369 default:
9bf825bf 370 g_assert_not_reached();
e11ef3d1
PB
371 }
372 }
373}
374
3c754a93 375static inline void memory_region_shift_read_access(uint64_t *value,
98f52cdb 376 signed shift,
3c754a93
PMD
377 uint64_t mask,
378 uint64_t tmp)
379{
98f52cdb
PMD
380 if (shift >= 0) {
381 *value |= (tmp & mask) << shift;
382 } else {
383 *value |= (tmp & mask) >> -shift;
384 }
3c754a93
PMD
385}
386
387static inline uint64_t memory_region_shift_write_access(uint64_t *value,
98f52cdb 388 signed shift,
3c754a93
PMD
389 uint64_t mask)
390{
98f52cdb
PMD
391 uint64_t tmp;
392
393 if (shift >= 0) {
394 tmp = (*value >> shift) & mask;
395 } else {
396 tmp = (*value << -shift) & mask;
397 }
398
399 return tmp;
3c754a93
PMD
400}
401
4779dc1d
HB
402static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
403{
404 MemoryRegion *root;
405 hwaddr abs_addr = offset;
406
407 abs_addr += mr->addr;
408 for (root = mr; root->container; ) {
409 root = root->container;
410 abs_addr += root->addr;
411 }
412
413 return abs_addr;
414}
415
5a68be94
HB
416static int get_cpu_index(void)
417{
418 if (current_cpu) {
419 return current_cpu->cpu_index;
420 }
421 return -1;
422}
423
cc05c43a 424static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
425 hwaddr addr,
426 uint64_t *value,
427 unsigned size,
98f52cdb 428 signed shift,
cc05c43a
PM
429 uint64_t mask,
430 MemTxAttrs attrs)
ce5d2f33 431{
ce5d2f33
PB
432 uint64_t tmp;
433
cc05c43a 434 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 435 if (mr->subpage) {
5a68be94 436 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
380ea843 437 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
4779dc1d 438 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 439 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 440 }
3c754a93 441 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 442 return MEMTX_OK;
ce5d2f33
PB
443}
444
cc05c43a
PM
445static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
446 hwaddr addr,
447 uint64_t *value,
448 unsigned size,
98f52cdb 449 signed shift,
cc05c43a
PM
450 uint64_t mask,
451 MemTxAttrs attrs)
164a4dcd 452{
cc05c43a
PM
453 uint64_t tmp = 0;
454 MemTxResult r;
164a4dcd 455
cc05c43a 456 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 457 if (mr->subpage) {
5a68be94 458 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
380ea843 459 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
4779dc1d 460 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 461 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 462 }
3c754a93 463 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 464 return r;
164a4dcd
AK
465}
466
cc05c43a
PM
467static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
468 hwaddr addr,
469 uint64_t *value,
470 unsigned size,
98f52cdb 471 signed shift,
cc05c43a
PM
472 uint64_t mask,
473 MemTxAttrs attrs)
164a4dcd 474{
3c754a93 475 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
164a4dcd 476
23d92d68 477 if (mr->subpage) {
5a68be94 478 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
380ea843 479 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
4779dc1d 480 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 481 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 482 }
164a4dcd 483 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 484 return MEMTX_OK;
164a4dcd
AK
485}
486
cc05c43a
PM
487static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
488 hwaddr addr,
489 uint64_t *value,
490 unsigned size,
98f52cdb 491 signed shift,
cc05c43a
PM
492 uint64_t mask,
493 MemTxAttrs attrs)
494{
3c754a93 495 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
cc05c43a 496
23d92d68 497 if (mr->subpage) {
5a68be94 498 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
380ea843 499 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
4779dc1d 500 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 501 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 502 }
cc05c43a
PM
503 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
504}
505
506static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
507 uint64_t *value,
508 unsigned size,
509 unsigned access_size_min,
510 unsigned access_size_max,
05e015f7
KF
511 MemTxResult (*access_fn)
512 (MemoryRegion *mr,
513 hwaddr addr,
514 uint64_t *value,
515 unsigned size,
98f52cdb 516 signed shift,
05e015f7
KF
517 uint64_t mask,
518 MemTxAttrs attrs),
cc05c43a
PM
519 MemoryRegion *mr,
520 MemTxAttrs attrs)
164a4dcd
AK
521{
522 uint64_t access_mask;
523 unsigned access_size;
524 unsigned i;
cc05c43a 525 MemTxResult r = MEMTX_OK;
164a4dcd
AK
526
527 if (!access_size_min) {
528 access_size_min = 1;
529 }
530 if (!access_size_max) {
531 access_size_max = 4;
532 }
ce5d2f33
PB
533
534 /* FIXME: support unaligned access? */
164a4dcd 535 access_size = MAX(MIN(size, access_size_max), access_size_min);
36960b4d 536 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
e7342aa3
PB
537 if (memory_region_big_endian(mr)) {
538 for (i = 0; i < size; i += access_size) {
05e015f7 539 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 540 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
541 }
542 } else {
543 for (i = 0; i < size; i += access_size) {
05e015f7 544 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 545 access_mask, attrs);
e7342aa3 546 }
164a4dcd 547 }
cc05c43a 548 return r;
164a4dcd
AK
549}
550
e2177955
AK
551static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
552{
0d673e36
AK
553 AddressSpace *as;
554
feca4ac1
PB
555 while (mr->container) {
556 mr = mr->container;
e2177955 557 }
0d673e36
AK
558 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
559 if (mr == as->root) {
560 return as;
561 }
e2177955 562 }
eed2bacf 563 return NULL;
e2177955
AK
564}
565
093bc2cd
AK
566/* Render a memory region into the global view. Ranges in @view obscure
567 * ranges in @mr.
568 */
569static void render_memory_region(FlatView *view,
570 MemoryRegion *mr,
08dafab4 571 Int128 base,
fb1cd6f9 572 AddrRange clip,
c26763f8
MAL
573 bool readonly,
574 bool nonvolatile)
093bc2cd
AK
575{
576 MemoryRegion *subregion;
577 unsigned i;
a8170e5e 578 hwaddr offset_in_region;
08dafab4
AK
579 Int128 remain;
580 Int128 now;
093bc2cd
AK
581 FlatRange fr;
582 AddrRange tmp;
583
6bba19ba
AK
584 if (!mr->enabled) {
585 return;
586 }
587
08dafab4 588 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 589 readonly |= mr->readonly;
c26763f8 590 nonvolatile |= mr->nonvolatile;
093bc2cd
AK
591
592 tmp = addrrange_make(base, mr->size);
593
594 if (!addrrange_intersects(tmp, clip)) {
595 return;
596 }
597
598 clip = addrrange_intersection(tmp, clip);
599
600 if (mr->alias) {
08dafab4
AK
601 int128_subfrom(&base, int128_make64(mr->alias->addr));
602 int128_subfrom(&base, int128_make64(mr->alias_offset));
c26763f8
MAL
603 render_memory_region(view, mr->alias, base, clip,
604 readonly, nonvolatile);
093bc2cd
AK
605 return;
606 }
607
608 /* Render subregions in priority order. */
609 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
c26763f8
MAL
610 render_memory_region(view, subregion, base, clip,
611 readonly, nonvolatile);
093bc2cd
AK
612 }
613
14a3c10a 614 if (!mr->terminates) {
093bc2cd
AK
615 return;
616 }
617
08dafab4 618 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
619 base = clip.start;
620 remain = clip.size;
621
2eb74e1a 622 fr.mr = mr;
6f6a5ef3 623 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 624 fr.romd_mode = mr->romd_mode;
2eb74e1a 625 fr.readonly = readonly;
c26763f8 626 fr.nonvolatile = nonvolatile;
2eb74e1a 627
093bc2cd 628 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
629 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
630 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
631 continue;
632 }
08dafab4
AK
633 if (int128_lt(base, view->ranges[i].addr.start)) {
634 now = int128_min(remain,
635 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
636 fr.offset_in_region = offset_in_region;
637 fr.addr = addrrange_make(base, now);
638 flatview_insert(view, i, &fr);
639 ++i;
08dafab4
AK
640 int128_addto(&base, now);
641 offset_in_region += int128_get64(now);
642 int128_subfrom(&remain, now);
093bc2cd 643 }
d26a8cae
AK
644 now = int128_sub(int128_min(int128_add(base, remain),
645 addrrange_end(view->ranges[i].addr)),
646 base);
647 int128_addto(&base, now);
648 offset_in_region += int128_get64(now);
649 int128_subfrom(&remain, now);
093bc2cd 650 }
08dafab4 651 if (int128_nz(remain)) {
093bc2cd
AK
652 fr.offset_in_region = offset_in_region;
653 fr.addr = addrrange_make(base, remain);
654 flatview_insert(view, i, &fr);
655 }
656}
657
89c177bb
AK
658static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
659{
e673ba9a
PB
660 while (mr->enabled) {
661 if (mr->alias) {
662 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
663 /* The alias is included in its entirety. Use it as
664 * the "real" root, so that we can share more FlatViews.
665 */
666 mr = mr->alias;
667 continue;
668 }
669 } else if (!mr->terminates) {
670 unsigned int found = 0;
671 MemoryRegion *child, *next = NULL;
672 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
673 if (child->enabled) {
674 if (++found > 1) {
675 next = NULL;
676 break;
677 }
678 if (!child->addr && int128_ge(mr->size, child->size)) {
679 /* A child is included in its entirety. If it's the only
680 * enabled one, use it in the hope of finding an alias down the
681 * way. This will also let us share FlatViews.
682 */
683 next = child;
684 }
685 }
686 }
092aa2fc
AK
687 if (found == 0) {
688 return NULL;
689 }
e673ba9a
PB
690 if (next) {
691 mr = next;
692 continue;
693 }
694 }
695
092aa2fc 696 return mr;
89c177bb
AK
697 }
698
092aa2fc 699 return NULL;
89c177bb
AK
700}
701
093bc2cd 702/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 703static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 704{
9bf561e3 705 int i;
a9a0c06d 706 FlatView *view;
093bc2cd 707
89c177bb 708 view = flatview_new(mr);
093bc2cd 709
83f3c251 710 if (mr) {
a9a0c06d 711 render_memory_region(view, mr, int128_zero(),
c26763f8
MAL
712 addrrange_make(int128_zero(), int128_2_64()),
713 false, false);
83f3c251 714 }
a9a0c06d 715 flatview_simplify(view);
093bc2cd 716
9bf561e3
AK
717 view->dispatch = address_space_dispatch_new(view);
718 for (i = 0; i < view->nr; i++) {
719 MemoryRegionSection mrs =
720 section_from_flat_range(&view->ranges[i], view);
721 flatview_add_to_dispatch(view, &mrs);
722 }
723 address_space_dispatch_compact(view->dispatch);
967dc9b1 724 g_hash_table_replace(flat_views, mr, view);
9bf561e3 725
093bc2cd
AK
726 return view;
727}
728
3e9d69e7
AK
729static void address_space_add_del_ioeventfds(AddressSpace *as,
730 MemoryRegionIoeventfd *fds_new,
731 unsigned fds_new_nb,
732 MemoryRegionIoeventfd *fds_old,
733 unsigned fds_old_nb)
734{
735 unsigned iold, inew;
80a1ea37
AK
736 MemoryRegionIoeventfd *fd;
737 MemoryRegionSection section;
3e9d69e7
AK
738
739 /* Generate a symmetric difference of the old and new fd sets, adding
740 * and deleting as necessary.
741 */
742
743 iold = inew = 0;
744 while (iold < fds_old_nb || inew < fds_new_nb) {
745 if (iold < fds_old_nb
746 && (inew == fds_new_nb
73bb753d
TB
747 || memory_region_ioeventfd_before(&fds_old[iold],
748 &fds_new[inew]))) {
80a1ea37
AK
749 fd = &fds_old[iold];
750 section = (MemoryRegionSection) {
16620684 751 .fv = address_space_to_flatview(as),
80a1ea37 752 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 753 .size = fd->addr.size,
80a1ea37 754 };
9a54635d 755 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 756 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
757 ++iold;
758 } else if (inew < fds_new_nb
759 && (iold == fds_old_nb
73bb753d
TB
760 || memory_region_ioeventfd_before(&fds_new[inew],
761 &fds_old[iold]))) {
80a1ea37
AK
762 fd = &fds_new[inew];
763 section = (MemoryRegionSection) {
16620684 764 .fv = address_space_to_flatview(as),
80a1ea37 765 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 766 .size = fd->addr.size,
80a1ea37 767 };
9a54635d 768 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 769 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
770 ++inew;
771 } else {
772 ++iold;
773 ++inew;
774 }
775 }
776}
777
48564041 778FlatView *address_space_get_flatview(AddressSpace *as)
856d7245
PB
779{
780 FlatView *view;
781
694ea274 782 RCU_READ_LOCK_GUARD();
447b0d0b 783 do {
16620684 784 view = address_space_to_flatview(as);
447b0d0b
PB
785 /* If somebody has replaced as->current_map concurrently,
786 * flatview_ref returns false.
787 */
788 } while (!flatview_ref(view));
856d7245
PB
789 return view;
790}
791
3e9d69e7
AK
792static void address_space_update_ioeventfds(AddressSpace *as)
793{
99e86347 794 FlatView *view;
3e9d69e7
AK
795 FlatRange *fr;
796 unsigned ioeventfd_nb = 0;
920d557e
SH
797 unsigned ioeventfd_max;
798 MemoryRegionIoeventfd *ioeventfds;
3e9d69e7
AK
799 AddrRange tmp;
800 unsigned i;
801
920d557e
SH
802 /*
803 * It is likely that the number of ioeventfds hasn't changed much, so use
804 * the previous size as the starting value, with some headroom to avoid
805 * gratuitous reallocations.
806 */
807 ioeventfd_max = QEMU_ALIGN_UP(as->ioeventfd_nb, 4);
808 ioeventfds = g_new(MemoryRegionIoeventfd, ioeventfd_max);
809
856d7245 810 view = address_space_get_flatview(as);
99e86347 811 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
812 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
813 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
814 int128_sub(fr->addr.start,
815 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
816 if (addrrange_intersects(fr->addr, tmp)) {
817 ++ioeventfd_nb;
920d557e
SH
818 if (ioeventfd_nb > ioeventfd_max) {
819 ioeventfd_max = MAX(ioeventfd_max * 2, 4);
820 ioeventfds = g_realloc(ioeventfds,
821 ioeventfd_max * sizeof(*ioeventfds));
822 }
3e9d69e7
AK
823 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
824 ioeventfds[ioeventfd_nb-1].addr = tmp;
825 }
826 }
827 }
828
829 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
830 as->ioeventfds, as->ioeventfd_nb);
831
7267c094 832 g_free(as->ioeventfds);
3e9d69e7
AK
833 as->ioeventfds = ioeventfds;
834 as->ioeventfd_nb = ioeventfd_nb;
856d7245 835 flatview_unref(view);
3e9d69e7
AK
836}
837
23f1174a
PX
838/*
839 * Notify the memory listeners about the coalesced IO change events of
840 * range `cmr'. Only the part that has intersection of the specified
841 * FlatRange will be sent.
842 */
843static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
844 CoalescedMemoryRange *cmr, bool add)
845{
846 AddrRange tmp;
847
848 tmp = addrrange_shift(cmr->addr,
849 int128_sub(fr->addr.start,
850 int128_make64(fr->offset_in_region)));
851 if (!addrrange_intersects(tmp, fr->addr)) {
852 return;
853 }
854 tmp = addrrange_intersection(tmp, fr->addr);
855
856 if (add) {
857 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
858 int128_get64(tmp.start),
859 int128_get64(tmp.size));
860 } else {
861 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
862 int128_get64(tmp.start),
863 int128_get64(tmp.size));
864 }
865}
866
909bf763
PB
867static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
868{
23f1174a
PX
869 CoalescedMemoryRange *cmr;
870
23f1174a
PX
871 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
872 flat_range_coalesced_io_notify(fr, as, cmr, false);
873 }
909bf763
PB
874}
875
876static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
877{
878 MemoryRegion *mr = fr->mr;
879 CoalescedMemoryRange *cmr;
909bf763 880
1f7af804
PB
881 if (QTAILQ_EMPTY(&mr->coalesced)) {
882 return;
883 }
884
909bf763 885 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
23f1174a 886 flat_range_coalesced_io_notify(fr, as, cmr, true);
909bf763
PB
887 }
888}
889
b8af1afb 890static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
891 const FlatView *old_view,
892 const FlatView *new_view,
b8af1afb 893 bool adding)
093bc2cd 894{
093bc2cd
AK
895 unsigned iold, inew;
896 FlatRange *frold, *frnew;
093bc2cd
AK
897
898 /* Generate a symmetric difference of the old and new memory maps.
899 * Kill ranges in the old map, and instantiate ranges in the new map.
900 */
901 iold = inew = 0;
a9a0c06d
PB
902 while (iold < old_view->nr || inew < new_view->nr) {
903 if (iold < old_view->nr) {
904 frold = &old_view->ranges[iold];
093bc2cd
AK
905 } else {
906 frold = NULL;
907 }
a9a0c06d
PB
908 if (inew < new_view->nr) {
909 frnew = &new_view->ranges[inew];
093bc2cd
AK
910 } else {
911 frnew = NULL;
912 }
913
914 if (frold
915 && (!frnew
08dafab4
AK
916 || int128_lt(frold->addr.start, frnew->addr.start)
917 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 918 && !flatrange_equal(frold, frnew)))) {
41a6e477 919 /* In old but not in new, or in both but attributes changed. */
093bc2cd 920
b8af1afb 921 if (!adding) {
3ac7d43a 922 flat_range_coalesced_io_del(frold, as);
72e22d2f 923 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
924 }
925
093bc2cd
AK
926 ++iold;
927 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 928 /* In both and unchanged (except logging may have changed) */
093bc2cd 929
4f826024 930 if (adding) {
50c1e149 931 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
932 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
933 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
934 frold->dirty_log_mask,
935 frnew->dirty_log_mask);
936 }
937 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
938 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
939 frold->dirty_log_mask,
940 frnew->dirty_log_mask);
b8af1afb 941 }
5a583347
AK
942 }
943
093bc2cd
AK
944 ++iold;
945 ++inew;
093bc2cd
AK
946 } else {
947 /* In new */
948
b8af1afb 949 if (adding) {
72e22d2f 950 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
3ac7d43a 951 flat_range_coalesced_io_add(frnew, as);
b8af1afb
AK
952 }
953
093bc2cd
AK
954 ++inew;
955 }
956 }
b8af1afb
AK
957}
958
967dc9b1
AK
959static void flatviews_init(void)
960{
092aa2fc
AK
961 static FlatView *empty_view;
962
967dc9b1
AK
963 if (flat_views) {
964 return;
965 }
966
967 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
968 (GDestroyNotify) flatview_unref);
092aa2fc
AK
969 if (!empty_view) {
970 empty_view = generate_memory_topology(NULL);
971 /* We keep it alive forever in the global variable. */
972 flatview_ref(empty_view);
973 } else {
974 g_hash_table_replace(flat_views, NULL, empty_view);
975 flatview_ref(empty_view);
976 }
967dc9b1
AK
977}
978
979static void flatviews_reset(void)
980{
981 AddressSpace *as;
982
983 if (flat_views) {
984 g_hash_table_unref(flat_views);
985 flat_views = NULL;
986 }
987 flatviews_init();
988
989 /* Render unique FVs */
990 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
991 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
992
993 if (g_hash_table_lookup(flat_views, physmr)) {
994 continue;
995 }
996
997 generate_memory_topology(physmr);
998 }
999}
1000
1001static void address_space_set_flatview(AddressSpace *as)
b8af1afb 1002{
67ace39b 1003 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK
1004 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1005 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1006
1007 assert(new_view);
1008
67ace39b
AK
1009 if (old_view == new_view) {
1010 return;
1011 }
1012
1013 if (old_view) {
1014 flatview_ref(old_view);
1015 }
1016
967dc9b1 1017 flatview_ref(new_view);
9a62e24f
AK
1018
1019 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK
1020 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1021
1022 if (!old_view2) {
1023 old_view2 = &tmpview;
1024 }
1025 address_space_update_topology_pass(as, old_view2, new_view, false);
1026 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1027 }
b8af1afb 1028
374f2981
PB
1029 /* Writes are protected by the BQL. */
1030 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK
1031 if (old_view) {
1032 flatview_unref(old_view);
1033 }
856d7245
PB
1034
1035 /* Note that all the old MemoryRegions are still alive up to this
1036 * point. This relieves most MemoryListeners from the need to
1037 * ref/unref the MemoryRegions they get---unless they use them
1038 * outside the iothread mutex, in which case precise reference
1039 * counting is necessary.
1040 */
67ace39b
AK
1041 if (old_view) {
1042 flatview_unref(old_view);
1043 }
093bc2cd
AK
1044}
1045
202fc01b
AK
1046static void address_space_update_topology(AddressSpace *as)
1047{
1048 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1049
1050 flatviews_init();
1051 if (!g_hash_table_lookup(flat_views, physmr)) {
1052 generate_memory_topology(physmr);
1053 }
1054 address_space_set_flatview(as);
1055}
1056
4ef4db86
AK
1057void memory_region_transaction_begin(void)
1058{
bb880ded 1059 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
1060 ++memory_region_transaction_depth;
1061}
1062
1063void memory_region_transaction_commit(void)
1064{
0d673e36
AK
1065 AddressSpace *as;
1066
4ef4db86 1067 assert(memory_region_transaction_depth);
8d04fb55
JK
1068 assert(qemu_mutex_iothread_locked());
1069
4ef4db86 1070 --memory_region_transaction_depth;
4dc56152
GA
1071 if (!memory_region_transaction_depth) {
1072 if (memory_region_update_pending) {
967dc9b1
AK
1073 flatviews_reset();
1074
4dc56152 1075 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1076
4dc56152 1077 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1078 address_space_set_flatview(as);
02218487 1079 address_space_update_ioeventfds(as);
4dc56152 1080 }
ade9c1aa 1081 memory_region_update_pending = false;
0b152095 1082 ioeventfd_update_pending = false;
4dc56152
GA
1083 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1084 } else if (ioeventfd_update_pending) {
1085 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1086 address_space_update_ioeventfds(as);
1087 }
ade9c1aa 1088 ioeventfd_update_pending = false;
4dc56152 1089 }
4dc56152 1090 }
4ef4db86
AK
1091}
1092
545e92e0
AK
1093static void memory_region_destructor_none(MemoryRegion *mr)
1094{
1095}
1096
1097static void memory_region_destructor_ram(MemoryRegion *mr)
1098{
f1060c55 1099 qemu_ram_free(mr->ram_block);
545e92e0
AK
1100}
1101
b4fefef9
PC
1102static bool memory_region_need_escape(char c)
1103{
1104 return c == '/' || c == '[' || c == '\\' || c == ']';
1105}
1106
1107static char *memory_region_escape_name(const char *name)
1108{
1109 const char *p;
1110 char *escaped, *q;
1111 uint8_t c;
1112 size_t bytes = 0;
1113
1114 for (p = name; *p; p++) {
1115 bytes += memory_region_need_escape(*p) ? 4 : 1;
1116 }
1117 if (bytes == p - name) {
1118 return g_memdup(name, bytes + 1);
1119 }
1120
1121 escaped = g_malloc(bytes + 1);
1122 for (p = name, q = escaped; *p; p++) {
1123 c = *p;
1124 if (unlikely(memory_region_need_escape(c))) {
1125 *q++ = '\\';
1126 *q++ = 'x';
1127 *q++ = "0123456789abcdef"[c >> 4];
1128 c = "0123456789abcdef"[c & 15];
1129 }
1130 *q++ = c;
1131 }
1132 *q = 0;
1133 return escaped;
1134}
1135
3df9d748
AK
1136static void memory_region_do_init(MemoryRegion *mr,
1137 Object *owner,
1138 const char *name,
1139 uint64_t size)
093bc2cd 1140{
08dafab4
AK
1141 mr->size = int128_make64(size);
1142 if (size == UINT64_MAX) {
1143 mr->size = int128_2_64();
1144 }
302fa283 1145 mr->name = g_strdup(name);
612263cf 1146 mr->owner = owner;
58eaa217 1147 mr->ram_block = NULL;
b4fefef9
PC
1148
1149 if (name) {
843ef73a
PC
1150 char *escaped_name = memory_region_escape_name(name);
1151 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1152
1153 if (!owner) {
1154 owner = container_get(qdev_get_machine(), "/unattached");
1155 }
1156
d2623129 1157 object_property_add_child(owner, name_array, OBJECT(mr));
b4fefef9 1158 object_unref(OBJECT(mr));
843ef73a
PC
1159 g_free(name_array);
1160 g_free(escaped_name);
b4fefef9
PC
1161 }
1162}
1163
3df9d748
AK
1164void memory_region_init(MemoryRegion *mr,
1165 Object *owner,
1166 const char *name,
1167 uint64_t size)
1168{
1169 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1170 memory_region_do_init(mr, owner, name, size);
1171}
1172
d7bce999
EB
1173static void memory_region_get_container(Object *obj, Visitor *v,
1174 const char *name, void *opaque,
1175 Error **errp)
409ddd01
PC
1176{
1177 MemoryRegion *mr = MEMORY_REGION(obj);
ddfb0baa 1178 char *path = (char *)"";
409ddd01
PC
1179
1180 if (mr->container) {
1181 path = object_get_canonical_path(OBJECT(mr->container));
1182 }
51e72bc1 1183 visit_type_str(v, name, &path, errp);
409ddd01
PC
1184 if (mr->container) {
1185 g_free(path);
1186 }
1187}
1188
1189static Object *memory_region_resolve_container(Object *obj, void *opaque,
1190 const char *part)
1191{
1192 MemoryRegion *mr = MEMORY_REGION(obj);
1193
1194 return OBJECT(mr->container);
1195}
1196
d7bce999
EB
1197static void memory_region_get_priority(Object *obj, Visitor *v,
1198 const char *name, void *opaque,
1199 Error **errp)
d33382da
PC
1200{
1201 MemoryRegion *mr = MEMORY_REGION(obj);
1202 int32_t value = mr->priority;
1203
51e72bc1 1204 visit_type_int32(v, name, &value, errp);
d33382da
PC
1205}
1206
d7bce999
EB
1207static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1208 void *opaque, Error **errp)
52aef7bb
PC
1209{
1210 MemoryRegion *mr = MEMORY_REGION(obj);
1211 uint64_t value = memory_region_size(mr);
1212
51e72bc1 1213 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1214}
1215
b4fefef9
PC
1216static void memory_region_initfn(Object *obj)
1217{
1218 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1219 ObjectProperty *op;
b4fefef9
PC
1220
1221 mr->ops = &unassigned_mem_ops;
6bba19ba 1222 mr->enabled = true;
5f9a5ea1 1223 mr->romd_mode = true;
196ea131 1224 mr->global_locking = true;
545e92e0 1225 mr->destructor = memory_region_destructor_none;
093bc2cd 1226 QTAILQ_INIT(&mr->subregions);
093bc2cd 1227 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1228
1229 op = object_property_add(OBJECT(mr), "container",
1230 "link<" TYPE_MEMORY_REGION ">",
1231 memory_region_get_container,
1232 NULL, /* memory_region_set_container */
d2623129 1233 NULL, NULL);
409ddd01
PC
1234 op->resolve = memory_region_resolve_container;
1235
64a7b8de 1236 object_property_add_uint64_ptr(OBJECT(mr), "addr",
d2623129 1237 &mr->addr, OBJ_PROP_FLAG_READ);
d33382da
PC
1238 object_property_add(OBJECT(mr), "priority", "uint32",
1239 memory_region_get_priority,
1240 NULL, /* memory_region_set_priority */
d2623129 1241 NULL, NULL);
52aef7bb
PC
1242 object_property_add(OBJECT(mr), "size", "uint64",
1243 memory_region_get_size,
1244 NULL, /* memory_region_set_size, */
d2623129 1245 NULL, NULL);
093bc2cd
AK
1246}
1247
3df9d748
AK
1248static void iommu_memory_region_initfn(Object *obj)
1249{
1250 MemoryRegion *mr = MEMORY_REGION(obj);
1251
1252 mr->is_iommu = true;
1253}
1254
b018ddf6
PB
1255static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1256 unsigned size)
1257{
1258#ifdef DEBUG_UNASSIGNED
1259 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1260#endif
68a7439a 1261 return 0;
b018ddf6
PB
1262}
1263
1264static void unassigned_mem_write(void *opaque, hwaddr addr,
1265 uint64_t val, unsigned size)
1266{
1267#ifdef DEBUG_UNASSIGNED
1268 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1269#endif
b018ddf6
PB
1270}
1271
d197063f 1272static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
8372d383
PM
1273 unsigned size, bool is_write,
1274 MemTxAttrs attrs)
d197063f
PB
1275{
1276 return false;
1277}
1278
1279const MemoryRegionOps unassigned_mem_ops = {
1280 .valid.accepts = unassigned_mem_accepts,
1281 .endianness = DEVICE_NATIVE_ENDIAN,
1282};
1283
4a2e242b
AW
1284static uint64_t memory_region_ram_device_read(void *opaque,
1285 hwaddr addr, unsigned size)
1286{
1287 MemoryRegion *mr = opaque;
1288 uint64_t data = (uint64_t)~0;
1289
1290 switch (size) {
1291 case 1:
1292 data = *(uint8_t *)(mr->ram_block->host + addr);
1293 break;
1294 case 2:
1295 data = *(uint16_t *)(mr->ram_block->host + addr);
1296 break;
1297 case 4:
1298 data = *(uint32_t *)(mr->ram_block->host + addr);
1299 break;
1300 case 8:
1301 data = *(uint64_t *)(mr->ram_block->host + addr);
1302 break;
1303 }
1304
1305 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1306
1307 return data;
1308}
1309
1310static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1311 uint64_t data, unsigned size)
1312{
1313 MemoryRegion *mr = opaque;
1314
1315 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1316
1317 switch (size) {
1318 case 1:
1319 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1320 break;
1321 case 2:
1322 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1323 break;
1324 case 4:
1325 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1326 break;
1327 case 8:
1328 *(uint64_t *)(mr->ram_block->host + addr) = data;
1329 break;
1330 }
1331}
1332
1333static const MemoryRegionOps ram_device_mem_ops = {
1334 .read = memory_region_ram_device_read,
1335 .write = memory_region_ram_device_write,
c99a29e7 1336 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1337 .valid = {
1338 .min_access_size = 1,
1339 .max_access_size = 8,
1340 .unaligned = true,
1341 },
1342 .impl = {
1343 .min_access_size = 1,
1344 .max_access_size = 8,
1345 .unaligned = true,
1346 },
1347};
1348
d2702032
PB
1349bool memory_region_access_valid(MemoryRegion *mr,
1350 hwaddr addr,
1351 unsigned size,
6d7b9a6c
PM
1352 bool is_write,
1353 MemTxAttrs attrs)
093bc2cd 1354{
a014ed07
PB
1355 int access_size_min, access_size_max;
1356 int access_size, i;
897fa7cf 1357
093bc2cd
AK
1358 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1359 return false;
1360 }
1361
a014ed07 1362 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1363 return true;
1364 }
1365
a014ed07
PB
1366 access_size_min = mr->ops->valid.min_access_size;
1367 if (!mr->ops->valid.min_access_size) {
1368 access_size_min = 1;
1369 }
1370
1371 access_size_max = mr->ops->valid.max_access_size;
1372 if (!mr->ops->valid.max_access_size) {
1373 access_size_max = 4;
1374 }
1375
1376 access_size = MAX(MIN(size, access_size_max), access_size_min);
1377 for (i = 0; i < size; i += access_size) {
1378 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
8372d383 1379 is_write, attrs)) {
a014ed07
PB
1380 return false;
1381 }
093bc2cd 1382 }
a014ed07 1383
093bc2cd
AK
1384 return true;
1385}
1386
cc05c43a
PM
1387static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1388 hwaddr addr,
1389 uint64_t *pval,
1390 unsigned size,
1391 MemTxAttrs attrs)
093bc2cd 1392{
cc05c43a 1393 *pval = 0;
093bc2cd 1394
ce5d2f33 1395 if (mr->ops->read) {
cc05c43a
PM
1396 return access_with_adjusted_size(addr, pval, size,
1397 mr->ops->impl.min_access_size,
1398 mr->ops->impl.max_access_size,
1399 memory_region_read_accessor,
1400 mr, attrs);
62a0db94 1401 } else {
cc05c43a
PM
1402 return access_with_adjusted_size(addr, pval, size,
1403 mr->ops->impl.min_access_size,
1404 mr->ops->impl.max_access_size,
1405 memory_region_read_with_attrs_accessor,
1406 mr, attrs);
74901c3b 1407 }
093bc2cd
AK
1408}
1409
3b643495
PM
1410MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1411 hwaddr addr,
1412 uint64_t *pval,
e67c9046 1413 MemOp op,
3b643495 1414 MemTxAttrs attrs)
a621f38d 1415{
e67c9046 1416 unsigned size = memop_size(op);
cc05c43a
PM
1417 MemTxResult r;
1418
6d7b9a6c 1419 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
791af8c8 1420 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1421 return MEMTX_DECODE_ERROR;
791af8c8 1422 }
a621f38d 1423
cc05c43a 1424 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
9bf825bf 1425 adjust_endianness(mr, pval, op);
cc05c43a 1426 return r;
a621f38d 1427}
093bc2cd 1428
8c56c1a5
PF
1429/* Return true if an eventfd was signalled */
1430static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1431 hwaddr addr,
1432 uint64_t data,
1433 unsigned size,
1434 MemTxAttrs attrs)
1435{
1436 MemoryRegionIoeventfd ioeventfd = {
1437 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1438 .data = data,
1439 };
1440 unsigned i;
1441
1442 for (i = 0; i < mr->ioeventfd_nb; i++) {
1443 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1444 ioeventfd.e = mr->ioeventfds[i].e;
1445
73bb753d 1446 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
8c56c1a5
PF
1447 event_notifier_set(ioeventfd.e);
1448 return true;
1449 }
1450 }
1451
1452 return false;
1453}
1454
3b643495
PM
1455MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1456 hwaddr addr,
1457 uint64_t data,
e67c9046 1458 MemOp op,
3b643495 1459 MemTxAttrs attrs)
a621f38d 1460{
e67c9046
TN
1461 unsigned size = memop_size(op);
1462
6d7b9a6c 1463 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
b018ddf6 1464 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1465 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1466 }
1467
9bf825bf 1468 adjust_endianness(mr, &data, op);
a621f38d 1469
8c56c1a5
PF
1470 if ((!kvm_eventfds_enabled()) &&
1471 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1472 return MEMTX_OK;
1473 }
1474
ce5d2f33 1475 if (mr->ops->write) {
cc05c43a
PM
1476 return access_with_adjusted_size(addr, &data, size,
1477 mr->ops->impl.min_access_size,
1478 mr->ops->impl.max_access_size,
1479 memory_region_write_accessor, mr,
1480 attrs);
62a0db94 1481 } else {
cc05c43a
PM
1482 return
1483 access_with_adjusted_size(addr, &data, size,
1484 mr->ops->impl.min_access_size,
1485 mr->ops->impl.max_access_size,
1486 memory_region_write_with_attrs_accessor,
1487 mr, attrs);
74901c3b 1488 }
093bc2cd
AK
1489}
1490
093bc2cd 1491void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1492 Object *owner,
093bc2cd
AK
1493 const MemoryRegionOps *ops,
1494 void *opaque,
1495 const char *name,
1496 uint64_t size)
1497{
2c9b15ca 1498 memory_region_init(mr, owner, name, size);
6d6d2abf 1499 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1500 mr->opaque = opaque;
14a3c10a 1501 mr->terminates = true;
093bc2cd
AK
1502}
1503
1cfe48c1
PM
1504void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1505 Object *owner,
1506 const char *name,
1507 uint64_t size,
1508 Error **errp)
06329cce
MA
1509{
1510 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1511}
1512
1513void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1514 Object *owner,
1515 const char *name,
1516 uint64_t size,
1517 bool share,
1518 Error **errp)
093bc2cd 1519{
1cd3d492 1520 Error *err = NULL;
2c9b15ca 1521 memory_region_init(mr, owner, name, size);
8ea9252a 1522 mr->ram = true;
14a3c10a 1523 mr->terminates = true;
545e92e0 1524 mr->destructor = memory_region_destructor_ram;
1cd3d492 1525 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
677e7805 1526 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1527 if (err) {
1528 mr->size = int128_zero();
1529 object_unparent(OBJECT(mr));
1530 error_propagate(errp, err);
1531 }
0b183fc8
PB
1532}
1533
60786ef3
MT
1534void memory_region_init_resizeable_ram(MemoryRegion *mr,
1535 Object *owner,
1536 const char *name,
1537 uint64_t size,
1538 uint64_t max_size,
1539 void (*resized)(const char*,
1540 uint64_t length,
1541 void *host),
1542 Error **errp)
1543{
1cd3d492 1544 Error *err = NULL;
60786ef3
MT
1545 memory_region_init(mr, owner, name, size);
1546 mr->ram = true;
1547 mr->terminates = true;
1548 mr->destructor = memory_region_destructor_ram;
8e41fb63 1549 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1cd3d492 1550 mr, &err);
677e7805 1551 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1552 if (err) {
1553 mr->size = int128_zero();
1554 object_unparent(OBJECT(mr));
1555 error_propagate(errp, err);
1556 }
60786ef3
MT
1557}
1558
d5dbde46 1559#ifdef CONFIG_POSIX
0b183fc8
PB
1560void memory_region_init_ram_from_file(MemoryRegion *mr,
1561 struct Object *owner,
1562 const char *name,
1563 uint64_t size,
98376843 1564 uint64_t align,
cbfc0171 1565 uint32_t ram_flags,
7f56e740
PB
1566 const char *path,
1567 Error **errp)
0b183fc8 1568{
1cd3d492 1569 Error *err = NULL;
0b183fc8
PB
1570 memory_region_init(mr, owner, name, size);
1571 mr->ram = true;
1572 mr->terminates = true;
1573 mr->destructor = memory_region_destructor_ram;
98376843 1574 mr->align = align;
1cd3d492 1575 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
677e7805 1576 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1577 if (err) {
1578 mr->size = int128_zero();
1579 object_unparent(OBJECT(mr));
1580 error_propagate(errp, err);
1581 }
093bc2cd 1582}
fea617c5
MAL
1583
1584void memory_region_init_ram_from_fd(MemoryRegion *mr,
1585 struct Object *owner,
1586 const char *name,
1587 uint64_t size,
1588 bool share,
1589 int fd,
1590 Error **errp)
1591{
1cd3d492 1592 Error *err = NULL;
fea617c5
MAL
1593 memory_region_init(mr, owner, name, size);
1594 mr->ram = true;
1595 mr->terminates = true;
1596 mr->destructor = memory_region_destructor_ram;
cbfc0171
JH
1597 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1598 share ? RAM_SHARED : 0,
1cd3d492 1599 fd, &err);
fea617c5 1600 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1601 if (err) {
1602 mr->size = int128_zero();
1603 object_unparent(OBJECT(mr));
1604 error_propagate(errp, err);
1605 }
fea617c5 1606}
0b183fc8 1607#endif
093bc2cd
AK
1608
1609void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1610 Object *owner,
093bc2cd
AK
1611 const char *name,
1612 uint64_t size,
1613 void *ptr)
1614{
2c9b15ca 1615 memory_region_init(mr, owner, name, size);
8ea9252a 1616 mr->ram = true;
14a3c10a 1617 mr->terminates = true;
fc3e7665 1618 mr->destructor = memory_region_destructor_ram;
677e7805 1619 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1620
1621 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1622 assert(ptr != NULL);
8e41fb63 1623 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1624}
1625
21e00fa5
AW
1626void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1627 Object *owner,
1628 const char *name,
1629 uint64_t size,
1630 void *ptr)
e4dc3f59 1631{
2ddb89b0
BS
1632 memory_region_init(mr, owner, name, size);
1633 mr->ram = true;
1634 mr->terminates = true;
21e00fa5 1635 mr->ram_device = true;
4a2e242b
AW
1636 mr->ops = &ram_device_mem_ops;
1637 mr->opaque = mr;
2ddb89b0
BS
1638 mr->destructor = memory_region_destructor_ram;
1639 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1640 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1641 assert(ptr != NULL);
1642 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
e4dc3f59
ND
1643}
1644
093bc2cd 1645void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1646 Object *owner,
093bc2cd
AK
1647 const char *name,
1648 MemoryRegion *orig,
a8170e5e 1649 hwaddr offset,
093bc2cd
AK
1650 uint64_t size)
1651{
2c9b15ca 1652 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1653 mr->alias = orig;
1654 mr->alias_offset = offset;
1655}
1656
b59821a9
PM
1657void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1658 struct Object *owner,
1659 const char *name,
1660 uint64_t size,
1661 Error **errp)
a1777f7f 1662{
83696c8f 1663 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
a1777f7f 1664 mr->readonly = true;
a1777f7f
PM
1665}
1666
b59821a9
PM
1667void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1668 Object *owner,
1669 const MemoryRegionOps *ops,
1670 void *opaque,
1671 const char *name,
1672 uint64_t size,
1673 Error **errp)
d0a9b5bc 1674{
1cd3d492 1675 Error *err = NULL;
39e0b03d 1676 assert(ops);
2c9b15ca 1677 memory_region_init(mr, owner, name, size);
7bc2b9cd 1678 mr->ops = ops;
75f5941c 1679 mr->opaque = opaque;
d0a9b5bc 1680 mr->terminates = true;
75c578dc 1681 mr->rom_device = true;
58268c8d 1682 mr->destructor = memory_region_destructor_ram;
1cd3d492
IM
1683 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1684 if (err) {
1685 mr->size = int128_zero();
1686 object_unparent(OBJECT(mr));
1687 error_propagate(errp, err);
1688 }
d0a9b5bc
AK
1689}
1690
1221a474
AK
1691void memory_region_init_iommu(void *_iommu_mr,
1692 size_t instance_size,
1693 const char *mrtypename,
2c9b15ca 1694 Object *owner,
30951157
AK
1695 const char *name,
1696 uint64_t size)
1697{
1221a474 1698 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1699 struct MemoryRegion *mr;
1700
1221a474
AK
1701 object_initialize(_iommu_mr, instance_size, mrtypename);
1702 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1703 memory_region_do_init(mr, owner, name, size);
1704 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1705 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1706 QLIST_INIT(&iommu_mr->iommu_notify);
1707 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1708}
1709
b4fefef9 1710static void memory_region_finalize(Object *obj)
093bc2cd 1711{
b4fefef9
PC
1712 MemoryRegion *mr = MEMORY_REGION(obj);
1713
2e2b8eb7
PB
1714 assert(!mr->container);
1715
1716 /* We know the region is not visible in any address space (it
1717 * does not have a container and cannot be a root either because
1718 * it has no references, so we can blindly clear mr->enabled.
1719 * memory_region_set_enabled instead could trigger a transaction
1720 * and cause an infinite loop.
1721 */
1722 mr->enabled = false;
1723 memory_region_transaction_begin();
1724 while (!QTAILQ_EMPTY(&mr->subregions)) {
1725 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1726 memory_region_del_subregion(mr, subregion);
1727 }
1728 memory_region_transaction_commit();
1729
545e92e0 1730 mr->destructor(mr);
093bc2cd 1731 memory_region_clear_coalescing(mr);
302fa283 1732 g_free((char *)mr->name);
7267c094 1733 g_free(mr->ioeventfds);
093bc2cd
AK
1734}
1735
803c0816
PB
1736Object *memory_region_owner(MemoryRegion *mr)
1737{
22a893e4
PB
1738 Object *obj = OBJECT(mr);
1739 return obj->parent;
803c0816
PB
1740}
1741
46637be2
PB
1742void memory_region_ref(MemoryRegion *mr)
1743{
22a893e4
PB
1744 /* MMIO callbacks most likely will access data that belongs
1745 * to the owner, hence the need to ref/unref the owner whenever
1746 * the memory region is in use.
1747 *
1748 * The memory region is a child of its owner. As long as the
1749 * owner doesn't call unparent itself on the memory region,
1750 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1751 * Memory regions without an owner are supposed to never go away;
1752 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1753 */
612263cf
PB
1754 if (mr && mr->owner) {
1755 object_ref(mr->owner);
46637be2
PB
1756 }
1757}
1758
1759void memory_region_unref(MemoryRegion *mr)
1760{
612263cf
PB
1761 if (mr && mr->owner) {
1762 object_unref(mr->owner);
46637be2
PB
1763 }
1764}
1765
093bc2cd
AK
1766uint64_t memory_region_size(MemoryRegion *mr)
1767{
08dafab4
AK
1768 if (int128_eq(mr->size, int128_2_64())) {
1769 return UINT64_MAX;
1770 }
1771 return int128_get64(mr->size);
093bc2cd
AK
1772}
1773
5d546d4b 1774const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1775{
d1dd32af
PC
1776 if (!mr->name) {
1777 ((MemoryRegion *)mr)->name =
1778 object_get_canonical_path_component(OBJECT(mr));
1779 }
302fa283 1780 return mr->name;
8991c79b
AK
1781}
1782
21e00fa5 1783bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1784{
21e00fa5 1785 return mr->ram_device;
e4dc3f59
ND
1786}
1787
2d1a35be 1788uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1789{
6f6a5ef3 1790 uint8_t mask = mr->dirty_log_mask;
adaad61c 1791 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1792 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1793 }
1794 return mask;
55043ba3
AK
1795}
1796
2d1a35be
PB
1797bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1798{
1799 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1800}
1801
549d4005
EA
1802static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1803 Error **errp)
5bf3d319
PX
1804{
1805 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1806 IOMMUNotifier *iommu_notifier;
1221a474 1807 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
549d4005 1808 int ret = 0;
5bf3d319 1809
3df9d748 1810 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1811 flags |= iommu_notifier->notifier_flags;
1812 }
1813
1221a474 1814 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
549d4005
EA
1815 ret = imrc->notify_flag_changed(iommu_mr,
1816 iommu_mr->iommu_notify_flags,
1817 flags, errp);
5bf3d319
PX
1818 }
1819
549d4005
EA
1820 if (!ret) {
1821 iommu_mr->iommu_notify_flags = flags;
1822 }
1823 return ret;
5bf3d319
PX
1824}
1825
549d4005
EA
1826int memory_region_register_iommu_notifier(MemoryRegion *mr,
1827 IOMMUNotifier *n, Error **errp)
06866575 1828{
3df9d748 1829 IOMMUMemoryRegion *iommu_mr;
549d4005 1830 int ret;
3df9d748 1831
efcd38c5 1832 if (mr->alias) {
549d4005 1833 return memory_region_register_iommu_notifier(mr->alias, n, errp);
efcd38c5
JW
1834 }
1835
cdb30812 1836 /* We need to register for at least one bitfield */
3df9d748 1837 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1838 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1839 assert(n->start <= n->end);
cb1efcf4
PM
1840 assert(n->iommu_idx >= 0 &&
1841 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1842
3df9d748 1843 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
549d4005
EA
1844 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1845 if (ret) {
1846 QLIST_REMOVE(n, node);
1847 }
1848 return ret;
06866575
DG
1849}
1850
3df9d748 1851uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1852{
1221a474
AK
1853 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1854
1855 if (imrc->get_min_page_size) {
1856 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1857 }
1858 return TARGET_PAGE_SIZE;
1859}
1860
3df9d748 1861void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1862{
3df9d748 1863 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1864 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1865 hwaddr addr, granularity;
a788f227
DG
1866 IOMMUTLBEntry iotlb;
1867
faa362e3 1868 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1869 if (imrc->replay) {
1870 imrc->replay(iommu_mr, n);
faa362e3
PX
1871 return;
1872 }
1873
3df9d748 1874 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1875
a788f227 1876 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
2c91bcf2 1877 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
a788f227
DG
1878 if (iotlb.perm != IOMMU_NONE) {
1879 n->notify(n, &iotlb);
1880 }
1881
1882 /* if (2^64 - MR size) < granularity, it's possible to get an
1883 * infinite loop here. This should catch such a wraparound */
1884 if ((addr + granularity) < addr) {
1885 break;
1886 }
1887 }
1888}
1889
cdb30812
PX
1890void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1891 IOMMUNotifier *n)
06866575 1892{
3df9d748
AK
1893 IOMMUMemoryRegion *iommu_mr;
1894
efcd38c5
JW
1895 if (mr->alias) {
1896 memory_region_unregister_iommu_notifier(mr->alias, n);
1897 return;
1898 }
cdb30812 1899 QLIST_REMOVE(n, node);
3df9d748 1900 iommu_mr = IOMMU_MEMORY_REGION(mr);
549d4005 1901 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
06866575
DG
1902}
1903
bd2bfa4c
PX
1904void memory_region_notify_one(IOMMUNotifier *notifier,
1905 IOMMUTLBEntry *entry)
06866575 1906{
cdb30812 1907 IOMMUNotifierFlag request_flags;
03c7140c 1908 hwaddr entry_end = entry->iova + entry->addr_mask;
cdb30812 1909
bd2bfa4c
PX
1910 /*
1911 * Skip the notification if the notification does not overlap
1912 * with registered range.
1913 */
03c7140c 1914 if (notifier->start > entry_end || notifier->end < entry->iova) {
bd2bfa4c
PX
1915 return;
1916 }
cdb30812 1917
03c7140c
YZ
1918 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1919
bd2bfa4c 1920 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1921 request_flags = IOMMU_NOTIFIER_MAP;
1922 } else {
1923 request_flags = IOMMU_NOTIFIER_UNMAP;
1924 }
1925
bd2bfa4c
PX
1926 if (notifier->notifier_flags & request_flags) {
1927 notifier->notify(notifier, entry);
1928 }
1929}
1930
3df9d748 1931void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
cb1efcf4 1932 int iommu_idx,
bd2bfa4c
PX
1933 IOMMUTLBEntry entry)
1934{
1935 IOMMUNotifier *iommu_notifier;
1936
3df9d748 1937 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1938
3df9d748 1939 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
cb1efcf4
PM
1940 if (iommu_notifier->iommu_idx == iommu_idx) {
1941 memory_region_notify_one(iommu_notifier, &entry);
1942 }
cdb30812 1943 }
06866575
DG
1944}
1945
f1334de6
AK
1946int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1947 enum IOMMUMemoryRegionAttr attr,
1948 void *data)
1949{
1950 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1951
1952 if (!imrc->get_attr) {
1953 return -EINVAL;
1954 }
1955
1956 return imrc->get_attr(iommu_mr, attr, data);
1957}
1958
21f40209
PM
1959int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1960 MemTxAttrs attrs)
1961{
1962 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1963
1964 if (!imrc->attrs_to_index) {
1965 return 0;
1966 }
1967
1968 return imrc->attrs_to_index(iommu_mr, attrs);
1969}
1970
1971int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1972{
1973 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1974
1975 if (!imrc->num_indexes) {
1976 return 1;
1977 }
1978
1979 return imrc->num_indexes(iommu_mr);
1980}
1981
093bc2cd
AK
1982void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1983{
5a583347 1984 uint8_t mask = 1 << client;
deb809ed 1985 uint8_t old_logging;
5a583347 1986
dbddac6d 1987 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
1988 old_logging = mr->vga_logging_count;
1989 mr->vga_logging_count += log ? 1 : -1;
1990 if (!!old_logging == !!mr->vga_logging_count) {
1991 return;
1992 }
1993
59023ef4 1994 memory_region_transaction_begin();
5a583347 1995 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1996 memory_region_update_pending |= mr->enabled;
59023ef4 1997 memory_region_transaction_commit();
093bc2cd
AK
1998}
1999
a8170e5e
AK
2000void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2001 hwaddr size)
093bc2cd 2002{
8e41fb63
FZ
2003 assert(mr->ram_block);
2004 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2005 size,
58d2707e 2006 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
2007}
2008
0fe1eca7 2009static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
093bc2cd 2010{
0a752eee 2011 MemoryListener *listener;
0d673e36 2012 AddressSpace *as;
0a752eee 2013 FlatView *view;
5a583347
AK
2014 FlatRange *fr;
2015
0a752eee
PB
2016 /* If the same address space has multiple log_sync listeners, we
2017 * visit that address space's FlatView multiple times. But because
2018 * log_sync listeners are rare, it's still cheaper than walking each
2019 * address space once.
2020 */
2021 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2022 if (!listener->log_sync) {
2023 continue;
2024 }
2025 as = listener->address_space;
2026 view = address_space_get_flatview(as);
99e86347 2027 FOR_EACH_FLAT_RANGE(fr, view) {
3ebb1817 2028 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
16620684 2029 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 2030 listener->log_sync(listener, &mrs);
0d673e36 2031 }
5a583347 2032 }
856d7245 2033 flatview_unref(view);
5a583347 2034 }
093bc2cd
AK
2035}
2036
077874e0
PX
2037void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2038 hwaddr len)
2039{
2040 MemoryRegionSection mrs;
2041 MemoryListener *listener;
2042 AddressSpace *as;
2043 FlatView *view;
2044 FlatRange *fr;
2045 hwaddr sec_start, sec_end, sec_size;
2046
2047 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2048 if (!listener->log_clear) {
2049 continue;
2050 }
2051 as = listener->address_space;
2052 view = address_space_get_flatview(as);
2053 FOR_EACH_FLAT_RANGE(fr, view) {
2054 if (!fr->dirty_log_mask || fr->mr != mr) {
2055 /*
2056 * Clear dirty bitmap operation only applies to those
2057 * regions whose dirty logging is at least enabled
2058 */
2059 continue;
2060 }
2061
2062 mrs = section_from_flat_range(fr, view);
2063
2064 sec_start = MAX(mrs.offset_within_region, start);
2065 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2066 sec_end = MIN(sec_end, start + len);
2067
2068 if (sec_start >= sec_end) {
2069 /*
2070 * If this memory region section has no intersection
2071 * with the requested range, skip.
2072 */
2073 continue;
2074 }
2075
2076 /* Valid case; shrink the section if needed */
2077 mrs.offset_within_address_space +=
2078 sec_start - mrs.offset_within_region;
2079 mrs.offset_within_region = sec_start;
2080 sec_size = sec_end - sec_start;
2081 mrs.size = int128_make64(sec_size);
2082 listener->log_clear(listener, &mrs);
2083 }
2084 flatview_unref(view);
2085 }
2086}
2087
0fe1eca7
PB
2088DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2089 hwaddr addr,
2090 hwaddr size,
2091 unsigned client)
2092{
9458a9a1 2093 DirtyBitmapSnapshot *snapshot;
0fe1eca7
PB
2094 assert(mr->ram_block);
2095 memory_region_sync_dirty_bitmap(mr);
9458a9a1
PB
2096 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2097 memory_global_after_dirty_log_sync();
2098 return snapshot;
0fe1eca7
PB
2099}
2100
2101bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2102 hwaddr addr, hwaddr size)
2103{
2104 assert(mr->ram_block);
2105 return cpu_physical_memory_snapshot_get_dirty(snap,
2106 memory_region_get_ram_addr(mr) + addr, size);
2107}
2108
093bc2cd
AK
2109void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2110{
fb1cd6f9 2111 if (mr->readonly != readonly) {
59023ef4 2112 memory_region_transaction_begin();
fb1cd6f9 2113 mr->readonly = readonly;
22bde714 2114 memory_region_update_pending |= mr->enabled;
59023ef4 2115 memory_region_transaction_commit();
fb1cd6f9 2116 }
093bc2cd
AK
2117}
2118
c26763f8
MAL
2119void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2120{
2121 if (mr->nonvolatile != nonvolatile) {
2122 memory_region_transaction_begin();
2123 mr->nonvolatile = nonvolatile;
2124 memory_region_update_pending |= mr->enabled;
2125 memory_region_transaction_commit();
2126 }
2127}
2128
5f9a5ea1 2129void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2130{
5f9a5ea1 2131 if (mr->romd_mode != romd_mode) {
59023ef4 2132 memory_region_transaction_begin();
5f9a5ea1 2133 mr->romd_mode = romd_mode;
22bde714 2134 memory_region_update_pending |= mr->enabled;
59023ef4 2135 memory_region_transaction_commit();
d0a9b5bc
AK
2136 }
2137}
2138
a8170e5e
AK
2139void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2140 hwaddr size, unsigned client)
093bc2cd 2141{
8e41fb63
FZ
2142 assert(mr->ram_block);
2143 cpu_physical_memory_test_and_clear_dirty(
2144 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
2145}
2146
a35ba7be
PB
2147int memory_region_get_fd(MemoryRegion *mr)
2148{
4ff87573
PB
2149 int fd;
2150
694ea274 2151 RCU_READ_LOCK_GUARD();
4ff87573
PB
2152 while (mr->alias) {
2153 mr = mr->alias;
a35ba7be 2154 }
4ff87573 2155 fd = mr->ram_block->fd;
a35ba7be 2156
4ff87573
PB
2157 return fd;
2158}
a35ba7be 2159
093bc2cd
AK
2160void *memory_region_get_ram_ptr(MemoryRegion *mr)
2161{
49b24afc
PB
2162 void *ptr;
2163 uint64_t offset = 0;
093bc2cd 2164
694ea274 2165 RCU_READ_LOCK_GUARD();
49b24afc
PB
2166 while (mr->alias) {
2167 offset += mr->alias_offset;
2168 mr = mr->alias;
2169 }
8e41fb63 2170 assert(mr->ram_block);
0878d0e1 2171 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
093bc2cd 2172
0878d0e1 2173 return ptr;
093bc2cd
AK
2174}
2175
07bdaa41
PB
2176MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2177{
2178 RAMBlock *block;
2179
2180 block = qemu_ram_block_from_host(ptr, false, offset);
2181 if (!block) {
2182 return NULL;
2183 }
2184
2185 return block->mr;
2186}
2187
7ebb2745
FZ
2188ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2189{
2190 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2191}
2192
37d7c084
PB
2193void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2194{
8e41fb63 2195 assert(mr->ram_block);
37d7c084 2196
fa53a0e5 2197 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
2198}
2199
9ecc996a
PMD
2200void memory_region_msync(MemoryRegion *mr, hwaddr addr, hwaddr size)
2201{
2202 if (mr->ram_block) {
ab7e41e6 2203 qemu_ram_msync(mr->ram_block, addr, size);
9ecc996a
PMD
2204 }
2205}
61c490e2 2206
4dfe59d1 2207void memory_region_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size)
61c490e2
BM
2208{
2209 /*
2210 * Might be extended case needed to cover
2211 * different types of memory regions
2212 */
9ecc996a
PMD
2213 if (mr->dirty_log_mask) {
2214 memory_region_msync(mr, addr, size);
61c490e2
BM
2215 }
2216}
2217
b960fc17
PX
2218/*
2219 * Call proper memory listeners about the change on the newly
2220 * added/removed CoalescedMemoryRange.
2221 */
2222static void memory_region_update_coalesced_range(MemoryRegion *mr,
2223 CoalescedMemoryRange *cmr,
2224 bool add)
093bc2cd 2225{
b960fc17 2226 AddressSpace *as;
99e86347 2227 FlatView *view;
093bc2cd 2228 FlatRange *fr;
093bc2cd 2229
0d673e36 2230 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b960fc17
PX
2231 view = address_space_get_flatview(as);
2232 FOR_EACH_FLAT_RANGE(fr, view) {
2233 if (fr->mr == mr) {
2234 flat_range_coalesced_io_notify(fr, as, cmr, add);
2235 }
2236 }
2237 flatview_unref(view);
0d673e36
AK
2238 }
2239}
2240
093bc2cd
AK
2241void memory_region_set_coalescing(MemoryRegion *mr)
2242{
2243 memory_region_clear_coalescing(mr);
08dafab4 2244 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
2245}
2246
2247void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2248 hwaddr offset,
093bc2cd
AK
2249 uint64_t size)
2250{
7267c094 2251 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2252
08dafab4 2253 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd 2254 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
b960fc17 2255 memory_region_update_coalesced_range(mr, cmr, true);
d410515e 2256 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2257}
2258
2259void memory_region_clear_coalescing(MemoryRegion *mr)
2260{
2261 CoalescedMemoryRange *cmr;
9c1aa1c2
PX
2262
2263 if (QTAILQ_EMPTY(&mr->coalesced)) {
2264 return;
2265 }
093bc2cd 2266
d410515e
JK
2267 qemu_flush_coalesced_mmio_buffer();
2268 mr->flush_coalesced_mmio = false;
2269
093bc2cd
AK
2270 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2271 cmr = QTAILQ_FIRST(&mr->coalesced);
2272 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
b960fc17 2273 memory_region_update_coalesced_range(mr, cmr, false);
7267c094 2274 g_free(cmr);
ab5b3db5 2275 }
093bc2cd
AK
2276}
2277
d410515e
JK
2278void memory_region_set_flush_coalesced(MemoryRegion *mr)
2279{
2280 mr->flush_coalesced_mmio = true;
2281}
2282
2283void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2284{
2285 qemu_flush_coalesced_mmio_buffer();
2286 if (QTAILQ_EMPTY(&mr->coalesced)) {
2287 mr->flush_coalesced_mmio = false;
2288 }
2289}
2290
196ea131
JK
2291void memory_region_clear_global_locking(MemoryRegion *mr)
2292{
2293 mr->global_locking = false;
2294}
2295
8c56c1a5
PF
2296static bool userspace_eventfd_warning;
2297
3e9d69e7 2298void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2299 hwaddr addr,
3e9d69e7
AK
2300 unsigned size,
2301 bool match_data,
2302 uint64_t data,
753d5e14 2303 EventNotifier *e)
3e9d69e7
AK
2304{
2305 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2306 .addr.start = int128_make64(addr),
2307 .addr.size = int128_make64(size),
3e9d69e7
AK
2308 .match_data = match_data,
2309 .data = data,
753d5e14 2310 .e = e,
3e9d69e7
AK
2311 };
2312 unsigned i;
2313
8c56c1a5
PF
2314 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2315 userspace_eventfd_warning))) {
2316 userspace_eventfd_warning = true;
2317 error_report("Using eventfd without MMIO binding in KVM. "
2318 "Suboptimal performance expected");
2319 }
2320
b8aecea2 2321 if (size) {
9bf825bf 2322 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
b8aecea2 2323 }
59023ef4 2324 memory_region_transaction_begin();
3e9d69e7 2325 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2326 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2327 break;
2328 }
2329 }
2330 ++mr->ioeventfd_nb;
7267c094 2331 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2332 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2333 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2334 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2335 mr->ioeventfds[i] = mrfd;
4dc56152 2336 ioeventfd_update_pending |= mr->enabled;
59023ef4 2337 memory_region_transaction_commit();
3e9d69e7
AK
2338}
2339
2340void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2341 hwaddr addr,
3e9d69e7
AK
2342 unsigned size,
2343 bool match_data,
2344 uint64_t data,
753d5e14 2345 EventNotifier *e)
3e9d69e7
AK
2346{
2347 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2348 .addr.start = int128_make64(addr),
2349 .addr.size = int128_make64(size),
3e9d69e7
AK
2350 .match_data = match_data,
2351 .data = data,
753d5e14 2352 .e = e,
3e9d69e7
AK
2353 };
2354 unsigned i;
2355
b8aecea2 2356 if (size) {
9bf825bf 2357 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
b8aecea2 2358 }
59023ef4 2359 memory_region_transaction_begin();
3e9d69e7 2360 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2361 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2362 break;
2363 }
2364 }
2365 assert(i != mr->ioeventfd_nb);
2366 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2367 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2368 --mr->ioeventfd_nb;
7267c094 2369 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2370 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2371 ioeventfd_update_pending |= mr->enabled;
59023ef4 2372 memory_region_transaction_commit();
3e9d69e7
AK
2373}
2374
feca4ac1 2375static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2376{
feca4ac1 2377 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2378 MemoryRegion *other;
2379
59023ef4
JK
2380 memory_region_transaction_begin();
2381
dfde4e6e 2382 memory_region_ref(subregion);
093bc2cd
AK
2383 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2384 if (subregion->priority >= other->priority) {
2385 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2386 goto done;
2387 }
2388 }
2389 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2390done:
22bde714 2391 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2392 memory_region_transaction_commit();
093bc2cd
AK
2393}
2394
0598701a
PC
2395static void memory_region_add_subregion_common(MemoryRegion *mr,
2396 hwaddr offset,
2397 MemoryRegion *subregion)
2398{
feca4ac1
PB
2399 assert(!subregion->container);
2400 subregion->container = mr;
0598701a 2401 subregion->addr = offset;
feca4ac1 2402 memory_region_update_container_subregions(subregion);
0598701a 2403}
093bc2cd
AK
2404
2405void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2406 hwaddr offset,
093bc2cd
AK
2407 MemoryRegion *subregion)
2408{
093bc2cd
AK
2409 subregion->priority = 0;
2410 memory_region_add_subregion_common(mr, offset, subregion);
2411}
2412
2413void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2414 hwaddr offset,
093bc2cd 2415 MemoryRegion *subregion,
a1ff8ae0 2416 int priority)
093bc2cd 2417{
093bc2cd
AK
2418 subregion->priority = priority;
2419 memory_region_add_subregion_common(mr, offset, subregion);
2420}
2421
2422void memory_region_del_subregion(MemoryRegion *mr,
2423 MemoryRegion *subregion)
2424{
59023ef4 2425 memory_region_transaction_begin();
feca4ac1
PB
2426 assert(subregion->container == mr);
2427 subregion->container = NULL;
093bc2cd 2428 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2429 memory_region_unref(subregion);
22bde714 2430 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2431 memory_region_transaction_commit();
6bba19ba
AK
2432}
2433
2434void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2435{
2436 if (enabled == mr->enabled) {
2437 return;
2438 }
59023ef4 2439 memory_region_transaction_begin();
6bba19ba 2440 mr->enabled = enabled;
22bde714 2441 memory_region_update_pending = true;
59023ef4 2442 memory_region_transaction_commit();
093bc2cd 2443}
1c0ffa58 2444
e7af4c67
MT
2445void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2446{
2447 Int128 s = int128_make64(size);
2448
2449 if (size == UINT64_MAX) {
2450 s = int128_2_64();
2451 }
2452 if (int128_eq(s, mr->size)) {
2453 return;
2454 }
2455 memory_region_transaction_begin();
2456 mr->size = s;
2457 memory_region_update_pending = true;
2458 memory_region_transaction_commit();
2459}
2460
67891b8a 2461static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2462{
feca4ac1 2463 MemoryRegion *container = mr->container;
2282e1af 2464
feca4ac1 2465 if (container) {
67891b8a
PC
2466 memory_region_transaction_begin();
2467 memory_region_ref(mr);
feca4ac1
PB
2468 memory_region_del_subregion(container, mr);
2469 mr->container = container;
2470 memory_region_update_container_subregions(mr);
67891b8a
PC
2471 memory_region_unref(mr);
2472 memory_region_transaction_commit();
2282e1af 2473 }
67891b8a 2474}
2282e1af 2475
67891b8a
PC
2476void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2477{
2478 if (addr != mr->addr) {
2479 mr->addr = addr;
2480 memory_region_readd_subregion(mr);
2481 }
2282e1af
AK
2482}
2483
a8170e5e 2484void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2485{
4703359e 2486 assert(mr->alias);
4703359e 2487
59023ef4 2488 if (offset == mr->alias_offset) {
4703359e
AK
2489 return;
2490 }
2491
59023ef4
JK
2492 memory_region_transaction_begin();
2493 mr->alias_offset = offset;
22bde714 2494 memory_region_update_pending |= mr->enabled;
59023ef4 2495 memory_region_transaction_commit();
4703359e
AK
2496}
2497
a2b257d6
IM
2498uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2499{
2500 return mr->align;
2501}
2502
e2177955
AK
2503static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2504{
2505 const AddrRange *addr = addr_;
2506 const FlatRange *fr = fr_;
2507
2508 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2509 return -1;
2510 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2511 return 1;
2512 }
2513 return 0;
2514}
2515
99e86347 2516static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2517{
99e86347 2518 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2519 sizeof(FlatRange), cmp_flatrange_addr);
2520}
2521
eed2bacf
IM
2522bool memory_region_is_mapped(MemoryRegion *mr)
2523{
2524 return mr->container ? true : false;
2525}
2526
c6742b14
PB
2527/* Same as memory_region_find, but it does not add a reference to the
2528 * returned region. It must be called from an RCU critical section.
2529 */
2530static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2531 hwaddr addr, uint64_t size)
e2177955 2532{
052e87b0 2533 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2534 MemoryRegion *root;
2535 AddressSpace *as;
2536 AddrRange range;
99e86347 2537 FlatView *view;
73034e9e
PB
2538 FlatRange *fr;
2539
2540 addr += mr->addr;
feca4ac1
PB
2541 for (root = mr; root->container; ) {
2542 root = root->container;
73034e9e
PB
2543 addr += root->addr;
2544 }
e2177955 2545
73034e9e 2546 as = memory_region_to_address_space(root);
eed2bacf
IM
2547 if (!as) {
2548 return ret;
2549 }
73034e9e 2550 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2551
16620684 2552 view = address_space_to_flatview(as);
99e86347 2553 fr = flatview_lookup(view, range);
e2177955 2554 if (!fr) {
c6742b14 2555 return ret;
e2177955
AK
2556 }
2557
99e86347 2558 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2559 --fr;
2560 }
2561
2562 ret.mr = fr->mr;
16620684 2563 ret.fv = view;
e2177955
AK
2564 range = addrrange_intersection(range, fr->addr);
2565 ret.offset_within_region = fr->offset_in_region;
2566 ret.offset_within_region += int128_get64(int128_sub(range.start,
2567 fr->addr.start));
052e87b0 2568 ret.size = range.size;
e2177955 2569 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2570 ret.readonly = fr->readonly;
c26763f8 2571 ret.nonvolatile = fr->nonvolatile;
c6742b14
PB
2572 return ret;
2573}
2574
2575MemoryRegionSection memory_region_find(MemoryRegion *mr,
2576 hwaddr addr, uint64_t size)
2577{
2578 MemoryRegionSection ret;
694ea274 2579 RCU_READ_LOCK_GUARD();
c6742b14
PB
2580 ret = memory_region_find_rcu(mr, addr, size);
2581 if (ret.mr) {
2582 memory_region_ref(ret.mr);
2583 }
e2177955
AK
2584 return ret;
2585}
2586
c6742b14
PB
2587bool memory_region_present(MemoryRegion *container, hwaddr addr)
2588{
2589 MemoryRegion *mr;
2590
694ea274 2591 RCU_READ_LOCK_GUARD();
c6742b14 2592 mr = memory_region_find_rcu(container, addr, 1).mr;
c6742b14
PB
2593 return mr && mr != container;
2594}
2595
9c1f8f44 2596void memory_global_dirty_log_sync(void)
86e775c6 2597{
3ebb1817 2598 memory_region_sync_dirty_bitmap(NULL);
7664e80c
AK
2599}
2600
9458a9a1
PB
2601void memory_global_after_dirty_log_sync(void)
2602{
2603 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2604}
2605
19310760
JZ
2606static VMChangeStateEntry *vmstate_change;
2607
7664e80c
AK
2608void memory_global_dirty_log_start(void)
2609{
19310760
JZ
2610 if (vmstate_change) {
2611 qemu_del_vm_change_state_handler(vmstate_change);
2612 vmstate_change = NULL;
2613 }
2614
7664e80c 2615 global_dirty_log = true;
6f6a5ef3 2616
7376e582 2617 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3 2618
39adb536 2619 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2620 memory_region_transaction_begin();
2621 memory_region_update_pending = true;
2622 memory_region_transaction_commit();
7664e80c
AK
2623}
2624
19310760 2625static void memory_global_dirty_log_do_stop(void)
7664e80c 2626{
7664e80c 2627 global_dirty_log = false;
6f6a5ef3 2628
39adb536 2629 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2630 memory_region_transaction_begin();
2631 memory_region_update_pending = true;
2632 memory_region_transaction_commit();
2633
7376e582 2634 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2635}
2636
19310760
JZ
2637static void memory_vm_change_state_handler(void *opaque, int running,
2638 RunState state)
2639{
2640 if (running) {
2641 memory_global_dirty_log_do_stop();
2642
2643 if (vmstate_change) {
2644 qemu_del_vm_change_state_handler(vmstate_change);
2645 vmstate_change = NULL;
2646 }
2647 }
2648}
2649
2650void memory_global_dirty_log_stop(void)
2651{
2652 if (!runstate_is_running()) {
2653 if (vmstate_change) {
2654 return;
2655 }
2656 vmstate_change = qemu_add_vm_change_state_handler(
2657 memory_vm_change_state_handler, NULL);
2658 return;
2659 }
2660
2661 memory_global_dirty_log_do_stop();
2662}
2663
7664e80c
AK
2664static void listener_add_address_space(MemoryListener *listener,
2665 AddressSpace *as)
2666{
99e86347 2667 FlatView *view;
7664e80c
AK
2668 FlatRange *fr;
2669
680a4783
PB
2670 if (listener->begin) {
2671 listener->begin(listener);
2672 }
7664e80c 2673 if (global_dirty_log) {
975aefe0
AK
2674 if (listener->log_global_start) {
2675 listener->log_global_start(listener);
2676 }
7664e80c 2677 }
975aefe0 2678
856d7245 2679 view = address_space_get_flatview(as);
99e86347 2680 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH
2681 MemoryRegionSection section = section_from_flat_range(fr, view);
2682
975aefe0
AK
2683 if (listener->region_add) {
2684 listener->region_add(listener, &section);
2685 }
ae990e6c
DH
2686 if (fr->dirty_log_mask && listener->log_start) {
2687 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2688 }
7664e80c 2689 }
680a4783
PB
2690 if (listener->commit) {
2691 listener->commit(listener);
2692 }
856d7245 2693 flatview_unref(view);
7664e80c
AK
2694}
2695
d25836ca
PX
2696static void listener_del_address_space(MemoryListener *listener,
2697 AddressSpace *as)
2698{
2699 FlatView *view;
2700 FlatRange *fr;
2701
2702 if (listener->begin) {
2703 listener->begin(listener);
2704 }
2705 view = address_space_get_flatview(as);
2706 FOR_EACH_FLAT_RANGE(fr, view) {
2707 MemoryRegionSection section = section_from_flat_range(fr, view);
2708
2709 if (fr->dirty_log_mask && listener->log_stop) {
2710 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2711 }
2712 if (listener->region_del) {
2713 listener->region_del(listener, &section);
2714 }
2715 }
2716 if (listener->commit) {
2717 listener->commit(listener);
2718 }
2719 flatview_unref(view);
2720}
2721
d45fa784 2722void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2723{
72e22d2f
AK
2724 MemoryListener *other = NULL;
2725
d45fa784 2726 listener->address_space = as;
72e22d2f 2727 if (QTAILQ_EMPTY(&memory_listeners)
eae3eb3e 2728 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
72e22d2f
AK
2729 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2730 } else {
2731 QTAILQ_FOREACH(other, &memory_listeners, link) {
2732 if (listener->priority < other->priority) {
2733 break;
2734 }
2735 }
2736 QTAILQ_INSERT_BEFORE(other, listener, link);
2737 }
0d673e36 2738
9a54635d 2739 if (QTAILQ_EMPTY(&as->listeners)
eae3eb3e 2740 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
9a54635d
PB
2741 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2742 } else {
2743 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2744 if (listener->priority < other->priority) {
2745 break;
2746 }
2747 }
2748 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2749 }
2750
d45fa784 2751 listener_add_address_space(listener, as);
7664e80c
AK
2752}
2753
2754void memory_listener_unregister(MemoryListener *listener)
2755{
1d8280c1
PB
2756 if (!listener->address_space) {
2757 return;
2758 }
2759
d25836ca 2760 listener_del_address_space(listener, listener->address_space);
72e22d2f 2761 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2762 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2763 listener->address_space = NULL;
86e775c6 2764}
e2177955 2765
a2166410
GK
2766void address_space_remove_listeners(AddressSpace *as)
2767{
2768 while (!QTAILQ_EMPTY(&as->listeners)) {
2769 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2770 }
2771}
2772
7dca8043 2773void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2774{
ac95190e 2775 memory_region_ref(root);
8786db7c 2776 as->root = root;
67ace39b 2777 as->current_map = NULL;
4c19eb72
AK
2778 as->ioeventfd_nb = 0;
2779 as->ioeventfds = NULL;
9a54635d 2780 QTAILQ_INIT(&as->listeners);
0d673e36 2781 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2782 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK
2783 address_space_update_topology(as);
2784 address_space_update_ioeventfds(as);
1c0ffa58 2785}
658b2224 2786
374f2981 2787static void do_address_space_destroy(AddressSpace *as)
83f3c251 2788{
9a54635d 2789 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2790
856d7245 2791 flatview_unref(as->current_map);
7dca8043 2792 g_free(as->name);
4c19eb72 2793 g_free(as->ioeventfds);
ac95190e 2794 memory_region_unref(as->root);
83f3c251
AK
2795}
2796
374f2981
PB
2797void address_space_destroy(AddressSpace *as)
2798{
ac95190e
PB
2799 MemoryRegion *root = as->root;
2800
374f2981
PB
2801 /* Flush out anything from MemoryListeners listening in on this */
2802 memory_region_transaction_begin();
2803 as->root = NULL;
2804 memory_region_transaction_commit();
2805 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2806
2807 /* At this point, as->dispatch and as->current_map are dummy
2808 * entries that the guest should never use. Wait for the old
2809 * values to expire before freeing the data.
2810 */
ac95190e 2811 as->root = root;
374f2981
PB
2812 call_rcu(as, do_address_space_destroy, rcu);
2813}
2814
4e831901
PX
2815static const char *memory_region_type(MemoryRegion *mr)
2816{
39fa93c4
PMD
2817 if (mr->alias) {
2818 return memory_region_type(mr->alias);
2819 }
4e831901
PX
2820 if (memory_region_is_ram_device(mr)) {
2821 return "ramd";
2822 } else if (memory_region_is_romd(mr)) {
2823 return "romd";
2824 } else if (memory_region_is_rom(mr)) {
2825 return "rom";
2826 } else if (memory_region_is_ram(mr)) {
2827 return "ram";
2828 } else {
2829 return "i/o";
2830 }
2831}
2832
314e2987
BS
2833typedef struct MemoryRegionList MemoryRegionList;
2834
2835struct MemoryRegionList {
2836 const MemoryRegion *mr;
a16878d2 2837 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2838};
2839
b58deb34 2840typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
314e2987 2841
4e831901
PX
2842#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2843 int128_sub((size), int128_one())) : 0)
2844#define MTREE_INDENT " "
2845
b6b71cb5 2846static void mtree_expand_owner(const char *label, Object *obj)
fc051ae6
AK
2847{
2848 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2849
b6b71cb5 2850 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
fc051ae6 2851 if (dev && dev->id) {
b6b71cb5 2852 qemu_printf(" id=%s", dev->id);
fc051ae6 2853 } else {
ddfb0baa 2854 char *canonical_path = object_get_canonical_path(obj);
fc051ae6 2855 if (canonical_path) {
b6b71cb5 2856 qemu_printf(" path=%s", canonical_path);
fc051ae6
AK
2857 g_free(canonical_path);
2858 } else {
b6b71cb5 2859 qemu_printf(" type=%s", object_get_typename(obj));
fc051ae6
AK
2860 }
2861 }
b6b71cb5 2862 qemu_printf("}");
fc051ae6
AK
2863}
2864
b6b71cb5 2865static void mtree_print_mr_owner(const MemoryRegion *mr)
fc051ae6
AK
2866{
2867 Object *owner = mr->owner;
2868 Object *parent = memory_region_owner((MemoryRegion *)mr);
2869
2870 if (!owner && !parent) {
b6b71cb5 2871 qemu_printf(" orphan");
fc051ae6
AK
2872 return;
2873 }
2874 if (owner) {
b6b71cb5 2875 mtree_expand_owner("owner", owner);
fc051ae6
AK
2876 }
2877 if (parent && parent != owner) {
b6b71cb5 2878 mtree_expand_owner("parent", parent);
fc051ae6
AK
2879 }
2880}
2881
b6b71cb5 2882static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
a8170e5e 2883 hwaddr base,
fc051ae6 2884 MemoryRegionListHead *alias_print_queue,
2261d393 2885 bool owner, bool display_disabled)
314e2987 2886{
9479c57a
JK
2887 MemoryRegionList *new_ml, *ml, *next_ml;
2888 MemoryRegionListHead submr_print_queue;
314e2987
BS
2889 const MemoryRegion *submr;
2890 unsigned int i;
b31f8412 2891 hwaddr cur_start, cur_end;
314e2987 2892
f8a9f720 2893 if (!mr) {
314e2987
BS
2894 return;
2895 }
2896
b31f8412
PX
2897 cur_start = base + mr->addr;
2898 cur_end = cur_start + MR_SIZE(mr->size);
2899
2900 /*
2901 * Try to detect overflow of memory region. This should never
2902 * happen normally. When it happens, we dump something to warn the
2903 * user who is observing this.
2904 */
2905 if (cur_start < base || cur_end < cur_start) {
b6b71cb5 2906 qemu_printf("[DETECTED OVERFLOW!] ");
b31f8412
PX
2907 }
2908
314e2987
BS
2909 if (mr->alias) {
2910 MemoryRegionList *ml;
2911 bool found = false;
2912
2913 /* check if the alias is already in the queue */
a16878d2 2914 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2915 if (ml->mr == mr->alias) {
314e2987
BS
2916 found = true;
2917 }
2918 }
2919
2920 if (!found) {
2921 ml = g_new(MemoryRegionList, 1);
2922 ml->mr = mr->alias;
a16878d2 2923 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2924 }
2261d393
PMD
2925 if (mr->enabled || display_disabled) {
2926 for (i = 0; i < level; i++) {
2927 qemu_printf(MTREE_INDENT);
2928 }
2929 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2930 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2931 "-" TARGET_FMT_plx "%s",
2932 cur_start, cur_end,
2933 mr->priority,
2934 mr->nonvolatile ? "nv-" : "",
2935 memory_region_type((MemoryRegion *)mr),
2936 memory_region_name(mr),
2937 memory_region_name(mr->alias),
2938 mr->alias_offset,
2939 mr->alias_offset + MR_SIZE(mr->size),
2940 mr->enabled ? "" : " [disabled]");
2941 if (owner) {
2942 mtree_print_mr_owner(mr);
2943 }
2944 qemu_printf("\n");
fc051ae6 2945 }
314e2987 2946 } else {
2261d393
PMD
2947 if (mr->enabled || display_disabled) {
2948 for (i = 0; i < level; i++) {
2949 qemu_printf(MTREE_INDENT);
2950 }
2951 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2952 " (prio %d, %s%s): %s%s",
2953 cur_start, cur_end,
2954 mr->priority,
2955 mr->nonvolatile ? "nv-" : "",
2956 memory_region_type((MemoryRegion *)mr),
2957 memory_region_name(mr),
2958 mr->enabled ? "" : " [disabled]");
2959 if (owner) {
2960 mtree_print_mr_owner(mr);
2961 }
2962 qemu_printf("\n");
fc051ae6 2963 }
314e2987 2964 }
9479c57a
JK
2965
2966 QTAILQ_INIT(&submr_print_queue);
2967
314e2987 2968 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2969 new_ml = g_new(MemoryRegionList, 1);
2970 new_ml->mr = submr;
a16878d2 2971 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2972 if (new_ml->mr->addr < ml->mr->addr ||
2973 (new_ml->mr->addr == ml->mr->addr &&
2974 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2975 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2976 new_ml = NULL;
2977 break;
2978 }
2979 }
2980 if (new_ml) {
a16878d2 2981 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2982 }
2983 }
2984
a16878d2 2985 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b6b71cb5 2986 mtree_print_mr(ml->mr, level + 1, cur_start,
2261d393 2987 alias_print_queue, owner, display_disabled);
9479c57a
JK
2988 }
2989
a16878d2 2990 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2991 g_free(ml);
314e2987
BS
2992 }
2993}
2994
5e8fd947 2995struct FlatViewInfo {
5e8fd947
AK
2996 int counter;
2997 bool dispatch_tree;
fc051ae6 2998 bool owner;
8072aae3 2999 AccelClass *ac;
5e8fd947
AK
3000};
3001
3002static void mtree_print_flatview(gpointer key, gpointer value,
3003 gpointer user_data)
57bb40c9 3004{
5e8fd947
AK
3005 FlatView *view = key;
3006 GArray *fv_address_spaces = value;
3007 struct FlatViewInfo *fvi = user_data;
57bb40c9
PX
3008 FlatRange *range = &view->ranges[0];
3009 MemoryRegion *mr;
3010 int n = view->nr;
5e8fd947
AK
3011 int i;
3012 AddressSpace *as;
3013
b6b71cb5 3014 qemu_printf("FlatView #%d\n", fvi->counter);
5e8fd947
AK
3015 ++fvi->counter;
3016
3017 for (i = 0; i < fv_address_spaces->len; ++i) {
3018 as = g_array_index(fv_address_spaces, AddressSpace*, i);
b6b71cb5
MA
3019 qemu_printf(" AS \"%s\", root: %s",
3020 as->name, memory_region_name(as->root));
5e8fd947 3021 if (as->root->alias) {
b6b71cb5 3022 qemu_printf(", alias %s", memory_region_name(as->root->alias));
5e8fd947 3023 }
b6b71cb5 3024 qemu_printf("\n");
5e8fd947
AK
3025 }
3026
b6b71cb5 3027 qemu_printf(" Root memory region: %s\n",
5e8fd947 3028 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX
3029
3030 if (n <= 0) {
b6b71cb5 3031 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX
3032 return;
3033 }
3034
3035 while (n--) {
3036 mr = range->mr;
377a07aa 3037 if (range->offset_in_region) {
b6b71cb5
MA
3038 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3039 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3040 int128_get64(range->addr.start),
3041 int128_get64(range->addr.start)
3042 + MR_SIZE(range->addr.size),
3043 mr->priority,
3044 range->nonvolatile ? "nv-" : "",
3045 range->readonly ? "rom" : memory_region_type(mr),
3046 memory_region_name(mr),
3047 range->offset_in_region);
377a07aa 3048 } else {
b6b71cb5
MA
3049 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3050 " (prio %d, %s%s): %s",
3051 int128_get64(range->addr.start),
3052 int128_get64(range->addr.start)
3053 + MR_SIZE(range->addr.size),
3054 mr->priority,
3055 range->nonvolatile ? "nv-" : "",
3056 range->readonly ? "rom" : memory_region_type(mr),
3057 memory_region_name(mr));
377a07aa 3058 }
fc051ae6 3059 if (fvi->owner) {
b6b71cb5 3060 mtree_print_mr_owner(mr);
fc051ae6 3061 }
8072aae3
AK
3062
3063 if (fvi->ac) {
3064 for (i = 0; i < fv_address_spaces->len; ++i) {
3065 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3066 if (fvi->ac->has_memory(current_machine, as,
3067 int128_get64(range->addr.start),
3068 MR_SIZE(range->addr.size) + 1)) {
53b62bec 3069 qemu_printf(" %s", fvi->ac->name);
8072aae3
AK
3070 }
3071 }
3072 }
b6b71cb5 3073 qemu_printf("\n");
57bb40c9
PX
3074 range++;
3075 }
3076
5e8fd947
AK
3077#if !defined(CONFIG_USER_ONLY)
3078 if (fvi->dispatch_tree && view->root) {
b6b71cb5 3079 mtree_print_dispatch(view->dispatch, view->root);
5e8fd947
AK
3080 }
3081#endif
3082
b6b71cb5 3083 qemu_printf("\n");
5e8fd947
AK
3084}
3085
3086static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3087 gpointer user_data)
3088{
3089 FlatView *view = key;
3090 GArray *fv_address_spaces = value;
3091
3092 g_array_unref(fv_address_spaces);
57bb40c9 3093 flatview_unref(view);
5e8fd947
AK
3094
3095 return true;
57bb40c9
PX
3096}
3097
2261d393 3098void mtree_info(bool flatview, bool dispatch_tree, bool owner, bool disabled)
314e2987
BS
3099{
3100 MemoryRegionListHead ml_head;
3101 MemoryRegionList *ml, *ml2;
0d673e36 3102 AddressSpace *as;
314e2987 3103
57bb40c9 3104 if (flatview) {
5e8fd947
AK
3105 FlatView *view;
3106 struct FlatViewInfo fvi = {
5e8fd947 3107 .counter = 0,
fc051ae6
AK
3108 .dispatch_tree = dispatch_tree,
3109 .owner = owner,
5e8fd947
AK
3110 };
3111 GArray *fv_address_spaces;
3112 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
4f7f5893 3113 AccelClass *ac = ACCEL_GET_CLASS(current_accel());
8072aae3
AK
3114
3115 if (ac->has_memory) {
3116 fvi.ac = ac;
8072aae3 3117 }
5e8fd947
AK
3118
3119 /* Gather all FVs in one table */
57bb40c9 3120 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK
3121 view = address_space_get_flatview(as);
3122
3123 fv_address_spaces = g_hash_table_lookup(views, view);
3124 if (!fv_address_spaces) {
3125 fv_address_spaces = g_array_new(false, false, sizeof(as));
3126 g_hash_table_insert(views, view, fv_address_spaces);
3127 }
3128
3129 g_array_append_val(fv_address_spaces, as);
57bb40c9 3130 }
5e8fd947
AK
3131
3132 /* Print */
3133 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3134
3135 /* Free */
3136 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3137 g_hash_table_unref(views);
3138
57bb40c9
PX
3139 return;
3140 }
3141
314e2987
BS
3142 QTAILQ_INIT(&ml_head);
3143
0d673e36 3144 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b6b71cb5 3145 qemu_printf("address-space: %s\n", as->name);
2261d393 3146 mtree_print_mr(as->root, 1, 0, &ml_head, owner, disabled);
b6b71cb5 3147 qemu_printf("\n");
b9f9be88
BS
3148 }
3149
314e2987 3150 /* print aliased regions */
a16878d2 3151 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
b6b71cb5 3152 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
2261d393 3153 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner, disabled);
b6b71cb5 3154 qemu_printf("\n");
314e2987
BS
3155 }
3156
a16878d2 3157 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3158 g_free(ml);
314e2987 3159 }
314e2987 3160}
b4fefef9 3161
b08199c6
PM
3162void memory_region_init_ram(MemoryRegion *mr,
3163 struct Object *owner,
3164 const char *name,
3165 uint64_t size,
3166 Error **errp)
3167{
3168 DeviceState *owner_dev;
3169 Error *err = NULL;
3170
3171 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3172 if (err) {
3173 error_propagate(errp, err);
3174 return;
3175 }
3176 /* This will assert if owner is neither NULL nor a DeviceState.
3177 * We only want the owner here for the purposes of defining a
3178 * unique name for migration. TODO: Ideally we should implement
3179 * a naming scheme for Objects which are not DeviceStates, in
3180 * which case we can relax this restriction.
3181 */
3182 owner_dev = DEVICE(owner);
3183 vmstate_register_ram(mr, owner_dev);
3184}
3185
3186void memory_region_init_rom(MemoryRegion *mr,
3187 struct Object *owner,
3188 const char *name,
3189 uint64_t size,
3190 Error **errp)
3191{
3192 DeviceState *owner_dev;
3193 Error *err = NULL;
3194
3195 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3196 if (err) {
3197 error_propagate(errp, err);
3198 return;
3199 }
3200 /* This will assert if owner is neither NULL nor a DeviceState.
3201 * We only want the owner here for the purposes of defining a
3202 * unique name for migration. TODO: Ideally we should implement
3203 * a naming scheme for Objects which are not DeviceStates, in
3204 * which case we can relax this restriction.
3205 */
3206 owner_dev = DEVICE(owner);
3207 vmstate_register_ram(mr, owner_dev);
3208}
3209
3210void memory_region_init_rom_device(MemoryRegion *mr,
3211 struct Object *owner,
3212 const MemoryRegionOps *ops,
3213 void *opaque,
3214 const char *name,
3215 uint64_t size,
3216 Error **errp)
3217{
3218 DeviceState *owner_dev;
3219 Error *err = NULL;
3220
3221 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3222 name, size, &err);
3223 if (err) {
3224 error_propagate(errp, err);
3225 return;
3226 }
3227 /* This will assert if owner is neither NULL nor a DeviceState.
3228 * We only want the owner here for the purposes of defining a
3229 * unique name for migration. TODO: Ideally we should implement
3230 * a naming scheme for Objects which are not DeviceStates, in
3231 * which case we can relax this restriction.
3232 */
3233 owner_dev = DEVICE(owner);
3234 vmstate_register_ram(mr, owner_dev);
3235}
3236
b4fefef9
PC
3237static const TypeInfo memory_region_info = {
3238 .parent = TYPE_OBJECT,
3239 .name = TYPE_MEMORY_REGION,
1b53ecd9 3240 .class_size = sizeof(MemoryRegionClass),
b4fefef9
PC
3241 .instance_size = sizeof(MemoryRegion),
3242 .instance_init = memory_region_initfn,
3243 .instance_finalize = memory_region_finalize,
3244};
3245
3df9d748
AK
3246static const TypeInfo iommu_memory_region_info = {
3247 .parent = TYPE_MEMORY_REGION,
3248 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3249 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
3250 .instance_size = sizeof(IOMMUMemoryRegion),
3251 .instance_init = iommu_memory_region_initfn,
1221a474 3252 .abstract = true,
3df9d748
AK
3253};
3254
b4fefef9
PC
3255static void memory_register_types(void)
3256{
3257 type_register_static(&memory_region_info);
3df9d748 3258 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
3259}
3260
3261type_init(memory_register_types)