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target-i386: Add "model" property to X86CPU
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
71ad61d3
AF		 30#include "qapi/qapi-visit-core.h"
31
28f52cc0
VR		 32#include "hyperv.h"
33
c6dc6f63
AP		 34/* feature flags taken from "Intel Processor Identification and the CPUID
35 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
36 * between feature naming conventions, aliases may be added.
37 */
38static const char *feature_name[] = {
39 "fpu", "vme", "de", "pse",
40 "tsc", "msr", "pae", "mce",
41 "cx8", "apic", NULL, "sep",
42 "mtrr", "pge", "mca", "cmov",
43 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
44 NULL, "ds" /* Intel dts */, "acpi", "mmx",
45 "fxsr", "sse", "sse2", "ss",
46 "ht" /* Intel htt */, "tm", "ia64", "pbe",
47};
48static const char *ext_feature_name[] = {
f370be3c 49 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 50 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 51 "tm2", "ssse3", "cid", NULL,
e117f772 52 "fma", "cx16", "xtpr", "pdcm",
c6dc6f63 53 NULL, NULL, "dca", "sse4.1|sse4_1",
e117f772 54 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 55 "tsc-deadline", "aes", "xsave", "osxsave",
e117f772 56 "avx", NULL, NULL, "hypervisor",
c6dc6f63
AP		 57};
58static const char *ext2_feature_name[] = {
59 "fpu", "vme", "de", "pse",
60 "tsc", "msr", "pae", "mce",
61 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
62 "mtrr", "pge", "mca", "cmov",
63 "pat", "pse36", NULL, NULL /* Linux mp */,
3ac8ebfe 64 "nx|xd", NULL, "mmxext", "mmx",
f370be3c 65 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
3ac8ebfe 66 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 67};
68static const char *ext3_feature_name[] = {
69 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
70 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 71 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 72 "skinit", "wdt", NULL, NULL,
e117f772 73 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 74 NULL, NULL, NULL, NULL,
75 NULL, NULL, NULL, NULL,
76 NULL, NULL, NULL, NULL,
77};
78
79static const char *kvm_feature_name[] = {
642258c6 80 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL,
c6dc6f63
AP		 81 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
82 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
83 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
84};
85
296acb64
JR		 86static const char *svm_feature_name[] = {
87 "npt", "lbrv", "svm_lock", "nrip_save",
88 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
89 NULL, NULL, "pause_filter", NULL,
90 "pfthreshold", NULL, NULL, NULL,
91 NULL, NULL, NULL, NULL,
92 NULL, NULL, NULL, NULL,
93 NULL, NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95};
96
c6dc6f63
AP		 97/* collects per-function cpuid data
98 */
99typedef struct model_features_t {
100 uint32_t *guest_feat;
101 uint32_t *host_feat;
102 uint32_t check_feat;
103 const char **flag_names;
104 uint32_t cpuid;
105 } model_features_t;
106
107int check_cpuid = 0;
108int enforce_cpuid = 0;
109
bb44e0d1
JK		 110void host_cpuid(uint32_t function, uint32_t count,
111 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 112{
113#if defined(CONFIG_KVM)
a1fd24af
AL		 114 uint32_t vec[4];
115
116#ifdef __x86_64__
117 asm volatile("cpuid"
118 : "=a"(vec[0]), "=b"(vec[1]),
119 "=c"(vec[2]), "=d"(vec[3])
120 : "0"(function), "c"(count) : "cc");
121#else
122 asm volatile("pusha \n\t"
123 "cpuid \n\t"
124 "mov %%eax, 0(%2) \n\t"
125 "mov %%ebx, 4(%2) \n\t"
126 "mov %%ecx, 8(%2) \n\t"
127 "mov %%edx, 12(%2) \n\t"
128 "popa"
129 : : "a"(function), "c"(count), "S"(vec)
130 : "memory", "cc");
131#endif
132
bdde476a 133 if (eax)
a1fd24af 134 *eax = vec[0];
bdde476a 135 if (ebx)
a1fd24af 136 *ebx = vec[1];
bdde476a 137 if (ecx)
a1fd24af 138 *ecx = vec[2];
bdde476a 139 if (edx)
a1fd24af 140 *edx = vec[3];
bdde476a
AP		 141#endif
142}
c6dc6f63
AP		 143
144#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
145
146/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
147 * a substring. ex if !NULL points to the first char after a substring,
148 * otherwise the string is assumed to sized by a terminating nul.
149 * Return lexical ordering of *s1:*s2.
150 */
151static int sstrcmp(const char *s1, const char *e1, const char *s2,
152 const char *e2)
153{
154 for (;;) {
155 if (!*s1 || !*s2 || *s1 != *s2)
156 return (*s1 - *s2);
157 ++s1, ++s2;
158 if (s1 == e1 && s2 == e2)
159 return (0);
160 else if (s1 == e1)
161 return (*s2);
162 else if (s2 == e2)
163 return (*s1);
164 }
165}
166
167/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
168 * '|' delimited (possibly empty) strings in which case search for a match
169 * within the alternatives proceeds left to right. Return 0 for success,
170 * non-zero otherwise.
171 */
172static int altcmp(const char *s, const char *e, const char *altstr)
173{
174 const char *p, *q;
175
176 for (q = p = altstr; ; ) {
177 while (*p && *p != '|')
178 ++p;
179 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
180 return (0);
181 if (!*p)
182 return (1);
183 else
184 q = ++p;
185 }
186}
187
188/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 189 * *pval and return true, otherwise return false
c6dc6f63 190 */
e41e0fc6
JK		 191static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
192 const char **featureset)
c6dc6f63
AP		 193{
194 uint32_t mask;
195 const char **ppc;
e41e0fc6 196 bool found = false;
c6dc6f63 197
e41e0fc6 198 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 199 if (*ppc && !altcmp(s, e, *ppc)) {
200 *pval |= mask;
e41e0fc6 201 found = true;
c6dc6f63 202 }
e41e0fc6
JK		 203 }
204 return found;
c6dc6f63
AP		 205}
206
207static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
208 uint32_t *ext_features,
209 uint32_t *ext2_features,
210 uint32_t *ext3_features,
296acb64
JR		 211 uint32_t *kvm_features,
212 uint32_t *svm_features)
c6dc6f63
AP		 213{
214 if (!lookup_feature(features, flagname, NULL, feature_name) &&
215 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
216 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
217 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 218 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
219 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 220 fprintf(stderr, "CPU feature %s not found\n", flagname);
221}
222
223typedef struct x86_def_t {
224 struct x86_def_t *next;
225 const char *name;
226 uint32_t level;
227 uint32_t vendor1, vendor2, vendor3;
228 int family;
229 int model;
230 int stepping;
b862d1fe 231 int tsc_khz;
296acb64
JR		 232 uint32_t features, ext_features, ext2_features, ext3_features;
233 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 234 uint32_t xlevel;
235 char model_id[48];
236 int vendor_override;
237 uint32_t flags;
b3baa152
BW		 238 /* Store the results of Centaur's CPUID instructions */
239 uint32_t ext4_features;
240 uint32_t xlevel2;
c6dc6f63
AP		 241} x86_def_t;
242
243#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
244#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
245 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
246#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
247 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
248 CPUID_PSE36 | CPUID_FXSR)
249#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
250#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
251 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
252 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
253 CPUID_PAE | CPUID_SEP | CPUID_APIC)
42673936 254#define EXT2_FEATURE_MASK 0x0183F3FF
c6dc6f63 255
551a2dec
AP		 256#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
257 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
258 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
259 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
260 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 261 /* partly implemented:
262 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
263 CPUID_PSE36 (needed for Solaris) */
264 /* missing:
265 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 266#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 267 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 268 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 269 /* missing:
270 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 271 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
551a2dec
AP		 272#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
273 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
274 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 275 /* missing:
276 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 277#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
278 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 279#define TCG_SVM_FEATURES 0
551a2dec 280
c6dc6f63
AP		 281/* maintains list of cpu model definitions
282 */
283static x86_def_t *x86_defs = {NULL};
284
285/* built-in cpu model definitions (deprecated)
286 */
287static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 288 {
289 .name = "qemu64",
290 .level = 4,
291 .vendor1 = CPUID_VENDOR_AMD_1,
292 .vendor2 = CPUID_VENDOR_AMD_2,
293 .vendor3 = CPUID_VENDOR_AMD_3,
294 .family = 6,
295 .model = 2,
296 .stepping = 3,
297 .features = PPRO_FEATURES |
c6dc6f63 298 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 299 CPUID_PSE36,
300 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
42673936 301 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 302 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
303 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
304 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
305 .xlevel = 0x8000000A,
306 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
307 },
308 {
309 .name = "phenom",
310 .level = 5,
311 .vendor1 = CPUID_VENDOR_AMD_1,
312 .vendor2 = CPUID_VENDOR_AMD_2,
313 .vendor3 = CPUID_VENDOR_AMD_3,
314 .family = 16,
315 .model = 2,
316 .stepping = 3,
c6dc6f63
AP		 317 .features = PPRO_FEATURES |
318 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 319 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 320 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
321 CPUID_EXT_POPCNT,
42673936 322 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 323 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
324 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 325 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 326 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
327 CPUID_EXT3_CR8LEG,
328 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
329 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
330 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
331 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 332 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 333 .xlevel = 0x8000001A,
334 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
335 },
336 {
337 .name = "core2duo",
338 .level = 10,
339 .family = 6,
340 .model = 15,
341 .stepping = 11,
c6dc6f63
AP		 342 .features = PPRO_FEATURES |
343 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 344 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
345 CPUID_HT | CPUID_TM | CPUID_PBE,
346 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
347 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
348 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 349 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
350 .ext3_features = CPUID_EXT3_LAHF_LM,
351 .xlevel = 0x80000008,
352 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
353 },
354 {
355 .name = "kvm64",
356 .level = 5,
357 .vendor1 = CPUID_VENDOR_INTEL_1,
358 .vendor2 = CPUID_VENDOR_INTEL_2,
359 .vendor3 = CPUID_VENDOR_INTEL_3,
360 .family = 15,
361 .model = 6,
362 .stepping = 1,
363 /* Missing: CPUID_VME, CPUID_HT */
364 .features = PPRO_FEATURES |
365 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
366 CPUID_PSE36,
367 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
368 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
369 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
42673936 370 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 371 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
372 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
373 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
374 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
375 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
376 .ext3_features = 0,
377 .xlevel = 0x80000008,
378 .model_id = "Common KVM processor"
379 },
c6dc6f63
AP		 380 {
381 .name = "qemu32",
382 .level = 4,
383 .family = 6,
384 .model = 3,
385 .stepping = 3,
386 .features = PPRO_FEATURES,
387 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 388 .xlevel = 0x80000004,
c6dc6f63
AP		 389 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
390 },
eafaf1e5
AP		 391 {
392 .name = "kvm32",
393 .level = 5,
394 .family = 15,
395 .model = 6,
396 .stepping = 1,
397 .features = PPRO_FEATURES |
398 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
399 .ext_features = CPUID_EXT_SSE3,
400 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
401 .ext3_features = 0,
402 .xlevel = 0x80000008,
403 .model_id = "Common 32-bit KVM processor"
404 },
c6dc6f63
AP		 405 {
406 .name = "coreduo",
407 .level = 10,
408 .family = 6,
409 .model = 14,
410 .stepping = 8,
c6dc6f63 411 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 412 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
413 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
414 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
415 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 416 .ext2_features = CPUID_EXT2_NX,
417 .xlevel = 0x80000008,
418 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
419 },
420 {
421 .name = "486",
58012d66 422 .level = 1,
c6dc6f63
AP		 423 .family = 4,
424 .model = 0,
425 .stepping = 0,
426 .features = I486_FEATURES,
427 .xlevel = 0,
428 },
429 {
430 .name = "pentium",
431 .level = 1,
432 .family = 5,
433 .model = 4,
434 .stepping = 3,
435 .features = PENTIUM_FEATURES,
436 .xlevel = 0,
437 },
438 {
439 .name = "pentium2",
440 .level = 2,
441 .family = 6,
442 .model = 5,
443 .stepping = 2,
444 .features = PENTIUM2_FEATURES,
445 .xlevel = 0,
446 },
447 {
448 .name = "pentium3",
449 .level = 2,
450 .family = 6,
451 .model = 7,
452 .stepping = 3,
453 .features = PENTIUM3_FEATURES,
454 .xlevel = 0,
455 },
456 {
457 .name = "athlon",
458 .level = 2,
459 .vendor1 = CPUID_VENDOR_AMD_1,
460 .vendor2 = CPUID_VENDOR_AMD_2,
461 .vendor3 = CPUID_VENDOR_AMD_3,
462 .family = 6,
463 .model = 2,
464 .stepping = 3,
465 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
42673936 466 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63
AP		 467 .xlevel = 0x80000008,
468 /* XXX: put another string ? */
469 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
470 },
471 {
472 .name = "n270",
473 /* original is on level 10 */
474 .level = 5,
475 .family = 6,
476 .model = 28,
477 .stepping = 2,
478 .features = PPRO_FEATURES |
8560efed
AJ		 479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
480 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 481 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 482 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
483 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
42673936 484 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
8560efed 485 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 486 .xlevel = 0x8000000A,
487 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
488 },
489};
490
491static int cpu_x86_fill_model_id(char *str)
492{
493 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
494 int i;
495
496 for (i = 0; i < 3; i++) {
497 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
498 memcpy(str + i * 16 + 0, &eax, 4);
499 memcpy(str + i * 16 + 4, &ebx, 4);
500 memcpy(str + i * 16 + 8, &ecx, 4);
501 memcpy(str + i * 16 + 12, &edx, 4);
502 }
503 return 0;
504}
505
506static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
507{
508 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
509
510 x86_cpu_def->name = "host";
511 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
512 x86_cpu_def->level = eax;
513 x86_cpu_def->vendor1 = ebx;
514 x86_cpu_def->vendor2 = edx;
515 x86_cpu_def->vendor3 = ecx;
516
517 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
518 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
519 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
520 x86_cpu_def->stepping = eax & 0x0F;
521 x86_cpu_def->ext_features = ecx;
522 x86_cpu_def->features = edx;
523
524 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
525 x86_cpu_def->xlevel = eax;
526
527 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
528 x86_cpu_def->ext2_features = edx;
529 x86_cpu_def->ext3_features = ecx;
530 cpu_x86_fill_model_id(x86_cpu_def->model_id);
531 x86_cpu_def->vendor_override = 0;
532
b3baa152
BW		 533 /* Call Centaur's CPUID instruction. */
534 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
535 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
536 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
537 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
538 if (eax >= 0xC0000001) {
539 /* Support VIA max extended level */
540 x86_cpu_def->xlevel2 = eax;
541 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
542 x86_cpu_def->ext4_features = edx;
543 }
544 }
296acb64
JR		 545
546 /*
547 * Every SVM feature requires emulation support in KVM - so we can't just
548 * read the host features here. KVM might even support SVM features not
549 * available on the host hardware. Just set all bits and mask out the
550 * unsupported ones later.
551 */
552 x86_cpu_def->svm_features = -1;
553
c6dc6f63
AP		 554 return 0;
555}
556
557static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
558{
559 int i;
560
561 for (i = 0; i < 32; ++i)
562 if (1 << i & mask) {
563 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
564 " flag '%s' [0x%08x]\n",
565 f->cpuid >> 16, f->cpuid & 0xffff,
566 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
567 break;
568 }
569 return 0;
570}
571
572/* best effort attempt to inform user requested cpu flags aren't making
573 * their way to the guest. Note: ft[].check_feat ideally should be
574 * specified via a guest_def field to suppress report of extraneous flags.
575 */
576static int check_features_against_host(x86_def_t *guest_def)
577{
578 x86_def_t host_def;
579 uint32_t mask;
580 int rv, i;
581 struct model_features_t ft[] = {
582 {&guest_def->features, &host_def.features,
583 ~0, feature_name, 0x00000000},
584 {&guest_def->ext_features, &host_def.ext_features,
585 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
586 {&guest_def->ext2_features, &host_def.ext2_features,
587 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
588 {&guest_def->ext3_features, &host_def.ext3_features,
589 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
590
591 cpu_x86_fill_host(&host_def);
66fe09ee 592 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 593 for (mask = 1; mask; mask <<= 1)
594 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
595 !(*ft[i].host_feat & mask)) {
596 unavailable_host_feature(&ft[i], mask);
597 rv = 1;
598 }
599 return rv;
600}
601
71ad61d3
AF		 602static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
603 const char *name, Error **errp)
ed5e1ec3 604{
71ad61d3
AF		 605 X86CPU *cpu = X86_CPU(obj);
606 CPUX86State *env = &cpu->env;
607 const int64_t min = 0;
608 const int64_t max = 0xff + 0xf;
609 int64_t value;
610
611 visit_type_int(v, &value, name, errp);
612 if (error_is_set(errp)) {
613 return;
614 }
615 if (value < min || value > max) {
616 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
617 name ? name : "null", value, min, max);
618 return;
619 }
620
ed5e1ec3 621 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 622 if (value > 0x0f) {
623 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 624 } else {
71ad61d3 625 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 626 }
627}
628
c5291a4f
AF		 629static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
630 const char *name, Error **errp)
b0704cbd 631{
c5291a4f
AF		 632 X86CPU *cpu = X86_CPU(obj);
633 CPUX86State *env = &cpu->env;
634 const int64_t min = 0;
635 const int64_t max = 0xff;
636 int64_t value;
637
638 visit_type_int(v, &value, name, errp);
639 if (error_is_set(errp)) {
640 return;
641 }
642 if (value < min || value > max) {
643 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
644 name ? name : "null", value, min, max);
645 return;
646 }
647
b0704cbd 648 env->cpuid_version &= ~0xf00f0;
c5291a4f 649 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 650}
651
38c3dc46
AF		 652static void x86_cpuid_version_set_stepping(CPUX86State *env, int stepping)
653{
654 env->cpuid_version &= ~0xf;
655 env->cpuid_version |= stepping & 0xf;
656}
657
dcce6675
AF		 658static void x86_cpuid_set_model_id(CPUX86State *env, const char *model_id)
659{
660 int c, len, i;
661
662 if (model_id == NULL) {
663 model_id = "";
664 }
665 len = strlen(model_id);
d0a6acf4 666 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 667 for (i = 0; i < 48; i++) {
668 if (i >= len) {
669 c = '\0';
670 } else {
671 c = (uint8_t)model_id[i];
672 }
673 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
674 }
675}
676
c6dc6f63
AP		 677static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
678{
679 unsigned int i;
680 x86_def_t *def;
681
d3c481b3 682 char *s = g_strdup(cpu_model);
c6dc6f63 683 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 684 /* Features to be added*/
685 uint32_t plus_features = 0, plus_ext_features = 0;
686 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
687 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
688 /* Features to be removed */
689 uint32_t minus_features = 0, minus_ext_features = 0;
690 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
691 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 692 uint32_t numvalue;
693
694 for (def = x86_defs; def; def = def->next)
04c5b17a 695 if (name && !strcmp(name, def->name))
c6dc6f63 696 break;
04c5b17a 697 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 698 cpu_x86_fill_host(x86_cpu_def);
699 } else if (!def) {
700 goto error;
701 } else {
702 memcpy(x86_cpu_def, def, sizeof(*def));
703 }
704
705 plus_kvm_features = ~0; /* not supported bits will be filtered out later */
706
707 add_flagname_to_bitmaps("hypervisor", &plus_features,
708 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 709 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 710
711 featurestr = strtok(NULL, ",");
712
713 while (featurestr) {
714 char *val;
715 if (featurestr[0] == '+') {
296acb64
JR		 716 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
717 &plus_ext_features, &plus_ext2_features,
718 &plus_ext3_features, &plus_kvm_features,
719 &plus_svm_features);
c6dc6f63 720 } else if (featurestr[0] == '-') {
296acb64
JR		 721 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
722 &minus_ext_features, &minus_ext2_features,
723 &minus_ext3_features, &minus_kvm_features,
724 &minus_svm_features);
c6dc6f63
AP		 725 } else if ((val = strchr(featurestr, '='))) {
726 *val = 0; val++;
727 if (!strcmp(featurestr, "family")) {
728 char *err;
729 numvalue = strtoul(val, &err, 0);
a88a677f 730 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 731 fprintf(stderr, "bad numerical value %s\n", val);
732 goto error;
733 }
734 x86_cpu_def->family = numvalue;
735 } else if (!strcmp(featurestr, "model")) {
736 char *err;
737 numvalue = strtoul(val, &err, 0);
738 if (!*val || *err || numvalue > 0xff) {
739 fprintf(stderr, "bad numerical value %s\n", val);
740 goto error;
741 }
742 x86_cpu_def->model = numvalue;
743 } else if (!strcmp(featurestr, "stepping")) {
744 char *err;
745 numvalue = strtoul(val, &err, 0);
746 if (!*val || *err || numvalue > 0xf) {
747 fprintf(stderr, "bad numerical value %s\n", val);
748 goto error;
749 }
750 x86_cpu_def->stepping = numvalue ;
751 } else if (!strcmp(featurestr, "level")) {
752 char *err;
753 numvalue = strtoul(val, &err, 0);
754 if (!*val || *err) {
755 fprintf(stderr, "bad numerical value %s\n", val);
756 goto error;
757 }
758 x86_cpu_def->level = numvalue;
759 } else if (!strcmp(featurestr, "xlevel")) {
760 char *err;
761 numvalue = strtoul(val, &err, 0);
762 if (!*val || *err) {
763 fprintf(stderr, "bad numerical value %s\n", val);
764 goto error;
765 }
766 if (numvalue < 0x80000000) {
2f7a21c4 767 numvalue += 0x80000000;
c6dc6f63
AP		 768 }
769 x86_cpu_def->xlevel = numvalue;
770 } else if (!strcmp(featurestr, "vendor")) {
771 if (strlen(val) != 12) {
772 fprintf(stderr, "vendor string must be 12 chars long\n");
773 goto error;
774 }
775 x86_cpu_def->vendor1 = 0;
776 x86_cpu_def->vendor2 = 0;
777 x86_cpu_def->vendor3 = 0;
778 for(i = 0; i < 4; i++) {
779 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
780 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
781 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
782 }
783 x86_cpu_def->vendor_override = 1;
784 } else if (!strcmp(featurestr, "model_id")) {
785 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
786 val);
b862d1fe
JR		 787 } else if (!strcmp(featurestr, "tsc_freq")) {
788 int64_t tsc_freq;
789 char *err;
790
791 tsc_freq = strtosz_suffix_unit(val, &err,
792 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 793 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 794 fprintf(stderr, "bad numerical value %s\n", val);
795 goto error;
796 }
797 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 798 } else if (!strcmp(featurestr, "hv_spinlocks")) {
799 char *err;
800 numvalue = strtoul(val, &err, 0);
801 if (!*val || *err) {
802 fprintf(stderr, "bad numerical value %s\n", val);
803 goto error;
804 }
805 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 806 } else {
807 fprintf(stderr, "unrecognized feature %s\n", featurestr);
808 goto error;
809 }
810 } else if (!strcmp(featurestr, "check")) {
811 check_cpuid = 1;
812 } else if (!strcmp(featurestr, "enforce")) {
813 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 814 } else if (!strcmp(featurestr, "hv_relaxed")) {
815 hyperv_enable_relaxed_timing(true);
816 } else if (!strcmp(featurestr, "hv_vapic")) {
817 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 818 } else {
819 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
820 goto error;
821 }
822 featurestr = strtok(NULL, ",");
823 }
824 x86_cpu_def->features |= plus_features;
825 x86_cpu_def->ext_features |= plus_ext_features;
826 x86_cpu_def->ext2_features |= plus_ext2_features;
827 x86_cpu_def->ext3_features |= plus_ext3_features;
828 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 829 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 830 x86_cpu_def->features &= ~minus_features;
831 x86_cpu_def->ext_features &= ~minus_ext_features;
832 x86_cpu_def->ext2_features &= ~minus_ext2_features;
833 x86_cpu_def->ext3_features &= ~minus_ext3_features;
834 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 835 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 836 if (check_cpuid) {
837 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
838 goto error;
839 }
d3c481b3 840 g_free(s);
c6dc6f63
AP		 841 return 0;
842
843error:
d3c481b3 844 g_free(s);
c6dc6f63
AP		 845 return -1;
846}
847
848/* generate a composite string into buf of all cpuid names in featureset
849 * selected by fbits. indicate truncation at bufsize in the event of overflow.
850 * if flags, suppress names undefined in featureset.
851 */
852static void listflags(char *buf, int bufsize, uint32_t fbits,
853 const char **featureset, uint32_t flags)
854{
855 const char **p = &featureset[31];
856 char *q, *b, bit;
857 int nc;
858
859 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
860 *buf = '\0';
861 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
862 if (fbits & 1 << bit && (*p || !flags)) {
863 if (*p)
864 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
865 else
866 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
867 if (bufsize <= nc) {
868 if (b) {
869 memcpy(b, "...", sizeof("..."));
870 }
871 return;
872 }
873 q += nc;
874 bufsize -= nc;
875 }
876}
877
878/* generate CPU information:
879 * -? list model names
880 * -?model list model names/IDs
881 * -?dump output all model (x86_def_t) data
882 * -?cpuid list all recognized cpuid flag names
883 */
9a78eead 884void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
c6dc6f63
AP		 885{
886 unsigned char model = !strcmp("?model", optarg);
887 unsigned char dump = !strcmp("?dump", optarg);
888 unsigned char cpuid = !strcmp("?cpuid", optarg);
889 x86_def_t *def;
890 char buf[256];
891
892 if (cpuid) {
893 (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
894 listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
895 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
896 listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
897 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
898 listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
899 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
900 listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
901 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
902 return;
903 }
904 for (def = x86_defs; def; def = def->next) {
905 snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
906 if (model || dump) {
907 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
908 } else {
909 (*cpu_fprintf)(f, "x86 %16s\n", buf);
910 }
911 if (dump) {
912 memcpy(buf, &def->vendor1, sizeof (def->vendor1));
913 memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
914 memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
915 buf[12] = '\0';
916 (*cpu_fprintf)(f,
917 " family %d model %d stepping %d level %d xlevel 0x%x"
918 " vendor \"%s\"\n",
919 def->family, def->model, def->stepping, def->level,
920 def->xlevel, buf);
921 listflags(buf, sizeof (buf), def->features, feature_name, 0);
922 (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
923 buf);
924 listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
925 0);
926 (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
927 buf);
928 listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
929 0);
930 (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
931 def->ext2_features, buf);
932 listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
933 0);
934 (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
935 def->ext3_features, buf);
936 (*cpu_fprintf)(f, "\n");
937 }
938 }
ed2c54d4
AP		 939 if (kvm_enabled()) {
940 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
941 }
c6dc6f63
AP		 942}
943
61dcd775 944int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 945{
61dcd775 946 CPUX86State *env = &cpu->env;
c6dc6f63 947 x86_def_t def1, *def = &def1;
71ad61d3 948 Error *error = NULL;
c6dc6f63 949
db0ad1ba
JR		 950 memset(def, 0, sizeof(*def));
951
c6dc6f63
AP		 952 if (cpu_x86_find_by_name(def, cpu_model) < 0)
953 return -1;
954 if (def->vendor1) {
955 env->cpuid_vendor1 = def->vendor1;
956 env->cpuid_vendor2 = def->vendor2;
957 env->cpuid_vendor3 = def->vendor3;
958 } else {
959 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
960 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
961 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
962 }
963 env->cpuid_vendor_override = def->vendor_override;
964 env->cpuid_level = def->level;
71ad61d3 965 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 966 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
38c3dc46 967 x86_cpuid_version_set_stepping(env, def->stepping);
c6dc6f63 968 env->cpuid_features = def->features;
c6dc6f63
AP		 969 env->cpuid_ext_features = def->ext_features;
970 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 971 env->cpuid_ext3_features = def->ext3_features;
c6dc6f63
AP		 972 env->cpuid_xlevel = def->xlevel;
973 env->cpuid_kvm_features = def->kvm_features;
296acb64 974 env->cpuid_svm_features = def->svm_features;
b3baa152
BW		 975 env->cpuid_ext4_features = def->ext4_features;
976 env->cpuid_xlevel2 = def->xlevel2;
b862d1fe 977 env->tsc_khz = def->tsc_khz;
551a2dec
AP		 978 if (!kvm_enabled()) {
979 env->cpuid_features &= TCG_FEATURES;
980 env->cpuid_ext_features &= TCG_EXT_FEATURES;
981 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
982#ifdef TARGET_X86_64
983 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
984#endif
985 );
986 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 987 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 988 }
dcce6675 989 x86_cpuid_set_model_id(env, def->model_id);
71ad61d3
AF		 990 if (error_is_set(&error)) {
991 error_free(error);
992 return -1;
993 }
c6dc6f63
AP		 994 return 0;
995}
996
997#if !defined(CONFIG_USER_ONLY)
998/* copy vendor id string to 32 bit register, nul pad as needed
999 */
1000static void cpyid(const char *s, uint32_t *id)
1001{
1002 char *d = (char *)id;
1003 char i;
1004
1005 for (i = sizeof (*id); i--; )
1006 *d++ = *s ? *s++ : '\0';
1007}
1008
1009/* interpret radix and convert from string to arbitrary scalar,
1010 * otherwise flag failure
1011 */
1012#define setscalar(pval, str, perr) \
1013{ \
1014 char *pend; \
1015 unsigned long ul; \
1016 \
1017 ul = strtoul(str, &pend, 0); \
1018 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1019}
1020
1021/* map cpuid options to feature bits, otherwise return failure
1022 * (option tags in *str are delimited by whitespace)
1023 */
1024static void setfeatures(uint32_t *pval, const char *str,
1025 const char **featureset, int *perr)
1026{
1027 const char *p, *q;
1028
1029 for (q = p = str; *p || *q; q = p) {
1030 while (iswhite(*p))
1031 q = ++p;
1032 while (*p && !iswhite(*p))
1033 ++p;
1034 if (!*q && !*p)
1035 return;
1036 if (!lookup_feature(pval, q, p, featureset)) {
1037 fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
1038 (int)(p - q), q);
1039 *perr = 1;
1040 return;
1041 }
1042 }
1043}
1044
1045/* map config file options to x86_def_t form
1046 */
1047static int cpudef_setfield(const char *name, const char *str, void *opaque)
1048{
1049 x86_def_t *def = opaque;
1050 int err = 0;
1051
1052 if (!strcmp(name, "name")) {
99e1dec0 1053 g_free((void *)def->name);
d3c481b3 1054 def->name = g_strdup(str);
c6dc6f63
AP		 1055 } else if (!strcmp(name, "model_id")) {
1056 strncpy(def->model_id, str, sizeof (def->model_id));
1057 } else if (!strcmp(name, "level")) {
1058 setscalar(&def->level, str, &err)
1059 } else if (!strcmp(name, "vendor")) {
1060 cpyid(&str[0], &def->vendor1);
1061 cpyid(&str[4], &def->vendor2);
1062 cpyid(&str[8], &def->vendor3);
1063 } else if (!strcmp(name, "family")) {
1064 setscalar(&def->family, str, &err)
1065 } else if (!strcmp(name, "model")) {
1066 setscalar(&def->model, str, &err)
1067 } else if (!strcmp(name, "stepping")) {
1068 setscalar(&def->stepping, str, &err)
1069 } else if (!strcmp(name, "feature_edx")) {
1070 setfeatures(&def->features, str, feature_name, &err);
1071 } else if (!strcmp(name, "feature_ecx")) {
1072 setfeatures(&def->ext_features, str, ext_feature_name, &err);
1073 } else if (!strcmp(name, "extfeature_edx")) {
1074 setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
1075 } else if (!strcmp(name, "extfeature_ecx")) {
1076 setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
1077 } else if (!strcmp(name, "xlevel")) {
1078 setscalar(&def->xlevel, str, &err)
1079 } else {
1080 fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
1081 return (1);
1082 }
1083 if (err) {
1084 fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
1085 return (1);
1086 }
1087 return (0);
1088}
1089
1090/* register config file entry as x86_def_t
1091 */
1092static int cpudef_register(QemuOpts *opts, void *opaque)
1093{
7267c094 1094 x86_def_t *def = g_malloc0(sizeof (x86_def_t));
c6dc6f63
AP		 1095
1096 qemu_opt_foreach(opts, cpudef_setfield, def, 1);
1097 def->next = x86_defs;
1098 x86_defs = def;
1099 return (0);
1100}
0e26b7b8
BS		 1101
1102void cpu_clear_apic_feature(CPUX86State *env)
1103{
1104 env->cpuid_features &= ~CPUID_APIC;
1105}
1106
c6dc6f63
AP		 1107#endif /* !CONFIG_USER_ONLY */
1108
1109/* register "cpudef" models defined in configuration file. Here we first
1110 * preload any built-in definitions
1111 */
1112void x86_cpudef_setup(void)
1113{
1114 int i;
1115
1116 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1117 builtin_x86_defs[i].next = x86_defs;
1118 builtin_x86_defs[i].flags = 1;
1119 x86_defs = &builtin_x86_defs[i];
1120 }
1121#if !defined(CONFIG_USER_ONLY)
3329f07b 1122 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
c6dc6f63
AP		 1123#endif
1124}
1125
c6dc6f63
AP		 1126static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1127 uint32_t *ecx, uint32_t *edx)
1128{
1129 *ebx = env->cpuid_vendor1;
1130 *edx = env->cpuid_vendor2;
1131 *ecx = env->cpuid_vendor3;
1132
1133 /* sysenter isn't supported on compatibility mode on AMD, syscall
1134 * isn't supported in compatibility mode on Intel.
1135 * Normally we advertise the actual cpu vendor, but you can override
1136 * this if you want to use KVM's sysenter/syscall emulation
1137 * in compatibility mode and when doing cross vendor migration
1138 */
89354998 1139 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1140 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1141 }
1142}
1143
1144void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1145 uint32_t *eax, uint32_t *ebx,
1146 uint32_t *ecx, uint32_t *edx)
1147{
1148 /* test if maximum index reached */
1149 if (index & 0x80000000) {
b3baa152
BW		 1150 if (index > env->cpuid_xlevel) {
1151 if (env->cpuid_xlevel2 > 0) {
1152 /* Handle the Centaur's CPUID instruction. */
1153 if (index > env->cpuid_xlevel2) {
1154 index = env->cpuid_xlevel2;
1155 } else if (index < 0xC0000000) {
1156 index = env->cpuid_xlevel;
1157 }
1158 } else {
1159 index = env->cpuid_xlevel;
1160 }
1161 }
c6dc6f63
AP		 1162 } else {
1163 if (index > env->cpuid_level)
1164 index = env->cpuid_level;
1165 }
1166
1167 switch(index) {
1168 case 0:
1169 *eax = env->cpuid_level;
1170 get_cpuid_vendor(env, ebx, ecx, edx);
1171 break;
1172 case 1:
1173 *eax = env->cpuid_version;
1174 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1175 *ecx = env->cpuid_ext_features;
1176 *edx = env->cpuid_features;
1177 if (env->nr_cores * env->nr_threads > 1) {
1178 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1179 *edx |= 1 << 28; /* HTT bit */
1180 }
1181 break;
1182 case 2:
1183 /* cache info: needed for Pentium Pro compatibility */
1184 *eax = 1;
1185 *ebx = 0;
1186 *ecx = 0;
1187 *edx = 0x2c307d;
1188 break;
1189 case 4:
1190 /* cache info: needed for Core compatibility */
1191 if (env->nr_cores > 1) {
2f7a21c4 1192 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1193 } else {
2f7a21c4 1194 *eax = 0;
c6dc6f63
AP		 1195 }
1196 switch (count) {
1197 case 0: /* L1 dcache info */
1198 *eax |= 0x0000121;
1199 *ebx = 0x1c0003f;
1200 *ecx = 0x000003f;
1201 *edx = 0x0000001;
1202 break;
1203 case 1: /* L1 icache info */
1204 *eax |= 0x0000122;
1205 *ebx = 0x1c0003f;
1206 *ecx = 0x000003f;
1207 *edx = 0x0000001;
1208 break;
1209 case 2: /* L2 cache info */
1210 *eax |= 0x0000143;
1211 if (env->nr_threads > 1) {
1212 *eax |= (env->nr_threads - 1) << 14;
1213 }
1214 *ebx = 0x3c0003f;
1215 *ecx = 0x0000fff;
1216 *edx = 0x0000001;
1217 break;
1218 default: /* end of info */
1219 *eax = 0;
1220 *ebx = 0;
1221 *ecx = 0;
1222 *edx = 0;
1223 break;
1224 }
1225 break;
1226 case 5:
1227 /* mwait info: needed for Core compatibility */
1228 *eax = 0; /* Smallest monitor-line size in bytes */
1229 *ebx = 0; /* Largest monitor-line size in bytes */
1230 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1231 *edx = 0;
1232 break;
1233 case 6:
1234 /* Thermal and Power Leaf */
1235 *eax = 0;
1236 *ebx = 0;
1237 *ecx = 0;
1238 *edx = 0;
1239 break;
f7911686
YW		 1240 case 7:
1241 if (kvm_enabled()) {
ba9bc59e
JK		 1242 KVMState *s = env->kvm_state;
1243
1244 *eax = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EAX);
1245 *ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX);
1246 *ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX);
1247 *edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX);
f7911686
YW		 1248 } else {
1249 *eax = 0;
1250 *ebx = 0;
1251 *ecx = 0;
1252 *edx = 0;
1253 }
1254 break;
c6dc6f63
AP		 1255 case 9:
1256 /* Direct Cache Access Information Leaf */
1257 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1258 *ebx = 0;
1259 *ecx = 0;
1260 *edx = 0;
1261 break;
1262 case 0xA:
1263 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1264 if (kvm_enabled()) {
1265 KVMState *s = env->kvm_state;
1266
1267 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1268 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1269 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1270 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1271 } else {
1272 *eax = 0;
1273 *ebx = 0;
1274 *ecx = 0;
1275 *edx = 0;
1276 }
c6dc6f63 1277 break;
51e49430
SY		 1278 case 0xD:
1279 /* Processor Extended State */
1280 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1281 *eax = 0;
1282 *ebx = 0;
1283 *ecx = 0;
1284 *edx = 0;
1285 break;
1286 }
1287 if (kvm_enabled()) {
ba9bc59e
JK		 1288 KVMState *s = env->kvm_state;
1289
1290 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1291 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1292 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1293 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1294 } else {
1295 *eax = 0;
1296 *ebx = 0;
1297 *ecx = 0;
1298 *edx = 0;
1299 }
1300 break;
c6dc6f63
AP		 1301 case 0x80000000:
1302 *eax = env->cpuid_xlevel;
1303 *ebx = env->cpuid_vendor1;
1304 *edx = env->cpuid_vendor2;
1305 *ecx = env->cpuid_vendor3;
1306 break;
1307 case 0x80000001:
1308 *eax = env->cpuid_version;
1309 *ebx = 0;
1310 *ecx = env->cpuid_ext3_features;
1311 *edx = env->cpuid_ext2_features;
1312
1313 /* The Linux kernel checks for the CMPLegacy bit and
1314 * discards multiple thread information if it is set.
1315 * So dont set it here for Intel to make Linux guests happy.
1316 */
1317 if (env->nr_cores * env->nr_threads > 1) {
1318 uint32_t tebx, tecx, tedx;
1319 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1320 if (tebx != CPUID_VENDOR_INTEL_1 ||
1321 tedx != CPUID_VENDOR_INTEL_2 ||
1322 tecx != CPUID_VENDOR_INTEL_3) {
1323 *ecx |= 1 << 1; /* CmpLegacy bit */
1324 }
1325 }
c6dc6f63
AP		 1326 break;
1327 case 0x80000002:
1328 case 0x80000003:
1329 case 0x80000004:
1330 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1331 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1332 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1333 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1334 break;
1335 case 0x80000005:
1336 /* cache info (L1 cache) */
1337 *eax = 0x01ff01ff;
1338 *ebx = 0x01ff01ff;
1339 *ecx = 0x40020140;
1340 *edx = 0x40020140;
1341 break;
1342 case 0x80000006:
1343 /* cache info (L2 cache) */
1344 *eax = 0;
1345 *ebx = 0x42004200;
1346 *ecx = 0x02008140;
1347 *edx = 0;
1348 break;
1349 case 0x80000008:
1350 /* virtual & phys address size in low 2 bytes. */
1351/* XXX: This value must match the one used in the MMU code. */
1352 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1353 /* 64 bit processor */
1354/* XXX: The physical address space is limited to 42 bits in exec.c. */
1355 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1356 } else {
1357 if (env->cpuid_features & CPUID_PSE36)
1358 *eax = 0x00000024; /* 36 bits physical */
1359 else
1360 *eax = 0x00000020; /* 32 bits physical */
1361 }
1362 *ebx = 0;
1363 *ecx = 0;
1364 *edx = 0;
1365 if (env->nr_cores * env->nr_threads > 1) {
1366 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1367 }
1368 break;
1369 case 0x8000000A:
296acb64
JR		 1370 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1371 *eax = 0x00000001; /* SVM Revision */
1372 *ebx = 0x00000010; /* nr of ASIDs */
1373 *ecx = 0;
1374 *edx = env->cpuid_svm_features; /* optional features */
1375 } else {
1376 *eax = 0;
1377 *ebx = 0;
1378 *ecx = 0;
1379 *edx = 0;
1380 }
c6dc6f63 1381 break;
b3baa152
BW		 1382 case 0xC0000000:
1383 *eax = env->cpuid_xlevel2;
1384 *ebx = 0;
1385 *ecx = 0;
1386 *edx = 0;
1387 break;
1388 case 0xC0000001:
1389 /* Support for VIA CPU's CPUID instruction */
1390 *eax = env->cpuid_version;
1391 *ebx = 0;
1392 *ecx = 0;
1393 *edx = env->cpuid_ext4_features;
1394 break;
1395 case 0xC0000002:
1396 case 0xC0000003:
1397 case 0xC0000004:
1398 /* Reserved for the future, and now filled with zero */
1399 *eax = 0;
1400 *ebx = 0;
1401 *ecx = 0;
1402 *edx = 0;
1403 break;
c6dc6f63
AP		 1404 default:
1405 /* reserved values: zero */
1406 *eax = 0;
1407 *ebx = 0;
1408 *ecx = 0;
1409 *edx = 0;
1410 break;
1411 }
1412}
5fd2087a
AF		 1413
1414/* CPUClass::reset() */
1415static void x86_cpu_reset(CPUState *s)
1416{
1417 X86CPU *cpu = X86_CPU(s);
1418 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1419 CPUX86State *env = &cpu->env;
c1958aea
AF		 1420 int i;
1421
1422 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1423 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1424 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1425 }
5fd2087a
AF		 1426
1427 xcc->parent_reset(s);
1428
c1958aea
AF		 1429
1430 memset(env, 0, offsetof(CPUX86State, breakpoints));
1431
1432 tlb_flush(env, 1);
1433
1434 env->old_exception = -1;
1435
1436 /* init to reset state */
1437
1438#ifdef CONFIG_SOFTMMU
1439 env->hflags |= HF_SOFTMMU_MASK;
1440#endif
1441 env->hflags2 |= HF2_GIF_MASK;
1442
1443 cpu_x86_update_cr0(env, 0x60000010);
1444 env->a20_mask = ~0x0;
1445 env->smbase = 0x30000;
1446
1447 env->idt.limit = 0xffff;
1448 env->gdt.limit = 0xffff;
1449 env->ldt.limit = 0xffff;
1450 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1451 env->tr.limit = 0xffff;
1452 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1453
1454 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1455 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1456 DESC_R_MASK | DESC_A_MASK);
1457 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1458 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1459 DESC_A_MASK);
1460 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1461 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1462 DESC_A_MASK);
1463 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1464 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1465 DESC_A_MASK);
1466 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1467 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1468 DESC_A_MASK);
1469 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1470 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1471 DESC_A_MASK);
1472
1473 env->eip = 0xfff0;
1474 env->regs[R_EDX] = env->cpuid_version;
1475
1476 env->eflags = 0x2;
1477
1478 /* FPU init */
1479 for (i = 0; i < 8; i++) {
1480 env->fptags[i] = 1;
1481 }
1482 env->fpuc = 0x37f;
1483
1484 env->mxcsr = 0x1f80;
1485
1486 env->pat = 0x0007040600070406ULL;
1487 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1488
1489 memset(env->dr, 0, sizeof(env->dr));
1490 env->dr[6] = DR6_FIXED_1;
1491 env->dr[7] = DR7_FIXED_1;
1492 cpu_breakpoint_remove_all(env, BP_CPU);
1493 cpu_watchpoint_remove_all(env, BP_CPU);
5fd2087a
AF		 1494}
1495
de024815
AF		 1496static void mce_init(X86CPU *cpu)
1497{
1498 CPUX86State *cenv = &cpu->env;
1499 unsigned int bank;
1500
1501 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1502 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1503 (CPUID_MCE | CPUID_MCA)) {
1504 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1505 cenv->mcg_ctl = ~(uint64_t)0;
1506 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1507 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1508 }
1509 }
1510}
1511
1512static void x86_cpu_initfn(Object *obj)
1513{
1514 X86CPU *cpu = X86_CPU(obj);
1515 CPUX86State *env = &cpu->env;
1516
1517 cpu_exec_init(env);
71ad61d3
AF		 1518
1519 object_property_add(obj, "family", "int",
1520 NULL,
1521 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f
AF		 1522 object_property_add(obj, "model", "int",
1523 NULL,
1524 x86_cpuid_version_set_model, NULL, NULL, NULL);
71ad61d3 1525
de024815
AF		 1526 env->cpuid_apic_id = env->cpu_index;
1527 mce_init(cpu);
1528}
1529
5fd2087a
AF		 1530static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1531{
1532 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1533 CPUClass *cc = CPU_CLASS(oc);
1534
1535 xcc->parent_reset = cc->reset;
1536 cc->reset = x86_cpu_reset;
1537}
1538
1539static const TypeInfo x86_cpu_type_info = {
1540 .name = TYPE_X86_CPU,
1541 .parent = TYPE_CPU,
1542 .instance_size = sizeof(X86CPU),
de024815 1543 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 1544 .abstract = false,
1545 .class_size = sizeof(X86CPUClass),
1546 .class_init = x86_cpu_common_class_init,
1547};
1548
1549static void x86_cpu_register_types(void)
1550{
1551 type_register_static(&x86_cpu_type_info);
1552}
1553
1554type_init(x86_cpu_register_types)
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