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edu: fix memory leak on msi_broken platforms
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c
AS		 29#include "hyperv.h"
30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
022c62cb 42#include "exec/ioport.h"
73aa529a 43#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 44#include "hw/pci/pci.h"
15eafc2e 45#include "hw/pci/msi.h"
fd563564 46#include "hw/pci/msix.h"
795c40b8 47#include "migration/blocker.h"
4c663752 48#include "exec/memattrs.h"
8b5ed7df 49#include "trace.h"
05330448
AL		 50
51//#define DEBUG_KVM
52
53#ifdef DEBUG_KVM
8c0d577e 54#define DPRINTF(fmt, ...) \
05330448
AL		 55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56#else
8c0d577e 57#define DPRINTF(fmt, ...) \
05330448
AL		 58 do { } while (0)
59#endif
60
1a03675d
GC		 61#define MSR_KVM_WALL_CLOCK 0x11
62#define MSR_KVM_SYSTEM_TIME 0x12
63
d1138251
EH		 64/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66#define MSR_BUF_SIZE 4096
d71b62a1 67
94a8d39a
JK		 68const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73};
25d2e361 74
c3a3a7d3
JK		 75static bool has_msr_star;
76static bool has_msr_hsave_pa;
c9b8f6b6 77static bool has_msr_tsc_aux;
f28558d3 78static bool has_msr_tsc_adjust;
aa82ba54 79static bool has_msr_tsc_deadline;
df67696e 80static bool has_msr_feature_control;
21e87c46 81static bool has_msr_misc_enable;
fc12d72e 82static bool has_msr_smbase;
79e9ebeb 83static bool has_msr_bndcfgs;
25d2e361 84static int lm_capable_kernel;
7bc3d711 85static bool has_msr_hv_hypercall;
f2a53c9e 86static bool has_msr_hv_crash;
744b8a94 87static bool has_msr_hv_reset;
8c145d7c 88static bool has_msr_hv_vpindex;
46eb8f98 89static bool has_msr_hv_runtime;
866eea9a 90static bool has_msr_hv_synic;
ff99aa64 91static bool has_msr_hv_stimer;
18cd2c17 92static bool has_msr_xss;
b827df58 93
0d894367
PB		 94static bool has_msr_architectural_pmu;
95static uint32_t num_architectural_pmu_counters;
96
28143b40
TH		 97static int has_xsave;
98static int has_xcrs;
99static int has_pit_state2;
100
87f8b626
AR		 101static bool has_msr_mcg_ext_ctl;
102
494e95e9
CP		 103static struct kvm_cpuid2 *cpuid_cache;
104
28143b40
TH		 105int kvm_has_pit_state2(void)
106{
107 return has_pit_state2;
108}
109
355023f2
PB		 110bool kvm_has_smm(void)
111{
112 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
113}
114
6053a86f
MT		 115bool kvm_has_adjust_clock_stable(void)
116{
117 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
118
119 return (ret == KVM_CLOCK_TSC_STABLE);
120}
121
1d31f66b
PM		 122bool kvm_allows_irq0_override(void)
123{
124 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
125}
126
fb506e70
RK		 127static bool kvm_x2apic_api_set_flags(uint64_t flags)
128{
129 KVMState *s = KVM_STATE(current_machine->accelerator);
130
131 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
132}
133
e391c009 134#define MEMORIZE(fn, _result) \
2a138ec3 135 ({ \
2a138ec3
RK		 136 static bool _memorized; \
137 \
138 if (_memorized) { \
139 return _result; \
140 } \
141 _memorized = true; \
142 _result = fn; \
143 })
144
e391c009
IM		 145static bool has_x2apic_api;
146
147bool kvm_has_x2apic_api(void)
148{
149 return has_x2apic_api;
150}
151
fb506e70
RK		 152bool kvm_enable_x2apic(void)
153{
2a138ec3
RK		 154 return MEMORIZE(
155 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 156 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
157 has_x2apic_api);
fb506e70
RK		 158}
159
0fd7e098
LL		 160static int kvm_get_tsc(CPUState *cs)
161{
162 X86CPU *cpu = X86_CPU(cs);
163 CPUX86State *env = &cpu->env;
164 struct {
165 struct kvm_msrs info;
166 struct kvm_msr_entry entries[1];
167 } msr_data;
168 int ret;
169
170 if (env->tsc_valid) {
171 return 0;
172 }
173
174 msr_data.info.nmsrs = 1;
175 msr_data.entries[0].index = MSR_IA32_TSC;
176 env->tsc_valid = !runstate_is_running();
177
178 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
179 if (ret < 0) {
180 return ret;
181 }
182
48e1a45c 183 assert(ret == 1);
0fd7e098
LL		 184 env->tsc = msr_data.entries[0].data;
185 return 0;
186}
187
14e6fe12 188static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 189{
0fd7e098
LL		 190 kvm_get_tsc(cpu);
191}
192
193void kvm_synchronize_all_tsc(void)
194{
195 CPUState *cpu;
196
197 if (kvm_enabled()) {
198 CPU_FOREACH(cpu) {
14e6fe12 199 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 200 }
201 }
202}
203
b827df58
AK		 204static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
205{
206 struct kvm_cpuid2 *cpuid;
207 int r, size;
208
209 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 210 cpuid = g_malloc0(size);
b827df58
AK		 211 cpuid->nent = max;
212 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 213 if (r == 0 && cpuid->nent >= max) {
214 r = -E2BIG;
215 }
b827df58
AK		 216 if (r < 0) {
217 if (r == -E2BIG) {
7267c094 218 g_free(cpuid);
b827df58
AK		 219 return NULL;
220 } else {
221 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
222 strerror(-r));
223 exit(1);
224 }
225 }
226 return cpuid;
227}
228
dd87f8a6
EH		 229/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
230 * for all entries.
231 */
232static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
233{
234 struct kvm_cpuid2 *cpuid;
235 int max = 1;
494e95e9
CP		 236
237 if (cpuid_cache != NULL) {
238 return cpuid_cache;
239 }
dd87f8a6
EH		 240 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
241 max *= 2;
242 }
494e95e9 243 cpuid_cache = cpuid;
dd87f8a6
EH		 244 return cpuid;
245}
246
a443bc34 247static const struct kvm_para_features {
0c31b744
GC		 248 int cap;
249 int feature;
250} para_features[] = {
251 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
252 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
253 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 254 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 255};
256
ba9bc59e 257static int get_para_features(KVMState *s)
0c31b744
GC		 258{
259 int i, features = 0;
260
8e03c100 261 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 262 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 263 features |= (1 << para_features[i].feature);
264 }
265 }
266
267 return features;
268}
0c31b744 269
40e80ee4
EH		 270static bool host_tsx_blacklisted(void)
271{
272 int family, model, stepping;\
273 char vendor[CPUID_VENDOR_SZ + 1];
274
275 host_vendor_fms(vendor, &family, &model, &stepping);
276
277 /* Check if we are running on a Haswell host known to have broken TSX */
278 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
279 (family == 6) &&
280 ((model == 63 && stepping < 4) ||
281 model == 60 || model == 69 || model == 70);
282}
0c31b744 283
829ae2f9
EH		 284/* Returns the value for a specific register on the cpuid entry
285 */
286static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
287{
288 uint32_t ret = 0;
289 switch (reg) {
290 case R_EAX:
291 ret = entry->eax;
292 break;
293 case R_EBX:
294 ret = entry->ebx;
295 break;
296 case R_ECX:
297 ret = entry->ecx;
298 break;
299 case R_EDX:
300 ret = entry->edx;
301 break;
302 }
303 return ret;
304}
305
4fb73f1d
EH		 306/* Find matching entry for function/index on kvm_cpuid2 struct
307 */
308static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
309 uint32_t function,
310 uint32_t index)
311{
312 int i;
313 for (i = 0; i < cpuid->nent; ++i) {
314 if (cpuid->entries[i].function == function &&
315 cpuid->entries[i].index == index) {
316 return &cpuid->entries[i];
317 }
318 }
319 /* not found: */
320 return NULL;
321}
322
ba9bc59e 323uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 324 uint32_t index, int reg)
b827df58
AK		 325{
326 struct kvm_cpuid2 *cpuid;
b827df58
AK		 327 uint32_t ret = 0;
328 uint32_t cpuid_1_edx;
8c723b79 329 bool found = false;
b827df58 330
dd87f8a6 331 cpuid = get_supported_cpuid(s);
b827df58 332
4fb73f1d
EH		 333 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
334 if (entry) {
335 found = true;
336 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 337 }
338
7b46e5ce
EH		 339 /* Fixups for the data returned by KVM, below */
340
c2acb022
EH		 341 if (function == 1 && reg == R_EDX) {
342 /* KVM before 2.6.30 misreports the following features */
343 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 344 } else if (function == 1 && reg == R_ECX) {
345 /* We can set the hypervisor flag, even if KVM does not return it on
346 * GET_SUPPORTED_CPUID
347 */
348 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 349 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
350 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
351 * and the irqchip is in the kernel.
352 */
353 if (kvm_irqchip_in_kernel() &&
354 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
355 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
356 }
41e5e76d
EH		 357
358 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
359 * without the in-kernel irqchip
360 */
361 if (!kvm_irqchip_in_kernel()) {
362 ret &= ~CPUID_EXT_X2APIC;
b827df58 363 }
28b8e4d0
JK		 364 } else if (function == 6 && reg == R_EAX) {
365 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 366 } else if (function == 7 && index == 0 && reg == R_EBX) {
367 if (host_tsx_blacklisted()) {
368 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
369 }
c2acb022
EH		 370 } else if (function == 0x80000001 && reg == R_EDX) {
371 /* On Intel, kvm returns cpuid according to the Intel spec,
372 * so add missing bits according to the AMD spec:
373 */
374 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
375 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 376 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
377 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
378 * be enabled without the in-kernel irqchip
379 */
380 if (!kvm_irqchip_in_kernel()) {
381 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
382 }
b827df58
AK		 383 }
384
0c31b744 385 /* fallback for older kernels */
8c723b79 386 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 387 ret = get_para_features(s);
b9bec74b 388 }
0c31b744
GC		 389
390 return ret;
bb0300dc 391}
bb0300dc 392
3c85e74f
HY		 393typedef struct HWPoisonPage {
394 ram_addr_t ram_addr;
395 QLIST_ENTRY(HWPoisonPage) list;
396} HWPoisonPage;
397
398static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
399 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
400
401static void kvm_unpoison_all(void *param)
402{
403 HWPoisonPage *page, *next_page;
404
405 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
406 QLIST_REMOVE(page, list);
407 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 408 g_free(page);
3c85e74f
HY		 409 }
410}
411
3c85e74f
HY		 412static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
413{
414 HWPoisonPage *page;
415
416 QLIST_FOREACH(page, &hwpoison_page_list, list) {
417 if (page->ram_addr == ram_addr) {
418 return;
419 }
420 }
ab3ad07f 421 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 422 page->ram_addr = ram_addr;
423 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
424}
425
e7701825
MT		 426static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
427 int *max_banks)
428{
429 int r;
430
14a09518 431 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 432 if (r > 0) {
433 *max_banks = r;
434 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
435 }
436 return -ENOSYS;
437}
438
bee615d4 439static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 440{
87f8b626 441 CPUState *cs = CPU(cpu);
bee615d4 442 CPUX86State *env = &cpu->env;
c34d440a
JK		 443 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
444 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
445 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 446 int flags = 0;
e7701825 447
c34d440a
JK		 448 if (code == BUS_MCEERR_AR) {
449 status |= MCI_STATUS_AR | 0x134;
450 mcg_status |= MCG_STATUS_EIPV;
451 } else {
452 status |= 0xc0;
453 mcg_status |= MCG_STATUS_RIPV;
419fb20a 454 }
87f8b626
AR		 455
456 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
457 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
458 * guest kernel back into env->mcg_ext_ctl.
459 */
460 cpu_synchronize_state(cs);
461 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
462 mcg_status |= MCG_STATUS_LMCE;
463 flags = 0;
464 }
465
8c5cf3b6 466 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 467 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 468}
419fb20a
JK		 469
470static void hardware_memory_error(void)
471{
472 fprintf(stderr, "Hardware memory error!\n");
473 exit(1);
474}
475
2ae41db2 476void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 477{
20d695a9
AF		 478 X86CPU *cpu = X86_CPU(c);
479 CPUX86State *env = &cpu->env;
419fb20a 480 ram_addr_t ram_addr;
a8170e5e 481 hwaddr paddr;
419fb20a 482
4d39892c
PB		 483 /* If we get an action required MCE, it has been injected by KVM
484 * while the VM was running. An action optional MCE instead should
485 * be coming from the main thread, which qemu_init_sigbus identifies
486 * as the "early kill" thread.
487 */
a16fc07e 488 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 489
20e0ff59 490 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 491 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 492 if (ram_addr != RAM_ADDR_INVALID &&
493 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
494 kvm_hwpoison_page_add(ram_addr);
495 kvm_mce_inject(cpu, paddr, code);
2ae41db2 496 return;
419fb20a 497 }
20e0ff59
PB		 498
499 fprintf(stderr, "Hardware memory error for memory used by "
500 "QEMU itself instead of guest system!\n");
419fb20a 501 }
20e0ff59
PB		 502
503 if (code == BUS_MCEERR_AR) {
504 hardware_memory_error();
505 }
506
507 /* Hope we are lucky for AO MCE */
419fb20a
JK		 508}
509
1bc22652 510static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 511{
1bc22652
AF		 512 CPUX86State *env = &cpu->env;
513
ab443475
JK		 514 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
515 unsigned int bank, bank_num = env->mcg_cap & 0xff;
516 struct kvm_x86_mce mce;
517
518 env->exception_injected = -1;
519
520 /*
521 * There must be at least one bank in use if an MCE is pending.
522 * Find it and use its values for the event injection.
523 */
524 for (bank = 0; bank < bank_num; bank++) {
525 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
526 break;
527 }
528 }
529 assert(bank < bank_num);
530
531 mce.bank = bank;
532 mce.status = env->mce_banks[bank * 4 + 1];
533 mce.mcg_status = env->mcg_status;
534 mce.addr = env->mce_banks[bank * 4 + 2];
535 mce.misc = env->mce_banks[bank * 4 + 3];
536
1bc22652 537 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 538 }
ab443475
JK		 539 return 0;
540}
541
1dfb4dd9 542static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 543{
317ac620 544 CPUX86State *env = opaque;
b8cc45d6
GC		 545
546 if (running) {
547 env->tsc_valid = false;
548 }
549}
550
83b17af5 551unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 552{
83b17af5 553 X86CPU *cpu = X86_CPU(cs);
7e72a45c 554 return cpu->apic_id;
b164e48e
EH		 555}
556
92067bf4
IM		 557#ifndef KVM_CPUID_SIGNATURE_NEXT
558#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
559#endif
560
561static bool hyperv_hypercall_available(X86CPU *cpu)
562{
563 return cpu->hyperv_vapic ||
564 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
565}
566
567static bool hyperv_enabled(X86CPU *cpu)
568{
7bc3d711
PB		 569 CPUState *cs = CPU(cpu);
570 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
571 (hyperv_hypercall_available(cpu) ||
48a5f3bc 572 cpu->hyperv_time ||
f2a53c9e 573 cpu->hyperv_relaxed_timing ||
744b8a94 574 cpu->hyperv_crash ||
8c145d7c 575 cpu->hyperv_reset ||
46eb8f98 576 cpu->hyperv_vpindex ||
866eea9a 577 cpu->hyperv_runtime ||
ff99aa64
AS		 578 cpu->hyperv_synic ||
579 cpu->hyperv_stimer);
92067bf4
IM		 580}
581
5031283d
HZ		 582static int kvm_arch_set_tsc_khz(CPUState *cs)
583{
584 X86CPU *cpu = X86_CPU(cs);
585 CPUX86State *env = &cpu->env;
586 int r;
587
588 if (!env->tsc_khz) {
589 return 0;
590 }
591
592 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
593 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
594 -ENOTSUP;
595 if (r < 0) {
596 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
597 * TSC frequency doesn't match the one we want.
598 */
599 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
600 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
601 -ENOTSUP;
602 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
603 error_report("warning: TSC frequency mismatch between "
d6276d26
EH		 604 "VM (%" PRId64 " kHz) and host (%d kHz), "
605 "and TSC scaling unavailable",
606 env->tsc_khz, cur_freq);
5031283d
HZ		 607 return r;
608 }
609 }
610
611 return 0;
612}
613
c35bd19a
EY		 614static int hyperv_handle_properties(CPUState *cs)
615{
616 X86CPU *cpu = X86_CPU(cs);
617 CPUX86State *env = &cpu->env;
618
3ddcd2ed
EH		 619 if (cpu->hyperv_time &&
620 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
621 cpu->hyperv_time = false;
622 }
623
c35bd19a
EY		 624 if (cpu->hyperv_relaxed_timing) {
625 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
626 }
627 if (cpu->hyperv_vapic) {
628 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
629 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
c35bd19a 630 }
3ddcd2ed 631 if (cpu->hyperv_time) {
c35bd19a
EY		 632 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
633 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
634 env->features[FEAT_HYPERV_EAX] |= 0x200;
c35bd19a
EY		 635 }
636 if (cpu->hyperv_crash && has_msr_hv_crash) {
637 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
638 }
639 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
640 if (cpu->hyperv_reset && has_msr_hv_reset) {
641 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
642 }
643 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
644 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
645 }
646 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
647 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
648 }
649 if (cpu->hyperv_synic) {
650 int sint;
651
652 if (!has_msr_hv_synic ||
653 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
654 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
655 return -ENOSYS;
656 }
657
658 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
659 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
660 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
661 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
662 }
663 }
664 if (cpu->hyperv_stimer) {
665 if (!has_msr_hv_stimer) {
666 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
667 return -ENOSYS;
668 }
669 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
670 }
671 return 0;
672}
673
68bfd0ad
MT		 674static Error *invtsc_mig_blocker;
675
f8bb0565 676#define KVM_MAX_CPUID_ENTRIES 100
0893d460 677
20d695a9 678int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 679{
680 struct {
486bd5a2 681 struct kvm_cpuid2 cpuid;
f8bb0565 682 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 683 } QEMU_PACKED cpuid_data;
20d695a9
AF		 684 X86CPU *cpu = X86_CPU(cs);
685 CPUX86State *env = &cpu->env;
486bd5a2 686 uint32_t limit, i, j, cpuid_i;
a33609ca 687 uint32_t unused;
bb0300dc 688 struct kvm_cpuid_entry2 *c;
bb0300dc 689 uint32_t signature[3];
234cc647 690 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 691 int r;
fe44dc91 692 Error *local_err = NULL;
05330448 693
ef4cbe14
SW		 694 memset(&cpuid_data, 0, sizeof(cpuid_data));
695
05330448
AL		 696 cpuid_i = 0;
697
bb0300dc 698 /* Paravirtualization CPUIDs */
234cc647
PB		 699 if (hyperv_enabled(cpu)) {
700 c = &cpuid_data.entries[cpuid_i++];
701 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 702 if (!cpu->hyperv_vendor_id) {
703 memcpy(signature, "Microsoft Hv", 12);
704 } else {
705 size_t len = strlen(cpu->hyperv_vendor_id);
706
707 if (len > 12) {
708 error_report("hv-vendor-id truncated to 12 characters");
709 len = 12;
710 }
711 memset(signature, 0, 12);
712 memcpy(signature, cpu->hyperv_vendor_id, len);
713 }
eab70139 714 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 715 c->ebx = signature[0];
716 c->ecx = signature[1];
717 c->edx = signature[2];
0c31b744 718
234cc647
PB		 719 c = &cpuid_data.entries[cpuid_i++];
720 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 721 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
722 c->eax = signature[0];
234cc647
PB		 723 c->ebx = 0;
724 c->ecx = 0;
725 c->edx = 0;
eab70139
VR		 726
727 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 728 c->function = HYPERV_CPUID_VERSION;
729 c->eax = 0x00001bbc;
730 c->ebx = 0x00060001;
731
732 c = &cpuid_data.entries[cpuid_i++];
eab70139 733 c->function = HYPERV_CPUID_FEATURES;
c35bd19a
EY		 734 r = hyperv_handle_properties(cs);
735 if (r) {
736 return r;
46eb8f98 737 }
c35bd19a
EY		 738 c->eax = env->features[FEAT_HYPERV_EAX];
739 c->ebx = env->features[FEAT_HYPERV_EBX];
740 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 741
eab70139 742 c = &cpuid_data.entries[cpuid_i++];
eab70139 743 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 744 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 745 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
746 }
2d5aa872 747 if (cpu->hyperv_vapic) {
eab70139
VR		 748 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
749 }
92067bf4 750 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 751
752 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 753 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
754 c->eax = 0x40;
755 c->ebx = 0x40;
756
234cc647 757 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 758 has_msr_hv_hypercall = true;
eab70139
VR		 759 }
760
f522d2ac
AW		 761 if (cpu->expose_kvm) {
762 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
763 c = &cpuid_data.entries[cpuid_i++];
764 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 765 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 766 c->ebx = signature[0];
767 c->ecx = signature[1];
768 c->edx = signature[2];
234cc647 769
f522d2ac
AW		 770 c = &cpuid_data.entries[cpuid_i++];
771 c->function = KVM_CPUID_FEATURES | kvm_base;
772 c->eax = env->features[FEAT_KVM];
f522d2ac 773 }
917367aa 774
a33609ca 775 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 776
777 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 778 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
779 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
780 abort();
781 }
bb0300dc 782 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 783
784 switch (i) {
a36b1029
AL		 785 case 2: {
786 /* Keep reading function 2 till all the input is received */
787 int times;
788
a36b1029 789 c->function = i;
a33609ca
AL		 790 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
791 KVM_CPUID_FLAG_STATE_READ_NEXT;
792 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
793 times = c->eax & 0xff;
a36b1029
AL		 794
795 for (j = 1; j < times; ++j) {
f8bb0565
IM		 796 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
797 fprintf(stderr, "cpuid_data is full, no space for "
798 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
799 abort();
800 }
a33609ca 801 c = &cpuid_data.entries[cpuid_i++];
a36b1029 802 c->function = i;
a33609ca
AL		 803 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
804 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 805 }
806 break;
807 }
486bd5a2
AL		 808 case 4:
809 case 0xb:
810 case 0xd:
811 for (j = 0; ; j++) {
31e8c696
AP		 812 if (i == 0xd && j == 64) {
813 break;
814 }
486bd5a2
AL		 815 c->function = i;
816 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
817 c->index = j;
a33609ca 818 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 819
b9bec74b 820 if (i == 4 && c->eax == 0) {
486bd5a2 821 break;
b9bec74b
JK		 822 }
823 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 824 break;
b9bec74b
JK		 825 }
826 if (i == 0xd && c->eax == 0) {
31e8c696 827 continue;
b9bec74b 828 }
f8bb0565
IM		 829 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
830 fprintf(stderr, "cpuid_data is full, no space for "
831 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
832 abort();
833 }
a33609ca 834 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 835 }
836 break;
837 default:
486bd5a2 838 c->function = i;
a33609ca
AL		 839 c->flags = 0;
840 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 841 break;
842 }
05330448 843 }
0d894367
PB		 844
845 if (limit >= 0x0a) {
846 uint32_t ver;
847
848 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
849 if ((ver & 0xff) > 0) {
850 has_msr_architectural_pmu = true;
851 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
852
853 /* Shouldn't be more than 32, since that's the number of bits
854 * available in EBX to tell us _which_ counters are available.
855 * Play it safe.
856 */
857 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
858 num_architectural_pmu_counters = MAX_GP_COUNTERS;
859 }
860 }
861 }
862
a33609ca 863 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 864
865 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 866 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
867 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
868 abort();
869 }
bb0300dc 870 c = &cpuid_data.entries[cpuid_i++];
05330448 871
05330448 872 c->function = i;
a33609ca
AL		 873 c->flags = 0;
874 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 875 }
876
b3baa152
BW		 877 /* Call Centaur's CPUID instructions they are supported. */
878 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 879 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
880
881 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 882 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
883 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
884 abort();
885 }
b3baa152
BW		 886 c = &cpuid_data.entries[cpuid_i++];
887
888 c->function = i;
889 c->flags = 0;
890 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
891 }
892 }
893
05330448
AL		 894 cpuid_data.cpuid.nent = cpuid_i;
895
e7701825 896 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 897 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 898 (CPUID_MCE | CPUID_MCA)
a60f24b5 899 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 900 uint64_t mcg_cap, unsupported_caps;
e7701825 901 int banks;
32a42024 902 int ret;
e7701825 903
a60f24b5 904 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 905 if (ret < 0) {
906 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
907 return ret;
e7701825 908 }
75d49497 909
2590f15b 910 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 911 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 912 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 913 return -ENOTSUP;
75d49497 914 }
49b69cbf 915
5120901a
EH		 916 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
917 if (unsupported_caps) {
87f8b626
AR		 918 if (unsupported_caps & MCG_LMCE_P) {
919 error_report("kvm: LMCE not supported");
920 return -ENOTSUP;
921 }
5120901a
EH		 922 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
923 unsupported_caps);
924 }
925
2590f15b
EH		 926 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
927 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 928 if (ret < 0) {
929 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
930 return ret;
931 }
e7701825 932 }
e7701825 933
b8cc45d6
GC		 934 qemu_add_vm_change_state_handler(cpu_update_state, env);
935
df67696e
LJ		 936 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
937 if (c) {
938 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
939 !!(c->ecx & CPUID_EXT_SMX);
940 }
941
87f8b626
AR		 942 if (env->mcg_cap & MCG_LMCE_P) {
943 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
944 }
945
d99569d9
EH		 946 if (!env->user_tsc_khz) {
947 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
948 invtsc_mig_blocker == NULL) {
949 /* for migration */
950 error_setg(&invtsc_mig_blocker,
951 "State blocked by non-migratable CPU device"
952 " (invtsc flag)");
fe44dc91
AA		 953 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
954 if (local_err) {
955 error_report_err(local_err);
956 error_free(invtsc_mig_blocker);
957 goto fail;
958 }
d99569d9
EH		 959 /* for savevm */
960 vmstate_x86_cpu.unmigratable = 1;
961 }
68bfd0ad
MT		 962 }
963
5031283d
HZ		 964 r = kvm_arch_set_tsc_khz(cs);
965 if (r < 0) {
fe44dc91 966 goto fail;
e7429073 967 }
e7429073 968
bcffbeeb
HZ		 969 /* vcpu's TSC frequency is either specified by user, or following
970 * the value used by KVM if the former is not present. In the
971 * latter case, we query it from KVM and record in env->tsc_khz,
972 * so that vcpu's TSC frequency can be migrated later via this field.
973 */
974 if (!env->tsc_khz) {
975 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
976 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
977 -ENOTSUP;
978 if (r > 0) {
979 env->tsc_khz = r;
980 }
981 }
982
9954a158
PDJ		 983 if (cpu->vmware_cpuid_freq
984 /* Guests depend on 0x40000000 to detect this feature, so only expose
985 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
986 && cpu->expose_kvm
987 && kvm_base == KVM_CPUID_SIGNATURE
988 /* TSC clock must be stable and known for this feature. */
989 && ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
990 || env->user_tsc_khz != 0)
991 && env->tsc_khz != 0) {
992
993 c = &cpuid_data.entries[cpuid_i++];
994 c->function = KVM_CPUID_SIGNATURE | 0x10;
995 c->eax = env->tsc_khz;
996 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
997 * APIC_BUS_CYCLE_NS */
998 c->ebx = 1000000;
999 c->ecx = c->edx = 0;
1000
1001 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1002 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1003 }
1004
1005 cpuid_data.cpuid.nent = cpuid_i;
1006
1007 cpuid_data.cpuid.padding = 0;
1008 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1009 if (r) {
1010 goto fail;
1011 }
1012
28143b40 1013 if (has_xsave) {
fabacc0f
JK		 1014 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1015 }
d71b62a1 1016 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1017
273c515c
PB		 1018 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1019 has_msr_tsc_aux = false;
1020 }
d1ae67f6 1021
e7429073 1022 return 0;
fe44dc91
AA		 1023
1024 fail:
1025 migrate_del_blocker(invtsc_mig_blocker);
1026 return r;
05330448
AL		 1027}
1028
50a2c6e5 1029void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1030{
20d695a9 1031 CPUX86State *env = &cpu->env;
dd673288 1032
e73223a5 1033 env->exception_injected = -1;
0e607a80 1034 env->interrupt_injected = -1;
1a5e9d2f 1035 env->xcr0 = 1;
ddced198 1036 if (kvm_irqchip_in_kernel()) {
dd673288 1037 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1038 KVM_MP_STATE_UNINITIALIZED;
1039 } else {
1040 env->mp_state = KVM_MP_STATE_RUNNABLE;
1041 }
caa5af0f
JK		 1042}
1043
e0723c45
PB		 1044void kvm_arch_do_init_vcpu(X86CPU *cpu)
1045{
1046 CPUX86State *env = &cpu->env;
1047
1048 /* APs get directly into wait-for-SIPI state. */
1049 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1050 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1051 }
1052}
1053
c3a3a7d3 1054static int kvm_get_supported_msrs(KVMState *s)
05330448 1055{
75b10c43 1056 static int kvm_supported_msrs;
c3a3a7d3 1057 int ret = 0;
05330448
AL		 1058
1059 /* first time */
75b10c43 1060 if (kvm_supported_msrs == 0) {
05330448
AL		 1061 struct kvm_msr_list msr_list, *kvm_msr_list;
1062
75b10c43 1063 kvm_supported_msrs = -1;
05330448
AL		 1064
1065 /* Obtain MSR list from KVM. These are the MSRs that we must
1066 * save/restore */
4c9f7372 1067 msr_list.nmsrs = 0;
c3a3a7d3 1068 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1069 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1070 return ret;
6fb6d245 1071 }
d9db889f
JK		 1072 /* Old kernel modules had a bug and could write beyond the provided
1073 memory. Allocate at least a safe amount of 1K. */
7267c094 1074 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1075 msr_list.nmsrs *
1076 sizeof(msr_list.indices[0])));
05330448 1077
55308450 1078 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1079 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1080 if (ret >= 0) {
1081 int i;
1082
1083 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1084 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 1085 has_msr_star = true;
75b10c43
MT		 1086 continue;
1087 }
1088 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 1089 has_msr_hsave_pa = true;
75b10c43 1090 continue;
05330448 1091 }
c9b8f6b6
AS		 1092 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1093 has_msr_tsc_aux = true;
1094 continue;
1095 }
f28558d3
WA		 1096 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1097 has_msr_tsc_adjust = true;
1098 continue;
1099 }
aa82ba54
LJ		 1100 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1101 has_msr_tsc_deadline = true;
1102 continue;
1103 }
fc12d72e
PB		 1104 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1105 has_msr_smbase = true;
1106 continue;
1107 }
21e87c46
AK		 1108 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1109 has_msr_misc_enable = true;
1110 continue;
1111 }
79e9ebeb
LJ		 1112 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1113 has_msr_bndcfgs = true;
1114 continue;
1115 }
18cd2c17
WL		 1116 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1117 has_msr_xss = true;
1118 continue;
1119 }
f2a53c9e
AS		 1120 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1121 has_msr_hv_crash = true;
1122 continue;
1123 }
744b8a94
AS		 1124 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1125 has_msr_hv_reset = true;
1126 continue;
1127 }
8c145d7c
AS		 1128 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1129 has_msr_hv_vpindex = true;
1130 continue;
1131 }
46eb8f98
AS		 1132 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1133 has_msr_hv_runtime = true;
1134 continue;
1135 }
866eea9a
AS		 1136 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1137 has_msr_hv_synic = true;
1138 continue;
1139 }
ff99aa64
AS		 1140 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1141 has_msr_hv_stimer = true;
1142 continue;
1143 }
05330448
AL		 1144 }
1145 }
1146
7267c094 1147 g_free(kvm_msr_list);
05330448
AL		 1148 }
1149
c3a3a7d3 1150 return ret;
05330448
AL		 1151}
1152
6410848b
PB		 1153static Notifier smram_machine_done;
1154static KVMMemoryListener smram_listener;
1155static AddressSpace smram_address_space;
1156static MemoryRegion smram_as_root;
1157static MemoryRegion smram_as_mem;
1158
1159static void register_smram_listener(Notifier *n, void *unused)
1160{
1161 MemoryRegion *smram =
1162 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1163
1164 /* Outer container... */
1165 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1166 memory_region_set_enabled(&smram_as_root, true);
1167
1168 /* ... with two regions inside: normal system memory with low
1169 * priority, and...
1170 */
1171 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1172 get_system_memory(), 0, ~0ull);
1173 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1174 memory_region_set_enabled(&smram_as_mem, true);
1175
1176 if (smram) {
1177 /* ... SMRAM with higher priority */
1178 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1179 memory_region_set_enabled(smram, true);
1180 }
1181
1182 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1183 kvm_memory_listener_register(kvm_state, &smram_listener,
1184 &smram_address_space, 1);
1185}
1186
b16565b3 1187int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1188{
11076198 1189 uint64_t identity_base = 0xfffbc000;
39d6960a 1190 uint64_t shadow_mem;
20420430 1191 int ret;
25d2e361 1192 struct utsname utsname;
20420430 1193
28143b40
TH		 1194#ifdef KVM_CAP_XSAVE
1195 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1196#endif
1197
1198#ifdef KVM_CAP_XCRS
1199 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1200#endif
1201
1202#ifdef KVM_CAP_PIT_STATE2
1203 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1204#endif
1205
c3a3a7d3 1206 ret = kvm_get_supported_msrs(s);
20420430 1207 if (ret < 0) {
20420430
SY		 1208 return ret;
1209 }
25d2e361
MT		 1210
1211 uname(&utsname);
1212 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1213
4c5b10b7 1214 /*
11076198
JK		 1215 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1216 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1217 * Since these must be part of guest physical memory, we need to allocate
1218 * them, both by setting their start addresses in the kernel and by
1219 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1220 *
1221 * Older KVM versions may not support setting the identity map base. In
1222 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1223 * size.
4c5b10b7 1224 */
11076198
JK		 1225 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1226 /* Allows up to 16M BIOSes. */
1227 identity_base = 0xfeffc000;
1228
1229 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1230 if (ret < 0) {
1231 return ret;
1232 }
4c5b10b7 1233 }
e56ff191 1234
11076198
JK		 1235 /* Set TSS base one page after EPT identity map. */
1236 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1237 if (ret < 0) {
1238 return ret;
1239 }
1240
11076198
JK		 1241 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1242 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1243 if (ret < 0) {
11076198 1244 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1245 return ret;
1246 }
3c85e74f 1247 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1248
4689b77b 1249 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1250 if (shadow_mem != -1) {
1251 shadow_mem /= 4096;
1252 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1253 if (ret < 0) {
1254 return ret;
39d6960a
JK		 1255 }
1256 }
6410848b
PB		 1257
1258 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1259 smram_machine_done.notify = register_smram_listener;
1260 qemu_add_machine_init_done_notifier(&smram_machine_done);
1261 }
11076198 1262 return 0;
05330448 1263}
b9bec74b 1264
05330448
AL		 1265static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1266{
1267 lhs->selector = rhs->selector;
1268 lhs->base = rhs->base;
1269 lhs->limit = rhs->limit;
1270 lhs->type = 3;
1271 lhs->present = 1;
1272 lhs->dpl = 3;
1273 lhs->db = 0;
1274 lhs->s = 1;
1275 lhs->l = 0;
1276 lhs->g = 0;
1277 lhs->avl = 0;
1278 lhs->unusable = 0;
1279}
1280
1281static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1282{
1283 unsigned flags = rhs->flags;
1284 lhs->selector = rhs->selector;
1285 lhs->base = rhs->base;
1286 lhs->limit = rhs->limit;
1287 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1288 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1289 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1290 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1291 lhs->s = (flags & DESC_S_MASK) != 0;
1292 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1293 lhs->g = (flags & DESC_G_MASK) != 0;
1294 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1295 lhs->unusable = !lhs->present;
7e680753 1296 lhs->padding = 0;
05330448
AL		 1297}
1298
1299static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1300{
1301 lhs->selector = rhs->selector;
1302 lhs->base = rhs->base;
1303 lhs->limit = rhs->limit;
4cae9c97
MC		 1304 if (rhs->unusable) {
1305 lhs->flags = 0;
1306 } else {
1307 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1308 (rhs->present * DESC_P_MASK) |
1309 (rhs->dpl << DESC_DPL_SHIFT) |
1310 (rhs->db << DESC_B_SHIFT) |
1311 (rhs->s * DESC_S_MASK) |
1312 (rhs->l << DESC_L_SHIFT) |
1313 (rhs->g * DESC_G_MASK) |
1314 (rhs->avl * DESC_AVL_MASK);
1315 }
05330448
AL		 1316}
1317
1318static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1319{
b9bec74b 1320 if (set) {
05330448 1321 *kvm_reg = *qemu_reg;
b9bec74b 1322 } else {
05330448 1323 *qemu_reg = *kvm_reg;
b9bec74b 1324 }
05330448
AL		 1325}
1326
1bc22652 1327static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1328{
1bc22652 1329 CPUX86State *env = &cpu->env;
05330448
AL		 1330 struct kvm_regs regs;
1331 int ret = 0;
1332
1333 if (!set) {
1bc22652 1334 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1335 if (ret < 0) {
05330448 1336 return ret;
b9bec74b 1337 }
05330448
AL		 1338 }
1339
1340 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1341 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1342 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1343 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1344 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1345 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1346 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1347 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1348#ifdef TARGET_X86_64
1349 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1350 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1351 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1352 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1353 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1354 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1355 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1356 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1357#endif
1358
1359 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1360 kvm_getput_reg(&regs.rip, &env->eip, set);
1361
b9bec74b 1362 if (set) {
1bc22652 1363 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1364 }
05330448
AL		 1365
1366 return ret;
1367}
1368
1bc22652 1369static int kvm_put_fpu(X86CPU *cpu)
05330448 1370{
1bc22652 1371 CPUX86State *env = &cpu->env;
05330448
AL		 1372 struct kvm_fpu fpu;
1373 int i;
1374
1375 memset(&fpu, 0, sizeof fpu);
1376 fpu.fsw = env->fpus & ~(7 << 11);
1377 fpu.fsw |= (env->fpstt & 7) << 11;
1378 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1379 fpu.last_opcode = env->fpop;
1380 fpu.last_ip = env->fpip;
1381 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1382 for (i = 0; i < 8; ++i) {
1383 fpu.ftwx |= (!env->fptags[i]) << i;
1384 }
05330448 1385 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1386 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1387 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1388 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1389 }
05330448
AL		 1390 fpu.mxcsr = env->mxcsr;
1391
1bc22652 1392 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1393}
1394
6b42494b
JK		 1395#define XSAVE_FCW_FSW 0
1396#define XSAVE_FTW_FOP 1
f1665b21
SY		 1397#define XSAVE_CWD_RIP 2
1398#define XSAVE_CWD_RDP 4
1399#define XSAVE_MXCSR 6
1400#define XSAVE_ST_SPACE 8
1401#define XSAVE_XMM_SPACE 40
1402#define XSAVE_XSTATE_BV 128
1403#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1404#define XSAVE_BNDREGS 240
1405#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1406#define XSAVE_OPMASK 272
1407#define XSAVE_ZMM_Hi256 288
1408#define XSAVE_Hi16_ZMM 416
f74eefe0 1409#define XSAVE_PKRU 672
f1665b21 1410
b503717d
EH		 1411#define XSAVE_BYTE_OFFSET(word_offset) \
1412 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1413
1414#define ASSERT_OFFSET(word_offset, field) \
1415 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1416 offsetof(X86XSaveArea, field))
1417
1418ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1419ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1420ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1421ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1422ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1423ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1424ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1425ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1426ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1427ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1428ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1429ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1430ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1431ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1432ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1433
1bc22652 1434static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1435{
1bc22652 1436 CPUX86State *env = &cpu->env;
86cd2ea0 1437 X86XSaveArea *xsave = env->kvm_xsave_buf;
42cc8fa6 1438 uint16_t cwd, swd, twd;
9be38598 1439 int i;
f1665b21 1440
28143b40 1441 if (!has_xsave) {
1bc22652 1442 return kvm_put_fpu(cpu);
b9bec74b 1443 }
f1665b21 1444
f1665b21 1445 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1446 twd = 0;
f1665b21
SY		 1447 swd = env->fpus & ~(7 << 11);
1448 swd |= (env->fpstt & 7) << 11;
1449 cwd = env->fpuc;
b9bec74b 1450 for (i = 0; i < 8; ++i) {
f1665b21 1451 twd |= (!env->fptags[i]) << i;
b9bec74b 1452 }
86cd2ea0
EH		 1453 xsave->legacy.fcw = cwd;
1454 xsave->legacy.fsw = swd;
1455 xsave->legacy.ftw = twd;
1456 xsave->legacy.fpop = env->fpop;
1457 xsave->legacy.fpip = env->fpip;
1458 xsave->legacy.fpdp = env->fpdp;
1459 memcpy(&xsave->legacy.fpregs, env->fpregs,
f1665b21 1460 sizeof env->fpregs);
86cd2ea0
EH		 1461 xsave->legacy.mxcsr = env->mxcsr;
1462 xsave->header.xstate_bv = env->xstate_bv;
1463 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
79e9ebeb 1464 sizeof env->bnd_regs);
86cd2ea0
EH		 1465 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1466 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
9aecd6f8 1467 sizeof env->opmask_regs);
bee81887 1468
86cd2ea0
EH		 1469 for (i = 0; i < CPU_NB_REGS; i++) {
1470 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1471 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1472 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1473 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1474 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1475 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1476 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1477 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1478 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1479 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1480 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
bee81887
PB		 1481 }
1482
9aecd6f8 1483#ifdef TARGET_X86_64
86cd2ea0 1484 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
b7711471 1485 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1486 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
9aecd6f8 1487#endif
9be38598 1488 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1489}
1490
1bc22652 1491static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1492{
1bc22652 1493 CPUX86State *env = &cpu->env;
bdfc8480 1494 struct kvm_xcrs xcrs = {};
f1665b21 1495
28143b40 1496 if (!has_xcrs) {
f1665b21 1497 return 0;
b9bec74b 1498 }
f1665b21
SY		 1499
1500 xcrs.nr_xcrs = 1;
1501 xcrs.flags = 0;
1502 xcrs.xcrs[0].xcr = 0;
1503 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1504 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1505}
1506
1bc22652 1507static int kvm_put_sregs(X86CPU *cpu)
05330448 1508{
1bc22652 1509 CPUX86State *env = &cpu->env;
05330448
AL		 1510 struct kvm_sregs sregs;
1511
0e607a80
JK		 1512 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1513 if (env->interrupt_injected >= 0) {
1514 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1515 (uint64_t)1 << (env->interrupt_injected % 64);
1516 }
05330448
AL		 1517
1518 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1519 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1520 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1521 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1522 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1523 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1524 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1525 } else {
b9bec74b
JK		 1526 set_seg(&sregs.cs, &env->segs[R_CS]);
1527 set_seg(&sregs.ds, &env->segs[R_DS]);
1528 set_seg(&sregs.es, &env->segs[R_ES]);
1529 set_seg(&sregs.fs, &env->segs[R_FS]);
1530 set_seg(&sregs.gs, &env->segs[R_GS]);
1531 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1532 }
1533
1534 set_seg(&sregs.tr, &env->tr);
1535 set_seg(&sregs.ldt, &env->ldt);
1536
1537 sregs.idt.limit = env->idt.limit;
1538 sregs.idt.base = env->idt.base;
7e680753 1539 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1540 sregs.gdt.limit = env->gdt.limit;
1541 sregs.gdt.base = env->gdt.base;
7e680753 1542 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1543
1544 sregs.cr0 = env->cr[0];
1545 sregs.cr2 = env->cr[2];
1546 sregs.cr3 = env->cr[3];
1547 sregs.cr4 = env->cr[4];
1548
02e51483
CF		 1549 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1550 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1551
1552 sregs.efer = env->efer;
1553
1bc22652 1554 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1555}
1556
d71b62a1
EH		 1557static void kvm_msr_buf_reset(X86CPU *cpu)
1558{
1559 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1560}
1561
9c600a84
EH		 1562static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1563{
1564 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1565 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1566 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1567
1568 assert((void *)(entry + 1) <= limit);
1569
1abc2cae
EH		 1570 entry->index = index;
1571 entry->reserved = 0;
1572 entry->data = value;
9c600a84
EH		 1573 msrs->nmsrs++;
1574}
1575
73e1b8f2
PB		 1576static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1577{
1578 kvm_msr_buf_reset(cpu);
1579 kvm_msr_entry_add(cpu, index, value);
1580
1581 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1582}
1583
f8d9ccf8
DDAG		 1584void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1585{
1586 int ret;
1587
1588 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1589 assert(ret == 1);
1590}
1591
7477cd38
MT		 1592static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1593{
1594 CPUX86State *env = &cpu->env;
48e1a45c 1595 int ret;
7477cd38
MT		 1596
1597 if (!has_msr_tsc_deadline) {
1598 return 0;
1599 }
1600
73e1b8f2 1601 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1602 if (ret < 0) {
1603 return ret;
1604 }
1605
1606 assert(ret == 1);
1607 return 0;
7477cd38
MT		 1608}
1609
6bdf863d
JK		 1610/*
1611 * Provide a separate write service for the feature control MSR in order to
1612 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1613 * before writing any other state because forcibly leaving nested mode
1614 * invalidates the VCPU state.
1615 */
1616static int kvm_put_msr_feature_control(X86CPU *cpu)
1617{
48e1a45c
PB		 1618 int ret;
1619
1620 if (!has_msr_feature_control) {
1621 return 0;
1622 }
6bdf863d 1623
73e1b8f2
PB		 1624 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1625 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1626 if (ret < 0) {
1627 return ret;
1628 }
1629
1630 assert(ret == 1);
1631 return 0;
6bdf863d
JK		 1632}
1633
1bc22652 1634static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1635{
1bc22652 1636 CPUX86State *env = &cpu->env;
9c600a84 1637 int i;
48e1a45c 1638 int ret;
05330448 1639
d71b62a1
EH		 1640 kvm_msr_buf_reset(cpu);
1641
9c600a84
EH		 1642 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1643 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1644 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1645 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1646 if (has_msr_star) {
9c600a84 1647 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1648 }
c3a3a7d3 1649 if (has_msr_hsave_pa) {
9c600a84 1650 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1651 }
c9b8f6b6 1652 if (has_msr_tsc_aux) {
9c600a84 1653 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1654 }
f28558d3 1655 if (has_msr_tsc_adjust) {
9c600a84 1656 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1657 }
21e87c46 1658 if (has_msr_misc_enable) {
9c600a84 1659 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1660 env->msr_ia32_misc_enable);
1661 }
fc12d72e 1662 if (has_msr_smbase) {
9c600a84 1663 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1664 }
439d19f2 1665 if (has_msr_bndcfgs) {
9c600a84 1666 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1667 }
18cd2c17 1668 if (has_msr_xss) {
9c600a84 1669 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1670 }
05330448 1671#ifdef TARGET_X86_64
25d2e361 1672 if (lm_capable_kernel) {
9c600a84
EH		 1673 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1674 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1675 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1676 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1677 }
05330448 1678#endif
ff5c186b 1679 /*
0d894367
PB		 1680 * The following MSRs have side effects on the guest or are too heavy
1681 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1682 */
1683 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1684 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1685 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1686 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1687 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1688 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1689 }
55c911a5 1690 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1691 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1692 }
55c911a5 1693 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1694 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1695 }
0d894367
PB		 1696 if (has_msr_architectural_pmu) {
1697 /* Stop the counter. */
9c600a84
EH		 1698 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1699 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1700
1701 /* Set the counter values. */
1702 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1703 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1704 env->msr_fixed_counters[i]);
1705 }
1706 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1707 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1708 env->msr_gp_counters[i]);
9c600a84 1709 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1710 env->msr_gp_evtsel[i]);
1711 }
9c600a84 1712 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1713 env->msr_global_status);
9c600a84 1714 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1715 env->msr_global_ovf_ctrl);
1716
1717 /* Now start the PMU. */
9c600a84 1718 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1719 env->msr_fixed_ctr_ctrl);
9c600a84 1720 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1721 env->msr_global_ctrl);
1722 }
7bc3d711 1723 if (has_msr_hv_hypercall) {
9c600a84 1724 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1725 env->msr_hv_guest_os_id);
9c600a84 1726 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1727 env->msr_hv_hypercall);
eab70139 1728 }
2d5aa872 1729 if (cpu->hyperv_vapic) {
9c600a84 1730 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1731 env->msr_hv_vapic);
eab70139 1732 }
3ddcd2ed 1733 if (cpu->hyperv_time) {
9c600a84 1734 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1735 }
f2a53c9e
AS		 1736 if (has_msr_hv_crash) {
1737 int j;
1738
1739 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
9c600a84 1740 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1741 env->msr_hv_crash_params[j]);
1742
9c600a84 1743 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
f2a53c9e
AS		 1744 HV_X64_MSR_CRASH_CTL_NOTIFY);
1745 }
46eb8f98 1746 if (has_msr_hv_runtime) {
9c600a84 1747 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1748 }
866eea9a
AS		 1749 if (cpu->hyperv_synic) {
1750 int j;
1751
9c600a84 1752 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1753 env->msr_hv_synic_control);
9c600a84 1754 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1755 env->msr_hv_synic_version);
9c600a84 1756 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1757 env->msr_hv_synic_evt_page);
9c600a84 1758 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1759 env->msr_hv_synic_msg_page);
1760
1761 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1762 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1763 env->msr_hv_synic_sint[j]);
1764 }
1765 }
ff99aa64
AS		 1766 if (has_msr_hv_stimer) {
1767 int j;
1768
1769 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1770 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1771 env->msr_hv_stimer_config[j]);
1772 }
1773
1774 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1775 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1776 env->msr_hv_stimer_count[j]);
1777 }
1778 }
1eabfce6 1779 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1780 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1781
9c600a84
EH		 1782 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1783 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1784 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1785 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1786 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1787 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1788 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1789 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1790 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1791 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1792 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1793 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1794 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1795 /* The CPU GPs if we write to a bit above the physical limit of
1796 * the host CPU (and KVM emulates that)
1797 */
1798 uint64_t mask = env->mtrr_var[i].mask;
1799 mask &= phys_mask;
1800
9c600a84
EH		 1801 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1802 env->mtrr_var[i].base);
112dad69 1803 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1804 }
1805 }
6bdf863d
JK		 1806
1807 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1808 * kvm_put_msr_feature_control. */
ea643051 1809 }
57780495 1810 if (env->mcg_cap) {
d8da8574 1811 int i;
b9bec74b 1812
9c600a84
EH		 1813 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1814 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1815 if (has_msr_mcg_ext_ctl) {
1816 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1817 }
c34d440a 1818 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1819 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1820 }
1821 }
1a03675d 1822
d71b62a1 1823 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1824 if (ret < 0) {
1825 return ret;
1826 }
05330448 1827
c70b11d1
EH		 1828 if (ret < cpu->kvm_msr_buf->nmsrs) {
1829 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1830 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1831 (uint32_t)e->index, (uint64_t)e->data);
1832 }
1833
9c600a84 1834 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1835 return 0;
05330448
AL		 1836}
1837
1838
1bc22652 1839static int kvm_get_fpu(X86CPU *cpu)
05330448 1840{
1bc22652 1841 CPUX86State *env = &cpu->env;
05330448
AL		 1842 struct kvm_fpu fpu;
1843 int i, ret;
1844
1bc22652 1845 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1846 if (ret < 0) {
05330448 1847 return ret;
b9bec74b 1848 }
05330448
AL		 1849
1850 env->fpstt = (fpu.fsw >> 11) & 7;
1851 env->fpus = fpu.fsw;
1852 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1853 env->fpop = fpu.last_opcode;
1854 env->fpip = fpu.last_ip;
1855 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1856 for (i = 0; i < 8; ++i) {
1857 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1858 }
05330448 1859 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1860 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1861 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1862 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1863 }
05330448
AL		 1864 env->mxcsr = fpu.mxcsr;
1865
1866 return 0;
1867}
1868
1bc22652 1869static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1870{
1bc22652 1871 CPUX86State *env = &cpu->env;
86cd2ea0 1872 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1873 int ret, i;
42cc8fa6 1874 uint16_t cwd, swd, twd;
f1665b21 1875
28143b40 1876 if (!has_xsave) {
1bc22652 1877 return kvm_get_fpu(cpu);
b9bec74b 1878 }
f1665b21 1879
1bc22652 1880 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1881 if (ret < 0) {
f1665b21 1882 return ret;
0f53994f 1883 }
f1665b21 1884
86cd2ea0
EH		 1885 cwd = xsave->legacy.fcw;
1886 swd = xsave->legacy.fsw;
1887 twd = xsave->legacy.ftw;
1888 env->fpop = xsave->legacy.fpop;
f1665b21
SY		 1889 env->fpstt = (swd >> 11) & 7;
1890 env->fpus = swd;
1891 env->fpuc = cwd;
b9bec74b 1892 for (i = 0; i < 8; ++i) {
f1665b21 1893 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1894 }
86cd2ea0
EH		 1895 env->fpip = xsave->legacy.fpip;
1896 env->fpdp = xsave->legacy.fpdp;
1897 env->mxcsr = xsave->legacy.mxcsr;
1898 memcpy(env->fpregs, &xsave->legacy.fpregs,
f1665b21 1899 sizeof env->fpregs);
86cd2ea0
EH		 1900 env->xstate_bv = xsave->header.xstate_bv;
1901 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
79e9ebeb 1902 sizeof env->bnd_regs);
86cd2ea0
EH		 1903 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1904 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
9aecd6f8 1905 sizeof env->opmask_regs);
bee81887 1906
86cd2ea0
EH		 1907 for (i = 0; i < CPU_NB_REGS; i++) {
1908 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1909 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1910 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1911 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1912 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1913 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1914 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1915 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1916 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1917 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1918 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1919 }
1920
9aecd6f8 1921#ifdef TARGET_X86_64
86cd2ea0 1922 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
b7711471 1923 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1924 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
9aecd6f8 1925#endif
f1665b21 1926 return 0;
f1665b21
SY		 1927}
1928
1bc22652 1929static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1930{
1bc22652 1931 CPUX86State *env = &cpu->env;
f1665b21
SY		 1932 int i, ret;
1933 struct kvm_xcrs xcrs;
1934
28143b40 1935 if (!has_xcrs) {
f1665b21 1936 return 0;
b9bec74b 1937 }
f1665b21 1938
1bc22652 1939 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1940 if (ret < 0) {
f1665b21 1941 return ret;
b9bec74b 1942 }
f1665b21 1943
b9bec74b 1944 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1945 /* Only support xcr0 now */
0fd53fec
PB		 1946 if (xcrs.xcrs[i].xcr == 0) {
1947 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1948 break;
1949 }
b9bec74b 1950 }
f1665b21 1951 return 0;
f1665b21
SY		 1952}
1953
1bc22652 1954static int kvm_get_sregs(X86CPU *cpu)
05330448 1955{
1bc22652 1956 CPUX86State *env = &cpu->env;
05330448
AL		 1957 struct kvm_sregs sregs;
1958 uint32_t hflags;
0e607a80 1959 int bit, i, ret;
05330448 1960
1bc22652 1961 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1962 if (ret < 0) {
05330448 1963 return ret;
b9bec74b 1964 }
05330448 1965
0e607a80
JK		 1966 /* There can only be one pending IRQ set in the bitmap at a time, so try
1967 to find it and save its number instead (-1 for none). */
1968 env->interrupt_injected = -1;
1969 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1970 if (sregs.interrupt_bitmap[i]) {
1971 bit = ctz64(sregs.interrupt_bitmap[i]);
1972 env->interrupt_injected = i * 64 + bit;
1973 break;
1974 }
1975 }
05330448
AL		 1976
1977 get_seg(&env->segs[R_CS], &sregs.cs);
1978 get_seg(&env->segs[R_DS], &sregs.ds);
1979 get_seg(&env->segs[R_ES], &sregs.es);
1980 get_seg(&env->segs[R_FS], &sregs.fs);
1981 get_seg(&env->segs[R_GS], &sregs.gs);
1982 get_seg(&env->segs[R_SS], &sregs.ss);
1983
1984 get_seg(&env->tr, &sregs.tr);
1985 get_seg(&env->ldt, &sregs.ldt);
1986
1987 env->idt.limit = sregs.idt.limit;
1988 env->idt.base = sregs.idt.base;
1989 env->gdt.limit = sregs.gdt.limit;
1990 env->gdt.base = sregs.gdt.base;
1991
1992 env->cr[0] = sregs.cr0;
1993 env->cr[2] = sregs.cr2;
1994 env->cr[3] = sregs.cr3;
1995 env->cr[4] = sregs.cr4;
1996
05330448 1997 env->efer = sregs.efer;
cce47516
JK		 1998
1999 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 2000
b9bec74b
JK		 2001#define HFLAG_COPY_MASK \
2002 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
2003 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
2004 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
2005 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 2006
19dc85db
RH		 2007 hflags = env->hflags & HFLAG_COPY_MASK;
2008 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 2009 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
2010 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 2011 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 2012 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 2013
2014 if (env->cr[4] & CR4_OSFXSR_MASK) {
2015 hflags |= HF_OSFXSR_MASK;
2016 }
05330448
AL		 2017
2018 if (env->efer & MSR_EFER_LMA) {
2019 hflags |= HF_LMA_MASK;
2020 }
2021
2022 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
2023 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2024 } else {
2025 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 2026 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 2027 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 2028 (DESC_B_SHIFT - HF_SS32_SHIFT);
2029 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
2030 !(hflags & HF_CS32_MASK)) {
2031 hflags |= HF_ADDSEG_MASK;
2032 } else {
2033 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
2034 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
2035 }
05330448 2036 }
19dc85db 2037 env->hflags = hflags;
05330448
AL		 2038
2039 return 0;
2040}
2041
1bc22652 2042static int kvm_get_msrs(X86CPU *cpu)
05330448 2043{
1bc22652 2044 CPUX86State *env = &cpu->env;
d71b62a1 2045 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2046 int ret, i;
fcc35e7c 2047 uint64_t mtrr_top_bits;
05330448 2048
d71b62a1
EH		 2049 kvm_msr_buf_reset(cpu);
2050
9c600a84
EH		 2051 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2052 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2053 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2054 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2055 if (has_msr_star) {
9c600a84 2056 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2057 }
c3a3a7d3 2058 if (has_msr_hsave_pa) {
9c600a84 2059 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2060 }
c9b8f6b6 2061 if (has_msr_tsc_aux) {
9c600a84 2062 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2063 }
f28558d3 2064 if (has_msr_tsc_adjust) {
9c600a84 2065 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2066 }
aa82ba54 2067 if (has_msr_tsc_deadline) {
9c600a84 2068 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2069 }
21e87c46 2070 if (has_msr_misc_enable) {
9c600a84 2071 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2072 }
fc12d72e 2073 if (has_msr_smbase) {
9c600a84 2074 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2075 }
df67696e 2076 if (has_msr_feature_control) {
9c600a84 2077 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2078 }
79e9ebeb 2079 if (has_msr_bndcfgs) {
9c600a84 2080 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2081 }
18cd2c17 2082 if (has_msr_xss) {
9c600a84 2083 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 2084 }
2085
b8cc45d6
GC		 2086
2087 if (!env->tsc_valid) {
9c600a84 2088 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2089 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2090 }
2091
05330448 2092#ifdef TARGET_X86_64
25d2e361 2093 if (lm_capable_kernel) {
9c600a84
EH		 2094 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2095 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2096 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2097 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2098 }
05330448 2099#endif
9c600a84
EH		 2100 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2101 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2102 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2103 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2104 }
55c911a5 2105 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2106 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2107 }
55c911a5 2108 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2109 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2110 }
0d894367 2111 if (has_msr_architectural_pmu) {
9c600a84
EH		 2112 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2113 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2114 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2115 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2116 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2117 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2118 }
2119 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2120 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2121 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2122 }
2123 }
1a03675d 2124
57780495 2125 if (env->mcg_cap) {
9c600a84
EH		 2126 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2127 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2128 if (has_msr_mcg_ext_ctl) {
2129 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2130 }
b9bec74b 2131 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2132 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2133 }
57780495 2134 }
57780495 2135
1c90ef26 2136 if (has_msr_hv_hypercall) {
9c600a84
EH		 2137 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2138 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2139 }
2d5aa872 2140 if (cpu->hyperv_vapic) {
9c600a84 2141 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2142 }
3ddcd2ed 2143 if (cpu->hyperv_time) {
9c600a84 2144 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2145 }
f2a53c9e
AS		 2146 if (has_msr_hv_crash) {
2147 int j;
2148
2149 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
9c600a84 2150 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2151 }
2152 }
46eb8f98 2153 if (has_msr_hv_runtime) {
9c600a84 2154 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2155 }
866eea9a
AS		 2156 if (cpu->hyperv_synic) {
2157 uint32_t msr;
2158
9c600a84
EH		 2159 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2160 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2161 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2162 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2163 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2164 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2165 }
2166 }
ff99aa64
AS		 2167 if (has_msr_hv_stimer) {
2168 uint32_t msr;
2169
2170 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2171 msr++) {
9c600a84 2172 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2173 }
2174 }
1eabfce6 2175 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2176 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2177 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2178 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2179 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2180 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2181 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2182 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2183 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2184 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2185 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2186 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2187 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2188 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2189 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2190 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2191 }
2192 }
5ef68987 2193
d71b62a1 2194 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2195 if (ret < 0) {
05330448 2196 return ret;
b9bec74b 2197 }
05330448 2198
c70b11d1
EH		 2199 if (ret < cpu->kvm_msr_buf->nmsrs) {
2200 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2201 error_report("error: failed to get MSR 0x%" PRIx32,
2202 (uint32_t)e->index);
2203 }
2204
9c600a84 2205 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2206 /*
2207 * MTRR masks: Each mask consists of 5 parts
2208 * a 10..0: must be zero
2209 * b 11 : valid bit
2210 * c n-1.12: actual mask bits
2211 * d 51..n: reserved must be zero
2212 * e 63.52: reserved must be zero
2213 *
2214 * 'n' is the number of physical bits supported by the CPU and is
2215 * apparently always <= 52. We know our 'n' but don't know what
2216 * the destinations 'n' is; it might be smaller, in which case
2217 * it masks (c) on loading. It might be larger, in which case
2218 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2219 * we're migrating to.
2220 */
2221
2222 if (cpu->fill_mtrr_mask) {
2223 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2224 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2225 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2226 } else {
2227 mtrr_top_bits = 0;
2228 }
2229
05330448 2230 for (i = 0; i < ret; i++) {
0d894367
PB		 2231 uint32_t index = msrs[i].index;
2232 switch (index) {
05330448
AL		 2233 case MSR_IA32_SYSENTER_CS:
2234 env->sysenter_cs = msrs[i].data;
2235 break;
2236 case MSR_IA32_SYSENTER_ESP:
2237 env->sysenter_esp = msrs[i].data;
2238 break;
2239 case MSR_IA32_SYSENTER_EIP:
2240 env->sysenter_eip = msrs[i].data;
2241 break;
0c03266a
JK		 2242 case MSR_PAT:
2243 env->pat = msrs[i].data;
2244 break;
05330448
AL		 2245 case MSR_STAR:
2246 env->star = msrs[i].data;
2247 break;
2248#ifdef TARGET_X86_64
2249 case MSR_CSTAR:
2250 env->cstar = msrs[i].data;
2251 break;
2252 case MSR_KERNELGSBASE:
2253 env->kernelgsbase = msrs[i].data;
2254 break;
2255 case MSR_FMASK:
2256 env->fmask = msrs[i].data;
2257 break;
2258 case MSR_LSTAR:
2259 env->lstar = msrs[i].data;
2260 break;
2261#endif
2262 case MSR_IA32_TSC:
2263 env->tsc = msrs[i].data;
2264 break;
c9b8f6b6
AS		 2265 case MSR_TSC_AUX:
2266 env->tsc_aux = msrs[i].data;
2267 break;
f28558d3
WA		 2268 case MSR_TSC_ADJUST:
2269 env->tsc_adjust = msrs[i].data;
2270 break;
aa82ba54
LJ		 2271 case MSR_IA32_TSCDEADLINE:
2272 env->tsc_deadline = msrs[i].data;
2273 break;
aa851e36
MT		 2274 case MSR_VM_HSAVE_PA:
2275 env->vm_hsave = msrs[i].data;
2276 break;
1a03675d
GC		 2277 case MSR_KVM_SYSTEM_TIME:
2278 env->system_time_msr = msrs[i].data;
2279 break;
2280 case MSR_KVM_WALL_CLOCK:
2281 env->wall_clock_msr = msrs[i].data;
2282 break;
57780495
MT		 2283 case MSR_MCG_STATUS:
2284 env->mcg_status = msrs[i].data;
2285 break;
2286 case MSR_MCG_CTL:
2287 env->mcg_ctl = msrs[i].data;
2288 break;
87f8b626
AR		 2289 case MSR_MCG_EXT_CTL:
2290 env->mcg_ext_ctl = msrs[i].data;
2291 break;
21e87c46
AK		 2292 case MSR_IA32_MISC_ENABLE:
2293 env->msr_ia32_misc_enable = msrs[i].data;
2294 break;
fc12d72e
PB		 2295 case MSR_IA32_SMBASE:
2296 env->smbase = msrs[i].data;
2297 break;
0779caeb
ACL		 2298 case MSR_IA32_FEATURE_CONTROL:
2299 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2300 break;
79e9ebeb
LJ		 2301 case MSR_IA32_BNDCFGS:
2302 env->msr_bndcfgs = msrs[i].data;
2303 break;
18cd2c17
WL		 2304 case MSR_IA32_XSS:
2305 env->xss = msrs[i].data;
2306 break;
57780495 2307 default:
57780495
MT		 2308 if (msrs[i].index >= MSR_MC0_CTL &&
2309 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2310 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2311 }
d8da8574 2312 break;
f6584ee2
GN		 2313 case MSR_KVM_ASYNC_PF_EN:
2314 env->async_pf_en_msr = msrs[i].data;
2315 break;
bc9a839d
MT		 2316 case MSR_KVM_PV_EOI_EN:
2317 env->pv_eoi_en_msr = msrs[i].data;
2318 break;
917367aa
MT		 2319 case MSR_KVM_STEAL_TIME:
2320 env->steal_time_msr = msrs[i].data;
2321 break;
0d894367
PB		 2322 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2323 env->msr_fixed_ctr_ctrl = msrs[i].data;
2324 break;
2325 case MSR_CORE_PERF_GLOBAL_CTRL:
2326 env->msr_global_ctrl = msrs[i].data;
2327 break;
2328 case MSR_CORE_PERF_GLOBAL_STATUS:
2329 env->msr_global_status = msrs[i].data;
2330 break;
2331 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2332 env->msr_global_ovf_ctrl = msrs[i].data;
2333 break;
2334 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2335 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2336 break;
2337 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2338 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2339 break;
2340 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2341 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2342 break;
1c90ef26
VR		 2343 case HV_X64_MSR_HYPERCALL:
2344 env->msr_hv_hypercall = msrs[i].data;
2345 break;
2346 case HV_X64_MSR_GUEST_OS_ID:
2347 env->msr_hv_guest_os_id = msrs[i].data;
2348 break;
5ef68987
VR		 2349 case HV_X64_MSR_APIC_ASSIST_PAGE:
2350 env->msr_hv_vapic = msrs[i].data;
2351 break;
48a5f3bc
VR		 2352 case HV_X64_MSR_REFERENCE_TSC:
2353 env->msr_hv_tsc = msrs[i].data;
2354 break;
f2a53c9e
AS		 2355 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2356 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2357 break;
46eb8f98
AS		 2358 case HV_X64_MSR_VP_RUNTIME:
2359 env->msr_hv_runtime = msrs[i].data;
2360 break;
866eea9a
AS		 2361 case HV_X64_MSR_SCONTROL:
2362 env->msr_hv_synic_control = msrs[i].data;
2363 break;
2364 case HV_X64_MSR_SVERSION:
2365 env->msr_hv_synic_version = msrs[i].data;
2366 break;
2367 case HV_X64_MSR_SIEFP:
2368 env->msr_hv_synic_evt_page = msrs[i].data;
2369 break;
2370 case HV_X64_MSR_SIMP:
2371 env->msr_hv_synic_msg_page = msrs[i].data;
2372 break;
2373 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2374 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2375 break;
2376 case HV_X64_MSR_STIMER0_CONFIG:
2377 case HV_X64_MSR_STIMER1_CONFIG:
2378 case HV_X64_MSR_STIMER2_CONFIG:
2379 case HV_X64_MSR_STIMER3_CONFIG:
2380 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2381 msrs[i].data;
2382 break;
2383 case HV_X64_MSR_STIMER0_COUNT:
2384 case HV_X64_MSR_STIMER1_COUNT:
2385 case HV_X64_MSR_STIMER2_COUNT:
2386 case HV_X64_MSR_STIMER3_COUNT:
2387 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2388 msrs[i].data;
866eea9a 2389 break;
d1ae67f6
AW		 2390 case MSR_MTRRdefType:
2391 env->mtrr_deftype = msrs[i].data;
2392 break;
2393 case MSR_MTRRfix64K_00000:
2394 env->mtrr_fixed[0] = msrs[i].data;
2395 break;
2396 case MSR_MTRRfix16K_80000:
2397 env->mtrr_fixed[1] = msrs[i].data;
2398 break;
2399 case MSR_MTRRfix16K_A0000:
2400 env->mtrr_fixed[2] = msrs[i].data;
2401 break;
2402 case MSR_MTRRfix4K_C0000:
2403 env->mtrr_fixed[3] = msrs[i].data;
2404 break;
2405 case MSR_MTRRfix4K_C8000:
2406 env->mtrr_fixed[4] = msrs[i].data;
2407 break;
2408 case MSR_MTRRfix4K_D0000:
2409 env->mtrr_fixed[5] = msrs[i].data;
2410 break;
2411 case MSR_MTRRfix4K_D8000:
2412 env->mtrr_fixed[6] = msrs[i].data;
2413 break;
2414 case MSR_MTRRfix4K_E0000:
2415 env->mtrr_fixed[7] = msrs[i].data;
2416 break;
2417 case MSR_MTRRfix4K_E8000:
2418 env->mtrr_fixed[8] = msrs[i].data;
2419 break;
2420 case MSR_MTRRfix4K_F0000:
2421 env->mtrr_fixed[9] = msrs[i].data;
2422 break;
2423 case MSR_MTRRfix4K_F8000:
2424 env->mtrr_fixed[10] = msrs[i].data;
2425 break;
2426 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2427 if (index & 1) {
fcc35e7c
DDAG		 2428 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2429 mtrr_top_bits;
d1ae67f6
AW		 2430 } else {
2431 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2432 }
2433 break;
05330448
AL		 2434 }
2435 }
2436
2437 return 0;
2438}
2439
1bc22652 2440static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2441{
1bc22652 2442 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2443
1bc22652 2444 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2445}
2446
23d02d9b 2447static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2448{
259186a7 2449 CPUState *cs = CPU(cpu);
23d02d9b 2450 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2451 struct kvm_mp_state mp_state;
2452 int ret;
2453
259186a7 2454 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2455 if (ret < 0) {
2456 return ret;
2457 }
2458 env->mp_state = mp_state.mp_state;
c14750e8 2459 if (kvm_irqchip_in_kernel()) {
259186a7 2460 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2461 }
9bdbe550
HB		 2462 return 0;
2463}
2464
1bc22652 2465static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2466{
02e51483 2467 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2468 struct kvm_lapic_state kapic;
2469 int ret;
2470
3d4b2649 2471 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2472 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2473 if (ret < 0) {
2474 return ret;
2475 }
2476
2477 kvm_get_apic_state(apic, &kapic);
2478 }
2479 return 0;
2480}
2481
1bc22652 2482static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2483{
fc12d72e 2484 CPUState *cs = CPU(cpu);
1bc22652 2485 CPUX86State *env = &cpu->env;
076796f8 2486 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2487
2488 if (!kvm_has_vcpu_events()) {
2489 return 0;
2490 }
2491
31827373
JK		 2492 events.exception.injected = (env->exception_injected >= 0);
2493 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2494 events.exception.has_error_code = env->has_error_code;
2495 events.exception.error_code = env->error_code;
7e680753 2496 events.exception.pad = 0;
a0fb002c
JK		 2497
2498 events.interrupt.injected = (env->interrupt_injected >= 0);
2499 events.interrupt.nr = env->interrupt_injected;
2500 events.interrupt.soft = env->soft_interrupt;
2501
2502 events.nmi.injected = env->nmi_injected;
2503 events.nmi.pending = env->nmi_pending;
2504 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2505 events.nmi.pad = 0;
a0fb002c
JK		 2506
2507 events.sipi_vector = env->sipi_vector;
68c6efe0 2508 events.flags = 0;
a0fb002c 2509
fc12d72e
PB		 2510 if (has_msr_smbase) {
2511 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2512 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2513 if (kvm_irqchip_in_kernel()) {
2514 /* As soon as these are moved to the kernel, remove them
2515 * from cs->interrupt_request.
2516 */
2517 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2518 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2519 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2520 } else {
2521 /* Keep these in cs->interrupt_request. */
2522 events.smi.pending = 0;
2523 events.smi.latched_init = 0;
2524 }
fc3a1fd7
DDAG		 2525 /* Stop SMI delivery on old machine types to avoid a reboot
2526 * on an inward migration of an old VM.
2527 */
2528 if (!cpu->kvm_no_smi_migration) {
2529 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2530 }
fc12d72e
PB		 2531 }
2532
ea643051
JK		 2533 if (level >= KVM_PUT_RESET_STATE) {
2534 events.flags |=
2535 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2536 }
aee028b9 2537
1bc22652 2538 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2539}
2540
1bc22652 2541static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2542{
1bc22652 2543 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2544 struct kvm_vcpu_events events;
2545 int ret;
2546
2547 if (!kvm_has_vcpu_events()) {
2548 return 0;
2549 }
2550
fc12d72e 2551 memset(&events, 0, sizeof(events));
1bc22652 2552 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2553 if (ret < 0) {
2554 return ret;
2555 }
31827373 2556 env->exception_injected =
a0fb002c
JK		 2557 events.exception.injected ? events.exception.nr : -1;
2558 env->has_error_code = events.exception.has_error_code;
2559 env->error_code = events.exception.error_code;
2560
2561 env->interrupt_injected =
2562 events.interrupt.injected ? events.interrupt.nr : -1;
2563 env->soft_interrupt = events.interrupt.soft;
2564
2565 env->nmi_injected = events.nmi.injected;
2566 env->nmi_pending = events.nmi.pending;
2567 if (events.nmi.masked) {
2568 env->hflags2 |= HF2_NMI_MASK;
2569 } else {
2570 env->hflags2 &= ~HF2_NMI_MASK;
2571 }
2572
fc12d72e
PB		 2573 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2574 if (events.smi.smm) {
2575 env->hflags |= HF_SMM_MASK;
2576 } else {
2577 env->hflags &= ~HF_SMM_MASK;
2578 }
2579 if (events.smi.pending) {
2580 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2581 } else {
2582 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2583 }
2584 if (events.smi.smm_inside_nmi) {
2585 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2586 } else {
2587 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2588 }
2589 if (events.smi.latched_init) {
2590 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2591 } else {
2592 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2593 }
2594 }
2595
a0fb002c 2596 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2597
2598 return 0;
2599}
2600
1bc22652 2601static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2602{
ed2803da 2603 CPUState *cs = CPU(cpu);
1bc22652 2604 CPUX86State *env = &cpu->env;
b0b1d690 2605 int ret = 0;
b0b1d690
JK		 2606 unsigned long reinject_trap = 0;
2607
2608 if (!kvm_has_vcpu_events()) {
2609 if (env->exception_injected == 1) {
2610 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2611 } else if (env->exception_injected == 3) {
2612 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2613 }
2614 env->exception_injected = -1;
2615 }
2616
2617 /*
2618 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2619 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2620 * by updating the debug state once again if single-stepping is on.
2621 * Another reason to call kvm_update_guest_debug here is a pending debug
2622 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2623 * reinject them via SET_GUEST_DEBUG.
2624 */
2625 if (reinject_trap ||
ed2803da 2626 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2627 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2628 }
b0b1d690
JK		 2629 return ret;
2630}
2631
1bc22652 2632static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2633{
1bc22652 2634 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2635 struct kvm_debugregs dbgregs;
2636 int i;
2637
2638 if (!kvm_has_debugregs()) {
2639 return 0;
2640 }
2641
2642 for (i = 0; i < 4; i++) {
2643 dbgregs.db[i] = env->dr[i];
2644 }
2645 dbgregs.dr6 = env->dr[6];
2646 dbgregs.dr7 = env->dr[7];
2647 dbgregs.flags = 0;
2648
1bc22652 2649 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2650}
2651
1bc22652 2652static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2653{
1bc22652 2654 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2655 struct kvm_debugregs dbgregs;
2656 int i, ret;
2657
2658 if (!kvm_has_debugregs()) {
2659 return 0;
2660 }
2661
1bc22652 2662 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2663 if (ret < 0) {
b9bec74b 2664 return ret;
ff44f1a3
JK		 2665 }
2666 for (i = 0; i < 4; i++) {
2667 env->dr[i] = dbgregs.db[i];
2668 }
2669 env->dr[4] = env->dr[6] = dbgregs.dr6;
2670 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2671
2672 return 0;
2673}
2674
20d695a9 2675int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2676{
20d695a9 2677 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2678 int ret;
2679
2fa45344 2680 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2681
48e1a45c 2682 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2683 ret = kvm_put_msr_feature_control(x86_cpu);
2684 if (ret < 0) {
2685 return ret;
2686 }
2687 }
2688
36f96c4b
HZ		 2689 if (level == KVM_PUT_FULL_STATE) {
2690 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2691 * because TSC frequency mismatch shouldn't abort migration,
2692 * unless the user explicitly asked for a more strict TSC
2693 * setting (e.g. using an explicit "tsc-freq" option).
2694 */
2695 kvm_arch_set_tsc_khz(cpu);
2696 }
2697
1bc22652 2698 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2699 if (ret < 0) {
05330448 2700 return ret;
b9bec74b 2701 }
1bc22652 2702 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2703 if (ret < 0) {
f1665b21 2704 return ret;
b9bec74b 2705 }
1bc22652 2706 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2707 if (ret < 0) {
05330448 2708 return ret;
b9bec74b 2709 }
1bc22652 2710 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2711 if (ret < 0) {
05330448 2712 return ret;
b9bec74b 2713 }
ab443475 2714 /* must be before kvm_put_msrs */
1bc22652 2715 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2716 if (ret < 0) {
2717 return ret;
2718 }
1bc22652 2719 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2720 if (ret < 0) {
05330448 2721 return ret;
b9bec74b 2722 }
ea643051 2723 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2724 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2725 if (ret < 0) {
680c1c6f
JK		 2726 return ret;
2727 }
ea643051 2728 }
7477cd38
MT		 2729
2730 ret = kvm_put_tscdeadline_msr(x86_cpu);
2731 if (ret < 0) {
2732 return ret;
2733 }
2734
1bc22652 2735 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2736 if (ret < 0) {
a0fb002c 2737 return ret;
b9bec74b 2738 }
1bc22652 2739 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2740 if (ret < 0) {
b0b1d690 2741 return ret;
b9bec74b 2742 }
b0b1d690 2743 /* must be last */
1bc22652 2744 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2745 if (ret < 0) {
ff44f1a3 2746 return ret;
b9bec74b 2747 }
05330448
AL		 2748 return 0;
2749}
2750
20d695a9 2751int kvm_arch_get_registers(CPUState *cs)
05330448 2752{
20d695a9 2753 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2754 int ret;
2755
20d695a9 2756 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2757
1bc22652 2758 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2759 if (ret < 0) {
f4f1110e 2760 goto out;
b9bec74b 2761 }
1bc22652 2762 ret = kvm_get_xsave(cpu);
b9bec74b 2763 if (ret < 0) {
f4f1110e 2764 goto out;
b9bec74b 2765 }
1bc22652 2766 ret = kvm_get_xcrs(cpu);
b9bec74b 2767 if (ret < 0) {
f4f1110e 2768 goto out;
b9bec74b 2769 }
1bc22652 2770 ret = kvm_get_sregs(cpu);
b9bec74b 2771 if (ret < 0) {
f4f1110e 2772 goto out;
b9bec74b 2773 }
1bc22652 2774 ret = kvm_get_msrs(cpu);
b9bec74b 2775 if (ret < 0) {
f4f1110e 2776 goto out;
b9bec74b 2777 }
23d02d9b 2778 ret = kvm_get_mp_state(cpu);
b9bec74b 2779 if (ret < 0) {
f4f1110e 2780 goto out;
b9bec74b 2781 }
1bc22652 2782 ret = kvm_get_apic(cpu);
680c1c6f 2783 if (ret < 0) {
f4f1110e 2784 goto out;
680c1c6f 2785 }
1bc22652 2786 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2787 if (ret < 0) {
f4f1110e 2788 goto out;
b9bec74b 2789 }
1bc22652 2790 ret = kvm_get_debugregs(cpu);
b9bec74b 2791 if (ret < 0) {
f4f1110e 2792 goto out;
b9bec74b 2793 }
f4f1110e
RH		 2794 ret = 0;
2795 out:
2796 cpu_sync_bndcs_hflags(&cpu->env);
2797 return ret;
05330448
AL		 2798}
2799
20d695a9 2800void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2801{
20d695a9
AF		 2802 X86CPU *x86_cpu = X86_CPU(cpu);
2803 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2804 int ret;
2805
276ce815 2806 /* Inject NMI */
fc12d72e
PB		 2807 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2808 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2809 qemu_mutex_lock_iothread();
2810 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2811 qemu_mutex_unlock_iothread();
2812 DPRINTF("injected NMI\n");
2813 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2814 if (ret < 0) {
2815 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2816 strerror(-ret));
2817 }
2818 }
2819 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2820 qemu_mutex_lock_iothread();
2821 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2822 qemu_mutex_unlock_iothread();
2823 DPRINTF("injected SMI\n");
2824 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2825 if (ret < 0) {
2826 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2827 strerror(-ret));
2828 }
ce377af3 2829 }
276ce815
LJ		 2830 }
2831
15eafc2e 2832 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2833 qemu_mutex_lock_iothread();
2834 }
2835
e0723c45
PB		 2836 /* Force the VCPU out of its inner loop to process any INIT requests
2837 * or (for userspace APIC, but it is cheap to combine the checks here)
2838 * pending TPR access reports.
2839 */
2840 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2841 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2842 !(env->hflags & HF_SMM_MASK)) {
2843 cpu->exit_request = 1;
2844 }
2845 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2846 cpu->exit_request = 1;
2847 }
e0723c45 2848 }
05330448 2849
15eafc2e 2850 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2851 /* Try to inject an interrupt if the guest can accept it */
2852 if (run->ready_for_interrupt_injection &&
259186a7 2853 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2854 (env->eflags & IF_MASK)) {
2855 int irq;
2856
259186a7 2857 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2858 irq = cpu_get_pic_interrupt(env);
2859 if (irq >= 0) {
2860 struct kvm_interrupt intr;
2861
2862 intr.irq = irq;
db1669bc 2863 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2864 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2865 if (ret < 0) {
2866 fprintf(stderr,
2867 "KVM: injection failed, interrupt lost (%s)\n",
2868 strerror(-ret));
2869 }
db1669bc
JK		 2870 }
2871 }
05330448 2872
db1669bc
JK		 2873 /* If we have an interrupt but the guest is not ready to receive an
2874 * interrupt, request an interrupt window exit. This will
2875 * cause a return to userspace as soon as the guest is ready to
2876 * receive interrupts. */
259186a7 2877 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2878 run->request_interrupt_window = 1;
2879 } else {
2880 run->request_interrupt_window = 0;
2881 }
2882
2883 DPRINTF("setting tpr\n");
02e51483 2884 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2885
2886 qemu_mutex_unlock_iothread();
db1669bc 2887 }
05330448
AL		 2888}
2889
4c663752 2890MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2891{
20d695a9
AF		 2892 X86CPU *x86_cpu = X86_CPU(cpu);
2893 CPUX86State *env = &x86_cpu->env;
2894
fc12d72e
PB		 2895 if (run->flags & KVM_RUN_X86_SMM) {
2896 env->hflags |= HF_SMM_MASK;
2897 } else {
f5c052b9 2898 env->hflags &= ~HF_SMM_MASK;
fc12d72e 2899 }
b9bec74b 2900 if (run->if_flag) {
05330448 2901 env->eflags |= IF_MASK;
b9bec74b 2902 } else {
05330448 2903 env->eflags &= ~IF_MASK;
b9bec74b 2904 }
4b8523ee
JK		 2905
2906 /* We need to protect the apic state against concurrent accesses from
2907 * different threads in case the userspace irqchip is used. */
2908 if (!kvm_irqchip_in_kernel()) {
2909 qemu_mutex_lock_iothread();
2910 }
02e51483
CF		 2911 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2912 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2913 if (!kvm_irqchip_in_kernel()) {
2914 qemu_mutex_unlock_iothread();
2915 }
f794aa4a 2916 return cpu_get_mem_attrs(env);
05330448
AL		 2917}
2918
20d695a9 2919int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2920{
20d695a9
AF		 2921 X86CPU *cpu = X86_CPU(cs);
2922 CPUX86State *env = &cpu->env;
232fc23b 2923
259186a7 2924 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2925 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2926 assert(env->mcg_cap);
2927
259186a7 2928 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2929
dd1750d7 2930 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2931
2932 if (env->exception_injected == EXCP08_DBLE) {
2933 /* this means triple fault */
cf83f140 2934 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 2935 cs->exit_request = 1;
ab443475
JK		 2936 return 0;
2937 }
2938 env->exception_injected = EXCP12_MCHK;
2939 env->has_error_code = 0;
2940
259186a7 2941 cs->halted = 0;
ab443475
JK		 2942 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2943 env->mp_state = KVM_MP_STATE_RUNNABLE;
2944 }
2945 }
2946
fc12d72e
PB		 2947 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2948 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2949 kvm_cpu_synchronize_state(cs);
2950 do_cpu_init(cpu);
2951 }
2952
db1669bc
JK		 2953 if (kvm_irqchip_in_kernel()) {
2954 return 0;
2955 }
2956
259186a7
AF		 2957 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2958 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2959 apic_poll_irq(cpu->apic_state);
5d62c43a 2960 }
259186a7 2961 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2962 (env->eflags & IF_MASK)) ||
259186a7
AF		 2963 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2964 cs->halted = 0;
6792a57b 2965 }
259186a7 2966 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2967 kvm_cpu_synchronize_state(cs);
232fc23b 2968 do_cpu_sipi(cpu);
0af691d7 2969 }
259186a7
AF		 2970 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2971 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2972 kvm_cpu_synchronize_state(cs);
02e51483 2973 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2974 env->tpr_access_type);
2975 }
0af691d7 2976
259186a7 2977 return cs->halted;
0af691d7
MT		 2978}
2979
839b5630 2980static int kvm_handle_halt(X86CPU *cpu)
05330448 2981{
259186a7 2982 CPUState *cs = CPU(cpu);
839b5630
AF		 2983 CPUX86State *env = &cpu->env;
2984
259186a7 2985 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2986 (env->eflags & IF_MASK)) &&
259186a7
AF		 2987 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2988 cs->halted = 1;
bb4ea393 2989 return EXCP_HLT;
05330448
AL		 2990 }
2991
bb4ea393 2992 return 0;
05330448
AL		 2993}
2994
f7575c96 2995static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2996{
f7575c96
AF		 2997 CPUState *cs = CPU(cpu);
2998 struct kvm_run *run = cs->kvm_run;
d362e757 2999
02e51483 3000 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3001 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3002 : TPR_ACCESS_READ);
3003 return 1;
3004}
3005
f17ec444 3006int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3007{
38972938 3008 static const uint8_t int3 = 0xcc;
64bf3f4e 3009
f17ec444
AF		 3010 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3011 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3012 return -EINVAL;
b9bec74b 3013 }
e22a25c9
AL		 3014 return 0;
3015}
3016
f17ec444 3017int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3018{
3019 uint8_t int3;
3020
f17ec444
AF		 3021 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3022 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3023 return -EINVAL;
b9bec74b 3024 }
e22a25c9
AL		 3025 return 0;
3026}
3027
3028static struct {
3029 target_ulong addr;
3030 int len;
3031 int type;
3032} hw_breakpoint[4];
3033
3034static int nb_hw_breakpoint;
3035
3036static int find_hw_breakpoint(target_ulong addr, int len, int type)
3037{
3038 int n;
3039
b9bec74b 3040 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3041 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3042 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3043 return n;
b9bec74b
JK		 3044 }
3045 }
e22a25c9
AL		 3046 return -1;
3047}
3048
3049int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3050 target_ulong len, int type)
3051{
3052 switch (type) {
3053 case GDB_BREAKPOINT_HW:
3054 len = 1;
3055 break;
3056 case GDB_WATCHPOINT_WRITE:
3057 case GDB_WATCHPOINT_ACCESS:
3058 switch (len) {
3059 case 1:
3060 break;
3061 case 2:
3062 case 4:
3063 case 8:
b9bec74b 3064 if (addr & (len - 1)) {
e22a25c9 3065 return -EINVAL;
b9bec74b 3066 }
e22a25c9
AL		 3067 break;
3068 default:
3069 return -EINVAL;
3070 }
3071 break;
3072 default:
3073 return -ENOSYS;
3074 }
3075
b9bec74b 3076 if (nb_hw_breakpoint == 4) {
e22a25c9 3077 return -ENOBUFS;
b9bec74b
JK		 3078 }
3079 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3080 return -EEXIST;
b9bec74b 3081 }
e22a25c9
AL		 3082 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3083 hw_breakpoint[nb_hw_breakpoint].len = len;
3084 hw_breakpoint[nb_hw_breakpoint].type = type;
3085 nb_hw_breakpoint++;
3086
3087 return 0;
3088}
3089
3090int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3091 target_ulong len, int type)
3092{
3093 int n;
3094
3095 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3096 if (n < 0) {
e22a25c9 3097 return -ENOENT;
b9bec74b 3098 }
e22a25c9
AL		 3099 nb_hw_breakpoint--;
3100 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3101
3102 return 0;
3103}
3104
3105void kvm_arch_remove_all_hw_breakpoints(void)
3106{
3107 nb_hw_breakpoint = 0;
3108}
3109
3110static CPUWatchpoint hw_watchpoint;
3111
a60f24b5 3112static int kvm_handle_debug(X86CPU *cpu,
48405526 3113 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3114{
ed2803da 3115 CPUState *cs = CPU(cpu);
a60f24b5 3116 CPUX86State *env = &cpu->env;
f2574737 3117 int ret = 0;
e22a25c9
AL		 3118 int n;
3119
3120 if (arch_info->exception == 1) {
3121 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3122 if (cs->singlestep_enabled) {
f2574737 3123 ret = EXCP_DEBUG;
b9bec74b 3124 }
e22a25c9 3125 } else {
b9bec74b
JK		 3126 for (n = 0; n < 4; n++) {
3127 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3128 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3129 case 0x0:
f2574737 3130 ret = EXCP_DEBUG;
e22a25c9
AL		 3131 break;
3132 case 0x1:
f2574737 3133 ret = EXCP_DEBUG;
ff4700b0 3134 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3135 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3136 hw_watchpoint.flags = BP_MEM_WRITE;
3137 break;
3138 case 0x3:
f2574737 3139 ret = EXCP_DEBUG;
ff4700b0 3140 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3141 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3142 hw_watchpoint.flags = BP_MEM_ACCESS;
3143 break;
3144 }
b9bec74b
JK		 3145 }
3146 }
e22a25c9 3147 }
ff4700b0 3148 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3149 ret = EXCP_DEBUG;
b9bec74b 3150 }
f2574737 3151 if (ret == 0) {
ff4700b0 3152 cpu_synchronize_state(cs);
48405526 3153 assert(env->exception_injected == -1);
b0b1d690 3154
f2574737 3155 /* pass to guest */
48405526
BS		 3156 env->exception_injected = arch_info->exception;
3157 env->has_error_code = 0;
b0b1d690 3158 }
e22a25c9 3159
f2574737 3160 return ret;
e22a25c9
AL		 3161}
3162
20d695a9 3163void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3164{
3165 const uint8_t type_code[] = {
3166 [GDB_BREAKPOINT_HW] = 0x0,
3167 [GDB_WATCHPOINT_WRITE] = 0x1,
3168 [GDB_WATCHPOINT_ACCESS] = 0x3
3169 };
3170 const uint8_t len_code[] = {
3171 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3172 };
3173 int n;
3174
a60f24b5 3175 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3176 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3177 }
e22a25c9
AL		 3178 if (nb_hw_breakpoint > 0) {
3179 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3180 dbg->arch.debugreg[7] = 0x0600;
3181 for (n = 0; n < nb_hw_breakpoint; n++) {
3182 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3183 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3184 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3185 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3186 }
3187 }
3188}
4513d923 3189
2a4dac83
JK		 3190static bool host_supports_vmx(void)
3191{
3192 uint32_t ecx, unused;
3193
3194 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3195 return ecx & CPUID_EXT_VMX;
3196}
3197
3198#define VMX_INVALID_GUEST_STATE 0x80000021
3199
20d695a9 3200int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3201{
20d695a9 3202 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3203 uint64_t code;
3204 int ret;
3205
3206 switch (run->exit_reason) {
3207 case KVM_EXIT_HLT:
3208 DPRINTF("handle_hlt\n");
4b8523ee 3209 qemu_mutex_lock_iothread();
839b5630 3210 ret = kvm_handle_halt(cpu);
4b8523ee 3211 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3212 break;
3213 case KVM_EXIT_SET_TPR:
3214 ret = 0;
3215 break;
d362e757 3216 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3217 qemu_mutex_lock_iothread();
f7575c96 3218 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3219 qemu_mutex_unlock_iothread();
d362e757 3220 break;
2a4dac83
JK		 3221 case KVM_EXIT_FAIL_ENTRY:
3222 code = run->fail_entry.hardware_entry_failure_reason;
3223 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3224 code);
3225 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3226 fprintf(stderr,
12619721 3227 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3228 "unrestricted mode\n"
3229 "support, the failure can be most likely due to the guest "
3230 "entering an invalid\n"
3231 "state for Intel VT. For example, the guest maybe running "
3232 "in big real mode\n"
3233 "which is not supported on less recent Intel processors."
3234 "\n\n");
3235 }
3236 ret = -1;
3237 break;
3238 case KVM_EXIT_EXCEPTION:
3239 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3240 run->ex.exception, run->ex.error_code);
3241 ret = -1;
3242 break;
f2574737
JK		 3243 case KVM_EXIT_DEBUG:
3244 DPRINTF("kvm_exit_debug\n");
4b8523ee 3245 qemu_mutex_lock_iothread();
a60f24b5 3246 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3247 qemu_mutex_unlock_iothread();
f2574737 3248 break;
50efe82c
AS		 3249 case KVM_EXIT_HYPERV:
3250 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3251 break;
15eafc2e
PB		 3252 case KVM_EXIT_IOAPIC_EOI:
3253 ioapic_eoi_broadcast(run->eoi.vector);
3254 ret = 0;
3255 break;
2a4dac83
JK		 3256 default:
3257 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3258 ret = -1;
3259 break;
3260 }
3261
3262 return ret;
3263}
3264
20d695a9 3265bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3266{
20d695a9
AF		 3267 X86CPU *cpu = X86_CPU(cs);
3268 CPUX86State *env = &cpu->env;
3269
dd1750d7 3270 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3271 return !(env->cr[0] & CR0_PE_MASK) ||
3272 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3273}
84b058d7
JK		 3274
3275void kvm_arch_init_irq_routing(KVMState *s)
3276{
3277 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3278 /* If kernel can't do irq routing, interrupt source
3279 * override 0->2 cannot be set up as required by HPET.
3280 * So we have to disable it.
3281 */
3282 no_hpet = 1;
3283 }
cc7e0ddf 3284 /* We know at this point that we're using the in-kernel
614e41bc 3285 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3286 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3287 */
614e41bc 3288 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3289 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3290
3291 if (kvm_irqchip_is_split()) {
3292 int i;
3293
3294 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3295 MSI routes for signaling interrupts to the local apics. */
3296 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3297 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3298 error_report("Could not enable split IRQ mode.");
3299 exit(1);
3300 }
3301 }
3302 }
3303}
3304
3305int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3306{
3307 int ret;
3308 if (machine_kernel_irqchip_split(ms)) {
3309 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3310 if (ret) {
df3c286c 3311 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3312 strerror(-ret));
3313 exit(1);
3314 } else {
3315 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3316 kvm_split_irqchip = true;
3317 return 1;
3318 }
3319 } else {
3320 return 0;
3321 }
84b058d7 3322}
b139bd30
JK		 3323
3324/* Classic KVM device assignment interface. Will remain x86 only. */
3325int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3326 uint32_t flags, uint32_t *dev_id)
3327{
3328 struct kvm_assigned_pci_dev dev_data = {
3329 .segnr = dev_addr->domain,
3330 .busnr = dev_addr->bus,
3331 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3332 .flags = flags,
3333 };
3334 int ret;
3335
3336 dev_data.assigned_dev_id =
3337 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3338
3339 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3340 if (ret < 0) {
3341 return ret;
3342 }
3343
3344 *dev_id = dev_data.assigned_dev_id;
3345
3346 return 0;
3347}
3348
3349int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3350{
3351 struct kvm_assigned_pci_dev dev_data = {
3352 .assigned_dev_id = dev_id,
3353 };
3354
3355 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3356}
3357
3358static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3359 uint32_t irq_type, uint32_t guest_irq)
3360{
3361 struct kvm_assigned_irq assigned_irq = {
3362 .assigned_dev_id = dev_id,
3363 .guest_irq = guest_irq,
3364 .flags = irq_type,
3365 };
3366
3367 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3368 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3369 } else {
3370 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3371 }
3372}
3373
3374int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3375 uint32_t guest_irq)
3376{
3377 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3378 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3379
3380 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3381}
3382
3383int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3384{
3385 struct kvm_assigned_pci_dev dev_data = {
3386 .assigned_dev_id = dev_id,
3387 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3388 };
3389
3390 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3391}
3392
3393static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3394 uint32_t type)
3395{
3396 struct kvm_assigned_irq assigned_irq = {
3397 .assigned_dev_id = dev_id,
3398 .flags = type,
3399 };
3400
3401 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3402}
3403
3404int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3405{
3406 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3407 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3408}
3409
3410int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3411{
3412 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3413 KVM_DEV_IRQ_GUEST_MSI, virq);
3414}
3415
3416int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3417{
3418 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3419 KVM_DEV_IRQ_HOST_MSI);
3420}
3421
3422bool kvm_device_msix_supported(KVMState *s)
3423{
3424 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3425 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3426 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3427}
3428
3429int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3430 uint32_t nr_vectors)
3431{
3432 struct kvm_assigned_msix_nr msix_nr = {
3433 .assigned_dev_id = dev_id,
3434 .entry_nr = nr_vectors,
3435 };
3436
3437 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3438}
3439
3440int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3441 int virq)
3442{
3443 struct kvm_assigned_msix_entry msix_entry = {
3444 .assigned_dev_id = dev_id,
3445 .gsi = virq,
3446 .entry = vector,
3447 };
3448
3449 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3450}
3451
3452int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3453{
3454 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3455 KVM_DEV_IRQ_GUEST_MSIX, 0);
3456}
3457
3458int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3459{
3460 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3461 KVM_DEV_IRQ_HOST_MSIX);
3462}
9e03a040
FB		 3463
3464int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3465 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3466{
8b5ed7df
PX		 3467 X86IOMMUState *iommu = x86_iommu_get_default();
3468
3469 if (iommu) {
3470 int ret;
3471 MSIMessage src, dst;
3472 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3473
3474 src.address = route->u.msi.address_hi;
3475 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3476 src.address |= route->u.msi.address_lo;
3477 src.data = route->u.msi.data;
3478
3479 ret = class->int_remap(iommu, &src, &dst, dev ? \
3480 pci_requester_id(dev) : \
3481 X86_IOMMU_SID_INVALID);
3482 if (ret) {
3483 trace_kvm_x86_fixup_msi_error(route->gsi);
3484 return 1;
3485 }
3486
3487 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3488 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3489 route->u.msi.data = dst.data;
3490 }
3491
9e03a040
FB		 3492 return 0;
3493}
1850b6b7 3494
38d87493
PX		 3495typedef struct MSIRouteEntry MSIRouteEntry;
3496
3497struct MSIRouteEntry {
3498 PCIDevice *dev; /* Device pointer */
3499 int vector; /* MSI/MSIX vector index */
3500 int virq; /* Virtual IRQ index */
3501 QLIST_ENTRY(MSIRouteEntry) list;
3502};
3503
3504/* List of used GSI routes */
3505static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3506 QLIST_HEAD_INITIALIZER(msi_route_list);
3507
e1d4fb2d
PX		 3508static void kvm_update_msi_routes_all(void *private, bool global,
3509 uint32_t index, uint32_t mask)
3510{
3511 int cnt = 0;
3512 MSIRouteEntry *entry;
3513 MSIMessage msg;
fd563564
PX		 3514 PCIDevice *dev;
3515
e1d4fb2d
PX		 3516 /* TODO: explicit route update */
3517 QLIST_FOREACH(entry, &msi_route_list, list) {
3518 cnt++;
fd563564
PX		 3519 dev = entry->dev;
3520 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3521 continue;
3522 }
3523 msg = pci_get_msi_message(dev, entry->vector);
3524 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3525 }
3f1fea0f 3526 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3527 trace_kvm_x86_update_msi_routes(cnt);
3528}
3529
38d87493
PX		 3530int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3531 int vector, PCIDevice *dev)
3532{
e1d4fb2d 3533 static bool notify_list_inited = false;
38d87493
PX		 3534 MSIRouteEntry *entry;
3535
3536 if (!dev) {
3537 /* These are (possibly) IOAPIC routes only used for split
3538 * kernel irqchip mode, while what we are housekeeping are
3539 * PCI devices only. */
3540 return 0;
3541 }
3542
3543 entry = g_new0(MSIRouteEntry, 1);
3544 entry->dev = dev;
3545 entry->vector = vector;
3546 entry->virq = route->gsi;
3547 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3548
3549 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3550
3551 if (!notify_list_inited) {
3552 /* For the first time we do add route, add ourselves into
3553 * IOMMU's IEC notify list if needed. */
3554 X86IOMMUState *iommu = x86_iommu_get_default();
3555 if (iommu) {
3556 x86_iommu_iec_register_notifier(iommu,
3557 kvm_update_msi_routes_all,
3558 NULL);
3559 }
3560 notify_list_inited = true;
3561 }
38d87493
PX		 3562 return 0;
3563}
3564
3565int kvm_arch_release_virq_post(int virq)
3566{
3567 MSIRouteEntry *entry, *next;
3568 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3569 if (entry->virq == virq) {
3570 trace_kvm_x86_remove_msi_route(virq);
3571 QLIST_REMOVE(entry, list);
3572 break;
3573 }
3574 }
9e03a040
FB		 3575 return 0;
3576}
1850b6b7
EA		 3577
3578int kvm_arch_msi_data_to_gsi(uint32_t data)
3579{
3580 abort();
3581}
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