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KVM: MMU: Add 5 level EPT & Shadow page table support.
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
18863bdd
AK		 137#define KVM_NR_SHARED_MSRS 16
138
139struct kvm_shared_msrs_global {
140 int nr;
2bf78fa7 141 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144struct kvm_shared_msrs {
145 struct user_return_notifier urn;
146 bool registered;
2bf78fa7
SY		 147 struct kvm_shared_msr_values {
148 u64 host;
149 u64 curr;
150 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 151};
152
153static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 154static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 155
417bc304 156struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 157 { "pf_fixed", VCPU_STAT(pf_fixed) },
158 { "pf_guest", VCPU_STAT(pf_guest) },
159 { "tlb_flush", VCPU_STAT(tlb_flush) },
160 { "invlpg", VCPU_STAT(invlpg) },
161 { "exits", VCPU_STAT(exits) },
162 { "io_exits", VCPU_STAT(io_exits) },
163 { "mmio_exits", VCPU_STAT(mmio_exits) },
164 { "signal_exits", VCPU_STAT(signal_exits) },
165 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 166 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 167 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 168 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 169 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 170 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 171 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 172 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 173 { "request_irq", VCPU_STAT(request_irq_exits) },
174 { "irq_exits", VCPU_STAT(irq_exits) },
175 { "host_state_reload", VCPU_STAT(host_state_reload) },
176 { "efer_reload", VCPU_STAT(efer_reload) },
177 { "fpu_reload", VCPU_STAT(fpu_reload) },
178 { "insn_emulation", VCPU_STAT(insn_emulation) },
179 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 180 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 181 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 182 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 195 { NULL }
196};
197
2acf923e
DC		 198u64 __read_mostly host_xcr0;
199
b6785def 200static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 201
af585b92
GN		 202static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
203{
204 int i;
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
207}
208
18863bdd
AK		 209static void kvm_on_user_return(struct user_return_notifier *urn)
210{
211 unsigned slot;
18863bdd
AK		 212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 214 struct kvm_shared_msr_values *values;
1650b4eb
IA		 215 unsigned long flags;
216
217 /*
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
220 */
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
225 }
226 local_irq_restore(flags);
18863bdd 227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
18863bdd
AK		 232 }
233 }
18863bdd
AK		 234}
235
2bf78fa7 236static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 237{
18863bdd 238 u64 value;
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 241
2bf78fa7
SY		 242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
246 return;
247 }
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
251}
252
253void kvm_define_shared_msr(unsigned slot, u32 msr)
254{
0123be42 255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 256 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
261
262static void kvm_shared_msr_cpu_online(void)
263{
264 unsigned i;
18863bdd
AK		 265
266 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 267 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 268}
269
8b3c3104 270int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 274 int err;
18863bdd 275
2bf78fa7 276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 277 return 0;
2bf78fa7 278 smsr->values[slot].curr = value;
8b3c3104
AH		 279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
280 if (err)
281 return 1;
282
18863bdd
AK		 283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
287 }
8b3c3104 288 return 0;
18863bdd
AK		 289}
290EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
291
13a34e06 292static void drop_user_return_notifiers(void)
3548bab5 293{
013f6a5d
MT		 294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 296
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
299}
300
6866b83e
CO		 301u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
302{
8a5a87d9 303 return vcpu->arch.apic_base;
6866b83e
CO		 304}
305EXPORT_SYMBOL_GPL(kvm_get_apic_base);
306
58cb628d
JK		 307int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
308{
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
314 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 315
d3802286
JM		 316 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
317 return 1;
58cb628d 318 if (!msr_info->host_initiated &&
d3802286 319 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
322 old_state == 0)))
323 return 1;
324
325 kvm_lapic_set_base(vcpu, msr_info->data);
326 return 0;
6866b83e
CO		 327}
328EXPORT_SYMBOL_GPL(kvm_set_apic_base);
329
2605fc21 330asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 331{
332 /* Fault while not rebooting. We want the trace. */
333 BUG();
334}
335EXPORT_SYMBOL_GPL(kvm_spurious_fault);
336
3fd28fce
ED		 337#define EXCPT_BENIGN 0
338#define EXCPT_CONTRIBUTORY 1
339#define EXCPT_PF 2
340
341static int exception_class(int vector)
342{
343 switch (vector) {
344 case PF_VECTOR:
345 return EXCPT_PF;
346 case DE_VECTOR:
347 case TS_VECTOR:
348 case NP_VECTOR:
349 case SS_VECTOR:
350 case GP_VECTOR:
351 return EXCPT_CONTRIBUTORY;
352 default:
353 break;
354 }
355 return EXCPT_BENIGN;
356}
357
d6e8c854
NA		 358#define EXCPT_FAULT 0
359#define EXCPT_TRAP 1
360#define EXCPT_ABORT 2
361#define EXCPT_INTERRUPT 3
362
363static int exception_type(int vector)
364{
365 unsigned int mask;
366
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
369
370 mask = 1 << vector;
371
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
374 return EXCPT_TRAP;
375
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
377 return EXCPT_ABORT;
378
379 /* Reserved exceptions will result in fault */
380 return EXCPT_FAULT;
381}
382
3fd28fce 383static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 384 unsigned nr, bool has_error, u32 error_code,
385 bool reinject)
3fd28fce
ED		 386{
387 u32 prev_nr;
388 int class1, class2;
389
3842d135
AK		 390 kvm_make_request(KVM_REQ_EVENT, vcpu);
391
3fd28fce
ED		 392 if (!vcpu->arch.exception.pending) {
393 queue:
3ffb2468
NA		 394 if (has_error && !is_protmode(vcpu))
395 has_error = false;
3fd28fce
ED		 396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
3f0fd292 400 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 401 return;
402 }
403
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
a8eeb04a 408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 409 return;
410 }
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
420 } else
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
423 exception */
424 goto queue;
425}
426
298101da
AK		 427void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
428{
ce7ddec4 429 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 430}
431EXPORT_SYMBOL_GPL(kvm_queue_exception);
432
ce7ddec4
JR		 433void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
434{
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
436}
437EXPORT_SYMBOL_GPL(kvm_requeue_exception);
438
6affcbed 439int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 440{
db8fcefa
AP		 441 if (err)
442 kvm_inject_gp(vcpu, 0);
443 else
6affcbed
KH		 444 return kvm_skip_emulated_instruction(vcpu);
445
446 return 1;
db8fcefa
AP		 447}
448EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 449
6389ee94 450void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 451{
452 ++vcpu->stat.pf_guest;
adfe20fb
WL		 453 vcpu->arch.exception.nested_apf =
454 is_guest_mode(vcpu) && fault->async_page_fault;
455 if (vcpu->arch.exception.nested_apf)
456 vcpu->arch.apf.nested_apf_token = fault->address;
457 else
458 vcpu->arch.cr2 = fault->address;
6389ee94 459 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 460}
27d6c865 461EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 462
ef54bcfe 463static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 464{
6389ee94
AK		 465 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
466 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 467 else
6389ee94 468 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 469
470 return fault->nested_page_fault;
d4f8cf66
JR		 471}
472
3419ffc8
SY		 473void kvm_inject_nmi(struct kvm_vcpu *vcpu)
474{
7460fb4a
AK		 475 atomic_inc(&vcpu->arch.nmi_queued);
476 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 477}
478EXPORT_SYMBOL_GPL(kvm_inject_nmi);
479
298101da
AK		 480void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
481{
ce7ddec4 482 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 483}
484EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
485
ce7ddec4
JR		 486void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
487{
488 kvm_multiple_exception(vcpu, nr, true, error_code, true);
489}
490EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
491
0a79b009
AK		 492/*
493 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
494 * a #GP and return false.
495 */
496bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 497{
0a79b009
AK		 498 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
499 return true;
500 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
501 return false;
298101da 502}
0a79b009 503EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 504
16f8a6f9
NA		 505bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
506{
507 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
508 return true;
509
510 kvm_queue_exception(vcpu, UD_VECTOR);
511 return false;
512}
513EXPORT_SYMBOL_GPL(kvm_require_dr);
514
ec92fe44
JR		 515/*
516 * This function will be used to read from the physical memory of the currently
54bf36aa 517 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 518 * can read from guest physical or from the guest's guest physical memory.
519 */
520int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
521 gfn_t ngfn, void *data, int offset, int len,
522 u32 access)
523{
54987b7a 524 struct x86_exception exception;
ec92fe44
JR		 525 gfn_t real_gfn;
526 gpa_t ngpa;
527
528 ngpa = gfn_to_gpa(ngfn);
54987b7a 529 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 530 if (real_gfn == UNMAPPED_GVA)
531 return -EFAULT;
532
533 real_gfn = gpa_to_gfn(real_gfn);
534
54bf36aa 535 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 536}
537EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
538
69b0049a 539static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 540 void *data, int offset, int len, u32 access)
541{
542 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
543 data, offset, len, access);
544}
545
a03490ed
CO		 546/*
547 * Load the pae pdptrs. Return true is they are all valid.
548 */
ff03a073 549int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 550{
551 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
552 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
553 int i;
554 int ret;
ff03a073 555 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 556
ff03a073
JR		 557 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
558 offset * sizeof(u64), sizeof(pdpte),
559 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 560 if (ret < 0) {
561 ret = 0;
562 goto out;
563 }
564 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 565 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 566 (pdpte[i] &
567 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 568 ret = 0;
569 goto out;
570 }
571 }
572 ret = 1;
573
ff03a073 574 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 575 __set_bit(VCPU_EXREG_PDPTR,
576 (unsigned long *)&vcpu->arch.regs_avail);
577 __set_bit(VCPU_EXREG_PDPTR,
578 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 579out:
a03490ed
CO		 580
581 return ret;
582}
cc4b6871 583EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 584
9ed38ffa 585bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 586{
ff03a073 587 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 588 bool changed = true;
3d06b8bf
JR		 589 int offset;
590 gfn_t gfn;
d835dfec
AK		 591 int r;
592
593 if (is_long_mode(vcpu) || !is_pae(vcpu))
594 return false;
595
6de4f3ad
AK		 596 if (!test_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_avail))
598 return true;
599
a512177e
PB		 600 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
601 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 602 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
603 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 604 if (r < 0)
605 goto out;
ff03a073 606 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 607out:
d835dfec
AK		 608
609 return changed;
610}
9ed38ffa 611EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 612
49a9b07e 613int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 614{
aad82703 615 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 616 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 617
f9a48e6a
AK		 618 cr0 |= X86_CR0_ET;
619
ab344828 620#ifdef CONFIG_X86_64
0f12244f
GN		 621 if (cr0 & 0xffffffff00000000UL)
622 return 1;
ab344828
GN		 623#endif
624
625 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
628 return 1;
a03490ed 629
0f12244f
GN		 630 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
631 return 1;
a03490ed
CO		 632
633 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
634#ifdef CONFIG_X86_64
f6801dff 635 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 636 int cs_db, cs_l;
637
0f12244f
GN		 638 if (!is_pae(vcpu))
639 return 1;
a03490ed 640 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 641 if (cs_l)
642 return 1;
a03490ed
CO		 643 } else
644#endif
ff03a073 645 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 646 kvm_read_cr3(vcpu)))
0f12244f 647 return 1;
a03490ed
CO		 648 }
649
ad756a16
MJ		 650 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
651 return 1;
652
a03490ed 653 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 654
d170c419 655 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 656 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 657 kvm_async_pf_hash_reset(vcpu);
658 }
e5f3f027 659
aad82703
SY		 660 if ((cr0 ^ old_cr0) & update_bits)
661 kvm_mmu_reset_context(vcpu);
b18d5431 662
879ae188
LE		 663 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
664 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
665 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 666 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
667
0f12244f
GN		 668 return 0;
669}
2d3ad1f4 670EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 671
2d3ad1f4 672void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 673{
49a9b07e 674 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 677
42bdf991
MT		 678static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
679{
680 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
681 !vcpu->guest_xcr0_loaded) {
682 /* kvm_set_xcr() also depends on this */
683 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
684 vcpu->guest_xcr0_loaded = 1;
685 }
686}
687
688static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
689{
690 if (vcpu->guest_xcr0_loaded) {
691 if (vcpu->arch.xcr0 != host_xcr0)
692 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
693 vcpu->guest_xcr0_loaded = 0;
694 }
695}
696
69b0049a 697static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 698{
56c103ec
LJ		 699 u64 xcr0 = xcr;
700 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 701 u64 valid_bits;
2acf923e
DC		 702
703 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
704 if (index != XCR_XFEATURE_ENABLED_MASK)
705 return 1;
d91cab78 706 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 709 return 1;
46c34cb0
PB		 710
711 /*
712 * Do not allow the guest to set bits that we do not support
713 * saving. However, xcr0 bit 0 is always set, even if the
714 * emulated CPU does not support XSAVE (see fx_init).
715 */
d91cab78 716 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 717 if (xcr0 & ~valid_bits)
2acf923e 718 return 1;
46c34cb0 719
d91cab78
DH		 720 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
721 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 722 return 1;
723
d91cab78
DH		 724 if (xcr0 & XFEATURE_MASK_AVX512) {
725 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 728 return 1;
729 }
2acf923e 730 vcpu->arch.xcr0 = xcr0;
56c103ec 731
d91cab78 732 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 733 kvm_update_cpuid(vcpu);
2acf923e
DC		 734 return 0;
735}
736
737int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
738{
764bcbc5
Z		 739 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
740 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 741 kvm_inject_gp(vcpu, 0);
742 return 1;
743 }
744 return 0;
745}
746EXPORT_SYMBOL_GPL(kvm_set_xcr);
747
a83b29c6 748int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 749{
fc78f519 750 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 751 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 752 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 753
0f12244f
GN		 754 if (cr4 & CR4_RESERVED_BITS)
755 return 1;
a03490ed 756
d6321d49 757 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 758 return 1;
759
d6321d49 760 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
c68b734f
YW		 761 return 1;
762
d6321d49 763 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
97ec8c06
FW		 764 return 1;
765
d6321d49 766 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 767 return 1;
768
d6321d49 769 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
b9baba86
HH		 770 return 1;
771
a03490ed 772 if (is_long_mode(vcpu)) {
0f12244f
GN		 773 if (!(cr4 & X86_CR4_PAE))
774 return 1;
a2edf57f
AK		 775 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
776 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 777 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
778 kvm_read_cr3(vcpu)))
0f12244f
GN		 779 return 1;
780
ad756a16 781 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 783 return 1;
784
785 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
786 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
787 return 1;
788 }
789
5e1746d6 790 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 791 return 1;
a03490ed 792
ad756a16
MJ		 793 if (((cr4 ^ old_cr4) & pdptr_bits) ||
794 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 795 kvm_mmu_reset_context(vcpu);
0f12244f 796
b9baba86 797 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 798 kvm_update_cpuid(vcpu);
2acf923e 799
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 803
2390218b 804int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 805{
ac146235 806#ifdef CONFIG_X86_64
9d88fca7 807 cr3 &= ~CR3_PCID_INVD;
ac146235 808#endif
9d88fca7 809
9f8fe504 810 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 811 kvm_mmu_sync_roots(vcpu);
77c3913b 812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 813 return 0;
d835dfec
AK		 814 }
815
d1cd3ce9
YZ		 816 if (is_long_mode(vcpu) &&
817 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
818 return 1;
819 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 820 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 821 return 1;
a03490ed 822
0f12244f 823 vcpu->arch.cr3 = cr3;
aff48baa 824 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 825 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 826 return 0;
827}
2d3ad1f4 828EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 829
eea1cff9 830int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 831{
0f12244f
GN		 832 if (cr8 & CR8_RESERVED_BITS)
833 return 1;
35754c98 834 if (lapic_in_kernel(vcpu))
a03490ed
CO		 835 kvm_lapic_set_tpr(vcpu, cr8);
836 else
ad312c7c 837 vcpu->arch.cr8 = cr8;
0f12244f
GN		 838 return 0;
839}
2d3ad1f4 840EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 841
2d3ad1f4 842unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 843{
35754c98 844 if (lapic_in_kernel(vcpu))
a03490ed
CO		 845 return kvm_lapic_get_cr8(vcpu);
846 else
ad312c7c 847 return vcpu->arch.cr8;
a03490ed 848}
2d3ad1f4 849EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 850
ae561ede
NA		 851static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
852{
853 int i;
854
855 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
856 for (i = 0; i < KVM_NR_DB_REGS; i++)
857 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
858 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
859 }
860}
861
73aaf249
JK		 862static void kvm_update_dr6(struct kvm_vcpu *vcpu)
863{
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
866}
867
c8639010
JK		 868static void kvm_update_dr7(struct kvm_vcpu *vcpu)
869{
870 unsigned long dr7;
871
872 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
873 dr7 = vcpu->arch.guest_debug_dr7;
874 else
875 dr7 = vcpu->arch.dr7;
876 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 877 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
878 if (dr7 & DR7_BP_EN_MASK)
879 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 880}
881
6f43ed01
NA		 882static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
883{
884 u64 fixed = DR6_FIXED_1;
885
d6321d49 886 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 887 fixed |= DR6_RTM;
888 return fixed;
889}
890
338dbc97 891static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 892{
893 switch (dr) {
894 case 0 ... 3:
895 vcpu->arch.db[dr] = val;
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 vcpu->arch.eff_db[dr] = val;
898 break;
899 case 4:
020df079
GN		 900 /* fall through */
901 case 6:
338dbc97
GN		 902 if (val & 0xffffffff00000000ULL)
903 return -1; /* #GP */
6f43ed01 904 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 905 kvm_update_dr6(vcpu);
020df079
GN		 906 break;
907 case 5:
020df079
GN		 908 /* fall through */
909 default: /* 7 */
338dbc97
GN		 910 if (val & 0xffffffff00000000ULL)
911 return -1; /* #GP */
020df079 912 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 913 kvm_update_dr7(vcpu);
020df079
GN		 914 break;
915 }
916
917 return 0;
918}
338dbc97
GN		 919
920int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
921{
16f8a6f9 922 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 923 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 924 return 1;
925 }
926 return 0;
338dbc97 927}
020df079
GN		 928EXPORT_SYMBOL_GPL(kvm_set_dr);
929
16f8a6f9 930int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 931{
932 switch (dr) {
933 case 0 ... 3:
934 *val = vcpu->arch.db[dr];
935 break;
936 case 4:
020df079
GN		 937 /* fall through */
938 case 6:
73aaf249
JK		 939 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
940 *val = vcpu->arch.dr6;
941 else
942 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 943 break;
944 case 5:
020df079
GN		 945 /* fall through */
946 default: /* 7 */
947 *val = vcpu->arch.dr7;
948 break;
949 }
338dbc97
GN		 950 return 0;
951}
020df079
GN		 952EXPORT_SYMBOL_GPL(kvm_get_dr);
953
022cd0e8
AK		 954bool kvm_rdpmc(struct kvm_vcpu *vcpu)
955{
956 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
957 u64 data;
958 int err;
959
c6702c9d 960 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 961 if (err)
962 return err;
963 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
964 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
965 return err;
966}
967EXPORT_SYMBOL_GPL(kvm_rdpmc);
968
043405e1
CO		 969/*
970 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
971 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
972 *
973 * This list is modified at module load time to reflect the
e3267cbb 974 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 975 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
976 * may depend on host virtualization features rather than host cpu features.
043405e1 977 */
e3267cbb 978
043405e1
CO		 979static u32 msrs_to_save[] = {
980 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 981 MSR_STAR,
043405e1
CO		 982#ifdef CONFIG_X86_64
983 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
984#endif
b3897a49 985 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 986 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 987};
988
989static unsigned num_msrs_to_save;
990
62ef68bb
PB		 991static u32 emulated_msrs[] = {
992 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
993 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
994 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
995 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 996 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 997 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
998 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 999 HV_X64_MSR_RESET,
11c4b1ca 1000 HV_X64_MSR_VP_INDEX,
9eec50b8 1001 HV_X64_MSR_VP_RUNTIME,
5c919412 1002 HV_X64_MSR_SCONTROL,
1f4b34f8 1003 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1004 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1005 MSR_KVM_PV_EOI_EN,
1006
ba904635 1007 MSR_IA32_TSC_ADJUST,
a3e06bbe 1008 MSR_IA32_TSCDEADLINE,
043405e1 1009 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1010 MSR_IA32_MCG_STATUS,
1011 MSR_IA32_MCG_CTL,
c45dcc71 1012 MSR_IA32_MCG_EXT_CTL,
64d60670 1013 MSR_IA32_SMBASE,
db2336a8
KH		 1014 MSR_PLATFORM_INFO,
1015 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1016};
1017
62ef68bb
PB		 1018static unsigned num_emulated_msrs;
1019
384bb783 1020bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1021{
b69e8cae 1022 if (efer & efer_reserved_bits)
384bb783 1023 return false;
15c4a640 1024
1b4d56b8 1025 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1026 return false;
1b2fd70c 1027
1b4d56b8 1028 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1029 return false;
d8017474 1030
384bb783
JK		 1031 return true;
1032}
1033EXPORT_SYMBOL_GPL(kvm_valid_efer);
1034
1035static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1036{
1037 u64 old_efer = vcpu->arch.efer;
1038
1039 if (!kvm_valid_efer(vcpu, efer))
1040 return 1;
1041
1042 if (is_paging(vcpu)
1043 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1044 return 1;
1045
15c4a640 1046 efer &= ~EFER_LMA;
f6801dff 1047 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1048
a3d204e2
SY		 1049 kvm_x86_ops->set_efer(vcpu, efer);
1050
aad82703
SY		 1051 /* Update reserved bits */
1052 if ((efer ^ old_efer) & EFER_NX)
1053 kvm_mmu_reset_context(vcpu);
1054
b69e8cae 1055 return 0;
15c4a640
CO		 1056}
1057
f2b4b7dd
JR		 1058void kvm_enable_efer_bits(u64 mask)
1059{
1060 efer_reserved_bits &= ~mask;
1061}
1062EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1063
15c4a640
CO		 1064/*
1065 * Writes msr value into into the appropriate "register".
1066 * Returns 0 on success, non-0 otherwise.
1067 * Assumes vcpu_load() was already called.
1068 */
8fe8ab46 1069int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1070{
854e8bb1
NA		 1071 switch (msr->index) {
1072 case MSR_FS_BASE:
1073 case MSR_GS_BASE:
1074 case MSR_KERNEL_GS_BASE:
1075 case MSR_CSTAR:
1076 case MSR_LSTAR:
1077 if (is_noncanonical_address(msr->data))
1078 return 1;
1079 break;
1080 case MSR_IA32_SYSENTER_EIP:
1081 case MSR_IA32_SYSENTER_ESP:
1082 /*
1083 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1084 * non-canonical address is written on Intel but not on
1085 * AMD (which ignores the top 32-bits, because it does
1086 * not implement 64-bit SYSENTER).
1087 *
1088 * 64-bit code should hence be able to write a non-canonical
1089 * value on AMD. Making the address canonical ensures that
1090 * vmentry does not fail on Intel after writing a non-canonical
1091 * value, and that something deterministic happens if the guest
1092 * invokes 64-bit SYSENTER.
1093 */
1094 msr->data = get_canonical(msr->data);
1095 }
8fe8ab46 1096 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1097}
854e8bb1 1098EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1099
313a3dc7
CO		 1100/*
1101 * Adapt set_msr() to msr_io()'s calling convention
1102 */
609e36d3
PB		 1103static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1104{
1105 struct msr_data msr;
1106 int r;
1107
1108 msr.index = index;
1109 msr.host_initiated = true;
1110 r = kvm_get_msr(vcpu, &msr);
1111 if (r)
1112 return r;
1113
1114 *data = msr.data;
1115 return 0;
1116}
1117
313a3dc7
CO		 1118static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1119{
8fe8ab46
WA		 1120 struct msr_data msr;
1121
1122 msr.data = *data;
1123 msr.index = index;
1124 msr.host_initiated = true;
1125 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1126}
1127
16e8d74d
MT		 1128#ifdef CONFIG_X86_64
1129struct pvclock_gtod_data {
1130 seqcount_t seq;
1131
1132 struct { /* extract of a clocksource struct */
1133 int vclock_mode;
a5a1d1c2
TG		 1134 u64 cycle_last;
1135 u64 mask;
16e8d74d
MT		 1136 u32 mult;
1137 u32 shift;
1138 } clock;
1139
cbcf2dd3
TG		 1140 u64 boot_ns;
1141 u64 nsec_base;
55dd00a7 1142 u64 wall_time_sec;
16e8d74d
MT		 1143};
1144
1145static struct pvclock_gtod_data pvclock_gtod_data;
1146
1147static void update_pvclock_gtod(struct timekeeper *tk)
1148{
1149 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1150 u64 boot_ns;
1151
876e7881 1152 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1153
1154 write_seqcount_begin(&vdata->seq);
1155
1156 /* copy pvclock gtod data */
876e7881
PZ		 1157 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1158 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1159 vdata->clock.mask = tk->tkr_mono.mask;
1160 vdata->clock.mult = tk->tkr_mono.mult;
1161 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1162
cbcf2dd3 1163 vdata->boot_ns = boot_ns;
876e7881 1164 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1165
55dd00a7
MT		 1166 vdata->wall_time_sec = tk->xtime_sec;
1167
16e8d74d
MT		 1168 write_seqcount_end(&vdata->seq);
1169}
1170#endif
1171
bab5bb39
NK		 1172void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1173{
1174 /*
1175 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1176 * vcpu_enter_guest. This function is only called from
1177 * the physical CPU that is running vcpu.
1178 */
1179 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1180}
16e8d74d 1181
18068523
GOC		 1182static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1183{
9ed3c444
AK		 1184 int version;
1185 int r;
50d0a0f9 1186 struct pvclock_wall_clock wc;
87aeb54f 1187 struct timespec64 boot;
18068523
GOC		 1188
1189 if (!wall_clock)
1190 return;
1191
9ed3c444
AK		 1192 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1193 if (r)
1194 return;
1195
1196 if (version & 1)
1197 ++version; /* first time write, random junk */
1198
1199 ++version;
18068523 1200
1dab1345
NK		 1201 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1202 return;
18068523 1203
50d0a0f9
GH		 1204 /*
1205 * The guest calculates current wall clock time by adding
34c238a1 1206 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1207 * wall clock specified here. guest system time equals host
1208 * system time for us, thus we must fill in host boot time here.
1209 */
87aeb54f 1210 getboottime64(&boot);
50d0a0f9 1211
4b648665 1212 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1213 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1214 boot = timespec64_sub(boot, ts);
4b648665 1215 }
87aeb54f 1216 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1217 wc.nsec = boot.tv_nsec;
1218 wc.version = version;
18068523
GOC		 1219
1220 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1221
1222 version++;
1223 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1224}
1225
50d0a0f9
GH		 1226static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1227{
b51012de
PB		 1228 do_shl32_div32(dividend, divisor);
1229 return dividend;
50d0a0f9
GH		 1230}
1231
3ae13faa 1232static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1233 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1234{
5f4e3f88 1235 uint64_t scaled64;
50d0a0f9
GH		 1236 int32_t shift = 0;
1237 uint64_t tps64;
1238 uint32_t tps32;
1239
3ae13faa
PB		 1240 tps64 = base_hz;
1241 scaled64 = scaled_hz;
50933623 1242 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1243 tps64 >>= 1;
1244 shift--;
1245 }
1246
1247 tps32 = (uint32_t)tps64;
50933623
JK		 1248 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1249 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1250 scaled64 >>= 1;
1251 else
1252 tps32 <<= 1;
50d0a0f9
GH		 1253 shift++;
1254 }
1255
5f4e3f88
ZA		 1256 *pshift = shift;
1257 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1258
3ae13faa
PB		 1259 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1260 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1261}
1262
d828199e 1263#ifdef CONFIG_X86_64
16e8d74d 1264static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1265#endif
16e8d74d 1266
c8076604 1267static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1268static unsigned long max_tsc_khz;
c8076604 1269
cc578287 1270static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1271{
cc578287
ZA		 1272 u64 v = (u64)khz * (1000000 + ppm);
1273 do_div(v, 1000000);
1274 return v;
1e993611
JR		 1275}
1276
381d585c
HZ		 1277static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1278{
1279 u64 ratio;
1280
1281 /* Guest TSC same frequency as host TSC? */
1282 if (!scale) {
1283 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1284 return 0;
1285 }
1286
1287 /* TSC scaling supported? */
1288 if (!kvm_has_tsc_control) {
1289 if (user_tsc_khz > tsc_khz) {
1290 vcpu->arch.tsc_catchup = 1;
1291 vcpu->arch.tsc_always_catchup = 1;
1292 return 0;
1293 } else {
1294 WARN(1, "user requested TSC rate below hardware speed\n");
1295 return -1;
1296 }
1297 }
1298
1299 /* TSC scaling required - calculate ratio */
1300 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1301 user_tsc_khz, tsc_khz);
1302
1303 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1304 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1305 user_tsc_khz);
1306 return -1;
1307 }
1308
1309 vcpu->arch.tsc_scaling_ratio = ratio;
1310 return 0;
1311}
1312
4941b8cb 1313static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1314{
cc578287
ZA		 1315 u32 thresh_lo, thresh_hi;
1316 int use_scaling = 0;
217fc9cf 1317
03ba32ca 1318 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1319 if (user_tsc_khz == 0) {
ad721883
HZ		 1320 /* set tsc_scaling_ratio to a safe value */
1321 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1322 return -1;
ad721883 1323 }
03ba32ca 1324
c285545f 1325 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1326 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1327 &vcpu->arch.virtual_tsc_shift,
1328 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1329 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1330
1331 /*
1332 * Compute the variation in TSC rate which is acceptable
1333 * within the range of tolerance and decide if the
1334 * rate being applied is within that bounds of the hardware
1335 * rate. If so, no scaling or compensation need be done.
1336 */
1337 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1338 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1339 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1340 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1341 use_scaling = 1;
1342 }
4941b8cb 1343 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1344}
1345
1346static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1347{
e26101b1 1348 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1349 vcpu->arch.virtual_tsc_mult,
1350 vcpu->arch.virtual_tsc_shift);
e26101b1 1351 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1352 return tsc;
1353}
1354
69b0049a 1355static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1356{
1357#ifdef CONFIG_X86_64
1358 bool vcpus_matched;
b48aa97e
MT		 1359 struct kvm_arch *ka = &vcpu->kvm->arch;
1360 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1361
1362 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1363 atomic_read(&vcpu->kvm->online_vcpus));
1364
7f187922
MT		 1365 /*
1366 * Once the masterclock is enabled, always perform request in
1367 * order to update it.
1368 *
1369 * In order to enable masterclock, the host clocksource must be TSC
1370 * and the vcpus need to have matched TSCs. When that happens,
1371 * perform request to enable masterclock.
1372 */
1373 if (ka->use_master_clock ||
1374 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1375 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1376
1377 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1378 atomic_read(&vcpu->kvm->online_vcpus),
1379 ka->use_master_clock, gtod->clock.vclock_mode);
1380#endif
1381}
1382
ba904635
WA		 1383static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1384{
3e3f5026 1385 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1386 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1387}
1388
35181e86
HZ		 1389/*
1390 * Multiply tsc by a fixed point number represented by ratio.
1391 *
1392 * The most significant 64-N bits (mult) of ratio represent the
1393 * integral part of the fixed point number; the remaining N bits
1394 * (frac) represent the fractional part, ie. ratio represents a fixed
1395 * point number (mult + frac * 2^(-N)).
1396 *
1397 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1398 */
1399static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1400{
1401 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1402}
1403
1404u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1405{
1406 u64 _tsc = tsc;
1407 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1408
1409 if (ratio != kvm_default_tsc_scaling_ratio)
1410 _tsc = __scale_tsc(ratio, tsc);
1411
1412 return _tsc;
1413}
1414EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1415
07c1419a
HZ		 1416static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1417{
1418 u64 tsc;
1419
1420 tsc = kvm_scale_tsc(vcpu, rdtsc());
1421
1422 return target_tsc - tsc;
1423}
1424
4ba76538
HZ		 1425u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1426{
ea26e4ec 1427 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1428}
1429EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1430
a545ab6a
LC		 1431static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1432{
1433 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1434 vcpu->arch.tsc_offset = offset;
1435}
1436
8fe8ab46 1437void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1438{
1439 struct kvm *kvm = vcpu->kvm;
f38e098f 1440 u64 offset, ns, elapsed;
99e3e30a 1441 unsigned long flags;
b48aa97e 1442 bool matched;
0d3da0d2 1443 bool already_matched;
8fe8ab46 1444 u64 data = msr->data;
c5e8ec8e 1445 bool synchronizing = false;
99e3e30a 1446
038f8c11 1447 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1448 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1449 ns = ktime_get_boot_ns();
f38e098f 1450 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1451
03ba32ca 1452 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1453 if (data == 0 && msr->host_initiated) {
1454 /*
1455 * detection of vcpu initialization -- need to sync
1456 * with other vCPUs. This particularly helps to keep
1457 * kvm_clock stable after CPU hotplug
1458 */
1459 synchronizing = true;
1460 } else {
1461 u64 tsc_exp = kvm->arch.last_tsc_write +
1462 nsec_to_cycles(vcpu, elapsed);
1463 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1464 /*
1465 * Special case: TSC write with a small delta (1 second)
1466 * of virtual cycle time against real time is
1467 * interpreted as an attempt to synchronize the CPU.
1468 */
1469 synchronizing = data < tsc_exp + tsc_hz &&
1470 data + tsc_hz > tsc_exp;
1471 }
c5e8ec8e 1472 }
f38e098f
ZA		 1473
1474 /*
5d3cb0f6
ZA		 1475 * For a reliable TSC, we can match TSC offsets, and for an unstable
1476 * TSC, we add elapsed time in this computation. We could let the
1477 * compensation code attempt to catch up if we fall behind, but
1478 * it's better to try to match offsets from the beginning.
1479 */
c5e8ec8e 1480 if (synchronizing &&
5d3cb0f6 1481 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1482 if (!check_tsc_unstable()) {
e26101b1 1483 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1484 pr_debug("kvm: matched tsc offset for %llu\n", data);
1485 } else {
857e4099 1486 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1487 data += delta;
07c1419a 1488 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1489 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1490 }
b48aa97e 1491 matched = true;
0d3da0d2 1492 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1493 } else {
1494 /*
1495 * We split periods of matched TSC writes into generations.
1496 * For each generation, we track the original measured
1497 * nanosecond time, offset, and write, so if TSCs are in
1498 * sync, we can match exact offset, and if not, we can match
4a969980 1499 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1500 *
1501 * These values are tracked in kvm->arch.cur_xxx variables.
1502 */
1503 kvm->arch.cur_tsc_generation++;
1504 kvm->arch.cur_tsc_nsec = ns;
1505 kvm->arch.cur_tsc_write = data;
1506 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1507 matched = false;
0d3da0d2 1508 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1509 kvm->arch.cur_tsc_generation, data);
f38e098f 1510 }
e26101b1
ZA		 1511
1512 /*
1513 * We also track th most recent recorded KHZ, write and time to
1514 * allow the matching interval to be extended at each write.
1515 */
f38e098f
ZA		 1516 kvm->arch.last_tsc_nsec = ns;
1517 kvm->arch.last_tsc_write = data;
5d3cb0f6 1518 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1519
b183aa58 1520 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1521
1522 /* Keep track of which generation this VCPU has synchronized to */
1523 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1524 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1525 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1526
d6321d49 1527 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1528 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1529
a545ab6a 1530 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1531 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1532
1533 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1534 if (!matched) {
b48aa97e 1535 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1536 } else if (!already_matched) {
1537 kvm->arch.nr_vcpus_matched_tsc++;
1538 }
b48aa97e
MT		 1539
1540 kvm_track_tsc_matching(vcpu);
1541 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1542}
e26101b1 1543
99e3e30a
ZA		 1544EXPORT_SYMBOL_GPL(kvm_write_tsc);
1545
58ea6767
HZ		 1546static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1547 s64 adjustment)
1548{
ea26e4ec 1549 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1550}
1551
1552static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1553{
1554 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1555 WARN_ON(adjustment < 0);
1556 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1557 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1558}
1559
d828199e
MT		 1560#ifdef CONFIG_X86_64
1561
a5a1d1c2 1562static u64 read_tsc(void)
d828199e 1563{
a5a1d1c2 1564 u64 ret = (u64)rdtsc_ordered();
03b9730b 1565 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1566
1567 if (likely(ret >= last))
1568 return ret;
1569
1570 /*
1571 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1572 * predictable (it's just a function of time and the likely is
d828199e
MT		 1573 * very likely) and there's a data dependence, so force GCC
1574 * to generate a branch instead. I don't barrier() because
1575 * we don't actually need a barrier, and if this function
1576 * ever gets inlined it will generate worse code.
1577 */
1578 asm volatile ("");
1579 return last;
1580}
1581
a5a1d1c2 1582static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1583{
1584 long v;
1585 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1586
1587 *cycle_now = read_tsc();
1588
1589 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1590 return v * gtod->clock.mult;
1591}
1592
a5a1d1c2 1593static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1594{
cbcf2dd3 1595 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1596 unsigned long seq;
d828199e 1597 int mode;
cbcf2dd3 1598 u64 ns;
d828199e 1599
d828199e
MT		 1600 do {
1601 seq = read_seqcount_begin(&gtod->seq);
1602 mode = gtod->clock.vclock_mode;
cbcf2dd3 1603 ns = gtod->nsec_base;
d828199e
MT		 1604 ns += vgettsc(cycle_now);
1605 ns >>= gtod->clock.shift;
cbcf2dd3 1606 ns += gtod->boot_ns;
d828199e 1607 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1608 *t = ns;
d828199e
MT		 1609
1610 return mode;
1611}
1612
55dd00a7
MT		 1613static int do_realtime(struct timespec *ts, u64 *cycle_now)
1614{
1615 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1616 unsigned long seq;
1617 int mode;
1618 u64 ns;
1619
1620 do {
1621 seq = read_seqcount_begin(&gtod->seq);
1622 mode = gtod->clock.vclock_mode;
1623 ts->tv_sec = gtod->wall_time_sec;
1624 ns = gtod->nsec_base;
1625 ns += vgettsc(cycle_now);
1626 ns >>= gtod->clock.shift;
1627 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1628
1629 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1630 ts->tv_nsec = ns;
1631
1632 return mode;
1633}
1634
d828199e 1635/* returns true if host is using tsc clocksource */
a5a1d1c2 1636static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1637{
d828199e
MT		 1638 /* checked again under seqlock below */
1639 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1640 return false;
1641
cbcf2dd3 1642 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1643}
55dd00a7
MT		 1644
1645/* returns true if host is using tsc clocksource */
1646static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1647 u64 *cycle_now)
1648{
1649 /* checked again under seqlock below */
1650 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1651 return false;
1652
1653 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1654}
d828199e
MT		 1655#endif
1656
1657/*
1658 *
b48aa97e
MT		 1659 * Assuming a stable TSC across physical CPUS, and a stable TSC
1660 * across virtual CPUs, the following condition is possible.
1661 * Each numbered line represents an event visible to both
d828199e
MT		 1662 * CPUs at the next numbered event.
1663 *
1664 * "timespecX" represents host monotonic time. "tscX" represents
1665 * RDTSC value.
1666 *
1667 * VCPU0 on CPU0 | VCPU1 on CPU1
1668 *
1669 * 1. read timespec0,tsc0
1670 * 2. | timespec1 = timespec0 + N
1671 * | tsc1 = tsc0 + M
1672 * 3. transition to guest | transition to guest
1673 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1674 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1675 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1676 *
1677 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1678 *
1679 * - ret0 < ret1
1680 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1681 * ...
1682 * - 0 < N - M => M < N
1683 *
1684 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1685 * always the case (the difference between two distinct xtime instances
1686 * might be smaller then the difference between corresponding TSC reads,
1687 * when updating guest vcpus pvclock areas).
1688 *
1689 * To avoid that problem, do not allow visibility of distinct
1690 * system_timestamp/tsc_timestamp values simultaneously: use a master
1691 * copy of host monotonic time values. Update that master copy
1692 * in lockstep.
1693 *
b48aa97e 1694 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1695 *
1696 */
1697
1698static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1699{
1700#ifdef CONFIG_X86_64
1701 struct kvm_arch *ka = &kvm->arch;
1702 int vclock_mode;
b48aa97e
MT		 1703 bool host_tsc_clocksource, vcpus_matched;
1704
1705 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1706 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1707
1708 /*
1709 * If the host uses TSC clock, then passthrough TSC as stable
1710 * to the guest.
1711 */
b48aa97e 1712 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1713 &ka->master_kernel_ns,
1714 &ka->master_cycle_now);
1715
16a96021 1716 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1717 && !ka->backwards_tsc_observed
54750f2c 1718 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1719
d828199e
MT		 1720 if (ka->use_master_clock)
1721 atomic_set(&kvm_guest_has_master_clock, 1);
1722
1723 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1724 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1725 vcpus_matched);
d828199e
MT		 1726#endif
1727}
1728
2860c4b1
PB		 1729void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1730{
1731 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1732}
1733
2e762ff7
MT		 1734static void kvm_gen_update_masterclock(struct kvm *kvm)
1735{
1736#ifdef CONFIG_X86_64
1737 int i;
1738 struct kvm_vcpu *vcpu;
1739 struct kvm_arch *ka = &kvm->arch;
1740
1741 spin_lock(&ka->pvclock_gtod_sync_lock);
1742 kvm_make_mclock_inprogress_request(kvm);
1743 /* no guest entries from this point */
1744 pvclock_update_vm_gtod_copy(kvm);
1745
1746 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1748
1749 /* guest entries allowed */
1750 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1751 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1752
1753 spin_unlock(&ka->pvclock_gtod_sync_lock);
1754#endif
1755}
1756
e891a32e 1757u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1758{
108b249c 1759 struct kvm_arch *ka = &kvm->arch;
8b953440 1760 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1761 u64 ret;
108b249c 1762
8b953440
PB		 1763 spin_lock(&ka->pvclock_gtod_sync_lock);
1764 if (!ka->use_master_clock) {
1765 spin_unlock(&ka->pvclock_gtod_sync_lock);
1766 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1767 }
1768
8b953440
PB		 1769 hv_clock.tsc_timestamp = ka->master_cycle_now;
1770 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1771 spin_unlock(&ka->pvclock_gtod_sync_lock);
1772
e2c2206a
WL		 1773 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1774 get_cpu();
1775
8b953440
PB		 1776 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1777 &hv_clock.tsc_shift,
1778 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1779 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1780
1781 put_cpu();
1782
1783 return ret;
108b249c
PB		 1784}
1785
0d6dd2ff
PB		 1786static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1787{
1788 struct kvm_vcpu_arch *vcpu = &v->arch;
1789 struct pvclock_vcpu_time_info guest_hv_clock;
1790
4e335d9e 1791 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1792 &guest_hv_clock, sizeof(guest_hv_clock))))
1793 return;
1794
1795 /* This VCPU is paused, but it's legal for a guest to read another
1796 * VCPU's kvmclock, so we really have to follow the specification where
1797 * it says that version is odd if data is being modified, and even after
1798 * it is consistent.
1799 *
1800 * Version field updates must be kept separate. This is because
1801 * kvm_write_guest_cached might use a "rep movs" instruction, and
1802 * writes within a string instruction are weakly ordered. So there
1803 * are three writes overall.
1804 *
1805 * As a small optimization, only write the version field in the first
1806 * and third write. The vcpu->pv_time cache is still valid, because the
1807 * version field is the first in the struct.
1808 */
1809 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1810
1811 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1812 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1813 &vcpu->hv_clock,
1814 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1815
1816 smp_wmb();
1817
1818 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1819 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1820
1821 if (vcpu->pvclock_set_guest_stopped_request) {
1822 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1823 vcpu->pvclock_set_guest_stopped_request = false;
1824 }
1825
1826 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1827
4e335d9e
PB		 1828 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1829 &vcpu->hv_clock,
1830 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1831
1832 smp_wmb();
1833
1834 vcpu->hv_clock.version++;
4e335d9e
PB		 1835 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1836 &vcpu->hv_clock,
1837 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1838}
1839
34c238a1 1840static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1841{
78db6a50 1842 unsigned long flags, tgt_tsc_khz;
18068523 1843 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1844 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1845 s64 kernel_ns;
d828199e 1846 u64 tsc_timestamp, host_tsc;
51d59c6b 1847 u8 pvclock_flags;
d828199e
MT		 1848 bool use_master_clock;
1849
1850 kernel_ns = 0;
1851 host_tsc = 0;
18068523 1852
d828199e
MT		 1853 /*
1854 * If the host uses TSC clock, then passthrough TSC as stable
1855 * to the guest.
1856 */
1857 spin_lock(&ka->pvclock_gtod_sync_lock);
1858 use_master_clock = ka->use_master_clock;
1859 if (use_master_clock) {
1860 host_tsc = ka->master_cycle_now;
1861 kernel_ns = ka->master_kernel_ns;
1862 }
1863 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1864
1865 /* Keep irq disabled to prevent changes to the clock */
1866 local_irq_save(flags);
78db6a50
PB		 1867 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1868 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1869 local_irq_restore(flags);
1870 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1871 return 1;
1872 }
d828199e 1873 if (!use_master_clock) {
4ea1636b 1874 host_tsc = rdtsc();
108b249c 1875 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1876 }
1877
4ba76538 1878 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1879
c285545f
ZA		 1880 /*
1881 * We may have to catch up the TSC to match elapsed wall clock
1882 * time for two reasons, even if kvmclock is used.
1883 * 1) CPU could have been running below the maximum TSC rate
1884 * 2) Broken TSC compensation resets the base at each VCPU
1885 * entry to avoid unknown leaps of TSC even when running
1886 * again on the same CPU. This may cause apparent elapsed
1887 * time to disappear, and the guest to stand still or run
1888 * very slowly.
1889 */
1890 if (vcpu->tsc_catchup) {
1891 u64 tsc = compute_guest_tsc(v, kernel_ns);
1892 if (tsc > tsc_timestamp) {
f1e2b260 1893 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1894 tsc_timestamp = tsc;
1895 }
50d0a0f9
GH		 1896 }
1897
18068523
GOC		 1898 local_irq_restore(flags);
1899
0d6dd2ff 1900 /* With all the info we got, fill in the values */
18068523 1901
78db6a50
PB		 1902 if (kvm_has_tsc_control)
1903 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1904
1905 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1906 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1907 &vcpu->hv_clock.tsc_shift,
1908 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1909 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1910 }
1911
1d5f066e 1912 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1913 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1914 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1915
d828199e 1916 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1917 pvclock_flags = 0;
d828199e
MT		 1918 if (use_master_clock)
1919 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1920
78c0337a
MT		 1921 vcpu->hv_clock.flags = pvclock_flags;
1922
095cf55d
PB		 1923 if (vcpu->pv_time_enabled)
1924 kvm_setup_pvclock_page(v);
1925 if (v == kvm_get_vcpu(v->kvm, 0))
1926 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1927 return 0;
c8076604
GH		 1928}
1929
0061d53d
MT		 1930/*
1931 * kvmclock updates which are isolated to a given vcpu, such as
1932 * vcpu->cpu migration, should not allow system_timestamp from
1933 * the rest of the vcpus to remain static. Otherwise ntp frequency
1934 * correction applies to one vcpu's system_timestamp but not
1935 * the others.
1936 *
1937 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1938 * We need to rate-limit these requests though, as they can
1939 * considerably slow guests that have a large number of vcpus.
1940 * The time for a remote vcpu to update its kvmclock is bound
1941 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1942 */
1943
7e44e449
AJ		 1944#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1945
1946static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1947{
1948 int i;
7e44e449
AJ		 1949 struct delayed_work *dwork = to_delayed_work(work);
1950 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1951 kvmclock_update_work);
1952 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1953 struct kvm_vcpu *vcpu;
1954
1955 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1956 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1957 kvm_vcpu_kick(vcpu);
1958 }
1959}
1960
7e44e449
AJ		 1961static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1962{
1963 struct kvm *kvm = v->kvm;
1964
105b21bb 1965 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1966 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1967 KVMCLOCK_UPDATE_DELAY);
1968}
1969
332967a3
AJ		 1970#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1971
1972static void kvmclock_sync_fn(struct work_struct *work)
1973{
1974 struct delayed_work *dwork = to_delayed_work(work);
1975 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1976 kvmclock_sync_work);
1977 struct kvm *kvm = container_of(ka, struct kvm, arch);
1978
630994b3
MT		 1979 if (!kvmclock_periodic_sync)
1980 return;
1981
332967a3
AJ		 1982 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1983 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1984 KVMCLOCK_SYNC_PERIOD);
1985}
1986
890ca9ae 1987static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1988{
890ca9ae
HY		 1989 u64 mcg_cap = vcpu->arch.mcg_cap;
1990 unsigned bank_num = mcg_cap & 0xff;
1991
15c4a640 1992 switch (msr) {
15c4a640 1993 case MSR_IA32_MCG_STATUS:
890ca9ae 1994 vcpu->arch.mcg_status = data;
15c4a640 1995 break;
c7ac679c 1996 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1997 if (!(mcg_cap & MCG_CTL_P))
1998 return 1;
1999 if (data != 0 && data != ~(u64)0)
2000 return -1;
2001 vcpu->arch.mcg_ctl = data;
2002 break;
2003 default:
2004 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2005 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2006 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2007 /* only 0 or all 1s can be written to IA32_MCi_CTL
2008 * some Linux kernels though clear bit 10 in bank 4 to
2009 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2010 * this to avoid an uncatched #GP in the guest
2011 */
890ca9ae 2012 if ((offset & 0x3) == 0 &&
114be429 2013 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2014 return -1;
2015 vcpu->arch.mce_banks[offset] = data;
2016 break;
2017 }
2018 return 1;
2019 }
2020 return 0;
2021}
2022
ffde22ac
ES		 2023static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2024{
2025 struct kvm *kvm = vcpu->kvm;
2026 int lm = is_long_mode(vcpu);
2027 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2028 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2029 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2030 : kvm->arch.xen_hvm_config.blob_size_32;
2031 u32 page_num = data & ~PAGE_MASK;
2032 u64 page_addr = data & PAGE_MASK;
2033 u8 *page;
2034 int r;
2035
2036 r = -E2BIG;
2037 if (page_num >= blob_size)
2038 goto out;
2039 r = -ENOMEM;
ff5c2c03
SL		 2040 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2041 if (IS_ERR(page)) {
2042 r = PTR_ERR(page);
ffde22ac 2043 goto out;
ff5c2c03 2044 }
54bf36aa 2045 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2046 goto out_free;
2047 r = 0;
2048out_free:
2049 kfree(page);
2050out:
2051 return r;
2052}
2053
344d9588
GN		 2054static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2055{
2056 gpa_t gpa = data & ~0x3f;
2057
52a5c155
WL		 2058 /* Bits 3:5 are reserved, Should be zero */
2059 if (data & 0x38)
344d9588
GN		 2060 return 1;
2061
2062 vcpu->arch.apf.msr_val = data;
2063
2064 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2065 kvm_clear_async_pf_completion_queue(vcpu);
2066 kvm_async_pf_hash_reset(vcpu);
2067 return 0;
2068 }
2069
4e335d9e 2070 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2071 sizeof(u32)))
344d9588
GN		 2072 return 1;
2073
6adba527 2074 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2075 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2076 kvm_async_pf_wakeup_all(vcpu);
2077 return 0;
2078}
2079
12f9a48f
GC		 2080static void kvmclock_reset(struct kvm_vcpu *vcpu)
2081{
0b79459b 2082 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2083}
2084
c9aaa895
GC		 2085static void record_steal_time(struct kvm_vcpu *vcpu)
2086{
2087 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2088 return;
2089
4e335d9e 2090 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2091 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2092 return;
2093
0b9f6c46
PX		 2094 vcpu->arch.st.steal.preempted = 0;
2095
35f3fae1
WL		 2096 if (vcpu->arch.st.steal.version & 1)
2097 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2098
2099 vcpu->arch.st.steal.version += 1;
2100
4e335d9e 2101 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2102 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2103
2104 smp_wmb();
2105
c54cdf14
LC		 2106 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2107 vcpu->arch.st.last_steal;
2108 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2109
4e335d9e 2110 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2111 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2112
2113 smp_wmb();
2114
2115 vcpu->arch.st.steal.version += 1;
c9aaa895 2116
4e335d9e 2117 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2118 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2119}
2120
8fe8ab46 2121int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2122{
5753785f 2123 bool pr = false;
8fe8ab46
WA		 2124 u32 msr = msr_info->index;
2125 u64 data = msr_info->data;
5753785f 2126
15c4a640 2127 switch (msr) {
2e32b719
BP		 2128 case MSR_AMD64_NB_CFG:
2129 case MSR_IA32_UCODE_REV:
2130 case MSR_IA32_UCODE_WRITE:
2131 case MSR_VM_HSAVE_PA:
2132 case MSR_AMD64_PATCH_LOADER:
2133 case MSR_AMD64_BU_CFG2:
405a353a 2134 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2135 break;
2136
15c4a640 2137 case MSR_EFER:
b69e8cae 2138 return set_efer(vcpu, data);
8f1589d9
AP		 2139 case MSR_K7_HWCR:
2140 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2141 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2142 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2143 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2144 if (data != 0) {
a737f256
CD		 2145 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2146 data);
8f1589d9
AP		 2147 return 1;
2148 }
15c4a640 2149 break;
f7c6d140
AP		 2150 case MSR_FAM10H_MMIO_CONF_BASE:
2151 if (data != 0) {
a737f256
CD		 2152 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2153 "0x%llx\n", data);
f7c6d140
AP		 2154 return 1;
2155 }
15c4a640 2156 break;
b5e2fec0
AG		 2157 case MSR_IA32_DEBUGCTLMSR:
2158 if (!data) {
2159 /* We support the non-activated case already */
2160 break;
2161 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2162 /* Values other than LBR and BTF are vendor-specific,
2163 thus reserved and should throw a #GP */
2164 return 1;
2165 }
a737f256
CD		 2166 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2167 __func__, data);
b5e2fec0 2168 break;
9ba075a6 2169 case 0x200 ... 0x2ff:
ff53604b 2170 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2171 case MSR_IA32_APICBASE:
58cb628d 2172 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2173 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2174 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2175 case MSR_IA32_TSCDEADLINE:
2176 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2177 break;
ba904635 2178 case MSR_IA32_TSC_ADJUST:
d6321d49 2179 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2180 if (!msr_info->host_initiated) {
d913b904 2181 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2182 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2183 }
2184 vcpu->arch.ia32_tsc_adjust_msr = data;
2185 }
2186 break;
15c4a640 2187 case MSR_IA32_MISC_ENABLE:
ad312c7c 2188 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2189 break;
64d60670
PB		 2190 case MSR_IA32_SMBASE:
2191 if (!msr_info->host_initiated)
2192 return 1;
2193 vcpu->arch.smbase = data;
2194 break;
11c6bffa 2195 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2196 case MSR_KVM_WALL_CLOCK:
2197 vcpu->kvm->arch.wall_clock = data;
2198 kvm_write_wall_clock(vcpu->kvm, data);
2199 break;
11c6bffa 2200 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2201 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2202 struct kvm_arch *ka = &vcpu->kvm->arch;
2203
12f9a48f 2204 kvmclock_reset(vcpu);
18068523 2205
54750f2c
MT		 2206 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2207 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2208
2209 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2210 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2211
2212 ka->boot_vcpu_runs_old_kvmclock = tmp;
2213 }
2214
18068523 2215 vcpu->arch.time = data;
0061d53d 2216 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2217
2218 /* we verify if the enable bit is set... */
2219 if (!(data & 1))
2220 break;
2221
4e335d9e 2222 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2223 &vcpu->arch.pv_time, data & ~1ULL,
2224 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2225 vcpu->arch.pv_time_enabled = false;
2226 else
2227 vcpu->arch.pv_time_enabled = true;
32cad84f 2228
18068523
GOC		 2229 break;
2230 }
344d9588
GN		 2231 case MSR_KVM_ASYNC_PF_EN:
2232 if (kvm_pv_enable_async_pf(vcpu, data))
2233 return 1;
2234 break;
c9aaa895
GC		 2235 case MSR_KVM_STEAL_TIME:
2236
2237 if (unlikely(!sched_info_on()))
2238 return 1;
2239
2240 if (data & KVM_STEAL_RESERVED_MASK)
2241 return 1;
2242
4e335d9e 2243 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2244 data & KVM_STEAL_VALID_BITS,
2245 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2246 return 1;
2247
2248 vcpu->arch.st.msr_val = data;
2249
2250 if (!(data & KVM_MSR_ENABLED))
2251 break;
2252
c9aaa895
GC		 2253 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2254
2255 break;
ae7a2a3f
MT		 2256 case MSR_KVM_PV_EOI_EN:
2257 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2258 return 1;
2259 break;
c9aaa895 2260
890ca9ae
HY		 2261 case MSR_IA32_MCG_CTL:
2262 case MSR_IA32_MCG_STATUS:
81760dcc 2263 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2264 return set_msr_mce(vcpu, msr, data);
71db6023 2265
6912ac32
WH		 2266 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2267 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2268 pr = true; /* fall through */
2269 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2270 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2271 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2272 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2273
2274 if (pr || data != 0)
a737f256
CD		 2275 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2276 "0x%x data 0x%llx\n", msr, data);
5753785f 2277 break;
84e0cefa
JS		 2278 case MSR_K7_CLK_CTL:
2279 /*
2280 * Ignore all writes to this no longer documented MSR.
2281 * Writes are only relevant for old K7 processors,
2282 * all pre-dating SVM, but a recommended workaround from
4a969980 2283 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2284 * affected processor models on the command line, hence
2285 * the need to ignore the workaround.
2286 */
2287 break;
55cd8e5a 2288 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2289 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2290 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2291 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2292 return kvm_hv_set_msr_common(vcpu, msr, data,
2293 msr_info->host_initiated);
91c9c3ed 2294 case MSR_IA32_BBL_CR_CTL3:
2295 /* Drop writes to this legacy MSR -- see rdmsr
2296 * counterpart for further detail.
2297 */
796f4687 2298 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2299 break;
2b036c6b 2300 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2301 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2302 return 1;
2303 vcpu->arch.osvw.length = data;
2304 break;
2305 case MSR_AMD64_OSVW_STATUS:
d6321d49 2306 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2307 return 1;
2308 vcpu->arch.osvw.status = data;
2309 break;
db2336a8
KH		 2310 case MSR_PLATFORM_INFO:
2311 if (!msr_info->host_initiated ||
2312 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2313 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2314 cpuid_fault_enabled(vcpu)))
2315 return 1;
2316 vcpu->arch.msr_platform_info = data;
2317 break;
2318 case MSR_MISC_FEATURES_ENABLES:
2319 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2320 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2321 !supports_cpuid_fault(vcpu)))
2322 return 1;
2323 vcpu->arch.msr_misc_features_enables = data;
2324 break;
15c4a640 2325 default:
ffde22ac
ES		 2326 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2327 return xen_hvm_config(vcpu, data);
c6702c9d 2328 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2329 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2330 if (!ignore_msrs) {
ae0f5499 2331 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2332 msr, data);
ed85c068
AP		 2333 return 1;
2334 } else {
796f4687 2335 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2336 msr, data);
ed85c068
AP		 2337 break;
2338 }
15c4a640
CO		 2339 }
2340 return 0;
2341}
2342EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2343
2344
2345/*
2346 * Reads an msr value (of 'msr_index') into 'pdata'.
2347 * Returns 0 on success, non-0 otherwise.
2348 * Assumes vcpu_load() was already called.
2349 */
609e36d3 2350int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2351{
609e36d3 2352 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2353}
ff651cb6 2354EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2355
890ca9ae 2356static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2357{
2358 u64 data;
890ca9ae
HY		 2359 u64 mcg_cap = vcpu->arch.mcg_cap;
2360 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2361
2362 switch (msr) {
15c4a640
CO		 2363 case MSR_IA32_P5_MC_ADDR:
2364 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2365 data = 0;
2366 break;
15c4a640 2367 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2368 data = vcpu->arch.mcg_cap;
2369 break;
c7ac679c 2370 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2371 if (!(mcg_cap & MCG_CTL_P))
2372 return 1;
2373 data = vcpu->arch.mcg_ctl;
2374 break;
2375 case MSR_IA32_MCG_STATUS:
2376 data = vcpu->arch.mcg_status;
2377 break;
2378 default:
2379 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2380 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2381 u32 offset = msr - MSR_IA32_MC0_CTL;
2382 data = vcpu->arch.mce_banks[offset];
2383 break;
2384 }
2385 return 1;
2386 }
2387 *pdata = data;
2388 return 0;
2389}
2390
609e36d3 2391int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2392{
609e36d3 2393 switch (msr_info->index) {
890ca9ae 2394 case MSR_IA32_PLATFORM_ID:
15c4a640 2395 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2396 case MSR_IA32_DEBUGCTLMSR:
2397 case MSR_IA32_LASTBRANCHFROMIP:
2398 case MSR_IA32_LASTBRANCHTOIP:
2399 case MSR_IA32_LASTINTFROMIP:
2400 case MSR_IA32_LASTINTTOIP:
60af2ecd 2401 case MSR_K8_SYSCFG:
3afb1121
PB		 2402 case MSR_K8_TSEG_ADDR:
2403 case MSR_K8_TSEG_MASK:
60af2ecd 2404 case MSR_K7_HWCR:
61a6bd67 2405 case MSR_VM_HSAVE_PA:
1fdbd48c 2406 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2407 case MSR_AMD64_NB_CFG:
f7c6d140 2408 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2409 case MSR_AMD64_BU_CFG2:
0c2df2a1 2410 case MSR_IA32_PERF_CTL:
405a353a 2411 case MSR_AMD64_DC_CFG:
609e36d3 2412 msr_info->data = 0;
15c4a640 2413 break;
6912ac32
WH		 2414 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2415 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2416 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2417 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2418 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2419 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2420 msr_info->data = 0;
5753785f 2421 break;
742bc670 2422 case MSR_IA32_UCODE_REV:
609e36d3 2423 msr_info->data = 0x100000000ULL;
742bc670 2424 break;
9ba075a6 2425 case MSR_MTRRcap:
9ba075a6 2426 case 0x200 ... 0x2ff:
ff53604b 2427 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2428 case 0xcd: /* fsb frequency */
609e36d3 2429 msr_info->data = 3;
15c4a640 2430 break;
7b914098
JS		 2431 /*
2432 * MSR_EBC_FREQUENCY_ID
2433 * Conservative value valid for even the basic CPU models.
2434 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2435 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2436 * and 266MHz for model 3, or 4. Set Core Clock
2437 * Frequency to System Bus Frequency Ratio to 1 (bits
2438 * 31:24) even though these are only valid for CPU
2439 * models > 2, however guests may end up dividing or
2440 * multiplying by zero otherwise.
2441 */
2442 case MSR_EBC_FREQUENCY_ID:
609e36d3 2443 msr_info->data = 1 << 24;
7b914098 2444 break;
15c4a640 2445 case MSR_IA32_APICBASE:
609e36d3 2446 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2447 break;
0105d1a5 2448 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2449 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2450 break;
a3e06bbe 2451 case MSR_IA32_TSCDEADLINE:
609e36d3 2452 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2453 break;
ba904635 2454 case MSR_IA32_TSC_ADJUST:
609e36d3 2455 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2456 break;
15c4a640 2457 case MSR_IA32_MISC_ENABLE:
609e36d3 2458 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2459 break;
64d60670
PB		 2460 case MSR_IA32_SMBASE:
2461 if (!msr_info->host_initiated)
2462 return 1;
2463 msr_info->data = vcpu->arch.smbase;
15c4a640 2464 break;
847f0ad8
AG		 2465 case MSR_IA32_PERF_STATUS:
2466 /* TSC increment by tick */
609e36d3 2467 msr_info->data = 1000ULL;
847f0ad8 2468 /* CPU multiplier */
b0996ae4 2469 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2470 break;
15c4a640 2471 case MSR_EFER:
609e36d3 2472 msr_info->data = vcpu->arch.efer;
15c4a640 2473 break;
18068523 2474 case MSR_KVM_WALL_CLOCK:
11c6bffa 2475 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2476 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2477 break;
2478 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2479 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2480 msr_info->data = vcpu->arch.time;
18068523 2481 break;
344d9588 2482 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2483 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2484 break;
c9aaa895 2485 case MSR_KVM_STEAL_TIME:
609e36d3 2486 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2487 break;
1d92128f 2488 case MSR_KVM_PV_EOI_EN:
609e36d3 2489 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2490 break;
890ca9ae
HY		 2491 case MSR_IA32_P5_MC_ADDR:
2492 case MSR_IA32_P5_MC_TYPE:
2493 case MSR_IA32_MCG_CAP:
2494 case MSR_IA32_MCG_CTL:
2495 case MSR_IA32_MCG_STATUS:
81760dcc 2496 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2497 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2498 case MSR_K7_CLK_CTL:
2499 /*
2500 * Provide expected ramp-up count for K7. All other
2501 * are set to zero, indicating minimum divisors for
2502 * every field.
2503 *
2504 * This prevents guest kernels on AMD host with CPU
2505 * type 6, model 8 and higher from exploding due to
2506 * the rdmsr failing.
2507 */
609e36d3 2508 msr_info->data = 0x20000000;
84e0cefa 2509 break;
55cd8e5a 2510 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2511 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2512 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2513 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2514 return kvm_hv_get_msr_common(vcpu,
2515 msr_info->index, &msr_info->data);
55cd8e5a 2516 break;
91c9c3ed 2517 case MSR_IA32_BBL_CR_CTL3:
2518 /* This legacy MSR exists but isn't fully documented in current
2519 * silicon. It is however accessed by winxp in very narrow
2520 * scenarios where it sets bit #19, itself documented as
2521 * a "reserved" bit. Best effort attempt to source coherent
2522 * read data here should the balance of the register be
2523 * interpreted by the guest:
2524 *
2525 * L2 cache control register 3: 64GB range, 256KB size,
2526 * enabled, latency 0x1, configured
2527 */
609e36d3 2528 msr_info->data = 0xbe702111;
91c9c3ed 2529 break;
2b036c6b 2530 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2531 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2532 return 1;
609e36d3 2533 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2534 break;
2535 case MSR_AMD64_OSVW_STATUS:
d6321d49 2536 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2537 return 1;
609e36d3 2538 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2539 break;
db2336a8
KH		 2540 case MSR_PLATFORM_INFO:
2541 msr_info->data = vcpu->arch.msr_platform_info;
2542 break;
2543 case MSR_MISC_FEATURES_ENABLES:
2544 msr_info->data = vcpu->arch.msr_misc_features_enables;
2545 break;
15c4a640 2546 default:
c6702c9d 2547 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2548 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2549 if (!ignore_msrs) {
ae0f5499
BD		 2550 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2551 msr_info->index);
ed85c068
AP		 2552 return 1;
2553 } else {
609e36d3
PB		 2554 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2555 msr_info->data = 0;
ed85c068
AP		 2556 }
2557 break;
15c4a640 2558 }
15c4a640
CO		 2559 return 0;
2560}
2561EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2562
313a3dc7
CO		 2563/*
2564 * Read or write a bunch of msrs. All parameters are kernel addresses.
2565 *
2566 * @return number of msrs set successfully.
2567 */
2568static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2569 struct kvm_msr_entry *entries,
2570 int (*do_msr)(struct kvm_vcpu *vcpu,
2571 unsigned index, u64 *data))
2572{
f656ce01 2573 int i, idx;
313a3dc7 2574
f656ce01 2575 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2576 for (i = 0; i < msrs->nmsrs; ++i)
2577 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2578 break;
f656ce01 2579 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2580
313a3dc7
CO		 2581 return i;
2582}
2583
2584/*
2585 * Read or write a bunch of msrs. Parameters are user addresses.
2586 *
2587 * @return number of msrs set successfully.
2588 */
2589static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2590 int (*do_msr)(struct kvm_vcpu *vcpu,
2591 unsigned index, u64 *data),
2592 int writeback)
2593{
2594 struct kvm_msrs msrs;
2595 struct kvm_msr_entry *entries;
2596 int r, n;
2597 unsigned size;
2598
2599 r = -EFAULT;
2600 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2601 goto out;
2602
2603 r = -E2BIG;
2604 if (msrs.nmsrs >= MAX_IO_MSRS)
2605 goto out;
2606
313a3dc7 2607 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2608 entries = memdup_user(user_msrs->entries, size);
2609 if (IS_ERR(entries)) {
2610 r = PTR_ERR(entries);
313a3dc7 2611 goto out;
ff5c2c03 2612 }
313a3dc7
CO		 2613
2614 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2615 if (r < 0)
2616 goto out_free;
2617
2618 r = -EFAULT;
2619 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2620 goto out_free;
2621
2622 r = n;
2623
2624out_free:
7a73c028 2625 kfree(entries);
313a3dc7
CO		 2626out:
2627 return r;
2628}
2629
784aa3d7 2630int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2631{
2632 int r;
2633
2634 switch (ext) {
2635 case KVM_CAP_IRQCHIP:
2636 case KVM_CAP_HLT:
2637 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2638 case KVM_CAP_SET_TSS_ADDR:
07716717 2639 case KVM_CAP_EXT_CPUID:
9c15bb1d 2640 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2641 case KVM_CAP_CLOCKSOURCE:
7837699f 2642 case KVM_CAP_PIT:
a28e4f5a 2643 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2644 case KVM_CAP_MP_STATE:
ed848624 2645 case KVM_CAP_SYNC_MMU:
a355c85c 2646 case KVM_CAP_USER_NMI:
52d939a0 2647 case KVM_CAP_REINJECT_CONTROL:
4925663a 2648 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2649 case KVM_CAP_IOEVENTFD:
f848a5a8 2650 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2651 case KVM_CAP_PIT2:
e9f42757 2652 case KVM_CAP_PIT_STATE2:
b927a3ce 2653 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2654 case KVM_CAP_XEN_HVM:
3cfc3092 2655 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2656 case KVM_CAP_HYPERV:
10388a07 2657 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2658 case KVM_CAP_HYPERV_SPIN:
5c919412 2659 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2660 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2661 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2662 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2663 case KVM_CAP_DEBUGREGS:
d2be1651 2664 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2665 case KVM_CAP_XSAVE:
344d9588 2666 case KVM_CAP_ASYNC_PF:
92a1f12d 2667 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2668 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2669 case KVM_CAP_READONLY_MEM:
5f66b620 2670 case KVM_CAP_HYPERV_TIME:
100943c5 2671 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2672 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2673 case KVM_CAP_ENABLE_CAP_VM:
2674 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2675 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2676 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2677 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2678 r = 1;
2679 break;
e3fd9a93
PB		 2680 case KVM_CAP_ADJUST_CLOCK:
2681 r = KVM_CLOCK_TSC_STABLE;
2682 break;
668fffa3
MT		 2683 case KVM_CAP_X86_GUEST_MWAIT:
2684 r = kvm_mwait_in_guest();
2685 break;
6d396b55
PB		 2686 case KVM_CAP_X86_SMM:
2687 /* SMBASE is usually relocated above 1M on modern chipsets,
2688 * and SMM handlers might indeed rely on 4G segment limits,
2689 * so do not report SMM to be available if real mode is
2690 * emulated via vm86 mode. Still, do not go to great lengths
2691 * to avoid userspace's usage of the feature, because it is a
2692 * fringe case that is not enabled except via specific settings
2693 * of the module parameters.
2694 */
2695 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2696 break;
774ead3a
AK		 2697 case KVM_CAP_VAPIC:
2698 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2699 break;
f725230a 2700 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2701 r = KVM_SOFT_MAX_VCPUS;
2702 break;
2703 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2704 r = KVM_MAX_VCPUS;
2705 break;
a988b910 2706 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2707 r = KVM_USER_MEM_SLOTS;
a988b910 2708 break;
a68a6a72
MT		 2709 case KVM_CAP_PV_MMU: /* obsolete */
2710 r = 0;
2f333bcb 2711 break;
890ca9ae
HY		 2712 case KVM_CAP_MCE:
2713 r = KVM_MAX_MCE_BANKS;
2714 break;
2d5b5a66 2715 case KVM_CAP_XCRS:
d366bf7e 2716 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2717 break;
92a1f12d
JR		 2718 case KVM_CAP_TSC_CONTROL:
2719 r = kvm_has_tsc_control;
2720 break;
37131313
RK		 2721 case KVM_CAP_X2APIC_API:
2722 r = KVM_X2APIC_API_VALID_FLAGS;
2723 break;
018d00d2
ZX		 2724 default:
2725 r = 0;
2726 break;
2727 }
2728 return r;
2729
2730}
2731
043405e1
CO		 2732long kvm_arch_dev_ioctl(struct file *filp,
2733 unsigned int ioctl, unsigned long arg)
2734{
2735 void __user *argp = (void __user *)arg;
2736 long r;
2737
2738 switch (ioctl) {
2739 case KVM_GET_MSR_INDEX_LIST: {
2740 struct kvm_msr_list __user *user_msr_list = argp;
2741 struct kvm_msr_list msr_list;
2742 unsigned n;
2743
2744 r = -EFAULT;
2745 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2746 goto out;
2747 n = msr_list.nmsrs;
62ef68bb 2748 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2749 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2750 goto out;
2751 r = -E2BIG;
e125e7b6 2752 if (n < msr_list.nmsrs)
043405e1
CO		 2753 goto out;
2754 r = -EFAULT;
2755 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2756 num_msrs_to_save * sizeof(u32)))
2757 goto out;
e125e7b6 2758 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2759 &emulated_msrs,
62ef68bb 2760 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2761 goto out;
2762 r = 0;
2763 break;
2764 }
9c15bb1d
BP		 2765 case KVM_GET_SUPPORTED_CPUID:
2766 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2767 struct kvm_cpuid2 __user *cpuid_arg = argp;
2768 struct kvm_cpuid2 cpuid;
2769
2770 r = -EFAULT;
2771 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2772 goto out;
9c15bb1d
BP		 2773
2774 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2775 ioctl);
674eea0f
AK		 2776 if (r)
2777 goto out;
2778
2779 r = -EFAULT;
2780 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2781 goto out;
2782 r = 0;
2783 break;
2784 }
890ca9ae 2785 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2786 r = -EFAULT;
c45dcc71
AR		 2787 if (copy_to_user(argp, &kvm_mce_cap_supported,
2788 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2789 goto out;
2790 r = 0;
2791 break;
2792 }
043405e1
CO		 2793 default:
2794 r = -EINVAL;
2795 }
2796out:
2797 return r;
2798}
2799
f5f48ee1
SY		 2800static void wbinvd_ipi(void *garbage)
2801{
2802 wbinvd();
2803}
2804
2805static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2806{
e0f0bbc5 2807 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2808}
2809
313a3dc7
CO		 2810void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2811{
f5f48ee1
SY		 2812 /* Address WBINVD may be executed by guest */
2813 if (need_emulate_wbinvd(vcpu)) {
2814 if (kvm_x86_ops->has_wbinvd_exit())
2815 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2816 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2817 smp_call_function_single(vcpu->cpu,
2818 wbinvd_ipi, NULL, 1);
2819 }
2820
313a3dc7 2821 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2822
0dd6a6ed
ZA		 2823 /* Apply any externally detected TSC adjustments (due to suspend) */
2824 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2825 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2826 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2827 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2828 }
8f6055cb 2829
48434c20 2830 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2831 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2832 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2833 if (tsc_delta < 0)
2834 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2835
c285545f 2836 if (check_tsc_unstable()) {
07c1419a 2837 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2838 vcpu->arch.last_guest_tsc);
a545ab6a 2839 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2840 vcpu->arch.tsc_catchup = 1;
c285545f 2841 }
a749e247
PB		 2842
2843 if (kvm_lapic_hv_timer_in_use(vcpu))
2844 kvm_lapic_restart_hv_timer(vcpu);
2845
d98d07ca
MT		 2846 /*
2847 * On a host with synchronized TSC, there is no need to update
2848 * kvmclock on vcpu->cpu migration
2849 */
2850 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2851 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2852 if (vcpu->cpu != cpu)
1bd2009e 2853 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2854 vcpu->cpu = cpu;
6b7d7e76 2855 }
c9aaa895 2856
c9aaa895 2857 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2858}
2859
0b9f6c46
PX		 2860static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2861{
2862 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2863 return;
2864
2865 vcpu->arch.st.steal.preempted = 1;
2866
4e335d9e 2867 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2868 &vcpu->arch.st.steal.preempted,
2869 offsetof(struct kvm_steal_time, preempted),
2870 sizeof(vcpu->arch.st.steal.preempted));
2871}
2872
313a3dc7
CO		 2873void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2874{
cc0d907c 2875 int idx;
de63ad4c
LM		 2876
2877 if (vcpu->preempted)
2878 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2879
931f261b
AA		 2880 /*
2881 * Disable page faults because we're in atomic context here.
2882 * kvm_write_guest_offset_cached() would call might_fault()
2883 * that relies on pagefault_disable() to tell if there's a
2884 * bug. NOTE: the write to guest memory may not go through if
2885 * during postcopy live migration or if there's heavy guest
2886 * paging.
2887 */
2888 pagefault_disable();
cc0d907c
AA		 2889 /*
2890 * kvm_memslots() will be called by
2891 * kvm_write_guest_offset_cached() so take the srcu lock.
2892 */
2893 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2894 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2895 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2896 pagefault_enable();
02daab21 2897 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2898 kvm_put_guest_fpu(vcpu);
4ea1636b 2899 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2900}
2901
313a3dc7
CO		 2902static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2903 struct kvm_lapic_state *s)
2904{
76dfafd5 2905 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2906 kvm_x86_ops->sync_pir_to_irr(vcpu);
2907
a92e2543 2908 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2909}
2910
2911static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2912 struct kvm_lapic_state *s)
2913{
a92e2543
RK		 2914 int r;
2915
2916 r = kvm_apic_set_state(vcpu, s);
2917 if (r)
2918 return r;
cb142eb7 2919 update_cr8_intercept(vcpu);
313a3dc7
CO		 2920
2921 return 0;
2922}
2923
127a457a
MG		 2924static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2925{
2926 return (!lapic_in_kernel(vcpu) ||
2927 kvm_apic_accept_pic_intr(vcpu));
2928}
2929
782d422b
MG		 2930/*
2931 * if userspace requested an interrupt window, check that the
2932 * interrupt window is open.
2933 *
2934 * No need to exit to userspace if we already have an interrupt queued.
2935 */
2936static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2937{
2938 return kvm_arch_interrupt_allowed(vcpu) &&
2939 !kvm_cpu_has_interrupt(vcpu) &&
2940 !kvm_event_needs_reinjection(vcpu) &&
2941 kvm_cpu_accept_dm_intr(vcpu);
2942}
2943
f77bc6a4
ZX		 2944static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2945 struct kvm_interrupt *irq)
2946{
02cdb50f 2947 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2948 return -EINVAL;
1c1a9ce9
SR		 2949
2950 if (!irqchip_in_kernel(vcpu->kvm)) {
2951 kvm_queue_interrupt(vcpu, irq->irq, false);
2952 kvm_make_request(KVM_REQ_EVENT, vcpu);
2953 return 0;
2954 }
2955
2956 /*
2957 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2958 * fail for in-kernel 8259.
2959 */
2960 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2961 return -ENXIO;
f77bc6a4 2962
1c1a9ce9
SR		 2963 if (vcpu->arch.pending_external_vector != -1)
2964 return -EEXIST;
f77bc6a4 2965
1c1a9ce9 2966 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2967 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2968 return 0;
2969}
2970
c4abb7c9
JK		 2971static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2972{
c4abb7c9 2973 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2974
2975 return 0;
2976}
2977
f077825a
PB		 2978static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2979{
64d60670
PB		 2980 kvm_make_request(KVM_REQ_SMI, vcpu);
2981
f077825a
PB		 2982 return 0;
2983}
2984
b209749f
AK		 2985static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2986 struct kvm_tpr_access_ctl *tac)
2987{
2988 if (tac->flags)
2989 return -EINVAL;
2990 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2991 return 0;
2992}
2993
890ca9ae
HY		 2994static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2995 u64 mcg_cap)
2996{
2997 int r;
2998 unsigned bank_num = mcg_cap & 0xff, bank;
2999
3000 r = -EINVAL;
a9e38c3e 3001 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3002 goto out;
c45dcc71 3003 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3004 goto out;
3005 r = 0;
3006 vcpu->arch.mcg_cap = mcg_cap;
3007 /* Init IA32_MCG_CTL to all 1s */
3008 if (mcg_cap & MCG_CTL_P)
3009 vcpu->arch.mcg_ctl = ~(u64)0;
3010 /* Init IA32_MCi_CTL to all 1s */
3011 for (bank = 0; bank < bank_num; bank++)
3012 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3013
3014 if (kvm_x86_ops->setup_mce)
3015 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3016out:
3017 return r;
3018}
3019
3020static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3021 struct kvm_x86_mce *mce)
3022{
3023 u64 mcg_cap = vcpu->arch.mcg_cap;
3024 unsigned bank_num = mcg_cap & 0xff;
3025 u64 *banks = vcpu->arch.mce_banks;
3026
3027 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3028 return -EINVAL;
3029 /*
3030 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3031 * reporting is disabled
3032 */
3033 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3034 vcpu->arch.mcg_ctl != ~(u64)0)
3035 return 0;
3036 banks += 4 * mce->bank;
3037 /*
3038 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3039 * reporting is disabled for the bank
3040 */
3041 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3042 return 0;
3043 if (mce->status & MCI_STATUS_UC) {
3044 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3045 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3046 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3047 return 0;
3048 }
3049 if (banks[1] & MCI_STATUS_VAL)
3050 mce->status |= MCI_STATUS_OVER;
3051 banks[2] = mce->addr;
3052 banks[3] = mce->misc;
3053 vcpu->arch.mcg_status = mce->mcg_status;
3054 banks[1] = mce->status;
3055 kvm_queue_exception(vcpu, MC_VECTOR);
3056 } else if (!(banks[1] & MCI_STATUS_VAL)
3057 || !(banks[1] & MCI_STATUS_UC)) {
3058 if (banks[1] & MCI_STATUS_VAL)
3059 mce->status |= MCI_STATUS_OVER;
3060 banks[2] = mce->addr;
3061 banks[3] = mce->misc;
3062 banks[1] = mce->status;
3063 } else
3064 banks[1] |= MCI_STATUS_OVER;
3065 return 0;
3066}
3067
3cfc3092
JK		 3068static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3069 struct kvm_vcpu_events *events)
3070{
7460fb4a 3071 process_nmi(vcpu);
03b82a30
JK		 3072 events->exception.injected =
3073 vcpu->arch.exception.pending &&
3074 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3075 events->exception.nr = vcpu->arch.exception.nr;
3076 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3077 events->exception.pad = 0;
3cfc3092
JK		 3078 events->exception.error_code = vcpu->arch.exception.error_code;
3079
03b82a30
JK		 3080 events->interrupt.injected =
3081 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3082 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3083 events->interrupt.soft = 0;
37ccdcbe 3084 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3085
3086 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3087 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3088 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3089 events->nmi.pad = 0;
3cfc3092 3090
66450a21 3091 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3092
f077825a
PB		 3093 events->smi.smm = is_smm(vcpu);
3094 events->smi.pending = vcpu->arch.smi_pending;
3095 events->smi.smm_inside_nmi =
3096 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3097 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3098
dab4b911 3099 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3100 | KVM_VCPUEVENT_VALID_SHADOW
3101 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3102 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3103}
3104
6ef4e07e
XG		 3105static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3106
3cfc3092
JK		 3107static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3108 struct kvm_vcpu_events *events)
3109{
dab4b911 3110 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3111 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3112 | KVM_VCPUEVENT_VALID_SHADOW
3113 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3114 return -EINVAL;
3115
78e546c8 3116 if (events->exception.injected &&
28d06353
JM		 3117 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3118 is_guest_mode(vcpu)))
78e546c8
PB		 3119 return -EINVAL;
3120
28bf2888
DH		 3121 /* INITs are latched while in SMM */
3122 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3123 (events->smi.smm || events->smi.pending) &&
3124 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3125 return -EINVAL;
3126
7460fb4a 3127 process_nmi(vcpu);
3cfc3092
JK		 3128 vcpu->arch.exception.pending = events->exception.injected;
3129 vcpu->arch.exception.nr = events->exception.nr;
3130 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3131 vcpu->arch.exception.error_code = events->exception.error_code;
3132
3133 vcpu->arch.interrupt.pending = events->interrupt.injected;
3134 vcpu->arch.interrupt.nr = events->interrupt.nr;
3135 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3136 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3137 kvm_x86_ops->set_interrupt_shadow(vcpu,
3138 events->interrupt.shadow);
3cfc3092
JK		 3139
3140 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3141 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3142 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3143 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3144
66450a21 3145 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3146 lapic_in_kernel(vcpu))
66450a21 3147 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3148
f077825a 3149 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3150 u32 hflags = vcpu->arch.hflags;
f077825a 3151 if (events->smi.smm)
6ef4e07e 3152 hflags |= HF_SMM_MASK;
f077825a 3153 else
6ef4e07e
XG		 3154 hflags &= ~HF_SMM_MASK;
3155 kvm_set_hflags(vcpu, hflags);
3156
f077825a 3157 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3158
3159 if (events->smi.smm) {
3160 if (events->smi.smm_inside_nmi)
3161 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3162 else
f4ef1910
WL		 3163 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3164 if (lapic_in_kernel(vcpu)) {
3165 if (events->smi.latched_init)
3166 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3167 else
3168 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3169 }
f077825a
PB		 3170 }
3171 }
3172
3842d135
AK		 3173 kvm_make_request(KVM_REQ_EVENT, vcpu);
3174
3cfc3092
JK		 3175 return 0;
3176}
3177
a1efbe77
JK		 3178static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3179 struct kvm_debugregs *dbgregs)
3180{
73aaf249
JK		 3181 unsigned long val;
3182
a1efbe77 3183 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3184 kvm_get_dr(vcpu, 6, &val);
73aaf249 3185 dbgregs->dr6 = val;
a1efbe77
JK		 3186 dbgregs->dr7 = vcpu->arch.dr7;
3187 dbgregs->flags = 0;
97e69aa6 3188 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3189}
3190
3191static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3192 struct kvm_debugregs *dbgregs)
3193{
3194 if (dbgregs->flags)
3195 return -EINVAL;
3196
d14bdb55
PB		 3197 if (dbgregs->dr6 & ~0xffffffffull)
3198 return -EINVAL;
3199 if (dbgregs->dr7 & ~0xffffffffull)
3200 return -EINVAL;
3201
a1efbe77 3202 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3203 kvm_update_dr0123(vcpu);
a1efbe77 3204 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3205 kvm_update_dr6(vcpu);
a1efbe77 3206 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3207 kvm_update_dr7(vcpu);
a1efbe77 3208
a1efbe77
JK		 3209 return 0;
3210}
3211
df1daba7
PB		 3212#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3213
3214static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3215{
c47ada30 3216 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3217 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3218 u64 valid;
3219
3220 /*
3221 * Copy legacy XSAVE area, to avoid complications with CPUID
3222 * leaves 0 and 1 in the loop below.
3223 */
3224 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3225
3226 /* Set XSTATE_BV */
00c87e9a 3227 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3228 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3229
3230 /*
3231 * Copy each region from the possibly compacted offset to the
3232 * non-compacted offset.
3233 */
d91cab78 3234 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3235 while (valid) {
3236 u64 feature = valid & -valid;
3237 int index = fls64(feature) - 1;
3238 void *src = get_xsave_addr(xsave, feature);
3239
3240 if (src) {
3241 u32 size, offset, ecx, edx;
3242 cpuid_count(XSTATE_CPUID, index,
3243 &size, &offset, &ecx, &edx);
3244 memcpy(dest + offset, src, size);
3245 }
3246
3247 valid -= feature;
3248 }
3249}
3250
3251static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3252{
c47ada30 3253 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3254 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3255 u64 valid;
3256
3257 /*
3258 * Copy legacy XSAVE area, to avoid complications with CPUID
3259 * leaves 0 and 1 in the loop below.
3260 */
3261 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3262
3263 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3264 xsave->header.xfeatures = xstate_bv;
782511b0 3265 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3266 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3267
3268 /*
3269 * Copy each region from the non-compacted offset to the
3270 * possibly compacted offset.
3271 */
d91cab78 3272 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3273 while (valid) {
3274 u64 feature = valid & -valid;
3275 int index = fls64(feature) - 1;
3276 void *dest = get_xsave_addr(xsave, feature);
3277
3278 if (dest) {
3279 u32 size, offset, ecx, edx;
3280 cpuid_count(XSTATE_CPUID, index,
3281 &size, &offset, &ecx, &edx);
3282 memcpy(dest, src + offset, size);
ee4100da 3283 }
df1daba7
PB		 3284
3285 valid -= feature;
3286 }
3287}
3288
2d5b5a66
SY		 3289static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3290 struct kvm_xsave *guest_xsave)
3291{
d366bf7e 3292 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3293 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3294 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3295 } else {
2d5b5a66 3296 memcpy(guest_xsave->region,
7366ed77 3297 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3298 sizeof(struct fxregs_state));
2d5b5a66 3299 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3300 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3301 }
3302}
3303
a575813b
WL		 3304#define XSAVE_MXCSR_OFFSET 24
3305
2d5b5a66
SY		 3306static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3307 struct kvm_xsave *guest_xsave)
3308{
3309 u64 xstate_bv =
3310 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3311 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3312
d366bf7e 3313 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3314 /*
3315 * Here we allow setting states that are not present in
3316 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3317 * with old userspace.
3318 */
a575813b
WL		 3319 if (xstate_bv & ~kvm_supported_xcr0() ||
3320 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3321 return -EINVAL;
df1daba7 3322 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3323 } else {
a575813b
WL		 3324 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3325 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3326 return -EINVAL;
7366ed77 3327 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3328 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3329 }
3330 return 0;
3331}
3332
3333static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3334 struct kvm_xcrs *guest_xcrs)
3335{
d366bf7e 3336 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3337 guest_xcrs->nr_xcrs = 0;
3338 return;
3339 }
3340
3341 guest_xcrs->nr_xcrs = 1;
3342 guest_xcrs->flags = 0;
3343 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3344 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3345}
3346
3347static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3348 struct kvm_xcrs *guest_xcrs)
3349{
3350 int i, r = 0;
3351
d366bf7e 3352 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3353 return -EINVAL;
3354
3355 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3356 return -EINVAL;
3357
3358 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3359 /* Only support XCR0 currently */
c67a04cb 3360 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3361 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3362 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3363 break;
3364 }
3365 if (r)
3366 r = -EINVAL;
3367 return r;
3368}
3369
1c0b28c2
EM		 3370/*
3371 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3372 * stopped by the hypervisor. This function will be called from the host only.
3373 * EINVAL is returned when the host attempts to set the flag for a guest that
3374 * does not support pv clocks.
3375 */
3376static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3377{
0b79459b 3378 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3379 return -EINVAL;
51d59c6b 3380 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3381 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3382 return 0;
3383}
3384
5c919412
AS		 3385static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3386 struct kvm_enable_cap *cap)
3387{
3388 if (cap->flags)
3389 return -EINVAL;
3390
3391 switch (cap->cap) {
efc479e6
RK		 3392 case KVM_CAP_HYPERV_SYNIC2:
3393 if (cap->args[0])
3394 return -EINVAL;
5c919412 3395 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3396 if (!irqchip_in_kernel(vcpu->kvm))
3397 return -EINVAL;
efc479e6
RK		 3398 return kvm_hv_activate_synic(vcpu, cap->cap ==
3399 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3400 default:
3401 return -EINVAL;
3402 }
3403}
3404
313a3dc7
CO		 3405long kvm_arch_vcpu_ioctl(struct file *filp,
3406 unsigned int ioctl, unsigned long arg)
3407{
3408 struct kvm_vcpu *vcpu = filp->private_data;
3409 void __user *argp = (void __user *)arg;
3410 int r;
d1ac91d8
AK		 3411 union {
3412 struct kvm_lapic_state *lapic;
3413 struct kvm_xsave *xsave;
3414 struct kvm_xcrs *xcrs;
3415 void *buffer;
3416 } u;
3417
3418 u.buffer = NULL;
313a3dc7
CO		 3419 switch (ioctl) {
3420 case KVM_GET_LAPIC: {
2204ae3c 3421 r = -EINVAL;
bce87cce 3422 if (!lapic_in_kernel(vcpu))
2204ae3c 3423 goto out;
d1ac91d8 3424 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3425
b772ff36 3426 r = -ENOMEM;
d1ac91d8 3427 if (!u.lapic)
b772ff36 3428 goto out;
d1ac91d8 3429 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3430 if (r)
3431 goto out;
3432 r = -EFAULT;
d1ac91d8 3433 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3434 goto out;
3435 r = 0;
3436 break;
3437 }
3438 case KVM_SET_LAPIC: {
2204ae3c 3439 r = -EINVAL;
bce87cce 3440 if (!lapic_in_kernel(vcpu))
2204ae3c 3441 goto out;
ff5c2c03 3442 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3443 if (IS_ERR(u.lapic))
3444 return PTR_ERR(u.lapic);
ff5c2c03 3445
d1ac91d8 3446 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3447 break;
3448 }
f77bc6a4
ZX		 3449 case KVM_INTERRUPT: {
3450 struct kvm_interrupt irq;
3451
3452 r = -EFAULT;
3453 if (copy_from_user(&irq, argp, sizeof irq))
3454 goto out;
3455 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3456 break;
3457 }
c4abb7c9
JK		 3458 case KVM_NMI: {
3459 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3460 break;
3461 }
f077825a
PB		 3462 case KVM_SMI: {
3463 r = kvm_vcpu_ioctl_smi(vcpu);
3464 break;
3465 }
313a3dc7
CO		 3466 case KVM_SET_CPUID: {
3467 struct kvm_cpuid __user *cpuid_arg = argp;
3468 struct kvm_cpuid cpuid;
3469
3470 r = -EFAULT;
3471 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3472 goto out;
3473 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3474 break;
3475 }
07716717
DK		 3476 case KVM_SET_CPUID2: {
3477 struct kvm_cpuid2 __user *cpuid_arg = argp;
3478 struct kvm_cpuid2 cpuid;
3479
3480 r = -EFAULT;
3481 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3482 goto out;
3483 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3484 cpuid_arg->entries);
07716717
DK		 3485 break;
3486 }
3487 case KVM_GET_CPUID2: {
3488 struct kvm_cpuid2 __user *cpuid_arg = argp;
3489 struct kvm_cpuid2 cpuid;
3490
3491 r = -EFAULT;
3492 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3493 goto out;
3494 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3495 cpuid_arg->entries);
07716717
DK		 3496 if (r)
3497 goto out;
3498 r = -EFAULT;
3499 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3500 goto out;
3501 r = 0;
3502 break;
3503 }
313a3dc7 3504 case KVM_GET_MSRS:
609e36d3 3505 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3506 break;
3507 case KVM_SET_MSRS:
3508 r = msr_io(vcpu, argp, do_set_msr, 0);
3509 break;
b209749f
AK		 3510 case KVM_TPR_ACCESS_REPORTING: {
3511 struct kvm_tpr_access_ctl tac;
3512
3513 r = -EFAULT;
3514 if (copy_from_user(&tac, argp, sizeof tac))
3515 goto out;
3516 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3517 if (r)
3518 goto out;
3519 r = -EFAULT;
3520 if (copy_to_user(argp, &tac, sizeof tac))
3521 goto out;
3522 r = 0;
3523 break;
3524 };
b93463aa
AK		 3525 case KVM_SET_VAPIC_ADDR: {
3526 struct kvm_vapic_addr va;
7301d6ab 3527 int idx;
b93463aa
AK		 3528
3529 r = -EINVAL;
35754c98 3530 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3531 goto out;
3532 r = -EFAULT;
3533 if (copy_from_user(&va, argp, sizeof va))
3534 goto out;
7301d6ab 3535 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3536 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3537 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3538 break;
3539 }
890ca9ae
HY		 3540 case KVM_X86_SETUP_MCE: {
3541 u64 mcg_cap;
3542
3543 r = -EFAULT;
3544 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3545 goto out;
3546 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3547 break;
3548 }
3549 case KVM_X86_SET_MCE: {
3550 struct kvm_x86_mce mce;
3551
3552 r = -EFAULT;
3553 if (copy_from_user(&mce, argp, sizeof mce))
3554 goto out;
3555 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3556 break;
3557 }
3cfc3092
JK		 3558 case KVM_GET_VCPU_EVENTS: {
3559 struct kvm_vcpu_events events;
3560
3561 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3562
3563 r = -EFAULT;
3564 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3565 break;
3566 r = 0;
3567 break;
3568 }
3569 case KVM_SET_VCPU_EVENTS: {
3570 struct kvm_vcpu_events events;
3571
3572 r = -EFAULT;
3573 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3574 break;
3575
3576 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3577 break;
3578 }
a1efbe77
JK		 3579 case KVM_GET_DEBUGREGS: {
3580 struct kvm_debugregs dbgregs;
3581
3582 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3583
3584 r = -EFAULT;
3585 if (copy_to_user(argp, &dbgregs,
3586 sizeof(struct kvm_debugregs)))
3587 break;
3588 r = 0;
3589 break;
3590 }
3591 case KVM_SET_DEBUGREGS: {
3592 struct kvm_debugregs dbgregs;
3593
3594 r = -EFAULT;
3595 if (copy_from_user(&dbgregs, argp,
3596 sizeof(struct kvm_debugregs)))
3597 break;
3598
3599 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3600 break;
3601 }
2d5b5a66 3602 case KVM_GET_XSAVE: {
d1ac91d8 3603 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3604 r = -ENOMEM;
d1ac91d8 3605 if (!u.xsave)
2d5b5a66
SY		 3606 break;
3607
d1ac91d8 3608 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3609
3610 r = -EFAULT;
d1ac91d8 3611 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3612 break;
3613 r = 0;
3614 break;
3615 }
3616 case KVM_SET_XSAVE: {
ff5c2c03 3617 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3618 if (IS_ERR(u.xsave))
3619 return PTR_ERR(u.xsave);
2d5b5a66 3620
d1ac91d8 3621 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3622 break;
3623 }
3624 case KVM_GET_XCRS: {
d1ac91d8 3625 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3626 r = -ENOMEM;
d1ac91d8 3627 if (!u.xcrs)
2d5b5a66
SY		 3628 break;
3629
d1ac91d8 3630 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3631
3632 r = -EFAULT;
d1ac91d8 3633 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3634 sizeof(struct kvm_xcrs)))
3635 break;
3636 r = 0;
3637 break;
3638 }
3639 case KVM_SET_XCRS: {
ff5c2c03 3640 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3641 if (IS_ERR(u.xcrs))
3642 return PTR_ERR(u.xcrs);
2d5b5a66 3643
d1ac91d8 3644 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3645 break;
3646 }
92a1f12d
JR		 3647 case KVM_SET_TSC_KHZ: {
3648 u32 user_tsc_khz;
3649
3650 r = -EINVAL;
92a1f12d
JR		 3651 user_tsc_khz = (u32)arg;
3652
3653 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3654 goto out;
3655
cc578287
ZA		 3656 if (user_tsc_khz == 0)
3657 user_tsc_khz = tsc_khz;
3658
381d585c
HZ		 3659 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3660 r = 0;
92a1f12d 3661
92a1f12d
JR		 3662 goto out;
3663 }
3664 case KVM_GET_TSC_KHZ: {
cc578287 3665 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3666 goto out;
3667 }
1c0b28c2
EM		 3668 case KVM_KVMCLOCK_CTRL: {
3669 r = kvm_set_guest_paused(vcpu);
3670 goto out;
3671 }
5c919412
AS		 3672 case KVM_ENABLE_CAP: {
3673 struct kvm_enable_cap cap;
3674
3675 r = -EFAULT;
3676 if (copy_from_user(&cap, argp, sizeof(cap)))
3677 goto out;
3678 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3679 break;
3680 }
313a3dc7
CO		 3681 default:
3682 r = -EINVAL;
3683 }
3684out:
d1ac91d8 3685 kfree(u.buffer);
313a3dc7
CO		 3686 return r;
3687}
3688
5b1c1493
CO		 3689int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3690{
3691 return VM_FAULT_SIGBUS;
3692}
3693
1fe779f8
CO		 3694static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3695{
3696 int ret;
3697
3698 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3699 return -EINVAL;
1fe779f8
CO		 3700 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3701 return ret;
3702}
3703
b927a3ce
SY		 3704static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3705 u64 ident_addr)
3706{
3707 kvm->arch.ept_identity_map_addr = ident_addr;
3708 return 0;
3709}
3710
1fe779f8
CO		 3711static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3712 u32 kvm_nr_mmu_pages)
3713{
3714 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3715 return -EINVAL;
3716
79fac95e 3717 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3718
3719 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3720 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3721
79fac95e 3722 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3723 return 0;
3724}
3725
3726static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3727{
39de71ec 3728 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3729}
3730
1fe779f8
CO		 3731static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3732{
90bca052 3733 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3734 int r;
3735
3736 r = 0;
3737 switch (chip->chip_id) {
3738 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3739 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3740 sizeof(struct kvm_pic_state));
3741 break;
3742 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3743 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3744 sizeof(struct kvm_pic_state));
3745 break;
3746 case KVM_IRQCHIP_IOAPIC:
33392b49 3747 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3748 break;
3749 default:
3750 r = -EINVAL;
3751 break;
3752 }
3753 return r;
3754}
3755
3756static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3757{
90bca052 3758 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3759 int r;
3760
3761 r = 0;
3762 switch (chip->chip_id) {
3763 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3764 spin_lock(&pic->lock);
3765 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3766 sizeof(struct kvm_pic_state));
90bca052 3767 spin_unlock(&pic->lock);
1fe779f8
CO		 3768 break;
3769 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3770 spin_lock(&pic->lock);
3771 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3772 sizeof(struct kvm_pic_state));
90bca052 3773 spin_unlock(&pic->lock);
1fe779f8
CO		 3774 break;
3775 case KVM_IRQCHIP_IOAPIC:
33392b49 3776 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3777 break;
3778 default:
3779 r = -EINVAL;
3780 break;
3781 }
90bca052 3782 kvm_pic_update_irq(pic);
1fe779f8
CO		 3783 return r;
3784}
3785
e0f63cb9
SY		 3786static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3787{
34f3941c
RK		 3788 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3789
3790 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3791
3792 mutex_lock(&kps->lock);
3793 memcpy(ps, &kps->channels, sizeof(*ps));
3794 mutex_unlock(&kps->lock);
2da29bcc 3795 return 0;
e0f63cb9
SY		 3796}
3797
3798static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3799{
0185604c 3800 int i;
09edea72
RK		 3801 struct kvm_pit *pit = kvm->arch.vpit;
3802
3803 mutex_lock(&pit->pit_state.lock);
34f3941c 3804 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3805 for (i = 0; i < 3; i++)
09edea72
RK		 3806 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3807 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3808 return 0;
e9f42757
BK		 3809}
3810
3811static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3812{
e9f42757
BK		 3813 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3814 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3815 sizeof(ps->channels));
3816 ps->flags = kvm->arch.vpit->pit_state.flags;
3817 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3818 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3819 return 0;
e9f42757
BK		 3820}
3821
3822static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3823{
2da29bcc 3824 int start = 0;
0185604c 3825 int i;
e9f42757 3826 u32 prev_legacy, cur_legacy;
09edea72
RK		 3827 struct kvm_pit *pit = kvm->arch.vpit;
3828
3829 mutex_lock(&pit->pit_state.lock);
3830 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3831 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3832 if (!prev_legacy && cur_legacy)
3833 start = 1;
09edea72
RK		 3834 memcpy(&pit->pit_state.channels, &ps->channels,
3835 sizeof(pit->pit_state.channels));
3836 pit->pit_state.flags = ps->flags;
0185604c 3837 for (i = 0; i < 3; i++)
09edea72 3838 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3839 start && i == 0);
09edea72 3840 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3841 return 0;
e0f63cb9
SY		 3842}
3843
52d939a0
MT		 3844static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3845 struct kvm_reinject_control *control)
3846{
71474e2f
RK		 3847 struct kvm_pit *pit = kvm->arch.vpit;
3848
3849 if (!pit)
52d939a0 3850 return -ENXIO;
b39c90b6 3851
71474e2f
RK		 3852 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3853 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3854 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3855 */
3856 mutex_lock(&pit->pit_state.lock);
3857 kvm_pit_set_reinject(pit, control->pit_reinject);
3858 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3859
52d939a0
MT		 3860 return 0;
3861}
3862
95d4c16c 3863/**
60c34612
TY		 3864 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3865 * @kvm: kvm instance
3866 * @log: slot id and address to which we copy the log
95d4c16c 3867 *
e108ff2f
PB		 3868 * Steps 1-4 below provide general overview of dirty page logging. See
3869 * kvm_get_dirty_log_protect() function description for additional details.
3870 *
3871 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3872 * always flush the TLB (step 4) even if previous step failed and the dirty
3873 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3874 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3875 * writes will be marked dirty for next log read.
95d4c16c 3876 *
60c34612
TY		 3877 * 1. Take a snapshot of the bit and clear it if needed.
3878 * 2. Write protect the corresponding page.
e108ff2f
PB		 3879 * 3. Copy the snapshot to the userspace.
3880 * 4. Flush TLB's if needed.
5bb064dc 3881 */
60c34612 3882int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3883{
60c34612 3884 bool is_dirty = false;
e108ff2f 3885 int r;
5bb064dc 3886
79fac95e 3887 mutex_lock(&kvm->slots_lock);
5bb064dc 3888
88178fd4
KH		 3889 /*
3890 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3891 */
3892 if (kvm_x86_ops->flush_log_dirty)
3893 kvm_x86_ops->flush_log_dirty(kvm);
3894
e108ff2f 3895 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3896
3897 /*
3898 * All the TLBs can be flushed out of mmu lock, see the comments in
3899 * kvm_mmu_slot_remove_write_access().
3900 */
e108ff2f 3901 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3902 if (is_dirty)
3903 kvm_flush_remote_tlbs(kvm);
3904
79fac95e 3905 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3906 return r;
3907}
3908
aa2fbe6d
YZ		 3909int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3910 bool line_status)
23d43cf9
CD		 3911{
3912 if (!irqchip_in_kernel(kvm))
3913 return -ENXIO;
3914
3915 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3916 irq_event->irq, irq_event->level,
3917 line_status);
23d43cf9
CD		 3918 return 0;
3919}
3920
90de4a18
NA		 3921static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3922 struct kvm_enable_cap *cap)
3923{
3924 int r;
3925
3926 if (cap->flags)
3927 return -EINVAL;
3928
3929 switch (cap->cap) {
3930 case KVM_CAP_DISABLE_QUIRKS:
3931 kvm->arch.disabled_quirks = cap->args[0];
3932 r = 0;
3933 break;
49df6397
SR		 3934 case KVM_CAP_SPLIT_IRQCHIP: {
3935 mutex_lock(&kvm->lock);
b053b2ae
SR		 3936 r = -EINVAL;
3937 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3938 goto split_irqchip_unlock;
49df6397
SR		 3939 r = -EEXIST;
3940 if (irqchip_in_kernel(kvm))
3941 goto split_irqchip_unlock;
557abc40 3942 if (kvm->created_vcpus)
49df6397
SR		 3943 goto split_irqchip_unlock;
3944 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3945 if (r)
49df6397
SR		 3946 goto split_irqchip_unlock;
3947 /* Pairs with irqchip_in_kernel. */
3948 smp_wmb();
49776faf 3949 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3950 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3951 r = 0;
3952split_irqchip_unlock:
3953 mutex_unlock(&kvm->lock);
3954 break;
3955 }
37131313
RK		 3956 case KVM_CAP_X2APIC_API:
3957 r = -EINVAL;
3958 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3959 break;
3960
3961 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3962 kvm->arch.x2apic_format = true;
c519265f
RK		 3963 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3964 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3965
3966 r = 0;
3967 break;
90de4a18
NA		 3968 default:
3969 r = -EINVAL;
3970 break;
3971 }
3972 return r;
3973}
3974
1fe779f8
CO		 3975long kvm_arch_vm_ioctl(struct file *filp,
3976 unsigned int ioctl, unsigned long arg)
3977{
3978 struct kvm *kvm = filp->private_data;
3979 void __user *argp = (void __user *)arg;
367e1319 3980 int r = -ENOTTY;
f0d66275
DH		 3981 /*
3982 * This union makes it completely explicit to gcc-3.x
3983 * that these two variables' stack usage should be
3984 * combined, not added together.
3985 */
3986 union {
3987 struct kvm_pit_state ps;
e9f42757 3988 struct kvm_pit_state2 ps2;
c5ff41ce 3989 struct kvm_pit_config pit_config;
f0d66275 3990 } u;
1fe779f8
CO		 3991
3992 switch (ioctl) {
3993 case KVM_SET_TSS_ADDR:
3994 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3995 break;
b927a3ce
SY		 3996 case KVM_SET_IDENTITY_MAP_ADDR: {
3997 u64 ident_addr;
3998
3999 r = -EFAULT;
4000 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4001 goto out;
4002 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4003 break;
4004 }
1fe779f8
CO		 4005 case KVM_SET_NR_MMU_PAGES:
4006 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4007 break;
4008 case KVM_GET_NR_MMU_PAGES:
4009 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4010 break;
3ddea128 4011 case KVM_CREATE_IRQCHIP: {
3ddea128 4012 mutex_lock(&kvm->lock);
09941366 4013
3ddea128 4014 r = -EEXIST;
35e6eaa3 4015 if (irqchip_in_kernel(kvm))
3ddea128 4016 goto create_irqchip_unlock;
09941366 4017
3e515705 4018 r = -EINVAL;
557abc40 4019 if (kvm->created_vcpus)
3e515705 4020 goto create_irqchip_unlock;
09941366
RK		 4021
4022 r = kvm_pic_init(kvm);
4023 if (r)
3ddea128 4024 goto create_irqchip_unlock;
09941366
RK		 4025
4026 r = kvm_ioapic_init(kvm);
4027 if (r) {
09941366 4028 kvm_pic_destroy(kvm);
3ddea128 4029 goto create_irqchip_unlock;
09941366
RK		 4030 }
4031
399ec807
AK		 4032 r = kvm_setup_default_irq_routing(kvm);
4033 if (r) {
72bb2fcd 4034 kvm_ioapic_destroy(kvm);
09941366 4035 kvm_pic_destroy(kvm);
71ba994c 4036 goto create_irqchip_unlock;
399ec807 4037 }
49776faf 4038 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4039 smp_wmb();
49776faf 4040 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4041 create_irqchip_unlock:
4042 mutex_unlock(&kvm->lock);
1fe779f8 4043 break;
3ddea128 4044 }
7837699f 4045 case KVM_CREATE_PIT:
c5ff41ce
JK		 4046 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4047 goto create_pit;
4048 case KVM_CREATE_PIT2:
4049 r = -EFAULT;
4050 if (copy_from_user(&u.pit_config, argp,
4051 sizeof(struct kvm_pit_config)))
4052 goto out;
4053 create_pit:
250715a6 4054 mutex_lock(&kvm->lock);
269e05e4
AK		 4055 r = -EEXIST;
4056 if (kvm->arch.vpit)
4057 goto create_pit_unlock;
7837699f 4058 r = -ENOMEM;
c5ff41ce 4059 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4060 if (kvm->arch.vpit)
4061 r = 0;
269e05e4 4062 create_pit_unlock:
250715a6 4063 mutex_unlock(&kvm->lock);
7837699f 4064 break;
1fe779f8
CO		 4065 case KVM_GET_IRQCHIP: {
4066 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4067 struct kvm_irqchip *chip;
1fe779f8 4068
ff5c2c03
SL		 4069 chip = memdup_user(argp, sizeof(*chip));
4070 if (IS_ERR(chip)) {
4071 r = PTR_ERR(chip);
1fe779f8 4072 goto out;
ff5c2c03
SL		 4073 }
4074
1fe779f8 4075 r = -ENXIO;
826da321 4076 if (!irqchip_kernel(kvm))
f0d66275
DH		 4077 goto get_irqchip_out;
4078 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4079 if (r)
f0d66275 4080 goto get_irqchip_out;
1fe779f8 4081 r = -EFAULT;
f0d66275
DH		 4082 if (copy_to_user(argp, chip, sizeof *chip))
4083 goto get_irqchip_out;
1fe779f8 4084 r = 0;
f0d66275
DH		 4085 get_irqchip_out:
4086 kfree(chip);
1fe779f8
CO		 4087 break;
4088 }
4089 case KVM_SET_IRQCHIP: {
4090 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4091 struct kvm_irqchip *chip;
1fe779f8 4092
ff5c2c03
SL		 4093 chip = memdup_user(argp, sizeof(*chip));
4094 if (IS_ERR(chip)) {
4095 r = PTR_ERR(chip);
1fe779f8 4096 goto out;
ff5c2c03
SL		 4097 }
4098
1fe779f8 4099 r = -ENXIO;
826da321 4100 if (!irqchip_kernel(kvm))
f0d66275
DH		 4101 goto set_irqchip_out;
4102 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4103 if (r)
f0d66275 4104 goto set_irqchip_out;
1fe779f8 4105 r = 0;
f0d66275
DH		 4106 set_irqchip_out:
4107 kfree(chip);
1fe779f8
CO		 4108 break;
4109 }
e0f63cb9 4110 case KVM_GET_PIT: {
e0f63cb9 4111 r = -EFAULT;
f0d66275 4112 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4113 goto out;
4114 r = -ENXIO;
4115 if (!kvm->arch.vpit)
4116 goto out;
f0d66275 4117 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4118 if (r)
4119 goto out;
4120 r = -EFAULT;
f0d66275 4121 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4122 goto out;
4123 r = 0;
4124 break;
4125 }
4126 case KVM_SET_PIT: {
e0f63cb9 4127 r = -EFAULT;
f0d66275 4128 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4129 goto out;
4130 r = -ENXIO;
4131 if (!kvm->arch.vpit)
4132 goto out;
f0d66275 4133 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4134 break;
4135 }
e9f42757
BK		 4136 case KVM_GET_PIT2: {
4137 r = -ENXIO;
4138 if (!kvm->arch.vpit)
4139 goto out;
4140 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4141 if (r)
4142 goto out;
4143 r = -EFAULT;
4144 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4145 goto out;
4146 r = 0;
4147 break;
4148 }
4149 case KVM_SET_PIT2: {
4150 r = -EFAULT;
4151 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4152 goto out;
4153 r = -ENXIO;
4154 if (!kvm->arch.vpit)
4155 goto out;
4156 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4157 break;
4158 }
52d939a0
MT		 4159 case KVM_REINJECT_CONTROL: {
4160 struct kvm_reinject_control control;
4161 r = -EFAULT;
4162 if (copy_from_user(&control, argp, sizeof(control)))
4163 goto out;
4164 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4165 break;
4166 }
d71ba788
PB		 4167 case KVM_SET_BOOT_CPU_ID:
4168 r = 0;
4169 mutex_lock(&kvm->lock);
557abc40 4170 if (kvm->created_vcpus)
d71ba788
PB		 4171 r = -EBUSY;
4172 else
4173 kvm->arch.bsp_vcpu_id = arg;
4174 mutex_unlock(&kvm->lock);
4175 break;
ffde22ac
ES		 4176 case KVM_XEN_HVM_CONFIG: {
4177 r = -EFAULT;
4178 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4179 sizeof(struct kvm_xen_hvm_config)))
4180 goto out;
4181 r = -EINVAL;
4182 if (kvm->arch.xen_hvm_config.flags)
4183 goto out;
4184 r = 0;
4185 break;
4186 }
afbcf7ab 4187 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4188 struct kvm_clock_data user_ns;
4189 u64 now_ns;
afbcf7ab
GC		 4190
4191 r = -EFAULT;
4192 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4193 goto out;
4194
4195 r = -EINVAL;
4196 if (user_ns.flags)
4197 goto out;
4198
4199 r = 0;
0bc48bea
RK		 4200 /*
4201 * TODO: userspace has to take care of races with VCPU_RUN, so
4202 * kvm_gen_update_masterclock() can be cut down to locked
4203 * pvclock_update_vm_gtod_copy().
4204 */
4205 kvm_gen_update_masterclock(kvm);
e891a32e 4206 now_ns = get_kvmclock_ns(kvm);
108b249c 4207 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4208 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4209 break;
4210 }
4211 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4212 struct kvm_clock_data user_ns;
4213 u64 now_ns;
4214
e891a32e 4215 now_ns = get_kvmclock_ns(kvm);
108b249c 4216 user_ns.clock = now_ns;
e3fd9a93 4217 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4218 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4219
4220 r = -EFAULT;
4221 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4222 goto out;
4223 r = 0;
4224 break;
4225 }
90de4a18
NA		 4226 case KVM_ENABLE_CAP: {
4227 struct kvm_enable_cap cap;
afbcf7ab 4228
90de4a18
NA		 4229 r = -EFAULT;
4230 if (copy_from_user(&cap, argp, sizeof(cap)))
4231 goto out;
4232 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4233 break;
4234 }
1fe779f8 4235 default:
ad6260da 4236 r = -ENOTTY;
1fe779f8
CO		 4237 }
4238out:
4239 return r;
4240}
4241
a16b043c 4242static void kvm_init_msr_list(void)
043405e1
CO		 4243{
4244 u32 dummy[2];
4245 unsigned i, j;
4246
62ef68bb 4247 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4248 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4249 continue;
93c4adc7
PB		 4250
4251 /*
4252 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4253 * to the guests in some cases.
93c4adc7
PB		 4254 */
4255 switch (msrs_to_save[i]) {
4256 case MSR_IA32_BNDCFGS:
4257 if (!kvm_x86_ops->mpx_supported())
4258 continue;
4259 break;
9dbe6cf9
PB		 4260 case MSR_TSC_AUX:
4261 if (!kvm_x86_ops->rdtscp_supported())
4262 continue;
4263 break;
93c4adc7
PB		 4264 default:
4265 break;
4266 }
4267
043405e1
CO		 4268 if (j < i)
4269 msrs_to_save[j] = msrs_to_save[i];
4270 j++;
4271 }
4272 num_msrs_to_save = j;
62ef68bb
PB		 4273
4274 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4275 switch (emulated_msrs[i]) {
6d396b55
PB		 4276 case MSR_IA32_SMBASE:
4277 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4278 continue;
4279 break;
62ef68bb
PB		 4280 default:
4281 break;
4282 }
4283
4284 if (j < i)
4285 emulated_msrs[j] = emulated_msrs[i];
4286 j++;
4287 }
4288 num_emulated_msrs = j;
043405e1
CO		 4289}
4290
bda9020e
MT		 4291static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4292 const void *v)
bbd9b64e 4293{
70252a10
AK		 4294 int handled = 0;
4295 int n;
4296
4297 do {
4298 n = min(len, 8);
bce87cce 4299 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4300 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4301 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4302 break;
4303 handled += n;
4304 addr += n;
4305 len -= n;
4306 v += n;
4307 } while (len);
bbd9b64e 4308
70252a10 4309 return handled;
bbd9b64e
CO		 4310}
4311
bda9020e 4312static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4313{
70252a10
AK		 4314 int handled = 0;
4315 int n;
4316
4317 do {
4318 n = min(len, 8);
bce87cce 4319 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4320 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4321 addr, n, v))
4322 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4323 break;
4324 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4325 handled += n;
4326 addr += n;
4327 len -= n;
4328 v += n;
4329 } while (len);
bbd9b64e 4330
70252a10 4331 return handled;
bbd9b64e
CO		 4332}
4333
2dafc6c2
GN		 4334static void kvm_set_segment(struct kvm_vcpu *vcpu,
4335 struct kvm_segment *var, int seg)
4336{
4337 kvm_x86_ops->set_segment(vcpu, var, seg);
4338}
4339
4340void kvm_get_segment(struct kvm_vcpu *vcpu,
4341 struct kvm_segment *var, int seg)
4342{
4343 kvm_x86_ops->get_segment(vcpu, var, seg);
4344}
4345
54987b7a
PB		 4346gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4347 struct x86_exception *exception)
02f59dc9
JR		 4348{
4349 gpa_t t_gpa;
02f59dc9
JR		 4350
4351 BUG_ON(!mmu_is_nested(vcpu));
4352
4353 /* NPT walks are always user-walks */
4354 access |= PFERR_USER_MASK;
54987b7a 4355 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4356
4357 return t_gpa;
4358}
4359
ab9ae313
AK		 4360gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4361 struct x86_exception *exception)
1871c602
GN		 4362{
4363 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4364 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4365}
4366
ab9ae313
AK		 4367 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4368 struct x86_exception *exception)
1871c602
GN		 4369{
4370 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4371 access |= PFERR_FETCH_MASK;
ab9ae313 4372 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4373}
4374
ab9ae313
AK		 4375gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4376 struct x86_exception *exception)
1871c602
GN		 4377{
4378 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4379 access |= PFERR_WRITE_MASK;
ab9ae313 4380 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4381}
4382
4383/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4384gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4385 struct x86_exception *exception)
1871c602 4386{
ab9ae313 4387 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4388}
4389
4390static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4391 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4392 struct x86_exception *exception)
bbd9b64e
CO		 4393{
4394 void *data = val;
10589a46 4395 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4396
4397 while (bytes) {
14dfe855 4398 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4399 exception);
bbd9b64e 4400 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4401 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4402 int ret;
4403
bcc55cba 4404 if (gpa == UNMAPPED_GVA)
ab9ae313 4405 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4406 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4407 offset, toread);
10589a46 4408 if (ret < 0) {
c3cd7ffa 4409 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4410 goto out;
4411 }
bbd9b64e 4412
77c2002e
IE		 4413 bytes -= toread;
4414 data += toread;
4415 addr += toread;
bbd9b64e 4416 }
10589a46 4417out:
10589a46 4418 return r;
bbd9b64e 4419}
77c2002e 4420
1871c602 4421/* used for instruction fetching */
0f65dd70
AK		 4422static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4423 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4424 struct x86_exception *exception)
1871c602 4425{
0f65dd70 4426 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4427 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4428 unsigned offset;
4429 int ret;
0f65dd70 4430
44583cba
PB		 4431 /* Inline kvm_read_guest_virt_helper for speed. */
4432 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4433 exception);
4434 if (unlikely(gpa == UNMAPPED_GVA))
4435 return X86EMUL_PROPAGATE_FAULT;
4436
4437 offset = addr & (PAGE_SIZE-1);
4438 if (WARN_ON(offset + bytes > PAGE_SIZE))
4439 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4440 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4441 offset, bytes);
44583cba
PB		 4442 if (unlikely(ret < 0))
4443 return X86EMUL_IO_NEEDED;
4444
4445 return X86EMUL_CONTINUE;
1871c602
GN		 4446}
4447
064aea77 4448int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4449 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4450 struct x86_exception *exception)
1871c602 4451{
0f65dd70 4452 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4453 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4454
1871c602 4455 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4456 exception);
1871c602 4457}
064aea77 4458EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4459
0f65dd70
AK		 4460static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4461 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4462 struct x86_exception *exception)
1871c602 4463{
0f65dd70 4464 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4465 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4466}
4467
7a036a6f
RK		 4468static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4469 unsigned long addr, void *val, unsigned int bytes)
4470{
4471 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4472 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4473
4474 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4475}
4476
6a4d7550 4477int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4478 gva_t addr, void *val,
2dafc6c2 4479 unsigned int bytes,
bcc55cba 4480 struct x86_exception *exception)
77c2002e 4481{
0f65dd70 4482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4483 void *data = val;
4484 int r = X86EMUL_CONTINUE;
4485
4486 while (bytes) {
14dfe855
JR		 4487 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4488 PFERR_WRITE_MASK,
ab9ae313 4489 exception);
77c2002e
IE		 4490 unsigned offset = addr & (PAGE_SIZE-1);
4491 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4492 int ret;
4493
bcc55cba 4494 if (gpa == UNMAPPED_GVA)
ab9ae313 4495 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4496 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4497 if (ret < 0) {
c3cd7ffa 4498 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4499 goto out;
4500 }
4501
4502 bytes -= towrite;
4503 data += towrite;
4504 addr += towrite;
4505 }
4506out:
4507 return r;
4508}
6a4d7550 4509EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4510
0f89b207
TL		 4511static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4512 gpa_t gpa, bool write)
4513{
4514 /* For APIC access vmexit */
4515 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4516 return 1;
4517
4518 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4519 trace_vcpu_match_mmio(gva, gpa, write, true);
4520 return 1;
4521 }
4522
4523 return 0;
4524}
4525
af7cc7d1
XG		 4526static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4527 gpa_t *gpa, struct x86_exception *exception,
4528 bool write)
4529{
97d64b78
AK		 4530 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4531 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4532
be94f6b7
HH		 4533 /*
4534 * currently PKRU is only applied to ept enabled guest so
4535 * there is no pkey in EPT page table for L1 guest or EPT
4536 * shadow page table for L2 guest.
4537 */
97d64b78 4538 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4539 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4540 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4541 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4542 (gva & (PAGE_SIZE - 1));
4f022648 4543 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4544 return 1;
4545 }
4546
af7cc7d1
XG		 4547 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4548
4549 if (*gpa == UNMAPPED_GVA)
4550 return -1;
4551
0f89b207 4552 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4553}
4554
3200f405 4555int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4556 const void *val, int bytes)
bbd9b64e
CO		 4557{
4558 int ret;
4559
54bf36aa 4560 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4561 if (ret < 0)
bbd9b64e 4562 return 0;
0eb05bf2 4563 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4564 return 1;
4565}
4566
77d197b2
XG		 4567struct read_write_emulator_ops {
4568 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4569 int bytes);
4570 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4571 void *val, int bytes);
4572 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4573 int bytes, void *val);
4574 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4575 void *val, int bytes);
4576 bool write;
4577};
4578
4579static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4580{
4581 if (vcpu->mmio_read_completed) {
77d197b2 4582 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4583 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4584 vcpu->mmio_read_completed = 0;
4585 return 1;
4586 }
4587
4588 return 0;
4589}
4590
4591static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4592 void *val, int bytes)
4593{
54bf36aa 4594 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4595}
4596
4597static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4598 void *val, int bytes)
4599{
4600 return emulator_write_phys(vcpu, gpa, val, bytes);
4601}
4602
4603static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4604{
4605 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4606 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4607}
4608
4609static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4610 void *val, int bytes)
4611{
4612 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4613 return X86EMUL_IO_NEEDED;
4614}
4615
4616static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4617 void *val, int bytes)
4618{
f78146b0
AK		 4619 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4620
87da7e66 4621 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4622 return X86EMUL_CONTINUE;
4623}
4624
0fbe9b0b 4625static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4626 .read_write_prepare = read_prepare,
4627 .read_write_emulate = read_emulate,
4628 .read_write_mmio = vcpu_mmio_read,
4629 .read_write_exit_mmio = read_exit_mmio,
4630};
4631
0fbe9b0b 4632static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4633 .read_write_emulate = write_emulate,
4634 .read_write_mmio = write_mmio,
4635 .read_write_exit_mmio = write_exit_mmio,
4636 .write = true,
4637};
4638
22388a3c
XG		 4639static int emulator_read_write_onepage(unsigned long addr, void *val,
4640 unsigned int bytes,
4641 struct x86_exception *exception,
4642 struct kvm_vcpu *vcpu,
0fbe9b0b 4643 const struct read_write_emulator_ops *ops)
bbd9b64e 4644{
af7cc7d1
XG		 4645 gpa_t gpa;
4646 int handled, ret;
22388a3c 4647 bool write = ops->write;
f78146b0 4648 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4649 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4650
4651 /*
4652 * If the exit was due to a NPF we may already have a GPA.
4653 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4654 * Note, this cannot be used on string operations since string
4655 * operation using rep will only have the initial GPA from the NPF
4656 * occurred.
4657 */
4658 if (vcpu->arch.gpa_available &&
4659 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4660 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4661 gpa = vcpu->arch.gpa_val;
4662 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4663 } else {
4664 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4665 if (ret < 0)
4666 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4667 }
10589a46 4668
618232e2 4669 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4670 return X86EMUL_CONTINUE;
4671
bbd9b64e
CO		 4672 /*
4673 * Is this MMIO handled locally?
4674 */
22388a3c 4675 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4676 if (handled == bytes)
bbd9b64e 4677 return X86EMUL_CONTINUE;
bbd9b64e 4678
70252a10
AK		 4679 gpa += handled;
4680 bytes -= handled;
4681 val += handled;
4682
87da7e66
XG		 4683 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4684 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4685 frag->gpa = gpa;
4686 frag->data = val;
4687 frag->len = bytes;
f78146b0 4688 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4689}
4690
52eb5a6d
XL		 4691static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4692 unsigned long addr,
22388a3c
XG		 4693 void *val, unsigned int bytes,
4694 struct x86_exception *exception,
0fbe9b0b 4695 const struct read_write_emulator_ops *ops)
bbd9b64e 4696{
0f65dd70 4697 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4698 gpa_t gpa;
4699 int rc;
4700
4701 if (ops->read_write_prepare &&
4702 ops->read_write_prepare(vcpu, val, bytes))
4703 return X86EMUL_CONTINUE;
4704
4705 vcpu->mmio_nr_fragments = 0;
0f65dd70 4706
bbd9b64e
CO		 4707 /* Crossing a page boundary? */
4708 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4709 int now;
bbd9b64e
CO		 4710
4711 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4712 rc = emulator_read_write_onepage(addr, val, now, exception,
4713 vcpu, ops);
4714
bbd9b64e
CO		 4715 if (rc != X86EMUL_CONTINUE)
4716 return rc;
4717 addr += now;
bac15531
NA		 4718 if (ctxt->mode != X86EMUL_MODE_PROT64)
4719 addr = (u32)addr;
bbd9b64e
CO		 4720 val += now;
4721 bytes -= now;
4722 }
22388a3c 4723
f78146b0
AK		 4724 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4725 vcpu, ops);
4726 if (rc != X86EMUL_CONTINUE)
4727 return rc;
4728
4729 if (!vcpu->mmio_nr_fragments)
4730 return rc;
4731
4732 gpa = vcpu->mmio_fragments[0].gpa;
4733
4734 vcpu->mmio_needed = 1;
4735 vcpu->mmio_cur_fragment = 0;
4736
87da7e66 4737 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4738 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4739 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4740 vcpu->run->mmio.phys_addr = gpa;
4741
4742 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4743}
4744
4745static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4746 unsigned long addr,
4747 void *val,
4748 unsigned int bytes,
4749 struct x86_exception *exception)
4750{
4751 return emulator_read_write(ctxt, addr, val, bytes,
4752 exception, &read_emultor);
4753}
4754
52eb5a6d 4755static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4756 unsigned long addr,
4757 const void *val,
4758 unsigned int bytes,
4759 struct x86_exception *exception)
4760{
4761 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4762 exception, &write_emultor);
bbd9b64e 4763}
bbd9b64e 4764
daea3e73
AK		 4765#define CMPXCHG_TYPE(t, ptr, old, new) \
4766 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4767
4768#ifdef CONFIG_X86_64
4769# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4770#else
4771# define CMPXCHG64(ptr, old, new) \
9749a6c0 4772 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4773#endif
4774
0f65dd70
AK		 4775static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4776 unsigned long addr,
bbd9b64e
CO		 4777 const void *old,
4778 const void *new,
4779 unsigned int bytes,
0f65dd70 4780 struct x86_exception *exception)
bbd9b64e 4781{
0f65dd70 4782 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4783 gpa_t gpa;
4784 struct page *page;
4785 char *kaddr;
4786 bool exchanged;
2bacc55c 4787
daea3e73
AK		 4788 /* guests cmpxchg8b have to be emulated atomically */
4789 if (bytes > 8 || (bytes & (bytes - 1)))
4790 goto emul_write;
10589a46 4791
daea3e73 4792 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4793
daea3e73
AK		 4794 if (gpa == UNMAPPED_GVA ||
4795 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4796 goto emul_write;
2bacc55c 4797
daea3e73
AK		 4798 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4799 goto emul_write;
72dc67a6 4800
54bf36aa 4801 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4802 if (is_error_page(page))
c19b8bd6 4803 goto emul_write;
72dc67a6 4804
8fd75e12 4805 kaddr = kmap_atomic(page);
daea3e73
AK		 4806 kaddr += offset_in_page(gpa);
4807 switch (bytes) {
4808 case 1:
4809 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4810 break;
4811 case 2:
4812 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4813 break;
4814 case 4:
4815 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4816 break;
4817 case 8:
4818 exchanged = CMPXCHG64(kaddr, old, new);
4819 break;
4820 default:
4821 BUG();
2bacc55c 4822 }
8fd75e12 4823 kunmap_atomic(kaddr);
daea3e73
AK		 4824 kvm_release_page_dirty(page);
4825
4826 if (!exchanged)
4827 return X86EMUL_CMPXCHG_FAILED;
4828
54bf36aa 4829 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4830 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4831
4832 return X86EMUL_CONTINUE;
4a5f48f6 4833
3200f405 4834emul_write:
daea3e73 4835 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4836
0f65dd70 4837 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4838}
4839
cf8f70bf
GN		 4840static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4841{
cbfc6c91 4842 int r = 0, i;
cf8f70bf 4843
cbfc6c91
WL		 4844 for (i = 0; i < vcpu->arch.pio.count; i++) {
4845 if (vcpu->arch.pio.in)
4846 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4847 vcpu->arch.pio.size, pd);
4848 else
4849 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4850 vcpu->arch.pio.port, vcpu->arch.pio.size,
4851 pd);
4852 if (r)
4853 break;
4854 pd += vcpu->arch.pio.size;
4855 }
cf8f70bf
GN		 4856 return r;
4857}
4858
6f6fbe98
XG		 4859static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4860 unsigned short port, void *val,
4861 unsigned int count, bool in)
cf8f70bf 4862{
cf8f70bf 4863 vcpu->arch.pio.port = port;
6f6fbe98 4864 vcpu->arch.pio.in = in;
7972995b 4865 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4866 vcpu->arch.pio.size = size;
4867
4868 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4869 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4870 return 1;
4871 }
4872
4873 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4874 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4875 vcpu->run->io.size = size;
4876 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4877 vcpu->run->io.count = count;
4878 vcpu->run->io.port = port;
4879
4880 return 0;
4881}
4882
6f6fbe98
XG		 4883static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4884 int size, unsigned short port, void *val,
4885 unsigned int count)
cf8f70bf 4886{
ca1d4a9e 4887 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4888 int ret;
ca1d4a9e 4889
6f6fbe98
XG		 4890 if (vcpu->arch.pio.count)
4891 goto data_avail;
cf8f70bf 4892
cbfc6c91
WL		 4893 memset(vcpu->arch.pio_data, 0, size * count);
4894
6f6fbe98
XG		 4895 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4896 if (ret) {
4897data_avail:
4898 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4899 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4900 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4901 return 1;
4902 }
4903
cf8f70bf
GN		 4904 return 0;
4905}
4906
6f6fbe98
XG		 4907static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4908 int size, unsigned short port,
4909 const void *val, unsigned int count)
4910{
4911 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4912
4913 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4914 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4915 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4916}
4917
bbd9b64e
CO		 4918static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4919{
4920 return kvm_x86_ops->get_segment_base(vcpu, seg);
4921}
4922
3cb16fe7 4923static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4924{
3cb16fe7 4925 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4926}
4927
ae6a2375 4928static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4929{
4930 if (!need_emulate_wbinvd(vcpu))
4931 return X86EMUL_CONTINUE;
4932
4933 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4934 int cpu = get_cpu();
4935
4936 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4937 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4938 wbinvd_ipi, NULL, 1);
2eec7343 4939 put_cpu();
f5f48ee1 4940 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4941 } else
4942 wbinvd();
f5f48ee1
SY		 4943 return X86EMUL_CONTINUE;
4944}
5cb56059
JS		 4945
4946int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4947{
6affcbed
KH		 4948 kvm_emulate_wbinvd_noskip(vcpu);
4949 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4950}
f5f48ee1
SY		 4951EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4952
5cb56059
JS		 4953
4954
bcaf5cc5
AK		 4955static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4956{
5cb56059 4957 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4958}
4959
52eb5a6d
XL		 4960static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4961 unsigned long *dest)
bbd9b64e 4962{
16f8a6f9 4963 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4964}
4965
52eb5a6d
XL		 4966static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4967 unsigned long value)
bbd9b64e 4968{
338dbc97 4969
717746e3 4970 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4971}
4972
52a46617 4973static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4974{
52a46617 4975 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4976}
4977
717746e3 4978static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4979{
717746e3 4980 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4981 unsigned long value;
4982
4983 switch (cr) {
4984 case 0:
4985 value = kvm_read_cr0(vcpu);
4986 break;
4987 case 2:
4988 value = vcpu->arch.cr2;
4989 break;
4990 case 3:
9f8fe504 4991 value = kvm_read_cr3(vcpu);
52a46617
GN		 4992 break;
4993 case 4:
4994 value = kvm_read_cr4(vcpu);
4995 break;
4996 case 8:
4997 value = kvm_get_cr8(vcpu);
4998 break;
4999 default:
a737f256 5000 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5001 return 0;
5002 }
5003
5004 return value;
5005}
5006
717746e3 5007static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5008{
717746e3 5009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5010 int res = 0;
5011
52a46617
GN		 5012 switch (cr) {
5013 case 0:
49a9b07e 5014 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5015 break;
5016 case 2:
5017 vcpu->arch.cr2 = val;
5018 break;
5019 case 3:
2390218b 5020 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5021 break;
5022 case 4:
a83b29c6 5023 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5024 break;
5025 case 8:
eea1cff9 5026 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5027 break;
5028 default:
a737f256 5029 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5030 res = -1;
52a46617 5031 }
0f12244f
GN		 5032
5033 return res;
52a46617
GN		 5034}
5035
717746e3 5036static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5037{
717746e3 5038 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5039}
5040
4bff1e86 5041static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5042{
4bff1e86 5043 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5044}
5045
4bff1e86 5046static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5047{
4bff1e86 5048 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5049}
5050
1ac9d0cf
AK		 5051static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5052{
5053 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5054}
5055
5056static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5057{
5058 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5059}
5060
4bff1e86
AK		 5061static unsigned long emulator_get_cached_segment_base(
5062 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5063{
4bff1e86 5064 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5065}
5066
1aa36616
AK		 5067static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5068 struct desc_struct *desc, u32 *base3,
5069 int seg)
2dafc6c2
GN		 5070{
5071 struct kvm_segment var;
5072
4bff1e86 5073 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5074 *selector = var.selector;
2dafc6c2 5075
378a8b09
GN		 5076 if (var.unusable) {
5077 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5078 if (base3)
5079 *base3 = 0;
2dafc6c2 5080 return false;
378a8b09 5081 }
2dafc6c2
GN		 5082
5083 if (var.g)
5084 var.limit >>= 12;
5085 set_desc_limit(desc, var.limit);
5086 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5087#ifdef CONFIG_X86_64
5088 if (base3)
5089 *base3 = var.base >> 32;
5090#endif
2dafc6c2
GN		 5091 desc->type = var.type;
5092 desc->s = var.s;
5093 desc->dpl = var.dpl;
5094 desc->p = var.present;
5095 desc->avl = var.avl;
5096 desc->l = var.l;
5097 desc->d = var.db;
5098 desc->g = var.g;
5099
5100 return true;
5101}
5102
1aa36616
AK		 5103static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5104 struct desc_struct *desc, u32 base3,
5105 int seg)
2dafc6c2 5106{
4bff1e86 5107 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5108 struct kvm_segment var;
5109
1aa36616 5110 var.selector = selector;
2dafc6c2 5111 var.base = get_desc_base(desc);
5601d05b
GN		 5112#ifdef CONFIG_X86_64
5113 var.base |= ((u64)base3) << 32;
5114#endif
2dafc6c2
GN		 5115 var.limit = get_desc_limit(desc);
5116 if (desc->g)
5117 var.limit = (var.limit << 12) | 0xfff;
5118 var.type = desc->type;
2dafc6c2
GN		 5119 var.dpl = desc->dpl;
5120 var.db = desc->d;
5121 var.s = desc->s;
5122 var.l = desc->l;
5123 var.g = desc->g;
5124 var.avl = desc->avl;
5125 var.present = desc->p;
5126 var.unusable = !var.present;
5127 var.padding = 0;
5128
5129 kvm_set_segment(vcpu, &var, seg);
5130 return;
5131}
5132
717746e3
AK		 5133static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5134 u32 msr_index, u64 *pdata)
5135{
609e36d3
PB		 5136 struct msr_data msr;
5137 int r;
5138
5139 msr.index = msr_index;
5140 msr.host_initiated = false;
5141 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5142 if (r)
5143 return r;
5144
5145 *pdata = msr.data;
5146 return 0;
717746e3
AK		 5147}
5148
5149static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5150 u32 msr_index, u64 data)
5151{
8fe8ab46
WA		 5152 struct msr_data msr;
5153
5154 msr.data = data;
5155 msr.index = msr_index;
5156 msr.host_initiated = false;
5157 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5158}
5159
64d60670
PB		 5160static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5161{
5162 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5163
5164 return vcpu->arch.smbase;
5165}
5166
5167static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5168{
5169 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5170
5171 vcpu->arch.smbase = smbase;
5172}
5173
67f4d428
NA		 5174static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5175 u32 pmc)
5176{
c6702c9d 5177 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5178}
5179
222d21aa
AK		 5180static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5181 u32 pmc, u64 *pdata)
5182{
c6702c9d 5183 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5184}
5185
6c3287f7
AK		 5186static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5187{
5188 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5189}
5190
5037f6f3
AK		 5191static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5192{
5193 preempt_disable();
5197b808 5194 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5195}
5196
5197static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5198{
5199 preempt_enable();
5200}
5201
2953538e 5202static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5203 struct x86_instruction_info *info,
c4f035c6
AK		 5204 enum x86_intercept_stage stage)
5205{
2953538e 5206 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5207}
5208
e911eb3b
YZ		 5209static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5210 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5211{
e911eb3b 5212 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5213}
5214
dd856efa
AK		 5215static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5216{
5217 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5218}
5219
5220static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5221{
5222 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5223}
5224
801806d9
NA		 5225static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5226{
5227 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5228}
5229
6ed071f0
LP		 5230static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5231{
5232 return emul_to_vcpu(ctxt)->arch.hflags;
5233}
5234
5235static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5236{
5237 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5238}
5239
0225fb50 5240static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5241 .read_gpr = emulator_read_gpr,
5242 .write_gpr = emulator_write_gpr,
1871c602 5243 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5244 .write_std = kvm_write_guest_virt_system,
7a036a6f 5245 .read_phys = kvm_read_guest_phys_system,
1871c602 5246 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5247 .read_emulated = emulator_read_emulated,
5248 .write_emulated = emulator_write_emulated,
5249 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5250 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5251 .pio_in_emulated = emulator_pio_in_emulated,
5252 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5253 .get_segment = emulator_get_segment,
5254 .set_segment = emulator_set_segment,
5951c442 5255 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5256 .get_gdt = emulator_get_gdt,
160ce1f1 5257 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5258 .set_gdt = emulator_set_gdt,
5259 .set_idt = emulator_set_idt,
52a46617
GN		 5260 .get_cr = emulator_get_cr,
5261 .set_cr = emulator_set_cr,
9c537244 5262 .cpl = emulator_get_cpl,
35aa5375
GN		 5263 .get_dr = emulator_get_dr,
5264 .set_dr = emulator_set_dr,
64d60670
PB		 5265 .get_smbase = emulator_get_smbase,
5266 .set_smbase = emulator_set_smbase,
717746e3
AK		 5267 .set_msr = emulator_set_msr,
5268 .get_msr = emulator_get_msr,
67f4d428 5269 .check_pmc = emulator_check_pmc,
222d21aa 5270 .read_pmc = emulator_read_pmc,
6c3287f7 5271 .halt = emulator_halt,
bcaf5cc5 5272 .wbinvd = emulator_wbinvd,
d6aa1000 5273 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5274 .get_fpu = emulator_get_fpu,
5275 .put_fpu = emulator_put_fpu,
c4f035c6 5276 .intercept = emulator_intercept,
bdb42f5a 5277 .get_cpuid = emulator_get_cpuid,
801806d9 5278 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5279 .get_hflags = emulator_get_hflags,
5280 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5281};
5282
95cb2295
GN		 5283static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5284{
37ccdcbe 5285 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5286 /*
5287 * an sti; sti; sequence only disable interrupts for the first
5288 * instruction. So, if the last instruction, be it emulated or
5289 * not, left the system with the INT_STI flag enabled, it
5290 * means that the last instruction is an sti. We should not
5291 * leave the flag on in this case. The same goes for mov ss
5292 */
37ccdcbe
PB		 5293 if (int_shadow & mask)
5294 mask = 0;
6addfc42 5295 if (unlikely(int_shadow || mask)) {
95cb2295 5296 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5297 if (!mask)
5298 kvm_make_request(KVM_REQ_EVENT, vcpu);
5299 }
95cb2295
GN		 5300}
5301
ef54bcfe 5302static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5303{
5304 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5305 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5306 return kvm_propagate_fault(vcpu, &ctxt->exception);
5307
5308 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5309 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5310 ctxt->exception.error_code);
54b8486f 5311 else
da9cb575 5312 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5313 return false;
54b8486f
GN		 5314}
5315
8ec4722d
MG		 5316static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5317{
adf52235 5318 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5319 int cs_db, cs_l;
5320
8ec4722d
MG		 5321 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5322
adf52235 5323 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5324 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5325
adf52235
TY		 5326 ctxt->eip = kvm_rip_read(vcpu);
5327 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5328 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5329 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5330 cs_db ? X86EMUL_MODE_PROT32 :
5331 X86EMUL_MODE_PROT16;
a584539b 5332 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5333 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5334 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5335
dd856efa 5336 init_decode_cache(ctxt);
7ae441ea 5337 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5338}
5339
71f9833b 5340int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5341{
9d74191a 5342 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5343 int ret;
5344
5345 init_emulate_ctxt(vcpu);
5346
9dac77fa
AK		 5347 ctxt->op_bytes = 2;
5348 ctxt->ad_bytes = 2;
5349 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5350 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5351
5352 if (ret != X86EMUL_CONTINUE)
5353 return EMULATE_FAIL;
5354
9dac77fa 5355 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5356 kvm_rip_write(vcpu, ctxt->eip);
5357 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5358
5359 if (irq == NMI_VECTOR)
7460fb4a 5360 vcpu->arch.nmi_pending = 0;
63995653
MG		 5361 else
5362 vcpu->arch.interrupt.pending = false;
5363
5364 return EMULATE_DONE;
5365}
5366EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5367
6d77dbfc
GN		 5368static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5369{
fc3a9157
JR		 5370 int r = EMULATE_DONE;
5371
6d77dbfc
GN		 5372 ++vcpu->stat.insn_emulation_fail;
5373 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5374 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5375 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5376 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5377 vcpu->run->internal.ndata = 0;
5378 r = EMULATE_FAIL;
5379 }
6d77dbfc 5380 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5381
5382 return r;
6d77dbfc
GN		 5383}
5384
93c05d3e 5385static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5386 bool write_fault_to_shadow_pgtable,
5387 int emulation_type)
a6f177ef 5388{
95b3cf69 5389 gpa_t gpa = cr2;
ba049e93 5390 kvm_pfn_t pfn;
a6f177ef 5391
991eebf9
GN		 5392 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5393 return false;
5394
95b3cf69
XG		 5395 if (!vcpu->arch.mmu.direct_map) {
5396 /*
5397 * Write permission should be allowed since only
5398 * write access need to be emulated.
5399 */
5400 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5401
95b3cf69
XG		 5402 /*
5403 * If the mapping is invalid in guest, let cpu retry
5404 * it to generate fault.
5405 */
5406 if (gpa == UNMAPPED_GVA)
5407 return true;
5408 }
a6f177ef 5409
8e3d9d06
XG		 5410 /*
5411 * Do not retry the unhandleable instruction if it faults on the
5412 * readonly host memory, otherwise it will goto a infinite loop:
5413 * retry instruction -> write #PF -> emulation fail -> retry
5414 * instruction -> ...
5415 */
5416 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5417
5418 /*
5419 * If the instruction failed on the error pfn, it can not be fixed,
5420 * report the error to userspace.
5421 */
5422 if (is_error_noslot_pfn(pfn))
5423 return false;
5424
5425 kvm_release_pfn_clean(pfn);
5426
5427 /* The instructions are well-emulated on direct mmu. */
5428 if (vcpu->arch.mmu.direct_map) {
5429 unsigned int indirect_shadow_pages;
5430
5431 spin_lock(&vcpu->kvm->mmu_lock);
5432 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5433 spin_unlock(&vcpu->kvm->mmu_lock);
5434
5435 if (indirect_shadow_pages)
5436 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5437
a6f177ef 5438 return true;
8e3d9d06 5439 }
a6f177ef 5440
95b3cf69
XG		 5441 /*
5442 * if emulation was due to access to shadowed page table
5443 * and it failed try to unshadow page and re-enter the
5444 * guest to let CPU execute the instruction.
5445 */
5446 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5447
5448 /*
5449 * If the access faults on its page table, it can not
5450 * be fixed by unprotecting shadow page and it should
5451 * be reported to userspace.
5452 */
5453 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5454}
5455
1cb3f3ae
XG		 5456static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5457 unsigned long cr2, int emulation_type)
5458{
5459 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5460 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5461
5462 last_retry_eip = vcpu->arch.last_retry_eip;
5463 last_retry_addr = vcpu->arch.last_retry_addr;
5464
5465 /*
5466 * If the emulation is caused by #PF and it is non-page_table
5467 * writing instruction, it means the VM-EXIT is caused by shadow
5468 * page protected, we can zap the shadow page and retry this
5469 * instruction directly.
5470 *
5471 * Note: if the guest uses a non-page-table modifying instruction
5472 * on the PDE that points to the instruction, then we will unmap
5473 * the instruction and go to an infinite loop. So, we cache the
5474 * last retried eip and the last fault address, if we meet the eip
5475 * and the address again, we can break out of the potential infinite
5476 * loop.
5477 */
5478 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5479
5480 if (!(emulation_type & EMULTYPE_RETRY))
5481 return false;
5482
5483 if (x86_page_table_writing_insn(ctxt))
5484 return false;
5485
5486 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5487 return false;
5488
5489 vcpu->arch.last_retry_eip = ctxt->eip;
5490 vcpu->arch.last_retry_addr = cr2;
5491
5492 if (!vcpu->arch.mmu.direct_map)
5493 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5494
22368028 5495 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5496
5497 return true;
5498}
5499
716d51ab
GN		 5500static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5501static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5502
64d60670 5503static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5504{
64d60670 5505 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5506 /* This is a good place to trace that we are exiting SMM. */
5507 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5508
c43203ca
PB		 5509 /* Process a latched INIT or SMI, if any. */
5510 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5511 }
699023e2
PB		 5512
5513 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5514}
5515
5516static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5517{
5518 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5519
a584539b 5520 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5521
5522 if (changed & HF_SMM_MASK)
5523 kvm_smm_changed(vcpu);
a584539b
PB		 5524}
5525
4a1e10d5
PB		 5526static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5527 unsigned long *db)
5528{
5529 u32 dr6 = 0;
5530 int i;
5531 u32 enable, rwlen;
5532
5533 enable = dr7;
5534 rwlen = dr7 >> 16;
5535 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5536 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5537 dr6 |= (1 << i);
5538 return dr6;
5539}
5540
c8401dda 5541static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5542{
5543 struct kvm_run *kvm_run = vcpu->run;
5544
c8401dda
PB		 5545 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5546 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5547 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5548 kvm_run->debug.arch.exception = DB_VECTOR;
5549 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5550 *r = EMULATE_USER_EXIT;
5551 } else {
5552 /*
5553 * "Certain debug exceptions may clear bit 0-3. The
5554 * remaining contents of the DR6 register are never
5555 * cleared by the processor".
5556 */
5557 vcpu->arch.dr6 &= ~15;
5558 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5559 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5560 }
5561}
5562
6affcbed
KH		 5563int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5564{
5565 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5566 int r = EMULATE_DONE;
5567
5568 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5569
5570 /*
5571 * rflags is the old, "raw" value of the flags. The new value has
5572 * not been saved yet.
5573 *
5574 * This is correct even for TF set by the guest, because "the
5575 * processor will not generate this exception after the instruction
5576 * that sets the TF flag".
5577 */
5578 if (unlikely(rflags & X86_EFLAGS_TF))
5579 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5580 return r == EMULATE_DONE;
5581}
5582EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5583
4a1e10d5
PB		 5584static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5585{
4a1e10d5
PB		 5586 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5587 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5588 struct kvm_run *kvm_run = vcpu->run;
5589 unsigned long eip = kvm_get_linear_rip(vcpu);
5590 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5591 vcpu->arch.guest_debug_dr7,
5592 vcpu->arch.eff_db);
5593
5594 if (dr6 != 0) {
6f43ed01 5595 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5596 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5597 kvm_run->debug.arch.exception = DB_VECTOR;
5598 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5599 *r = EMULATE_USER_EXIT;
5600 return true;
5601 }
5602 }
5603
4161a569
NA		 5604 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5605 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5606 unsigned long eip = kvm_get_linear_rip(vcpu);
5607 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5608 vcpu->arch.dr7,
5609 vcpu->arch.db);
5610
5611 if (dr6 != 0) {
5612 vcpu->arch.dr6 &= ~15;
6f43ed01 5613 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5614 kvm_queue_exception(vcpu, DB_VECTOR);
5615 *r = EMULATE_DONE;
5616 return true;
5617 }
5618 }
5619
5620 return false;
5621}
5622
51d8b661
AP		 5623int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5624 unsigned long cr2,
dc25e89e
AP		 5625 int emulation_type,
5626 void *insn,
5627 int insn_len)
bbd9b64e 5628{
95cb2295 5629 int r;
9d74191a 5630 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5631 bool writeback = true;
93c05d3e 5632 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5633
93c05d3e
XG		 5634 /*
5635 * Clear write_fault_to_shadow_pgtable here to ensure it is
5636 * never reused.
5637 */
5638 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5639 kvm_clear_exception_queue(vcpu);
8d7d8102 5640
571008da 5641 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5642 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5643
5644 /*
5645 * We will reenter on the same instruction since
5646 * we do not set complete_userspace_io. This does not
5647 * handle watchpoints yet, those would be handled in
5648 * the emulate_ops.
5649 */
5650 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5651 return r;
5652
9d74191a
TY		 5653 ctxt->interruptibility = 0;
5654 ctxt->have_exception = false;
e0ad0b47 5655 ctxt->exception.vector = -1;
9d74191a 5656 ctxt->perm_ok = false;
bbd9b64e 5657
b51e974f 5658 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5659
9d74191a 5660 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5661
e46479f8 5662 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5663 ++vcpu->stat.insn_emulation;
1d2887e2 5664 if (r != EMULATION_OK) {
4005996e
AK		 5665 if (emulation_type & EMULTYPE_TRAP_UD)
5666 return EMULATE_FAIL;
991eebf9
GN		 5667 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5668 emulation_type))
bbd9b64e 5669 return EMULATE_DONE;
6d77dbfc
GN		 5670 if (emulation_type & EMULTYPE_SKIP)
5671 return EMULATE_FAIL;
5672 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5673 }
5674 }
5675
ba8afb6b 5676 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5677 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5678 if (ctxt->eflags & X86_EFLAGS_RF)
5679 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5680 return EMULATE_DONE;
5681 }
5682
1cb3f3ae
XG		 5683 if (retry_instruction(ctxt, cr2, emulation_type))
5684 return EMULATE_DONE;
5685
7ae441ea 5686 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5687 changes registers values during IO operation */
7ae441ea
GN		 5688 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5689 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5690 emulator_invalidate_register_cache(ctxt);
7ae441ea 5691 }
4d2179e1 5692
5cd21917 5693restart:
0f89b207
TL		 5694 /* Save the faulting GPA (cr2) in the address field */
5695 ctxt->exception.address = cr2;
5696
9d74191a 5697 r = x86_emulate_insn(ctxt);
bbd9b64e 5698
775fde86
JR		 5699 if (r == EMULATION_INTERCEPTED)
5700 return EMULATE_DONE;
5701
d2ddd1c4 5702 if (r == EMULATION_FAILED) {
991eebf9
GN		 5703 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5704 emulation_type))
c3cd7ffa
GN		 5705 return EMULATE_DONE;
5706
6d77dbfc 5707 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5708 }
5709
9d74191a 5710 if (ctxt->have_exception) {
d2ddd1c4 5711 r = EMULATE_DONE;
ef54bcfe
PB		 5712 if (inject_emulated_exception(vcpu))
5713 return r;
d2ddd1c4 5714 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5715 if (!vcpu->arch.pio.in) {
5716 /* FIXME: return into emulator if single-stepping. */
3457e419 5717 vcpu->arch.pio.count = 0;
0912c977 5718 } else {
7ae441ea 5719 writeback = false;
716d51ab
GN		 5720 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5721 }
ac0a48c3 5722 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5723 } else if (vcpu->mmio_needed) {
5724 if (!vcpu->mmio_is_write)
5725 writeback = false;
ac0a48c3 5726 r = EMULATE_USER_EXIT;
716d51ab 5727 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5728 } else if (r == EMULATION_RESTART)
5cd21917 5729 goto restart;
d2ddd1c4
GN		 5730 else
5731 r = EMULATE_DONE;
f850e2e6 5732
7ae441ea 5733 if (writeback) {
6addfc42 5734 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5735 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5736 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5737 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5738 if (r == EMULATE_DONE &&
5739 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5740 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5741 if (!ctxt->have_exception ||
5742 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5743 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5744
5745 /*
5746 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5747 * do nothing, and it will be requested again as soon as
5748 * the shadow expires. But we still need to check here,
5749 * because POPF has no interrupt shadow.
5750 */
5751 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5752 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5753 } else
5754 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5755
5756 return r;
de7d789a 5757}
51d8b661 5758EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5759
cf8f70bf 5760int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5761{
cf8f70bf 5762 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5763 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5764 size, port, &val, 1);
cf8f70bf 5765 /* do not return to emulator after return from userspace */
7972995b 5766 vcpu->arch.pio.count = 0;
de7d789a
CO		 5767 return ret;
5768}
cf8f70bf 5769EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5770
8370c3d0
TL		 5771static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5772{
5773 unsigned long val;
5774
5775 /* We should only ever be called with arch.pio.count equal to 1 */
5776 BUG_ON(vcpu->arch.pio.count != 1);
5777
5778 /* For size less than 4 we merge, else we zero extend */
5779 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5780 : 0;
5781
5782 /*
5783 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5784 * the copy and tracing
5785 */
5786 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5787 vcpu->arch.pio.port, &val, 1);
5788 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5789
5790 return 1;
5791}
5792
5793int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5794{
5795 unsigned long val;
5796 int ret;
5797
5798 /* For size less than 4 we merge, else we zero extend */
5799 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5800
5801 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5802 &val, 1);
5803 if (ret) {
5804 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5805 return ret;
5806 }
5807
5808 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5809
5810 return 0;
5811}
5812EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5813
251a5fd6 5814static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5815{
0a3aee0d 5816 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5817 return 0;
8cfdc000
ZA		 5818}
5819
5820static void tsc_khz_changed(void *data)
c8076604 5821{
8cfdc000
ZA		 5822 struct cpufreq_freqs *freq = data;
5823 unsigned long khz = 0;
5824
5825 if (data)
5826 khz = freq->new;
5827 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5828 khz = cpufreq_quick_get(raw_smp_processor_id());
5829 if (!khz)
5830 khz = tsc_khz;
0a3aee0d 5831 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5832}
5833
c8076604
GH		 5834static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5835 void *data)
5836{
5837 struct cpufreq_freqs *freq = data;
5838 struct kvm *kvm;
5839 struct kvm_vcpu *vcpu;
5840 int i, send_ipi = 0;
5841
8cfdc000
ZA		 5842 /*
5843 * We allow guests to temporarily run on slowing clocks,
5844 * provided we notify them after, or to run on accelerating
5845 * clocks, provided we notify them before. Thus time never
5846 * goes backwards.
5847 *
5848 * However, we have a problem. We can't atomically update
5849 * the frequency of a given CPU from this function; it is
5850 * merely a notifier, which can be called from any CPU.
5851 * Changing the TSC frequency at arbitrary points in time
5852 * requires a recomputation of local variables related to
5853 * the TSC for each VCPU. We must flag these local variables
5854 * to be updated and be sure the update takes place with the
5855 * new frequency before any guests proceed.
5856 *
5857 * Unfortunately, the combination of hotplug CPU and frequency
5858 * change creates an intractable locking scenario; the order
5859 * of when these callouts happen is undefined with respect to
5860 * CPU hotplug, and they can race with each other. As such,
5861 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5862 * undefined; you can actually have a CPU frequency change take
5863 * place in between the computation of X and the setting of the
5864 * variable. To protect against this problem, all updates of
5865 * the per_cpu tsc_khz variable are done in an interrupt
5866 * protected IPI, and all callers wishing to update the value
5867 * must wait for a synchronous IPI to complete (which is trivial
5868 * if the caller is on the CPU already). This establishes the
5869 * necessary total order on variable updates.
5870 *
5871 * Note that because a guest time update may take place
5872 * anytime after the setting of the VCPU's request bit, the
5873 * correct TSC value must be set before the request. However,
5874 * to ensure the update actually makes it to any guest which
5875 * starts running in hardware virtualization between the set
5876 * and the acquisition of the spinlock, we must also ping the
5877 * CPU after setting the request bit.
5878 *
5879 */
5880
c8076604
GH		 5881 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5882 return 0;
5883 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5884 return 0;
8cfdc000
ZA		 5885
5886 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5887
2f303b74 5888 spin_lock(&kvm_lock);
c8076604 5889 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5890 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5891 if (vcpu->cpu != freq->cpu)
5892 continue;
c285545f 5893 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5894 if (vcpu->cpu != smp_processor_id())
8cfdc000 5895 send_ipi = 1;
c8076604
GH		 5896 }
5897 }
2f303b74 5898 spin_unlock(&kvm_lock);
c8076604
GH		 5899
5900 if (freq->old < freq->new && send_ipi) {
5901 /*
5902 * We upscale the frequency. Must make the guest
5903 * doesn't see old kvmclock values while running with
5904 * the new frequency, otherwise we risk the guest sees
5905 * time go backwards.
5906 *
5907 * In case we update the frequency for another cpu
5908 * (which might be in guest context) send an interrupt
5909 * to kick the cpu out of guest context. Next time
5910 * guest context is entered kvmclock will be updated,
5911 * so the guest will not see stale values.
5912 */
8cfdc000 5913 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5914 }
5915 return 0;
5916}
5917
5918static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5919 .notifier_call = kvmclock_cpufreq_notifier
5920};
5921
251a5fd6 5922static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5923{
251a5fd6
SAS		 5924 tsc_khz_changed(NULL);
5925 return 0;
8cfdc000
ZA		 5926}
5927
b820cc0c
ZA		 5928static void kvm_timer_init(void)
5929{
c285545f 5930 max_tsc_khz = tsc_khz;
460dd42e 5931
b820cc0c 5932 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5933#ifdef CONFIG_CPU_FREQ
5934 struct cpufreq_policy policy;
758f588d
BP		 5935 int cpu;
5936
c285545f 5937 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5938 cpu = get_cpu();
5939 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5940 if (policy.cpuinfo.max_freq)
5941 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5942 put_cpu();
c285545f 5943#endif
b820cc0c
ZA		 5944 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5945 CPUFREQ_TRANSITION_NOTIFIER);
5946 }
c285545f 5947 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5948
73c1b41e 5949 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5950 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5951}
5952
ff9d07a0
ZY		 5953static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5954
f5132b01 5955int kvm_is_in_guest(void)
ff9d07a0 5956{
086c9855 5957 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5958}
5959
5960static int kvm_is_user_mode(void)
5961{
5962 int user_mode = 3;
dcf46b94 5963
086c9855
AS		 5964 if (__this_cpu_read(current_vcpu))
5965 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5966
ff9d07a0
ZY		 5967 return user_mode != 0;
5968}
5969
5970static unsigned long kvm_get_guest_ip(void)
5971{
5972 unsigned long ip = 0;
dcf46b94 5973
086c9855
AS		 5974 if (__this_cpu_read(current_vcpu))
5975 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5976
ff9d07a0
ZY		 5977 return ip;
5978}
5979
5980static struct perf_guest_info_callbacks kvm_guest_cbs = {
5981 .is_in_guest = kvm_is_in_guest,
5982 .is_user_mode = kvm_is_user_mode,
5983 .get_guest_ip = kvm_get_guest_ip,
5984};
5985
5986void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5987{
086c9855 5988 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5989}
5990EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5991
5992void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5993{
086c9855 5994 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5995}
5996EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5997
ce88decf
XG		 5998static void kvm_set_mmio_spte_mask(void)
5999{
6000 u64 mask;
6001 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6002
6003 /*
6004 * Set the reserved bits and the present bit of an paging-structure
6005 * entry to generate page fault with PFER.RSV = 1.
6006 */
885032b9 6007 /* Mask the reserved physical address bits. */
d1431483 6008 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6009
885032b9 6010 /* Set the present bit. */
ce88decf
XG		 6011 mask |= 1ull;
6012
6013#ifdef CONFIG_X86_64
6014 /*
6015 * If reserved bit is not supported, clear the present bit to disable
6016 * mmio page fault.
6017 */
6018 if (maxphyaddr == 52)
6019 mask &= ~1ull;
6020#endif
6021
dcdca5fe 6022 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6023}
6024
16e8d74d
MT		 6025#ifdef CONFIG_X86_64
6026static void pvclock_gtod_update_fn(struct work_struct *work)
6027{
d828199e
MT		 6028 struct kvm *kvm;
6029
6030 struct kvm_vcpu *vcpu;
6031 int i;
6032
2f303b74 6033 spin_lock(&kvm_lock);
d828199e
MT		 6034 list_for_each_entry(kvm, &vm_list, vm_list)
6035 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6036 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6037 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6038 spin_unlock(&kvm_lock);
16e8d74d
MT		 6039}
6040
6041static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6042
6043/*
6044 * Notification about pvclock gtod data update.
6045 */
6046static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6047 void *priv)
6048{
6049 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6050 struct timekeeper *tk = priv;
6051
6052 update_pvclock_gtod(tk);
6053
6054 /* disable master clock if host does not trust, or does not
6055 * use, TSC clocksource
6056 */
6057 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6058 atomic_read(&kvm_guest_has_master_clock) != 0)
6059 queue_work(system_long_wq, &pvclock_gtod_work);
6060
6061 return 0;
6062}
6063
6064static struct notifier_block pvclock_gtod_notifier = {
6065 .notifier_call = pvclock_gtod_notify,
6066};
6067#endif
6068
f8c16bba 6069int kvm_arch_init(void *opaque)
043405e1 6070{
b820cc0c 6071 int r;
6b61edf7 6072 struct kvm_x86_ops *ops = opaque;
f8c16bba 6073
f8c16bba
ZX		 6074 if (kvm_x86_ops) {
6075 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6076 r = -EEXIST;
6077 goto out;
f8c16bba
ZX		 6078 }
6079
6080 if (!ops->cpu_has_kvm_support()) {
6081 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6082 r = -EOPNOTSUPP;
6083 goto out;
f8c16bba
ZX		 6084 }
6085 if (ops->disabled_by_bios()) {
6086 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6087 r = -EOPNOTSUPP;
6088 goto out;
f8c16bba
ZX		 6089 }
6090
013f6a5d
MT		 6091 r = -ENOMEM;
6092 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6093 if (!shared_msrs) {
6094 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6095 goto out;
6096 }
6097
97db56ce
AK		 6098 r = kvm_mmu_module_init();
6099 if (r)
013f6a5d 6100 goto out_free_percpu;
97db56ce 6101
ce88decf 6102 kvm_set_mmio_spte_mask();
97db56ce 6103
f8c16bba 6104 kvm_x86_ops = ops;
920c8377 6105
7b52345e 6106 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6107 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6108 PT_PRESENT_MASK, 0);
b820cc0c 6109 kvm_timer_init();
c8076604 6110
ff9d07a0
ZY		 6111 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6112
d366bf7e 6113 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6114 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6115
c5cc421b 6116 kvm_lapic_init();
16e8d74d
MT		 6117#ifdef CONFIG_X86_64
6118 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6119#endif
6120
f8c16bba 6121 return 0;
56c6d28a 6122
013f6a5d
MT		 6123out_free_percpu:
6124 free_percpu(shared_msrs);
56c6d28a 6125out:
56c6d28a 6126 return r;
043405e1 6127}
8776e519 6128
f8c16bba
ZX		 6129void kvm_arch_exit(void)
6130{
cef84c30 6131 kvm_lapic_exit();
ff9d07a0
ZY		 6132 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6133
888d256e
JK		 6134 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6135 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6136 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6137 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6138#ifdef CONFIG_X86_64
6139 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6140#endif
f8c16bba 6141 kvm_x86_ops = NULL;
56c6d28a 6142 kvm_mmu_module_exit();
013f6a5d 6143 free_percpu(shared_msrs);
56c6d28a 6144}
f8c16bba 6145
5cb56059 6146int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6147{
6148 ++vcpu->stat.halt_exits;
35754c98 6149 if (lapic_in_kernel(vcpu)) {
a4535290 6150 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6151 return 1;
6152 } else {
6153 vcpu->run->exit_reason = KVM_EXIT_HLT;
6154 return 0;
6155 }
6156}
5cb56059
JS		 6157EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6158
6159int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6160{
6affcbed
KH		 6161 int ret = kvm_skip_emulated_instruction(vcpu);
6162 /*
6163 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6164 * KVM_EXIT_DEBUG here.
6165 */
6166 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6167}
8776e519
HB		 6168EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6169
8ef81a9a 6170#ifdef CONFIG_X86_64
55dd00a7
MT		 6171static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6172 unsigned long clock_type)
6173{
6174 struct kvm_clock_pairing clock_pairing;
6175 struct timespec ts;
80fbd89c 6176 u64 cycle;
55dd00a7
MT		 6177 int ret;
6178
6179 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6180 return -KVM_EOPNOTSUPP;
6181
6182 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6183 return -KVM_EOPNOTSUPP;
6184
6185 clock_pairing.sec = ts.tv_sec;
6186 clock_pairing.nsec = ts.tv_nsec;
6187 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6188 clock_pairing.flags = 0;
6189
6190 ret = 0;
6191 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6192 sizeof(struct kvm_clock_pairing)))
6193 ret = -KVM_EFAULT;
6194
6195 return ret;
6196}
8ef81a9a 6197#endif
55dd00a7 6198
6aef266c
SV		 6199/*
6200 * kvm_pv_kick_cpu_op: Kick a vcpu.
6201 *
6202 * @apicid - apicid of vcpu to be kicked.
6203 */
6204static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6205{
24d2166b 6206 struct kvm_lapic_irq lapic_irq;
6aef266c 6207
24d2166b
R		 6208 lapic_irq.shorthand = 0;
6209 lapic_irq.dest_mode = 0;
ebd28fcb 6210 lapic_irq.level = 0;
24d2166b 6211 lapic_irq.dest_id = apicid;
93bbf0b8 6212 lapic_irq.msi_redir_hint = false;
6aef266c 6213
24d2166b 6214 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6215 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6216}
6217
d62caabb
AS		 6218void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6219{
6220 vcpu->arch.apicv_active = false;
6221 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6222}
6223
8776e519
HB		 6224int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6225{
6226 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6227 int op_64_bit, r;
8776e519 6228
6affcbed 6229 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6230
55cd8e5a
GN		 6231 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6232 return kvm_hv_hypercall(vcpu);
6233
5fdbf976
MT		 6234 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6235 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6236 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6237 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6238 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6239
229456fc 6240 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6241
a449c7aa
NA		 6242 op_64_bit = is_64_bit_mode(vcpu);
6243 if (!op_64_bit) {
8776e519
HB		 6244 nr &= 0xFFFFFFFF;
6245 a0 &= 0xFFFFFFFF;
6246 a1 &= 0xFFFFFFFF;
6247 a2 &= 0xFFFFFFFF;
6248 a3 &= 0xFFFFFFFF;
6249 }
6250
07708c4a
JK		 6251 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6252 ret = -KVM_EPERM;
6253 goto out;
6254 }
6255
8776e519 6256 switch (nr) {
b93463aa
AK		 6257 case KVM_HC_VAPIC_POLL_IRQ:
6258 ret = 0;
6259 break;
6aef266c
SV		 6260 case KVM_HC_KICK_CPU:
6261 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6262 ret = 0;
6263 break;
8ef81a9a 6264#ifdef CONFIG_X86_64
55dd00a7
MT		 6265 case KVM_HC_CLOCK_PAIRING:
6266 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6267 break;
8ef81a9a 6268#endif
8776e519
HB		 6269 default:
6270 ret = -KVM_ENOSYS;
6271 break;
6272 }
07708c4a 6273out:
a449c7aa
NA		 6274 if (!op_64_bit)
6275 ret = (u32)ret;
5fdbf976 6276 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6277 ++vcpu->stat.hypercalls;
2f333bcb 6278 return r;
8776e519
HB		 6279}
6280EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6281
b6785def 6282static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6283{
d6aa1000 6284 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6285 char instruction[3];
5fdbf976 6286 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6287
8776e519 6288 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6289
ce2e852e
DV		 6290 return emulator_write_emulated(ctxt, rip, instruction, 3,
6291 &ctxt->exception);
8776e519
HB		 6292}
6293
851ba692 6294static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6295{
782d422b
MG		 6296 return vcpu->run->request_interrupt_window &&
6297 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6298}
6299
851ba692 6300static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6301{
851ba692
AK		 6302 struct kvm_run *kvm_run = vcpu->run;
6303
91586a3b 6304 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6305 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6306 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6307 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6308 kvm_run->ready_for_interrupt_injection =
6309 pic_in_kernel(vcpu->kvm) ||
782d422b 6310 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6311}
6312
95ba8273
GN		 6313static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6314{
6315 int max_irr, tpr;
6316
6317 if (!kvm_x86_ops->update_cr8_intercept)
6318 return;
6319
bce87cce 6320 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6321 return;
6322
d62caabb
AS		 6323 if (vcpu->arch.apicv_active)
6324 return;
6325
8db3baa2
GN		 6326 if (!vcpu->arch.apic->vapic_addr)
6327 max_irr = kvm_lapic_find_highest_irr(vcpu);
6328 else
6329 max_irr = -1;
95ba8273
GN		 6330
6331 if (max_irr != -1)
6332 max_irr >>= 4;
6333
6334 tpr = kvm_lapic_get_cr8(vcpu);
6335
6336 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6337}
6338
b6b8a145 6339static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6340{
b6b8a145
JK		 6341 int r;
6342
95ba8273 6343 /* try to reinject previous events if any */
b59bb7bd 6344 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6345 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6346 vcpu->arch.exception.has_error_code,
6347 vcpu->arch.exception.error_code);
d6e8c854
NA		 6348
6349 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6350 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6351 X86_EFLAGS_RF);
6352
6bdf0662
NA		 6353 if (vcpu->arch.exception.nr == DB_VECTOR &&
6354 (vcpu->arch.dr7 & DR7_GD)) {
6355 vcpu->arch.dr7 &= ~DR7_GD;
6356 kvm_update_dr7(vcpu);
6357 }
6358
cfcd20e5 6359 kvm_x86_ops->queue_exception(vcpu);
b6b8a145 6360 return 0;
b59bb7bd
GN		 6361 }
6362
95ba8273
GN		 6363 if (vcpu->arch.nmi_injected) {
6364 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6365 return 0;
95ba8273
GN		 6366 }
6367
6368 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6369 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6370 return 0;
6371 }
6372
6373 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6374 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6375 if (r != 0)
6376 return r;
95ba8273
GN		 6377 }
6378
6379 /* try to inject new event if pending */
c43203ca
PB		 6380 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6381 vcpu->arch.smi_pending = false;
ee2cd4b7 6382 enter_smm(vcpu);
c43203ca 6383 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6384 --vcpu->arch.nmi_pending;
6385 vcpu->arch.nmi_injected = true;
6386 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6387 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6388 /*
6389 * Because interrupts can be injected asynchronously, we are
6390 * calling check_nested_events again here to avoid a race condition.
6391 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6392 * proposal and current concerns. Perhaps we should be setting
6393 * KVM_REQ_EVENT only on certain events and not unconditionally?
6394 */
6395 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6396 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6397 if (r != 0)
6398 return r;
6399 }
95ba8273 6400 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6401 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6402 false);
6403 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6404 }
6405 }
ee2cd4b7 6406
b6b8a145 6407 return 0;
95ba8273
GN		 6408}
6409
7460fb4a
AK		 6410static void process_nmi(struct kvm_vcpu *vcpu)
6411{
6412 unsigned limit = 2;
6413
6414 /*
6415 * x86 is limited to one NMI running, and one NMI pending after it.
6416 * If an NMI is already in progress, limit further NMIs to just one.
6417 * Otherwise, allow two (and we'll inject the first one immediately).
6418 */
6419 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6420 limit = 1;
6421
6422 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6423 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6424 kvm_make_request(KVM_REQ_EVENT, vcpu);
6425}
6426
660a5d51
PB		 6427#define put_smstate(type, buf, offset, val) \
6428 *(type *)((buf) + (offset) - 0x7e00) = val
6429
ee2cd4b7 6430static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6431{
6432 u32 flags = 0;
6433 flags |= seg->g << 23;
6434 flags |= seg->db << 22;
6435 flags |= seg->l << 21;
6436 flags |= seg->avl << 20;
6437 flags |= seg->present << 15;
6438 flags |= seg->dpl << 13;
6439 flags |= seg->s << 12;
6440 flags |= seg->type << 8;
6441 return flags;
6442}
6443
ee2cd4b7 6444static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6445{
6446 struct kvm_segment seg;
6447 int offset;
6448
6449 kvm_get_segment(vcpu, &seg, n);
6450 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6451
6452 if (n < 3)
6453 offset = 0x7f84 + n * 12;
6454 else
6455 offset = 0x7f2c + (n - 3) * 12;
6456
6457 put_smstate(u32, buf, offset + 8, seg.base);
6458 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6459 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6460}
6461
efbb288a 6462#ifdef CONFIG_X86_64
ee2cd4b7 6463static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6464{
6465 struct kvm_segment seg;
6466 int offset;
6467 u16 flags;
6468
6469 kvm_get_segment(vcpu, &seg, n);
6470 offset = 0x7e00 + n * 16;
6471
ee2cd4b7 6472 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6473 put_smstate(u16, buf, offset, seg.selector);
6474 put_smstate(u16, buf, offset + 2, flags);
6475 put_smstate(u32, buf, offset + 4, seg.limit);
6476 put_smstate(u64, buf, offset + 8, seg.base);
6477}
efbb288a 6478#endif
660a5d51 6479
ee2cd4b7 6480static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6481{
6482 struct desc_ptr dt;
6483 struct kvm_segment seg;
6484 unsigned long val;
6485 int i;
6486
6487 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6488 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6489 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6490 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6491
6492 for (i = 0; i < 8; i++)
6493 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6494
6495 kvm_get_dr(vcpu, 6, &val);
6496 put_smstate(u32, buf, 0x7fcc, (u32)val);
6497 kvm_get_dr(vcpu, 7, &val);
6498 put_smstate(u32, buf, 0x7fc8, (u32)val);
6499
6500 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6501 put_smstate(u32, buf, 0x7fc4, seg.selector);
6502 put_smstate(u32, buf, 0x7f64, seg.base);
6503 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6504 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6505
6506 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6507 put_smstate(u32, buf, 0x7fc0, seg.selector);
6508 put_smstate(u32, buf, 0x7f80, seg.base);
6509 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6510 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6511
6512 kvm_x86_ops->get_gdt(vcpu, &dt);
6513 put_smstate(u32, buf, 0x7f74, dt.address);
6514 put_smstate(u32, buf, 0x7f70, dt.size);
6515
6516 kvm_x86_ops->get_idt(vcpu, &dt);
6517 put_smstate(u32, buf, 0x7f58, dt.address);
6518 put_smstate(u32, buf, 0x7f54, dt.size);
6519
6520 for (i = 0; i < 6; i++)
ee2cd4b7 6521 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6522
6523 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6524
6525 /* revision id */
6526 put_smstate(u32, buf, 0x7efc, 0x00020000);
6527 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6528}
6529
ee2cd4b7 6530static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6531{
6532#ifdef CONFIG_X86_64
6533 struct desc_ptr dt;
6534 struct kvm_segment seg;
6535 unsigned long val;
6536 int i;
6537
6538 for (i = 0; i < 16; i++)
6539 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6540
6541 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6542 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6543
6544 kvm_get_dr(vcpu, 6, &val);
6545 put_smstate(u64, buf, 0x7f68, val);
6546 kvm_get_dr(vcpu, 7, &val);
6547 put_smstate(u64, buf, 0x7f60, val);
6548
6549 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6550 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6551 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6552
6553 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6554
6555 /* revision id */
6556 put_smstate(u32, buf, 0x7efc, 0x00020064);
6557
6558 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6559
6560 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6561 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6562 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6563 put_smstate(u32, buf, 0x7e94, seg.limit);
6564 put_smstate(u64, buf, 0x7e98, seg.base);
6565
6566 kvm_x86_ops->get_idt(vcpu, &dt);
6567 put_smstate(u32, buf, 0x7e84, dt.size);
6568 put_smstate(u64, buf, 0x7e88, dt.address);
6569
6570 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6571 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6572 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6573 put_smstate(u32, buf, 0x7e74, seg.limit);
6574 put_smstate(u64, buf, 0x7e78, seg.base);
6575
6576 kvm_x86_ops->get_gdt(vcpu, &dt);
6577 put_smstate(u32, buf, 0x7e64, dt.size);
6578 put_smstate(u64, buf, 0x7e68, dt.address);
6579
6580 for (i = 0; i < 6; i++)
ee2cd4b7 6581 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6582#else
6583 WARN_ON_ONCE(1);
6584#endif
6585}
6586
ee2cd4b7 6587static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6588{
660a5d51 6589 struct kvm_segment cs, ds;
18c3626e 6590 struct desc_ptr dt;
660a5d51
PB		 6591 char buf[512];
6592 u32 cr0;
6593
660a5d51
PB		 6594 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6595 vcpu->arch.hflags |= HF_SMM_MASK;
6596 memset(buf, 0, 512);
d6321d49 6597 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6598 enter_smm_save_state_64(vcpu, buf);
660a5d51 6599 else
ee2cd4b7 6600 enter_smm_save_state_32(vcpu, buf);
660a5d51 6601
54bf36aa 6602 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6603
6604 if (kvm_x86_ops->get_nmi_mask(vcpu))
6605 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6606 else
6607 kvm_x86_ops->set_nmi_mask(vcpu, true);
6608
6609 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6610 kvm_rip_write(vcpu, 0x8000);
6611
6612 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6613 kvm_x86_ops->set_cr0(vcpu, cr0);
6614 vcpu->arch.cr0 = cr0;
6615
6616 kvm_x86_ops->set_cr4(vcpu, 0);
6617
18c3626e
PB		 6618 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6619 dt.address = dt.size = 0;
6620 kvm_x86_ops->set_idt(vcpu, &dt);
6621
660a5d51
PB		 6622 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6623
6624 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6625 cs.base = vcpu->arch.smbase;
6626
6627 ds.selector = 0;
6628 ds.base = 0;
6629
6630 cs.limit = ds.limit = 0xffffffff;
6631 cs.type = ds.type = 0x3;
6632 cs.dpl = ds.dpl = 0;
6633 cs.db = ds.db = 0;
6634 cs.s = ds.s = 1;
6635 cs.l = ds.l = 0;
6636 cs.g = ds.g = 1;
6637 cs.avl = ds.avl = 0;
6638 cs.present = ds.present = 1;
6639 cs.unusable = ds.unusable = 0;
6640 cs.padding = ds.padding = 0;
6641
6642 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6643 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6644 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6645 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6646 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6647 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6648
d6321d49 6649 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6650 kvm_x86_ops->set_efer(vcpu, 0);
6651
6652 kvm_update_cpuid(vcpu);
6653 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6654}
6655
ee2cd4b7 6656static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6657{
6658 vcpu->arch.smi_pending = true;
6659 kvm_make_request(KVM_REQ_EVENT, vcpu);
6660}
6661
2860c4b1
PB		 6662void kvm_make_scan_ioapic_request(struct kvm *kvm)
6663{
6664 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6665}
6666
3d81bc7e 6667static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6668{
5c919412
AS		 6669 u64 eoi_exit_bitmap[4];
6670
3d81bc7e
YZ		 6671 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6672 return;
c7c9c56c 6673
6308630b 6674 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6675
b053b2ae 6676 if (irqchip_split(vcpu->kvm))
6308630b 6677 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6678 else {
76dfafd5 6679 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6680 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6681 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6682 }
5c919412
AS		 6683 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6684 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6685 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6686}
6687
a70656b6
RK		 6688static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6689{
6690 ++vcpu->stat.tlb_flush;
6691 kvm_x86_ops->tlb_flush(vcpu);
6692}
6693
4256f43f
TC		 6694void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6695{
c24ae0dc
TC		 6696 struct page *page = NULL;
6697
35754c98 6698 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6699 return;
6700
4256f43f
TC		 6701 if (!kvm_x86_ops->set_apic_access_page_addr)
6702 return;
6703
c24ae0dc 6704 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6705 if (is_error_page(page))
6706 return;
c24ae0dc
TC		 6707 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6708
6709 /*
6710 * Do not pin apic access page in memory, the MMU notifier
6711 * will call us again if it is migrated or swapped out.
6712 */
6713 put_page(page);
4256f43f
TC		 6714}
6715EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6716
fe71557a
TC		 6717void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6718 unsigned long address)
6719{
c24ae0dc
TC		 6720 /*
6721 * The physical address of apic access page is stored in the VMCS.
6722 * Update it when it becomes invalid.
6723 */
6724 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6725 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6726}
6727
9357d939 6728/*
362c698f 6729 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6730 * exiting to the userspace. Otherwise, the value will be returned to the
6731 * userspace.
6732 */
851ba692 6733static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6734{
6735 int r;
62a193ed
MG		 6736 bool req_int_win =
6737 dm_request_for_irq_injection(vcpu) &&
6738 kvm_cpu_accept_dm_intr(vcpu);
6739
730dca42 6740 bool req_immediate_exit = false;
b6c7a5dc 6741
2fa6e1e1 6742 if (kvm_request_pending(vcpu)) {
a8eeb04a 6743 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6744 kvm_mmu_unload(vcpu);
a8eeb04a 6745 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6746 __kvm_migrate_timers(vcpu);
d828199e
MT		 6747 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6748 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6749 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6750 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6751 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6752 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6753 if (unlikely(r))
6754 goto out;
6755 }
a8eeb04a 6756 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6757 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6758 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6759 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6760 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6761 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6762 r = 0;
6763 goto out;
6764 }
a8eeb04a 6765 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6766 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6767 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6768 r = 0;
6769 goto out;
6770 }
af585b92
GN		 6771 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6772 /* Page is swapped out. Do synthetic halt */
6773 vcpu->arch.apf.halted = true;
6774 r = 1;
6775 goto out;
6776 }
c9aaa895
GC		 6777 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6778 record_steal_time(vcpu);
64d60670
PB		 6779 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6780 process_smi(vcpu);
7460fb4a
AK		 6781 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6782 process_nmi(vcpu);
f5132b01 6783 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6784 kvm_pmu_handle_event(vcpu);
f5132b01 6785 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6786 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6787 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6788 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6789 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6790 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6791 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6792 vcpu->run->eoi.vector =
6793 vcpu->arch.pending_ioapic_eoi;
6794 r = 0;
6795 goto out;
6796 }
6797 }
3d81bc7e
YZ		 6798 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6799 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6800 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6801 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6802 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6803 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6804 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6805 r = 0;
6806 goto out;
6807 }
e516cebb
AS		 6808 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6809 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6810 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6811 r = 0;
6812 goto out;
6813 }
db397571
AS		 6814 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6815 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6816 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6817 r = 0;
6818 goto out;
6819 }
f3b138c5
AS		 6820
6821 /*
6822 * KVM_REQ_HV_STIMER has to be processed after
6823 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6824 * depend on the guest clock being up-to-date
6825 */
1f4b34f8
AS		 6826 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6827 kvm_hv_process_stimers(vcpu);
2f52d58c 6828 }
b93463aa 6829
b463a6f7 6830 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6831 ++vcpu->stat.req_event;
66450a21
JK		 6832 kvm_apic_accept_events(vcpu);
6833 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6834 r = 1;
6835 goto out;
6836 }
6837
b6b8a145
JK		 6838 if (inject_pending_event(vcpu, req_int_win) != 0)
6839 req_immediate_exit = true;
321c5658 6840 else {
c43203ca
PB		 6841 /* Enable NMI/IRQ window open exits if needed.
6842 *
6843 * SMIs have two cases: 1) they can be nested, and
6844 * then there is nothing to do here because RSM will
6845 * cause a vmexit anyway; 2) or the SMI can be pending
6846 * because inject_pending_event has completed the
6847 * injection of an IRQ or NMI from the previous vmexit,
6848 * and then we request an immediate exit to inject the SMI.
6849 */
6850 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6851 req_immediate_exit = true;
321c5658
YS		 6852 if (vcpu->arch.nmi_pending)
6853 kvm_x86_ops->enable_nmi_window(vcpu);
6854 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6855 kvm_x86_ops->enable_irq_window(vcpu);
6856 }
b463a6f7
AK		 6857
6858 if (kvm_lapic_enabled(vcpu)) {
6859 update_cr8_intercept(vcpu);
6860 kvm_lapic_sync_to_vapic(vcpu);
6861 }
6862 }
6863
d8368af8
AK		 6864 r = kvm_mmu_reload(vcpu);
6865 if (unlikely(r)) {
d905c069 6866 goto cancel_injection;
d8368af8
AK		 6867 }
6868
b6c7a5dc
HB		 6869 preempt_disable();
6870
6871 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6872 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6873
6874 /*
6875 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6876 * IPI are then delayed after guest entry, which ensures that they
6877 * result in virtual interrupt delivery.
6878 */
6879 local_irq_disable();
6b7e2d09
XG		 6880 vcpu->mode = IN_GUEST_MODE;
6881
01b71917
MT		 6882 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6883
0f127d12 6884 /*
b95234c8 6885 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6886 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6887 *
6888 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6889 * pairs with the memory barrier implicit in pi_test_and_set_on
6890 * (see vmx_deliver_posted_interrupt).
6891 *
6892 * 3) This also orders the write to mode from any reads to the page
6893 * tables done while the VCPU is running. Please see the comment
6894 * in kvm_flush_remote_tlbs.
6b7e2d09 6895 */
01b71917 6896 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6897
b95234c8
PB		 6898 /*
6899 * This handles the case where a posted interrupt was
6900 * notified with kvm_vcpu_kick.
6901 */
6902 if (kvm_lapic_enabled(vcpu)) {
6903 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6904 kvm_x86_ops->sync_pir_to_irr(vcpu);
6905 }
32f88400 6906
2fa6e1e1 6907 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6908 || need_resched() || signal_pending(current)) {
6b7e2d09 6909 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6910 smp_wmb();
6c142801
AK		 6911 local_irq_enable();
6912 preempt_enable();
01b71917 6913 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6914 r = 1;
d905c069 6915 goto cancel_injection;
6c142801
AK		 6916 }
6917
fc5b7f3b
DM		 6918 kvm_load_guest_xcr0(vcpu);
6919
c43203ca
PB		 6920 if (req_immediate_exit) {
6921 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6922 smp_send_reschedule(vcpu->cpu);
c43203ca 6923 }
d6185f20 6924
8b89fe1f
PB		 6925 trace_kvm_entry(vcpu->vcpu_id);
6926 wait_lapic_expire(vcpu);
6edaa530 6927 guest_enter_irqoff();
b6c7a5dc 6928
42dbaa5a 6929 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6930 set_debugreg(0, 7);
6931 set_debugreg(vcpu->arch.eff_db[0], 0);
6932 set_debugreg(vcpu->arch.eff_db[1], 1);
6933 set_debugreg(vcpu->arch.eff_db[2], 2);
6934 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6935 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6936 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6937 }
b6c7a5dc 6938
851ba692 6939 kvm_x86_ops->run(vcpu);
b6c7a5dc 6940
c77fb5fe
PB		 6941 /*
6942 * Do this here before restoring debug registers on the host. And
6943 * since we do this before handling the vmexit, a DR access vmexit
6944 * can (a) read the correct value of the debug registers, (b) set
6945 * KVM_DEBUGREG_WONT_EXIT again.
6946 */
6947 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6948 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6949 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6950 kvm_update_dr0123(vcpu);
6951 kvm_update_dr6(vcpu);
6952 kvm_update_dr7(vcpu);
6953 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6954 }
6955
24f1e32c
FW		 6956 /*
6957 * If the guest has used debug registers, at least dr7
6958 * will be disabled while returning to the host.
6959 * If we don't have active breakpoints in the host, we don't
6960 * care about the messed up debug address registers. But if
6961 * we have some of them active, restore the old state.
6962 */
59d8eb53 6963 if (hw_breakpoint_active())
24f1e32c 6964 hw_breakpoint_restore();
42dbaa5a 6965
4ba76538 6966 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6967
6b7e2d09 6968 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6969 smp_wmb();
a547c6db 6970
fc5b7f3b
DM		 6971 kvm_put_guest_xcr0(vcpu);
6972
a547c6db 6973 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6974
6975 ++vcpu->stat.exits;
6976
f2485b3e 6977 guest_exit_irqoff();
b6c7a5dc 6978
f2485b3e 6979 local_irq_enable();
b6c7a5dc
HB		 6980 preempt_enable();
6981
f656ce01 6982 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6983
b6c7a5dc
HB		 6984 /*
6985 * Profile KVM exit RIPs:
6986 */
6987 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6988 unsigned long rip = kvm_rip_read(vcpu);
6989 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6990 }
6991
cc578287
ZA		 6992 if (unlikely(vcpu->arch.tsc_always_catchup))
6993 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6994
5cfb1d5a
MT		 6995 if (vcpu->arch.apic_attention)
6996 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6997
618232e2 6998 vcpu->arch.gpa_available = false;
851ba692 6999 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7000 return r;
7001
7002cancel_injection:
7003 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7004 if (unlikely(vcpu->arch.apic_attention))
7005 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7006out:
7007 return r;
7008}
b6c7a5dc 7009
362c698f
PB		 7010static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7011{
bf9f6ac8
FW		 7012 if (!kvm_arch_vcpu_runnable(vcpu) &&
7013 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7014 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7015 kvm_vcpu_block(vcpu);
7016 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7017
7018 if (kvm_x86_ops->post_block)
7019 kvm_x86_ops->post_block(vcpu);
7020
9c8fd1ba
PB		 7021 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7022 return 1;
7023 }
362c698f
PB		 7024
7025 kvm_apic_accept_events(vcpu);
7026 switch(vcpu->arch.mp_state) {
7027 case KVM_MP_STATE_HALTED:
7028 vcpu->arch.pv.pv_unhalted = false;
7029 vcpu->arch.mp_state =
7030 KVM_MP_STATE_RUNNABLE;
7031 case KVM_MP_STATE_RUNNABLE:
7032 vcpu->arch.apf.halted = false;
7033 break;
7034 case KVM_MP_STATE_INIT_RECEIVED:
7035 break;
7036 default:
7037 return -EINTR;
7038 break;
7039 }
7040 return 1;
7041}
09cec754 7042
5d9bc648
PB		 7043static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7044{
0ad3bed6
PB		 7045 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7046 kvm_x86_ops->check_nested_events(vcpu, false);
7047
5d9bc648
PB		 7048 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7049 !vcpu->arch.apf.halted);
7050}
7051
362c698f 7052static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7053{
7054 int r;
f656ce01 7055 struct kvm *kvm = vcpu->kvm;
d7690175 7056
f656ce01 7057 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7058
362c698f 7059 for (;;) {
58f800d5 7060 if (kvm_vcpu_running(vcpu)) {
851ba692 7061 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7062 } else {
362c698f 7063 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7064 }
7065
09cec754
GN		 7066 if (r <= 0)
7067 break;
7068
72875d8a 7069 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7070 if (kvm_cpu_has_pending_timer(vcpu))
7071 kvm_inject_pending_timer_irqs(vcpu);
7072
782d422b
MG		 7073 if (dm_request_for_irq_injection(vcpu) &&
7074 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7075 r = 0;
7076 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7077 ++vcpu->stat.request_irq_exits;
362c698f 7078 break;
09cec754 7079 }
af585b92
GN		 7080
7081 kvm_check_async_pf_completion(vcpu);
7082
09cec754
GN		 7083 if (signal_pending(current)) {
7084 r = -EINTR;
851ba692 7085 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7086 ++vcpu->stat.signal_exits;
362c698f 7087 break;
09cec754
GN		 7088 }
7089 if (need_resched()) {
f656ce01 7090 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7091 cond_resched();
f656ce01 7092 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7093 }
b6c7a5dc
HB		 7094 }
7095
f656ce01 7096 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7097
7098 return r;
7099}
7100
716d51ab
GN		 7101static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7102{
7103 int r;
7104 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7105 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7106 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7107 if (r != EMULATE_DONE)
7108 return 0;
7109 return 1;
7110}
7111
7112static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7113{
7114 BUG_ON(!vcpu->arch.pio.count);
7115
7116 return complete_emulated_io(vcpu);
7117}
7118
f78146b0
AK		 7119/*
7120 * Implements the following, as a state machine:
7121 *
7122 * read:
7123 * for each fragment
87da7e66
XG		 7124 * for each mmio piece in the fragment
7125 * write gpa, len
7126 * exit
7127 * copy data
f78146b0
AK		 7128 * execute insn
7129 *
7130 * write:
7131 * for each fragment
87da7e66
XG		 7132 * for each mmio piece in the fragment
7133 * write gpa, len
7134 * copy data
7135 * exit
f78146b0 7136 */
716d51ab 7137static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7138{
7139 struct kvm_run *run = vcpu->run;
f78146b0 7140 struct kvm_mmio_fragment *frag;
87da7e66 7141 unsigned len;
5287f194 7142
716d51ab 7143 BUG_ON(!vcpu->mmio_needed);
5287f194 7144
716d51ab 7145 /* Complete previous fragment */
87da7e66
XG		 7146 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7147 len = min(8u, frag->len);
716d51ab 7148 if (!vcpu->mmio_is_write)
87da7e66
XG		 7149 memcpy(frag->data, run->mmio.data, len);
7150
7151 if (frag->len <= 8) {
7152 /* Switch to the next fragment. */
7153 frag++;
7154 vcpu->mmio_cur_fragment++;
7155 } else {
7156 /* Go forward to the next mmio piece. */
7157 frag->data += len;
7158 frag->gpa += len;
7159 frag->len -= len;
7160 }
7161
a08d3b3b 7162 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7163 vcpu->mmio_needed = 0;
0912c977
PB		 7164
7165 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7166 if (vcpu->mmio_is_write)
716d51ab
GN		 7167 return 1;
7168 vcpu->mmio_read_completed = 1;
7169 return complete_emulated_io(vcpu);
7170 }
87da7e66 7171
716d51ab
GN		 7172 run->exit_reason = KVM_EXIT_MMIO;
7173 run->mmio.phys_addr = frag->gpa;
7174 if (vcpu->mmio_is_write)
87da7e66
XG		 7175 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7176 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7177 run->mmio.is_write = vcpu->mmio_is_write;
7178 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7179 return 0;
5287f194
AK		 7180}
7181
716d51ab 7182
b6c7a5dc
HB		 7183int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7184{
c5bedc68 7185 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7186 int r;
7187 sigset_t sigsaved;
7188
c4d72e2d 7189 fpu__activate_curr(fpu);
e5c30142 7190
ac9f6dc0
AK		 7191 if (vcpu->sigset_active)
7192 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7193
a4535290 7194 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7195 kvm_vcpu_block(vcpu);
66450a21 7196 kvm_apic_accept_events(vcpu);
72875d8a 7197 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0
AK		 7198 r = -EAGAIN;
7199 goto out;
b6c7a5dc
HB		 7200 }
7201
b6c7a5dc 7202 /* re-sync apic's tpr */
35754c98 7203 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7204 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7205 r = -EINVAL;
7206 goto out;
7207 }
7208 }
b6c7a5dc 7209
716d51ab
GN		 7210 if (unlikely(vcpu->arch.complete_userspace_io)) {
7211 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7212 vcpu->arch.complete_userspace_io = NULL;
7213 r = cui(vcpu);
7214 if (r <= 0)
7215 goto out;
7216 } else
7217 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7218
460df4c1
PB		 7219 if (kvm_run->immediate_exit)
7220 r = -EINTR;
7221 else
7222 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7223
7224out:
f1d86e46 7225 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7226 if (vcpu->sigset_active)
7227 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7228
b6c7a5dc
HB		 7229 return r;
7230}
7231
7232int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7233{
7ae441ea
GN		 7234 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7235 /*
7236 * We are here if userspace calls get_regs() in the middle of
7237 * instruction emulation. Registers state needs to be copied
4a969980 7238 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7239 * that usually, but some bad designed PV devices (vmware
7240 * backdoor interface) need this to work
7241 */
dd856efa 7242 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7243 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7244 }
5fdbf976
MT		 7245 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7246 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7247 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7248 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7249 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7250 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7251 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7252 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7253#ifdef CONFIG_X86_64
5fdbf976
MT		 7254 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7255 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7256 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7257 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7258 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7259 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7260 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7261 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7262#endif
7263
5fdbf976 7264 regs->rip = kvm_rip_read(vcpu);
91586a3b 7265 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7266
b6c7a5dc
HB		 7267 return 0;
7268}
7269
7270int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7271{
7ae441ea
GN		 7272 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7273 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7274
5fdbf976
MT		 7275 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7276 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7277 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7278 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7279 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7280 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7281 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7282 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7283#ifdef CONFIG_X86_64
5fdbf976
MT		 7284 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7285 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7286 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7287 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7288 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7289 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7290 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7291 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7292#endif
7293
5fdbf976 7294 kvm_rip_write(vcpu, regs->rip);
91586a3b 7295 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7296
b4f14abd
JK		 7297 vcpu->arch.exception.pending = false;
7298
3842d135
AK		 7299 kvm_make_request(KVM_REQ_EVENT, vcpu);
7300
b6c7a5dc
HB		 7301 return 0;
7302}
7303
b6c7a5dc
HB		 7304void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7305{
7306 struct kvm_segment cs;
7307
3e6e0aab 7308 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7309 *db = cs.db;
7310 *l = cs.l;
7311}
7312EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7313
7314int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7315 struct kvm_sregs *sregs)
7316{
89a27f4d 7317 struct desc_ptr dt;
b6c7a5dc 7318
3e6e0aab
GT		 7319 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7320 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7321 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7322 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7323 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7324 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7325
3e6e0aab
GT		 7326 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7327 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7328
7329 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7330 sregs->idt.limit = dt.size;
7331 sregs->idt.base = dt.address;
b6c7a5dc 7332 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7333 sregs->gdt.limit = dt.size;
7334 sregs->gdt.base = dt.address;
b6c7a5dc 7335
4d4ec087 7336 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7337 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7338 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7339 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7340 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7341 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7342 sregs->apic_base = kvm_get_apic_base(vcpu);
7343
923c61bb 7344 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7345
36752c9b 7346 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7347 set_bit(vcpu->arch.interrupt.nr,
7348 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7349
b6c7a5dc
HB		 7350 return 0;
7351}
7352
62d9f0db
MT		 7353int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7354 struct kvm_mp_state *mp_state)
7355{
66450a21 7356 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7357 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7358 vcpu->arch.pv.pv_unhalted)
7359 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7360 else
7361 mp_state->mp_state = vcpu->arch.mp_state;
7362
62d9f0db
MT		 7363 return 0;
7364}
7365
7366int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7367 struct kvm_mp_state *mp_state)
7368{
bce87cce 7369 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7370 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7371 return -EINVAL;
7372
28bf2888
DH		 7373 /* INITs are latched while in SMM */
7374 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7375 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7376 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7377 return -EINVAL;
7378
66450a21
JK		 7379 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7380 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7381 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7382 } else
7383 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7384 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7385 return 0;
7386}
7387
7f3d35fd
KW		 7388int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7389 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7390{
9d74191a 7391 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7392 int ret;
e01c2426 7393
8ec4722d 7394 init_emulate_ctxt(vcpu);
c697518a 7395
7f3d35fd 7396 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7397 has_error_code, error_code);
c697518a 7398
c697518a 7399 if (ret)
19d04437 7400 return EMULATE_FAIL;
37817f29 7401
9d74191a
TY		 7402 kvm_rip_write(vcpu, ctxt->eip);
7403 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7404 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7405 return EMULATE_DONE;
37817f29
IE		 7406}
7407EXPORT_SYMBOL_GPL(kvm_task_switch);
7408
b6c7a5dc
HB		 7409int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7410 struct kvm_sregs *sregs)
7411{
58cb628d 7412 struct msr_data apic_base_msr;
b6c7a5dc 7413 int mmu_reset_needed = 0;
63f42e02 7414 int pending_vec, max_bits, idx;
89a27f4d 7415 struct desc_ptr dt;
b6c7a5dc 7416
d6321d49
RK		 7417 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7418 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7419 return -EINVAL;
7420
d3802286
JM		 7421 apic_base_msr.data = sregs->apic_base;
7422 apic_base_msr.host_initiated = true;
7423 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7424 return -EINVAL;
7425
89a27f4d
GN		 7426 dt.size = sregs->idt.limit;
7427 dt.address = sregs->idt.base;
b6c7a5dc 7428 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7429 dt.size = sregs->gdt.limit;
7430 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7431 kvm_x86_ops->set_gdt(vcpu, &dt);
7432
ad312c7c 7433 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7434 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7435 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7436 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7437
2d3ad1f4 7438 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7439
f6801dff 7440 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7441 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7442
4d4ec087 7443 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7444 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7445 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7446
fc78f519 7447 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7448 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7449 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7450 kvm_update_cpuid(vcpu);
63f42e02
XG		 7451
7452 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7453 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7454 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7455 mmu_reset_needed = 1;
7456 }
63f42e02 7457 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7458
7459 if (mmu_reset_needed)
7460 kvm_mmu_reset_context(vcpu);
7461
a50abc3b 7462 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7463 pending_vec = find_first_bit(
7464 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7465 if (pending_vec < max_bits) {
66fd3f7f 7466 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7467 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7468 }
7469
3e6e0aab
GT		 7470 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7471 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7472 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7473 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7474 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7475 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7476
3e6e0aab
GT		 7477 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7478 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7479
5f0269f5
ME		 7480 update_cr8_intercept(vcpu);
7481
9c3e4aab 7482 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7483 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7484 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7485 !is_protmode(vcpu))
9c3e4aab
MT		 7486 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7487
3842d135
AK		 7488 kvm_make_request(KVM_REQ_EVENT, vcpu);
7489
b6c7a5dc
HB		 7490 return 0;
7491}
7492
d0bfb940
JK		 7493int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7494 struct kvm_guest_debug *dbg)
b6c7a5dc 7495{
355be0b9 7496 unsigned long rflags;
ae675ef0 7497 int i, r;
b6c7a5dc 7498
4f926bf2
JK		 7499 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7500 r = -EBUSY;
7501 if (vcpu->arch.exception.pending)
2122ff5e 7502 goto out;
4f926bf2
JK		 7503 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7504 kvm_queue_exception(vcpu, DB_VECTOR);
7505 else
7506 kvm_queue_exception(vcpu, BP_VECTOR);
7507 }
7508
91586a3b
JK		 7509 /*
7510 * Read rflags as long as potentially injected trace flags are still
7511 * filtered out.
7512 */
7513 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7514
7515 vcpu->guest_debug = dbg->control;
7516 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7517 vcpu->guest_debug = 0;
7518
7519 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7520 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7521 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7522 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7523 } else {
7524 for (i = 0; i < KVM_NR_DB_REGS; i++)
7525 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7526 }
c8639010 7527 kvm_update_dr7(vcpu);
ae675ef0 7528
f92653ee
JK		 7529 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7530 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7531 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7532
91586a3b
JK		 7533 /*
7534 * Trigger an rflags update that will inject or remove the trace
7535 * flags.
7536 */
7537 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7538
a96036b8 7539 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7540
4f926bf2 7541 r = 0;
d0bfb940 7542
2122ff5e 7543out:
b6c7a5dc
HB		 7544
7545 return r;
7546}
7547
8b006791
ZX		 7548/*
7549 * Translate a guest virtual address to a guest physical address.
7550 */
7551int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7552 struct kvm_translation *tr)
7553{
7554 unsigned long vaddr = tr->linear_address;
7555 gpa_t gpa;
f656ce01 7556 int idx;
8b006791 7557
f656ce01 7558 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7559 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7561 tr->physical_address = gpa;
7562 tr->valid = gpa != UNMAPPED_GVA;
7563 tr->writeable = 1;
7564 tr->usermode = 0;
8b006791
ZX		 7565
7566 return 0;
7567}
7568
d0752060
HB		 7569int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7570{
c47ada30 7571 struct fxregs_state *fxsave =
7366ed77 7572 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7573
d0752060
HB		 7574 memcpy(fpu->fpr, fxsave->st_space, 128);
7575 fpu->fcw = fxsave->cwd;
7576 fpu->fsw = fxsave->swd;
7577 fpu->ftwx = fxsave->twd;
7578 fpu->last_opcode = fxsave->fop;
7579 fpu->last_ip = fxsave->rip;
7580 fpu->last_dp = fxsave->rdp;
7581 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7582
d0752060
HB		 7583 return 0;
7584}
7585
7586int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7587{
c47ada30 7588 struct fxregs_state *fxsave =
7366ed77 7589 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7590
d0752060
HB		 7591 memcpy(fxsave->st_space, fpu->fpr, 128);
7592 fxsave->cwd = fpu->fcw;
7593 fxsave->swd = fpu->fsw;
7594 fxsave->twd = fpu->ftwx;
7595 fxsave->fop = fpu->last_opcode;
7596 fxsave->rip = fpu->last_ip;
7597 fxsave->rdp = fpu->last_dp;
7598 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7599
d0752060
HB		 7600 return 0;
7601}
7602
0ee6a517 7603static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7604{
bf935b0b 7605 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7606 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7607 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7608 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7609
2acf923e
DC		 7610 /*
7611 * Ensure guest xcr0 is valid for loading
7612 */
d91cab78 7613 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7614
ad312c7c 7615 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7616}
d0752060
HB		 7617
7618void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7619{
2608d7a1 7620 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7621 return;
7622
2acf923e
DC		 7623 /*
7624 * Restore all possible states in the guest,
7625 * and assume host would use all available bits.
7626 * Guest xcr0 would be loaded later.
7627 */
d0752060 7628 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7629 __kernel_fpu_begin();
003e2e8b 7630 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7631 trace_kvm_fpu(1);
d0752060 7632}
d0752060
HB		 7633
7634void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7635{
3d42de25 7636 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7637 return;
7638
7639 vcpu->guest_fpu_loaded = 0;
4f836347 7640 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7641 __kernel_fpu_end();
f096ed85 7642 ++vcpu->stat.fpu_reload;
0c04851c 7643 trace_kvm_fpu(0);
d0752060 7644}
e9b11c17
ZX		 7645
7646void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7647{
bd768e14
IY		 7648 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7649
12f9a48f 7650 kvmclock_reset(vcpu);
7f1ea208 7651
e9b11c17 7652 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7653 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7654}
7655
7656struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7657 unsigned int id)
7658{
c447e76b
LL		 7659 struct kvm_vcpu *vcpu;
7660
6755bae8
ZA		 7661 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7662 printk_once(KERN_WARNING
7663 "kvm: SMP vm created on host with unstable TSC; "
7664 "guest TSC will not be reliable\n");
c447e76b
LL		 7665
7666 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7667
c447e76b 7668 return vcpu;
26e5215f 7669}
e9b11c17 7670
26e5215f
AK		 7671int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7672{
7673 int r;
e9b11c17 7674
19efffa2 7675 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7676 r = vcpu_load(vcpu);
7677 if (r)
7678 return r;
d28bc9dd 7679 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7680 kvm_mmu_setup(vcpu);
e9b11c17 7681 vcpu_put(vcpu);
26e5215f 7682 return r;
e9b11c17
ZX		 7683}
7684
31928aa5 7685void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7686{
8fe8ab46 7687 struct msr_data msr;
332967a3 7688 struct kvm *kvm = vcpu->kvm;
42897d86 7689
d3457c87
RK		 7690 kvm_hv_vcpu_postcreate(vcpu);
7691
31928aa5
DD		 7692 if (vcpu_load(vcpu))
7693 return;
8fe8ab46
WA		 7694 msr.data = 0x0;
7695 msr.index = MSR_IA32_TSC;
7696 msr.host_initiated = true;
7697 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7698 vcpu_put(vcpu);
7699
630994b3
MT		 7700 if (!kvmclock_periodic_sync)
7701 return;
7702
332967a3
AJ		 7703 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7704 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7705}
7706
d40ccc62 7707void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7708{
9fc77441 7709 int r;
344d9588
GN		 7710 vcpu->arch.apf.msr_val = 0;
7711
9fc77441
MT		 7712 r = vcpu_load(vcpu);
7713 BUG_ON(r);
e9b11c17
ZX		 7714 kvm_mmu_unload(vcpu);
7715 vcpu_put(vcpu);
7716
7717 kvm_x86_ops->vcpu_free(vcpu);
7718}
7719
d28bc9dd 7720void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7721{
e69fab5d
PB		 7722 vcpu->arch.hflags = 0;
7723
c43203ca 7724 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7725 atomic_set(&vcpu->arch.nmi_queued, 0);
7726 vcpu->arch.nmi_pending = 0;
448fa4a9 7727 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7728 kvm_clear_interrupt_queue(vcpu);
7729 kvm_clear_exception_queue(vcpu);
448fa4a9 7730
42dbaa5a 7731 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7732 kvm_update_dr0123(vcpu);
6f43ed01 7733 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7734 kvm_update_dr6(vcpu);
42dbaa5a 7735 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7736 kvm_update_dr7(vcpu);
42dbaa5a 7737
1119022c
NA		 7738 vcpu->arch.cr2 = 0;
7739
3842d135 7740 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7741 vcpu->arch.apf.msr_val = 0;
c9aaa895 7742 vcpu->arch.st.msr_val = 0;
3842d135 7743
12f9a48f
GC		 7744 kvmclock_reset(vcpu);
7745
af585b92
GN		 7746 kvm_clear_async_pf_completion_queue(vcpu);
7747 kvm_async_pf_hash_reset(vcpu);
7748 vcpu->arch.apf.halted = false;
3842d135 7749
64d60670 7750 if (!init_event) {
d28bc9dd 7751 kvm_pmu_reset(vcpu);
64d60670 7752 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7753
7754 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7755 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7756 }
f5132b01 7757
66f7b72e
JS		 7758 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7759 vcpu->arch.regs_avail = ~0;
7760 vcpu->arch.regs_dirty = ~0;
7761
d28bc9dd 7762 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7763}
7764
2b4a273b 7765void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7766{
7767 struct kvm_segment cs;
7768
7769 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7770 cs.selector = vector << 8;
7771 cs.base = vector << 12;
7772 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7773 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7774}
7775
13a34e06 7776int kvm_arch_hardware_enable(void)
e9b11c17 7777{
ca84d1a2
ZA		 7778 struct kvm *kvm;
7779 struct kvm_vcpu *vcpu;
7780 int i;
0dd6a6ed
ZA		 7781 int ret;
7782 u64 local_tsc;
7783 u64 max_tsc = 0;
7784 bool stable, backwards_tsc = false;
18863bdd
AK		 7785
7786 kvm_shared_msr_cpu_online();
13a34e06 7787 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7788 if (ret != 0)
7789 return ret;
7790
4ea1636b 7791 local_tsc = rdtsc();
0dd6a6ed
ZA		 7792 stable = !check_tsc_unstable();
7793 list_for_each_entry(kvm, &vm_list, vm_list) {
7794 kvm_for_each_vcpu(i, vcpu, kvm) {
7795 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7796 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7797 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7798 backwards_tsc = true;
7799 if (vcpu->arch.last_host_tsc > max_tsc)
7800 max_tsc = vcpu->arch.last_host_tsc;
7801 }
7802 }
7803 }
7804
7805 /*
7806 * Sometimes, even reliable TSCs go backwards. This happens on
7807 * platforms that reset TSC during suspend or hibernate actions, but
7808 * maintain synchronization. We must compensate. Fortunately, we can
7809 * detect that condition here, which happens early in CPU bringup,
7810 * before any KVM threads can be running. Unfortunately, we can't
7811 * bring the TSCs fully up to date with real time, as we aren't yet far
7812 * enough into CPU bringup that we know how much real time has actually
108b249c 7813 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7814 * variables that haven't been updated yet.
7815 *
7816 * So we simply find the maximum observed TSC above, then record the
7817 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7818 * the adjustment will be applied. Note that we accumulate
7819 * adjustments, in case multiple suspend cycles happen before some VCPU
7820 * gets a chance to run again. In the event that no KVM threads get a
7821 * chance to run, we will miss the entire elapsed period, as we'll have
7822 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7823 * loose cycle time. This isn't too big a deal, since the loss will be
7824 * uniform across all VCPUs (not to mention the scenario is extremely
7825 * unlikely). It is possible that a second hibernate recovery happens
7826 * much faster than a first, causing the observed TSC here to be
7827 * smaller; this would require additional padding adjustment, which is
7828 * why we set last_host_tsc to the local tsc observed here.
7829 *
7830 * N.B. - this code below runs only on platforms with reliable TSC,
7831 * as that is the only way backwards_tsc is set above. Also note
7832 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7833 * have the same delta_cyc adjustment applied if backwards_tsc
7834 * is detected. Note further, this adjustment is only done once,
7835 * as we reset last_host_tsc on all VCPUs to stop this from being
7836 * called multiple times (one for each physical CPU bringup).
7837 *
4a969980 7838 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7839 * will be compensated by the logic in vcpu_load, which sets the TSC to
7840 * catchup mode. This will catchup all VCPUs to real time, but cannot
7841 * guarantee that they stay in perfect synchronization.
7842 */
7843 if (backwards_tsc) {
7844 u64 delta_cyc = max_tsc - local_tsc;
7845 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7846 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7847 kvm_for_each_vcpu(i, vcpu, kvm) {
7848 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7849 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7850 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7851 }
7852
7853 /*
7854 * We have to disable TSC offset matching.. if you were
7855 * booting a VM while issuing an S4 host suspend....
7856 * you may have some problem. Solving this issue is
7857 * left as an exercise to the reader.
7858 */
7859 kvm->arch.last_tsc_nsec = 0;
7860 kvm->arch.last_tsc_write = 0;
7861 }
7862
7863 }
7864 return 0;
e9b11c17
ZX		 7865}
7866
13a34e06 7867void kvm_arch_hardware_disable(void)
e9b11c17 7868{
13a34e06
RK		 7869 kvm_x86_ops->hardware_disable();
7870 drop_user_return_notifiers();
e9b11c17
ZX		 7871}
7872
7873int kvm_arch_hardware_setup(void)
7874{
9e9c3fe4
NA		 7875 int r;
7876
7877 r = kvm_x86_ops->hardware_setup();
7878 if (r != 0)
7879 return r;
7880
35181e86
HZ		 7881 if (kvm_has_tsc_control) {
7882 /*
7883 * Make sure the user can only configure tsc_khz values that
7884 * fit into a signed integer.
7885 * A min value is not calculated needed because it will always
7886 * be 1 on all machines.
7887 */
7888 u64 max = min(0x7fffffffULL,
7889 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7890 kvm_max_guest_tsc_khz = max;
7891
ad721883 7892 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7893 }
ad721883 7894
9e9c3fe4
NA		 7895 kvm_init_msr_list();
7896 return 0;
e9b11c17
ZX		 7897}
7898
7899void kvm_arch_hardware_unsetup(void)
7900{
7901 kvm_x86_ops->hardware_unsetup();
7902}
7903
7904void kvm_arch_check_processor_compat(void *rtn)
7905{
7906 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7907}
7908
7909bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7910{
7911 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7912}
7913EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7914
7915bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7916{
7917 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7918}
7919
54e9818f 7920struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7921EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7922
e9b11c17
ZX		 7923int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7924{
7925 struct page *page;
7926 struct kvm *kvm;
7927 int r;
7928
7929 BUG_ON(vcpu->kvm == NULL);
7930 kvm = vcpu->kvm;
7931
d62caabb 7932 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7933 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7934 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7935 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7936 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7937 else
a4535290 7938 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7939
7940 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7941 if (!page) {
7942 r = -ENOMEM;
7943 goto fail;
7944 }
ad312c7c 7945 vcpu->arch.pio_data = page_address(page);
e9b11c17 7946
cc578287 7947 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7948
e9b11c17
ZX		 7949 r = kvm_mmu_create(vcpu);
7950 if (r < 0)
7951 goto fail_free_pio_data;
7952
7953 if (irqchip_in_kernel(kvm)) {
7954 r = kvm_create_lapic(vcpu);
7955 if (r < 0)
7956 goto fail_mmu_destroy;
54e9818f
GN		 7957 } else
7958 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7959
890ca9ae
HY		 7960 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7961 GFP_KERNEL);
7962 if (!vcpu->arch.mce_banks) {
7963 r = -ENOMEM;
443c39bc 7964 goto fail_free_lapic;
890ca9ae
HY		 7965 }
7966 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7967
f1797359
WY		 7968 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7969 r = -ENOMEM;
f5f48ee1 7970 goto fail_free_mce_banks;
f1797359 7971 }
f5f48ee1 7972
0ee6a517 7973 fx_init(vcpu);
66f7b72e 7974
ba904635 7975 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7976 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7977
7978 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7979 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7980
5a4f55cd
EK		 7981 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7982
74545705
RK		 7983 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7984
af585b92 7985 kvm_async_pf_hash_reset(vcpu);
f5132b01 7986 kvm_pmu_init(vcpu);
af585b92 7987
1c1a9ce9 7988 vcpu->arch.pending_external_vector = -1;
de63ad4c 7989 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 7990
5c919412
AS		 7991 kvm_hv_vcpu_init(vcpu);
7992
e9b11c17 7993 return 0;
0ee6a517 7994
f5f48ee1
SY		 7995fail_free_mce_banks:
7996 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7997fail_free_lapic:
7998 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7999fail_mmu_destroy:
8000 kvm_mmu_destroy(vcpu);
8001fail_free_pio_data:
ad312c7c 8002 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8003fail:
8004 return r;
8005}
8006
8007void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8008{
f656ce01
MT		 8009 int idx;
8010
1f4b34f8 8011 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8012 kvm_pmu_destroy(vcpu);
36cb93fd 8013 kfree(vcpu->arch.mce_banks);
e9b11c17 8014 kvm_free_lapic(vcpu);
f656ce01 8015 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8016 kvm_mmu_destroy(vcpu);
f656ce01 8017 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8018 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8019 if (!lapic_in_kernel(vcpu))
54e9818f 8020 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8021}
d19a9cd2 8022
e790d9ef
RK		 8023void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8024{
ae97a3b8 8025 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8026}
8027
e08b9637 8028int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8029{
e08b9637
CO		 8030 if (type)
8031 return -EINVAL;
8032
6ef768fa 8033 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8034 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8035 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8036 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8037 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8038
5550af4d
SY		 8039 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8040 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8041 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8042 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8043 &kvm->arch.irq_sources_bitmap);
5550af4d 8044
038f8c11 8045 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8046 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8047 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8048 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8049
108b249c 8050 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8051 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8052
7e44e449 8053 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8054 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8055
0eb05bf2 8056 kvm_page_track_init(kvm);
13d268ca 8057 kvm_mmu_init_vm(kvm);
0eb05bf2 8058
03543133
SS		 8059 if (kvm_x86_ops->vm_init)
8060 return kvm_x86_ops->vm_init(kvm);
8061
d89f5eff 8062 return 0;
d19a9cd2
ZX		 8063}
8064
8065static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8066{
9fc77441
MT		 8067 int r;
8068 r = vcpu_load(vcpu);
8069 BUG_ON(r);
d19a9cd2
ZX		 8070 kvm_mmu_unload(vcpu);
8071 vcpu_put(vcpu);
8072}
8073
8074static void kvm_free_vcpus(struct kvm *kvm)
8075{
8076 unsigned int i;
988a2cae 8077 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8078
8079 /*
8080 * Unpin any mmu pages first.
8081 */
af585b92
GN		 8082 kvm_for_each_vcpu(i, vcpu, kvm) {
8083 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8084 kvm_unload_vcpu_mmu(vcpu);
af585b92 8085 }
988a2cae
GN		 8086 kvm_for_each_vcpu(i, vcpu, kvm)
8087 kvm_arch_vcpu_free(vcpu);
8088
8089 mutex_lock(&kvm->lock);
8090 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8091 kvm->vcpus[i] = NULL;
d19a9cd2 8092
988a2cae
GN		 8093 atomic_set(&kvm->online_vcpus, 0);
8094 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8095}
8096
ad8ba2cd
SY		 8097void kvm_arch_sync_events(struct kvm *kvm)
8098{
332967a3 8099 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8100 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8101 kvm_free_pit(kvm);
ad8ba2cd
SY		 8102}
8103
1d8007bd 8104int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8105{
8106 int i, r;
25188b99 8107 unsigned long hva;
f0d648bd
PB		 8108 struct kvm_memslots *slots = kvm_memslots(kvm);
8109 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8110
8111 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8112 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8113 return -EINVAL;
9da0e4d5 8114
f0d648bd
PB		 8115 slot = id_to_memslot(slots, id);
8116 if (size) {
b21629da 8117 if (slot->npages)
f0d648bd
PB		 8118 return -EEXIST;
8119
8120 /*
8121 * MAP_SHARED to prevent internal slot pages from being moved
8122 * by fork()/COW.
8123 */
8124 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8125 MAP_SHARED | MAP_ANONYMOUS, 0);
8126 if (IS_ERR((void *)hva))
8127 return PTR_ERR((void *)hva);
8128 } else {
8129 if (!slot->npages)
8130 return 0;
8131
8132 hva = 0;
8133 }
8134
8135 old = *slot;
9da0e4d5 8136 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8137 struct kvm_userspace_memory_region m;
9da0e4d5 8138
1d8007bd
PB		 8139 m.slot = id | (i << 16);
8140 m.flags = 0;
8141 m.guest_phys_addr = gpa;
f0d648bd 8142 m.userspace_addr = hva;
1d8007bd 8143 m.memory_size = size;
9da0e4d5
PB		 8144 r = __kvm_set_memory_region(kvm, &m);
8145 if (r < 0)
8146 return r;
8147 }
8148
f0d648bd
PB		 8149 if (!size) {
8150 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8151 WARN_ON(r < 0);
8152 }
8153
9da0e4d5
PB		 8154 return 0;
8155}
8156EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8157
1d8007bd 8158int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8159{
8160 int r;
8161
8162 mutex_lock(&kvm->slots_lock);
1d8007bd 8163 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8164 mutex_unlock(&kvm->slots_lock);
8165
8166 return r;
8167}
8168EXPORT_SYMBOL_GPL(x86_set_memory_region);
8169
d19a9cd2
ZX		 8170void kvm_arch_destroy_vm(struct kvm *kvm)
8171{
27469d29
AH		 8172 if (current->mm == kvm->mm) {
8173 /*
8174 * Free memory regions allocated on behalf of userspace,
8175 * unless the the memory map has changed due to process exit
8176 * or fd copying.
8177 */
1d8007bd
PB		 8178 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8179 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8180 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8181 }
03543133
SS		 8182 if (kvm_x86_ops->vm_destroy)
8183 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8184 kvm_pic_destroy(kvm);
8185 kvm_ioapic_destroy(kvm);
d19a9cd2 8186 kvm_free_vcpus(kvm);
af1bae54 8187 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8188 kvm_mmu_uninit_vm(kvm);
2beb6dad 8189 kvm_page_track_cleanup(kvm);
d19a9cd2 8190}
0de10343 8191
5587027c 8192void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8193 struct kvm_memory_slot *dont)
8194{
8195 int i;
8196
d89cc617
TY		 8197 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8198 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8199 kvfree(free->arch.rmap[i]);
d89cc617 8200 free->arch.rmap[i] = NULL;
77d11309 8201 }
d89cc617
TY		 8202 if (i == 0)
8203 continue;
8204
8205 if (!dont || free->arch.lpage_info[i - 1] !=
8206 dont->arch.lpage_info[i - 1]) {
548ef284 8207 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8208 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8209 }
8210 }
21ebbeda
XG		 8211
8212 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8213}
8214
5587027c
AK		 8215int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8216 unsigned long npages)
db3fe4eb
TY		 8217{
8218 int i;
8219
d89cc617 8220 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8221 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8222 unsigned long ugfn;
8223 int lpages;
d89cc617 8224 int level = i + 1;
db3fe4eb
TY		 8225
8226 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8227 slot->base_gfn, level) + 1;
8228
d89cc617 8229 slot->arch.rmap[i] =
a7c3e901 8230 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8231 if (!slot->arch.rmap[i])
77d11309 8232 goto out_free;
d89cc617
TY		 8233 if (i == 0)
8234 continue;
77d11309 8235
a7c3e901 8236 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8237 if (!linfo)
db3fe4eb
TY		 8238 goto out_free;
8239
92f94f1e
XG		 8240 slot->arch.lpage_info[i - 1] = linfo;
8241
db3fe4eb 8242 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8243 linfo[0].disallow_lpage = 1;
db3fe4eb 8244 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8245 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8246 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8247 /*
8248 * If the gfn and userspace address are not aligned wrt each
8249 * other, or if explicitly asked to, disable large page
8250 * support for this slot
8251 */
8252 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8253 !kvm_largepages_enabled()) {
8254 unsigned long j;
8255
8256 for (j = 0; j < lpages; ++j)
92f94f1e 8257 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8258 }
8259 }
8260
21ebbeda
XG		 8261 if (kvm_page_track_create_memslot(slot, npages))
8262 goto out_free;
8263
db3fe4eb
TY		 8264 return 0;
8265
8266out_free:
d89cc617 8267 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8268 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8269 slot->arch.rmap[i] = NULL;
8270 if (i == 0)
8271 continue;
8272
548ef284 8273 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8274 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8275 }
8276 return -ENOMEM;
8277}
8278
15f46015 8279void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8280{
e6dff7d1
TY		 8281 /*
8282 * memslots->generation has been incremented.
8283 * mmio generation may have reached its maximum value.
8284 */
54bf36aa 8285 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8286}
8287
f7784b8e
MT		 8288int kvm_arch_prepare_memory_region(struct kvm *kvm,
8289 struct kvm_memory_slot *memslot,
09170a49 8290 const struct kvm_userspace_memory_region *mem,
7b6195a9 8291 enum kvm_mr_change change)
0de10343 8292{
f7784b8e
MT		 8293 return 0;
8294}
8295
88178fd4
KH		 8296static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8297 struct kvm_memory_slot *new)
8298{
8299 /* Still write protect RO slot */
8300 if (new->flags & KVM_MEM_READONLY) {
8301 kvm_mmu_slot_remove_write_access(kvm, new);
8302 return;
8303 }
8304
8305 /*
8306 * Call kvm_x86_ops dirty logging hooks when they are valid.
8307 *
8308 * kvm_x86_ops->slot_disable_log_dirty is called when:
8309 *
8310 * - KVM_MR_CREATE with dirty logging is disabled
8311 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8312 *
8313 * The reason is, in case of PML, we need to set D-bit for any slots
8314 * with dirty logging disabled in order to eliminate unnecessary GPA
8315 * logging in PML buffer (and potential PML buffer full VMEXT). This
8316 * guarantees leaving PML enabled during guest's lifetime won't have
8317 * any additonal overhead from PML when guest is running with dirty
8318 * logging disabled for memory slots.
8319 *
8320 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8321 * to dirty logging mode.
8322 *
8323 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8324 *
8325 * In case of write protect:
8326 *
8327 * Write protect all pages for dirty logging.
8328 *
8329 * All the sptes including the large sptes which point to this
8330 * slot are set to readonly. We can not create any new large
8331 * spte on this slot until the end of the logging.
8332 *
8333 * See the comments in fast_page_fault().
8334 */
8335 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8336 if (kvm_x86_ops->slot_enable_log_dirty)
8337 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8338 else
8339 kvm_mmu_slot_remove_write_access(kvm, new);
8340 } else {
8341 if (kvm_x86_ops->slot_disable_log_dirty)
8342 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8343 }
8344}
8345
f7784b8e 8346void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8347 const struct kvm_userspace_memory_region *mem,
8482644a 8348 const struct kvm_memory_slot *old,
f36f3f28 8349 const struct kvm_memory_slot *new,
8482644a 8350 enum kvm_mr_change change)
f7784b8e 8351{
8482644a 8352 int nr_mmu_pages = 0;
f7784b8e 8353
48c0e4e9
XG		 8354 if (!kvm->arch.n_requested_mmu_pages)
8355 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8356
48c0e4e9 8357 if (nr_mmu_pages)
0de10343 8358 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8359
3ea3b7fa
WL		 8360 /*
8361 * Dirty logging tracks sptes in 4k granularity, meaning that large
8362 * sptes have to be split. If live migration is successful, the guest
8363 * in the source machine will be destroyed and large sptes will be
8364 * created in the destination. However, if the guest continues to run
8365 * in the source machine (for example if live migration fails), small
8366 * sptes will remain around and cause bad performance.
8367 *
8368 * Scan sptes if dirty logging has been stopped, dropping those
8369 * which can be collapsed into a single large-page spte. Later
8370 * page faults will create the large-page sptes.
8371 */
8372 if ((change != KVM_MR_DELETE) &&
8373 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8374 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8375 kvm_mmu_zap_collapsible_sptes(kvm, new);
8376
c972f3b1 8377 /*
88178fd4 8378 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8379 *
88178fd4
KH		 8380 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8381 * been zapped so no dirty logging staff is needed for old slot. For
8382 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8383 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8384 *
8385 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8386 */
88178fd4 8387 if (change != KVM_MR_DELETE)
f36f3f28 8388 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8389}
1d737c8a 8390
2df72e9b 8391void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8392{
6ca18b69 8393 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8394}
8395
2df72e9b
MT		 8396void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8397 struct kvm_memory_slot *slot)
8398{
ae7cd873 8399 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8400}
8401
5d9bc648
PB		 8402static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8403{
8404 if (!list_empty_careful(&vcpu->async_pf.done))
8405 return true;
8406
8407 if (kvm_apic_has_events(vcpu))
8408 return true;
8409
8410 if (vcpu->arch.pv.pv_unhalted)
8411 return true;
8412
47a66eed
Z		 8413 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8414 (vcpu->arch.nmi_pending &&
8415 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8416 return true;
8417
47a66eed
Z		 8418 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8419 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8420 return true;
8421
5d9bc648
PB		 8422 if (kvm_arch_interrupt_allowed(vcpu) &&
8423 kvm_cpu_has_interrupt(vcpu))
8424 return true;
8425
1f4b34f8
AS		 8426 if (kvm_hv_has_stimer_pending(vcpu))
8427 return true;
8428
5d9bc648
PB		 8429 return false;
8430}
8431
1d737c8a
ZX		 8432int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8433{
5d9bc648 8434 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8435}
5736199a 8436
199b5763
LM		 8437bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8438{
de63ad4c 8439 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8440}
8441
b6d33834 8442int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8443{
b6d33834 8444 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8445}
78646121
GN		 8446
8447int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8448{
8449 return kvm_x86_ops->interrupt_allowed(vcpu);
8450}
229456fc 8451
82b32774 8452unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8453{
82b32774
NA		 8454 if (is_64_bit_mode(vcpu))
8455 return kvm_rip_read(vcpu);
8456 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8457 kvm_rip_read(vcpu));
8458}
8459EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8460
82b32774
NA		 8461bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8462{
8463 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8464}
8465EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8466
94fe45da
JK		 8467unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8468{
8469 unsigned long rflags;
8470
8471 rflags = kvm_x86_ops->get_rflags(vcpu);
8472 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8473 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8474 return rflags;
8475}
8476EXPORT_SYMBOL_GPL(kvm_get_rflags);
8477
6addfc42 8478static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8479{
8480 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8481 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8482 rflags |= X86_EFLAGS_TF;
94fe45da 8483 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8484}
8485
8486void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8487{
8488 __kvm_set_rflags(vcpu, rflags);
3842d135 8489 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8490}
8491EXPORT_SYMBOL_GPL(kvm_set_rflags);
8492
56028d08
GN		 8493void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8494{
8495 int r;
8496
fb67e14f 8497 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8498 work->wakeup_all)
56028d08
GN		 8499 return;
8500
8501 r = kvm_mmu_reload(vcpu);
8502 if (unlikely(r))
8503 return;
8504
fb67e14f
XG		 8505 if (!vcpu->arch.mmu.direct_map &&
8506 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8507 return;
8508
56028d08
GN		 8509 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8510}
8511
af585b92
GN		 8512static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8513{
8514 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8515}
8516
8517static inline u32 kvm_async_pf_next_probe(u32 key)
8518{
8519 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8520}
8521
8522static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8523{
8524 u32 key = kvm_async_pf_hash_fn(gfn);
8525
8526 while (vcpu->arch.apf.gfns[key] != ~0)
8527 key = kvm_async_pf_next_probe(key);
8528
8529 vcpu->arch.apf.gfns[key] = gfn;
8530}
8531
8532static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8533{
8534 int i;
8535 u32 key = kvm_async_pf_hash_fn(gfn);
8536
8537 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8538 (vcpu->arch.apf.gfns[key] != gfn &&
8539 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8540 key = kvm_async_pf_next_probe(key);
8541
8542 return key;
8543}
8544
8545bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8546{
8547 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8548}
8549
8550static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8551{
8552 u32 i, j, k;
8553
8554 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8555 while (true) {
8556 vcpu->arch.apf.gfns[i] = ~0;
8557 do {
8558 j = kvm_async_pf_next_probe(j);
8559 if (vcpu->arch.apf.gfns[j] == ~0)
8560 return;
8561 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8562 /*
8563 * k lies cyclically in ]i,j]
8564 * | i.k.j |
8565 * |....j i.k.| or |.k..j i...|
8566 */
8567 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8568 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8569 i = j;
8570 }
8571}
8572
7c90705b
GN		 8573static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8574{
4e335d9e
PB		 8575
8576 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8577 sizeof(val));
7c90705b
GN		 8578}
8579
af585b92
GN		 8580void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8581 struct kvm_async_pf *work)
8582{
6389ee94
AK		 8583 struct x86_exception fault;
8584
7c90705b 8585 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8586 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8587
8588 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8589 (vcpu->arch.apf.send_user_only &&
8590 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8591 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8592 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8593 fault.vector = PF_VECTOR;
8594 fault.error_code_valid = true;
8595 fault.error_code = 0;
8596 fault.nested_page_fault = false;
8597 fault.address = work->arch.token;
adfe20fb 8598 fault.async_page_fault = true;
6389ee94 8599 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8600 }
af585b92
GN		 8601}
8602
8603void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8604 struct kvm_async_pf *work)
8605{
6389ee94
AK		 8606 struct x86_exception fault;
8607
f2e10669 8608 if (work->wakeup_all)
7c90705b
GN		 8609 work->arch.token = ~0; /* broadcast wakeup */
8610 else
8611 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8612 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8613
8614 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8615 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8616 fault.vector = PF_VECTOR;
8617 fault.error_code_valid = true;
8618 fault.error_code = 0;
8619 fault.nested_page_fault = false;
8620 fault.address = work->arch.token;
adfe20fb 8621 fault.async_page_fault = true;
6389ee94 8622 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8623 }
e6d53e3b 8624 vcpu->arch.apf.halted = false;
a4fa1635 8625 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8626}
8627
8628bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8629{
8630 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8631 return true;
8632 else
9bc1f09f 8633 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8634}
8635
5544eb9b
PB		 8636void kvm_arch_start_assignment(struct kvm *kvm)
8637{
8638 atomic_inc(&kvm->arch.assigned_device_count);
8639}
8640EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8641
8642void kvm_arch_end_assignment(struct kvm *kvm)
8643{
8644 atomic_dec(&kvm->arch.assigned_device_count);
8645}
8646EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8647
8648bool kvm_arch_has_assigned_device(struct kvm *kvm)
8649{
8650 return atomic_read(&kvm->arch.assigned_device_count);
8651}
8652EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8653
e0f0bbc5
AW		 8654void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8655{
8656 atomic_inc(&kvm->arch.noncoherent_dma_count);
8657}
8658EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8659
8660void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8661{
8662 atomic_dec(&kvm->arch.noncoherent_dma_count);
8663}
8664EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8665
8666bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8667{
8668 return atomic_read(&kvm->arch.noncoherent_dma_count);
8669}
8670EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8671
14717e20
AW		 8672bool kvm_arch_has_irq_bypass(void)
8673{
8674 return kvm_x86_ops->update_pi_irte != NULL;
8675}
8676
87276880
FW		 8677int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8678 struct irq_bypass_producer *prod)
8679{
8680 struct kvm_kernel_irqfd *irqfd =
8681 container_of(cons, struct kvm_kernel_irqfd, consumer);
8682
14717e20 8683 irqfd->producer = prod;
87276880 8684
14717e20
AW		 8685 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8686 prod->irq, irqfd->gsi, 1);
87276880
FW		 8687}
8688
8689void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8690 struct irq_bypass_producer *prod)
8691{
8692 int ret;
8693 struct kvm_kernel_irqfd *irqfd =
8694 container_of(cons, struct kvm_kernel_irqfd, consumer);
8695
87276880
FW		 8696 WARN_ON(irqfd->producer != prod);
8697 irqfd->producer = NULL;
8698
8699 /*
8700 * When producer of consumer is unregistered, we change back to
8701 * remapped mode, so we can re-use the current implementation
bb3541f1 8702 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8703 * int this case doesn't want to receive the interrupts.
8704 */
8705 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8706 if (ret)
8707 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8708 " fails: %d\n", irqfd->consumer.token, ret);
8709}
8710
8711int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8712 uint32_t guest_irq, bool set)
8713{
8714 if (!kvm_x86_ops->update_pi_irte)
8715 return -EINVAL;
8716
8717 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8718}
8719
52004014
FW		 8720bool kvm_vector_hashing_enabled(void)
8721{
8722 return vector_hashing;
8723}
8724EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8725
229456fc 8726EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8727EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8728EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8729EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8730EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8731EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8732EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8733EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8734EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8735EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8737EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8738EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8739EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8740EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8741EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8742EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8743EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8744EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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