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KVM: x86: do mask out upper bits of PAE CR3
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
18863bdd
AK		 137#define KVM_NR_SHARED_MSRS 16
138
139struct kvm_shared_msrs_global {
140 int nr;
2bf78fa7 141 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144struct kvm_shared_msrs {
145 struct user_return_notifier urn;
146 bool registered;
2bf78fa7
SY		 147 struct kvm_shared_msr_values {
148 u64 host;
149 u64 curr;
150 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 151};
152
153static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 154static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 155
417bc304 156struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 157 { "pf_fixed", VCPU_STAT(pf_fixed) },
158 { "pf_guest", VCPU_STAT(pf_guest) },
159 { "tlb_flush", VCPU_STAT(tlb_flush) },
160 { "invlpg", VCPU_STAT(invlpg) },
161 { "exits", VCPU_STAT(exits) },
162 { "io_exits", VCPU_STAT(io_exits) },
163 { "mmio_exits", VCPU_STAT(mmio_exits) },
164 { "signal_exits", VCPU_STAT(signal_exits) },
165 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 166 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 167 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 168 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 169 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 170 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 171 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 172 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 173 { "request_irq", VCPU_STAT(request_irq_exits) },
174 { "irq_exits", VCPU_STAT(irq_exits) },
175 { "host_state_reload", VCPU_STAT(host_state_reload) },
176 { "efer_reload", VCPU_STAT(efer_reload) },
177 { "fpu_reload", VCPU_STAT(fpu_reload) },
178 { "insn_emulation", VCPU_STAT(insn_emulation) },
179 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 180 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 181 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 182 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 195 { NULL }
196};
197
2acf923e
DC		 198u64 __read_mostly host_xcr0;
199
b6785def 200static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 201
af585b92
GN		 202static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
203{
204 int i;
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
207}
208
18863bdd
AK		 209static void kvm_on_user_return(struct user_return_notifier *urn)
210{
211 unsigned slot;
18863bdd
AK		 212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 214 struct kvm_shared_msr_values *values;
1650b4eb
IA		 215 unsigned long flags;
216
217 /*
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
220 */
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
225 }
226 local_irq_restore(flags);
18863bdd 227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
18863bdd
AK		 232 }
233 }
18863bdd
AK		 234}
235
2bf78fa7 236static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 237{
18863bdd 238 u64 value;
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 241
2bf78fa7
SY		 242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
246 return;
247 }
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
251}
252
253void kvm_define_shared_msr(unsigned slot, u32 msr)
254{
0123be42 255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 256 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
261
262static void kvm_shared_msr_cpu_online(void)
263{
264 unsigned i;
18863bdd
AK		 265
266 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 267 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 268}
269
8b3c3104 270int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 274 int err;
18863bdd 275
2bf78fa7 276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 277 return 0;
2bf78fa7 278 smsr->values[slot].curr = value;
8b3c3104
AH		 279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
280 if (err)
281 return 1;
282
18863bdd
AK		 283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
287 }
8b3c3104 288 return 0;
18863bdd
AK		 289}
290EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
291
13a34e06 292static void drop_user_return_notifiers(void)
3548bab5 293{
013f6a5d
MT		 294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 296
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
299}
300
6866b83e
CO		 301u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
302{
8a5a87d9 303 return vcpu->arch.apic_base;
6866b83e
CO		 304}
305EXPORT_SYMBOL_GPL(kvm_get_apic_base);
306
58cb628d
JK		 307int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
308{
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
314 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
315
316 if (!msr_info->host_initiated &&
317 ((msr_info->data & reserved_bits) != 0 ||
318 new_state == X2APIC_ENABLE ||
319 (new_state == MSR_IA32_APICBASE_ENABLE &&
320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
322 old_state == 0)))
323 return 1;
324
325 kvm_lapic_set_base(vcpu, msr_info->data);
326 return 0;
6866b83e
CO		 327}
328EXPORT_SYMBOL_GPL(kvm_set_apic_base);
329
2605fc21 330asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 331{
332 /* Fault while not rebooting. We want the trace. */
333 BUG();
334}
335EXPORT_SYMBOL_GPL(kvm_spurious_fault);
336
3fd28fce
ED		 337#define EXCPT_BENIGN 0
338#define EXCPT_CONTRIBUTORY 1
339#define EXCPT_PF 2
340
341static int exception_class(int vector)
342{
343 switch (vector) {
344 case PF_VECTOR:
345 return EXCPT_PF;
346 case DE_VECTOR:
347 case TS_VECTOR:
348 case NP_VECTOR:
349 case SS_VECTOR:
350 case GP_VECTOR:
351 return EXCPT_CONTRIBUTORY;
352 default:
353 break;
354 }
355 return EXCPT_BENIGN;
356}
357
d6e8c854
NA		 358#define EXCPT_FAULT 0
359#define EXCPT_TRAP 1
360#define EXCPT_ABORT 2
361#define EXCPT_INTERRUPT 3
362
363static int exception_type(int vector)
364{
365 unsigned int mask;
366
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
369
370 mask = 1 << vector;
371
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
374 return EXCPT_TRAP;
375
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
377 return EXCPT_ABORT;
378
379 /* Reserved exceptions will result in fault */
380 return EXCPT_FAULT;
381}
382
3fd28fce 383static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 384 unsigned nr, bool has_error, u32 error_code,
385 bool reinject)
3fd28fce
ED		 386{
387 u32 prev_nr;
388 int class1, class2;
389
3842d135
AK		 390 kvm_make_request(KVM_REQ_EVENT, vcpu);
391
3fd28fce
ED		 392 if (!vcpu->arch.exception.pending) {
393 queue:
3ffb2468
NA		 394 if (has_error && !is_protmode(vcpu))
395 has_error = false;
3fd28fce
ED		 396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
3f0fd292 400 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 401 return;
402 }
403
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
a8eeb04a 408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 409 return;
410 }
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
420 } else
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
423 exception */
424 goto queue;
425}
426
298101da
AK		 427void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
428{
ce7ddec4 429 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 430}
431EXPORT_SYMBOL_GPL(kvm_queue_exception);
432
ce7ddec4
JR		 433void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
434{
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
436}
437EXPORT_SYMBOL_GPL(kvm_requeue_exception);
438
6affcbed 439int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 440{
db8fcefa
AP		 441 if (err)
442 kvm_inject_gp(vcpu, 0);
443 else
6affcbed
KH		 444 return kvm_skip_emulated_instruction(vcpu);
445
446 return 1;
db8fcefa
AP		 447}
448EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 449
6389ee94 450void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 451{
452 ++vcpu->stat.pf_guest;
adfe20fb
WL		 453 vcpu->arch.exception.nested_apf =
454 is_guest_mode(vcpu) && fault->async_page_fault;
455 if (vcpu->arch.exception.nested_apf)
456 vcpu->arch.apf.nested_apf_token = fault->address;
457 else
458 vcpu->arch.cr2 = fault->address;
6389ee94 459 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 460}
27d6c865 461EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 462
ef54bcfe 463static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 464{
6389ee94
AK		 465 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
466 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 467 else
6389ee94 468 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 469
470 return fault->nested_page_fault;
d4f8cf66
JR		 471}
472
3419ffc8
SY		 473void kvm_inject_nmi(struct kvm_vcpu *vcpu)
474{
7460fb4a
AK		 475 atomic_inc(&vcpu->arch.nmi_queued);
476 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 477}
478EXPORT_SYMBOL_GPL(kvm_inject_nmi);
479
298101da
AK		 480void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
481{
ce7ddec4 482 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 483}
484EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
485
ce7ddec4
JR		 486void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
487{
488 kvm_multiple_exception(vcpu, nr, true, error_code, true);
489}
490EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
491
0a79b009
AK		 492/*
493 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
494 * a #GP and return false.
495 */
496bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 497{
0a79b009
AK		 498 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
499 return true;
500 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
501 return false;
298101da 502}
0a79b009 503EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 504
16f8a6f9
NA		 505bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
506{
507 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
508 return true;
509
510 kvm_queue_exception(vcpu, UD_VECTOR);
511 return false;
512}
513EXPORT_SYMBOL_GPL(kvm_require_dr);
514
ec92fe44
JR		 515/*
516 * This function will be used to read from the physical memory of the currently
54bf36aa 517 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 518 * can read from guest physical or from the guest's guest physical memory.
519 */
520int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
521 gfn_t ngfn, void *data, int offset, int len,
522 u32 access)
523{
54987b7a 524 struct x86_exception exception;
ec92fe44
JR		 525 gfn_t real_gfn;
526 gpa_t ngpa;
527
528 ngpa = gfn_to_gpa(ngfn);
54987b7a 529 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 530 if (real_gfn == UNMAPPED_GVA)
531 return -EFAULT;
532
533 real_gfn = gpa_to_gfn(real_gfn);
534
54bf36aa 535 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 536}
537EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
538
69b0049a 539static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 540 void *data, int offset, int len, u32 access)
541{
542 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
543 data, offset, len, access);
544}
545
a03490ed
CO		 546/*
547 * Load the pae pdptrs. Return true is they are all valid.
548 */
ff03a073 549int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 550{
551 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
552 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
553 int i;
554 int ret;
ff03a073 555 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 556
ff03a073
JR		 557 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
558 offset * sizeof(u64), sizeof(pdpte),
559 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 560 if (ret < 0) {
561 ret = 0;
562 goto out;
563 }
564 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 565 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 566 (pdpte[i] &
567 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 568 ret = 0;
569 goto out;
570 }
571 }
572 ret = 1;
573
ff03a073 574 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 575 __set_bit(VCPU_EXREG_PDPTR,
576 (unsigned long *)&vcpu->arch.regs_avail);
577 __set_bit(VCPU_EXREG_PDPTR,
578 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 579out:
a03490ed
CO		 580
581 return ret;
582}
cc4b6871 583EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 584
9ed38ffa 585bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 586{
ff03a073 587 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 588 bool changed = true;
3d06b8bf
JR		 589 int offset;
590 gfn_t gfn;
d835dfec
AK		 591 int r;
592
593 if (is_long_mode(vcpu) || !is_pae(vcpu))
594 return false;
595
6de4f3ad
AK		 596 if (!test_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_avail))
598 return true;
599
a512177e
PB		 600 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
601 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 602 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
603 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 604 if (r < 0)
605 goto out;
ff03a073 606 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 607out:
d835dfec
AK		 608
609 return changed;
610}
9ed38ffa 611EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 612
49a9b07e 613int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 614{
aad82703 615 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 616 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 617
f9a48e6a
AK		 618 cr0 |= X86_CR0_ET;
619
ab344828 620#ifdef CONFIG_X86_64
0f12244f
GN		 621 if (cr0 & 0xffffffff00000000UL)
622 return 1;
ab344828
GN		 623#endif
624
625 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
628 return 1;
a03490ed 629
0f12244f
GN		 630 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
631 return 1;
a03490ed
CO		 632
633 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
634#ifdef CONFIG_X86_64
f6801dff 635 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 636 int cs_db, cs_l;
637
0f12244f
GN		 638 if (!is_pae(vcpu))
639 return 1;
a03490ed 640 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 641 if (cs_l)
642 return 1;
a03490ed
CO		 643 } else
644#endif
ff03a073 645 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 646 kvm_read_cr3(vcpu)))
0f12244f 647 return 1;
a03490ed
CO		 648 }
649
ad756a16
MJ		 650 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
651 return 1;
652
a03490ed 653 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 654
d170c419 655 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 656 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 657 kvm_async_pf_hash_reset(vcpu);
658 }
e5f3f027 659
aad82703
SY		 660 if ((cr0 ^ old_cr0) & update_bits)
661 kvm_mmu_reset_context(vcpu);
b18d5431 662
879ae188
LE		 663 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
664 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
665 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 666 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
667
0f12244f
GN		 668 return 0;
669}
2d3ad1f4 670EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 671
2d3ad1f4 672void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 673{
49a9b07e 674 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 677
42bdf991
MT		 678static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
679{
680 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
681 !vcpu->guest_xcr0_loaded) {
682 /* kvm_set_xcr() also depends on this */
683 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
684 vcpu->guest_xcr0_loaded = 1;
685 }
686}
687
688static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
689{
690 if (vcpu->guest_xcr0_loaded) {
691 if (vcpu->arch.xcr0 != host_xcr0)
692 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
693 vcpu->guest_xcr0_loaded = 0;
694 }
695}
696
69b0049a 697static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 698{
56c103ec
LJ		 699 u64 xcr0 = xcr;
700 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 701 u64 valid_bits;
2acf923e
DC		 702
703 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
704 if (index != XCR_XFEATURE_ENABLED_MASK)
705 return 1;
d91cab78 706 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 709 return 1;
46c34cb0
PB		 710
711 /*
712 * Do not allow the guest to set bits that we do not support
713 * saving. However, xcr0 bit 0 is always set, even if the
714 * emulated CPU does not support XSAVE (see fx_init).
715 */
d91cab78 716 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 717 if (xcr0 & ~valid_bits)
2acf923e 718 return 1;
46c34cb0 719
d91cab78
DH		 720 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
721 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 722 return 1;
723
d91cab78
DH		 724 if (xcr0 & XFEATURE_MASK_AVX512) {
725 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 728 return 1;
729 }
2acf923e 730 vcpu->arch.xcr0 = xcr0;
56c103ec 731
d91cab78 732 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 733 kvm_update_cpuid(vcpu);
2acf923e
DC		 734 return 0;
735}
736
737int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
738{
764bcbc5
Z		 739 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
740 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 741 kvm_inject_gp(vcpu, 0);
742 return 1;
743 }
744 return 0;
745}
746EXPORT_SYMBOL_GPL(kvm_set_xcr);
747
a83b29c6 748int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 749{
fc78f519 750 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 751 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 752 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 753
0f12244f
GN		 754 if (cr4 & CR4_RESERVED_BITS)
755 return 1;
a03490ed 756
2acf923e
DC		 757 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
758 return 1;
759
c68b734f
YW		 760 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
761 return 1;
762
97ec8c06
FW		 763 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
764 return 1;
765
afcbf13f 766 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 767 return 1;
768
b9baba86
HH		 769 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
770 return 1;
771
a03490ed 772 if (is_long_mode(vcpu)) {
0f12244f
GN		 773 if (!(cr4 & X86_CR4_PAE))
774 return 1;
a2edf57f
AK		 775 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
776 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 777 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
778 kvm_read_cr3(vcpu)))
0f12244f
GN		 779 return 1;
780
ad756a16
MJ		 781 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
782 if (!guest_cpuid_has_pcid(vcpu))
783 return 1;
784
785 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
786 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
787 return 1;
788 }
789
5e1746d6 790 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 791 return 1;
a03490ed 792
ad756a16
MJ		 793 if (((cr4 ^ old_cr4) & pdptr_bits) ||
794 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 795 kvm_mmu_reset_context(vcpu);
0f12244f 796
b9baba86 797 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 798 kvm_update_cpuid(vcpu);
2acf923e 799
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 803
2390218b 804int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 805{
ac146235 806#ifdef CONFIG_X86_64
9d88fca7 807 cr3 &= ~CR3_PCID_INVD;
ac146235 808#endif
9d88fca7 809
9f8fe504 810 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 811 kvm_mmu_sync_roots(vcpu);
77c3913b 812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 813 return 0;
d835dfec
AK		 814 }
815
a03490ed 816 if (is_long_mode(vcpu)) {
d9f89b88
JK		 817 if (cr3 & CR3_L_MODE_RESERVED_BITS)
818 return 1;
819 } else if (is_pae(vcpu) && is_paging(vcpu) &&
820 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 821 return 1;
a03490ed 822
0f12244f 823 vcpu->arch.cr3 = cr3;
aff48baa 824 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 825 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 826 return 0;
827}
2d3ad1f4 828EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 829
eea1cff9 830int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 831{
0f12244f
GN		 832 if (cr8 & CR8_RESERVED_BITS)
833 return 1;
35754c98 834 if (lapic_in_kernel(vcpu))
a03490ed
CO		 835 kvm_lapic_set_tpr(vcpu, cr8);
836 else
ad312c7c 837 vcpu->arch.cr8 = cr8;
0f12244f
GN		 838 return 0;
839}
2d3ad1f4 840EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 841
2d3ad1f4 842unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 843{
35754c98 844 if (lapic_in_kernel(vcpu))
a03490ed
CO		 845 return kvm_lapic_get_cr8(vcpu);
846 else
ad312c7c 847 return vcpu->arch.cr8;
a03490ed 848}
2d3ad1f4 849EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 850
ae561ede
NA		 851static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
852{
853 int i;
854
855 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
856 for (i = 0; i < KVM_NR_DB_REGS; i++)
857 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
858 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
859 }
860}
861
73aaf249
JK		 862static void kvm_update_dr6(struct kvm_vcpu *vcpu)
863{
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
866}
867
c8639010
JK		 868static void kvm_update_dr7(struct kvm_vcpu *vcpu)
869{
870 unsigned long dr7;
871
872 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
873 dr7 = vcpu->arch.guest_debug_dr7;
874 else
875 dr7 = vcpu->arch.dr7;
876 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 877 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
878 if (dr7 & DR7_BP_EN_MASK)
879 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 880}
881
6f43ed01
NA		 882static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
883{
884 u64 fixed = DR6_FIXED_1;
885
886 if (!guest_cpuid_has_rtm(vcpu))
887 fixed |= DR6_RTM;
888 return fixed;
889}
890
338dbc97 891static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 892{
893 switch (dr) {
894 case 0 ... 3:
895 vcpu->arch.db[dr] = val;
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 vcpu->arch.eff_db[dr] = val;
898 break;
899 case 4:
020df079
GN		 900 /* fall through */
901 case 6:
338dbc97
GN		 902 if (val & 0xffffffff00000000ULL)
903 return -1; /* #GP */
6f43ed01 904 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 905 kvm_update_dr6(vcpu);
020df079
GN		 906 break;
907 case 5:
020df079
GN		 908 /* fall through */
909 default: /* 7 */
338dbc97
GN		 910 if (val & 0xffffffff00000000ULL)
911 return -1; /* #GP */
020df079 912 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 913 kvm_update_dr7(vcpu);
020df079
GN		 914 break;
915 }
916
917 return 0;
918}
338dbc97
GN		 919
920int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
921{
16f8a6f9 922 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 923 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 924 return 1;
925 }
926 return 0;
338dbc97 927}
020df079
GN		 928EXPORT_SYMBOL_GPL(kvm_set_dr);
929
16f8a6f9 930int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 931{
932 switch (dr) {
933 case 0 ... 3:
934 *val = vcpu->arch.db[dr];
935 break;
936 case 4:
020df079
GN		 937 /* fall through */
938 case 6:
73aaf249
JK		 939 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
940 *val = vcpu->arch.dr6;
941 else
942 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 943 break;
944 case 5:
020df079
GN		 945 /* fall through */
946 default: /* 7 */
947 *val = vcpu->arch.dr7;
948 break;
949 }
338dbc97
GN		 950 return 0;
951}
020df079
GN		 952EXPORT_SYMBOL_GPL(kvm_get_dr);
953
022cd0e8
AK		 954bool kvm_rdpmc(struct kvm_vcpu *vcpu)
955{
956 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
957 u64 data;
958 int err;
959
c6702c9d 960 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 961 if (err)
962 return err;
963 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
964 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
965 return err;
966}
967EXPORT_SYMBOL_GPL(kvm_rdpmc);
968
043405e1
CO		 969/*
970 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
971 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
972 *
973 * This list is modified at module load time to reflect the
e3267cbb 974 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 975 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
976 * may depend on host virtualization features rather than host cpu features.
043405e1 977 */
e3267cbb 978
043405e1
CO		 979static u32 msrs_to_save[] = {
980 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 981 MSR_STAR,
043405e1
CO		 982#ifdef CONFIG_X86_64
983 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
984#endif
b3897a49 985 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 986 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 987};
988
989static unsigned num_msrs_to_save;
990
62ef68bb
PB		 991static u32 emulated_msrs[] = {
992 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
993 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
994 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
995 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 996 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
997 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 998 HV_X64_MSR_RESET,
11c4b1ca 999 HV_X64_MSR_VP_INDEX,
9eec50b8 1000 HV_X64_MSR_VP_RUNTIME,
5c919412 1001 HV_X64_MSR_SCONTROL,
1f4b34f8 1002 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1003 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1004 MSR_KVM_PV_EOI_EN,
1005
ba904635 1006 MSR_IA32_TSC_ADJUST,
a3e06bbe 1007 MSR_IA32_TSCDEADLINE,
043405e1 1008 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1009 MSR_IA32_MCG_STATUS,
1010 MSR_IA32_MCG_CTL,
c45dcc71 1011 MSR_IA32_MCG_EXT_CTL,
64d60670 1012 MSR_IA32_SMBASE,
db2336a8
KH		 1013 MSR_PLATFORM_INFO,
1014 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1015};
1016
62ef68bb
PB		 1017static unsigned num_emulated_msrs;
1018
384bb783 1019bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1020{
b69e8cae 1021 if (efer & efer_reserved_bits)
384bb783 1022 return false;
15c4a640 1023
1b2fd70c
AG		 1024 if (efer & EFER_FFXSR) {
1025 struct kvm_cpuid_entry2 *feat;
1026
1027 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1028 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1029 return false;
1b2fd70c
AG		 1030 }
1031
d8017474
AG		 1032 if (efer & EFER_SVME) {
1033 struct kvm_cpuid_entry2 *feat;
1034
1035 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1036 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1037 return false;
d8017474
AG		 1038 }
1039
384bb783
JK		 1040 return true;
1041}
1042EXPORT_SYMBOL_GPL(kvm_valid_efer);
1043
1044static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1045{
1046 u64 old_efer = vcpu->arch.efer;
1047
1048 if (!kvm_valid_efer(vcpu, efer))
1049 return 1;
1050
1051 if (is_paging(vcpu)
1052 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1053 return 1;
1054
15c4a640 1055 efer &= ~EFER_LMA;
f6801dff 1056 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1057
a3d204e2
SY		 1058 kvm_x86_ops->set_efer(vcpu, efer);
1059
aad82703
SY		 1060 /* Update reserved bits */
1061 if ((efer ^ old_efer) & EFER_NX)
1062 kvm_mmu_reset_context(vcpu);
1063
b69e8cae 1064 return 0;
15c4a640
CO		 1065}
1066
f2b4b7dd
JR		 1067void kvm_enable_efer_bits(u64 mask)
1068{
1069 efer_reserved_bits &= ~mask;
1070}
1071EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1072
15c4a640
CO		 1073/*
1074 * Writes msr value into into the appropriate "register".
1075 * Returns 0 on success, non-0 otherwise.
1076 * Assumes vcpu_load() was already called.
1077 */
8fe8ab46 1078int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1079{
854e8bb1
NA		 1080 switch (msr->index) {
1081 case MSR_FS_BASE:
1082 case MSR_GS_BASE:
1083 case MSR_KERNEL_GS_BASE:
1084 case MSR_CSTAR:
1085 case MSR_LSTAR:
1086 if (is_noncanonical_address(msr->data))
1087 return 1;
1088 break;
1089 case MSR_IA32_SYSENTER_EIP:
1090 case MSR_IA32_SYSENTER_ESP:
1091 /*
1092 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1093 * non-canonical address is written on Intel but not on
1094 * AMD (which ignores the top 32-bits, because it does
1095 * not implement 64-bit SYSENTER).
1096 *
1097 * 64-bit code should hence be able to write a non-canonical
1098 * value on AMD. Making the address canonical ensures that
1099 * vmentry does not fail on Intel after writing a non-canonical
1100 * value, and that something deterministic happens if the guest
1101 * invokes 64-bit SYSENTER.
1102 */
1103 msr->data = get_canonical(msr->data);
1104 }
8fe8ab46 1105 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1106}
854e8bb1 1107EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1108
313a3dc7
CO		 1109/*
1110 * Adapt set_msr() to msr_io()'s calling convention
1111 */
609e36d3
PB		 1112static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1113{
1114 struct msr_data msr;
1115 int r;
1116
1117 msr.index = index;
1118 msr.host_initiated = true;
1119 r = kvm_get_msr(vcpu, &msr);
1120 if (r)
1121 return r;
1122
1123 *data = msr.data;
1124 return 0;
1125}
1126
313a3dc7
CO		 1127static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1128{
8fe8ab46
WA		 1129 struct msr_data msr;
1130
1131 msr.data = *data;
1132 msr.index = index;
1133 msr.host_initiated = true;
1134 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1135}
1136
16e8d74d
MT		 1137#ifdef CONFIG_X86_64
1138struct pvclock_gtod_data {
1139 seqcount_t seq;
1140
1141 struct { /* extract of a clocksource struct */
1142 int vclock_mode;
a5a1d1c2
TG		 1143 u64 cycle_last;
1144 u64 mask;
16e8d74d
MT		 1145 u32 mult;
1146 u32 shift;
1147 } clock;
1148
cbcf2dd3
TG		 1149 u64 boot_ns;
1150 u64 nsec_base;
55dd00a7 1151 u64 wall_time_sec;
16e8d74d
MT		 1152};
1153
1154static struct pvclock_gtod_data pvclock_gtod_data;
1155
1156static void update_pvclock_gtod(struct timekeeper *tk)
1157{
1158 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1159 u64 boot_ns;
1160
876e7881 1161 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1162
1163 write_seqcount_begin(&vdata->seq);
1164
1165 /* copy pvclock gtod data */
876e7881
PZ		 1166 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1167 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1168 vdata->clock.mask = tk->tkr_mono.mask;
1169 vdata->clock.mult = tk->tkr_mono.mult;
1170 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1171
cbcf2dd3 1172 vdata->boot_ns = boot_ns;
876e7881 1173 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1174
55dd00a7
MT		 1175 vdata->wall_time_sec = tk->xtime_sec;
1176
16e8d74d
MT		 1177 write_seqcount_end(&vdata->seq);
1178}
1179#endif
1180
bab5bb39
NK		 1181void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1182{
1183 /*
1184 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1185 * vcpu_enter_guest. This function is only called from
1186 * the physical CPU that is running vcpu.
1187 */
1188 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1189}
16e8d74d 1190
18068523
GOC		 1191static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1192{
9ed3c444
AK		 1193 int version;
1194 int r;
50d0a0f9 1195 struct pvclock_wall_clock wc;
87aeb54f 1196 struct timespec64 boot;
18068523
GOC		 1197
1198 if (!wall_clock)
1199 return;
1200
9ed3c444
AK		 1201 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1202 if (r)
1203 return;
1204
1205 if (version & 1)
1206 ++version; /* first time write, random junk */
1207
1208 ++version;
18068523 1209
1dab1345
NK		 1210 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1211 return;
18068523 1212
50d0a0f9
GH		 1213 /*
1214 * The guest calculates current wall clock time by adding
34c238a1 1215 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1216 * wall clock specified here. guest system time equals host
1217 * system time for us, thus we must fill in host boot time here.
1218 */
87aeb54f 1219 getboottime64(&boot);
50d0a0f9 1220
4b648665 1221 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1222 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1223 boot = timespec64_sub(boot, ts);
4b648665 1224 }
87aeb54f 1225 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1226 wc.nsec = boot.tv_nsec;
1227 wc.version = version;
18068523
GOC		 1228
1229 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1230
1231 version++;
1232 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1233}
1234
50d0a0f9
GH		 1235static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1236{
b51012de
PB		 1237 do_shl32_div32(dividend, divisor);
1238 return dividend;
50d0a0f9
GH		 1239}
1240
3ae13faa 1241static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1242 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1243{
5f4e3f88 1244 uint64_t scaled64;
50d0a0f9
GH		 1245 int32_t shift = 0;
1246 uint64_t tps64;
1247 uint32_t tps32;
1248
3ae13faa
PB		 1249 tps64 = base_hz;
1250 scaled64 = scaled_hz;
50933623 1251 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1252 tps64 >>= 1;
1253 shift--;
1254 }
1255
1256 tps32 = (uint32_t)tps64;
50933623
JK		 1257 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1258 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1259 scaled64 >>= 1;
1260 else
1261 tps32 <<= 1;
50d0a0f9
GH		 1262 shift++;
1263 }
1264
5f4e3f88
ZA		 1265 *pshift = shift;
1266 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1267
3ae13faa
PB		 1268 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1269 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1270}
1271
d828199e 1272#ifdef CONFIG_X86_64
16e8d74d 1273static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1274#endif
16e8d74d 1275
c8076604 1276static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1277static unsigned long max_tsc_khz;
c8076604 1278
cc578287 1279static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1280{
cc578287
ZA		 1281 u64 v = (u64)khz * (1000000 + ppm);
1282 do_div(v, 1000000);
1283 return v;
1e993611
JR		 1284}
1285
381d585c
HZ		 1286static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1287{
1288 u64 ratio;
1289
1290 /* Guest TSC same frequency as host TSC? */
1291 if (!scale) {
1292 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1293 return 0;
1294 }
1295
1296 /* TSC scaling supported? */
1297 if (!kvm_has_tsc_control) {
1298 if (user_tsc_khz > tsc_khz) {
1299 vcpu->arch.tsc_catchup = 1;
1300 vcpu->arch.tsc_always_catchup = 1;
1301 return 0;
1302 } else {
1303 WARN(1, "user requested TSC rate below hardware speed\n");
1304 return -1;
1305 }
1306 }
1307
1308 /* TSC scaling required - calculate ratio */
1309 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1310 user_tsc_khz, tsc_khz);
1311
1312 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1313 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1314 user_tsc_khz);
1315 return -1;
1316 }
1317
1318 vcpu->arch.tsc_scaling_ratio = ratio;
1319 return 0;
1320}
1321
4941b8cb 1322static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1323{
cc578287
ZA		 1324 u32 thresh_lo, thresh_hi;
1325 int use_scaling = 0;
217fc9cf 1326
03ba32ca 1327 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1328 if (user_tsc_khz == 0) {
ad721883
HZ		 1329 /* set tsc_scaling_ratio to a safe value */
1330 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1331 return -1;
ad721883 1332 }
03ba32ca 1333
c285545f 1334 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1335 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1336 &vcpu->arch.virtual_tsc_shift,
1337 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1338 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1339
1340 /*
1341 * Compute the variation in TSC rate which is acceptable
1342 * within the range of tolerance and decide if the
1343 * rate being applied is within that bounds of the hardware
1344 * rate. If so, no scaling or compensation need be done.
1345 */
1346 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1347 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1348 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1349 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1350 use_scaling = 1;
1351 }
4941b8cb 1352 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1353}
1354
1355static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1356{
e26101b1 1357 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1358 vcpu->arch.virtual_tsc_mult,
1359 vcpu->arch.virtual_tsc_shift);
e26101b1 1360 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1361 return tsc;
1362}
1363
69b0049a 1364static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1365{
1366#ifdef CONFIG_X86_64
1367 bool vcpus_matched;
b48aa97e
MT		 1368 struct kvm_arch *ka = &vcpu->kvm->arch;
1369 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1370
1371 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1372 atomic_read(&vcpu->kvm->online_vcpus));
1373
7f187922
MT		 1374 /*
1375 * Once the masterclock is enabled, always perform request in
1376 * order to update it.
1377 *
1378 * In order to enable masterclock, the host clocksource must be TSC
1379 * and the vcpus need to have matched TSCs. When that happens,
1380 * perform request to enable masterclock.
1381 */
1382 if (ka->use_master_clock ||
1383 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1384 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1385
1386 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1387 atomic_read(&vcpu->kvm->online_vcpus),
1388 ka->use_master_clock, gtod->clock.vclock_mode);
1389#endif
1390}
1391
ba904635
WA		 1392static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1393{
3e3f5026 1394 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1395 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1396}
1397
35181e86
HZ		 1398/*
1399 * Multiply tsc by a fixed point number represented by ratio.
1400 *
1401 * The most significant 64-N bits (mult) of ratio represent the
1402 * integral part of the fixed point number; the remaining N bits
1403 * (frac) represent the fractional part, ie. ratio represents a fixed
1404 * point number (mult + frac * 2^(-N)).
1405 *
1406 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1407 */
1408static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1409{
1410 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1411}
1412
1413u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1414{
1415 u64 _tsc = tsc;
1416 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1417
1418 if (ratio != kvm_default_tsc_scaling_ratio)
1419 _tsc = __scale_tsc(ratio, tsc);
1420
1421 return _tsc;
1422}
1423EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1424
07c1419a
HZ		 1425static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1426{
1427 u64 tsc;
1428
1429 tsc = kvm_scale_tsc(vcpu, rdtsc());
1430
1431 return target_tsc - tsc;
1432}
1433
4ba76538
HZ		 1434u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1435{
ea26e4ec 1436 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1437}
1438EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1439
a545ab6a
LC		 1440static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1441{
1442 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1443 vcpu->arch.tsc_offset = offset;
1444}
1445
8fe8ab46 1446void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1447{
1448 struct kvm *kvm = vcpu->kvm;
f38e098f 1449 u64 offset, ns, elapsed;
99e3e30a 1450 unsigned long flags;
b48aa97e 1451 bool matched;
0d3da0d2 1452 bool already_matched;
8fe8ab46 1453 u64 data = msr->data;
c5e8ec8e 1454 bool synchronizing = false;
99e3e30a 1455
038f8c11 1456 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1457 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1458 ns = ktime_get_boot_ns();
f38e098f 1459 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1460
03ba32ca 1461 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1462 if (data == 0 && msr->host_initiated) {
1463 /*
1464 * detection of vcpu initialization -- need to sync
1465 * with other vCPUs. This particularly helps to keep
1466 * kvm_clock stable after CPU hotplug
1467 */
1468 synchronizing = true;
1469 } else {
1470 u64 tsc_exp = kvm->arch.last_tsc_write +
1471 nsec_to_cycles(vcpu, elapsed);
1472 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1473 /*
1474 * Special case: TSC write with a small delta (1 second)
1475 * of virtual cycle time against real time is
1476 * interpreted as an attempt to synchronize the CPU.
1477 */
1478 synchronizing = data < tsc_exp + tsc_hz &&
1479 data + tsc_hz > tsc_exp;
1480 }
c5e8ec8e 1481 }
f38e098f
ZA		 1482
1483 /*
5d3cb0f6
ZA		 1484 * For a reliable TSC, we can match TSC offsets, and for an unstable
1485 * TSC, we add elapsed time in this computation. We could let the
1486 * compensation code attempt to catch up if we fall behind, but
1487 * it's better to try to match offsets from the beginning.
1488 */
c5e8ec8e 1489 if (synchronizing &&
5d3cb0f6 1490 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1491 if (!check_tsc_unstable()) {
e26101b1 1492 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1493 pr_debug("kvm: matched tsc offset for %llu\n", data);
1494 } else {
857e4099 1495 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1496 data += delta;
07c1419a 1497 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1498 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1499 }
b48aa97e 1500 matched = true;
0d3da0d2 1501 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1502 } else {
1503 /*
1504 * We split periods of matched TSC writes into generations.
1505 * For each generation, we track the original measured
1506 * nanosecond time, offset, and write, so if TSCs are in
1507 * sync, we can match exact offset, and if not, we can match
4a969980 1508 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1509 *
1510 * These values are tracked in kvm->arch.cur_xxx variables.
1511 */
1512 kvm->arch.cur_tsc_generation++;
1513 kvm->arch.cur_tsc_nsec = ns;
1514 kvm->arch.cur_tsc_write = data;
1515 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1516 matched = false;
0d3da0d2 1517 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1518 kvm->arch.cur_tsc_generation, data);
f38e098f 1519 }
e26101b1
ZA		 1520
1521 /*
1522 * We also track th most recent recorded KHZ, write and time to
1523 * allow the matching interval to be extended at each write.
1524 */
f38e098f
ZA		 1525 kvm->arch.last_tsc_nsec = ns;
1526 kvm->arch.last_tsc_write = data;
5d3cb0f6 1527 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1528
b183aa58 1529 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1530
1531 /* Keep track of which generation this VCPU has synchronized to */
1532 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1533 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1534 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1535
ba904635
WA		 1536 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1537 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1538 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1539 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1540
1541 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1542 if (!matched) {
b48aa97e 1543 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1544 } else if (!already_matched) {
1545 kvm->arch.nr_vcpus_matched_tsc++;
1546 }
b48aa97e
MT		 1547
1548 kvm_track_tsc_matching(vcpu);
1549 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1550}
e26101b1 1551
99e3e30a
ZA		 1552EXPORT_SYMBOL_GPL(kvm_write_tsc);
1553
58ea6767
HZ		 1554static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1555 s64 adjustment)
1556{
ea26e4ec 1557 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1558}
1559
1560static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1561{
1562 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1563 WARN_ON(adjustment < 0);
1564 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1565 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1566}
1567
d828199e
MT		 1568#ifdef CONFIG_X86_64
1569
a5a1d1c2 1570static u64 read_tsc(void)
d828199e 1571{
a5a1d1c2 1572 u64 ret = (u64)rdtsc_ordered();
03b9730b 1573 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1574
1575 if (likely(ret >= last))
1576 return ret;
1577
1578 /*
1579 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1580 * predictable (it's just a function of time and the likely is
d828199e
MT		 1581 * very likely) and there's a data dependence, so force GCC
1582 * to generate a branch instead. I don't barrier() because
1583 * we don't actually need a barrier, and if this function
1584 * ever gets inlined it will generate worse code.
1585 */
1586 asm volatile ("");
1587 return last;
1588}
1589
a5a1d1c2 1590static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1591{
1592 long v;
1593 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1594
1595 *cycle_now = read_tsc();
1596
1597 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1598 return v * gtod->clock.mult;
1599}
1600
a5a1d1c2 1601static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1602{
cbcf2dd3 1603 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1604 unsigned long seq;
d828199e 1605 int mode;
cbcf2dd3 1606 u64 ns;
d828199e 1607
d828199e
MT		 1608 do {
1609 seq = read_seqcount_begin(&gtod->seq);
1610 mode = gtod->clock.vclock_mode;
cbcf2dd3 1611 ns = gtod->nsec_base;
d828199e
MT		 1612 ns += vgettsc(cycle_now);
1613 ns >>= gtod->clock.shift;
cbcf2dd3 1614 ns += gtod->boot_ns;
d828199e 1615 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1616 *t = ns;
d828199e
MT		 1617
1618 return mode;
1619}
1620
55dd00a7
MT		 1621static int do_realtime(struct timespec *ts, u64 *cycle_now)
1622{
1623 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1624 unsigned long seq;
1625 int mode;
1626 u64 ns;
1627
1628 do {
1629 seq = read_seqcount_begin(&gtod->seq);
1630 mode = gtod->clock.vclock_mode;
1631 ts->tv_sec = gtod->wall_time_sec;
1632 ns = gtod->nsec_base;
1633 ns += vgettsc(cycle_now);
1634 ns >>= gtod->clock.shift;
1635 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1636
1637 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1638 ts->tv_nsec = ns;
1639
1640 return mode;
1641}
1642
d828199e 1643/* returns true if host is using tsc clocksource */
a5a1d1c2 1644static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1645{
d828199e
MT		 1646 /* checked again under seqlock below */
1647 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1648 return false;
1649
cbcf2dd3 1650 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1651}
55dd00a7
MT		 1652
1653/* returns true if host is using tsc clocksource */
1654static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1655 u64 *cycle_now)
1656{
1657 /* checked again under seqlock below */
1658 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1659 return false;
1660
1661 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1662}
d828199e
MT		 1663#endif
1664
1665/*
1666 *
b48aa97e
MT		 1667 * Assuming a stable TSC across physical CPUS, and a stable TSC
1668 * across virtual CPUs, the following condition is possible.
1669 * Each numbered line represents an event visible to both
d828199e
MT		 1670 * CPUs at the next numbered event.
1671 *
1672 * "timespecX" represents host monotonic time. "tscX" represents
1673 * RDTSC value.
1674 *
1675 * VCPU0 on CPU0 | VCPU1 on CPU1
1676 *
1677 * 1. read timespec0,tsc0
1678 * 2. | timespec1 = timespec0 + N
1679 * | tsc1 = tsc0 + M
1680 * 3. transition to guest | transition to guest
1681 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1682 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1683 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1684 *
1685 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1686 *
1687 * - ret0 < ret1
1688 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1689 * ...
1690 * - 0 < N - M => M < N
1691 *
1692 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1693 * always the case (the difference between two distinct xtime instances
1694 * might be smaller then the difference between corresponding TSC reads,
1695 * when updating guest vcpus pvclock areas).
1696 *
1697 * To avoid that problem, do not allow visibility of distinct
1698 * system_timestamp/tsc_timestamp values simultaneously: use a master
1699 * copy of host monotonic time values. Update that master copy
1700 * in lockstep.
1701 *
b48aa97e 1702 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1703 *
1704 */
1705
1706static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1707{
1708#ifdef CONFIG_X86_64
1709 struct kvm_arch *ka = &kvm->arch;
1710 int vclock_mode;
b48aa97e
MT		 1711 bool host_tsc_clocksource, vcpus_matched;
1712
1713 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1714 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1715
1716 /*
1717 * If the host uses TSC clock, then passthrough TSC as stable
1718 * to the guest.
1719 */
b48aa97e 1720 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1721 &ka->master_kernel_ns,
1722 &ka->master_cycle_now);
1723
16a96021 1724 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1725 && !ka->backwards_tsc_observed
54750f2c 1726 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1727
d828199e
MT		 1728 if (ka->use_master_clock)
1729 atomic_set(&kvm_guest_has_master_clock, 1);
1730
1731 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1732 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1733 vcpus_matched);
d828199e
MT		 1734#endif
1735}
1736
2860c4b1
PB		 1737void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1738{
1739 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1740}
1741
2e762ff7
MT		 1742static void kvm_gen_update_masterclock(struct kvm *kvm)
1743{
1744#ifdef CONFIG_X86_64
1745 int i;
1746 struct kvm_vcpu *vcpu;
1747 struct kvm_arch *ka = &kvm->arch;
1748
1749 spin_lock(&ka->pvclock_gtod_sync_lock);
1750 kvm_make_mclock_inprogress_request(kvm);
1751 /* no guest entries from this point */
1752 pvclock_update_vm_gtod_copy(kvm);
1753
1754 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1755 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1756
1757 /* guest entries allowed */
1758 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1759 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1760
1761 spin_unlock(&ka->pvclock_gtod_sync_lock);
1762#endif
1763}
1764
e891a32e 1765u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1766{
108b249c 1767 struct kvm_arch *ka = &kvm->arch;
8b953440 1768 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1769 u64 ret;
108b249c 1770
8b953440
PB		 1771 spin_lock(&ka->pvclock_gtod_sync_lock);
1772 if (!ka->use_master_clock) {
1773 spin_unlock(&ka->pvclock_gtod_sync_lock);
1774 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1775 }
1776
8b953440
PB		 1777 hv_clock.tsc_timestamp = ka->master_cycle_now;
1778 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1779 spin_unlock(&ka->pvclock_gtod_sync_lock);
1780
e2c2206a
WL		 1781 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1782 get_cpu();
1783
8b953440
PB		 1784 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1785 &hv_clock.tsc_shift,
1786 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1787 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1788
1789 put_cpu();
1790
1791 return ret;
108b249c
PB		 1792}
1793
0d6dd2ff
PB		 1794static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1795{
1796 struct kvm_vcpu_arch *vcpu = &v->arch;
1797 struct pvclock_vcpu_time_info guest_hv_clock;
1798
4e335d9e 1799 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1800 &guest_hv_clock, sizeof(guest_hv_clock))))
1801 return;
1802
1803 /* This VCPU is paused, but it's legal for a guest to read another
1804 * VCPU's kvmclock, so we really have to follow the specification where
1805 * it says that version is odd if data is being modified, and even after
1806 * it is consistent.
1807 *
1808 * Version field updates must be kept separate. This is because
1809 * kvm_write_guest_cached might use a "rep movs" instruction, and
1810 * writes within a string instruction are weakly ordered. So there
1811 * are three writes overall.
1812 *
1813 * As a small optimization, only write the version field in the first
1814 * and third write. The vcpu->pv_time cache is still valid, because the
1815 * version field is the first in the struct.
1816 */
1817 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1818
1819 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1820 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1821 &vcpu->hv_clock,
1822 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1823
1824 smp_wmb();
1825
1826 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1827 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1828
1829 if (vcpu->pvclock_set_guest_stopped_request) {
1830 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1831 vcpu->pvclock_set_guest_stopped_request = false;
1832 }
1833
1834 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1835
4e335d9e
PB		 1836 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1837 &vcpu->hv_clock,
1838 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1839
1840 smp_wmb();
1841
1842 vcpu->hv_clock.version++;
4e335d9e
PB		 1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1844 &vcpu->hv_clock,
1845 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1846}
1847
34c238a1 1848static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1849{
78db6a50 1850 unsigned long flags, tgt_tsc_khz;
18068523 1851 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1852 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1853 s64 kernel_ns;
d828199e 1854 u64 tsc_timestamp, host_tsc;
51d59c6b 1855 u8 pvclock_flags;
d828199e
MT		 1856 bool use_master_clock;
1857
1858 kernel_ns = 0;
1859 host_tsc = 0;
18068523 1860
d828199e
MT		 1861 /*
1862 * If the host uses TSC clock, then passthrough TSC as stable
1863 * to the guest.
1864 */
1865 spin_lock(&ka->pvclock_gtod_sync_lock);
1866 use_master_clock = ka->use_master_clock;
1867 if (use_master_clock) {
1868 host_tsc = ka->master_cycle_now;
1869 kernel_ns = ka->master_kernel_ns;
1870 }
1871 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1872
1873 /* Keep irq disabled to prevent changes to the clock */
1874 local_irq_save(flags);
78db6a50
PB		 1875 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1876 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1877 local_irq_restore(flags);
1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1879 return 1;
1880 }
d828199e 1881 if (!use_master_clock) {
4ea1636b 1882 host_tsc = rdtsc();
108b249c 1883 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1884 }
1885
4ba76538 1886 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1887
c285545f
ZA		 1888 /*
1889 * We may have to catch up the TSC to match elapsed wall clock
1890 * time for two reasons, even if kvmclock is used.
1891 * 1) CPU could have been running below the maximum TSC rate
1892 * 2) Broken TSC compensation resets the base at each VCPU
1893 * entry to avoid unknown leaps of TSC even when running
1894 * again on the same CPU. This may cause apparent elapsed
1895 * time to disappear, and the guest to stand still or run
1896 * very slowly.
1897 */
1898 if (vcpu->tsc_catchup) {
1899 u64 tsc = compute_guest_tsc(v, kernel_ns);
1900 if (tsc > tsc_timestamp) {
f1e2b260 1901 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1902 tsc_timestamp = tsc;
1903 }
50d0a0f9
GH		 1904 }
1905
18068523
GOC		 1906 local_irq_restore(flags);
1907
0d6dd2ff 1908 /* With all the info we got, fill in the values */
18068523 1909
78db6a50
PB		 1910 if (kvm_has_tsc_control)
1911 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1912
1913 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1914 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1915 &vcpu->hv_clock.tsc_shift,
1916 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1917 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1918 }
1919
1d5f066e 1920 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1921 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1922 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1923
d828199e 1924 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1925 pvclock_flags = 0;
d828199e
MT		 1926 if (use_master_clock)
1927 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1928
78c0337a
MT		 1929 vcpu->hv_clock.flags = pvclock_flags;
1930
095cf55d
PB		 1931 if (vcpu->pv_time_enabled)
1932 kvm_setup_pvclock_page(v);
1933 if (v == kvm_get_vcpu(v->kvm, 0))
1934 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1935 return 0;
c8076604
GH		 1936}
1937
0061d53d
MT		 1938/*
1939 * kvmclock updates which are isolated to a given vcpu, such as
1940 * vcpu->cpu migration, should not allow system_timestamp from
1941 * the rest of the vcpus to remain static. Otherwise ntp frequency
1942 * correction applies to one vcpu's system_timestamp but not
1943 * the others.
1944 *
1945 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1946 * We need to rate-limit these requests though, as they can
1947 * considerably slow guests that have a large number of vcpus.
1948 * The time for a remote vcpu to update its kvmclock is bound
1949 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1950 */
1951
7e44e449
AJ		 1952#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1953
1954static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1955{
1956 int i;
7e44e449
AJ		 1957 struct delayed_work *dwork = to_delayed_work(work);
1958 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1959 kvmclock_update_work);
1960 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1961 struct kvm_vcpu *vcpu;
1962
1963 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1964 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1965 kvm_vcpu_kick(vcpu);
1966 }
1967}
1968
7e44e449
AJ		 1969static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1970{
1971 struct kvm *kvm = v->kvm;
1972
105b21bb 1973 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1974 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1975 KVMCLOCK_UPDATE_DELAY);
1976}
1977
332967a3
AJ		 1978#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1979
1980static void kvmclock_sync_fn(struct work_struct *work)
1981{
1982 struct delayed_work *dwork = to_delayed_work(work);
1983 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1984 kvmclock_sync_work);
1985 struct kvm *kvm = container_of(ka, struct kvm, arch);
1986
630994b3
MT		 1987 if (!kvmclock_periodic_sync)
1988 return;
1989
332967a3
AJ		 1990 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1991 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1992 KVMCLOCK_SYNC_PERIOD);
1993}
1994
890ca9ae 1995static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1996{
890ca9ae
HY		 1997 u64 mcg_cap = vcpu->arch.mcg_cap;
1998 unsigned bank_num = mcg_cap & 0xff;
1999
15c4a640 2000 switch (msr) {
15c4a640 2001 case MSR_IA32_MCG_STATUS:
890ca9ae 2002 vcpu->arch.mcg_status = data;
15c4a640 2003 break;
c7ac679c 2004 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2005 if (!(mcg_cap & MCG_CTL_P))
2006 return 1;
2007 if (data != 0 && data != ~(u64)0)
2008 return -1;
2009 vcpu->arch.mcg_ctl = data;
2010 break;
2011 default:
2012 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2013 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2014 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2015 /* only 0 or all 1s can be written to IA32_MCi_CTL
2016 * some Linux kernels though clear bit 10 in bank 4 to
2017 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2018 * this to avoid an uncatched #GP in the guest
2019 */
890ca9ae 2020 if ((offset & 0x3) == 0 &&
114be429 2021 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2022 return -1;
2023 vcpu->arch.mce_banks[offset] = data;
2024 break;
2025 }
2026 return 1;
2027 }
2028 return 0;
2029}
2030
ffde22ac
ES		 2031static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2032{
2033 struct kvm *kvm = vcpu->kvm;
2034 int lm = is_long_mode(vcpu);
2035 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2036 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2037 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2038 : kvm->arch.xen_hvm_config.blob_size_32;
2039 u32 page_num = data & ~PAGE_MASK;
2040 u64 page_addr = data & PAGE_MASK;
2041 u8 *page;
2042 int r;
2043
2044 r = -E2BIG;
2045 if (page_num >= blob_size)
2046 goto out;
2047 r = -ENOMEM;
ff5c2c03
SL		 2048 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2049 if (IS_ERR(page)) {
2050 r = PTR_ERR(page);
ffde22ac 2051 goto out;
ff5c2c03 2052 }
54bf36aa 2053 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2054 goto out_free;
2055 r = 0;
2056out_free:
2057 kfree(page);
2058out:
2059 return r;
2060}
2061
344d9588
GN		 2062static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2063{
2064 gpa_t gpa = data & ~0x3f;
2065
52a5c155
WL		 2066 /* Bits 3:5 are reserved, Should be zero */
2067 if (data & 0x38)
344d9588
GN		 2068 return 1;
2069
2070 vcpu->arch.apf.msr_val = data;
2071
2072 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2073 kvm_clear_async_pf_completion_queue(vcpu);
2074 kvm_async_pf_hash_reset(vcpu);
2075 return 0;
2076 }
2077
4e335d9e 2078 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2079 sizeof(u32)))
344d9588
GN		 2080 return 1;
2081
6adba527 2082 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2083 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2084 kvm_async_pf_wakeup_all(vcpu);
2085 return 0;
2086}
2087
12f9a48f
GC		 2088static void kvmclock_reset(struct kvm_vcpu *vcpu)
2089{
0b79459b 2090 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2091}
2092
c9aaa895
GC		 2093static void record_steal_time(struct kvm_vcpu *vcpu)
2094{
2095 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2096 return;
2097
4e335d9e 2098 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2099 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2100 return;
2101
0b9f6c46
PX		 2102 vcpu->arch.st.steal.preempted = 0;
2103
35f3fae1
WL		 2104 if (vcpu->arch.st.steal.version & 1)
2105 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2106
2107 vcpu->arch.st.steal.version += 1;
2108
4e335d9e 2109 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2110 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2111
2112 smp_wmb();
2113
c54cdf14
LC		 2114 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2115 vcpu->arch.st.last_steal;
2116 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2117
4e335d9e 2118 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2119 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2120
2121 smp_wmb();
2122
2123 vcpu->arch.st.steal.version += 1;
c9aaa895 2124
4e335d9e 2125 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2126 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2127}
2128
8fe8ab46 2129int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2130{
5753785f 2131 bool pr = false;
8fe8ab46
WA		 2132 u32 msr = msr_info->index;
2133 u64 data = msr_info->data;
5753785f 2134
15c4a640 2135 switch (msr) {
2e32b719
BP		 2136 case MSR_AMD64_NB_CFG:
2137 case MSR_IA32_UCODE_REV:
2138 case MSR_IA32_UCODE_WRITE:
2139 case MSR_VM_HSAVE_PA:
2140 case MSR_AMD64_PATCH_LOADER:
2141 case MSR_AMD64_BU_CFG2:
405a353a 2142 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2143 break;
2144
15c4a640 2145 case MSR_EFER:
b69e8cae 2146 return set_efer(vcpu, data);
8f1589d9
AP		 2147 case MSR_K7_HWCR:
2148 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2149 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2150 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2151 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2152 if (data != 0) {
a737f256
CD		 2153 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2154 data);
8f1589d9
AP		 2155 return 1;
2156 }
15c4a640 2157 break;
f7c6d140
AP		 2158 case MSR_FAM10H_MMIO_CONF_BASE:
2159 if (data != 0) {
a737f256
CD		 2160 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2161 "0x%llx\n", data);
f7c6d140
AP		 2162 return 1;
2163 }
15c4a640 2164 break;
b5e2fec0
AG		 2165 case MSR_IA32_DEBUGCTLMSR:
2166 if (!data) {
2167 /* We support the non-activated case already */
2168 break;
2169 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2170 /* Values other than LBR and BTF are vendor-specific,
2171 thus reserved and should throw a #GP */
2172 return 1;
2173 }
a737f256
CD		 2174 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2175 __func__, data);
b5e2fec0 2176 break;
9ba075a6 2177 case 0x200 ... 0x2ff:
ff53604b 2178 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2179 case MSR_IA32_APICBASE:
58cb628d 2180 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2181 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2182 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2183 case MSR_IA32_TSCDEADLINE:
2184 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2185 break;
ba904635
WA		 2186 case MSR_IA32_TSC_ADJUST:
2187 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2188 if (!msr_info->host_initiated) {
d913b904 2189 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2190 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2191 }
2192 vcpu->arch.ia32_tsc_adjust_msr = data;
2193 }
2194 break;
15c4a640 2195 case MSR_IA32_MISC_ENABLE:
ad312c7c 2196 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2197 break;
64d60670
PB		 2198 case MSR_IA32_SMBASE:
2199 if (!msr_info->host_initiated)
2200 return 1;
2201 vcpu->arch.smbase = data;
2202 break;
11c6bffa 2203 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2204 case MSR_KVM_WALL_CLOCK:
2205 vcpu->kvm->arch.wall_clock = data;
2206 kvm_write_wall_clock(vcpu->kvm, data);
2207 break;
11c6bffa 2208 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2209 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2210 struct kvm_arch *ka = &vcpu->kvm->arch;
2211
12f9a48f 2212 kvmclock_reset(vcpu);
18068523 2213
54750f2c
MT		 2214 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2215 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2216
2217 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2218 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2219
2220 ka->boot_vcpu_runs_old_kvmclock = tmp;
2221 }
2222
18068523 2223 vcpu->arch.time = data;
0061d53d 2224 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2225
2226 /* we verify if the enable bit is set... */
2227 if (!(data & 1))
2228 break;
2229
4e335d9e 2230 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2231 &vcpu->arch.pv_time, data & ~1ULL,
2232 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2233 vcpu->arch.pv_time_enabled = false;
2234 else
2235 vcpu->arch.pv_time_enabled = true;
32cad84f 2236
18068523
GOC		 2237 break;
2238 }
344d9588
GN		 2239 case MSR_KVM_ASYNC_PF_EN:
2240 if (kvm_pv_enable_async_pf(vcpu, data))
2241 return 1;
2242 break;
c9aaa895
GC		 2243 case MSR_KVM_STEAL_TIME:
2244
2245 if (unlikely(!sched_info_on()))
2246 return 1;
2247
2248 if (data & KVM_STEAL_RESERVED_MASK)
2249 return 1;
2250
4e335d9e 2251 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2252 data & KVM_STEAL_VALID_BITS,
2253 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2254 return 1;
2255
2256 vcpu->arch.st.msr_val = data;
2257
2258 if (!(data & KVM_MSR_ENABLED))
2259 break;
2260
c9aaa895
GC		 2261 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2262
2263 break;
ae7a2a3f
MT		 2264 case MSR_KVM_PV_EOI_EN:
2265 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2266 return 1;
2267 break;
c9aaa895 2268
890ca9ae
HY		 2269 case MSR_IA32_MCG_CTL:
2270 case MSR_IA32_MCG_STATUS:
81760dcc 2271 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2272 return set_msr_mce(vcpu, msr, data);
71db6023 2273
6912ac32
WH		 2274 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2275 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2276 pr = true; /* fall through */
2277 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2278 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2279 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2280 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2281
2282 if (pr || data != 0)
a737f256
CD		 2283 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2284 "0x%x data 0x%llx\n", msr, data);
5753785f 2285 break;
84e0cefa
JS		 2286 case MSR_K7_CLK_CTL:
2287 /*
2288 * Ignore all writes to this no longer documented MSR.
2289 * Writes are only relevant for old K7 processors,
2290 * all pre-dating SVM, but a recommended workaround from
4a969980 2291 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2292 * affected processor models on the command line, hence
2293 * the need to ignore the workaround.
2294 */
2295 break;
55cd8e5a 2296 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2297 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2298 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2299 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2300 return kvm_hv_set_msr_common(vcpu, msr, data,
2301 msr_info->host_initiated);
91c9c3ed 2302 case MSR_IA32_BBL_CR_CTL3:
2303 /* Drop writes to this legacy MSR -- see rdmsr
2304 * counterpart for further detail.
2305 */
796f4687 2306 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2307 break;
2b036c6b
BO		 2308 case MSR_AMD64_OSVW_ID_LENGTH:
2309 if (!guest_cpuid_has_osvw(vcpu))
2310 return 1;
2311 vcpu->arch.osvw.length = data;
2312 break;
2313 case MSR_AMD64_OSVW_STATUS:
2314 if (!guest_cpuid_has_osvw(vcpu))
2315 return 1;
2316 vcpu->arch.osvw.status = data;
2317 break;
db2336a8
KH		 2318 case MSR_PLATFORM_INFO:
2319 if (!msr_info->host_initiated ||
2320 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2321 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2322 cpuid_fault_enabled(vcpu)))
2323 return 1;
2324 vcpu->arch.msr_platform_info = data;
2325 break;
2326 case MSR_MISC_FEATURES_ENABLES:
2327 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2328 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2329 !supports_cpuid_fault(vcpu)))
2330 return 1;
2331 vcpu->arch.msr_misc_features_enables = data;
2332 break;
15c4a640 2333 default:
ffde22ac
ES		 2334 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2335 return xen_hvm_config(vcpu, data);
c6702c9d 2336 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2337 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2338 if (!ignore_msrs) {
ae0f5499 2339 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2340 msr, data);
ed85c068
AP		 2341 return 1;
2342 } else {
796f4687 2343 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2344 msr, data);
ed85c068
AP		 2345 break;
2346 }
15c4a640
CO		 2347 }
2348 return 0;
2349}
2350EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2351
2352
2353/*
2354 * Reads an msr value (of 'msr_index') into 'pdata'.
2355 * Returns 0 on success, non-0 otherwise.
2356 * Assumes vcpu_load() was already called.
2357 */
609e36d3 2358int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2359{
609e36d3 2360 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2361}
ff651cb6 2362EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2363
890ca9ae 2364static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2365{
2366 u64 data;
890ca9ae
HY		 2367 u64 mcg_cap = vcpu->arch.mcg_cap;
2368 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2369
2370 switch (msr) {
15c4a640
CO		 2371 case MSR_IA32_P5_MC_ADDR:
2372 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2373 data = 0;
2374 break;
15c4a640 2375 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2376 data = vcpu->arch.mcg_cap;
2377 break;
c7ac679c 2378 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2379 if (!(mcg_cap & MCG_CTL_P))
2380 return 1;
2381 data = vcpu->arch.mcg_ctl;
2382 break;
2383 case MSR_IA32_MCG_STATUS:
2384 data = vcpu->arch.mcg_status;
2385 break;
2386 default:
2387 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2388 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2389 u32 offset = msr - MSR_IA32_MC0_CTL;
2390 data = vcpu->arch.mce_banks[offset];
2391 break;
2392 }
2393 return 1;
2394 }
2395 *pdata = data;
2396 return 0;
2397}
2398
609e36d3 2399int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2400{
609e36d3 2401 switch (msr_info->index) {
890ca9ae 2402 case MSR_IA32_PLATFORM_ID:
15c4a640 2403 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2404 case MSR_IA32_DEBUGCTLMSR:
2405 case MSR_IA32_LASTBRANCHFROMIP:
2406 case MSR_IA32_LASTBRANCHTOIP:
2407 case MSR_IA32_LASTINTFROMIP:
2408 case MSR_IA32_LASTINTTOIP:
60af2ecd 2409 case MSR_K8_SYSCFG:
3afb1121
PB		 2410 case MSR_K8_TSEG_ADDR:
2411 case MSR_K8_TSEG_MASK:
60af2ecd 2412 case MSR_K7_HWCR:
61a6bd67 2413 case MSR_VM_HSAVE_PA:
1fdbd48c 2414 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2415 case MSR_AMD64_NB_CFG:
f7c6d140 2416 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2417 case MSR_AMD64_BU_CFG2:
0c2df2a1 2418 case MSR_IA32_PERF_CTL:
405a353a 2419 case MSR_AMD64_DC_CFG:
609e36d3 2420 msr_info->data = 0;
15c4a640 2421 break;
6912ac32
WH		 2422 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2423 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2424 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2425 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2426 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2427 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2428 msr_info->data = 0;
5753785f 2429 break;
742bc670 2430 case MSR_IA32_UCODE_REV:
609e36d3 2431 msr_info->data = 0x100000000ULL;
742bc670 2432 break;
9ba075a6 2433 case MSR_MTRRcap:
9ba075a6 2434 case 0x200 ... 0x2ff:
ff53604b 2435 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2436 case 0xcd: /* fsb frequency */
609e36d3 2437 msr_info->data = 3;
15c4a640 2438 break;
7b914098
JS		 2439 /*
2440 * MSR_EBC_FREQUENCY_ID
2441 * Conservative value valid for even the basic CPU models.
2442 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2443 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2444 * and 266MHz for model 3, or 4. Set Core Clock
2445 * Frequency to System Bus Frequency Ratio to 1 (bits
2446 * 31:24) even though these are only valid for CPU
2447 * models > 2, however guests may end up dividing or
2448 * multiplying by zero otherwise.
2449 */
2450 case MSR_EBC_FREQUENCY_ID:
609e36d3 2451 msr_info->data = 1 << 24;
7b914098 2452 break;
15c4a640 2453 case MSR_IA32_APICBASE:
609e36d3 2454 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2455 break;
0105d1a5 2456 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2457 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2458 break;
a3e06bbe 2459 case MSR_IA32_TSCDEADLINE:
609e36d3 2460 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2461 break;
ba904635 2462 case MSR_IA32_TSC_ADJUST:
609e36d3 2463 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2464 break;
15c4a640 2465 case MSR_IA32_MISC_ENABLE:
609e36d3 2466 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2467 break;
64d60670
PB		 2468 case MSR_IA32_SMBASE:
2469 if (!msr_info->host_initiated)
2470 return 1;
2471 msr_info->data = vcpu->arch.smbase;
15c4a640 2472 break;
847f0ad8
AG		 2473 case MSR_IA32_PERF_STATUS:
2474 /* TSC increment by tick */
609e36d3 2475 msr_info->data = 1000ULL;
847f0ad8 2476 /* CPU multiplier */
b0996ae4 2477 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2478 break;
15c4a640 2479 case MSR_EFER:
609e36d3 2480 msr_info->data = vcpu->arch.efer;
15c4a640 2481 break;
18068523 2482 case MSR_KVM_WALL_CLOCK:
11c6bffa 2483 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2484 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2485 break;
2486 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2487 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2488 msr_info->data = vcpu->arch.time;
18068523 2489 break;
344d9588 2490 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2491 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2492 break;
c9aaa895 2493 case MSR_KVM_STEAL_TIME:
609e36d3 2494 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2495 break;
1d92128f 2496 case MSR_KVM_PV_EOI_EN:
609e36d3 2497 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2498 break;
890ca9ae
HY		 2499 case MSR_IA32_P5_MC_ADDR:
2500 case MSR_IA32_P5_MC_TYPE:
2501 case MSR_IA32_MCG_CAP:
2502 case MSR_IA32_MCG_CTL:
2503 case MSR_IA32_MCG_STATUS:
81760dcc 2504 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2505 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2506 case MSR_K7_CLK_CTL:
2507 /*
2508 * Provide expected ramp-up count for K7. All other
2509 * are set to zero, indicating minimum divisors for
2510 * every field.
2511 *
2512 * This prevents guest kernels on AMD host with CPU
2513 * type 6, model 8 and higher from exploding due to
2514 * the rdmsr failing.
2515 */
609e36d3 2516 msr_info->data = 0x20000000;
84e0cefa 2517 break;
55cd8e5a 2518 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2519 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2520 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2521 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2522 return kvm_hv_get_msr_common(vcpu,
2523 msr_info->index, &msr_info->data);
55cd8e5a 2524 break;
91c9c3ed 2525 case MSR_IA32_BBL_CR_CTL3:
2526 /* This legacy MSR exists but isn't fully documented in current
2527 * silicon. It is however accessed by winxp in very narrow
2528 * scenarios where it sets bit #19, itself documented as
2529 * a "reserved" bit. Best effort attempt to source coherent
2530 * read data here should the balance of the register be
2531 * interpreted by the guest:
2532 *
2533 * L2 cache control register 3: 64GB range, 256KB size,
2534 * enabled, latency 0x1, configured
2535 */
609e36d3 2536 msr_info->data = 0xbe702111;
91c9c3ed 2537 break;
2b036c6b
BO		 2538 case MSR_AMD64_OSVW_ID_LENGTH:
2539 if (!guest_cpuid_has_osvw(vcpu))
2540 return 1;
609e36d3 2541 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2542 break;
2543 case MSR_AMD64_OSVW_STATUS:
2544 if (!guest_cpuid_has_osvw(vcpu))
2545 return 1;
609e36d3 2546 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2547 break;
db2336a8
KH		 2548 case MSR_PLATFORM_INFO:
2549 msr_info->data = vcpu->arch.msr_platform_info;
2550 break;
2551 case MSR_MISC_FEATURES_ENABLES:
2552 msr_info->data = vcpu->arch.msr_misc_features_enables;
2553 break;
15c4a640 2554 default:
c6702c9d 2555 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2556 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2557 if (!ignore_msrs) {
ae0f5499
BD		 2558 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2559 msr_info->index);
ed85c068
AP		 2560 return 1;
2561 } else {
609e36d3
PB		 2562 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2563 msr_info->data = 0;
ed85c068
AP		 2564 }
2565 break;
15c4a640 2566 }
15c4a640
CO		 2567 return 0;
2568}
2569EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2570
313a3dc7
CO		 2571/*
2572 * Read or write a bunch of msrs. All parameters are kernel addresses.
2573 *
2574 * @return number of msrs set successfully.
2575 */
2576static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2577 struct kvm_msr_entry *entries,
2578 int (*do_msr)(struct kvm_vcpu *vcpu,
2579 unsigned index, u64 *data))
2580{
f656ce01 2581 int i, idx;
313a3dc7 2582
f656ce01 2583 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2584 for (i = 0; i < msrs->nmsrs; ++i)
2585 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2586 break;
f656ce01 2587 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2588
313a3dc7
CO		 2589 return i;
2590}
2591
2592/*
2593 * Read or write a bunch of msrs. Parameters are user addresses.
2594 *
2595 * @return number of msrs set successfully.
2596 */
2597static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2598 int (*do_msr)(struct kvm_vcpu *vcpu,
2599 unsigned index, u64 *data),
2600 int writeback)
2601{
2602 struct kvm_msrs msrs;
2603 struct kvm_msr_entry *entries;
2604 int r, n;
2605 unsigned size;
2606
2607 r = -EFAULT;
2608 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2609 goto out;
2610
2611 r = -E2BIG;
2612 if (msrs.nmsrs >= MAX_IO_MSRS)
2613 goto out;
2614
313a3dc7 2615 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2616 entries = memdup_user(user_msrs->entries, size);
2617 if (IS_ERR(entries)) {
2618 r = PTR_ERR(entries);
313a3dc7 2619 goto out;
ff5c2c03 2620 }
313a3dc7
CO		 2621
2622 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2623 if (r < 0)
2624 goto out_free;
2625
2626 r = -EFAULT;
2627 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2628 goto out_free;
2629
2630 r = n;
2631
2632out_free:
7a73c028 2633 kfree(entries);
313a3dc7
CO		 2634out:
2635 return r;
2636}
2637
784aa3d7 2638int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2639{
2640 int r;
2641
2642 switch (ext) {
2643 case KVM_CAP_IRQCHIP:
2644 case KVM_CAP_HLT:
2645 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2646 case KVM_CAP_SET_TSS_ADDR:
07716717 2647 case KVM_CAP_EXT_CPUID:
9c15bb1d 2648 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2649 case KVM_CAP_CLOCKSOURCE:
7837699f 2650 case KVM_CAP_PIT:
a28e4f5a 2651 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2652 case KVM_CAP_MP_STATE:
ed848624 2653 case KVM_CAP_SYNC_MMU:
a355c85c 2654 case KVM_CAP_USER_NMI:
52d939a0 2655 case KVM_CAP_REINJECT_CONTROL:
4925663a 2656 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2657 case KVM_CAP_IOEVENTFD:
f848a5a8 2658 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2659 case KVM_CAP_PIT2:
e9f42757 2660 case KVM_CAP_PIT_STATE2:
b927a3ce 2661 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2662 case KVM_CAP_XEN_HVM:
3cfc3092 2663 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2664 case KVM_CAP_HYPERV:
10388a07 2665 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2666 case KVM_CAP_HYPERV_SPIN:
5c919412 2667 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2668 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2669 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2670 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2671 case KVM_CAP_DEBUGREGS:
d2be1651 2672 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2673 case KVM_CAP_XSAVE:
344d9588 2674 case KVM_CAP_ASYNC_PF:
92a1f12d 2675 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2676 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2677 case KVM_CAP_READONLY_MEM:
5f66b620 2678 case KVM_CAP_HYPERV_TIME:
100943c5 2679 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2680 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2681 case KVM_CAP_ENABLE_CAP_VM:
2682 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2683 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2684 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2685 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2686 r = 1;
2687 break;
e3fd9a93
PB		 2688 case KVM_CAP_ADJUST_CLOCK:
2689 r = KVM_CLOCK_TSC_STABLE;
2690 break;
668fffa3
MT		 2691 case KVM_CAP_X86_GUEST_MWAIT:
2692 r = kvm_mwait_in_guest();
2693 break;
6d396b55
PB		 2694 case KVM_CAP_X86_SMM:
2695 /* SMBASE is usually relocated above 1M on modern chipsets,
2696 * and SMM handlers might indeed rely on 4G segment limits,
2697 * so do not report SMM to be available if real mode is
2698 * emulated via vm86 mode. Still, do not go to great lengths
2699 * to avoid userspace's usage of the feature, because it is a
2700 * fringe case that is not enabled except via specific settings
2701 * of the module parameters.
2702 */
2703 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2704 break;
774ead3a
AK		 2705 case KVM_CAP_VAPIC:
2706 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2707 break;
f725230a 2708 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2709 r = KVM_SOFT_MAX_VCPUS;
2710 break;
2711 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2712 r = KVM_MAX_VCPUS;
2713 break;
a988b910 2714 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2715 r = KVM_USER_MEM_SLOTS;
a988b910 2716 break;
a68a6a72
MT		 2717 case KVM_CAP_PV_MMU: /* obsolete */
2718 r = 0;
2f333bcb 2719 break;
890ca9ae
HY		 2720 case KVM_CAP_MCE:
2721 r = KVM_MAX_MCE_BANKS;
2722 break;
2d5b5a66 2723 case KVM_CAP_XCRS:
d366bf7e 2724 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2725 break;
92a1f12d
JR		 2726 case KVM_CAP_TSC_CONTROL:
2727 r = kvm_has_tsc_control;
2728 break;
37131313
RK		 2729 case KVM_CAP_X2APIC_API:
2730 r = KVM_X2APIC_API_VALID_FLAGS;
2731 break;
018d00d2
ZX		 2732 default:
2733 r = 0;
2734 break;
2735 }
2736 return r;
2737
2738}
2739
043405e1
CO		 2740long kvm_arch_dev_ioctl(struct file *filp,
2741 unsigned int ioctl, unsigned long arg)
2742{
2743 void __user *argp = (void __user *)arg;
2744 long r;
2745
2746 switch (ioctl) {
2747 case KVM_GET_MSR_INDEX_LIST: {
2748 struct kvm_msr_list __user *user_msr_list = argp;
2749 struct kvm_msr_list msr_list;
2750 unsigned n;
2751
2752 r = -EFAULT;
2753 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2754 goto out;
2755 n = msr_list.nmsrs;
62ef68bb 2756 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2757 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2758 goto out;
2759 r = -E2BIG;
e125e7b6 2760 if (n < msr_list.nmsrs)
043405e1
CO		 2761 goto out;
2762 r = -EFAULT;
2763 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2764 num_msrs_to_save * sizeof(u32)))
2765 goto out;
e125e7b6 2766 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2767 &emulated_msrs,
62ef68bb 2768 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2769 goto out;
2770 r = 0;
2771 break;
2772 }
9c15bb1d
BP		 2773 case KVM_GET_SUPPORTED_CPUID:
2774 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2775 struct kvm_cpuid2 __user *cpuid_arg = argp;
2776 struct kvm_cpuid2 cpuid;
2777
2778 r = -EFAULT;
2779 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2780 goto out;
9c15bb1d
BP		 2781
2782 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2783 ioctl);
674eea0f
AK		 2784 if (r)
2785 goto out;
2786
2787 r = -EFAULT;
2788 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2789 goto out;
2790 r = 0;
2791 break;
2792 }
890ca9ae 2793 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2794 r = -EFAULT;
c45dcc71
AR		 2795 if (copy_to_user(argp, &kvm_mce_cap_supported,
2796 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2797 goto out;
2798 r = 0;
2799 break;
2800 }
043405e1
CO		 2801 default:
2802 r = -EINVAL;
2803 }
2804out:
2805 return r;
2806}
2807
f5f48ee1
SY		 2808static void wbinvd_ipi(void *garbage)
2809{
2810 wbinvd();
2811}
2812
2813static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2814{
e0f0bbc5 2815 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2816}
2817
313a3dc7
CO		 2818void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2819{
f5f48ee1
SY		 2820 /* Address WBINVD may be executed by guest */
2821 if (need_emulate_wbinvd(vcpu)) {
2822 if (kvm_x86_ops->has_wbinvd_exit())
2823 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2824 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2825 smp_call_function_single(vcpu->cpu,
2826 wbinvd_ipi, NULL, 1);
2827 }
2828
313a3dc7 2829 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2830
0dd6a6ed
ZA		 2831 /* Apply any externally detected TSC adjustments (due to suspend) */
2832 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2833 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2834 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2835 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2836 }
8f6055cb 2837
48434c20 2838 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2839 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2840 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2841 if (tsc_delta < 0)
2842 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2843
c285545f 2844 if (check_tsc_unstable()) {
07c1419a 2845 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2846 vcpu->arch.last_guest_tsc);
a545ab6a 2847 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2848 vcpu->arch.tsc_catchup = 1;
c285545f 2849 }
a749e247
PB		 2850
2851 if (kvm_lapic_hv_timer_in_use(vcpu))
2852 kvm_lapic_restart_hv_timer(vcpu);
2853
d98d07ca
MT		 2854 /*
2855 * On a host with synchronized TSC, there is no need to update
2856 * kvmclock on vcpu->cpu migration
2857 */
2858 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2859 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2860 if (vcpu->cpu != cpu)
1bd2009e 2861 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2862 vcpu->cpu = cpu;
6b7d7e76 2863 }
c9aaa895 2864
c9aaa895 2865 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2866}
2867
0b9f6c46
PX		 2868static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2869{
2870 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2871 return;
2872
2873 vcpu->arch.st.steal.preempted = 1;
2874
4e335d9e 2875 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2876 &vcpu->arch.st.steal.preempted,
2877 offsetof(struct kvm_steal_time, preempted),
2878 sizeof(vcpu->arch.st.steal.preempted));
2879}
2880
313a3dc7
CO		 2881void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2882{
cc0d907c 2883 int idx;
931f261b
AA		 2884 /*
2885 * Disable page faults because we're in atomic context here.
2886 * kvm_write_guest_offset_cached() would call might_fault()
2887 * that relies on pagefault_disable() to tell if there's a
2888 * bug. NOTE: the write to guest memory may not go through if
2889 * during postcopy live migration or if there's heavy guest
2890 * paging.
2891 */
2892 pagefault_disable();
cc0d907c
AA		 2893 /*
2894 * kvm_memslots() will be called by
2895 * kvm_write_guest_offset_cached() so take the srcu lock.
2896 */
2897 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2898 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2899 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2900 pagefault_enable();
02daab21 2901 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2902 kvm_put_guest_fpu(vcpu);
4ea1636b 2903 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2904}
2905
313a3dc7
CO		 2906static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2907 struct kvm_lapic_state *s)
2908{
76dfafd5 2909 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2910 kvm_x86_ops->sync_pir_to_irr(vcpu);
2911
a92e2543 2912 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2913}
2914
2915static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2916 struct kvm_lapic_state *s)
2917{
a92e2543
RK		 2918 int r;
2919
2920 r = kvm_apic_set_state(vcpu, s);
2921 if (r)
2922 return r;
cb142eb7 2923 update_cr8_intercept(vcpu);
313a3dc7
CO		 2924
2925 return 0;
2926}
2927
127a457a
MG		 2928static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2929{
2930 return (!lapic_in_kernel(vcpu) ||
2931 kvm_apic_accept_pic_intr(vcpu));
2932}
2933
782d422b
MG		 2934/*
2935 * if userspace requested an interrupt window, check that the
2936 * interrupt window is open.
2937 *
2938 * No need to exit to userspace if we already have an interrupt queued.
2939 */
2940static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2941{
2942 return kvm_arch_interrupt_allowed(vcpu) &&
2943 !kvm_cpu_has_interrupt(vcpu) &&
2944 !kvm_event_needs_reinjection(vcpu) &&
2945 kvm_cpu_accept_dm_intr(vcpu);
2946}
2947
f77bc6a4
ZX		 2948static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2949 struct kvm_interrupt *irq)
2950{
02cdb50f 2951 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2952 return -EINVAL;
1c1a9ce9
SR		 2953
2954 if (!irqchip_in_kernel(vcpu->kvm)) {
2955 kvm_queue_interrupt(vcpu, irq->irq, false);
2956 kvm_make_request(KVM_REQ_EVENT, vcpu);
2957 return 0;
2958 }
2959
2960 /*
2961 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2962 * fail for in-kernel 8259.
2963 */
2964 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2965 return -ENXIO;
f77bc6a4 2966
1c1a9ce9
SR		 2967 if (vcpu->arch.pending_external_vector != -1)
2968 return -EEXIST;
f77bc6a4 2969
1c1a9ce9 2970 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2971 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2972 return 0;
2973}
2974
c4abb7c9
JK		 2975static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2976{
c4abb7c9 2977 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2978
2979 return 0;
2980}
2981
f077825a
PB		 2982static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2983{
64d60670
PB		 2984 kvm_make_request(KVM_REQ_SMI, vcpu);
2985
f077825a
PB		 2986 return 0;
2987}
2988
b209749f
AK		 2989static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2990 struct kvm_tpr_access_ctl *tac)
2991{
2992 if (tac->flags)
2993 return -EINVAL;
2994 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2995 return 0;
2996}
2997
890ca9ae
HY		 2998static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2999 u64 mcg_cap)
3000{
3001 int r;
3002 unsigned bank_num = mcg_cap & 0xff, bank;
3003
3004 r = -EINVAL;
a9e38c3e 3005 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3006 goto out;
c45dcc71 3007 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3008 goto out;
3009 r = 0;
3010 vcpu->arch.mcg_cap = mcg_cap;
3011 /* Init IA32_MCG_CTL to all 1s */
3012 if (mcg_cap & MCG_CTL_P)
3013 vcpu->arch.mcg_ctl = ~(u64)0;
3014 /* Init IA32_MCi_CTL to all 1s */
3015 for (bank = 0; bank < bank_num; bank++)
3016 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3017
3018 if (kvm_x86_ops->setup_mce)
3019 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3020out:
3021 return r;
3022}
3023
3024static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3025 struct kvm_x86_mce *mce)
3026{
3027 u64 mcg_cap = vcpu->arch.mcg_cap;
3028 unsigned bank_num = mcg_cap & 0xff;
3029 u64 *banks = vcpu->arch.mce_banks;
3030
3031 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3032 return -EINVAL;
3033 /*
3034 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3035 * reporting is disabled
3036 */
3037 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3038 vcpu->arch.mcg_ctl != ~(u64)0)
3039 return 0;
3040 banks += 4 * mce->bank;
3041 /*
3042 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3043 * reporting is disabled for the bank
3044 */
3045 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3046 return 0;
3047 if (mce->status & MCI_STATUS_UC) {
3048 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3049 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3050 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3051 return 0;
3052 }
3053 if (banks[1] & MCI_STATUS_VAL)
3054 mce->status |= MCI_STATUS_OVER;
3055 banks[2] = mce->addr;
3056 banks[3] = mce->misc;
3057 vcpu->arch.mcg_status = mce->mcg_status;
3058 banks[1] = mce->status;
3059 kvm_queue_exception(vcpu, MC_VECTOR);
3060 } else if (!(banks[1] & MCI_STATUS_VAL)
3061 || !(banks[1] & MCI_STATUS_UC)) {
3062 if (banks[1] & MCI_STATUS_VAL)
3063 mce->status |= MCI_STATUS_OVER;
3064 banks[2] = mce->addr;
3065 banks[3] = mce->misc;
3066 banks[1] = mce->status;
3067 } else
3068 banks[1] |= MCI_STATUS_OVER;
3069 return 0;
3070}
3071
3cfc3092
JK		 3072static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3073 struct kvm_vcpu_events *events)
3074{
7460fb4a 3075 process_nmi(vcpu);
03b82a30
JK		 3076 events->exception.injected =
3077 vcpu->arch.exception.pending &&
3078 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3079 events->exception.nr = vcpu->arch.exception.nr;
3080 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3081 events->exception.pad = 0;
3cfc3092
JK		 3082 events->exception.error_code = vcpu->arch.exception.error_code;
3083
03b82a30
JK		 3084 events->interrupt.injected =
3085 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3086 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3087 events->interrupt.soft = 0;
37ccdcbe 3088 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3089
3090 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3091 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3092 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3093 events->nmi.pad = 0;
3cfc3092 3094
66450a21 3095 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3096
f077825a
PB		 3097 events->smi.smm = is_smm(vcpu);
3098 events->smi.pending = vcpu->arch.smi_pending;
3099 events->smi.smm_inside_nmi =
3100 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3101 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3102
dab4b911 3103 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3104 | KVM_VCPUEVENT_VALID_SHADOW
3105 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3106 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3107}
3108
6ef4e07e
XG		 3109static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3110
3cfc3092
JK		 3111static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3112 struct kvm_vcpu_events *events)
3113{
dab4b911 3114 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3115 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3116 | KVM_VCPUEVENT_VALID_SHADOW
3117 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3118 return -EINVAL;
3119
78e546c8 3120 if (events->exception.injected &&
28d06353
JM		 3121 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3122 is_guest_mode(vcpu)))
78e546c8
PB		 3123 return -EINVAL;
3124
28bf2888
DH		 3125 /* INITs are latched while in SMM */
3126 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3127 (events->smi.smm || events->smi.pending) &&
3128 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3129 return -EINVAL;
3130
7460fb4a 3131 process_nmi(vcpu);
3cfc3092
JK		 3132 vcpu->arch.exception.pending = events->exception.injected;
3133 vcpu->arch.exception.nr = events->exception.nr;
3134 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3135 vcpu->arch.exception.error_code = events->exception.error_code;
3136
3137 vcpu->arch.interrupt.pending = events->interrupt.injected;
3138 vcpu->arch.interrupt.nr = events->interrupt.nr;
3139 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3140 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3141 kvm_x86_ops->set_interrupt_shadow(vcpu,
3142 events->interrupt.shadow);
3cfc3092
JK		 3143
3144 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3145 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3146 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3147 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3148
66450a21 3149 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3150 lapic_in_kernel(vcpu))
66450a21 3151 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3152
f077825a 3153 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3154 u32 hflags = vcpu->arch.hflags;
f077825a 3155 if (events->smi.smm)
6ef4e07e 3156 hflags |= HF_SMM_MASK;
f077825a 3157 else
6ef4e07e
XG		 3158 hflags &= ~HF_SMM_MASK;
3159 kvm_set_hflags(vcpu, hflags);
3160
f077825a
PB		 3161 vcpu->arch.smi_pending = events->smi.pending;
3162 if (events->smi.smm_inside_nmi)
3163 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3164 else
3165 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3166 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3167 if (events->smi.latched_init)
3168 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3169 else
3170 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3171 }
3172 }
3173
3842d135
AK		 3174 kvm_make_request(KVM_REQ_EVENT, vcpu);
3175
3cfc3092
JK		 3176 return 0;
3177}
3178
a1efbe77
JK		 3179static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3180 struct kvm_debugregs *dbgregs)
3181{
73aaf249
JK		 3182 unsigned long val;
3183
a1efbe77 3184 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3185 kvm_get_dr(vcpu, 6, &val);
73aaf249 3186 dbgregs->dr6 = val;
a1efbe77
JK		 3187 dbgregs->dr7 = vcpu->arch.dr7;
3188 dbgregs->flags = 0;
97e69aa6 3189 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3190}
3191
3192static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3193 struct kvm_debugregs *dbgregs)
3194{
3195 if (dbgregs->flags)
3196 return -EINVAL;
3197
d14bdb55
PB		 3198 if (dbgregs->dr6 & ~0xffffffffull)
3199 return -EINVAL;
3200 if (dbgregs->dr7 & ~0xffffffffull)
3201 return -EINVAL;
3202
a1efbe77 3203 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3204 kvm_update_dr0123(vcpu);
a1efbe77 3205 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3206 kvm_update_dr6(vcpu);
a1efbe77 3207 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3208 kvm_update_dr7(vcpu);
a1efbe77 3209
a1efbe77
JK		 3210 return 0;
3211}
3212
df1daba7
PB		 3213#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3214
3215static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3216{
c47ada30 3217 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3218 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3219 u64 valid;
3220
3221 /*
3222 * Copy legacy XSAVE area, to avoid complications with CPUID
3223 * leaves 0 and 1 in the loop below.
3224 */
3225 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3226
3227 /* Set XSTATE_BV */
00c87e9a 3228 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3229 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3230
3231 /*
3232 * Copy each region from the possibly compacted offset to the
3233 * non-compacted offset.
3234 */
d91cab78 3235 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3236 while (valid) {
3237 u64 feature = valid & -valid;
3238 int index = fls64(feature) - 1;
3239 void *src = get_xsave_addr(xsave, feature);
3240
3241 if (src) {
3242 u32 size, offset, ecx, edx;
3243 cpuid_count(XSTATE_CPUID, index,
3244 &size, &offset, &ecx, &edx);
3245 memcpy(dest + offset, src, size);
3246 }
3247
3248 valid -= feature;
3249 }
3250}
3251
3252static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3253{
c47ada30 3254 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3255 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3256 u64 valid;
3257
3258 /*
3259 * Copy legacy XSAVE area, to avoid complications with CPUID
3260 * leaves 0 and 1 in the loop below.
3261 */
3262 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3263
3264 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3265 xsave->header.xfeatures = xstate_bv;
782511b0 3266 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3267 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3268
3269 /*
3270 * Copy each region from the non-compacted offset to the
3271 * possibly compacted offset.
3272 */
d91cab78 3273 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3274 while (valid) {
3275 u64 feature = valid & -valid;
3276 int index = fls64(feature) - 1;
3277 void *dest = get_xsave_addr(xsave, feature);
3278
3279 if (dest) {
3280 u32 size, offset, ecx, edx;
3281 cpuid_count(XSTATE_CPUID, index,
3282 &size, &offset, &ecx, &edx);
3283 memcpy(dest, src + offset, size);
ee4100da 3284 }
df1daba7
PB		 3285
3286 valid -= feature;
3287 }
3288}
3289
2d5b5a66
SY		 3290static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3291 struct kvm_xsave *guest_xsave)
3292{
d366bf7e 3293 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3294 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3295 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3296 } else {
2d5b5a66 3297 memcpy(guest_xsave->region,
7366ed77 3298 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3299 sizeof(struct fxregs_state));
2d5b5a66 3300 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3301 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3302 }
3303}
3304
a575813b
WL		 3305#define XSAVE_MXCSR_OFFSET 24
3306
2d5b5a66
SY		 3307static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3308 struct kvm_xsave *guest_xsave)
3309{
3310 u64 xstate_bv =
3311 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3312 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3313
d366bf7e 3314 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3315 /*
3316 * Here we allow setting states that are not present in
3317 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3318 * with old userspace.
3319 */
a575813b
WL		 3320 if (xstate_bv & ~kvm_supported_xcr0() ||
3321 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3322 return -EINVAL;
df1daba7 3323 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3324 } else {
a575813b
WL		 3325 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3326 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3327 return -EINVAL;
7366ed77 3328 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3329 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3330 }
3331 return 0;
3332}
3333
3334static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3335 struct kvm_xcrs *guest_xcrs)
3336{
d366bf7e 3337 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3338 guest_xcrs->nr_xcrs = 0;
3339 return;
3340 }
3341
3342 guest_xcrs->nr_xcrs = 1;
3343 guest_xcrs->flags = 0;
3344 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3345 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3346}
3347
3348static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3349 struct kvm_xcrs *guest_xcrs)
3350{
3351 int i, r = 0;
3352
d366bf7e 3353 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3354 return -EINVAL;
3355
3356 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3357 return -EINVAL;
3358
3359 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3360 /* Only support XCR0 currently */
c67a04cb 3361 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3362 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3363 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3364 break;
3365 }
3366 if (r)
3367 r = -EINVAL;
3368 return r;
3369}
3370
1c0b28c2
EM		 3371/*
3372 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3373 * stopped by the hypervisor. This function will be called from the host only.
3374 * EINVAL is returned when the host attempts to set the flag for a guest that
3375 * does not support pv clocks.
3376 */
3377static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3378{
0b79459b 3379 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3380 return -EINVAL;
51d59c6b 3381 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3382 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3383 return 0;
3384}
3385
5c919412
AS		 3386static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3387 struct kvm_enable_cap *cap)
3388{
3389 if (cap->flags)
3390 return -EINVAL;
3391
3392 switch (cap->cap) {
efc479e6
RK		 3393 case KVM_CAP_HYPERV_SYNIC2:
3394 if (cap->args[0])
3395 return -EINVAL;
5c919412 3396 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3397 if (!irqchip_in_kernel(vcpu->kvm))
3398 return -EINVAL;
efc479e6
RK		 3399 return kvm_hv_activate_synic(vcpu, cap->cap ==
3400 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3401 default:
3402 return -EINVAL;
3403 }
3404}
3405
313a3dc7
CO		 3406long kvm_arch_vcpu_ioctl(struct file *filp,
3407 unsigned int ioctl, unsigned long arg)
3408{
3409 struct kvm_vcpu *vcpu = filp->private_data;
3410 void __user *argp = (void __user *)arg;
3411 int r;
d1ac91d8
AK		 3412 union {
3413 struct kvm_lapic_state *lapic;
3414 struct kvm_xsave *xsave;
3415 struct kvm_xcrs *xcrs;
3416 void *buffer;
3417 } u;
3418
3419 u.buffer = NULL;
313a3dc7
CO		 3420 switch (ioctl) {
3421 case KVM_GET_LAPIC: {
2204ae3c 3422 r = -EINVAL;
bce87cce 3423 if (!lapic_in_kernel(vcpu))
2204ae3c 3424 goto out;
d1ac91d8 3425 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3426
b772ff36 3427 r = -ENOMEM;
d1ac91d8 3428 if (!u.lapic)
b772ff36 3429 goto out;
d1ac91d8 3430 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3431 if (r)
3432 goto out;
3433 r = -EFAULT;
d1ac91d8 3434 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3435 goto out;
3436 r = 0;
3437 break;
3438 }
3439 case KVM_SET_LAPIC: {
2204ae3c 3440 r = -EINVAL;
bce87cce 3441 if (!lapic_in_kernel(vcpu))
2204ae3c 3442 goto out;
ff5c2c03 3443 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3444 if (IS_ERR(u.lapic))
3445 return PTR_ERR(u.lapic);
ff5c2c03 3446
d1ac91d8 3447 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3448 break;
3449 }
f77bc6a4
ZX		 3450 case KVM_INTERRUPT: {
3451 struct kvm_interrupt irq;
3452
3453 r = -EFAULT;
3454 if (copy_from_user(&irq, argp, sizeof irq))
3455 goto out;
3456 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3457 break;
3458 }
c4abb7c9
JK		 3459 case KVM_NMI: {
3460 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3461 break;
3462 }
f077825a
PB		 3463 case KVM_SMI: {
3464 r = kvm_vcpu_ioctl_smi(vcpu);
3465 break;
3466 }
313a3dc7
CO		 3467 case KVM_SET_CPUID: {
3468 struct kvm_cpuid __user *cpuid_arg = argp;
3469 struct kvm_cpuid cpuid;
3470
3471 r = -EFAULT;
3472 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3473 goto out;
3474 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3475 break;
3476 }
07716717
DK		 3477 case KVM_SET_CPUID2: {
3478 struct kvm_cpuid2 __user *cpuid_arg = argp;
3479 struct kvm_cpuid2 cpuid;
3480
3481 r = -EFAULT;
3482 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3483 goto out;
3484 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3485 cpuid_arg->entries);
07716717
DK		 3486 break;
3487 }
3488 case KVM_GET_CPUID2: {
3489 struct kvm_cpuid2 __user *cpuid_arg = argp;
3490 struct kvm_cpuid2 cpuid;
3491
3492 r = -EFAULT;
3493 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3494 goto out;
3495 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3496 cpuid_arg->entries);
07716717
DK		 3497 if (r)
3498 goto out;
3499 r = -EFAULT;
3500 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3501 goto out;
3502 r = 0;
3503 break;
3504 }
313a3dc7 3505 case KVM_GET_MSRS:
609e36d3 3506 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3507 break;
3508 case KVM_SET_MSRS:
3509 r = msr_io(vcpu, argp, do_set_msr, 0);
3510 break;
b209749f
AK		 3511 case KVM_TPR_ACCESS_REPORTING: {
3512 struct kvm_tpr_access_ctl tac;
3513
3514 r = -EFAULT;
3515 if (copy_from_user(&tac, argp, sizeof tac))
3516 goto out;
3517 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3518 if (r)
3519 goto out;
3520 r = -EFAULT;
3521 if (copy_to_user(argp, &tac, sizeof tac))
3522 goto out;
3523 r = 0;
3524 break;
3525 };
b93463aa
AK		 3526 case KVM_SET_VAPIC_ADDR: {
3527 struct kvm_vapic_addr va;
7301d6ab 3528 int idx;
b93463aa
AK		 3529
3530 r = -EINVAL;
35754c98 3531 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3532 goto out;
3533 r = -EFAULT;
3534 if (copy_from_user(&va, argp, sizeof va))
3535 goto out;
7301d6ab 3536 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3537 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3538 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3539 break;
3540 }
890ca9ae
HY		 3541 case KVM_X86_SETUP_MCE: {
3542 u64 mcg_cap;
3543
3544 r = -EFAULT;
3545 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3546 goto out;
3547 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3548 break;
3549 }
3550 case KVM_X86_SET_MCE: {
3551 struct kvm_x86_mce mce;
3552
3553 r = -EFAULT;
3554 if (copy_from_user(&mce, argp, sizeof mce))
3555 goto out;
3556 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3557 break;
3558 }
3cfc3092
JK		 3559 case KVM_GET_VCPU_EVENTS: {
3560 struct kvm_vcpu_events events;
3561
3562 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3563
3564 r = -EFAULT;
3565 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3566 break;
3567 r = 0;
3568 break;
3569 }
3570 case KVM_SET_VCPU_EVENTS: {
3571 struct kvm_vcpu_events events;
3572
3573 r = -EFAULT;
3574 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3575 break;
3576
3577 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3578 break;
3579 }
a1efbe77
JK		 3580 case KVM_GET_DEBUGREGS: {
3581 struct kvm_debugregs dbgregs;
3582
3583 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3584
3585 r = -EFAULT;
3586 if (copy_to_user(argp, &dbgregs,
3587 sizeof(struct kvm_debugregs)))
3588 break;
3589 r = 0;
3590 break;
3591 }
3592 case KVM_SET_DEBUGREGS: {
3593 struct kvm_debugregs dbgregs;
3594
3595 r = -EFAULT;
3596 if (copy_from_user(&dbgregs, argp,
3597 sizeof(struct kvm_debugregs)))
3598 break;
3599
3600 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3601 break;
3602 }
2d5b5a66 3603 case KVM_GET_XSAVE: {
d1ac91d8 3604 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3605 r = -ENOMEM;
d1ac91d8 3606 if (!u.xsave)
2d5b5a66
SY		 3607 break;
3608
d1ac91d8 3609 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3610
3611 r = -EFAULT;
d1ac91d8 3612 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3613 break;
3614 r = 0;
3615 break;
3616 }
3617 case KVM_SET_XSAVE: {
ff5c2c03 3618 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3619 if (IS_ERR(u.xsave))
3620 return PTR_ERR(u.xsave);
2d5b5a66 3621
d1ac91d8 3622 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3623 break;
3624 }
3625 case KVM_GET_XCRS: {
d1ac91d8 3626 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3627 r = -ENOMEM;
d1ac91d8 3628 if (!u.xcrs)
2d5b5a66
SY		 3629 break;
3630
d1ac91d8 3631 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3632
3633 r = -EFAULT;
d1ac91d8 3634 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3635 sizeof(struct kvm_xcrs)))
3636 break;
3637 r = 0;
3638 break;
3639 }
3640 case KVM_SET_XCRS: {
ff5c2c03 3641 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3642 if (IS_ERR(u.xcrs))
3643 return PTR_ERR(u.xcrs);
2d5b5a66 3644
d1ac91d8 3645 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3646 break;
3647 }
92a1f12d
JR		 3648 case KVM_SET_TSC_KHZ: {
3649 u32 user_tsc_khz;
3650
3651 r = -EINVAL;
92a1f12d
JR		 3652 user_tsc_khz = (u32)arg;
3653
3654 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3655 goto out;
3656
cc578287
ZA		 3657 if (user_tsc_khz == 0)
3658 user_tsc_khz = tsc_khz;
3659
381d585c
HZ		 3660 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3661 r = 0;
92a1f12d 3662
92a1f12d
JR		 3663 goto out;
3664 }
3665 case KVM_GET_TSC_KHZ: {
cc578287 3666 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3667 goto out;
3668 }
1c0b28c2
EM		 3669 case KVM_KVMCLOCK_CTRL: {
3670 r = kvm_set_guest_paused(vcpu);
3671 goto out;
3672 }
5c919412
AS		 3673 case KVM_ENABLE_CAP: {
3674 struct kvm_enable_cap cap;
3675
3676 r = -EFAULT;
3677 if (copy_from_user(&cap, argp, sizeof(cap)))
3678 goto out;
3679 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3680 break;
3681 }
313a3dc7
CO		 3682 default:
3683 r = -EINVAL;
3684 }
3685out:
d1ac91d8 3686 kfree(u.buffer);
313a3dc7
CO		 3687 return r;
3688}
3689
5b1c1493
CO		 3690int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3691{
3692 return VM_FAULT_SIGBUS;
3693}
3694
1fe779f8
CO		 3695static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3696{
3697 int ret;
3698
3699 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3700 return -EINVAL;
1fe779f8
CO		 3701 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3702 return ret;
3703}
3704
b927a3ce
SY		 3705static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3706 u64 ident_addr)
3707{
3708 kvm->arch.ept_identity_map_addr = ident_addr;
3709 return 0;
3710}
3711
1fe779f8
CO		 3712static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3713 u32 kvm_nr_mmu_pages)
3714{
3715 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3716 return -EINVAL;
3717
79fac95e 3718 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3719
3720 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3721 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3722
79fac95e 3723 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3724 return 0;
3725}
3726
3727static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3728{
39de71ec 3729 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3730}
3731
1fe779f8
CO		 3732static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3733{
90bca052 3734 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3735 int r;
3736
3737 r = 0;
3738 switch (chip->chip_id) {
3739 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3740 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3741 sizeof(struct kvm_pic_state));
3742 break;
3743 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3744 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3745 sizeof(struct kvm_pic_state));
3746 break;
3747 case KVM_IRQCHIP_IOAPIC:
33392b49 3748 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3749 break;
3750 default:
3751 r = -EINVAL;
3752 break;
3753 }
3754 return r;
3755}
3756
3757static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3758{
90bca052 3759 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3760 int r;
3761
3762 r = 0;
3763 switch (chip->chip_id) {
3764 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3765 spin_lock(&pic->lock);
3766 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3767 sizeof(struct kvm_pic_state));
90bca052 3768 spin_unlock(&pic->lock);
1fe779f8
CO		 3769 break;
3770 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3771 spin_lock(&pic->lock);
3772 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3773 sizeof(struct kvm_pic_state));
90bca052 3774 spin_unlock(&pic->lock);
1fe779f8
CO		 3775 break;
3776 case KVM_IRQCHIP_IOAPIC:
33392b49 3777 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3778 break;
3779 default:
3780 r = -EINVAL;
3781 break;
3782 }
90bca052 3783 kvm_pic_update_irq(pic);
1fe779f8
CO		 3784 return r;
3785}
3786
e0f63cb9
SY		 3787static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3788{
34f3941c
RK		 3789 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3790
3791 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3792
3793 mutex_lock(&kps->lock);
3794 memcpy(ps, &kps->channels, sizeof(*ps));
3795 mutex_unlock(&kps->lock);
2da29bcc 3796 return 0;
e0f63cb9
SY		 3797}
3798
3799static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3800{
0185604c 3801 int i;
09edea72
RK		 3802 struct kvm_pit *pit = kvm->arch.vpit;
3803
3804 mutex_lock(&pit->pit_state.lock);
34f3941c 3805 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3806 for (i = 0; i < 3; i++)
09edea72
RK		 3807 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3808 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3809 return 0;
e9f42757
BK		 3810}
3811
3812static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3813{
e9f42757
BK		 3814 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3815 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3816 sizeof(ps->channels));
3817 ps->flags = kvm->arch.vpit->pit_state.flags;
3818 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3819 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3820 return 0;
e9f42757
BK		 3821}
3822
3823static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3824{
2da29bcc 3825 int start = 0;
0185604c 3826 int i;
e9f42757 3827 u32 prev_legacy, cur_legacy;
09edea72
RK		 3828 struct kvm_pit *pit = kvm->arch.vpit;
3829
3830 mutex_lock(&pit->pit_state.lock);
3831 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3832 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3833 if (!prev_legacy && cur_legacy)
3834 start = 1;
09edea72
RK		 3835 memcpy(&pit->pit_state.channels, &ps->channels,
3836 sizeof(pit->pit_state.channels));
3837 pit->pit_state.flags = ps->flags;
0185604c 3838 for (i = 0; i < 3; i++)
09edea72 3839 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3840 start && i == 0);
09edea72 3841 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3842 return 0;
e0f63cb9
SY		 3843}
3844
52d939a0
MT		 3845static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3846 struct kvm_reinject_control *control)
3847{
71474e2f
RK		 3848 struct kvm_pit *pit = kvm->arch.vpit;
3849
3850 if (!pit)
52d939a0 3851 return -ENXIO;
b39c90b6 3852
71474e2f
RK		 3853 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3854 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3855 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3856 */
3857 mutex_lock(&pit->pit_state.lock);
3858 kvm_pit_set_reinject(pit, control->pit_reinject);
3859 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3860
52d939a0
MT		 3861 return 0;
3862}
3863
95d4c16c 3864/**
60c34612
TY		 3865 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3866 * @kvm: kvm instance
3867 * @log: slot id and address to which we copy the log
95d4c16c 3868 *
e108ff2f
PB		 3869 * Steps 1-4 below provide general overview of dirty page logging. See
3870 * kvm_get_dirty_log_protect() function description for additional details.
3871 *
3872 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3873 * always flush the TLB (step 4) even if previous step failed and the dirty
3874 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3875 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3876 * writes will be marked dirty for next log read.
95d4c16c 3877 *
60c34612
TY		 3878 * 1. Take a snapshot of the bit and clear it if needed.
3879 * 2. Write protect the corresponding page.
e108ff2f
PB		 3880 * 3. Copy the snapshot to the userspace.
3881 * 4. Flush TLB's if needed.
5bb064dc 3882 */
60c34612 3883int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3884{
60c34612 3885 bool is_dirty = false;
e108ff2f 3886 int r;
5bb064dc 3887
79fac95e 3888 mutex_lock(&kvm->slots_lock);
5bb064dc 3889
88178fd4
KH		 3890 /*
3891 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3892 */
3893 if (kvm_x86_ops->flush_log_dirty)
3894 kvm_x86_ops->flush_log_dirty(kvm);
3895
e108ff2f 3896 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3897
3898 /*
3899 * All the TLBs can be flushed out of mmu lock, see the comments in
3900 * kvm_mmu_slot_remove_write_access().
3901 */
e108ff2f 3902 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3903 if (is_dirty)
3904 kvm_flush_remote_tlbs(kvm);
3905
79fac95e 3906 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3907 return r;
3908}
3909
aa2fbe6d
YZ		 3910int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3911 bool line_status)
23d43cf9
CD		 3912{
3913 if (!irqchip_in_kernel(kvm))
3914 return -ENXIO;
3915
3916 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3917 irq_event->irq, irq_event->level,
3918 line_status);
23d43cf9
CD		 3919 return 0;
3920}
3921
90de4a18
NA		 3922static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3923 struct kvm_enable_cap *cap)
3924{
3925 int r;
3926
3927 if (cap->flags)
3928 return -EINVAL;
3929
3930 switch (cap->cap) {
3931 case KVM_CAP_DISABLE_QUIRKS:
3932 kvm->arch.disabled_quirks = cap->args[0];
3933 r = 0;
3934 break;
49df6397
SR		 3935 case KVM_CAP_SPLIT_IRQCHIP: {
3936 mutex_lock(&kvm->lock);
b053b2ae
SR		 3937 r = -EINVAL;
3938 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3939 goto split_irqchip_unlock;
49df6397
SR		 3940 r = -EEXIST;
3941 if (irqchip_in_kernel(kvm))
3942 goto split_irqchip_unlock;
557abc40 3943 if (kvm->created_vcpus)
49df6397
SR		 3944 goto split_irqchip_unlock;
3945 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3946 if (r)
49df6397
SR		 3947 goto split_irqchip_unlock;
3948 /* Pairs with irqchip_in_kernel. */
3949 smp_wmb();
49776faf 3950 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3951 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3952 r = 0;
3953split_irqchip_unlock:
3954 mutex_unlock(&kvm->lock);
3955 break;
3956 }
37131313
RK		 3957 case KVM_CAP_X2APIC_API:
3958 r = -EINVAL;
3959 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3960 break;
3961
3962 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3963 kvm->arch.x2apic_format = true;
c519265f
RK		 3964 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3965 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3966
3967 r = 0;
3968 break;
90de4a18
NA		 3969 default:
3970 r = -EINVAL;
3971 break;
3972 }
3973 return r;
3974}
3975
1fe779f8
CO		 3976long kvm_arch_vm_ioctl(struct file *filp,
3977 unsigned int ioctl, unsigned long arg)
3978{
3979 struct kvm *kvm = filp->private_data;
3980 void __user *argp = (void __user *)arg;
367e1319 3981 int r = -ENOTTY;
f0d66275
DH		 3982 /*
3983 * This union makes it completely explicit to gcc-3.x
3984 * that these two variables' stack usage should be
3985 * combined, not added together.
3986 */
3987 union {
3988 struct kvm_pit_state ps;
e9f42757 3989 struct kvm_pit_state2 ps2;
c5ff41ce 3990 struct kvm_pit_config pit_config;
f0d66275 3991 } u;
1fe779f8
CO		 3992
3993 switch (ioctl) {
3994 case KVM_SET_TSS_ADDR:
3995 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3996 break;
b927a3ce
SY		 3997 case KVM_SET_IDENTITY_MAP_ADDR: {
3998 u64 ident_addr;
3999
4000 r = -EFAULT;
4001 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4002 goto out;
4003 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4004 break;
4005 }
1fe779f8
CO		 4006 case KVM_SET_NR_MMU_PAGES:
4007 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4008 break;
4009 case KVM_GET_NR_MMU_PAGES:
4010 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4011 break;
3ddea128 4012 case KVM_CREATE_IRQCHIP: {
3ddea128 4013 mutex_lock(&kvm->lock);
09941366 4014
3ddea128 4015 r = -EEXIST;
35e6eaa3 4016 if (irqchip_in_kernel(kvm))
3ddea128 4017 goto create_irqchip_unlock;
09941366 4018
3e515705 4019 r = -EINVAL;
557abc40 4020 if (kvm->created_vcpus)
3e515705 4021 goto create_irqchip_unlock;
09941366
RK		 4022
4023 r = kvm_pic_init(kvm);
4024 if (r)
3ddea128 4025 goto create_irqchip_unlock;
09941366
RK		 4026
4027 r = kvm_ioapic_init(kvm);
4028 if (r) {
09941366 4029 kvm_pic_destroy(kvm);
3ddea128 4030 goto create_irqchip_unlock;
09941366
RK		 4031 }
4032
399ec807
AK		 4033 r = kvm_setup_default_irq_routing(kvm);
4034 if (r) {
72bb2fcd 4035 kvm_ioapic_destroy(kvm);
09941366 4036 kvm_pic_destroy(kvm);
71ba994c 4037 goto create_irqchip_unlock;
399ec807 4038 }
49776faf 4039 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4040 smp_wmb();
49776faf 4041 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4042 create_irqchip_unlock:
4043 mutex_unlock(&kvm->lock);
1fe779f8 4044 break;
3ddea128 4045 }
7837699f 4046 case KVM_CREATE_PIT:
c5ff41ce
JK		 4047 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4048 goto create_pit;
4049 case KVM_CREATE_PIT2:
4050 r = -EFAULT;
4051 if (copy_from_user(&u.pit_config, argp,
4052 sizeof(struct kvm_pit_config)))
4053 goto out;
4054 create_pit:
250715a6 4055 mutex_lock(&kvm->lock);
269e05e4
AK		 4056 r = -EEXIST;
4057 if (kvm->arch.vpit)
4058 goto create_pit_unlock;
7837699f 4059 r = -ENOMEM;
c5ff41ce 4060 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4061 if (kvm->arch.vpit)
4062 r = 0;
269e05e4 4063 create_pit_unlock:
250715a6 4064 mutex_unlock(&kvm->lock);
7837699f 4065 break;
1fe779f8
CO		 4066 case KVM_GET_IRQCHIP: {
4067 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4068 struct kvm_irqchip *chip;
1fe779f8 4069
ff5c2c03
SL		 4070 chip = memdup_user(argp, sizeof(*chip));
4071 if (IS_ERR(chip)) {
4072 r = PTR_ERR(chip);
1fe779f8 4073 goto out;
ff5c2c03
SL		 4074 }
4075
1fe779f8 4076 r = -ENXIO;
826da321 4077 if (!irqchip_kernel(kvm))
f0d66275
DH		 4078 goto get_irqchip_out;
4079 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4080 if (r)
f0d66275 4081 goto get_irqchip_out;
1fe779f8 4082 r = -EFAULT;
f0d66275
DH		 4083 if (copy_to_user(argp, chip, sizeof *chip))
4084 goto get_irqchip_out;
1fe779f8 4085 r = 0;
f0d66275
DH		 4086 get_irqchip_out:
4087 kfree(chip);
1fe779f8
CO		 4088 break;
4089 }
4090 case KVM_SET_IRQCHIP: {
4091 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4092 struct kvm_irqchip *chip;
1fe779f8 4093
ff5c2c03
SL		 4094 chip = memdup_user(argp, sizeof(*chip));
4095 if (IS_ERR(chip)) {
4096 r = PTR_ERR(chip);
1fe779f8 4097 goto out;
ff5c2c03
SL		 4098 }
4099
1fe779f8 4100 r = -ENXIO;
826da321 4101 if (!irqchip_kernel(kvm))
f0d66275
DH		 4102 goto set_irqchip_out;
4103 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4104 if (r)
f0d66275 4105 goto set_irqchip_out;
1fe779f8 4106 r = 0;
f0d66275
DH		 4107 set_irqchip_out:
4108 kfree(chip);
1fe779f8
CO		 4109 break;
4110 }
e0f63cb9 4111 case KVM_GET_PIT: {
e0f63cb9 4112 r = -EFAULT;
f0d66275 4113 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4114 goto out;
4115 r = -ENXIO;
4116 if (!kvm->arch.vpit)
4117 goto out;
f0d66275 4118 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4119 if (r)
4120 goto out;
4121 r = -EFAULT;
f0d66275 4122 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4123 goto out;
4124 r = 0;
4125 break;
4126 }
4127 case KVM_SET_PIT: {
e0f63cb9 4128 r = -EFAULT;
f0d66275 4129 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4130 goto out;
4131 r = -ENXIO;
4132 if (!kvm->arch.vpit)
4133 goto out;
f0d66275 4134 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4135 break;
4136 }
e9f42757
BK		 4137 case KVM_GET_PIT2: {
4138 r = -ENXIO;
4139 if (!kvm->arch.vpit)
4140 goto out;
4141 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4142 if (r)
4143 goto out;
4144 r = -EFAULT;
4145 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4146 goto out;
4147 r = 0;
4148 break;
4149 }
4150 case KVM_SET_PIT2: {
4151 r = -EFAULT;
4152 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4153 goto out;
4154 r = -ENXIO;
4155 if (!kvm->arch.vpit)
4156 goto out;
4157 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4158 break;
4159 }
52d939a0
MT		 4160 case KVM_REINJECT_CONTROL: {
4161 struct kvm_reinject_control control;
4162 r = -EFAULT;
4163 if (copy_from_user(&control, argp, sizeof(control)))
4164 goto out;
4165 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4166 break;
4167 }
d71ba788
PB		 4168 case KVM_SET_BOOT_CPU_ID:
4169 r = 0;
4170 mutex_lock(&kvm->lock);
557abc40 4171 if (kvm->created_vcpus)
d71ba788
PB		 4172 r = -EBUSY;
4173 else
4174 kvm->arch.bsp_vcpu_id = arg;
4175 mutex_unlock(&kvm->lock);
4176 break;
ffde22ac
ES		 4177 case KVM_XEN_HVM_CONFIG: {
4178 r = -EFAULT;
4179 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4180 sizeof(struct kvm_xen_hvm_config)))
4181 goto out;
4182 r = -EINVAL;
4183 if (kvm->arch.xen_hvm_config.flags)
4184 goto out;
4185 r = 0;
4186 break;
4187 }
afbcf7ab 4188 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4189 struct kvm_clock_data user_ns;
4190 u64 now_ns;
afbcf7ab
GC		 4191
4192 r = -EFAULT;
4193 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4194 goto out;
4195
4196 r = -EINVAL;
4197 if (user_ns.flags)
4198 goto out;
4199
4200 r = 0;
0bc48bea
RK		 4201 /*
4202 * TODO: userspace has to take care of races with VCPU_RUN, so
4203 * kvm_gen_update_masterclock() can be cut down to locked
4204 * pvclock_update_vm_gtod_copy().
4205 */
4206 kvm_gen_update_masterclock(kvm);
e891a32e 4207 now_ns = get_kvmclock_ns(kvm);
108b249c 4208 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4209 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4210 break;
4211 }
4212 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4213 struct kvm_clock_data user_ns;
4214 u64 now_ns;
4215
e891a32e 4216 now_ns = get_kvmclock_ns(kvm);
108b249c 4217 user_ns.clock = now_ns;
e3fd9a93 4218 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4219 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4220
4221 r = -EFAULT;
4222 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4223 goto out;
4224 r = 0;
4225 break;
4226 }
90de4a18
NA		 4227 case KVM_ENABLE_CAP: {
4228 struct kvm_enable_cap cap;
afbcf7ab 4229
90de4a18
NA		 4230 r = -EFAULT;
4231 if (copy_from_user(&cap, argp, sizeof(cap)))
4232 goto out;
4233 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4234 break;
4235 }
1fe779f8 4236 default:
ad6260da 4237 r = -ENOTTY;
1fe779f8
CO		 4238 }
4239out:
4240 return r;
4241}
4242
a16b043c 4243static void kvm_init_msr_list(void)
043405e1
CO		 4244{
4245 u32 dummy[2];
4246 unsigned i, j;
4247
62ef68bb 4248 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4249 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4250 continue;
93c4adc7
PB		 4251
4252 /*
4253 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4254 * to the guests in some cases.
93c4adc7
PB		 4255 */
4256 switch (msrs_to_save[i]) {
4257 case MSR_IA32_BNDCFGS:
4258 if (!kvm_x86_ops->mpx_supported())
4259 continue;
4260 break;
9dbe6cf9
PB		 4261 case MSR_TSC_AUX:
4262 if (!kvm_x86_ops->rdtscp_supported())
4263 continue;
4264 break;
93c4adc7
PB		 4265 default:
4266 break;
4267 }
4268
043405e1
CO		 4269 if (j < i)
4270 msrs_to_save[j] = msrs_to_save[i];
4271 j++;
4272 }
4273 num_msrs_to_save = j;
62ef68bb
PB		 4274
4275 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4276 switch (emulated_msrs[i]) {
6d396b55
PB		 4277 case MSR_IA32_SMBASE:
4278 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4279 continue;
4280 break;
62ef68bb
PB		 4281 default:
4282 break;
4283 }
4284
4285 if (j < i)
4286 emulated_msrs[j] = emulated_msrs[i];
4287 j++;
4288 }
4289 num_emulated_msrs = j;
043405e1
CO		 4290}
4291
bda9020e
MT		 4292static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4293 const void *v)
bbd9b64e 4294{
70252a10
AK		 4295 int handled = 0;
4296 int n;
4297
4298 do {
4299 n = min(len, 8);
bce87cce 4300 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4301 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4302 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4303 break;
4304 handled += n;
4305 addr += n;
4306 len -= n;
4307 v += n;
4308 } while (len);
bbd9b64e 4309
70252a10 4310 return handled;
bbd9b64e
CO		 4311}
4312
bda9020e 4313static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4314{
70252a10
AK		 4315 int handled = 0;
4316 int n;
4317
4318 do {
4319 n = min(len, 8);
bce87cce 4320 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4321 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4322 addr, n, v))
4323 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4324 break;
4325 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4326 handled += n;
4327 addr += n;
4328 len -= n;
4329 v += n;
4330 } while (len);
bbd9b64e 4331
70252a10 4332 return handled;
bbd9b64e
CO		 4333}
4334
2dafc6c2
GN		 4335static void kvm_set_segment(struct kvm_vcpu *vcpu,
4336 struct kvm_segment *var, int seg)
4337{
4338 kvm_x86_ops->set_segment(vcpu, var, seg);
4339}
4340
4341void kvm_get_segment(struct kvm_vcpu *vcpu,
4342 struct kvm_segment *var, int seg)
4343{
4344 kvm_x86_ops->get_segment(vcpu, var, seg);
4345}
4346
54987b7a
PB		 4347gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4348 struct x86_exception *exception)
02f59dc9
JR		 4349{
4350 gpa_t t_gpa;
02f59dc9
JR		 4351
4352 BUG_ON(!mmu_is_nested(vcpu));
4353
4354 /* NPT walks are always user-walks */
4355 access |= PFERR_USER_MASK;
54987b7a 4356 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4357
4358 return t_gpa;
4359}
4360
ab9ae313
AK		 4361gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4362 struct x86_exception *exception)
1871c602
GN		 4363{
4364 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4365 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4366}
4367
ab9ae313
AK		 4368 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4369 struct x86_exception *exception)
1871c602
GN		 4370{
4371 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4372 access |= PFERR_FETCH_MASK;
ab9ae313 4373 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4374}
4375
ab9ae313
AK		 4376gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4377 struct x86_exception *exception)
1871c602
GN		 4378{
4379 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4380 access |= PFERR_WRITE_MASK;
ab9ae313 4381 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4382}
4383
4384/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4385gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4386 struct x86_exception *exception)
1871c602 4387{
ab9ae313 4388 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4389}
4390
4391static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4392 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4393 struct x86_exception *exception)
bbd9b64e
CO		 4394{
4395 void *data = val;
10589a46 4396 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4397
4398 while (bytes) {
14dfe855 4399 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4400 exception);
bbd9b64e 4401 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4402 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4403 int ret;
4404
bcc55cba 4405 if (gpa == UNMAPPED_GVA)
ab9ae313 4406 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4407 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4408 offset, toread);
10589a46 4409 if (ret < 0) {
c3cd7ffa 4410 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4411 goto out;
4412 }
bbd9b64e 4413
77c2002e
IE		 4414 bytes -= toread;
4415 data += toread;
4416 addr += toread;
bbd9b64e 4417 }
10589a46 4418out:
10589a46 4419 return r;
bbd9b64e 4420}
77c2002e 4421
1871c602 4422/* used for instruction fetching */
0f65dd70
AK		 4423static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4424 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4425 struct x86_exception *exception)
1871c602 4426{
0f65dd70 4427 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4428 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4429 unsigned offset;
4430 int ret;
0f65dd70 4431
44583cba
PB		 4432 /* Inline kvm_read_guest_virt_helper for speed. */
4433 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4434 exception);
4435 if (unlikely(gpa == UNMAPPED_GVA))
4436 return X86EMUL_PROPAGATE_FAULT;
4437
4438 offset = addr & (PAGE_SIZE-1);
4439 if (WARN_ON(offset + bytes > PAGE_SIZE))
4440 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4441 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4442 offset, bytes);
44583cba
PB		 4443 if (unlikely(ret < 0))
4444 return X86EMUL_IO_NEEDED;
4445
4446 return X86EMUL_CONTINUE;
1871c602
GN		 4447}
4448
064aea77 4449int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4450 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4451 struct x86_exception *exception)
1871c602 4452{
0f65dd70 4453 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4454 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4455
1871c602 4456 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4457 exception);
1871c602 4458}
064aea77 4459EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4460
0f65dd70
AK		 4461static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4462 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4463 struct x86_exception *exception)
1871c602 4464{
0f65dd70 4465 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4466 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4467}
4468
7a036a6f
RK		 4469static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4470 unsigned long addr, void *val, unsigned int bytes)
4471{
4472 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4473 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4474
4475 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4476}
4477
6a4d7550 4478int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4479 gva_t addr, void *val,
2dafc6c2 4480 unsigned int bytes,
bcc55cba 4481 struct x86_exception *exception)
77c2002e 4482{
0f65dd70 4483 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4484 void *data = val;
4485 int r = X86EMUL_CONTINUE;
4486
4487 while (bytes) {
14dfe855
JR		 4488 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4489 PFERR_WRITE_MASK,
ab9ae313 4490 exception);
77c2002e
IE		 4491 unsigned offset = addr & (PAGE_SIZE-1);
4492 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4493 int ret;
4494
bcc55cba 4495 if (gpa == UNMAPPED_GVA)
ab9ae313 4496 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4497 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4498 if (ret < 0) {
c3cd7ffa 4499 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4500 goto out;
4501 }
4502
4503 bytes -= towrite;
4504 data += towrite;
4505 addr += towrite;
4506 }
4507out:
4508 return r;
4509}
6a4d7550 4510EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4511
0f89b207
TL		 4512static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4513 gpa_t gpa, bool write)
4514{
4515 /* For APIC access vmexit */
4516 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4517 return 1;
4518
4519 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4520 trace_vcpu_match_mmio(gva, gpa, write, true);
4521 return 1;
4522 }
4523
4524 return 0;
4525}
4526
af7cc7d1
XG		 4527static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4528 gpa_t *gpa, struct x86_exception *exception,
4529 bool write)
4530{
97d64b78
AK		 4531 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4532 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4533
be94f6b7
HH		 4534 /*
4535 * currently PKRU is only applied to ept enabled guest so
4536 * there is no pkey in EPT page table for L1 guest or EPT
4537 * shadow page table for L2 guest.
4538 */
97d64b78 4539 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4540 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4541 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4542 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4543 (gva & (PAGE_SIZE - 1));
4f022648 4544 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4545 return 1;
4546 }
4547
af7cc7d1
XG		 4548 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4549
4550 if (*gpa == UNMAPPED_GVA)
4551 return -1;
4552
0f89b207 4553 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4554}
4555
3200f405 4556int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4557 const void *val, int bytes)
bbd9b64e
CO		 4558{
4559 int ret;
4560
54bf36aa 4561 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4562 if (ret < 0)
bbd9b64e 4563 return 0;
0eb05bf2 4564 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4565 return 1;
4566}
4567
77d197b2
XG		 4568struct read_write_emulator_ops {
4569 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4570 int bytes);
4571 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4572 void *val, int bytes);
4573 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4574 int bytes, void *val);
4575 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4576 void *val, int bytes);
4577 bool write;
4578};
4579
4580static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4581{
4582 if (vcpu->mmio_read_completed) {
77d197b2 4583 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4584 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4585 vcpu->mmio_read_completed = 0;
4586 return 1;
4587 }
4588
4589 return 0;
4590}
4591
4592static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4593 void *val, int bytes)
4594{
54bf36aa 4595 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4596}
4597
4598static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4599 void *val, int bytes)
4600{
4601 return emulator_write_phys(vcpu, gpa, val, bytes);
4602}
4603
4604static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4605{
4606 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4607 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4608}
4609
4610static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4611 void *val, int bytes)
4612{
4613 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4614 return X86EMUL_IO_NEEDED;
4615}
4616
4617static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4618 void *val, int bytes)
4619{
f78146b0
AK		 4620 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4621
87da7e66 4622 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4623 return X86EMUL_CONTINUE;
4624}
4625
0fbe9b0b 4626static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4627 .read_write_prepare = read_prepare,
4628 .read_write_emulate = read_emulate,
4629 .read_write_mmio = vcpu_mmio_read,
4630 .read_write_exit_mmio = read_exit_mmio,
4631};
4632
0fbe9b0b 4633static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4634 .read_write_emulate = write_emulate,
4635 .read_write_mmio = write_mmio,
4636 .read_write_exit_mmio = write_exit_mmio,
4637 .write = true,
4638};
4639
22388a3c
XG		 4640static int emulator_read_write_onepage(unsigned long addr, void *val,
4641 unsigned int bytes,
4642 struct x86_exception *exception,
4643 struct kvm_vcpu *vcpu,
0fbe9b0b 4644 const struct read_write_emulator_ops *ops)
bbd9b64e 4645{
af7cc7d1
XG		 4646 gpa_t gpa;
4647 int handled, ret;
22388a3c 4648 bool write = ops->write;
f78146b0 4649 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4650 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4651
4652 /*
4653 * If the exit was due to a NPF we may already have a GPA.
4654 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4655 * Note, this cannot be used on string operations since string
4656 * operation using rep will only have the initial GPA from the NPF
4657 * occurred.
4658 */
4659 if (vcpu->arch.gpa_available &&
4660 emulator_can_use_gpa(ctxt) &&
4661 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4662 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4663 gpa = exception->address;
4664 goto mmio;
4665 }
10589a46 4666
22388a3c 4667 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4668
af7cc7d1 4669 if (ret < 0)
bbd9b64e 4670 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4671
4672 /* For APIC access vmexit */
af7cc7d1 4673 if (ret)
bbd9b64e
CO		 4674 goto mmio;
4675
22388a3c 4676 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4677 return X86EMUL_CONTINUE;
4678
4679mmio:
4680 /*
4681 * Is this MMIO handled locally?
4682 */
22388a3c 4683 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4684 if (handled == bytes)
bbd9b64e 4685 return X86EMUL_CONTINUE;
bbd9b64e 4686
70252a10
AK		 4687 gpa += handled;
4688 bytes -= handled;
4689 val += handled;
4690
87da7e66
XG		 4691 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4692 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4693 frag->gpa = gpa;
4694 frag->data = val;
4695 frag->len = bytes;
f78146b0 4696 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4697}
4698
52eb5a6d
XL		 4699static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4700 unsigned long addr,
22388a3c
XG		 4701 void *val, unsigned int bytes,
4702 struct x86_exception *exception,
0fbe9b0b 4703 const struct read_write_emulator_ops *ops)
bbd9b64e 4704{
0f65dd70 4705 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4706 gpa_t gpa;
4707 int rc;
4708
4709 if (ops->read_write_prepare &&
4710 ops->read_write_prepare(vcpu, val, bytes))
4711 return X86EMUL_CONTINUE;
4712
4713 vcpu->mmio_nr_fragments = 0;
0f65dd70 4714
bbd9b64e
CO		 4715 /* Crossing a page boundary? */
4716 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4717 int now;
bbd9b64e
CO		 4718
4719 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4720 rc = emulator_read_write_onepage(addr, val, now, exception,
4721 vcpu, ops);
4722
bbd9b64e
CO		 4723 if (rc != X86EMUL_CONTINUE)
4724 return rc;
4725 addr += now;
bac15531
NA		 4726 if (ctxt->mode != X86EMUL_MODE_PROT64)
4727 addr = (u32)addr;
bbd9b64e
CO		 4728 val += now;
4729 bytes -= now;
4730 }
22388a3c 4731
f78146b0
AK		 4732 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4733 vcpu, ops);
4734 if (rc != X86EMUL_CONTINUE)
4735 return rc;
4736
4737 if (!vcpu->mmio_nr_fragments)
4738 return rc;
4739
4740 gpa = vcpu->mmio_fragments[0].gpa;
4741
4742 vcpu->mmio_needed = 1;
4743 vcpu->mmio_cur_fragment = 0;
4744
87da7e66 4745 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4746 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4747 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4748 vcpu->run->mmio.phys_addr = gpa;
4749
4750 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4751}
4752
4753static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4754 unsigned long addr,
4755 void *val,
4756 unsigned int bytes,
4757 struct x86_exception *exception)
4758{
4759 return emulator_read_write(ctxt, addr, val, bytes,
4760 exception, &read_emultor);
4761}
4762
52eb5a6d 4763static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4764 unsigned long addr,
4765 const void *val,
4766 unsigned int bytes,
4767 struct x86_exception *exception)
4768{
4769 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4770 exception, &write_emultor);
bbd9b64e 4771}
bbd9b64e 4772
daea3e73
AK		 4773#define CMPXCHG_TYPE(t, ptr, old, new) \
4774 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4775
4776#ifdef CONFIG_X86_64
4777# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4778#else
4779# define CMPXCHG64(ptr, old, new) \
9749a6c0 4780 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4781#endif
4782
0f65dd70
AK		 4783static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4784 unsigned long addr,
bbd9b64e
CO		 4785 const void *old,
4786 const void *new,
4787 unsigned int bytes,
0f65dd70 4788 struct x86_exception *exception)
bbd9b64e 4789{
0f65dd70 4790 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4791 gpa_t gpa;
4792 struct page *page;
4793 char *kaddr;
4794 bool exchanged;
2bacc55c 4795
daea3e73
AK		 4796 /* guests cmpxchg8b have to be emulated atomically */
4797 if (bytes > 8 || (bytes & (bytes - 1)))
4798 goto emul_write;
10589a46 4799
daea3e73 4800 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4801
daea3e73
AK		 4802 if (gpa == UNMAPPED_GVA ||
4803 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4804 goto emul_write;
2bacc55c 4805
daea3e73
AK		 4806 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4807 goto emul_write;
72dc67a6 4808
54bf36aa 4809 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4810 if (is_error_page(page))
c19b8bd6 4811 goto emul_write;
72dc67a6 4812
8fd75e12 4813 kaddr = kmap_atomic(page);
daea3e73
AK		 4814 kaddr += offset_in_page(gpa);
4815 switch (bytes) {
4816 case 1:
4817 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4818 break;
4819 case 2:
4820 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4821 break;
4822 case 4:
4823 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4824 break;
4825 case 8:
4826 exchanged = CMPXCHG64(kaddr, old, new);
4827 break;
4828 default:
4829 BUG();
2bacc55c 4830 }
8fd75e12 4831 kunmap_atomic(kaddr);
daea3e73
AK		 4832 kvm_release_page_dirty(page);
4833
4834 if (!exchanged)
4835 return X86EMUL_CMPXCHG_FAILED;
4836
54bf36aa 4837 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4838 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4839
4840 return X86EMUL_CONTINUE;
4a5f48f6 4841
3200f405 4842emul_write:
daea3e73 4843 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4844
0f65dd70 4845 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4846}
4847
cf8f70bf
GN		 4848static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4849{
cbfc6c91 4850 int r = 0, i;
cf8f70bf 4851
cbfc6c91
WL		 4852 for (i = 0; i < vcpu->arch.pio.count; i++) {
4853 if (vcpu->arch.pio.in)
4854 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4855 vcpu->arch.pio.size, pd);
4856 else
4857 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4858 vcpu->arch.pio.port, vcpu->arch.pio.size,
4859 pd);
4860 if (r)
4861 break;
4862 pd += vcpu->arch.pio.size;
4863 }
cf8f70bf
GN		 4864 return r;
4865}
4866
6f6fbe98
XG		 4867static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4868 unsigned short port, void *val,
4869 unsigned int count, bool in)
cf8f70bf 4870{
cf8f70bf 4871 vcpu->arch.pio.port = port;
6f6fbe98 4872 vcpu->arch.pio.in = in;
7972995b 4873 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4874 vcpu->arch.pio.size = size;
4875
4876 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4877 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4878 return 1;
4879 }
4880
4881 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4882 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4883 vcpu->run->io.size = size;
4884 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4885 vcpu->run->io.count = count;
4886 vcpu->run->io.port = port;
4887
4888 return 0;
4889}
4890
6f6fbe98
XG		 4891static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4892 int size, unsigned short port, void *val,
4893 unsigned int count)
cf8f70bf 4894{
ca1d4a9e 4895 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4896 int ret;
ca1d4a9e 4897
6f6fbe98
XG		 4898 if (vcpu->arch.pio.count)
4899 goto data_avail;
cf8f70bf 4900
cbfc6c91
WL		 4901 memset(vcpu->arch.pio_data, 0, size * count);
4902
6f6fbe98
XG		 4903 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4904 if (ret) {
4905data_avail:
4906 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4907 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4908 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4909 return 1;
4910 }
4911
cf8f70bf
GN		 4912 return 0;
4913}
4914
6f6fbe98
XG		 4915static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4916 int size, unsigned short port,
4917 const void *val, unsigned int count)
4918{
4919 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4920
4921 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4922 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4923 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4924}
4925
bbd9b64e
CO		 4926static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4927{
4928 return kvm_x86_ops->get_segment_base(vcpu, seg);
4929}
4930
3cb16fe7 4931static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4932{
3cb16fe7 4933 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4934}
4935
ae6a2375 4936static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4937{
4938 if (!need_emulate_wbinvd(vcpu))
4939 return X86EMUL_CONTINUE;
4940
4941 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4942 int cpu = get_cpu();
4943
4944 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4945 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4946 wbinvd_ipi, NULL, 1);
2eec7343 4947 put_cpu();
f5f48ee1 4948 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4949 } else
4950 wbinvd();
f5f48ee1
SY		 4951 return X86EMUL_CONTINUE;
4952}
5cb56059
JS		 4953
4954int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4955{
6affcbed
KH		 4956 kvm_emulate_wbinvd_noskip(vcpu);
4957 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4958}
f5f48ee1
SY		 4959EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4960
5cb56059
JS		 4961
4962
bcaf5cc5
AK		 4963static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4964{
5cb56059 4965 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4966}
4967
52eb5a6d
XL		 4968static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4969 unsigned long *dest)
bbd9b64e 4970{
16f8a6f9 4971 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4972}
4973
52eb5a6d
XL		 4974static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4975 unsigned long value)
bbd9b64e 4976{
338dbc97 4977
717746e3 4978 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4979}
4980
52a46617 4981static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4982{
52a46617 4983 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4984}
4985
717746e3 4986static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4987{
717746e3 4988 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4989 unsigned long value;
4990
4991 switch (cr) {
4992 case 0:
4993 value = kvm_read_cr0(vcpu);
4994 break;
4995 case 2:
4996 value = vcpu->arch.cr2;
4997 break;
4998 case 3:
9f8fe504 4999 value = kvm_read_cr3(vcpu);
52a46617
GN		 5000 break;
5001 case 4:
5002 value = kvm_read_cr4(vcpu);
5003 break;
5004 case 8:
5005 value = kvm_get_cr8(vcpu);
5006 break;
5007 default:
a737f256 5008 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5009 return 0;
5010 }
5011
5012 return value;
5013}
5014
717746e3 5015static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5016{
717746e3 5017 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5018 int res = 0;
5019
52a46617
GN		 5020 switch (cr) {
5021 case 0:
49a9b07e 5022 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5023 break;
5024 case 2:
5025 vcpu->arch.cr2 = val;
5026 break;
5027 case 3:
2390218b 5028 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5029 break;
5030 case 4:
a83b29c6 5031 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5032 break;
5033 case 8:
eea1cff9 5034 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5035 break;
5036 default:
a737f256 5037 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5038 res = -1;
52a46617 5039 }
0f12244f
GN		 5040
5041 return res;
52a46617
GN		 5042}
5043
717746e3 5044static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5045{
717746e3 5046 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5047}
5048
4bff1e86 5049static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5050{
4bff1e86 5051 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5052}
5053
4bff1e86 5054static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5055{
4bff1e86 5056 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5057}
5058
1ac9d0cf
AK		 5059static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5060{
5061 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5062}
5063
5064static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5065{
5066 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5067}
5068
4bff1e86
AK		 5069static unsigned long emulator_get_cached_segment_base(
5070 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5071{
4bff1e86 5072 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5073}
5074
1aa36616
AK		 5075static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5076 struct desc_struct *desc, u32 *base3,
5077 int seg)
2dafc6c2
GN		 5078{
5079 struct kvm_segment var;
5080
4bff1e86 5081 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5082 *selector = var.selector;
2dafc6c2 5083
378a8b09
GN		 5084 if (var.unusable) {
5085 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5086 if (base3)
5087 *base3 = 0;
2dafc6c2 5088 return false;
378a8b09 5089 }
2dafc6c2
GN		 5090
5091 if (var.g)
5092 var.limit >>= 12;
5093 set_desc_limit(desc, var.limit);
5094 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5095#ifdef CONFIG_X86_64
5096 if (base3)
5097 *base3 = var.base >> 32;
5098#endif
2dafc6c2
GN		 5099 desc->type = var.type;
5100 desc->s = var.s;
5101 desc->dpl = var.dpl;
5102 desc->p = var.present;
5103 desc->avl = var.avl;
5104 desc->l = var.l;
5105 desc->d = var.db;
5106 desc->g = var.g;
5107
5108 return true;
5109}
5110
1aa36616
AK		 5111static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5112 struct desc_struct *desc, u32 base3,
5113 int seg)
2dafc6c2 5114{
4bff1e86 5115 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5116 struct kvm_segment var;
5117
1aa36616 5118 var.selector = selector;
2dafc6c2 5119 var.base = get_desc_base(desc);
5601d05b
GN		 5120#ifdef CONFIG_X86_64
5121 var.base |= ((u64)base3) << 32;
5122#endif
2dafc6c2
GN		 5123 var.limit = get_desc_limit(desc);
5124 if (desc->g)
5125 var.limit = (var.limit << 12) | 0xfff;
5126 var.type = desc->type;
2dafc6c2
GN		 5127 var.dpl = desc->dpl;
5128 var.db = desc->d;
5129 var.s = desc->s;
5130 var.l = desc->l;
5131 var.g = desc->g;
5132 var.avl = desc->avl;
5133 var.present = desc->p;
5134 var.unusable = !var.present;
5135 var.padding = 0;
5136
5137 kvm_set_segment(vcpu, &var, seg);
5138 return;
5139}
5140
717746e3
AK		 5141static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5142 u32 msr_index, u64 *pdata)
5143{
609e36d3
PB		 5144 struct msr_data msr;
5145 int r;
5146
5147 msr.index = msr_index;
5148 msr.host_initiated = false;
5149 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5150 if (r)
5151 return r;
5152
5153 *pdata = msr.data;
5154 return 0;
717746e3
AK		 5155}
5156
5157static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5158 u32 msr_index, u64 data)
5159{
8fe8ab46
WA		 5160 struct msr_data msr;
5161
5162 msr.data = data;
5163 msr.index = msr_index;
5164 msr.host_initiated = false;
5165 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5166}
5167
64d60670
PB		 5168static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5169{
5170 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5171
5172 return vcpu->arch.smbase;
5173}
5174
5175static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5176{
5177 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5178
5179 vcpu->arch.smbase = smbase;
5180}
5181
67f4d428
NA		 5182static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5183 u32 pmc)
5184{
c6702c9d 5185 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5186}
5187
222d21aa
AK		 5188static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5189 u32 pmc, u64 *pdata)
5190{
c6702c9d 5191 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5192}
5193
6c3287f7
AK		 5194static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5195{
5196 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5197}
5198
5037f6f3
AK		 5199static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5200{
5201 preempt_disable();
5197b808 5202 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5203}
5204
5205static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5206{
5207 preempt_enable();
5208}
5209
2953538e 5210static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5211 struct x86_instruction_info *info,
c4f035c6
AK		 5212 enum x86_intercept_stage stage)
5213{
2953538e 5214 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5215}
5216
0017f93a 5217static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5218 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5219{
0017f93a 5220 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5221}
5222
dd856efa
AK		 5223static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5224{
5225 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5226}
5227
5228static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5229{
5230 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5231}
5232
801806d9
NA		 5233static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5234{
5235 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5236}
5237
6ed071f0
LP		 5238static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5239{
5240 return emul_to_vcpu(ctxt)->arch.hflags;
5241}
5242
5243static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5244{
5245 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5246}
5247
0225fb50 5248static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5249 .read_gpr = emulator_read_gpr,
5250 .write_gpr = emulator_write_gpr,
1871c602 5251 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5252 .write_std = kvm_write_guest_virt_system,
7a036a6f 5253 .read_phys = kvm_read_guest_phys_system,
1871c602 5254 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5255 .read_emulated = emulator_read_emulated,
5256 .write_emulated = emulator_write_emulated,
5257 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5258 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5259 .pio_in_emulated = emulator_pio_in_emulated,
5260 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5261 .get_segment = emulator_get_segment,
5262 .set_segment = emulator_set_segment,
5951c442 5263 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5264 .get_gdt = emulator_get_gdt,
160ce1f1 5265 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5266 .set_gdt = emulator_set_gdt,
5267 .set_idt = emulator_set_idt,
52a46617
GN		 5268 .get_cr = emulator_get_cr,
5269 .set_cr = emulator_set_cr,
9c537244 5270 .cpl = emulator_get_cpl,
35aa5375
GN		 5271 .get_dr = emulator_get_dr,
5272 .set_dr = emulator_set_dr,
64d60670
PB		 5273 .get_smbase = emulator_get_smbase,
5274 .set_smbase = emulator_set_smbase,
717746e3
AK		 5275 .set_msr = emulator_set_msr,
5276 .get_msr = emulator_get_msr,
67f4d428 5277 .check_pmc = emulator_check_pmc,
222d21aa 5278 .read_pmc = emulator_read_pmc,
6c3287f7 5279 .halt = emulator_halt,
bcaf5cc5 5280 .wbinvd = emulator_wbinvd,
d6aa1000 5281 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5282 .get_fpu = emulator_get_fpu,
5283 .put_fpu = emulator_put_fpu,
c4f035c6 5284 .intercept = emulator_intercept,
bdb42f5a 5285 .get_cpuid = emulator_get_cpuid,
801806d9 5286 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5287 .get_hflags = emulator_get_hflags,
5288 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5289};
5290
95cb2295
GN		 5291static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5292{
37ccdcbe 5293 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5294 /*
5295 * an sti; sti; sequence only disable interrupts for the first
5296 * instruction. So, if the last instruction, be it emulated or
5297 * not, left the system with the INT_STI flag enabled, it
5298 * means that the last instruction is an sti. We should not
5299 * leave the flag on in this case. The same goes for mov ss
5300 */
37ccdcbe
PB		 5301 if (int_shadow & mask)
5302 mask = 0;
6addfc42 5303 if (unlikely(int_shadow || mask)) {
95cb2295 5304 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5305 if (!mask)
5306 kvm_make_request(KVM_REQ_EVENT, vcpu);
5307 }
95cb2295
GN		 5308}
5309
ef54bcfe 5310static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5311{
5312 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5313 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5314 return kvm_propagate_fault(vcpu, &ctxt->exception);
5315
5316 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5317 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5318 ctxt->exception.error_code);
54b8486f 5319 else
da9cb575 5320 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5321 return false;
54b8486f
GN		 5322}
5323
8ec4722d
MG		 5324static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5325{
adf52235 5326 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5327 int cs_db, cs_l;
5328
8ec4722d
MG		 5329 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5330
adf52235 5331 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5332 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5333
adf52235
TY		 5334 ctxt->eip = kvm_rip_read(vcpu);
5335 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5336 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5337 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5338 cs_db ? X86EMUL_MODE_PROT32 :
5339 X86EMUL_MODE_PROT16;
a584539b 5340 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5341 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5342 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5343
dd856efa 5344 init_decode_cache(ctxt);
7ae441ea 5345 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5346}
5347
71f9833b 5348int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5349{
9d74191a 5350 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5351 int ret;
5352
5353 init_emulate_ctxt(vcpu);
5354
9dac77fa
AK		 5355 ctxt->op_bytes = 2;
5356 ctxt->ad_bytes = 2;
5357 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5358 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5359
5360 if (ret != X86EMUL_CONTINUE)
5361 return EMULATE_FAIL;
5362
9dac77fa 5363 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5364 kvm_rip_write(vcpu, ctxt->eip);
5365 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5366
5367 if (irq == NMI_VECTOR)
7460fb4a 5368 vcpu->arch.nmi_pending = 0;
63995653
MG		 5369 else
5370 vcpu->arch.interrupt.pending = false;
5371
5372 return EMULATE_DONE;
5373}
5374EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5375
6d77dbfc
GN		 5376static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5377{
fc3a9157
JR		 5378 int r = EMULATE_DONE;
5379
6d77dbfc
GN		 5380 ++vcpu->stat.insn_emulation_fail;
5381 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5382 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5383 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5384 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5385 vcpu->run->internal.ndata = 0;
5386 r = EMULATE_FAIL;
5387 }
6d77dbfc 5388 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5389
5390 return r;
6d77dbfc
GN		 5391}
5392
93c05d3e 5393static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5394 bool write_fault_to_shadow_pgtable,
5395 int emulation_type)
a6f177ef 5396{
95b3cf69 5397 gpa_t gpa = cr2;
ba049e93 5398 kvm_pfn_t pfn;
a6f177ef 5399
991eebf9
GN		 5400 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5401 return false;
5402
95b3cf69
XG		 5403 if (!vcpu->arch.mmu.direct_map) {
5404 /*
5405 * Write permission should be allowed since only
5406 * write access need to be emulated.
5407 */
5408 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5409
95b3cf69
XG		 5410 /*
5411 * If the mapping is invalid in guest, let cpu retry
5412 * it to generate fault.
5413 */
5414 if (gpa == UNMAPPED_GVA)
5415 return true;
5416 }
a6f177ef 5417
8e3d9d06
XG		 5418 /*
5419 * Do not retry the unhandleable instruction if it faults on the
5420 * readonly host memory, otherwise it will goto a infinite loop:
5421 * retry instruction -> write #PF -> emulation fail -> retry
5422 * instruction -> ...
5423 */
5424 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5425
5426 /*
5427 * If the instruction failed on the error pfn, it can not be fixed,
5428 * report the error to userspace.
5429 */
5430 if (is_error_noslot_pfn(pfn))
5431 return false;
5432
5433 kvm_release_pfn_clean(pfn);
5434
5435 /* The instructions are well-emulated on direct mmu. */
5436 if (vcpu->arch.mmu.direct_map) {
5437 unsigned int indirect_shadow_pages;
5438
5439 spin_lock(&vcpu->kvm->mmu_lock);
5440 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5441 spin_unlock(&vcpu->kvm->mmu_lock);
5442
5443 if (indirect_shadow_pages)
5444 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5445
a6f177ef 5446 return true;
8e3d9d06 5447 }
a6f177ef 5448
95b3cf69
XG		 5449 /*
5450 * if emulation was due to access to shadowed page table
5451 * and it failed try to unshadow page and re-enter the
5452 * guest to let CPU execute the instruction.
5453 */
5454 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5455
5456 /*
5457 * If the access faults on its page table, it can not
5458 * be fixed by unprotecting shadow page and it should
5459 * be reported to userspace.
5460 */
5461 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5462}
5463
1cb3f3ae
XG		 5464static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5465 unsigned long cr2, int emulation_type)
5466{
5467 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5468 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5469
5470 last_retry_eip = vcpu->arch.last_retry_eip;
5471 last_retry_addr = vcpu->arch.last_retry_addr;
5472
5473 /*
5474 * If the emulation is caused by #PF and it is non-page_table
5475 * writing instruction, it means the VM-EXIT is caused by shadow
5476 * page protected, we can zap the shadow page and retry this
5477 * instruction directly.
5478 *
5479 * Note: if the guest uses a non-page-table modifying instruction
5480 * on the PDE that points to the instruction, then we will unmap
5481 * the instruction and go to an infinite loop. So, we cache the
5482 * last retried eip and the last fault address, if we meet the eip
5483 * and the address again, we can break out of the potential infinite
5484 * loop.
5485 */
5486 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5487
5488 if (!(emulation_type & EMULTYPE_RETRY))
5489 return false;
5490
5491 if (x86_page_table_writing_insn(ctxt))
5492 return false;
5493
5494 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5495 return false;
5496
5497 vcpu->arch.last_retry_eip = ctxt->eip;
5498 vcpu->arch.last_retry_addr = cr2;
5499
5500 if (!vcpu->arch.mmu.direct_map)
5501 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5502
22368028 5503 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5504
5505 return true;
5506}
5507
716d51ab
GN		 5508static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5509static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5510
64d60670 5511static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5512{
64d60670 5513 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5514 /* This is a good place to trace that we are exiting SMM. */
5515 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5516
c43203ca
PB		 5517 /* Process a latched INIT or SMI, if any. */
5518 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5519 }
699023e2
PB		 5520
5521 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5522}
5523
5524static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5525{
5526 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5527
a584539b 5528 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5529
5530 if (changed & HF_SMM_MASK)
5531 kvm_smm_changed(vcpu);
a584539b
PB		 5532}
5533
4a1e10d5
PB		 5534static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5535 unsigned long *db)
5536{
5537 u32 dr6 = 0;
5538 int i;
5539 u32 enable, rwlen;
5540
5541 enable = dr7;
5542 rwlen = dr7 >> 16;
5543 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5544 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5545 dr6 |= (1 << i);
5546 return dr6;
5547}
5548
c8401dda 5549static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5550{
5551 struct kvm_run *kvm_run = vcpu->run;
5552
c8401dda
PB		 5553 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5554 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5555 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5556 kvm_run->debug.arch.exception = DB_VECTOR;
5557 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5558 *r = EMULATE_USER_EXIT;
5559 } else {
5560 /*
5561 * "Certain debug exceptions may clear bit 0-3. The
5562 * remaining contents of the DR6 register are never
5563 * cleared by the processor".
5564 */
5565 vcpu->arch.dr6 &= ~15;
5566 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5567 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5568 }
5569}
5570
6affcbed
KH		 5571int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5572{
5573 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5574 int r = EMULATE_DONE;
5575
5576 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5577
5578 /*
5579 * rflags is the old, "raw" value of the flags. The new value has
5580 * not been saved yet.
5581 *
5582 * This is correct even for TF set by the guest, because "the
5583 * processor will not generate this exception after the instruction
5584 * that sets the TF flag".
5585 */
5586 if (unlikely(rflags & X86_EFLAGS_TF))
5587 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5588 return r == EMULATE_DONE;
5589}
5590EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5591
4a1e10d5
PB		 5592static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5593{
4a1e10d5
PB		 5594 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5595 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5596 struct kvm_run *kvm_run = vcpu->run;
5597 unsigned long eip = kvm_get_linear_rip(vcpu);
5598 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5599 vcpu->arch.guest_debug_dr7,
5600 vcpu->arch.eff_db);
5601
5602 if (dr6 != 0) {
6f43ed01 5603 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5604 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5605 kvm_run->debug.arch.exception = DB_VECTOR;
5606 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5607 *r = EMULATE_USER_EXIT;
5608 return true;
5609 }
5610 }
5611
4161a569
NA		 5612 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5613 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5614 unsigned long eip = kvm_get_linear_rip(vcpu);
5615 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5616 vcpu->arch.dr7,
5617 vcpu->arch.db);
5618
5619 if (dr6 != 0) {
5620 vcpu->arch.dr6 &= ~15;
6f43ed01 5621 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5622 kvm_queue_exception(vcpu, DB_VECTOR);
5623 *r = EMULATE_DONE;
5624 return true;
5625 }
5626 }
5627
5628 return false;
5629}
5630
51d8b661
AP		 5631int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5632 unsigned long cr2,
dc25e89e
AP		 5633 int emulation_type,
5634 void *insn,
5635 int insn_len)
bbd9b64e 5636{
95cb2295 5637 int r;
9d74191a 5638 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5639 bool writeback = true;
93c05d3e 5640 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5641
93c05d3e
XG		 5642 /*
5643 * Clear write_fault_to_shadow_pgtable here to ensure it is
5644 * never reused.
5645 */
5646 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5647 kvm_clear_exception_queue(vcpu);
8d7d8102 5648
571008da 5649 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5650 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5651
5652 /*
5653 * We will reenter on the same instruction since
5654 * we do not set complete_userspace_io. This does not
5655 * handle watchpoints yet, those would be handled in
5656 * the emulate_ops.
5657 */
5658 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5659 return r;
5660
9d74191a
TY		 5661 ctxt->interruptibility = 0;
5662 ctxt->have_exception = false;
e0ad0b47 5663 ctxt->exception.vector = -1;
9d74191a 5664 ctxt->perm_ok = false;
bbd9b64e 5665
b51e974f 5666 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5667
9d74191a 5668 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5669
e46479f8 5670 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5671 ++vcpu->stat.insn_emulation;
1d2887e2 5672 if (r != EMULATION_OK) {
4005996e
AK		 5673 if (emulation_type & EMULTYPE_TRAP_UD)
5674 return EMULATE_FAIL;
991eebf9
GN		 5675 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5676 emulation_type))
bbd9b64e 5677 return EMULATE_DONE;
6d77dbfc
GN		 5678 if (emulation_type & EMULTYPE_SKIP)
5679 return EMULATE_FAIL;
5680 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5681 }
5682 }
5683
ba8afb6b 5684 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5685 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5686 if (ctxt->eflags & X86_EFLAGS_RF)
5687 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5688 return EMULATE_DONE;
5689 }
5690
1cb3f3ae
XG		 5691 if (retry_instruction(ctxt, cr2, emulation_type))
5692 return EMULATE_DONE;
5693
7ae441ea 5694 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5695 changes registers values during IO operation */
7ae441ea
GN		 5696 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5697 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5698 emulator_invalidate_register_cache(ctxt);
7ae441ea 5699 }
4d2179e1 5700
5cd21917 5701restart:
0f89b207
TL		 5702 /* Save the faulting GPA (cr2) in the address field */
5703 ctxt->exception.address = cr2;
5704
9d74191a 5705 r = x86_emulate_insn(ctxt);
bbd9b64e 5706
775fde86
JR		 5707 if (r == EMULATION_INTERCEPTED)
5708 return EMULATE_DONE;
5709
d2ddd1c4 5710 if (r == EMULATION_FAILED) {
991eebf9
GN		 5711 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5712 emulation_type))
c3cd7ffa
GN		 5713 return EMULATE_DONE;
5714
6d77dbfc 5715 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5716 }
5717
9d74191a 5718 if (ctxt->have_exception) {
d2ddd1c4 5719 r = EMULATE_DONE;
ef54bcfe
PB		 5720 if (inject_emulated_exception(vcpu))
5721 return r;
d2ddd1c4 5722 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5723 if (!vcpu->arch.pio.in) {
5724 /* FIXME: return into emulator if single-stepping. */
3457e419 5725 vcpu->arch.pio.count = 0;
0912c977 5726 } else {
7ae441ea 5727 writeback = false;
716d51ab
GN		 5728 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5729 }
ac0a48c3 5730 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5731 } else if (vcpu->mmio_needed) {
5732 if (!vcpu->mmio_is_write)
5733 writeback = false;
ac0a48c3 5734 r = EMULATE_USER_EXIT;
716d51ab 5735 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5736 } else if (r == EMULATION_RESTART)
5cd21917 5737 goto restart;
d2ddd1c4
GN		 5738 else
5739 r = EMULATE_DONE;
f850e2e6 5740
7ae441ea 5741 if (writeback) {
6addfc42 5742 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5743 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5744 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5745 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5746 if (r == EMULATE_DONE &&
5747 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5748 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5749 if (!ctxt->have_exception ||
5750 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5751 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5752
5753 /*
5754 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5755 * do nothing, and it will be requested again as soon as
5756 * the shadow expires. But we still need to check here,
5757 * because POPF has no interrupt shadow.
5758 */
5759 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5760 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5761 } else
5762 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5763
5764 return r;
de7d789a 5765}
51d8b661 5766EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5767
cf8f70bf 5768int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5769{
cf8f70bf 5770 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5771 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5772 size, port, &val, 1);
cf8f70bf 5773 /* do not return to emulator after return from userspace */
7972995b 5774 vcpu->arch.pio.count = 0;
de7d789a
CO		 5775 return ret;
5776}
cf8f70bf 5777EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5778
8370c3d0
TL		 5779static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5780{
5781 unsigned long val;
5782
5783 /* We should only ever be called with arch.pio.count equal to 1 */
5784 BUG_ON(vcpu->arch.pio.count != 1);
5785
5786 /* For size less than 4 we merge, else we zero extend */
5787 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5788 : 0;
5789
5790 /*
5791 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5792 * the copy and tracing
5793 */
5794 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5795 vcpu->arch.pio.port, &val, 1);
5796 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5797
5798 return 1;
5799}
5800
5801int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5802{
5803 unsigned long val;
5804 int ret;
5805
5806 /* For size less than 4 we merge, else we zero extend */
5807 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5808
5809 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5810 &val, 1);
5811 if (ret) {
5812 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5813 return ret;
5814 }
5815
5816 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5817
5818 return 0;
5819}
5820EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5821
251a5fd6 5822static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5823{
0a3aee0d 5824 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5825 return 0;
8cfdc000
ZA		 5826}
5827
5828static void tsc_khz_changed(void *data)
c8076604 5829{
8cfdc000
ZA		 5830 struct cpufreq_freqs *freq = data;
5831 unsigned long khz = 0;
5832
5833 if (data)
5834 khz = freq->new;
5835 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5836 khz = cpufreq_quick_get(raw_smp_processor_id());
5837 if (!khz)
5838 khz = tsc_khz;
0a3aee0d 5839 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5840}
5841
c8076604
GH		 5842static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5843 void *data)
5844{
5845 struct cpufreq_freqs *freq = data;
5846 struct kvm *kvm;
5847 struct kvm_vcpu *vcpu;
5848 int i, send_ipi = 0;
5849
8cfdc000
ZA		 5850 /*
5851 * We allow guests to temporarily run on slowing clocks,
5852 * provided we notify them after, or to run on accelerating
5853 * clocks, provided we notify them before. Thus time never
5854 * goes backwards.
5855 *
5856 * However, we have a problem. We can't atomically update
5857 * the frequency of a given CPU from this function; it is
5858 * merely a notifier, which can be called from any CPU.
5859 * Changing the TSC frequency at arbitrary points in time
5860 * requires a recomputation of local variables related to
5861 * the TSC for each VCPU. We must flag these local variables
5862 * to be updated and be sure the update takes place with the
5863 * new frequency before any guests proceed.
5864 *
5865 * Unfortunately, the combination of hotplug CPU and frequency
5866 * change creates an intractable locking scenario; the order
5867 * of when these callouts happen is undefined with respect to
5868 * CPU hotplug, and they can race with each other. As such,
5869 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5870 * undefined; you can actually have a CPU frequency change take
5871 * place in between the computation of X and the setting of the
5872 * variable. To protect against this problem, all updates of
5873 * the per_cpu tsc_khz variable are done in an interrupt
5874 * protected IPI, and all callers wishing to update the value
5875 * must wait for a synchronous IPI to complete (which is trivial
5876 * if the caller is on the CPU already). This establishes the
5877 * necessary total order on variable updates.
5878 *
5879 * Note that because a guest time update may take place
5880 * anytime after the setting of the VCPU's request bit, the
5881 * correct TSC value must be set before the request. However,
5882 * to ensure the update actually makes it to any guest which
5883 * starts running in hardware virtualization between the set
5884 * and the acquisition of the spinlock, we must also ping the
5885 * CPU after setting the request bit.
5886 *
5887 */
5888
c8076604
GH		 5889 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5890 return 0;
5891 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5892 return 0;
8cfdc000
ZA		 5893
5894 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5895
2f303b74 5896 spin_lock(&kvm_lock);
c8076604 5897 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5898 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5899 if (vcpu->cpu != freq->cpu)
5900 continue;
c285545f 5901 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5902 if (vcpu->cpu != smp_processor_id())
8cfdc000 5903 send_ipi = 1;
c8076604
GH		 5904 }
5905 }
2f303b74 5906 spin_unlock(&kvm_lock);
c8076604
GH		 5907
5908 if (freq->old < freq->new && send_ipi) {
5909 /*
5910 * We upscale the frequency. Must make the guest
5911 * doesn't see old kvmclock values while running with
5912 * the new frequency, otherwise we risk the guest sees
5913 * time go backwards.
5914 *
5915 * In case we update the frequency for another cpu
5916 * (which might be in guest context) send an interrupt
5917 * to kick the cpu out of guest context. Next time
5918 * guest context is entered kvmclock will be updated,
5919 * so the guest will not see stale values.
5920 */
8cfdc000 5921 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5922 }
5923 return 0;
5924}
5925
5926static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5927 .notifier_call = kvmclock_cpufreq_notifier
5928};
5929
251a5fd6 5930static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5931{
251a5fd6
SAS		 5932 tsc_khz_changed(NULL);
5933 return 0;
8cfdc000
ZA		 5934}
5935
b820cc0c
ZA		 5936static void kvm_timer_init(void)
5937{
c285545f 5938 max_tsc_khz = tsc_khz;
460dd42e 5939
b820cc0c 5940 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5941#ifdef CONFIG_CPU_FREQ
5942 struct cpufreq_policy policy;
758f588d
BP		 5943 int cpu;
5944
c285545f 5945 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5946 cpu = get_cpu();
5947 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5948 if (policy.cpuinfo.max_freq)
5949 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5950 put_cpu();
c285545f 5951#endif
b820cc0c
ZA		 5952 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5953 CPUFREQ_TRANSITION_NOTIFIER);
5954 }
c285545f 5955 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5956
73c1b41e 5957 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5958 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5959}
5960
ff9d07a0
ZY		 5961static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5962
f5132b01 5963int kvm_is_in_guest(void)
ff9d07a0 5964{
086c9855 5965 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5966}
5967
5968static int kvm_is_user_mode(void)
5969{
5970 int user_mode = 3;
dcf46b94 5971
086c9855
AS		 5972 if (__this_cpu_read(current_vcpu))
5973 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5974
ff9d07a0
ZY		 5975 return user_mode != 0;
5976}
5977
5978static unsigned long kvm_get_guest_ip(void)
5979{
5980 unsigned long ip = 0;
dcf46b94 5981
086c9855
AS		 5982 if (__this_cpu_read(current_vcpu))
5983 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5984
ff9d07a0
ZY		 5985 return ip;
5986}
5987
5988static struct perf_guest_info_callbacks kvm_guest_cbs = {
5989 .is_in_guest = kvm_is_in_guest,
5990 .is_user_mode = kvm_is_user_mode,
5991 .get_guest_ip = kvm_get_guest_ip,
5992};
5993
5994void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5995{
086c9855 5996 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5997}
5998EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5999
6000void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6001{
086c9855 6002 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6003}
6004EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6005
ce88decf
XG		 6006static void kvm_set_mmio_spte_mask(void)
6007{
6008 u64 mask;
6009 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6010
6011 /*
6012 * Set the reserved bits and the present bit of an paging-structure
6013 * entry to generate page fault with PFER.RSV = 1.
6014 */
885032b9 6015 /* Mask the reserved physical address bits. */
d1431483 6016 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6017
885032b9 6018 /* Set the present bit. */
ce88decf
XG		 6019 mask |= 1ull;
6020
6021#ifdef CONFIG_X86_64
6022 /*
6023 * If reserved bit is not supported, clear the present bit to disable
6024 * mmio page fault.
6025 */
6026 if (maxphyaddr == 52)
6027 mask &= ~1ull;
6028#endif
6029
dcdca5fe 6030 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6031}
6032
16e8d74d
MT		 6033#ifdef CONFIG_X86_64
6034static void pvclock_gtod_update_fn(struct work_struct *work)
6035{
d828199e
MT		 6036 struct kvm *kvm;
6037
6038 struct kvm_vcpu *vcpu;
6039 int i;
6040
2f303b74 6041 spin_lock(&kvm_lock);
d828199e
MT		 6042 list_for_each_entry(kvm, &vm_list, vm_list)
6043 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6044 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6045 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6046 spin_unlock(&kvm_lock);
16e8d74d
MT		 6047}
6048
6049static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6050
6051/*
6052 * Notification about pvclock gtod data update.
6053 */
6054static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6055 void *priv)
6056{
6057 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6058 struct timekeeper *tk = priv;
6059
6060 update_pvclock_gtod(tk);
6061
6062 /* disable master clock if host does not trust, or does not
6063 * use, TSC clocksource
6064 */
6065 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6066 atomic_read(&kvm_guest_has_master_clock) != 0)
6067 queue_work(system_long_wq, &pvclock_gtod_work);
6068
6069 return 0;
6070}
6071
6072static struct notifier_block pvclock_gtod_notifier = {
6073 .notifier_call = pvclock_gtod_notify,
6074};
6075#endif
6076
f8c16bba 6077int kvm_arch_init(void *opaque)
043405e1 6078{
b820cc0c 6079 int r;
6b61edf7 6080 struct kvm_x86_ops *ops = opaque;
f8c16bba 6081
f8c16bba
ZX		 6082 if (kvm_x86_ops) {
6083 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6084 r = -EEXIST;
6085 goto out;
f8c16bba
ZX		 6086 }
6087
6088 if (!ops->cpu_has_kvm_support()) {
6089 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6090 r = -EOPNOTSUPP;
6091 goto out;
f8c16bba
ZX		 6092 }
6093 if (ops->disabled_by_bios()) {
6094 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6095 r = -EOPNOTSUPP;
6096 goto out;
f8c16bba
ZX		 6097 }
6098
013f6a5d
MT		 6099 r = -ENOMEM;
6100 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6101 if (!shared_msrs) {
6102 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6103 goto out;
6104 }
6105
97db56ce
AK		 6106 r = kvm_mmu_module_init();
6107 if (r)
013f6a5d 6108 goto out_free_percpu;
97db56ce 6109
ce88decf 6110 kvm_set_mmio_spte_mask();
97db56ce 6111
f8c16bba 6112 kvm_x86_ops = ops;
920c8377 6113
7b52345e 6114 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6115 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6116 PT_PRESENT_MASK, 0);
b820cc0c 6117 kvm_timer_init();
c8076604 6118
ff9d07a0
ZY		 6119 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6120
d366bf7e 6121 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6122 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6123
c5cc421b 6124 kvm_lapic_init();
16e8d74d
MT		 6125#ifdef CONFIG_X86_64
6126 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6127#endif
6128
f8c16bba 6129 return 0;
56c6d28a 6130
013f6a5d
MT		 6131out_free_percpu:
6132 free_percpu(shared_msrs);
56c6d28a 6133out:
56c6d28a 6134 return r;
043405e1 6135}
8776e519 6136
f8c16bba
ZX		 6137void kvm_arch_exit(void)
6138{
cef84c30 6139 kvm_lapic_exit();
ff9d07a0
ZY		 6140 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6141
888d256e
JK		 6142 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6143 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6144 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6145 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6146#ifdef CONFIG_X86_64
6147 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6148#endif
f8c16bba 6149 kvm_x86_ops = NULL;
56c6d28a 6150 kvm_mmu_module_exit();
013f6a5d 6151 free_percpu(shared_msrs);
56c6d28a 6152}
f8c16bba 6153
5cb56059 6154int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6155{
6156 ++vcpu->stat.halt_exits;
35754c98 6157 if (lapic_in_kernel(vcpu)) {
a4535290 6158 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6159 return 1;
6160 } else {
6161 vcpu->run->exit_reason = KVM_EXIT_HLT;
6162 return 0;
6163 }
6164}
5cb56059
JS		 6165EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6166
6167int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6168{
6affcbed
KH		 6169 int ret = kvm_skip_emulated_instruction(vcpu);
6170 /*
6171 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6172 * KVM_EXIT_DEBUG here.
6173 */
6174 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6175}
8776e519
HB		 6176EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6177
8ef81a9a 6178#ifdef CONFIG_X86_64
55dd00a7
MT		 6179static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6180 unsigned long clock_type)
6181{
6182 struct kvm_clock_pairing clock_pairing;
6183 struct timespec ts;
80fbd89c 6184 u64 cycle;
55dd00a7
MT		 6185 int ret;
6186
6187 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6188 return -KVM_EOPNOTSUPP;
6189
6190 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6191 return -KVM_EOPNOTSUPP;
6192
6193 clock_pairing.sec = ts.tv_sec;
6194 clock_pairing.nsec = ts.tv_nsec;
6195 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6196 clock_pairing.flags = 0;
6197
6198 ret = 0;
6199 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6200 sizeof(struct kvm_clock_pairing)))
6201 ret = -KVM_EFAULT;
6202
6203 return ret;
6204}
8ef81a9a 6205#endif
55dd00a7 6206
6aef266c
SV		 6207/*
6208 * kvm_pv_kick_cpu_op: Kick a vcpu.
6209 *
6210 * @apicid - apicid of vcpu to be kicked.
6211 */
6212static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6213{
24d2166b 6214 struct kvm_lapic_irq lapic_irq;
6aef266c 6215
24d2166b
R		 6216 lapic_irq.shorthand = 0;
6217 lapic_irq.dest_mode = 0;
6218 lapic_irq.dest_id = apicid;
93bbf0b8 6219 lapic_irq.msi_redir_hint = false;
6aef266c 6220
24d2166b 6221 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6222 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6223}
6224
d62caabb
AS		 6225void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6226{
6227 vcpu->arch.apicv_active = false;
6228 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6229}
6230
8776e519
HB		 6231int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6232{
6233 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6234 int op_64_bit, r;
8776e519 6235
6affcbed 6236 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6237
55cd8e5a
GN		 6238 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6239 return kvm_hv_hypercall(vcpu);
6240
5fdbf976
MT		 6241 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6242 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6243 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6244 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6245 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6246
229456fc 6247 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6248
a449c7aa
NA		 6249 op_64_bit = is_64_bit_mode(vcpu);
6250 if (!op_64_bit) {
8776e519
HB		 6251 nr &= 0xFFFFFFFF;
6252 a0 &= 0xFFFFFFFF;
6253 a1 &= 0xFFFFFFFF;
6254 a2 &= 0xFFFFFFFF;
6255 a3 &= 0xFFFFFFFF;
6256 }
6257
07708c4a
JK		 6258 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6259 ret = -KVM_EPERM;
6260 goto out;
6261 }
6262
8776e519 6263 switch (nr) {
b93463aa
AK		 6264 case KVM_HC_VAPIC_POLL_IRQ:
6265 ret = 0;
6266 break;
6aef266c
SV		 6267 case KVM_HC_KICK_CPU:
6268 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6269 ret = 0;
6270 break;
8ef81a9a 6271#ifdef CONFIG_X86_64
55dd00a7
MT		 6272 case KVM_HC_CLOCK_PAIRING:
6273 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6274 break;
8ef81a9a 6275#endif
8776e519
HB		 6276 default:
6277 ret = -KVM_ENOSYS;
6278 break;
6279 }
07708c4a 6280out:
a449c7aa
NA		 6281 if (!op_64_bit)
6282 ret = (u32)ret;
5fdbf976 6283 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6284 ++vcpu->stat.hypercalls;
2f333bcb 6285 return r;
8776e519
HB		 6286}
6287EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6288
b6785def 6289static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6290{
d6aa1000 6291 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6292 char instruction[3];
5fdbf976 6293 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6294
8776e519 6295 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6296
ce2e852e
DV		 6297 return emulator_write_emulated(ctxt, rip, instruction, 3,
6298 &ctxt->exception);
8776e519
HB		 6299}
6300
851ba692 6301static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6302{
782d422b
MG		 6303 return vcpu->run->request_interrupt_window &&
6304 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6305}
6306
851ba692 6307static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6308{
851ba692
AK		 6309 struct kvm_run *kvm_run = vcpu->run;
6310
91586a3b 6311 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6312 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6313 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6314 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6315 kvm_run->ready_for_interrupt_injection =
6316 pic_in_kernel(vcpu->kvm) ||
782d422b 6317 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6318}
6319
95ba8273
GN		 6320static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6321{
6322 int max_irr, tpr;
6323
6324 if (!kvm_x86_ops->update_cr8_intercept)
6325 return;
6326
bce87cce 6327 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6328 return;
6329
d62caabb
AS		 6330 if (vcpu->arch.apicv_active)
6331 return;
6332
8db3baa2
GN		 6333 if (!vcpu->arch.apic->vapic_addr)
6334 max_irr = kvm_lapic_find_highest_irr(vcpu);
6335 else
6336 max_irr = -1;
95ba8273
GN		 6337
6338 if (max_irr != -1)
6339 max_irr >>= 4;
6340
6341 tpr = kvm_lapic_get_cr8(vcpu);
6342
6343 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6344}
6345
b6b8a145 6346static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6347{
b6b8a145
JK		 6348 int r;
6349
95ba8273 6350 /* try to reinject previous events if any */
b59bb7bd 6351 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6352 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6353 vcpu->arch.exception.has_error_code,
6354 vcpu->arch.exception.error_code);
d6e8c854
NA		 6355
6356 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6357 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6358 X86_EFLAGS_RF);
6359
6bdf0662
NA		 6360 if (vcpu->arch.exception.nr == DB_VECTOR &&
6361 (vcpu->arch.dr7 & DR7_GD)) {
6362 vcpu->arch.dr7 &= ~DR7_GD;
6363 kvm_update_dr7(vcpu);
6364 }
6365
cfcd20e5 6366 kvm_x86_ops->queue_exception(vcpu);
b6b8a145 6367 return 0;
b59bb7bd
GN		 6368 }
6369
95ba8273
GN		 6370 if (vcpu->arch.nmi_injected) {
6371 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6372 return 0;
95ba8273
GN		 6373 }
6374
6375 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6376 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6377 return 0;
6378 }
6379
6380 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6381 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6382 if (r != 0)
6383 return r;
95ba8273
GN		 6384 }
6385
6386 /* try to inject new event if pending */
c43203ca
PB		 6387 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6388 vcpu->arch.smi_pending = false;
ee2cd4b7 6389 enter_smm(vcpu);
c43203ca 6390 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6391 --vcpu->arch.nmi_pending;
6392 vcpu->arch.nmi_injected = true;
6393 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6394 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6395 /*
6396 * Because interrupts can be injected asynchronously, we are
6397 * calling check_nested_events again here to avoid a race condition.
6398 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6399 * proposal and current concerns. Perhaps we should be setting
6400 * KVM_REQ_EVENT only on certain events and not unconditionally?
6401 */
6402 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6403 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6404 if (r != 0)
6405 return r;
6406 }
95ba8273 6407 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6408 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6409 false);
6410 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6411 }
6412 }
ee2cd4b7 6413
b6b8a145 6414 return 0;
95ba8273
GN		 6415}
6416
7460fb4a
AK		 6417static void process_nmi(struct kvm_vcpu *vcpu)
6418{
6419 unsigned limit = 2;
6420
6421 /*
6422 * x86 is limited to one NMI running, and one NMI pending after it.
6423 * If an NMI is already in progress, limit further NMIs to just one.
6424 * Otherwise, allow two (and we'll inject the first one immediately).
6425 */
6426 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6427 limit = 1;
6428
6429 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6430 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6431 kvm_make_request(KVM_REQ_EVENT, vcpu);
6432}
6433
660a5d51
PB		 6434#define put_smstate(type, buf, offset, val) \
6435 *(type *)((buf) + (offset) - 0x7e00) = val
6436
ee2cd4b7 6437static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6438{
6439 u32 flags = 0;
6440 flags |= seg->g << 23;
6441 flags |= seg->db << 22;
6442 flags |= seg->l << 21;
6443 flags |= seg->avl << 20;
6444 flags |= seg->present << 15;
6445 flags |= seg->dpl << 13;
6446 flags |= seg->s << 12;
6447 flags |= seg->type << 8;
6448 return flags;
6449}
6450
ee2cd4b7 6451static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6452{
6453 struct kvm_segment seg;
6454 int offset;
6455
6456 kvm_get_segment(vcpu, &seg, n);
6457 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6458
6459 if (n < 3)
6460 offset = 0x7f84 + n * 12;
6461 else
6462 offset = 0x7f2c + (n - 3) * 12;
6463
6464 put_smstate(u32, buf, offset + 8, seg.base);
6465 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6466 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6467}
6468
efbb288a 6469#ifdef CONFIG_X86_64
ee2cd4b7 6470static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6471{
6472 struct kvm_segment seg;
6473 int offset;
6474 u16 flags;
6475
6476 kvm_get_segment(vcpu, &seg, n);
6477 offset = 0x7e00 + n * 16;
6478
ee2cd4b7 6479 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6480 put_smstate(u16, buf, offset, seg.selector);
6481 put_smstate(u16, buf, offset + 2, flags);
6482 put_smstate(u32, buf, offset + 4, seg.limit);
6483 put_smstate(u64, buf, offset + 8, seg.base);
6484}
efbb288a 6485#endif
660a5d51 6486
ee2cd4b7 6487static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6488{
6489 struct desc_ptr dt;
6490 struct kvm_segment seg;
6491 unsigned long val;
6492 int i;
6493
6494 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6495 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6496 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6497 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6498
6499 for (i = 0; i < 8; i++)
6500 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6501
6502 kvm_get_dr(vcpu, 6, &val);
6503 put_smstate(u32, buf, 0x7fcc, (u32)val);
6504 kvm_get_dr(vcpu, 7, &val);
6505 put_smstate(u32, buf, 0x7fc8, (u32)val);
6506
6507 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6508 put_smstate(u32, buf, 0x7fc4, seg.selector);
6509 put_smstate(u32, buf, 0x7f64, seg.base);
6510 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6511 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6512
6513 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6514 put_smstate(u32, buf, 0x7fc0, seg.selector);
6515 put_smstate(u32, buf, 0x7f80, seg.base);
6516 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6517 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6518
6519 kvm_x86_ops->get_gdt(vcpu, &dt);
6520 put_smstate(u32, buf, 0x7f74, dt.address);
6521 put_smstate(u32, buf, 0x7f70, dt.size);
6522
6523 kvm_x86_ops->get_idt(vcpu, &dt);
6524 put_smstate(u32, buf, 0x7f58, dt.address);
6525 put_smstate(u32, buf, 0x7f54, dt.size);
6526
6527 for (i = 0; i < 6; i++)
ee2cd4b7 6528 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6529
6530 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6531
6532 /* revision id */
6533 put_smstate(u32, buf, 0x7efc, 0x00020000);
6534 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6535}
6536
ee2cd4b7 6537static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6538{
6539#ifdef CONFIG_X86_64
6540 struct desc_ptr dt;
6541 struct kvm_segment seg;
6542 unsigned long val;
6543 int i;
6544
6545 for (i = 0; i < 16; i++)
6546 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6547
6548 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6549 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6550
6551 kvm_get_dr(vcpu, 6, &val);
6552 put_smstate(u64, buf, 0x7f68, val);
6553 kvm_get_dr(vcpu, 7, &val);
6554 put_smstate(u64, buf, 0x7f60, val);
6555
6556 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6557 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6558 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6559
6560 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6561
6562 /* revision id */
6563 put_smstate(u32, buf, 0x7efc, 0x00020064);
6564
6565 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6566
6567 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6568 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6569 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6570 put_smstate(u32, buf, 0x7e94, seg.limit);
6571 put_smstate(u64, buf, 0x7e98, seg.base);
6572
6573 kvm_x86_ops->get_idt(vcpu, &dt);
6574 put_smstate(u32, buf, 0x7e84, dt.size);
6575 put_smstate(u64, buf, 0x7e88, dt.address);
6576
6577 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6578 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6579 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6580 put_smstate(u32, buf, 0x7e74, seg.limit);
6581 put_smstate(u64, buf, 0x7e78, seg.base);
6582
6583 kvm_x86_ops->get_gdt(vcpu, &dt);
6584 put_smstate(u32, buf, 0x7e64, dt.size);
6585 put_smstate(u64, buf, 0x7e68, dt.address);
6586
6587 for (i = 0; i < 6; i++)
ee2cd4b7 6588 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6589#else
6590 WARN_ON_ONCE(1);
6591#endif
6592}
6593
ee2cd4b7 6594static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6595{
660a5d51 6596 struct kvm_segment cs, ds;
18c3626e 6597 struct desc_ptr dt;
660a5d51
PB		 6598 char buf[512];
6599 u32 cr0;
6600
660a5d51
PB		 6601 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6602 vcpu->arch.hflags |= HF_SMM_MASK;
6603 memset(buf, 0, 512);
6604 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6605 enter_smm_save_state_64(vcpu, buf);
660a5d51 6606 else
ee2cd4b7 6607 enter_smm_save_state_32(vcpu, buf);
660a5d51 6608
54bf36aa 6609 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6610
6611 if (kvm_x86_ops->get_nmi_mask(vcpu))
6612 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6613 else
6614 kvm_x86_ops->set_nmi_mask(vcpu, true);
6615
6616 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6617 kvm_rip_write(vcpu, 0x8000);
6618
6619 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6620 kvm_x86_ops->set_cr0(vcpu, cr0);
6621 vcpu->arch.cr0 = cr0;
6622
6623 kvm_x86_ops->set_cr4(vcpu, 0);
6624
18c3626e
PB		 6625 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6626 dt.address = dt.size = 0;
6627 kvm_x86_ops->set_idt(vcpu, &dt);
6628
660a5d51
PB		 6629 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6630
6631 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6632 cs.base = vcpu->arch.smbase;
6633
6634 ds.selector = 0;
6635 ds.base = 0;
6636
6637 cs.limit = ds.limit = 0xffffffff;
6638 cs.type = ds.type = 0x3;
6639 cs.dpl = ds.dpl = 0;
6640 cs.db = ds.db = 0;
6641 cs.s = ds.s = 1;
6642 cs.l = ds.l = 0;
6643 cs.g = ds.g = 1;
6644 cs.avl = ds.avl = 0;
6645 cs.present = ds.present = 1;
6646 cs.unusable = ds.unusable = 0;
6647 cs.padding = ds.padding = 0;
6648
6649 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6650 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6651 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6652 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6653 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6654 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6655
6656 if (guest_cpuid_has_longmode(vcpu))
6657 kvm_x86_ops->set_efer(vcpu, 0);
6658
6659 kvm_update_cpuid(vcpu);
6660 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6661}
6662
ee2cd4b7 6663static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6664{
6665 vcpu->arch.smi_pending = true;
6666 kvm_make_request(KVM_REQ_EVENT, vcpu);
6667}
6668
2860c4b1
PB		 6669void kvm_make_scan_ioapic_request(struct kvm *kvm)
6670{
6671 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6672}
6673
3d81bc7e 6674static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6675{
5c919412
AS		 6676 u64 eoi_exit_bitmap[4];
6677
3d81bc7e
YZ		 6678 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6679 return;
c7c9c56c 6680
6308630b 6681 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6682
b053b2ae 6683 if (irqchip_split(vcpu->kvm))
6308630b 6684 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6685 else {
76dfafd5 6686 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6687 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6688 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6689 }
5c919412
AS		 6690 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6691 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6692 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6693}
6694
a70656b6
RK		 6695static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6696{
6697 ++vcpu->stat.tlb_flush;
6698 kvm_x86_ops->tlb_flush(vcpu);
6699}
6700
4256f43f
TC		 6701void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6702{
c24ae0dc
TC		 6703 struct page *page = NULL;
6704
35754c98 6705 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6706 return;
6707
4256f43f
TC		 6708 if (!kvm_x86_ops->set_apic_access_page_addr)
6709 return;
6710
c24ae0dc 6711 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6712 if (is_error_page(page))
6713 return;
c24ae0dc
TC		 6714 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6715
6716 /*
6717 * Do not pin apic access page in memory, the MMU notifier
6718 * will call us again if it is migrated or swapped out.
6719 */
6720 put_page(page);
4256f43f
TC		 6721}
6722EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6723
fe71557a
TC		 6724void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6725 unsigned long address)
6726{
c24ae0dc
TC		 6727 /*
6728 * The physical address of apic access page is stored in the VMCS.
6729 * Update it when it becomes invalid.
6730 */
6731 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6732 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6733}
6734
9357d939 6735/*
362c698f 6736 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6737 * exiting to the userspace. Otherwise, the value will be returned to the
6738 * userspace.
6739 */
851ba692 6740static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6741{
6742 int r;
62a193ed
MG		 6743 bool req_int_win =
6744 dm_request_for_irq_injection(vcpu) &&
6745 kvm_cpu_accept_dm_intr(vcpu);
6746
730dca42 6747 bool req_immediate_exit = false;
b6c7a5dc 6748
2fa6e1e1 6749 if (kvm_request_pending(vcpu)) {
a8eeb04a 6750 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6751 kvm_mmu_unload(vcpu);
a8eeb04a 6752 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6753 __kvm_migrate_timers(vcpu);
d828199e
MT		 6754 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6755 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6756 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6757 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6758 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6759 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6760 if (unlikely(r))
6761 goto out;
6762 }
a8eeb04a 6763 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6764 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6765 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6766 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6767 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6768 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6769 r = 0;
6770 goto out;
6771 }
a8eeb04a 6772 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6773 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6774 r = 0;
6775 goto out;
6776 }
af585b92
GN		 6777 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6778 /* Page is swapped out. Do synthetic halt */
6779 vcpu->arch.apf.halted = true;
6780 r = 1;
6781 goto out;
6782 }
c9aaa895
GC		 6783 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6784 record_steal_time(vcpu);
64d60670
PB		 6785 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6786 process_smi(vcpu);
7460fb4a
AK		 6787 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6788 process_nmi(vcpu);
f5132b01 6789 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6790 kvm_pmu_handle_event(vcpu);
f5132b01 6791 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6792 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6793 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6794 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6795 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6796 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6797 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6798 vcpu->run->eoi.vector =
6799 vcpu->arch.pending_ioapic_eoi;
6800 r = 0;
6801 goto out;
6802 }
6803 }
3d81bc7e
YZ		 6804 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6805 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6806 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6807 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6808 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6809 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6810 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6811 r = 0;
6812 goto out;
6813 }
e516cebb
AS		 6814 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6815 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6816 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6817 r = 0;
6818 goto out;
6819 }
db397571
AS		 6820 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6821 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6822 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6823 r = 0;
6824 goto out;
6825 }
f3b138c5
AS		 6826
6827 /*
6828 * KVM_REQ_HV_STIMER has to be processed after
6829 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6830 * depend on the guest clock being up-to-date
6831 */
1f4b34f8
AS		 6832 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6833 kvm_hv_process_stimers(vcpu);
2f52d58c 6834 }
b93463aa 6835
b463a6f7 6836 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6837 ++vcpu->stat.req_event;
66450a21
JK		 6838 kvm_apic_accept_events(vcpu);
6839 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6840 r = 1;
6841 goto out;
6842 }
6843
b6b8a145
JK		 6844 if (inject_pending_event(vcpu, req_int_win) != 0)
6845 req_immediate_exit = true;
321c5658 6846 else {
c43203ca
PB		 6847 /* Enable NMI/IRQ window open exits if needed.
6848 *
6849 * SMIs have two cases: 1) they can be nested, and
6850 * then there is nothing to do here because RSM will
6851 * cause a vmexit anyway; 2) or the SMI can be pending
6852 * because inject_pending_event has completed the
6853 * injection of an IRQ or NMI from the previous vmexit,
6854 * and then we request an immediate exit to inject the SMI.
6855 */
6856 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6857 req_immediate_exit = true;
321c5658
YS		 6858 if (vcpu->arch.nmi_pending)
6859 kvm_x86_ops->enable_nmi_window(vcpu);
6860 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6861 kvm_x86_ops->enable_irq_window(vcpu);
6862 }
b463a6f7
AK		 6863
6864 if (kvm_lapic_enabled(vcpu)) {
6865 update_cr8_intercept(vcpu);
6866 kvm_lapic_sync_to_vapic(vcpu);
6867 }
6868 }
6869
d8368af8
AK		 6870 r = kvm_mmu_reload(vcpu);
6871 if (unlikely(r)) {
d905c069 6872 goto cancel_injection;
d8368af8
AK		 6873 }
6874
b6c7a5dc
HB		 6875 preempt_disable();
6876
6877 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6878 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6879
6880 /*
6881 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6882 * IPI are then delayed after guest entry, which ensures that they
6883 * result in virtual interrupt delivery.
6884 */
6885 local_irq_disable();
6b7e2d09
XG		 6886 vcpu->mode = IN_GUEST_MODE;
6887
01b71917
MT		 6888 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6889
0f127d12 6890 /*
b95234c8 6891 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6892 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6893 *
6894 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6895 * pairs with the memory barrier implicit in pi_test_and_set_on
6896 * (see vmx_deliver_posted_interrupt).
6897 *
6898 * 3) This also orders the write to mode from any reads to the page
6899 * tables done while the VCPU is running. Please see the comment
6900 * in kvm_flush_remote_tlbs.
6b7e2d09 6901 */
01b71917 6902 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6903
b95234c8
PB		 6904 /*
6905 * This handles the case where a posted interrupt was
6906 * notified with kvm_vcpu_kick.
6907 */
6908 if (kvm_lapic_enabled(vcpu)) {
6909 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6910 kvm_x86_ops->sync_pir_to_irr(vcpu);
6911 }
32f88400 6912
2fa6e1e1 6913 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6914 || need_resched() || signal_pending(current)) {
6b7e2d09 6915 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6916 smp_wmb();
6c142801
AK		 6917 local_irq_enable();
6918 preempt_enable();
01b71917 6919 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6920 r = 1;
d905c069 6921 goto cancel_injection;
6c142801
AK		 6922 }
6923
fc5b7f3b
DM		 6924 kvm_load_guest_xcr0(vcpu);
6925
c43203ca
PB		 6926 if (req_immediate_exit) {
6927 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6928 smp_send_reschedule(vcpu->cpu);
c43203ca 6929 }
d6185f20 6930
8b89fe1f
PB		 6931 trace_kvm_entry(vcpu->vcpu_id);
6932 wait_lapic_expire(vcpu);
6edaa530 6933 guest_enter_irqoff();
b6c7a5dc 6934
42dbaa5a 6935 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6936 set_debugreg(0, 7);
6937 set_debugreg(vcpu->arch.eff_db[0], 0);
6938 set_debugreg(vcpu->arch.eff_db[1], 1);
6939 set_debugreg(vcpu->arch.eff_db[2], 2);
6940 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6941 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6942 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6943 }
b6c7a5dc 6944
851ba692 6945 kvm_x86_ops->run(vcpu);
b6c7a5dc 6946
c77fb5fe
PB		 6947 /*
6948 * Do this here before restoring debug registers on the host. And
6949 * since we do this before handling the vmexit, a DR access vmexit
6950 * can (a) read the correct value of the debug registers, (b) set
6951 * KVM_DEBUGREG_WONT_EXIT again.
6952 */
6953 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6954 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6955 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6956 kvm_update_dr0123(vcpu);
6957 kvm_update_dr6(vcpu);
6958 kvm_update_dr7(vcpu);
6959 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6960 }
6961
24f1e32c
FW		 6962 /*
6963 * If the guest has used debug registers, at least dr7
6964 * will be disabled while returning to the host.
6965 * If we don't have active breakpoints in the host, we don't
6966 * care about the messed up debug address registers. But if
6967 * we have some of them active, restore the old state.
6968 */
59d8eb53 6969 if (hw_breakpoint_active())
24f1e32c 6970 hw_breakpoint_restore();
42dbaa5a 6971
4ba76538 6972 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6973
6b7e2d09 6974 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6975 smp_wmb();
a547c6db 6976
fc5b7f3b
DM		 6977 kvm_put_guest_xcr0(vcpu);
6978
a547c6db 6979 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6980
6981 ++vcpu->stat.exits;
6982
f2485b3e 6983 guest_exit_irqoff();
b6c7a5dc 6984
f2485b3e 6985 local_irq_enable();
b6c7a5dc
HB		 6986 preempt_enable();
6987
f656ce01 6988 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6989
b6c7a5dc
HB		 6990 /*
6991 * Profile KVM exit RIPs:
6992 */
6993 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6994 unsigned long rip = kvm_rip_read(vcpu);
6995 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6996 }
6997
cc578287
ZA		 6998 if (unlikely(vcpu->arch.tsc_always_catchup))
6999 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7000
5cfb1d5a
MT		 7001 if (vcpu->arch.apic_attention)
7002 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7003
851ba692 7004 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7005 return r;
7006
7007cancel_injection:
7008 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7009 if (unlikely(vcpu->arch.apic_attention))
7010 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7011out:
7012 return r;
7013}
b6c7a5dc 7014
362c698f
PB		 7015static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7016{
bf9f6ac8
FW		 7017 if (!kvm_arch_vcpu_runnable(vcpu) &&
7018 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7019 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7020 kvm_vcpu_block(vcpu);
7021 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7022
7023 if (kvm_x86_ops->post_block)
7024 kvm_x86_ops->post_block(vcpu);
7025
9c8fd1ba
PB		 7026 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7027 return 1;
7028 }
362c698f
PB		 7029
7030 kvm_apic_accept_events(vcpu);
7031 switch(vcpu->arch.mp_state) {
7032 case KVM_MP_STATE_HALTED:
7033 vcpu->arch.pv.pv_unhalted = false;
7034 vcpu->arch.mp_state =
7035 KVM_MP_STATE_RUNNABLE;
7036 case KVM_MP_STATE_RUNNABLE:
7037 vcpu->arch.apf.halted = false;
7038 break;
7039 case KVM_MP_STATE_INIT_RECEIVED:
7040 break;
7041 default:
7042 return -EINTR;
7043 break;
7044 }
7045 return 1;
7046}
09cec754 7047
5d9bc648
PB		 7048static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7049{
0ad3bed6
PB		 7050 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7051 kvm_x86_ops->check_nested_events(vcpu, false);
7052
5d9bc648
PB		 7053 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7054 !vcpu->arch.apf.halted);
7055}
7056
362c698f 7057static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7058{
7059 int r;
f656ce01 7060 struct kvm *kvm = vcpu->kvm;
d7690175 7061
f656ce01 7062 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7063
362c698f 7064 for (;;) {
58f800d5 7065 if (kvm_vcpu_running(vcpu)) {
851ba692 7066 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7067 } else {
362c698f 7068 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7069 }
7070
09cec754
GN		 7071 if (r <= 0)
7072 break;
7073
72875d8a 7074 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7075 if (kvm_cpu_has_pending_timer(vcpu))
7076 kvm_inject_pending_timer_irqs(vcpu);
7077
782d422b
MG		 7078 if (dm_request_for_irq_injection(vcpu) &&
7079 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7080 r = 0;
7081 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7082 ++vcpu->stat.request_irq_exits;
362c698f 7083 break;
09cec754 7084 }
af585b92
GN		 7085
7086 kvm_check_async_pf_completion(vcpu);
7087
09cec754
GN		 7088 if (signal_pending(current)) {
7089 r = -EINTR;
851ba692 7090 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7091 ++vcpu->stat.signal_exits;
362c698f 7092 break;
09cec754
GN		 7093 }
7094 if (need_resched()) {
f656ce01 7095 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7096 cond_resched();
f656ce01 7097 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7098 }
b6c7a5dc
HB		 7099 }
7100
f656ce01 7101 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7102
7103 return r;
7104}
7105
716d51ab
GN		 7106static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7107{
7108 int r;
7109 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7110 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7111 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7112 if (r != EMULATE_DONE)
7113 return 0;
7114 return 1;
7115}
7116
7117static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7118{
7119 BUG_ON(!vcpu->arch.pio.count);
7120
7121 return complete_emulated_io(vcpu);
7122}
7123
f78146b0
AK		 7124/*
7125 * Implements the following, as a state machine:
7126 *
7127 * read:
7128 * for each fragment
87da7e66
XG		 7129 * for each mmio piece in the fragment
7130 * write gpa, len
7131 * exit
7132 * copy data
f78146b0
AK		 7133 * execute insn
7134 *
7135 * write:
7136 * for each fragment
87da7e66
XG		 7137 * for each mmio piece in the fragment
7138 * write gpa, len
7139 * copy data
7140 * exit
f78146b0 7141 */
716d51ab 7142static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7143{
7144 struct kvm_run *run = vcpu->run;
f78146b0 7145 struct kvm_mmio_fragment *frag;
87da7e66 7146 unsigned len;
5287f194 7147
716d51ab 7148 BUG_ON(!vcpu->mmio_needed);
5287f194 7149
716d51ab 7150 /* Complete previous fragment */
87da7e66
XG		 7151 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7152 len = min(8u, frag->len);
716d51ab 7153 if (!vcpu->mmio_is_write)
87da7e66
XG		 7154 memcpy(frag->data, run->mmio.data, len);
7155
7156 if (frag->len <= 8) {
7157 /* Switch to the next fragment. */
7158 frag++;
7159 vcpu->mmio_cur_fragment++;
7160 } else {
7161 /* Go forward to the next mmio piece. */
7162 frag->data += len;
7163 frag->gpa += len;
7164 frag->len -= len;
7165 }
7166
a08d3b3b 7167 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7168 vcpu->mmio_needed = 0;
0912c977
PB		 7169
7170 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7171 if (vcpu->mmio_is_write)
716d51ab
GN		 7172 return 1;
7173 vcpu->mmio_read_completed = 1;
7174 return complete_emulated_io(vcpu);
7175 }
87da7e66 7176
716d51ab
GN		 7177 run->exit_reason = KVM_EXIT_MMIO;
7178 run->mmio.phys_addr = frag->gpa;
7179 if (vcpu->mmio_is_write)
87da7e66
XG		 7180 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7181 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7182 run->mmio.is_write = vcpu->mmio_is_write;
7183 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7184 return 0;
5287f194
AK		 7185}
7186
716d51ab 7187
b6c7a5dc
HB		 7188int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7189{
c5bedc68 7190 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7191 int r;
7192 sigset_t sigsaved;
7193
c4d72e2d 7194 fpu__activate_curr(fpu);
e5c30142 7195
ac9f6dc0
AK		 7196 if (vcpu->sigset_active)
7197 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7198
a4535290 7199 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7200 kvm_vcpu_block(vcpu);
66450a21 7201 kvm_apic_accept_events(vcpu);
72875d8a 7202 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0
AK		 7203 r = -EAGAIN;
7204 goto out;
b6c7a5dc
HB		 7205 }
7206
b6c7a5dc 7207 /* re-sync apic's tpr */
35754c98 7208 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7209 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7210 r = -EINVAL;
7211 goto out;
7212 }
7213 }
b6c7a5dc 7214
716d51ab
GN		 7215 if (unlikely(vcpu->arch.complete_userspace_io)) {
7216 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7217 vcpu->arch.complete_userspace_io = NULL;
7218 r = cui(vcpu);
7219 if (r <= 0)
7220 goto out;
7221 } else
7222 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7223
460df4c1
PB		 7224 if (kvm_run->immediate_exit)
7225 r = -EINTR;
7226 else
7227 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7228
7229out:
f1d86e46 7230 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7231 if (vcpu->sigset_active)
7232 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7233
b6c7a5dc
HB		 7234 return r;
7235}
7236
7237int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7238{
7ae441ea
GN		 7239 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7240 /*
7241 * We are here if userspace calls get_regs() in the middle of
7242 * instruction emulation. Registers state needs to be copied
4a969980 7243 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7244 * that usually, but some bad designed PV devices (vmware
7245 * backdoor interface) need this to work
7246 */
dd856efa 7247 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7248 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7249 }
5fdbf976
MT		 7250 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7251 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7252 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7253 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7254 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7255 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7256 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7257 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7258#ifdef CONFIG_X86_64
5fdbf976
MT		 7259 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7260 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7261 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7262 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7263 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7264 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7265 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7266 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7267#endif
7268
5fdbf976 7269 regs->rip = kvm_rip_read(vcpu);
91586a3b 7270 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7271
b6c7a5dc
HB		 7272 return 0;
7273}
7274
7275int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7276{
7ae441ea
GN		 7277 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7278 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7279
5fdbf976
MT		 7280 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7281 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7282 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7283 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7284 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7285 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7286 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7287 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7288#ifdef CONFIG_X86_64
5fdbf976
MT		 7289 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7290 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7291 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7292 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7293 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7294 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7295 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7296 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7297#endif
7298
5fdbf976 7299 kvm_rip_write(vcpu, regs->rip);
91586a3b 7300 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7301
b4f14abd
JK		 7302 vcpu->arch.exception.pending = false;
7303
3842d135
AK		 7304 kvm_make_request(KVM_REQ_EVENT, vcpu);
7305
b6c7a5dc
HB		 7306 return 0;
7307}
7308
b6c7a5dc
HB		 7309void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7310{
7311 struct kvm_segment cs;
7312
3e6e0aab 7313 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7314 *db = cs.db;
7315 *l = cs.l;
7316}
7317EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7318
7319int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7320 struct kvm_sregs *sregs)
7321{
89a27f4d 7322 struct desc_ptr dt;
b6c7a5dc 7323
3e6e0aab
GT		 7324 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7325 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7326 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7327 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7328 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7329 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7330
3e6e0aab
GT		 7331 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7332 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7333
7334 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7335 sregs->idt.limit = dt.size;
7336 sregs->idt.base = dt.address;
b6c7a5dc 7337 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7338 sregs->gdt.limit = dt.size;
7339 sregs->gdt.base = dt.address;
b6c7a5dc 7340
4d4ec087 7341 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7342 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7343 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7344 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7345 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7346 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7347 sregs->apic_base = kvm_get_apic_base(vcpu);
7348
923c61bb 7349 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7350
36752c9b 7351 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7352 set_bit(vcpu->arch.interrupt.nr,
7353 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7354
b6c7a5dc
HB		 7355 return 0;
7356}
7357
62d9f0db
MT		 7358int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7359 struct kvm_mp_state *mp_state)
7360{
66450a21 7361 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7362 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7363 vcpu->arch.pv.pv_unhalted)
7364 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7365 else
7366 mp_state->mp_state = vcpu->arch.mp_state;
7367
62d9f0db
MT		 7368 return 0;
7369}
7370
7371int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7372 struct kvm_mp_state *mp_state)
7373{
bce87cce 7374 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7375 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7376 return -EINVAL;
7377
28bf2888
DH		 7378 /* INITs are latched while in SMM */
7379 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7380 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7381 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7382 return -EINVAL;
7383
66450a21
JK		 7384 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7385 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7386 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7387 } else
7388 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7389 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7390 return 0;
7391}
7392
7f3d35fd
KW		 7393int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7394 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7395{
9d74191a 7396 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7397 int ret;
e01c2426 7398
8ec4722d 7399 init_emulate_ctxt(vcpu);
c697518a 7400
7f3d35fd 7401 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7402 has_error_code, error_code);
c697518a 7403
c697518a 7404 if (ret)
19d04437 7405 return EMULATE_FAIL;
37817f29 7406
9d74191a
TY		 7407 kvm_rip_write(vcpu, ctxt->eip);
7408 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7409 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7410 return EMULATE_DONE;
37817f29
IE		 7411}
7412EXPORT_SYMBOL_GPL(kvm_task_switch);
7413
b6c7a5dc
HB		 7414int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7415 struct kvm_sregs *sregs)
7416{
58cb628d 7417 struct msr_data apic_base_msr;
b6c7a5dc 7418 int mmu_reset_needed = 0;
63f42e02 7419 int pending_vec, max_bits, idx;
89a27f4d 7420 struct desc_ptr dt;
b6c7a5dc 7421
6d1068b3
PM		 7422 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7423 return -EINVAL;
7424
89a27f4d
GN		 7425 dt.size = sregs->idt.limit;
7426 dt.address = sregs->idt.base;
b6c7a5dc 7427 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7428 dt.size = sregs->gdt.limit;
7429 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7430 kvm_x86_ops->set_gdt(vcpu, &dt);
7431
ad312c7c 7432 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7433 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7434 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7435 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7436
2d3ad1f4 7437 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7438
f6801dff 7439 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7440 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7441 apic_base_msr.data = sregs->apic_base;
7442 apic_base_msr.host_initiated = true;
7443 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7444
4d4ec087 7445 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7446 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7447 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7448
fc78f519 7449 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7450 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7451 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7452 kvm_update_cpuid(vcpu);
63f42e02
XG		 7453
7454 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7455 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7456 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7457 mmu_reset_needed = 1;
7458 }
63f42e02 7459 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7460
7461 if (mmu_reset_needed)
7462 kvm_mmu_reset_context(vcpu);
7463
a50abc3b 7464 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7465 pending_vec = find_first_bit(
7466 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7467 if (pending_vec < max_bits) {
66fd3f7f 7468 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7469 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7470 }
7471
3e6e0aab
GT		 7472 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7473 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7474 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7475 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7476 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7477 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7478
3e6e0aab
GT		 7479 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7480 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7481
5f0269f5
ME		 7482 update_cr8_intercept(vcpu);
7483
9c3e4aab 7484 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7485 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7486 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7487 !is_protmode(vcpu))
9c3e4aab
MT		 7488 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7489
3842d135
AK		 7490 kvm_make_request(KVM_REQ_EVENT, vcpu);
7491
b6c7a5dc
HB		 7492 return 0;
7493}
7494
d0bfb940
JK		 7495int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7496 struct kvm_guest_debug *dbg)
b6c7a5dc 7497{
355be0b9 7498 unsigned long rflags;
ae675ef0 7499 int i, r;
b6c7a5dc 7500
4f926bf2
JK		 7501 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7502 r = -EBUSY;
7503 if (vcpu->arch.exception.pending)
2122ff5e 7504 goto out;
4f926bf2
JK		 7505 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7506 kvm_queue_exception(vcpu, DB_VECTOR);
7507 else
7508 kvm_queue_exception(vcpu, BP_VECTOR);
7509 }
7510
91586a3b
JK		 7511 /*
7512 * Read rflags as long as potentially injected trace flags are still
7513 * filtered out.
7514 */
7515 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7516
7517 vcpu->guest_debug = dbg->control;
7518 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7519 vcpu->guest_debug = 0;
7520
7521 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7522 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7523 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7524 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7525 } else {
7526 for (i = 0; i < KVM_NR_DB_REGS; i++)
7527 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7528 }
c8639010 7529 kvm_update_dr7(vcpu);
ae675ef0 7530
f92653ee
JK		 7531 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7532 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7533 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7534
91586a3b
JK		 7535 /*
7536 * Trigger an rflags update that will inject or remove the trace
7537 * flags.
7538 */
7539 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7540
a96036b8 7541 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7542
4f926bf2 7543 r = 0;
d0bfb940 7544
2122ff5e 7545out:
b6c7a5dc
HB		 7546
7547 return r;
7548}
7549
8b006791
ZX		 7550/*
7551 * Translate a guest virtual address to a guest physical address.
7552 */
7553int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7554 struct kvm_translation *tr)
7555{
7556 unsigned long vaddr = tr->linear_address;
7557 gpa_t gpa;
f656ce01 7558 int idx;
8b006791 7559
f656ce01 7560 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7561 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7562 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7563 tr->physical_address = gpa;
7564 tr->valid = gpa != UNMAPPED_GVA;
7565 tr->writeable = 1;
7566 tr->usermode = 0;
8b006791
ZX		 7567
7568 return 0;
7569}
7570
d0752060
HB		 7571int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7572{
c47ada30 7573 struct fxregs_state *fxsave =
7366ed77 7574 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7575
d0752060
HB		 7576 memcpy(fpu->fpr, fxsave->st_space, 128);
7577 fpu->fcw = fxsave->cwd;
7578 fpu->fsw = fxsave->swd;
7579 fpu->ftwx = fxsave->twd;
7580 fpu->last_opcode = fxsave->fop;
7581 fpu->last_ip = fxsave->rip;
7582 fpu->last_dp = fxsave->rdp;
7583 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7584
d0752060
HB		 7585 return 0;
7586}
7587
7588int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7589{
c47ada30 7590 struct fxregs_state *fxsave =
7366ed77 7591 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7592
d0752060
HB		 7593 memcpy(fxsave->st_space, fpu->fpr, 128);
7594 fxsave->cwd = fpu->fcw;
7595 fxsave->swd = fpu->fsw;
7596 fxsave->twd = fpu->ftwx;
7597 fxsave->fop = fpu->last_opcode;
7598 fxsave->rip = fpu->last_ip;
7599 fxsave->rdp = fpu->last_dp;
7600 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7601
d0752060
HB		 7602 return 0;
7603}
7604
0ee6a517 7605static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7606{
bf935b0b 7607 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7608 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7609 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7610 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7611
2acf923e
DC		 7612 /*
7613 * Ensure guest xcr0 is valid for loading
7614 */
d91cab78 7615 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7616
ad312c7c 7617 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7618}
d0752060
HB		 7619
7620void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7621{
2608d7a1 7622 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7623 return;
7624
2acf923e
DC		 7625 /*
7626 * Restore all possible states in the guest,
7627 * and assume host would use all available bits.
7628 * Guest xcr0 would be loaded later.
7629 */
d0752060 7630 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7631 __kernel_fpu_begin();
003e2e8b 7632 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7633 trace_kvm_fpu(1);
d0752060 7634}
d0752060
HB		 7635
7636void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7637{
3d42de25 7638 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7639 return;
7640
7641 vcpu->guest_fpu_loaded = 0;
4f836347 7642 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7643 __kernel_fpu_end();
f096ed85 7644 ++vcpu->stat.fpu_reload;
0c04851c 7645 trace_kvm_fpu(0);
d0752060 7646}
e9b11c17
ZX		 7647
7648void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7649{
bd768e14
IY		 7650 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7651
12f9a48f 7652 kvmclock_reset(vcpu);
7f1ea208 7653
e9b11c17 7654 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7655 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7656}
7657
7658struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7659 unsigned int id)
7660{
c447e76b
LL		 7661 struct kvm_vcpu *vcpu;
7662
6755bae8
ZA		 7663 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7664 printk_once(KERN_WARNING
7665 "kvm: SMP vm created on host with unstable TSC; "
7666 "guest TSC will not be reliable\n");
c447e76b
LL		 7667
7668 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7669
c447e76b 7670 return vcpu;
26e5215f 7671}
e9b11c17 7672
26e5215f
AK		 7673int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7674{
7675 int r;
e9b11c17 7676
19efffa2 7677 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7678 r = vcpu_load(vcpu);
7679 if (r)
7680 return r;
d28bc9dd 7681 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7682 kvm_mmu_setup(vcpu);
e9b11c17 7683 vcpu_put(vcpu);
26e5215f 7684 return r;
e9b11c17
ZX		 7685}
7686
31928aa5 7687void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7688{
8fe8ab46 7689 struct msr_data msr;
332967a3 7690 struct kvm *kvm = vcpu->kvm;
42897d86 7691
d3457c87
RK		 7692 kvm_hv_vcpu_postcreate(vcpu);
7693
31928aa5
DD		 7694 if (vcpu_load(vcpu))
7695 return;
8fe8ab46
WA		 7696 msr.data = 0x0;
7697 msr.index = MSR_IA32_TSC;
7698 msr.host_initiated = true;
7699 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7700 vcpu_put(vcpu);
7701
630994b3
MT		 7702 if (!kvmclock_periodic_sync)
7703 return;
7704
332967a3
AJ		 7705 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7706 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7707}
7708
d40ccc62 7709void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7710{
9fc77441 7711 int r;
344d9588
GN		 7712 vcpu->arch.apf.msr_val = 0;
7713
9fc77441
MT		 7714 r = vcpu_load(vcpu);
7715 BUG_ON(r);
e9b11c17
ZX		 7716 kvm_mmu_unload(vcpu);
7717 vcpu_put(vcpu);
7718
7719 kvm_x86_ops->vcpu_free(vcpu);
7720}
7721
d28bc9dd 7722void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7723{
e69fab5d
PB		 7724 vcpu->arch.hflags = 0;
7725
c43203ca 7726 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7727 atomic_set(&vcpu->arch.nmi_queued, 0);
7728 vcpu->arch.nmi_pending = 0;
448fa4a9 7729 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7730 kvm_clear_interrupt_queue(vcpu);
7731 kvm_clear_exception_queue(vcpu);
448fa4a9 7732
42dbaa5a 7733 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7734 kvm_update_dr0123(vcpu);
6f43ed01 7735 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7736 kvm_update_dr6(vcpu);
42dbaa5a 7737 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7738 kvm_update_dr7(vcpu);
42dbaa5a 7739
1119022c
NA		 7740 vcpu->arch.cr2 = 0;
7741
3842d135 7742 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7743 vcpu->arch.apf.msr_val = 0;
c9aaa895 7744 vcpu->arch.st.msr_val = 0;
3842d135 7745
12f9a48f
GC		 7746 kvmclock_reset(vcpu);
7747
af585b92
GN		 7748 kvm_clear_async_pf_completion_queue(vcpu);
7749 kvm_async_pf_hash_reset(vcpu);
7750 vcpu->arch.apf.halted = false;
3842d135 7751
64d60670 7752 if (!init_event) {
d28bc9dd 7753 kvm_pmu_reset(vcpu);
64d60670 7754 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7755
7756 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7757 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7758 }
f5132b01 7759
66f7b72e
JS		 7760 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7761 vcpu->arch.regs_avail = ~0;
7762 vcpu->arch.regs_dirty = ~0;
7763
d28bc9dd 7764 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7765}
7766
2b4a273b 7767void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7768{
7769 struct kvm_segment cs;
7770
7771 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7772 cs.selector = vector << 8;
7773 cs.base = vector << 12;
7774 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7775 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7776}
7777
13a34e06 7778int kvm_arch_hardware_enable(void)
e9b11c17 7779{
ca84d1a2
ZA		 7780 struct kvm *kvm;
7781 struct kvm_vcpu *vcpu;
7782 int i;
0dd6a6ed
ZA		 7783 int ret;
7784 u64 local_tsc;
7785 u64 max_tsc = 0;
7786 bool stable, backwards_tsc = false;
18863bdd
AK		 7787
7788 kvm_shared_msr_cpu_online();
13a34e06 7789 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7790 if (ret != 0)
7791 return ret;
7792
4ea1636b 7793 local_tsc = rdtsc();
0dd6a6ed
ZA		 7794 stable = !check_tsc_unstable();
7795 list_for_each_entry(kvm, &vm_list, vm_list) {
7796 kvm_for_each_vcpu(i, vcpu, kvm) {
7797 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7798 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7799 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7800 backwards_tsc = true;
7801 if (vcpu->arch.last_host_tsc > max_tsc)
7802 max_tsc = vcpu->arch.last_host_tsc;
7803 }
7804 }
7805 }
7806
7807 /*
7808 * Sometimes, even reliable TSCs go backwards. This happens on
7809 * platforms that reset TSC during suspend or hibernate actions, but
7810 * maintain synchronization. We must compensate. Fortunately, we can
7811 * detect that condition here, which happens early in CPU bringup,
7812 * before any KVM threads can be running. Unfortunately, we can't
7813 * bring the TSCs fully up to date with real time, as we aren't yet far
7814 * enough into CPU bringup that we know how much real time has actually
108b249c 7815 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7816 * variables that haven't been updated yet.
7817 *
7818 * So we simply find the maximum observed TSC above, then record the
7819 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7820 * the adjustment will be applied. Note that we accumulate
7821 * adjustments, in case multiple suspend cycles happen before some VCPU
7822 * gets a chance to run again. In the event that no KVM threads get a
7823 * chance to run, we will miss the entire elapsed period, as we'll have
7824 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7825 * loose cycle time. This isn't too big a deal, since the loss will be
7826 * uniform across all VCPUs (not to mention the scenario is extremely
7827 * unlikely). It is possible that a second hibernate recovery happens
7828 * much faster than a first, causing the observed TSC here to be
7829 * smaller; this would require additional padding adjustment, which is
7830 * why we set last_host_tsc to the local tsc observed here.
7831 *
7832 * N.B. - this code below runs only on platforms with reliable TSC,
7833 * as that is the only way backwards_tsc is set above. Also note
7834 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7835 * have the same delta_cyc adjustment applied if backwards_tsc
7836 * is detected. Note further, this adjustment is only done once,
7837 * as we reset last_host_tsc on all VCPUs to stop this from being
7838 * called multiple times (one for each physical CPU bringup).
7839 *
4a969980 7840 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7841 * will be compensated by the logic in vcpu_load, which sets the TSC to
7842 * catchup mode. This will catchup all VCPUs to real time, but cannot
7843 * guarantee that they stay in perfect synchronization.
7844 */
7845 if (backwards_tsc) {
7846 u64 delta_cyc = max_tsc - local_tsc;
7847 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7848 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7849 kvm_for_each_vcpu(i, vcpu, kvm) {
7850 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7851 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7852 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7853 }
7854
7855 /*
7856 * We have to disable TSC offset matching.. if you were
7857 * booting a VM while issuing an S4 host suspend....
7858 * you may have some problem. Solving this issue is
7859 * left as an exercise to the reader.
7860 */
7861 kvm->arch.last_tsc_nsec = 0;
7862 kvm->arch.last_tsc_write = 0;
7863 }
7864
7865 }
7866 return 0;
e9b11c17
ZX		 7867}
7868
13a34e06 7869void kvm_arch_hardware_disable(void)
e9b11c17 7870{
13a34e06
RK		 7871 kvm_x86_ops->hardware_disable();
7872 drop_user_return_notifiers();
e9b11c17
ZX		 7873}
7874
7875int kvm_arch_hardware_setup(void)
7876{
9e9c3fe4
NA		 7877 int r;
7878
7879 r = kvm_x86_ops->hardware_setup();
7880 if (r != 0)
7881 return r;
7882
35181e86
HZ		 7883 if (kvm_has_tsc_control) {
7884 /*
7885 * Make sure the user can only configure tsc_khz values that
7886 * fit into a signed integer.
7887 * A min value is not calculated needed because it will always
7888 * be 1 on all machines.
7889 */
7890 u64 max = min(0x7fffffffULL,
7891 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7892 kvm_max_guest_tsc_khz = max;
7893
ad721883 7894 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7895 }
ad721883 7896
9e9c3fe4
NA		 7897 kvm_init_msr_list();
7898 return 0;
e9b11c17
ZX		 7899}
7900
7901void kvm_arch_hardware_unsetup(void)
7902{
7903 kvm_x86_ops->hardware_unsetup();
7904}
7905
7906void kvm_arch_check_processor_compat(void *rtn)
7907{
7908 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7909}
7910
7911bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7912{
7913 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7914}
7915EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7916
7917bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7918{
7919 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7920}
7921
54e9818f 7922struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7923EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7924
e9b11c17
ZX		 7925int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7926{
7927 struct page *page;
7928 struct kvm *kvm;
7929 int r;
7930
7931 BUG_ON(vcpu->kvm == NULL);
7932 kvm = vcpu->kvm;
7933
d62caabb 7934 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7935 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7936 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7937 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7938 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7939 else
a4535290 7940 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7941
7942 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7943 if (!page) {
7944 r = -ENOMEM;
7945 goto fail;
7946 }
ad312c7c 7947 vcpu->arch.pio_data = page_address(page);
e9b11c17 7948
cc578287 7949 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7950
e9b11c17
ZX		 7951 r = kvm_mmu_create(vcpu);
7952 if (r < 0)
7953 goto fail_free_pio_data;
7954
7955 if (irqchip_in_kernel(kvm)) {
7956 r = kvm_create_lapic(vcpu);
7957 if (r < 0)
7958 goto fail_mmu_destroy;
54e9818f
GN		 7959 } else
7960 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7961
890ca9ae
HY		 7962 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7963 GFP_KERNEL);
7964 if (!vcpu->arch.mce_banks) {
7965 r = -ENOMEM;
443c39bc 7966 goto fail_free_lapic;
890ca9ae
HY		 7967 }
7968 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7969
f1797359
WY		 7970 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7971 r = -ENOMEM;
f5f48ee1 7972 goto fail_free_mce_banks;
f1797359 7973 }
f5f48ee1 7974
0ee6a517 7975 fx_init(vcpu);
66f7b72e 7976
ba904635 7977 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7978 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7979
7980 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7981 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7982
5a4f55cd
EK		 7983 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7984
74545705
RK		 7985 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7986
af585b92 7987 kvm_async_pf_hash_reset(vcpu);
f5132b01 7988 kvm_pmu_init(vcpu);
af585b92 7989
1c1a9ce9
SR		 7990 vcpu->arch.pending_external_vector = -1;
7991
5c919412
AS		 7992 kvm_hv_vcpu_init(vcpu);
7993
e9b11c17 7994 return 0;
0ee6a517 7995
f5f48ee1
SY		 7996fail_free_mce_banks:
7997 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7998fail_free_lapic:
7999 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8000fail_mmu_destroy:
8001 kvm_mmu_destroy(vcpu);
8002fail_free_pio_data:
ad312c7c 8003 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8004fail:
8005 return r;
8006}
8007
8008void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8009{
f656ce01
MT		 8010 int idx;
8011
1f4b34f8 8012 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8013 kvm_pmu_destroy(vcpu);
36cb93fd 8014 kfree(vcpu->arch.mce_banks);
e9b11c17 8015 kvm_free_lapic(vcpu);
f656ce01 8016 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8017 kvm_mmu_destroy(vcpu);
f656ce01 8018 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8019 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8020 if (!lapic_in_kernel(vcpu))
54e9818f 8021 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8022}
d19a9cd2 8023
e790d9ef
RK		 8024void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8025{
ae97a3b8 8026 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8027}
8028
e08b9637 8029int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8030{
e08b9637
CO		 8031 if (type)
8032 return -EINVAL;
8033
6ef768fa 8034 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8035 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8036 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8037 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8038 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8039
5550af4d
SY		 8040 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8041 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8042 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8043 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8044 &kvm->arch.irq_sources_bitmap);
5550af4d 8045
038f8c11 8046 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8047 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8048 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8049 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8050
108b249c 8051 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8052 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8053
7e44e449 8054 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8055 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8056
0eb05bf2 8057 kvm_page_track_init(kvm);
13d268ca 8058 kvm_mmu_init_vm(kvm);
0eb05bf2 8059
03543133
SS		 8060 if (kvm_x86_ops->vm_init)
8061 return kvm_x86_ops->vm_init(kvm);
8062
d89f5eff 8063 return 0;
d19a9cd2
ZX		 8064}
8065
8066static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8067{
9fc77441
MT		 8068 int r;
8069 r = vcpu_load(vcpu);
8070 BUG_ON(r);
d19a9cd2
ZX		 8071 kvm_mmu_unload(vcpu);
8072 vcpu_put(vcpu);
8073}
8074
8075static void kvm_free_vcpus(struct kvm *kvm)
8076{
8077 unsigned int i;
988a2cae 8078 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8079
8080 /*
8081 * Unpin any mmu pages first.
8082 */
af585b92
GN		 8083 kvm_for_each_vcpu(i, vcpu, kvm) {
8084 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8085 kvm_unload_vcpu_mmu(vcpu);
af585b92 8086 }
988a2cae
GN		 8087 kvm_for_each_vcpu(i, vcpu, kvm)
8088 kvm_arch_vcpu_free(vcpu);
8089
8090 mutex_lock(&kvm->lock);
8091 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8092 kvm->vcpus[i] = NULL;
d19a9cd2 8093
988a2cae
GN		 8094 atomic_set(&kvm->online_vcpus, 0);
8095 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8096}
8097
ad8ba2cd
SY		 8098void kvm_arch_sync_events(struct kvm *kvm)
8099{
332967a3 8100 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8101 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8102 kvm_free_pit(kvm);
ad8ba2cd
SY		 8103}
8104
1d8007bd 8105int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8106{
8107 int i, r;
25188b99 8108 unsigned long hva;
f0d648bd
PB		 8109 struct kvm_memslots *slots = kvm_memslots(kvm);
8110 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8111
8112 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8113 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8114 return -EINVAL;
9da0e4d5 8115
f0d648bd
PB		 8116 slot = id_to_memslot(slots, id);
8117 if (size) {
b21629da 8118 if (slot->npages)
f0d648bd
PB		 8119 return -EEXIST;
8120
8121 /*
8122 * MAP_SHARED to prevent internal slot pages from being moved
8123 * by fork()/COW.
8124 */
8125 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8126 MAP_SHARED | MAP_ANONYMOUS, 0);
8127 if (IS_ERR((void *)hva))
8128 return PTR_ERR((void *)hva);
8129 } else {
8130 if (!slot->npages)
8131 return 0;
8132
8133 hva = 0;
8134 }
8135
8136 old = *slot;
9da0e4d5 8137 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8138 struct kvm_userspace_memory_region m;
9da0e4d5 8139
1d8007bd
PB		 8140 m.slot = id | (i << 16);
8141 m.flags = 0;
8142 m.guest_phys_addr = gpa;
f0d648bd 8143 m.userspace_addr = hva;
1d8007bd 8144 m.memory_size = size;
9da0e4d5
PB		 8145 r = __kvm_set_memory_region(kvm, &m);
8146 if (r < 0)
8147 return r;
8148 }
8149
f0d648bd
PB		 8150 if (!size) {
8151 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8152 WARN_ON(r < 0);
8153 }
8154
9da0e4d5
PB		 8155 return 0;
8156}
8157EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8158
1d8007bd 8159int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8160{
8161 int r;
8162
8163 mutex_lock(&kvm->slots_lock);
1d8007bd 8164 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8165 mutex_unlock(&kvm->slots_lock);
8166
8167 return r;
8168}
8169EXPORT_SYMBOL_GPL(x86_set_memory_region);
8170
d19a9cd2
ZX		 8171void kvm_arch_destroy_vm(struct kvm *kvm)
8172{
27469d29
AH		 8173 if (current->mm == kvm->mm) {
8174 /*
8175 * Free memory regions allocated on behalf of userspace,
8176 * unless the the memory map has changed due to process exit
8177 * or fd copying.
8178 */
1d8007bd
PB		 8179 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8180 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8181 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8182 }
03543133
SS		 8183 if (kvm_x86_ops->vm_destroy)
8184 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8185 kvm_pic_destroy(kvm);
8186 kvm_ioapic_destroy(kvm);
d19a9cd2 8187 kvm_free_vcpus(kvm);
af1bae54 8188 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8189 kvm_mmu_uninit_vm(kvm);
2beb6dad 8190 kvm_page_track_cleanup(kvm);
d19a9cd2 8191}
0de10343 8192
5587027c 8193void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8194 struct kvm_memory_slot *dont)
8195{
8196 int i;
8197
d89cc617
TY		 8198 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8199 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8200 kvfree(free->arch.rmap[i]);
d89cc617 8201 free->arch.rmap[i] = NULL;
77d11309 8202 }
d89cc617
TY		 8203 if (i == 0)
8204 continue;
8205
8206 if (!dont || free->arch.lpage_info[i - 1] !=
8207 dont->arch.lpage_info[i - 1]) {
548ef284 8208 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8209 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8210 }
8211 }
21ebbeda
XG		 8212
8213 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8214}
8215
5587027c
AK		 8216int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8217 unsigned long npages)
db3fe4eb
TY		 8218{
8219 int i;
8220
d89cc617 8221 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8222 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8223 unsigned long ugfn;
8224 int lpages;
d89cc617 8225 int level = i + 1;
db3fe4eb
TY		 8226
8227 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8228 slot->base_gfn, level) + 1;
8229
d89cc617 8230 slot->arch.rmap[i] =
a7c3e901 8231 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8232 if (!slot->arch.rmap[i])
77d11309 8233 goto out_free;
d89cc617
TY		 8234 if (i == 0)
8235 continue;
77d11309 8236
a7c3e901 8237 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8238 if (!linfo)
db3fe4eb
TY		 8239 goto out_free;
8240
92f94f1e
XG		 8241 slot->arch.lpage_info[i - 1] = linfo;
8242
db3fe4eb 8243 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8244 linfo[0].disallow_lpage = 1;
db3fe4eb 8245 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8246 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8247 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8248 /*
8249 * If the gfn and userspace address are not aligned wrt each
8250 * other, or if explicitly asked to, disable large page
8251 * support for this slot
8252 */
8253 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8254 !kvm_largepages_enabled()) {
8255 unsigned long j;
8256
8257 for (j = 0; j < lpages; ++j)
92f94f1e 8258 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8259 }
8260 }
8261
21ebbeda
XG		 8262 if (kvm_page_track_create_memslot(slot, npages))
8263 goto out_free;
8264
db3fe4eb
TY		 8265 return 0;
8266
8267out_free:
d89cc617 8268 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8269 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8270 slot->arch.rmap[i] = NULL;
8271 if (i == 0)
8272 continue;
8273
548ef284 8274 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8275 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8276 }
8277 return -ENOMEM;
8278}
8279
15f46015 8280void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8281{
e6dff7d1
TY		 8282 /*
8283 * memslots->generation has been incremented.
8284 * mmio generation may have reached its maximum value.
8285 */
54bf36aa 8286 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8287}
8288
f7784b8e
MT		 8289int kvm_arch_prepare_memory_region(struct kvm *kvm,
8290 struct kvm_memory_slot *memslot,
09170a49 8291 const struct kvm_userspace_memory_region *mem,
7b6195a9 8292 enum kvm_mr_change change)
0de10343 8293{
f7784b8e
MT		 8294 return 0;
8295}
8296
88178fd4
KH		 8297static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8298 struct kvm_memory_slot *new)
8299{
8300 /* Still write protect RO slot */
8301 if (new->flags & KVM_MEM_READONLY) {
8302 kvm_mmu_slot_remove_write_access(kvm, new);
8303 return;
8304 }
8305
8306 /*
8307 * Call kvm_x86_ops dirty logging hooks when they are valid.
8308 *
8309 * kvm_x86_ops->slot_disable_log_dirty is called when:
8310 *
8311 * - KVM_MR_CREATE with dirty logging is disabled
8312 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8313 *
8314 * The reason is, in case of PML, we need to set D-bit for any slots
8315 * with dirty logging disabled in order to eliminate unnecessary GPA
8316 * logging in PML buffer (and potential PML buffer full VMEXT). This
8317 * guarantees leaving PML enabled during guest's lifetime won't have
8318 * any additonal overhead from PML when guest is running with dirty
8319 * logging disabled for memory slots.
8320 *
8321 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8322 * to dirty logging mode.
8323 *
8324 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8325 *
8326 * In case of write protect:
8327 *
8328 * Write protect all pages for dirty logging.
8329 *
8330 * All the sptes including the large sptes which point to this
8331 * slot are set to readonly. We can not create any new large
8332 * spte on this slot until the end of the logging.
8333 *
8334 * See the comments in fast_page_fault().
8335 */
8336 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8337 if (kvm_x86_ops->slot_enable_log_dirty)
8338 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8339 else
8340 kvm_mmu_slot_remove_write_access(kvm, new);
8341 } else {
8342 if (kvm_x86_ops->slot_disable_log_dirty)
8343 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8344 }
8345}
8346
f7784b8e 8347void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8348 const struct kvm_userspace_memory_region *mem,
8482644a 8349 const struct kvm_memory_slot *old,
f36f3f28 8350 const struct kvm_memory_slot *new,
8482644a 8351 enum kvm_mr_change change)
f7784b8e 8352{
8482644a 8353 int nr_mmu_pages = 0;
f7784b8e 8354
48c0e4e9
XG		 8355 if (!kvm->arch.n_requested_mmu_pages)
8356 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8357
48c0e4e9 8358 if (nr_mmu_pages)
0de10343 8359 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8360
3ea3b7fa
WL		 8361 /*
8362 * Dirty logging tracks sptes in 4k granularity, meaning that large
8363 * sptes have to be split. If live migration is successful, the guest
8364 * in the source machine will be destroyed and large sptes will be
8365 * created in the destination. However, if the guest continues to run
8366 * in the source machine (for example if live migration fails), small
8367 * sptes will remain around and cause bad performance.
8368 *
8369 * Scan sptes if dirty logging has been stopped, dropping those
8370 * which can be collapsed into a single large-page spte. Later
8371 * page faults will create the large-page sptes.
8372 */
8373 if ((change != KVM_MR_DELETE) &&
8374 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8375 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8376 kvm_mmu_zap_collapsible_sptes(kvm, new);
8377
c972f3b1 8378 /*
88178fd4 8379 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8380 *
88178fd4
KH		 8381 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8382 * been zapped so no dirty logging staff is needed for old slot. For
8383 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8384 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8385 *
8386 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8387 */
88178fd4 8388 if (change != KVM_MR_DELETE)
f36f3f28 8389 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8390}
1d737c8a 8391
2df72e9b 8392void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8393{
6ca18b69 8394 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8395}
8396
2df72e9b
MT		 8397void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8398 struct kvm_memory_slot *slot)
8399{
ae7cd873 8400 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8401}
8402
5d9bc648
PB		 8403static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8404{
8405 if (!list_empty_careful(&vcpu->async_pf.done))
8406 return true;
8407
8408 if (kvm_apic_has_events(vcpu))
8409 return true;
8410
8411 if (vcpu->arch.pv.pv_unhalted)
8412 return true;
8413
47a66eed
Z		 8414 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8415 (vcpu->arch.nmi_pending &&
8416 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8417 return true;
8418
47a66eed
Z		 8419 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8420 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8421 return true;
8422
5d9bc648
PB		 8423 if (kvm_arch_interrupt_allowed(vcpu) &&
8424 kvm_cpu_has_interrupt(vcpu))
8425 return true;
8426
1f4b34f8
AS		 8427 if (kvm_hv_has_stimer_pending(vcpu))
8428 return true;
8429
5d9bc648
PB		 8430 return false;
8431}
8432
1d737c8a
ZX		 8433int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8434{
5d9bc648 8435 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8436}
5736199a 8437
b6d33834 8438int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8439{
b6d33834 8440 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8441}
78646121
GN		 8442
8443int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8444{
8445 return kvm_x86_ops->interrupt_allowed(vcpu);
8446}
229456fc 8447
82b32774 8448unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8449{
82b32774
NA		 8450 if (is_64_bit_mode(vcpu))
8451 return kvm_rip_read(vcpu);
8452 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8453 kvm_rip_read(vcpu));
8454}
8455EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8456
82b32774
NA		 8457bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8458{
8459 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8460}
8461EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8462
94fe45da
JK		 8463unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8464{
8465 unsigned long rflags;
8466
8467 rflags = kvm_x86_ops->get_rflags(vcpu);
8468 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8469 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8470 return rflags;
8471}
8472EXPORT_SYMBOL_GPL(kvm_get_rflags);
8473
6addfc42 8474static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8475{
8476 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8477 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8478 rflags |= X86_EFLAGS_TF;
94fe45da 8479 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8480}
8481
8482void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8483{
8484 __kvm_set_rflags(vcpu, rflags);
3842d135 8485 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8486}
8487EXPORT_SYMBOL_GPL(kvm_set_rflags);
8488
56028d08
GN		 8489void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8490{
8491 int r;
8492
fb67e14f 8493 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8494 work->wakeup_all)
56028d08
GN		 8495 return;
8496
8497 r = kvm_mmu_reload(vcpu);
8498 if (unlikely(r))
8499 return;
8500
fb67e14f
XG		 8501 if (!vcpu->arch.mmu.direct_map &&
8502 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8503 return;
8504
56028d08
GN		 8505 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8506}
8507
af585b92
GN		 8508static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8509{
8510 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8511}
8512
8513static inline u32 kvm_async_pf_next_probe(u32 key)
8514{
8515 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8516}
8517
8518static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8519{
8520 u32 key = kvm_async_pf_hash_fn(gfn);
8521
8522 while (vcpu->arch.apf.gfns[key] != ~0)
8523 key = kvm_async_pf_next_probe(key);
8524
8525 vcpu->arch.apf.gfns[key] = gfn;
8526}
8527
8528static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8529{
8530 int i;
8531 u32 key = kvm_async_pf_hash_fn(gfn);
8532
8533 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8534 (vcpu->arch.apf.gfns[key] != gfn &&
8535 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8536 key = kvm_async_pf_next_probe(key);
8537
8538 return key;
8539}
8540
8541bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8542{
8543 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8544}
8545
8546static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8547{
8548 u32 i, j, k;
8549
8550 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8551 while (true) {
8552 vcpu->arch.apf.gfns[i] = ~0;
8553 do {
8554 j = kvm_async_pf_next_probe(j);
8555 if (vcpu->arch.apf.gfns[j] == ~0)
8556 return;
8557 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8558 /*
8559 * k lies cyclically in ]i,j]
8560 * | i.k.j |
8561 * |....j i.k.| or |.k..j i...|
8562 */
8563 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8564 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8565 i = j;
8566 }
8567}
8568
7c90705b
GN		 8569static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8570{
4e335d9e
PB		 8571
8572 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8573 sizeof(val));
7c90705b
GN		 8574}
8575
af585b92
GN		 8576void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8577 struct kvm_async_pf *work)
8578{
6389ee94
AK		 8579 struct x86_exception fault;
8580
7c90705b 8581 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8582 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8583
8584 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8585 (vcpu->arch.apf.send_user_only &&
8586 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8587 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8588 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8589 fault.vector = PF_VECTOR;
8590 fault.error_code_valid = true;
8591 fault.error_code = 0;
8592 fault.nested_page_fault = false;
8593 fault.address = work->arch.token;
adfe20fb 8594 fault.async_page_fault = true;
6389ee94 8595 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8596 }
af585b92
GN		 8597}
8598
8599void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8600 struct kvm_async_pf *work)
8601{
6389ee94
AK		 8602 struct x86_exception fault;
8603
f2e10669 8604 if (work->wakeup_all)
7c90705b
GN		 8605 work->arch.token = ~0; /* broadcast wakeup */
8606 else
8607 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8608 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8609
8610 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8611 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8612 fault.vector = PF_VECTOR;
8613 fault.error_code_valid = true;
8614 fault.error_code = 0;
8615 fault.nested_page_fault = false;
8616 fault.address = work->arch.token;
adfe20fb 8617 fault.async_page_fault = true;
6389ee94 8618 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8619 }
e6d53e3b 8620 vcpu->arch.apf.halted = false;
a4fa1635 8621 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8622}
8623
8624bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8625{
8626 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8627 return true;
8628 else
9bc1f09f 8629 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8630}
8631
5544eb9b
PB		 8632void kvm_arch_start_assignment(struct kvm *kvm)
8633{
8634 atomic_inc(&kvm->arch.assigned_device_count);
8635}
8636EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8637
8638void kvm_arch_end_assignment(struct kvm *kvm)
8639{
8640 atomic_dec(&kvm->arch.assigned_device_count);
8641}
8642EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8643
8644bool kvm_arch_has_assigned_device(struct kvm *kvm)
8645{
8646 return atomic_read(&kvm->arch.assigned_device_count);
8647}
8648EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8649
e0f0bbc5
AW		 8650void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8651{
8652 atomic_inc(&kvm->arch.noncoherent_dma_count);
8653}
8654EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8655
8656void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8657{
8658 atomic_dec(&kvm->arch.noncoherent_dma_count);
8659}
8660EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8661
8662bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8663{
8664 return atomic_read(&kvm->arch.noncoherent_dma_count);
8665}
8666EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8667
14717e20
AW		 8668bool kvm_arch_has_irq_bypass(void)
8669{
8670 return kvm_x86_ops->update_pi_irte != NULL;
8671}
8672
87276880
FW		 8673int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8674 struct irq_bypass_producer *prod)
8675{
8676 struct kvm_kernel_irqfd *irqfd =
8677 container_of(cons, struct kvm_kernel_irqfd, consumer);
8678
14717e20 8679 irqfd->producer = prod;
87276880 8680
14717e20
AW		 8681 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8682 prod->irq, irqfd->gsi, 1);
87276880
FW		 8683}
8684
8685void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8686 struct irq_bypass_producer *prod)
8687{
8688 int ret;
8689 struct kvm_kernel_irqfd *irqfd =
8690 container_of(cons, struct kvm_kernel_irqfd, consumer);
8691
87276880
FW		 8692 WARN_ON(irqfd->producer != prod);
8693 irqfd->producer = NULL;
8694
8695 /*
8696 * When producer of consumer is unregistered, we change back to
8697 * remapped mode, so we can re-use the current implementation
bb3541f1 8698 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8699 * int this case doesn't want to receive the interrupts.
8700 */
8701 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8702 if (ret)
8703 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8704 " fails: %d\n", irqfd->consumer.token, ret);
8705}
8706
8707int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8708 uint32_t guest_irq, bool set)
8709{
8710 if (!kvm_x86_ops->update_pi_irte)
8711 return -EINVAL;
8712
8713 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8714}
8715
52004014
FW		 8716bool kvm_vector_hashing_enabled(void)
8717{
8718 return vector_hashing;
8719}
8720EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8721
229456fc 8722EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8723EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8724EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8725EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8726EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8727EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8728EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8729EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8730EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8731EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8732EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8733EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8734EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8735EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8737EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8738EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8739EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8740EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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