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NVMe: fail pci initialization if the device doesn't have any BARs
[mirror_ubuntu-bionic-kernel.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
5d0f6131 41#include <scsi/sg.h>
797a796a
HM		 42#include <asm-generic/io-64-nonatomic-lo-hi.h>
43
9d43cf64 44#define NVME_Q_DEPTH 1024
a4aea562 45#define NVME_AQ_DEPTH 64
b60503ba
MW		 46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 48#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 49#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 50#define IOD_TIMEOUT (retry_time * HZ)
51
52static unsigned char admin_timeout = 60;
53module_param(admin_timeout, byte, 0644);
54MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 55
bd67608a
MW		 56unsigned char nvme_io_timeout = 30;
57module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 58MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 59
61e4ce08
KB		 60static unsigned char retry_time = 30;
61module_param(retry_time, byte, 0644);
62MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
2484f407
DM		 64static unsigned char shutdown_timeout = 5;
65module_param(shutdown_timeout, byte, 0644);
66MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
b60503ba
MW		 68static int nvme_major;
69module_param(nvme_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
f3db22fe 79static struct notifier_block nvme_nb;
1fa6aead 80
d4b4ff8e 81static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 82static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 83
4d115420
KB		 84struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
a4aea562 87 struct request *req;
4d115420
KB		 88 u32 result;
89 int status;
90 void *ctx;
91};
1fa6aead 92
b60503ba
MW		 93/*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97struct nvme_queue {
f435c282 98 struct llist_node node;
b60503ba 99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
109 u16 cq_vector;
110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
e85248e5
MW		 147};
148
a4aea562
MB		 149static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
150 unsigned int hctx_idx)
e85248e5 151{
a4aea562
MB		 152 struct nvme_dev *dev = data;
153 struct nvme_queue *nvmeq = dev->queues[0];
154
155 WARN_ON(nvmeq->hctx);
156 nvmeq->hctx = hctx;
157 hctx->driver_data = nvmeq;
158 return 0;
e85248e5
MW		 159}
160
a4aea562
MB		 161static int nvme_admin_init_request(void *data, struct request *req,
162 unsigned int hctx_idx, unsigned int rq_idx,
163 unsigned int numa_node)
22404274 164{
a4aea562
MB		 165 struct nvme_dev *dev = data;
166 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
167 struct nvme_queue *nvmeq = dev->queues[0];
168
169 BUG_ON(!nvmeq);
170 cmd->nvmeq = nvmeq;
171 return 0;
22404274
KB		 172}
173
2c30540b
JA		 174static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
175{
176 struct nvme_queue *nvmeq = hctx->driver_data;
177
178 nvmeq->hctx = NULL;
179}
180
a4aea562
MB		 181static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
b60503ba 183{
a4aea562
MB		 184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[
186 (hctx_idx % dev->queue_count) + 1];
b60503ba 187
a4aea562
MB		 188 if (!nvmeq->hctx)
189 nvmeq->hctx = hctx;
190
191 /* nvmeq queues are shared between namespaces. We assume here that
192 * blk-mq map the tags so they match up with the nvme queue tags. */
193 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 194
a4aea562
MB		 195 hctx->driver_data = nvmeq;
196 return 0;
b60503ba
MW		 197}
198
a4aea562
MB		 199static int nvme_init_request(void *data, struct request *req,
200 unsigned int hctx_idx, unsigned int rq_idx,
201 unsigned int numa_node)
b60503ba 202{
a4aea562
MB		 203 struct nvme_dev *dev = data;
204 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
205 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
206
207 BUG_ON(!nvmeq);
208 cmd->nvmeq = nvmeq;
209 return 0;
210}
211
212static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
213 nvme_completion_fn handler)
214{
215 cmd->fn = handler;
216 cmd->ctx = ctx;
217 cmd->aborted = 0;
b60503ba
MW		 218}
219
c2f5b650
MW		 220/* Special values must be less than 0x1000 */
221#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 222#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
223#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
224#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 225
edd10d33 226static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 227 struct nvme_completion *cqe)
228{
229 if (ctx == CMD_CTX_CANCELLED)
230 return;
c2f5b650 231 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 232 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 233 "completed id %d twice on queue %d\n",
234 cqe->command_id, le16_to_cpup(&cqe->sq_id));
235 return;
236 }
237 if (ctx == CMD_CTX_INVALID) {
edd10d33 238 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 239 "invalid id %d completed on queue %d\n",
240 cqe->command_id, le16_to_cpup(&cqe->sq_id));
241 return;
242 }
edd10d33 243 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 244}
245
a4aea562 246static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 247{
c2f5b650 248 void *ctx;
b60503ba 249
859361a2 250 if (fn)
a4aea562
MB		 251 *fn = cmd->fn;
252 ctx = cmd->ctx;
253 cmd->fn = special_completion;
254 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 255 return ctx;
b60503ba
MW		 256}
257
a4aea562
MB		 258static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
259 struct nvme_completion *cqe)
3c0cf138 260{
a4aea562 261 struct request *req = ctx;
3c0cf138 262
a4aea562
MB		 263 u32 result = le32_to_cpup(&cqe->result);
264 u16 status = le16_to_cpup(&cqe->status) >> 1;
265
266 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
267 ++nvmeq->dev->event_limit;
268 if (status == NVME_SC_SUCCESS)
269 dev_warn(nvmeq->q_dmadev,
270 "async event result %08x\n", result);
271
9d135bb8 272 blk_mq_free_hctx_request(nvmeq->hctx, req);
b60503ba
MW		 273}
274
a4aea562
MB		 275static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
276 struct nvme_completion *cqe)
5a92e700 277{
a4aea562
MB		 278 struct request *req = ctx;
279
280 u16 status = le16_to_cpup(&cqe->status) >> 1;
281 u32 result = le32_to_cpup(&cqe->result);
a51afb54 282
9d135bb8 283 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 284
a4aea562
MB		 285 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
286 ++nvmeq->dev->abort_limit;
5a92e700
KB		 287}
288
a4aea562
MB		 289static void async_completion(struct nvme_queue *nvmeq, void *ctx,
290 struct nvme_completion *cqe)
b60503ba 291{
a4aea562
MB		 292 struct async_cmd_info *cmdinfo = ctx;
293 cmdinfo->result = le32_to_cpup(&cqe->result);
294 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
295 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 296 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 297}
298
a4aea562
MB		 299static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
300 unsigned int tag)
b60503ba 301{
a4aea562
MB		 302 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
303 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 304
a4aea562 305 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 306}
307
a4aea562
MB		 308/*
309 * Called with local interrupts disabled and the q_lock held. May not sleep.
310 */
311static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
312 nvme_completion_fn *fn)
4f5099af 313{
a4aea562
MB		 314 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
315 void *ctx;
316 if (tag >= nvmeq->q_depth) {
317 *fn = special_completion;
318 return CMD_CTX_INVALID;
319 }
320 if (fn)
321 *fn = cmd->fn;
322 ctx = cmd->ctx;
323 cmd->fn = special_completion;
324 cmd->ctx = CMD_CTX_COMPLETED;
325 return ctx;
b60503ba
MW		 326}
327
328/**
714a7a22 329 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 330 * @nvmeq: The queue to use
331 * @cmd: The command to send
332 *
333 * Safe to use from interrupt context
334 */
a4aea562 335static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 336{
a4aea562
MB		 337 u16 tail = nvmeq->sq_tail;
338
b60503ba 339 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 340 if (++tail == nvmeq->q_depth)
341 tail = 0;
7547881d 342 writel(tail, nvmeq->q_db);
b60503ba 343 nvmeq->sq_tail = tail;
b60503ba
MW		 344
345 return 0;
346}
347
a4aea562
MB		 348static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
349{
350 unsigned long flags;
351 int ret;
352 spin_lock_irqsave(&nvmeq->q_lock, flags);
353 ret = __nvme_submit_cmd(nvmeq, cmd);
354 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
355 return ret;
356}
357
eca18b23 358static __le64 **iod_list(struct nvme_iod *iod)
e025344c 359{
eca18b23 360 return ((void *)iod) + iod->offset;
e025344c
SMM		 361}
362
eca18b23
MW		 363/*
364 * Will slightly overestimate the number of pages needed. This is OK
365 * as it only leads to a small amount of wasted memory for the lifetime of
366 * the I/O.
367 */
1d090624 368static int nvme_npages(unsigned size, struct nvme_dev *dev)
eca18b23 369{
1d090624
KB		 370 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
371 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
eca18b23 372}
b60503ba 373
eca18b23 374static struct nvme_iod *
1d090624 375nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
b60503ba 376{
eca18b23 377 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
1d090624 378 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
eca18b23
MW		 379 sizeof(struct scatterlist) * nseg, gfp);
380
381 if (iod) {
382 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
383 iod->npages = -1;
384 iod->length = nbytes;
2b196034 385 iod->nents = 0;
edd10d33 386 iod->first_dma = 0ULL;
eca18b23
MW		 387 }
388
389 return iod;
b60503ba
MW		 390}
391
5d0f6131 392void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 393{
1d090624 394 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 395 int i;
396 __le64 **list = iod_list(iod);
397 dma_addr_t prp_dma = iod->first_dma;
398
399 if (iod->npages == 0)
400 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
401 for (i = 0; i < iod->npages; i++) {
402 __le64 *prp_list = list[i];
403 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
404 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
405 prp_dma = next_prp_dma;
406 }
407 kfree(iod);
b60503ba
MW		 408}
409
b4ff9c8d
KB		 410static int nvme_error_status(u16 status)
411{
412 switch (status & 0x7ff) {
413 case NVME_SC_SUCCESS:
414 return 0;
415 case NVME_SC_CAP_EXCEEDED:
416 return -ENOSPC;
417 default:
418 return -EIO;
419 }
420}
421
a4aea562 422static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 423 struct nvme_completion *cqe)
424{
eca18b23 425 struct nvme_iod *iod = ctx;
a4aea562
MB		 426 struct request *req = iod->private;
427 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
428
b60503ba
MW		 429 u16 status = le16_to_cpup(&cqe->status) >> 1;
430
edd10d33 431 if (unlikely(status)) {
a4aea562
MB		 432 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
433 && (jiffies - req->start_time) < req->timeout) {
434 blk_mq_requeue_request(req);
435 blk_mq_kick_requeue_list(req->q);
edd10d33
KB		 436 return;
437 }
a4aea562
MB		 438 req->errors = nvme_error_status(status);
439 } else
440 req->errors = 0;
441
442 if (cmd_rq->aborted)
443 dev_warn(&nvmeq->dev->pci_dev->dev,
444 "completing aborted command with status:%04x\n",
445 status);
446
447 if (iod->nents)
448 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
449 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
edd10d33 450 nvme_free_iod(nvmeq->dev, iod);
3291fa57 451
a4aea562 452 blk_mq_complete_request(req);
b60503ba
MW		 453}
454
184d2944 455/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 456int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
457 gfp_t gfp)
ff22b54f 458{
99802a7a 459 struct dma_pool *pool;
eca18b23
MW		 460 int length = total_len;
461 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 462 int dma_len = sg_dma_len(sg);
463 u64 dma_addr = sg_dma_address(sg);
464 int offset = offset_in_page(dma_addr);
e025344c 465 __le64 *prp_list;
eca18b23 466 __le64 **list = iod_list(iod);
e025344c 467 dma_addr_t prp_dma;
eca18b23 468 int nprps, i;
1d090624 469 u32 page_size = dev->page_size;
ff22b54f 470
1d090624 471 length -= (page_size - offset);
ff22b54f 472 if (length <= 0)
eca18b23 473 return total_len;
ff22b54f 474
1d090624 475 dma_len -= (page_size - offset);
ff22b54f 476 if (dma_len) {
1d090624 477 dma_addr += (page_size - offset);
ff22b54f
MW		 478 } else {
479 sg = sg_next(sg);
480 dma_addr = sg_dma_address(sg);
481 dma_len = sg_dma_len(sg);
482 }
483
1d090624 484 if (length <= page_size) {
edd10d33 485 iod->first_dma = dma_addr;
eca18b23 486 return total_len;
e025344c
SMM		 487 }
488
1d090624 489 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 490 if (nprps <= (256 / 8)) {
491 pool = dev->prp_small_pool;
eca18b23 492 iod->npages = 0;
99802a7a
MW		 493 } else {
494 pool = dev->prp_page_pool;
eca18b23 495 iod->npages = 1;
99802a7a
MW		 496 }
497
b77954cb
MW		 498 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
499 if (!prp_list) {
edd10d33 500 iod->first_dma = dma_addr;
eca18b23 501 iod->npages = -1;
1d090624 502 return (total_len - length) + page_size;
b77954cb 503 }
eca18b23
MW		 504 list[0] = prp_list;
505 iod->first_dma = prp_dma;
e025344c
SMM		 506 i = 0;
507 for (;;) {
1d090624 508 if (i == page_size >> 3) {
e025344c 509 __le64 *old_prp_list = prp_list;
b77954cb 510 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 511 if (!prp_list)
512 return total_len - length;
513 list[iod->npages++] = prp_list;
7523d834
MW		 514 prp_list[0] = old_prp_list[i - 1];
515 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
516 i = 1;
e025344c
SMM		 517 }
518 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 519 dma_len -= page_size;
520 dma_addr += page_size;
521 length -= page_size;
e025344c
SMM		 522 if (length <= 0)
523 break;
524 if (dma_len > 0)
525 continue;
526 BUG_ON(dma_len < 0);
527 sg = sg_next(sg);
528 dma_addr = sg_dma_address(sg);
529 dma_len = sg_dma_len(sg);
ff22b54f
MW		 530 }
531
eca18b23 532 return total_len;
ff22b54f
MW		 533}
534
a4aea562
MB		 535/*
536 * We reuse the small pool to allocate the 16-byte range here as it is not
537 * worth having a special pool for these or additional cases to handle freeing
538 * the iod.
539 */
540static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
541 struct request *req, struct nvme_iod *iod)
0e5e4f0e 542{
edd10d33
KB		 543 struct nvme_dsm_range *range =
544 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 545 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
546
0e5e4f0e 547 range->cattr = cpu_to_le32(0);
a4aea562
MB		 548 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
549 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 550
551 memset(cmnd, 0, sizeof(*cmnd));
552 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 553 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 554 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
555 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
556 cmnd->dsm.nr = 0;
557 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
558
559 if (++nvmeq->sq_tail == nvmeq->q_depth)
560 nvmeq->sq_tail = 0;
561 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 562}
563
a4aea562 564static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 565 int cmdid)
566{
567 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
568
569 memset(cmnd, 0, sizeof(*cmnd));
570 cmnd->common.opcode = nvme_cmd_flush;
571 cmnd->common.command_id = cmdid;
572 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
573
574 if (++nvmeq->sq_tail == nvmeq->q_depth)
575 nvmeq->sq_tail = 0;
576 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 577}
578
a4aea562
MB		 579static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
580 struct nvme_ns *ns)
b60503ba 581{
a4aea562 582 struct request *req = iod->private;
ff22b54f 583 struct nvme_command *cmnd;
a4aea562
MB		 584 u16 control = 0;
585 u32 dsmgmt = 0;
00df5cb4 586
a4aea562 587 if (req->cmd_flags & REQ_FUA)
b60503ba 588 control |= NVME_RW_FUA;
a4aea562 589 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 590 control |= NVME_RW_LR;
591
a4aea562 592 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 593 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
594
ff22b54f 595 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 596 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 597
a4aea562
MB		 598 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
599 cmnd->rw.command_id = req->tag;
ff22b54f 600 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 601 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
602 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 603 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
604 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
ff22b54f
MW		 605 cmnd->rw.control = cpu_to_le16(control);
606 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 607
b60503ba
MW		 608 if (++nvmeq->sq_tail == nvmeq->q_depth)
609 nvmeq->sq_tail = 0;
7547881d 610 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 611
1974b1ae 612 return 0;
edd10d33
KB		 613}
614
a4aea562
MB		 615static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
616 const struct blk_mq_queue_data *bd)
edd10d33 617{
a4aea562
MB		 618 struct nvme_ns *ns = hctx->queue->queuedata;
619 struct nvme_queue *nvmeq = hctx->driver_data;
620 struct request *req = bd->rq;
621 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 622 struct nvme_iod *iod;
a4aea562
MB		 623 int psegs = req->nr_phys_segments;
624 int result = BLK_MQ_RQ_QUEUE_BUSY;
625 enum dma_data_direction dma_dir;
626 unsigned size = !(req->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(req) :
9dbbfab7 627 sizeof(struct nvme_dsm_range);
edd10d33 628
a4aea562
MB		 629 /*
630 * Requeued IO has already been prepped
631 */
632 iod = req->special;
633 if (iod)
634 goto submit_iod;
edd10d33 635
9dbbfab7 636 iod = nvme_alloc_iod(psegs, size, ns->dev, GFP_ATOMIC);
edd10d33 637 if (!iod)
a4aea562
MB		 638 return result;
639
640 iod->private = req;
641 req->special = iod;
edd10d33 642
a4aea562
MB		 643 nvme_set_info(cmd, iod, req_completion);
644
645 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 646 void *range;
647 /*
648 * We reuse the small pool to allocate the 16-byte range here
649 * as it is not worth having a special pool for these or
650 * additional cases to handle freeing the iod.
651 */
652 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
653 GFP_ATOMIC,
654 &iod->first_dma);
a4aea562
MB		 655 if (!range)
656 goto finish_cmd;
edd10d33
KB		 657 iod_list(iod)[0] = (__le64 *)range;
658 iod->npages = 0;
659 } else if (psegs) {
a4aea562
MB		 660 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
661
662 sg_init_table(iod->sg, psegs);
663 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
664 if (!iod->nents) {
665 result = BLK_MQ_RQ_QUEUE_ERROR;
666 goto finish_cmd;
edd10d33 667 }
a4aea562
MB		 668
669 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
670 goto finish_cmd;
671
672 if (blk_rq_bytes(req) != nvme_setup_prps(nvmeq->dev, iod,
673 blk_rq_bytes(req), GFP_ATOMIC))
674 goto finish_cmd;
edd10d33 675 }
1974b1ae 676
a4aea562
MB		 677 blk_mq_start_request(req);
678
679 submit_iod:
680 spin_lock_irq(&nvmeq->q_lock);
681 if (req->cmd_flags & REQ_DISCARD)
682 nvme_submit_discard(nvmeq, ns, req, iod);
683 else if (req->cmd_flags & REQ_FLUSH)
684 nvme_submit_flush(nvmeq, ns, req->tag);
685 else
686 nvme_submit_iod(nvmeq, iod, ns);
687
688 nvme_process_cq(nvmeq);
689 spin_unlock_irq(&nvmeq->q_lock);
690 return BLK_MQ_RQ_QUEUE_OK;
691
692 finish_cmd:
693 nvme_finish_cmd(nvmeq, req->tag, NULL);
eca18b23 694 nvme_free_iod(nvmeq->dev, iod);
eeee3226 695 return result;
b60503ba
MW		 696}
697
e9539f47 698static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 699{
82123460 700 u16 head, phase;
b60503ba 701
b60503ba 702 head = nvmeq->cq_head;
82123460 703 phase = nvmeq->cq_phase;
b60503ba
MW		 704
705 for (;;) {
c2f5b650
MW		 706 void *ctx;
707 nvme_completion_fn fn;
b60503ba 708 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 709 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 710 break;
711 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
712 if (++head == nvmeq->q_depth) {
713 head = 0;
82123460 714 phase = !phase;
b60503ba 715 }
a4aea562 716 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 717 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 718 }
719
720 /* If the controller ignores the cq head doorbell and continuously
721 * writes to the queue, it is theoretically possible to wrap around
722 * the queue twice and mistakenly return IRQ_NONE. Linux only
723 * requires that 0.1% of your interrupts are handled, so this isn't
724 * a big problem.
725 */
82123460 726 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 727 return 0;
b60503ba 728
b80d5ccc 729 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 730 nvmeq->cq_head = head;
82123460 731 nvmeq->cq_phase = phase;
b60503ba 732
e9539f47
MW		 733 nvmeq->cqe_seen = 1;
734 return 1;
b60503ba
MW		 735}
736
a4aea562
MB		 737/* Admin queue isn't initialized as a request queue. If at some point this
738 * happens anyway, make sure to notify the user */
739static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
740 const struct blk_mq_queue_data *bd)
7d822457 741{
a4aea562
MB		 742 WARN_ON_ONCE(1);
743 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 744}
745
b60503ba 746static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 747{
748 irqreturn_t result;
749 struct nvme_queue *nvmeq = data;
750 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 751 nvme_process_cq(nvmeq);
752 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
753 nvmeq->cqe_seen = 0;
58ffacb5
MW		 754 spin_unlock(&nvmeq->q_lock);
755 return result;
756}
757
758static irqreturn_t nvme_irq_check(int irq, void *data)
759{
760 struct nvme_queue *nvmeq = data;
761 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
762 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
763 return IRQ_NONE;
764 return IRQ_WAKE_THREAD;
765}
766
a4aea562
MB		 767static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
768 cmd_info)
3c0cf138
MW		 769{
770 spin_lock_irq(&nvmeq->q_lock);
a4aea562 771 cancel_cmd_info(cmd_info, NULL);
3c0cf138
MW		 772 spin_unlock_irq(&nvmeq->q_lock);
773}
774
c2f5b650
MW		 775struct sync_cmd_info {
776 struct task_struct *task;
777 u32 result;
778 int status;
779};
780
edd10d33 781static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 782 struct nvme_completion *cqe)
783{
784 struct sync_cmd_info *cmdinfo = ctx;
785 cmdinfo->result = le32_to_cpup(&cqe->result);
786 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
787 wake_up_process(cmdinfo->task);
788}
789
b60503ba
MW		 790/*
791 * Returns 0 on success. If the result is negative, it's a Linux error code;
792 * if the result is positive, it's an NVM Express status code
793 */
a4aea562 794static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 795 u32 *result, unsigned timeout)
b60503ba 796{
a4aea562 797 int ret;
b60503ba 798 struct sync_cmd_info cmdinfo;
a4aea562
MB		 799 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
800 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 801
802 cmdinfo.task = current;
803 cmdinfo.status = -EINTR;
804
a4aea562
MB		 805 cmd->common.command_id = req->tag;
806
807 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 808
3c0cf138 809 set_current_state(TASK_KILLABLE);
4f5099af
KB		 810 ret = nvme_submit_cmd(nvmeq, cmd);
811 if (ret) {
a4aea562 812 nvme_finish_cmd(nvmeq, req->tag, NULL);
4f5099af 813 set_current_state(TASK_RUNNING);
4f5099af 814 }
78f8d257 815 schedule_timeout(timeout);
b60503ba 816
3c0cf138 817 if (cmdinfo.status == -EINTR) {
a4aea562 818 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
3c0cf138
MW		 819 return -EINTR;
820 }
821
b60503ba
MW		 822 if (result)
823 *result = cmdinfo.result;
824
825 return cmdinfo.status;
826}
827
a4aea562
MB		 828static int nvme_submit_async_admin_req(struct nvme_dev *dev)
829{
830 struct nvme_queue *nvmeq = dev->queues[0];
831 struct nvme_command c;
832 struct nvme_cmd_info *cmd_info;
833 struct request *req;
834
6dcc0cf6 835 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
9f173b33
DC		 836 if (IS_ERR(req))
837 return PTR_ERR(req);
a4aea562
MB		 838
839 cmd_info = blk_mq_rq_to_pdu(req);
840 nvme_set_info(cmd_info, req, async_req_completion);
841
842 memset(&c, 0, sizeof(c));
843 c.common.opcode = nvme_admin_async_event;
844 c.common.command_id = req->tag;
845
846 return __nvme_submit_cmd(nvmeq, &c);
847}
848
849static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 850 struct nvme_command *cmd,
851 struct async_cmd_info *cmdinfo, unsigned timeout)
852{
a4aea562
MB		 853 struct nvme_queue *nvmeq = dev->queues[0];
854 struct request *req;
855 struct nvme_cmd_info *cmd_rq;
4d115420 856
a4aea562 857 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 858 if (IS_ERR(req))
859 return PTR_ERR(req);
a4aea562
MB		 860
861 req->timeout = timeout;
862 cmd_rq = blk_mq_rq_to_pdu(req);
863 cmdinfo->req = req;
864 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 865 cmdinfo->status = -EINTR;
a4aea562
MB		 866
867 cmd->common.command_id = req->tag;
868
4f5099af 869 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 870}
871
a64e6bb4 872static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 873 u32 *result, unsigned timeout)
b60503ba 874{
a4aea562
MB		 875 int res;
876 struct request *req;
877
878 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
879 if (!req)
880 return -ENOMEM;
881 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 882 blk_mq_free_request(req);
a4aea562 883 return res;
4f5099af
KB		 884}
885
a4aea562 886int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 887 u32 *result)
888{
a4aea562 889 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 890}
891
a4aea562
MB		 892int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
893 struct nvme_command *cmd, u32 *result)
4d115420 894{
a4aea562
MB		 895 int res;
896 struct request *req;
897
898 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
899 false);
900 if (!req)
901 return -ENOMEM;
902 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 903 blk_mq_free_request(req);
a4aea562 904 return res;
4d115420
KB		 905}
906
b60503ba
MW		 907static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
908{
b60503ba
MW		 909 struct nvme_command c;
910
911 memset(&c, 0, sizeof(c));
912 c.delete_queue.opcode = opcode;
913 c.delete_queue.qid = cpu_to_le16(id);
914
a4aea562 915 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 916}
917
918static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
919 struct nvme_queue *nvmeq)
920{
b60503ba
MW		 921 struct nvme_command c;
922 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
923
924 memset(&c, 0, sizeof(c));
925 c.create_cq.opcode = nvme_admin_create_cq;
926 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
927 c.create_cq.cqid = cpu_to_le16(qid);
928 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
929 c.create_cq.cq_flags = cpu_to_le16(flags);
930 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
931
a4aea562 932 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 933}
934
935static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
936 struct nvme_queue *nvmeq)
937{
b60503ba
MW		 938 struct nvme_command c;
939 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
940
941 memset(&c, 0, sizeof(c));
942 c.create_sq.opcode = nvme_admin_create_sq;
943 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
944 c.create_sq.sqid = cpu_to_le16(qid);
945 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
946 c.create_sq.sq_flags = cpu_to_le16(flags);
947 c.create_sq.cqid = cpu_to_le16(qid);
948
a4aea562 949 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 950}
951
952static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
953{
954 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
955}
956
957static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
958{
959 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
960}
961
5d0f6131 962int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 963 dma_addr_t dma_addr)
964{
965 struct nvme_command c;
966
967 memset(&c, 0, sizeof(c));
968 c.identify.opcode = nvme_admin_identify;
969 c.identify.nsid = cpu_to_le32(nsid);
970 c.identify.prp1 = cpu_to_le64(dma_addr);
971 c.identify.cns = cpu_to_le32(cns);
972
973 return nvme_submit_admin_cmd(dev, &c, NULL);
974}
975
5d0f6131 976int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 977 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 978{
979 struct nvme_command c;
980
981 memset(&c, 0, sizeof(c));
982 c.features.opcode = nvme_admin_get_features;
a42cecce 983 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 984 c.features.prp1 = cpu_to_le64(dma_addr);
985 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 986
08df1e05 987 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 988}
989
5d0f6131
VV		 990int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
991 dma_addr_t dma_addr, u32 *result)
df348139
MW		 992{
993 struct nvme_command c;
994
995 memset(&c, 0, sizeof(c));
996 c.features.opcode = nvme_admin_set_features;
997 c.features.prp1 = cpu_to_le64(dma_addr);
998 c.features.fid = cpu_to_le32(fid);
999 c.features.dword11 = cpu_to_le32(dword11);
1000
bc5fc7e4
MW		 1001 return nvme_submit_admin_cmd(dev, &c, result);
1002}
1003
c30341dc 1004/**
a4aea562 1005 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1006 *
1007 * Schedule controller reset if the command was already aborted once before and
1008 * still hasn't been returned to the driver, or if this is the admin queue.
1009 */
a4aea562 1010static void nvme_abort_req(struct request *req)
c30341dc 1011{
a4aea562
MB		 1012 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1013 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1014 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1015 struct request *abort_req;
1016 struct nvme_cmd_info *abort_cmd;
1017 struct nvme_command cmd;
c30341dc 1018
a4aea562 1019 if (!nvmeq->qid || cmd_rq->aborted) {
c30341dc
KB		 1020 if (work_busy(&dev->reset_work))
1021 return;
1022 list_del_init(&dev->node);
1023 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1024 "I/O %d QID %d timeout, reset controller\n",
1025 req->tag, nvmeq->qid);
9ca97374 1026 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1027 queue_work(nvme_workq, &dev->reset_work);
1028 return;
1029 }
1030
1031 if (!dev->abort_limit)
1032 return;
1033
a4aea562
MB		 1034 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1035 false);
9f173b33 1036 if (IS_ERR(abort_req))
c30341dc
KB		 1037 return;
1038
a4aea562
MB		 1039 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1040 nvme_set_info(abort_cmd, abort_req, abort_completion);
1041
c30341dc
KB		 1042 memset(&cmd, 0, sizeof(cmd));
1043 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1044 cmd.abort.cid = req->tag;
c30341dc 1045 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1046 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1047
1048 --dev->abort_limit;
a4aea562 1049 cmd_rq->aborted = 1;
c30341dc 1050
a4aea562 1051 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1052 nvmeq->qid);
a4aea562
MB		 1053 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1054 dev_warn(nvmeq->q_dmadev,
1055 "Could not abort I/O %d QID %d",
1056 req->tag, nvmeq->qid);
9d135bb8 1057 blk_mq_free_request(req);
a4aea562 1058 }
c30341dc
KB		 1059}
1060
a4aea562
MB		 1061static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1062 struct request *req, void *data, bool reserved)
a09115b2 1063{
a4aea562
MB		 1064 struct nvme_queue *nvmeq = data;
1065 void *ctx;
1066 nvme_completion_fn fn;
1067 struct nvme_cmd_info *cmd;
1068 static struct nvme_completion cqe = {
1069 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
1070 };
a09115b2 1071
a4aea562 1072 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1073
a4aea562
MB		 1074 if (cmd->ctx == CMD_CTX_CANCELLED)
1075 return;
1076
1077 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1078 req->tag, nvmeq->qid);
1079 ctx = cancel_cmd_info(cmd, &fn);
1080 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1081}
1082
a4aea562 1083static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1084{
a4aea562
MB		 1085 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1086 struct nvme_queue *nvmeq = cmd->nvmeq;
1087
1088 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1089 nvmeq->qid);
1090 if (nvmeq->dev->initialized)
1091 nvme_abort_req(req);
1092
1093 /*
1094 * The aborted req will be completed on receiving the abort req.
1095 * We enable the timer again. If hit twice, it'll cause a device reset,
1096 * as the device then is in a faulty state.
1097 */
1098 return BLK_EH_RESET_TIMER;
1099}
22404274 1100
a4aea562
MB		 1101static void nvme_free_queue(struct nvme_queue *nvmeq)
1102{
9e866774
MW		 1103 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1104 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1105 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1106 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1107 kfree(nvmeq);
1108}
1109
a1a5ef99 1110static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274 1111{
f435c282
KB		 1112 LLIST_HEAD(q_list);
1113 struct nvme_queue *nvmeq, *next;
1114 struct llist_node *entry;
22404274
KB		 1115 int i;
1116
a1a5ef99 1117 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1118 struct nvme_queue *nvmeq = dev->queues[i];
f435c282 1119 llist_add(&nvmeq->node, &q_list);
22404274 1120 dev->queue_count--;
a4aea562 1121 dev->queues[i] = NULL;
22404274 1122 }
f435c282
KB		 1123 synchronize_rcu();
1124 entry = llist_del_all(&q_list);
1125 llist_for_each_entry_safe(nvmeq, next, entry, node)
1126 nvme_free_queue(nvmeq);
22404274
KB		 1127}
1128
4d115420
KB		 1129/**
1130 * nvme_suspend_queue - put queue into suspended state
1131 * @nvmeq - queue to suspend
4d115420
KB		 1132 */
1133static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1134{
4d115420 1135 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1136
a09115b2 1137 spin_lock_irq(&nvmeq->q_lock);
42f61420 1138 nvmeq->dev->online_queues--;
a09115b2
MW		 1139 spin_unlock_irq(&nvmeq->q_lock);
1140
aba2080f
MW		 1141 irq_set_affinity_hint(vector, NULL);
1142 free_irq(vector, nvmeq);
b60503ba 1143
4d115420
KB		 1144 return 0;
1145}
b60503ba 1146
4d115420
KB		 1147static void nvme_clear_queue(struct nvme_queue *nvmeq)
1148{
a4aea562
MB		 1149 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1150
22404274
KB		 1151 spin_lock_irq(&nvmeq->q_lock);
1152 nvme_process_cq(nvmeq);
a4aea562
MB		 1153 if (hctx && hctx->tags)
1154 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1155 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1156}
1157
4d115420
KB		 1158static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1159{
a4aea562 1160 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1161
1162 if (!nvmeq)
1163 return;
1164 if (nvme_suspend_queue(nvmeq))
1165 return;
1166
0e53d180
KB		 1167 /* Don't tell the adapter to delete the admin queue.
1168 * Don't tell a removed adapter to delete IO queues. */
1169 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1170 adapter_delete_sq(dev, qid);
1171 adapter_delete_cq(dev, qid);
1172 }
4d115420 1173 nvme_clear_queue(nvmeq);
b60503ba
MW		 1174}
1175
1176static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1177 int depth, int vector)
1178{
1179 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1180 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1181 if (!nvmeq)
1182 return NULL;
1183
4d51abf9
JP		 1184 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1185 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1186 if (!nvmeq->cqes)
1187 goto free_nvmeq;
b60503ba
MW		 1188
1189 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1190 &nvmeq->sq_dma_addr, GFP_KERNEL);
1191 if (!nvmeq->sq_cmds)
1192 goto free_cqdma;
1193
1194 nvmeq->q_dmadev = dmadev;
091b6092 1195 nvmeq->dev = dev;
3193f07b
MW		 1196 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1197 dev->instance, qid);
b60503ba
MW		 1198 spin_lock_init(&nvmeq->q_lock);
1199 nvmeq->cq_head = 0;
82123460 1200 nvmeq->cq_phase = 1;
b80d5ccc 1201 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1202 nvmeq->q_depth = depth;
1203 nvmeq->cq_vector = vector;
c30341dc 1204 nvmeq->qid = qid;
22404274 1205 dev->queue_count++;
a4aea562 1206 dev->queues[qid] = nvmeq;
b60503ba
MW		 1207
1208 return nvmeq;
1209
1210 free_cqdma:
68b8eca5 1211 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1212 nvmeq->cq_dma_addr);
1213 free_nvmeq:
1214 kfree(nvmeq);
1215 return NULL;
1216}
1217
3001082c
MW		 1218static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1219 const char *name)
1220{
58ffacb5
MW		 1221 if (use_threaded_interrupts)
1222 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1223 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1224 name, nvmeq);
3001082c 1225 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1226 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1227}
1228
22404274 1229static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1230{
22404274 1231 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1232
7be50e93 1233 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1234 nvmeq->sq_tail = 0;
1235 nvmeq->cq_head = 0;
1236 nvmeq->cq_phase = 1;
b80d5ccc 1237 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1238 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1239 dev->online_queues++;
7be50e93 1240 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1241}
1242
1243static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1244{
1245 struct nvme_dev *dev = nvmeq->dev;
1246 int result;
3f85d50b 1247
b60503ba
MW		 1248 result = adapter_alloc_cq(dev, qid, nvmeq);
1249 if (result < 0)
22404274 1250 return result;
b60503ba
MW		 1251
1252 result = adapter_alloc_sq(dev, qid, nvmeq);
1253 if (result < 0)
1254 goto release_cq;
1255
3193f07b 1256 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1257 if (result < 0)
1258 goto release_sq;
1259
22404274 1260 nvme_init_queue(nvmeq, qid);
22404274 1261 return result;
b60503ba
MW		 1262
1263 release_sq:
1264 adapter_delete_sq(dev, qid);
1265 release_cq:
1266 adapter_delete_cq(dev, qid);
22404274 1267 return result;
b60503ba
MW		 1268}
1269
ba47e386
MW		 1270static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1271{
1272 unsigned long timeout;
1273 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1274
1275 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1276
1277 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1278 msleep(100);
1279 if (fatal_signal_pending(current))
1280 return -EINTR;
1281 if (time_after(jiffies, timeout)) {
1282 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1283 "Device not ready; aborting %s\n", enabled ?
1284 "initialisation" : "reset");
ba47e386
MW		 1285 return -ENODEV;
1286 }
1287 }
1288
1289 return 0;
1290}
1291
1292/*
1293 * If the device has been passed off to us in an enabled state, just clear
1294 * the enabled bit. The spec says we should set the 'shutdown notification
1295 * bits', but doing so may cause the device to complete commands to the
1296 * admin queue ... and we don't know what memory that might be pointing at!
1297 */
1298static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1299{
01079522
DM		 1300 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1301 dev->ctrl_config &= ~NVME_CC_ENABLE;
1302 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1303
ba47e386
MW		 1304 return nvme_wait_ready(dev, cap, false);
1305}
1306
1307static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1308{
01079522
DM		 1309 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1310 dev->ctrl_config |= NVME_CC_ENABLE;
1311 writel(dev->ctrl_config, &dev->bar->cc);
1312
ba47e386
MW		 1313 return nvme_wait_ready(dev, cap, true);
1314}
1315
1894d8f1
KB		 1316static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1317{
1318 unsigned long timeout;
1894d8f1 1319
01079522
DM		 1320 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1321 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1322
1323 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1324
2484f407 1325 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1326 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1327 NVME_CSTS_SHST_CMPLT) {
1328 msleep(100);
1329 if (fatal_signal_pending(current))
1330 return -EINTR;
1331 if (time_after(jiffies, timeout)) {
1332 dev_err(&dev->pci_dev->dev,
1333 "Device shutdown incomplete; abort shutdown\n");
1334 return -ENODEV;
1335 }
1336 }
1337
1338 return 0;
1339}
1340
a4aea562
MB		 1341static struct blk_mq_ops nvme_mq_admin_ops = {
1342 .queue_rq = nvme_admin_queue_rq,
1343 .map_queue = blk_mq_map_queue,
1344 .init_hctx = nvme_admin_init_hctx,
2c30540b 1345 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1346 .init_request = nvme_admin_init_request,
1347 .timeout = nvme_timeout,
1348};
1349
1350static struct blk_mq_ops nvme_mq_ops = {
1351 .queue_rq = nvme_queue_rq,
1352 .map_queue = blk_mq_map_queue,
1353 .init_hctx = nvme_init_hctx,
2c30540b 1354 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1355 .init_request = nvme_init_request,
1356 .timeout = nvme_timeout,
1357};
1358
1359static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1360{
1361 if (!dev->admin_q) {
1362 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1363 dev->admin_tagset.nr_hw_queues = 1;
1364 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1365 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1366 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1367 dev->admin_tagset.cmd_size = sizeof(struct nvme_cmd_info);
1368 dev->admin_tagset.driver_data = dev;
1369
1370 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1371 return -ENOMEM;
1372
1373 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1374 if (!dev->admin_q) {
1375 blk_mq_free_tag_set(&dev->admin_tagset);
1376 return -ENOMEM;
1377 }
1378 }
1379
1380 return 0;
1381}
1382
1383static void nvme_free_admin_tags(struct nvme_dev *dev)
1384{
1385 if (dev->admin_q)
1386 blk_mq_free_tag_set(&dev->admin_tagset);
1387}
1388
8d85fce7 1389static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1390{
ba47e386 1391 int result;
b60503ba 1392 u32 aqa;
ba47e386 1393 u64 cap = readq(&dev->bar->cap);
b60503ba 1394 struct nvme_queue *nvmeq;
1d090624
KB		 1395 unsigned page_shift = PAGE_SHIFT;
1396 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1397 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1398
1399 if (page_shift < dev_page_min) {
1400 dev_err(&dev->pci_dev->dev,
1401 "Minimum device page size (%u) too large for "
1402 "host (%u)\n", 1 << dev_page_min,
1403 1 << page_shift);
1404 return -ENODEV;
1405 }
1406 if (page_shift > dev_page_max) {
1407 dev_info(&dev->pci_dev->dev,
1408 "Device maximum page size (%u) smaller than "
1409 "host (%u); enabling work-around\n",
1410 1 << dev_page_max, 1 << page_shift);
1411 page_shift = dev_page_max;
1412 }
b60503ba 1413
ba47e386
MW		 1414 result = nvme_disable_ctrl(dev, cap);
1415 if (result < 0)
1416 return result;
b60503ba 1417
a4aea562 1418 nvmeq = dev->queues[0];
cd638946 1419 if (!nvmeq) {
a4aea562 1420 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 0);
cd638946
KB		 1421 if (!nvmeq)
1422 return -ENOMEM;
cd638946 1423 }
b60503ba
MW		 1424
1425 aqa = nvmeq->q_depth - 1;
1426 aqa |= aqa << 16;
1427
1d090624
KB		 1428 dev->page_size = 1 << page_shift;
1429
01079522 1430 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1431 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1432 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1433 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1434
1435 writel(aqa, &dev->bar->aqa);
1436 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1437 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1438
ba47e386 1439 result = nvme_enable_ctrl(dev, cap);
025c557a 1440 if (result)
a4aea562
MB		 1441 goto free_nvmeq;
1442
1443 result = nvme_alloc_admin_tags(dev);
1444 if (result)
1445 goto free_nvmeq;
9e866774 1446
3193f07b 1447 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1448 if (result)
a4aea562 1449 goto free_tags;
025c557a 1450
b60503ba 1451 return result;
a4aea562
MB		 1452
1453 free_tags:
1454 nvme_free_admin_tags(dev);
1455 free_nvmeq:
1456 nvme_free_queues(dev, 0);
1457 return result;
b60503ba
MW		 1458}
1459
5d0f6131 1460struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1461 unsigned long addr, unsigned length)
b60503ba 1462{
36c14ed9 1463 int i, err, count, nents, offset;
7fc3cdab
MW		 1464 struct scatterlist *sg;
1465 struct page **pages;
eca18b23 1466 struct nvme_iod *iod;
36c14ed9
MW		 1467
1468 if (addr & 3)
eca18b23 1469 return ERR_PTR(-EINVAL);
5460fc03 1470 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1471 return ERR_PTR(-EINVAL);
7fc3cdab 1472
36c14ed9 1473 offset = offset_in_page(addr);
7fc3cdab
MW		 1474 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1475 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1476 if (!pages)
1477 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1478
1479 err = get_user_pages_fast(addr, count, 1, pages);
1480 if (err < count) {
1481 count = err;
1482 err = -EFAULT;
1483 goto put_pages;
1484 }
7fc3cdab 1485
6808c5fb 1486 err = -ENOMEM;
1d090624 1487 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
6808c5fb
S		 1488 if (!iod)
1489 goto put_pages;
1490
eca18b23 1491 sg = iod->sg;
36c14ed9 1492 sg_init_table(sg, count);
d0ba1e49
MW		 1493 for (i = 0; i < count; i++) {
1494 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1495 min_t(unsigned, length, PAGE_SIZE - offset),
1496 offset);
d0ba1e49
MW		 1497 length -= (PAGE_SIZE - offset);
1498 offset = 0;
7fc3cdab 1499 }
fe304c43 1500 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1501 iod->nents = count;
7fc3cdab 1502
7fc3cdab
MW		 1503 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1504 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1505 if (!nents)
eca18b23 1506 goto free_iod;
b60503ba 1507
7fc3cdab 1508 kfree(pages);
eca18b23 1509 return iod;
b60503ba 1510
eca18b23
MW		 1511 free_iod:
1512 kfree(iod);
7fc3cdab
MW		 1513 put_pages:
1514 for (i = 0; i < count; i++)
1515 put_page(pages[i]);
1516 kfree(pages);
eca18b23 1517 return ERR_PTR(err);
7fc3cdab 1518}
b60503ba 1519
5d0f6131 1520void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1521 struct nvme_iod *iod)
7fc3cdab 1522{
1c2ad9fa 1523 int i;
b60503ba 1524
1c2ad9fa
MW		 1525 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1526 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1527
1c2ad9fa
MW		 1528 for (i = 0; i < iod->nents; i++)
1529 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1530}
b60503ba 1531
a53295b6
MW		 1532static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1533{
1534 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1535 struct nvme_user_io io;
1536 struct nvme_command c;
f410c680
KB		 1537 unsigned length, meta_len;
1538 int status, i;
1539 struct nvme_iod *iod, *meta_iod = NULL;
1540 dma_addr_t meta_dma_addr;
1541 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1542
1543 if (copy_from_user(&io, uio, sizeof(io)))
1544 return -EFAULT;
6c7d4945 1545 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1546 meta_len = (io.nblocks + 1) * ns->ms;
1547
1548 if (meta_len && ((io.metadata & 3) || !io.metadata))
1549 return -EINVAL;
6c7d4945
MW		 1550
1551 switch (io.opcode) {
1552 case nvme_cmd_write:
1553 case nvme_cmd_read:
6bbf1acd 1554 case nvme_cmd_compare:
eca18b23 1555 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1556 break;
6c7d4945 1557 default:
6bbf1acd 1558 return -EINVAL;
6c7d4945
MW		 1559 }
1560
eca18b23
MW		 1561 if (IS_ERR(iod))
1562 return PTR_ERR(iod);
a53295b6
MW		 1563
1564 memset(&c, 0, sizeof(c));
1565 c.rw.opcode = io.opcode;
1566 c.rw.flags = io.flags;
6c7d4945 1567 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1568 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1569 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1570 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1571 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1572 c.rw.reftag = cpu_to_le32(io.reftag);
1573 c.rw.apptag = cpu_to_le16(io.apptag);
1574 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1575
1576 if (meta_len) {
1b56749e
KB		 1577 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1578 meta_len);
f410c680
KB		 1579 if (IS_ERR(meta_iod)) {
1580 status = PTR_ERR(meta_iod);
1581 meta_iod = NULL;
1582 goto unmap;
1583 }
1584
1585 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1586 &meta_dma_addr, GFP_KERNEL);
1587 if (!meta_mem) {
1588 status = -ENOMEM;
1589 goto unmap;
1590 }
1591
1592 if (io.opcode & 1) {
1593 int meta_offset = 0;
1594
1595 for (i = 0; i < meta_iod->nents; i++) {
1596 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1597 meta_iod->sg[i].offset;
1598 memcpy(meta_mem + meta_offset, meta,
1599 meta_iod->sg[i].length);
1600 kunmap_atomic(meta);
1601 meta_offset += meta_iod->sg[i].length;
1602 }
1603 }
1604
1605 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1606 }
1607
edd10d33
KB		 1608 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1609 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1610 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1611
b77954cb
MW		 1612 if (length != (io.nblocks + 1) << ns->lba_shift)
1613 status = -ENOMEM;
1614 else
a4aea562 1615 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1616
f410c680
KB		 1617 if (meta_len) {
1618 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1619 int meta_offset = 0;
1620
1621 for (i = 0; i < meta_iod->nents; i++) {
1622 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1623 meta_iod->sg[i].offset;
1624 memcpy(meta, meta_mem + meta_offset,
1625 meta_iod->sg[i].length);
1626 kunmap_atomic(meta);
1627 meta_offset += meta_iod->sg[i].length;
1628 }
1629 }
1630
1631 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1632 meta_dma_addr);
1633 }
1634
1635 unmap:
1c2ad9fa 1636 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1637 nvme_free_iod(dev, iod);
f410c680
KB		 1638
1639 if (meta_iod) {
1640 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1641 nvme_free_iod(dev, meta_iod);
1642 }
1643
a53295b6
MW		 1644 return status;
1645}
1646
a4aea562
MB		 1647static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1648 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1649{
7963e521 1650 struct nvme_passthru_cmd cmd;
6ee44cdc 1651 struct nvme_command c;
eca18b23 1652 int status, length;
c7d36ab8 1653 struct nvme_iod *uninitialized_var(iod);
94f370ca 1654 unsigned timeout;
6ee44cdc 1655
6bbf1acd
MW		 1656 if (!capable(CAP_SYS_ADMIN))
1657 return -EACCES;
1658 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1659 return -EFAULT;
6ee44cdc
MW		 1660
1661 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1662 c.common.opcode = cmd.opcode;
1663 c.common.flags = cmd.flags;
1664 c.common.nsid = cpu_to_le32(cmd.nsid);
1665 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1666 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1667 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1668 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1669 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1670 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1671 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1672 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1673
1674 length = cmd.data_len;
1675 if (cmd.data_len) {
49742188
MW		 1676 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1677 length);
eca18b23
MW		 1678 if (IS_ERR(iod))
1679 return PTR_ERR(iod);
edd10d33
KB		 1680 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1681 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1682 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1683 }
1684
94f370ca
KB		 1685 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1686 ADMIN_TIMEOUT;
a4aea562 1687
6bbf1acd 1688 if (length != cmd.data_len)
b77954cb 1689 status = -ENOMEM;
a4aea562
MB		 1690 else if (ns) {
1691 struct request *req;
1692
1693 req = blk_mq_alloc_request(ns->queue, WRITE,
1694 (GFP_KERNEL|__GFP_WAIT), false);
1695 if (!req)
1696 status = -ENOMEM;
1697 else {
1698 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1699 timeout);
9d135bb8 1700 blk_mq_free_request(req);
a4aea562
MB		 1701 }
1702 } else
1703 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1704
6bbf1acd 1705 if (cmd.data_len) {
1c2ad9fa 1706 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1707 nvme_free_iod(dev, iod);
6bbf1acd 1708 }
f4f117f6 1709
cf90bc48 1710 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1711 sizeof(cmd.result)))
1712 status = -EFAULT;
1713
6ee44cdc
MW		 1714 return status;
1715}
1716
b60503ba
MW		 1717static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1718 unsigned long arg)
1719{
1720 struct nvme_ns *ns = bdev->bd_disk->private_data;
1721
1722 switch (cmd) {
6bbf1acd 1723 case NVME_IOCTL_ID:
c3bfe717 1724 force_successful_syscall_return();
6bbf1acd
MW		 1725 return ns->ns_id;
1726 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1727 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1728 case NVME_IOCTL_IO_CMD:
a4aea562 1729 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1730 case NVME_IOCTL_SUBMIT_IO:
1731 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1732 case SG_GET_VERSION_NUM:
1733 return nvme_sg_get_version_num((void __user *)arg);
1734 case SG_IO:
1735 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1736 default:
1737 return -ENOTTY;
1738 }
1739}
1740
320a3827
KB		 1741#ifdef CONFIG_COMPAT
1742static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1743 unsigned int cmd, unsigned long arg)
1744{
320a3827
KB		 1745 switch (cmd) {
1746 case SG_IO:
e179729a 1747 return -ENOIOCTLCMD;
320a3827
KB		 1748 }
1749 return nvme_ioctl(bdev, mode, cmd, arg);
1750}
1751#else
1752#define nvme_compat_ioctl NULL
1753#endif
1754
9ac27090
KB		 1755static int nvme_open(struct block_device *bdev, fmode_t mode)
1756{
9e60352c
KB		 1757 int ret = 0;
1758 struct nvme_ns *ns;
9ac27090 1759
9e60352c
KB		 1760 spin_lock(&dev_list_lock);
1761 ns = bdev->bd_disk->private_data;
1762 if (!ns)
1763 ret = -ENXIO;
1764 else if (!kref_get_unless_zero(&ns->dev->kref))
1765 ret = -ENXIO;
1766 spin_unlock(&dev_list_lock);
1767
1768 return ret;
9ac27090
KB		 1769}
1770
1771static void nvme_free_dev(struct kref *kref);
1772
1773static void nvme_release(struct gendisk *disk, fmode_t mode)
1774{
1775 struct nvme_ns *ns = disk->private_data;
1776 struct nvme_dev *dev = ns->dev;
1777
1778 kref_put(&dev->kref, nvme_free_dev);
1779}
1780
4cc09e2d
KB		 1781static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1782{
1783 /* some standard values */
1784 geo->heads = 1 << 6;
1785 geo->sectors = 1 << 5;
1786 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1787 return 0;
1788}
1789
1b9dbf7f
KB		 1790static int nvme_revalidate_disk(struct gendisk *disk)
1791{
1792 struct nvme_ns *ns = disk->private_data;
1793 struct nvme_dev *dev = ns->dev;
1794 struct nvme_id_ns *id;
1795 dma_addr_t dma_addr;
1796 int lbaf;
1797
1798 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1799 GFP_KERNEL);
1800 if (!id) {
1801 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1802 __func__);
1803 return 0;
1804 }
1805
1806 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1807 goto free;
1808
1809 lbaf = id->flbas & 0xf;
1810 ns->lba_shift = id->lbaf[lbaf].ds;
1811
1812 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1813 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1814 free:
1815 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1816 return 0;
1817}
1818
b60503ba
MW		 1819static const struct block_device_operations nvme_fops = {
1820 .owner = THIS_MODULE,
1821 .ioctl = nvme_ioctl,
320a3827 1822 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1823 .open = nvme_open,
1824 .release = nvme_release,
4cc09e2d 1825 .getgeo = nvme_getgeo,
1b9dbf7f 1826 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 1827};
1828
1fa6aead
MW		 1829static int nvme_kthread(void *data)
1830{
d4b4ff8e 1831 struct nvme_dev *dev, *next;
1fa6aead
MW		 1832
1833 while (!kthread_should_stop()) {
564a232c 1834 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1835 spin_lock(&dev_list_lock);
d4b4ff8e 1836 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1837 int i;
d4b4ff8e
KB		 1838 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1839 dev->initialized) {
1840 if (work_busy(&dev->reset_work))
1841 continue;
1842 list_del_init(&dev->node);
1843 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1844 "Failed status: %x, reset controller\n",
1845 readl(&dev->bar->csts));
9ca97374 1846 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1847 queue_work(nvme_workq, &dev->reset_work);
1848 continue;
1849 }
1fa6aead 1850 for (i = 0; i < dev->queue_count; i++) {
a4aea562 1851 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1852 if (!nvmeq)
1853 continue;
1fa6aead 1854 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 1855 nvme_process_cq(nvmeq);
6fccf938
KB		 1856
1857 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 1858 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 1859 break;
1860 dev->event_limit--;
1861 }
1fa6aead
MW		 1862 spin_unlock_irq(&nvmeq->q_lock);
1863 }
1864 }
1865 spin_unlock(&dev_list_lock);
acb7aa0d 1866 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1867 }
1868 return 0;
1869}
1870
0e5e4f0e
KB		 1871static void nvme_config_discard(struct nvme_ns *ns)
1872{
1873 u32 logical_block_size = queue_logical_block_size(ns->queue);
1874 ns->queue->limits.discard_zeroes_data = 0;
1875 ns->queue->limits.discard_alignment = logical_block_size;
1876 ns->queue->limits.discard_granularity = logical_block_size;
1877 ns->queue->limits.max_discard_sectors = 0xffffffff;
1878 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1879}
1880
c3bfe717 1881static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1882 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1883{
1884 struct nvme_ns *ns;
1885 struct gendisk *disk;
a4aea562 1886 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba
MW		 1887 int lbaf;
1888
1889 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1890 return NULL;
1891
a4aea562 1892 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba
MW		 1893 if (!ns)
1894 return NULL;
a4aea562 1895 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 1896 if (IS_ERR(ns->queue))
b60503ba 1897 goto out_free_ns;
4eeb9215
MW		 1898 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1899 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 1900 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 1901 ns->dev = dev;
1902 ns->queue->queuedata = ns;
1903
a4aea562 1904 disk = alloc_disk_node(0, node);
b60503ba
MW		 1905 if (!disk)
1906 goto out_free_queue;
a4aea562 1907
5aff9382 1908 ns->ns_id = nsid;
b60503ba
MW		 1909 ns->disk = disk;
1910 lbaf = id->flbas & 0xf;
1911 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1912 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1913 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1914 if (dev->max_hw_sectors)
1915 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 1916 if (dev->stripe_size)
1917 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 1918 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1919 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 1920
1921 disk->major = nvme_major;
469071a3 1922 disk->first_minor = 0;
b60503ba
MW		 1923 disk->fops = &nvme_fops;
1924 disk->private_data = ns;
1925 disk->queue = ns->queue;
388f037f 1926 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1927 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1928 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1929 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1930
0e5e4f0e
KB		 1931 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1932 nvme_config_discard(ns);
1933
b60503ba
MW		 1934 return ns;
1935
1936 out_free_queue:
1937 blk_cleanup_queue(ns->queue);
1938 out_free_ns:
1939 kfree(ns);
1940 return NULL;
1941}
1942
42f61420
KB		 1943static void nvme_create_io_queues(struct nvme_dev *dev)
1944{
a4aea562 1945 unsigned i;
42f61420 1946
a4aea562 1947 for (i = dev->queue_count; i <= dev->max_qid; i++)
42f61420
KB		 1948 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1949 break;
1950
a4aea562
MB		 1951 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1952 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 1953 break;
1954}
1955
b3b06812 1956static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1957{
1958 int status;
1959 u32 result;
b3b06812 1960 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1961
df348139 1962 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1963 &result);
27e8166c
MW		 1964 if (status < 0)
1965 return status;
1966 if (status > 0) {
1967 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
1968 status);
badc34d4 1969 return 0;
27e8166c 1970 }
b60503ba
MW		 1971 return min(result & 0xffff, result >> 16) + 1;
1972}
1973
9d713c2b
KB		 1974static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1975{
b80d5ccc 1976 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 1977}
1978
8d85fce7 1979static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1980{
a4aea562 1981 struct nvme_queue *adminq = dev->queues[0];
fa08a396 1982 struct pci_dev *pdev = dev->pci_dev;
42f61420 1983 int result, i, vecs, nr_io_queues, size;
b60503ba 1984
42f61420 1985 nr_io_queues = num_possible_cpus();
b348b7d5 1986 result = set_queue_count(dev, nr_io_queues);
badc34d4 1987 if (result <= 0)
1b23484b 1988 return result;
b348b7d5
MW		 1989 if (result < nr_io_queues)
1990 nr_io_queues = result;
b60503ba 1991
9d713c2b
KB		 1992 size = db_bar_size(dev, nr_io_queues);
1993 if (size > 8192) {
f1938f6e 1994 iounmap(dev->bar);
9d713c2b
KB		 1995 do {
1996 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1997 if (dev->bar)
1998 break;
1999 if (!--nr_io_queues)
2000 return -ENOMEM;
2001 size = db_bar_size(dev, nr_io_queues);
2002 } while (1);
f1938f6e 2003 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2004 adminq->q_db = dev->dbs;
f1938f6e
MW		 2005 }
2006
9d713c2b 2007 /* Deregister the admin queue's interrupt */
3193f07b 2008 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2009
e32efbfc
JA		 2010 /*
2011 * If we enable msix early due to not intx, disable it again before
2012 * setting up the full range we need.
2013 */
2014 if (!pdev->irq)
2015 pci_disable_msix(pdev);
2016
be577fab 2017 for (i = 0; i < nr_io_queues; i++)
1b23484b 2018 dev->entry[i].entry = i;
be577fab
AG		 2019 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2020 if (vecs < 0) {
2021 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2022 if (vecs < 0) {
2023 vecs = 1;
2024 } else {
2025 for (i = 0; i < vecs; i++)
2026 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2027 }
2028 }
2029
063a8096
MW		 2030 /*
2031 * Should investigate if there's a performance win from allocating
2032 * more queues than interrupt vectors; it might allow the submission
2033 * path to scale better, even if the receive path is limited by the
2034 * number of interrupts.
2035 */
2036 nr_io_queues = vecs;
42f61420 2037 dev->max_qid = nr_io_queues;
063a8096 2038
3193f07b 2039 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2040 if (result)
22404274 2041 goto free_queues;
1b23484b 2042
cd638946 2043 /* Free previously allocated queues that are no longer usable */
42f61420 2044 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2045 nvme_create_io_queues(dev);
9ecdc946 2046
22404274 2047 return 0;
b60503ba 2048
22404274 2049 free_queues:
a1a5ef99 2050 nvme_free_queues(dev, 1);
22404274 2051 return result;
b60503ba
MW		 2052}
2053
422ef0c7
MW		 2054/*
2055 * Return: error value if an error occurred setting up the queues or calling
2056 * Identify Device. 0 if these succeeded, even if adding some of the
2057 * namespaces failed. At the moment, these failures are silent. TBD which
2058 * failures should be reported.
2059 */
8d85fce7 2060static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2061{
68608c26 2062 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2063 int res;
2064 unsigned nn, i;
cbb6218f 2065 struct nvme_ns *ns;
51814232 2066 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2067 struct nvme_id_ns *id_ns;
2068 void *mem;
b60503ba 2069 dma_addr_t dma_addr;
159b67d7 2070 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2071
68608c26 2072 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2073 if (!mem)
2074 return -ENOMEM;
b60503ba 2075
bc5fc7e4 2076 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2077 if (res) {
27e8166c 2078 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2079 res = -EIO;
cbb6218f 2080 goto out;
b60503ba
MW		 2081 }
2082
bc5fc7e4 2083 ctrl = mem;
51814232 2084 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2085 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2086 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2087 dev->vwc = ctrl->vwc;
6fccf938 2088 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW		 2089 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2090 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2091 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2092 if (ctrl->mdts)
8fc23e03 2093 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2094 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2095 (pdev->device == 0x0953) && ctrl->vs[3]) {
2096 unsigned int max_hw_sectors;
2097
159b67d7 2098 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2099 max_hw_sectors = dev->stripe_size >> (shift - 9);
2100 if (dev->max_hw_sectors) {
2101 dev->max_hw_sectors = min(max_hw_sectors,
2102 dev->max_hw_sectors);
2103 } else
2104 dev->max_hw_sectors = max_hw_sectors;
2105 }
2106
2107 dev->tagset.ops = &nvme_mq_ops;
2108 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2109 dev->tagset.timeout = NVME_IO_TIMEOUT;
2110 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2111 dev->tagset.queue_depth =
2112 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2113 dev->tagset.cmd_size = sizeof(struct nvme_cmd_info);
2114 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2115 dev->tagset.driver_data = dev;
2116
2117 if (blk_mq_alloc_tag_set(&dev->tagset))
2118 goto out;
b60503ba 2119
bc5fc7e4 2120 id_ns = mem;
2b2c1896 2121 for (i = 1; i <= nn; i++) {
bc5fc7e4 2122 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2123 if (res)
2124 continue;
2125
bc5fc7e4 2126 if (id_ns->ncap == 0)
b60503ba
MW		 2127 continue;
2128
bc5fc7e4 2129 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2130 dma_addr + 4096, NULL);
b60503ba 2131 if (res)
12209036 2132 memset(mem + 4096, 0, 4096);
b60503ba 2133
bc5fc7e4 2134 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2135 if (ns)
2136 list_add_tail(&ns->list, &dev->namespaces);
2137 }
2138 list_for_each_entry(ns, &dev->namespaces, list)
2139 add_disk(ns->disk);
422ef0c7 2140 res = 0;
b60503ba 2141
bc5fc7e4 2142 out:
684f5c20 2143 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2144 return res;
2145}
2146
0877cb0d
KB		 2147static int nvme_dev_map(struct nvme_dev *dev)
2148{
42f61420 2149 u64 cap;
0877cb0d
KB		 2150 int bars, result = -ENOMEM;
2151 struct pci_dev *pdev = dev->pci_dev;
2152
2153 if (pci_enable_device_mem(pdev))
2154 return result;
2155
2156 dev->entry[0].vector = pdev->irq;
2157 pci_set_master(pdev);
2158 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2159 if (!bars)
2160 goto disable_pci;
2161
0877cb0d
KB		 2162 if (pci_request_selected_regions(pdev, bars, "nvme"))
2163 goto disable_pci;
2164
052d0efa
RK		 2165 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2166 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2167 goto disable;
0877cb0d 2168
0877cb0d
KB		 2169 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2170 if (!dev->bar)
2171 goto disable;
e32efbfc 2172
0e53d180
KB		 2173 if (readl(&dev->bar->csts) == -1) {
2174 result = -ENODEV;
2175 goto unmap;
2176 }
e32efbfc
JA		 2177
2178 /*
2179 * Some devices don't advertse INTx interrupts, pre-enable a single
2180 * MSIX vec for setup. We'll adjust this later.
2181 */
2182 if (!pdev->irq) {
2183 result = pci_enable_msix(pdev, dev->entry, 1);
2184 if (result < 0)
2185 goto unmap;
2186 }
2187
42f61420
KB		 2188 cap = readq(&dev->bar->cap);
2189 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2190 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2191 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2192
2193 return 0;
2194
0e53d180
KB		 2195 unmap:
2196 iounmap(dev->bar);
2197 dev->bar = NULL;
0877cb0d
KB		 2198 disable:
2199 pci_release_regions(pdev);
2200 disable_pci:
2201 pci_disable_device(pdev);
2202 return result;
2203}
2204
2205static void nvme_dev_unmap(struct nvme_dev *dev)
2206{
2207 if (dev->pci_dev->msi_enabled)
2208 pci_disable_msi(dev->pci_dev);
2209 else if (dev->pci_dev->msix_enabled)
2210 pci_disable_msix(dev->pci_dev);
2211
2212 if (dev->bar) {
2213 iounmap(dev->bar);
2214 dev->bar = NULL;
9a6b9458 2215 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2216 }
2217
0877cb0d
KB		 2218 if (pci_is_enabled(dev->pci_dev))
2219 pci_disable_device(dev->pci_dev);
2220}
2221
4d115420
KB		 2222struct nvme_delq_ctx {
2223 struct task_struct *waiter;
2224 struct kthread_worker *worker;
2225 atomic_t refcount;
2226};
2227
2228static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2229{
2230 dq->waiter = current;
2231 mb();
2232
2233 for (;;) {
2234 set_current_state(TASK_KILLABLE);
2235 if (!atomic_read(&dq->refcount))
2236 break;
2237 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2238 fatal_signal_pending(current)) {
2239 set_current_state(TASK_RUNNING);
2240
2241 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2242 nvme_disable_queue(dev, 0);
2243
2244 send_sig(SIGKILL, dq->worker->task, 1);
2245 flush_kthread_worker(dq->worker);
2246 return;
2247 }
2248 }
2249 set_current_state(TASK_RUNNING);
2250}
2251
2252static void nvme_put_dq(struct nvme_delq_ctx *dq)
2253{
2254 atomic_dec(&dq->refcount);
2255 if (dq->waiter)
2256 wake_up_process(dq->waiter);
2257}
2258
2259static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2260{
2261 atomic_inc(&dq->refcount);
2262 return dq;
2263}
2264
2265static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2266{
2267 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2268
2269 nvme_clear_queue(nvmeq);
2270 nvme_put_dq(dq);
2271}
2272
2273static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2274 kthread_work_func_t fn)
2275{
2276 struct nvme_command c;
2277
2278 memset(&c, 0, sizeof(c));
2279 c.delete_queue.opcode = opcode;
2280 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2281
2282 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2283 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2284 ADMIN_TIMEOUT);
4d115420
KB		 2285}
2286
2287static void nvme_del_cq_work_handler(struct kthread_work *work)
2288{
2289 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2290 cmdinfo.work);
2291 nvme_del_queue_end(nvmeq);
2292}
2293
2294static int nvme_delete_cq(struct nvme_queue *nvmeq)
2295{
2296 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2297 nvme_del_cq_work_handler);
2298}
2299
2300static void nvme_del_sq_work_handler(struct kthread_work *work)
2301{
2302 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2303 cmdinfo.work);
2304 int status = nvmeq->cmdinfo.status;
2305
2306 if (!status)
2307 status = nvme_delete_cq(nvmeq);
2308 if (status)
2309 nvme_del_queue_end(nvmeq);
2310}
2311
2312static int nvme_delete_sq(struct nvme_queue *nvmeq)
2313{
2314 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2315 nvme_del_sq_work_handler);
2316}
2317
2318static void nvme_del_queue_start(struct kthread_work *work)
2319{
2320 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2321 cmdinfo.work);
2322 allow_signal(SIGKILL);
2323 if (nvme_delete_sq(nvmeq))
2324 nvme_del_queue_end(nvmeq);
2325}
2326
2327static void nvme_disable_io_queues(struct nvme_dev *dev)
2328{
2329 int i;
2330 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2331 struct nvme_delq_ctx dq;
2332 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2333 &worker, "nvme%d", dev->instance);
2334
2335 if (IS_ERR(kworker_task)) {
2336 dev_err(&dev->pci_dev->dev,
2337 "Failed to create queue del task\n");
2338 for (i = dev->queue_count - 1; i > 0; i--)
2339 nvme_disable_queue(dev, i);
2340 return;
2341 }
2342
2343 dq.waiter = NULL;
2344 atomic_set(&dq.refcount, 0);
2345 dq.worker = &worker;
2346 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2347 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2348
2349 if (nvme_suspend_queue(nvmeq))
2350 continue;
2351 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2352 nvmeq->cmdinfo.worker = dq.worker;
2353 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2354 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2355 }
2356 nvme_wait_dq(&dq, dev);
2357 kthread_stop(kworker_task);
2358}
2359
b9afca3e
DM		 2360/*
2361* Remove the node from the device list and check
2362* for whether or not we need to stop the nvme_thread.
2363*/
2364static void nvme_dev_list_remove(struct nvme_dev *dev)
2365{
2366 struct task_struct *tmp = NULL;
2367
2368 spin_lock(&dev_list_lock);
2369 list_del_init(&dev->node);
2370 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2371 tmp = nvme_thread;
2372 nvme_thread = NULL;
2373 }
2374 spin_unlock(&dev_list_lock);
2375
2376 if (tmp)
2377 kthread_stop(tmp);
2378}
2379
f0b50732 2380static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2381{
22404274 2382 int i;
7c1b2450 2383 u32 csts = -1;
22404274 2384
d4b4ff8e 2385 dev->initialized = 0;
b9afca3e 2386 nvme_dev_list_remove(dev);
1fa6aead 2387
7c1b2450
KB		 2388 if (dev->bar)
2389 csts = readl(&dev->bar->csts);
2390 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2391 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2392 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2393 nvme_suspend_queue(nvmeq);
2394 nvme_clear_queue(nvmeq);
2395 }
2396 } else {
2397 nvme_disable_io_queues(dev);
1894d8f1 2398 nvme_shutdown_ctrl(dev);
4d115420
KB		 2399 nvme_disable_queue(dev, 0);
2400 }
f0b50732
KB		 2401 nvme_dev_unmap(dev);
2402}
2403
a4aea562
MB		 2404static void nvme_dev_remove_admin(struct nvme_dev *dev)
2405{
2406 if (dev->admin_q && !blk_queue_dying(dev->admin_q))
2407 blk_cleanup_queue(dev->admin_q);
2408}
2409
f0b50732
KB		 2410static void nvme_dev_remove(struct nvme_dev *dev)
2411{
9ac27090 2412 struct nvme_ns *ns;
f0b50732 2413
9ac27090
KB		 2414 list_for_each_entry(ns, &dev->namespaces, list) {
2415 if (ns->disk->flags & GENHD_FL_UP)
2416 del_gendisk(ns->disk);
2417 if (!blk_queue_dying(ns->queue))
2418 blk_cleanup_queue(ns->queue);
b60503ba 2419 }
b60503ba
MW		 2420}
2421
091b6092
MW		 2422static int nvme_setup_prp_pools(struct nvme_dev *dev)
2423{
2424 struct device *dmadev = &dev->pci_dev->dev;
2425 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2426 PAGE_SIZE, PAGE_SIZE, 0);
2427 if (!dev->prp_page_pool)
2428 return -ENOMEM;
2429
99802a7a
MW		 2430 /* Optimisation for I/Os between 4k and 128k */
2431 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2432 256, 256, 0);
2433 if (!dev->prp_small_pool) {
2434 dma_pool_destroy(dev->prp_page_pool);
2435 return -ENOMEM;
2436 }
091b6092
MW		 2437 return 0;
2438}
2439
2440static void nvme_release_prp_pools(struct nvme_dev *dev)
2441{
2442 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2443 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2444}
2445
cd58ad7d
QSA		 2446static DEFINE_IDA(nvme_instance_ida);
2447
2448static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2449{
cd58ad7d
QSA		 2450 int instance, error;
2451
2452 do {
2453 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2454 return -ENODEV;
2455
2456 spin_lock(&dev_list_lock);
2457 error = ida_get_new(&nvme_instance_ida, &instance);
2458 spin_unlock(&dev_list_lock);
2459 } while (error == -EAGAIN);
2460
2461 if (error)
2462 return -ENODEV;
2463
2464 dev->instance = instance;
2465 return 0;
b60503ba
MW		 2466}
2467
2468static void nvme_release_instance(struct nvme_dev *dev)
2469{
cd58ad7d
QSA		 2470 spin_lock(&dev_list_lock);
2471 ida_remove(&nvme_instance_ida, dev->instance);
2472 spin_unlock(&dev_list_lock);
b60503ba
MW		 2473}
2474
9ac27090
KB		 2475static void nvme_free_namespaces(struct nvme_dev *dev)
2476{
2477 struct nvme_ns *ns, *next;
2478
2479 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2480 list_del(&ns->list);
9e60352c
KB		 2481
2482 spin_lock(&dev_list_lock);
2483 ns->disk->private_data = NULL;
2484 spin_unlock(&dev_list_lock);
2485
9ac27090
KB		 2486 put_disk(ns->disk);
2487 kfree(ns);
2488 }
2489}
2490
5e82e952
KB		 2491static void nvme_free_dev(struct kref *kref)
2492{
2493 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2494
a96d4f5c 2495 pci_dev_put(dev->pci_dev);
9ac27090 2496 nvme_free_namespaces(dev);
a4aea562 2497 blk_mq_free_tag_set(&dev->tagset);
5e82e952
KB		 2498 kfree(dev->queues);
2499 kfree(dev->entry);
2500 kfree(dev);
2501}
2502
2503static int nvme_dev_open(struct inode *inode, struct file *f)
2504{
2505 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2506 miscdev);
2507 kref_get(&dev->kref);
2508 f->private_data = dev;
2509 return 0;
2510}
2511
2512static int nvme_dev_release(struct inode *inode, struct file *f)
2513{
2514 struct nvme_dev *dev = f->private_data;
2515 kref_put(&dev->kref, nvme_free_dev);
2516 return 0;
2517}
2518
2519static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2520{
2521 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2522 struct nvme_ns *ns;
2523
5e82e952
KB		 2524 switch (cmd) {
2525 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2526 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2527 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2528 if (list_empty(&dev->namespaces))
2529 return -ENOTTY;
2530 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2531 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2532 default:
2533 return -ENOTTY;
2534 }
2535}
2536
2537static const struct file_operations nvme_dev_fops = {
2538 .owner = THIS_MODULE,
2539 .open = nvme_dev_open,
2540 .release = nvme_dev_release,
2541 .unlocked_ioctl = nvme_dev_ioctl,
2542 .compat_ioctl = nvme_dev_ioctl,
2543};
2544
a4aea562
MB		 2545static void nvme_set_irq_hints(struct nvme_dev *dev)
2546{
2547 struct nvme_queue *nvmeq;
2548 int i;
2549
2550 for (i = 0; i < dev->online_queues; i++) {
2551 nvmeq = dev->queues[i];
2552
2553 if (!nvmeq->hctx)
2554 continue;
2555
2556 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2557 nvmeq->hctx->cpumask);
2558 }
2559}
2560
f0b50732
KB		 2561static int nvme_dev_start(struct nvme_dev *dev)
2562{
2563 int result;
b9afca3e 2564 bool start_thread = false;
f0b50732
KB		 2565
2566 result = nvme_dev_map(dev);
2567 if (result)
2568 return result;
2569
2570 result = nvme_configure_admin_queue(dev);
2571 if (result)
2572 goto unmap;
2573
2574 spin_lock(&dev_list_lock);
b9afca3e
DM		 2575 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2576 start_thread = true;
2577 nvme_thread = NULL;
2578 }
f0b50732
KB		 2579 list_add(&dev->node, &dev_list);
2580 spin_unlock(&dev_list_lock);
2581
b9afca3e
DM		 2582 if (start_thread) {
2583 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2584 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2585 } else
2586 wait_event_killable(nvme_kthread_wait, nvme_thread);
2587
2588 if (IS_ERR_OR_NULL(nvme_thread)) {
2589 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2590 goto disable;
2591 }
a4aea562
MB		 2592
2593 nvme_init_queue(dev->queues[0], 0);
b9afca3e 2594
f0b50732 2595 result = nvme_setup_io_queues(dev);
badc34d4 2596 if (result)
f0b50732
KB		 2597 goto disable;
2598
a4aea562
MB		 2599 nvme_set_irq_hints(dev);
2600
d82e8bfd 2601 return result;
f0b50732
KB		 2602
2603 disable:
a1a5ef99 2604 nvme_disable_queue(dev, 0);
b9afca3e 2605 nvme_dev_list_remove(dev);
f0b50732
KB		 2606 unmap:
2607 nvme_dev_unmap(dev);
2608 return result;
2609}
2610
9a6b9458
KB		 2611static int nvme_remove_dead_ctrl(void *arg)
2612{
2613 struct nvme_dev *dev = (struct nvme_dev *)arg;
2614 struct pci_dev *pdev = dev->pci_dev;
2615
2616 if (pci_get_drvdata(pdev))
c81f4975 2617 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2618 kref_put(&dev->kref, nvme_free_dev);
2619 return 0;
2620}
2621
2622static void nvme_remove_disks(struct work_struct *ws)
2623{
9a6b9458
KB		 2624 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2625
5a92e700 2626 nvme_free_queues(dev, 1);
302c6727 2627 nvme_dev_remove(dev);
9a6b9458
KB		 2628}
2629
2630static int nvme_dev_resume(struct nvme_dev *dev)
2631{
2632 int ret;
2633
2634 ret = nvme_dev_start(dev);
badc34d4 2635 if (ret)
9a6b9458 2636 return ret;
badc34d4 2637 if (dev->online_queues < 2) {
9a6b9458 2638 spin_lock(&dev_list_lock);
9ca97374 2639 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2640 queue_work(nvme_workq, &dev->reset_work);
2641 spin_unlock(&dev_list_lock);
2642 }
d4b4ff8e 2643 dev->initialized = 1;
9a6b9458
KB		 2644 return 0;
2645}
2646
2647static void nvme_dev_reset(struct nvme_dev *dev)
2648{
2649 nvme_dev_shutdown(dev);
2650 if (nvme_dev_resume(dev)) {
a4aea562 2651 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2652 kref_get(&dev->kref);
2653 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2654 dev->instance))) {
2655 dev_err(&dev->pci_dev->dev,
2656 "Failed to start controller remove task\n");
2657 kref_put(&dev->kref, nvme_free_dev);
2658 }
2659 }
2660}
2661
2662static void nvme_reset_failed_dev(struct work_struct *ws)
2663{
2664 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2665 nvme_dev_reset(dev);
2666}
2667
9ca97374
TH		 2668static void nvme_reset_workfn(struct work_struct *work)
2669{
2670 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2671 dev->reset_workfn(work);
2672}
2673
8d85fce7 2674static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2675{
a4aea562 2676 int node, result = -ENOMEM;
b60503ba
MW		 2677 struct nvme_dev *dev;
2678
a4aea562
MB		 2679 node = dev_to_node(&pdev->dev);
2680 if (node == NUMA_NO_NODE)
2681 set_dev_node(&pdev->dev, 0);
2682
2683 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2684 if (!dev)
2685 return -ENOMEM;
a4aea562
MB		 2686 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2687 GFP_KERNEL, node);
b60503ba
MW		 2688 if (!dev->entry)
2689 goto free;
a4aea562
MB		 2690 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2691 GFP_KERNEL, node);
b60503ba
MW		 2692 if (!dev->queues)
2693 goto free;
2694
2695 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2696 dev->reset_workfn = nvme_reset_failed_dev;
2697 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2698 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2699 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2700 result = nvme_set_instance(dev);
2701 if (result)
a96d4f5c 2702 goto put_pci;
b60503ba 2703
091b6092
MW		 2704 result = nvme_setup_prp_pools(dev);
2705 if (result)
0877cb0d 2706 goto release;
091b6092 2707
fb35e914 2708 kref_init(&dev->kref);
f0b50732 2709 result = nvme_dev_start(dev);
badc34d4 2710 if (result)
0877cb0d 2711 goto release_pools;
b60503ba 2712
badc34d4
KB		 2713 if (dev->online_queues > 1)
2714 result = nvme_dev_add(dev);
d82e8bfd 2715 if (result)
f0b50732 2716 goto shutdown;
740216fc 2717
5e82e952
KB		 2718 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2719 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2720 dev->miscdev.parent = &pdev->dev;
2721 dev->miscdev.name = dev->name;
2722 dev->miscdev.fops = &nvme_dev_fops;
2723 result = misc_register(&dev->miscdev);
2724 if (result)
2725 goto remove;
2726
a4aea562
MB		 2727 nvme_set_irq_hints(dev);
2728
d4b4ff8e 2729 dev->initialized = 1;
b60503ba
MW		 2730 return 0;
2731
5e82e952
KB		 2732 remove:
2733 nvme_dev_remove(dev);
a4aea562 2734 nvme_dev_remove_admin(dev);
9ac27090 2735 nvme_free_namespaces(dev);
f0b50732
KB		 2736 shutdown:
2737 nvme_dev_shutdown(dev);
0877cb0d 2738 release_pools:
a1a5ef99 2739 nvme_free_queues(dev, 0);
091b6092 2740 nvme_release_prp_pools(dev);
0877cb0d
KB		 2741 release:
2742 nvme_release_instance(dev);
a96d4f5c
KB		 2743 put_pci:
2744 pci_dev_put(dev->pci_dev);
b60503ba
MW		 2745 free:
2746 kfree(dev->queues);
2747 kfree(dev->entry);
2748 kfree(dev);
2749 return result;
2750}
2751
f0d54a54
KB		 2752static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2753{
a6739479 2754 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2755
a6739479
KB		 2756 if (prepare)
2757 nvme_dev_shutdown(dev);
2758 else
2759 nvme_dev_resume(dev);
f0d54a54
KB		 2760}
2761
09ece142
KB		 2762static void nvme_shutdown(struct pci_dev *pdev)
2763{
2764 struct nvme_dev *dev = pci_get_drvdata(pdev);
2765 nvme_dev_shutdown(dev);
2766}
2767
8d85fce7 2768static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2769{
2770 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2771
2772 spin_lock(&dev_list_lock);
2773 list_del_init(&dev->node);
2774 spin_unlock(&dev_list_lock);
2775
2776 pci_set_drvdata(pdev, NULL);
2777 flush_work(&dev->reset_work);
5e82e952 2778 misc_deregister(&dev->miscdev);
a4aea562 2779 nvme_dev_remove(dev);
9a6b9458 2780 nvme_dev_shutdown(dev);
a4aea562 2781 nvme_dev_remove_admin(dev);
a1a5ef99 2782 nvme_free_queues(dev, 0);
a4aea562 2783 nvme_free_admin_tags(dev);
9a6b9458
KB		 2784 nvme_release_instance(dev);
2785 nvme_release_prp_pools(dev);
5e82e952 2786 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2787}
2788
2789/* These functions are yet to be implemented */
2790#define nvme_error_detected NULL
2791#define nvme_dump_registers NULL
2792#define nvme_link_reset NULL
2793#define nvme_slot_reset NULL
2794#define nvme_error_resume NULL
cd638946 2795
671a6018 2796#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2797static int nvme_suspend(struct device *dev)
2798{
2799 struct pci_dev *pdev = to_pci_dev(dev);
2800 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2801
2802 nvme_dev_shutdown(ndev);
2803 return 0;
2804}
2805
2806static int nvme_resume(struct device *dev)
2807{
2808 struct pci_dev *pdev = to_pci_dev(dev);
2809 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2810
9a6b9458 2811 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2812 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2813 queue_work(nvme_workq, &ndev->reset_work);
2814 }
2815 return 0;
cd638946 2816}
671a6018 2817#endif
cd638946
KB		 2818
2819static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2820
1d352035 2821static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2822 .error_detected = nvme_error_detected,
2823 .mmio_enabled = nvme_dump_registers,
2824 .link_reset = nvme_link_reset,
2825 .slot_reset = nvme_slot_reset,
2826 .resume = nvme_error_resume,
f0d54a54 2827 .reset_notify = nvme_reset_notify,
b60503ba
MW		 2828};
2829
2830/* Move to pci_ids.h later */
2831#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2832
6eb0d698 2833static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2834 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2835 { 0, }
2836};
2837MODULE_DEVICE_TABLE(pci, nvme_id_table);
2838
2839static struct pci_driver nvme_driver = {
2840 .name = "nvme",
2841 .id_table = nvme_id_table,
2842 .probe = nvme_probe,
8d85fce7 2843 .remove = nvme_remove,
09ece142 2844 .shutdown = nvme_shutdown,
cd638946
KB		 2845 .driver = {
2846 .pm = &nvme_dev_pm_ops,
2847 },
b60503ba
MW		 2848 .err_handler = &nvme_err_handler,
2849};
2850
2851static int __init nvme_init(void)
2852{
0ac13140 2853 int result;
1fa6aead 2854
b9afca3e 2855 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2856
9a6b9458
KB		 2857 nvme_workq = create_singlethread_workqueue("nvme");
2858 if (!nvme_workq)
b9afca3e 2859 return -ENOMEM;
9a6b9458 2860
5c42ea16
KB		 2861 result = register_blkdev(nvme_major, "nvme");
2862 if (result < 0)
9a6b9458 2863 goto kill_workq;
5c42ea16 2864 else if (result > 0)
0ac13140 2865 nvme_major = result;
b60503ba 2866
f3db22fe
KB		 2867 result = pci_register_driver(&nvme_driver);
2868 if (result)
a4aea562 2869 goto unregister_blkdev;
1fa6aead 2870 return 0;
b60503ba 2871
1fa6aead 2872 unregister_blkdev:
b60503ba 2873 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2874 kill_workq:
2875 destroy_workqueue(nvme_workq);
b60503ba
MW		 2876 return result;
2877}
2878
2879static void __exit nvme_exit(void)
2880{
2881 pci_unregister_driver(&nvme_driver);
f3db22fe 2882 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 2883 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2884 destroy_workqueue(nvme_workq);
b9afca3e 2885 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 2886 _nvme_check_size();
b60503ba
MW		 2887}
2888
2889MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2890MODULE_LICENSE("GPL");
6eb0d698 2891MODULE_VERSION("0.9");
b60503ba
MW		 2892module_init(nvme_init);
2893module_exit(nvme_exit);
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