]>
Commit | Line | Data |
---|---|---|
0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
7cba160a | 18 | #include <asm/cpuidle.h> |
da2bc464 | 19 | #include <asm/head-64.h> |
8aa34ab8 | 20 | |
0ebc4cda BH |
21 | /* |
22 | * We layout physical memory as follows: | |
23 | * 0x0000 - 0x00ff : Secondary processor spin code | |
c1fb6816 MN |
24 | * 0x0100 - 0x17ff : pSeries Interrupt prologs |
25 | * 0x1800 - 0x4000 : interrupt support common interrupt prologs | |
26 | * 0x4000 - 0x5fff : pSeries interrupts with IR=1,DR=1 | |
27 | * 0x6000 - 0x6fff : more interrupt support including for IR=1,DR=1 | |
0ebc4cda | 28 | * 0x7000 - 0x7fff : FWNMI data area |
c1fb6816 MN |
29 | * 0x8000 - 0x8fff : Initial (CPU0) segment table |
30 | * 0x9000 - : Early init and support code | |
0ebc4cda | 31 | */ |
742415d6 MN |
32 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ |
33 | #define SYSCALL_PSERIES_1 \ | |
34 | BEGIN_FTR_SECTION \ | |
35 | cmpdi r0,0x1ebe ; \ | |
36 | beq- 1f ; \ | |
37 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
38 | mr r9,r13 ; \ | |
39 | GET_PACA(r13) ; \ | |
40 | mfspr r11,SPRN_SRR0 ; \ | |
41 | 0: | |
42 | ||
43 | #define SYSCALL_PSERIES_2_RFID \ | |
44 | mfspr r12,SPRN_SRR1 ; \ | |
a24553dd | 45 | LOAD_HANDLER(r10, system_call_common) ; \ |
742415d6 MN |
46 | mtspr SPRN_SRR0,r10 ; \ |
47 | ld r10,PACAKMSR(r13) ; \ | |
48 | mtspr SPRN_SRR1,r10 ; \ | |
49 | rfid ; \ | |
50 | b . ; /* prevent speculative execution */ | |
51 | ||
52 | #define SYSCALL_PSERIES_3 \ | |
53 | /* Fast LE/BE switch system call */ \ | |
54 | 1: mfspr r12,SPRN_SRR1 ; \ | |
55 | xori r12,r12,MSR_LE ; \ | |
56 | mtspr SPRN_SRR1,r12 ; \ | |
57 | rfid ; /* return to userspace */ \ | |
742415d6 MN |
58 | b . ; /* prevent speculative execution */ |
59 | ||
4700dfaf MN |
60 | #if defined(CONFIG_RELOCATABLE) |
61 | /* | |
05b05f28 AB |
62 | * We can't branch directly so we do it via the CTR which |
63 | * is volatile across system calls. | |
4700dfaf MN |
64 | */ |
65 | #define SYSCALL_PSERIES_2_DIRECT \ | |
a24553dd | 66 | LOAD_HANDLER(r12, system_call_common) ; \ |
6a404806 | 67 | mtctr r12 ; \ |
4700dfaf | 68 | mfspr r12,SPRN_SRR1 ; \ |
18e3f56b NP |
69 | li r10,MSR_RI ; \ |
70 | mtmsrd r10,1 ; \ | |
6a404806 | 71 | bctr ; |
4700dfaf MN |
72 | #else |
73 | /* We can branch directly */ | |
74 | #define SYSCALL_PSERIES_2_DIRECT \ | |
75 | mfspr r12,SPRN_SRR1 ; \ | |
76 | li r10,MSR_RI ; \ | |
77 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
d20be433 | 78 | b system_call_common ; |
4700dfaf | 79 | #endif |
0ebc4cda | 80 | |
0ebc4cda BH |
81 | /* |
82 | * This is the start of the interrupt handlers for pSeries | |
83 | * This code runs with relocation off. | |
84 | * Code from here to __end_interrupts gets copied down to real | |
85 | * address 0x100 when we are running a relocatable kernel. | |
86 | * Therefore any relative branches in this section must only | |
87 | * branch to labels in this section. | |
88 | */ | |
89 | . = 0x100 | |
90 | .globl __start_interrupts | |
91 | __start_interrupts: | |
92 | ||
da2bc464 | 93 | EXC_REAL_BEGIN(system_reset, 0x100, 0x200) |
948cf67c BH |
94 | SET_SCRATCH0(r13) |
95 | #ifdef CONFIG_PPC_P7_NAP | |
96 | BEGIN_FTR_SECTION | |
97 | /* Running native on arch 2.06 or later, check if we are | |
77b54e9f | 98 | * waking up from nap/sleep/winkle. |
948cf67c BH |
99 | */ |
100 | mfspr r13,SPRN_SRR1 | |
371fefd6 PM |
101 | rlwinm. r13,r13,47-31,30,31 |
102 | beq 9f | |
103 | ||
7cba160a | 104 | cmpwi cr3,r13,2 |
371fefd6 | 105 | GET_PACA(r13) |
5fa6b6bd | 106 | bl pnv_restore_hyp_resource |
77b54e9f | 107 | |
7cba160a SP |
108 | li r0,PNV_THREAD_RUNNING |
109 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ | |
371fefd6 | 110 | |
3a167bea | 111 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
f0888f70 PM |
112 | li r0,KVM_HWTHREAD_IN_KERNEL |
113 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
114 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
115 | sync | |
116 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
117 | cmpwi r0,0 | |
118 | beq 1f | |
371fefd6 PM |
119 | b kvm_start_guest |
120 | 1: | |
121 | #endif | |
122 | ||
56548fc0 PM |
123 | /* Return SRR1 from power7_nap() */ |
124 | mfspr r3,SPRN_SRR1 | |
17065671 | 125 | blt cr3,2f |
5fa6b6bd SP |
126 | b pnv_wakeup_loss |
127 | 2: b pnv_wakeup_noloss | |
aca79d2b | 128 | |
371fefd6 | 129 | 9: |
969391c5 | 130 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
948cf67c | 131 | #endif /* CONFIG_PPC_P7_NAP */ |
b01c8b54 PM |
132 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
133 | NOTEST, 0x100) | |
da2bc464 | 134 | EXC_REAL_END(system_reset, 0x100, 0x200) |
0ebc4cda | 135 | |
da2bc464 | 136 | EXC_REAL_BEGIN(machine_check, 0x200, 0x300) |
b01c8b54 PM |
137 | /* This is moved out of line as it can be patched by FW, but |
138 | * some code path might still want to branch into the original | |
139 | * vector | |
140 | */ | |
1707dd16 | 141 | SET_SCRATCH0(r13) /* save r13 */ |
bc14c491 MS |
142 | /* |
143 | * Running native on arch 2.06 or later, we may wakeup from winkle | |
144 | * inside machine check. If yes, then last bit of HSPGR0 would be set | |
145 | * to 1. Hence clear it unconditionally. | |
1c51089f | 146 | */ |
bc14c491 MS |
147 | GET_PACA(r13) |
148 | clrrdi r13,r13,1 | |
149 | SET_PACA(r13) | |
1707dd16 | 150 | EXCEPTION_PROLOG_0(PACA_EXMC) |
1e9b4507 | 151 | BEGIN_FTR_SECTION |
2513767d | 152 | b machine_check_powernv_early |
1e9b4507 | 153 | FTR_SECTION_ELSE |
1707dd16 | 154 | b machine_check_pSeries_0 |
1e9b4507 | 155 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
da2bc464 | 156 | EXC_REAL_END(machine_check, 0x200, 0x300) |
0ebc4cda | 157 | |
da2bc464 | 158 | EXC_REAL(data_access, 0x300, 0x380) |
0ebc4cda | 159 | |
da2bc464 | 160 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400) |
673b189a | 161 | SET_SCRATCH0(r13) |
1707dd16 | 162 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 163 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
0ebc4cda BH |
164 | std r3,PACA_EXSLB+EX_R3(r13) |
165 | mfspr r3,SPRN_DAR | |
b01c8b54 | 166 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 167 | crset 4*cr6+eq |
0ebc4cda | 168 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 169 | b slb_miss_realmode |
0ebc4cda BH |
170 | #else |
171 | /* | |
ad0289e4 | 172 | * We can't just use a direct branch to slb_miss_realmode |
0ebc4cda BH |
173 | * because the distance from here to there depends on where |
174 | * the kernel ends up being put. | |
175 | */ | |
176 | mfctr r11 | |
ad0289e4 | 177 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
178 | mtctr r10 |
179 | bctr | |
180 | #endif | |
da2bc464 | 181 | EXC_REAL_END(data_access_slb, 0x380, 0x400) |
0ebc4cda | 182 | |
da2bc464 | 183 | EXC_REAL(instruction_access, 0x400, 0x480) |
0ebc4cda | 184 | |
da2bc464 | 185 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500) |
673b189a | 186 | SET_SCRATCH0(r13) |
1707dd16 | 187 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 188 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
189 | std r3,PACA_EXSLB+EX_R3(r13) |
190 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
b01c8b54 | 191 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 192 | crclr 4*cr6+eq |
0ebc4cda | 193 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 194 | b slb_miss_realmode |
0ebc4cda BH |
195 | #else |
196 | mfctr r11 | |
ad0289e4 | 197 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
198 | mtctr r10 |
199 | bctr | |
200 | #endif | |
da2bc464 | 201 | EXC_REAL_END(instruction_access_slb, 0x480, 0x500) |
0ebc4cda | 202 | |
b3e6b5df BH |
203 | /* We open code these as we can't have a ". = x" (even with |
204 | * x = "." within a feature section | |
205 | */ | |
da2bc464 | 206 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600) |
b3e6b5df | 207 | .globl hardware_interrupt_hv; |
b3e6b5df | 208 | hardware_interrupt_hv: |
a5d4f3ad | 209 | BEGIN_FTR_SECTION |
da2bc464 | 210 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
b01c8b54 | 211 | EXC_HV, SOFTEN_TEST_HV) |
da2bc464 | 212 | do_kvm_H0x500: |
b01c8b54 | 213 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) |
de56a948 | 214 | FTR_SECTION_ELSE |
da2bc464 | 215 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
31a40e2b | 216 | EXC_STD, SOFTEN_TEST_PR) |
da2bc464 | 217 | do_kvm_0x500: |
de56a948 | 218 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
969391c5 | 219 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
da2bc464 ME |
220 | EXC_REAL_END(hardware_interrupt, 0x500, 0x600) |
221 | ||
222 | EXC_REAL(alignment, 0x600, 0x700) | |
223 | ||
224 | TRAMP_KVM(PACA_EXGEN, 0x600) | |
225 | ||
226 | EXC_REAL(program_check, 0x700, 0x800) | |
a5d4f3ad | 227 | |
da2bc464 | 228 | TRAMP_KVM(PACA_EXGEN, 0x700) |
b01c8b54 | 229 | |
da2bc464 | 230 | EXC_REAL(fp_unavailable, 0x800, 0x900) |
b01c8b54 | 231 | |
da2bc464 | 232 | TRAMP_KVM(PACA_EXGEN, 0x800) |
a5d4f3ad | 233 | |
da2bc464 | 234 | EXC_REAL_MASKABLE(decrementer, 0x900, 0x980) |
a485c709 | 235 | |
da2bc464 | 236 | EXC_REAL_HV(hdecrementer, 0x980, 0xa00) |
a5d4f3ad | 237 | |
da2bc464 | 238 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00) |
b01c8b54 | 239 | |
da2bc464 | 240 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
0ebc4cda | 241 | |
da2bc464 ME |
242 | EXC_REAL(trap_0b, 0xb00, 0xc00) |
243 | ||
244 | TRAMP_KVM(PACA_EXGEN, 0xb00) | |
245 | ||
246 | EXC_REAL_BEGIN(system_call, 0xc00, 0xd00) | |
8b91a255 SW |
247 | /* |
248 | * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems | |
249 | * that support it) before changing to HMT_MEDIUM. That allows the KVM | |
250 | * code to save that value into the guest state (it is the guest's PPR | |
251 | * value). Otherwise just change to HMT_MEDIUM as userspace has | |
252 | * already saved the PPR. | |
253 | */ | |
b01c8b54 PM |
254 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
255 | SET_SCRATCH0(r13) | |
256 | GET_PACA(r13) | |
257 | std r9,PACA_EXGEN+EX_R9(r13) | |
8b91a255 SW |
258 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); |
259 | HMT_MEDIUM; | |
b01c8b54 | 260 | std r10,PACA_EXGEN+EX_R10(r13) |
8b91a255 | 261 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); |
b01c8b54 | 262 | mfcr r9 |
da2bc464 | 263 | KVMTEST_PR(0xc00) |
b01c8b54 | 264 | GET_SCRATCH0(r13) |
8b91a255 SW |
265 | #else |
266 | HMT_MEDIUM; | |
b01c8b54 | 267 | #endif |
742415d6 MN |
268 | SYSCALL_PSERIES_1 |
269 | SYSCALL_PSERIES_2_RFID | |
270 | SYSCALL_PSERIES_3 | |
da2bc464 ME |
271 | EXC_REAL_END(system_call, 0xc00, 0xd00) |
272 | ||
273 | TRAMP_KVM(PACA_EXGEN, 0xc00) | |
274 | ||
275 | EXC_REAL(single_step, 0xd00, 0xe00) | |
276 | ||
277 | TRAMP_KVM(PACA_EXGEN, 0xd00) | |
b01c8b54 | 278 | |
b3e6b5df BH |
279 | |
280 | /* At 0xe??? we have a bunch of hypervisor exceptions, we branch | |
281 | * out of line to handle them | |
282 | */ | |
da2bc464 | 283 | __EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20) |
1707dd16 | 284 | |
da2bc464 | 285 | __EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40) |
1707dd16 | 286 | |
da2bc464 | 287 | __EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60) |
1707dd16 | 288 | |
da2bc464 | 289 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early) |
1707dd16 | 290 | |
da2bc464 | 291 | __EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0) |
0ebc4cda | 292 | |
da2bc464 | 293 | __EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0) |
9baaef0a | 294 | |
da2bc464 | 295 | EXC_REAL_NONE(0xec0, 0xf00) |
0ebc4cda | 296 | |
da2bc464 | 297 | __EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20) |
0ebc4cda | 298 | |
da2bc464 | 299 | __EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40) |
0ebc4cda | 300 | |
da2bc464 ME |
301 | __EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60) |
302 | ||
303 | __EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80) | |
304 | ||
305 | __EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0) | |
306 | ||
307 | EXC_REAL_NONE(0xfa0, 0x1200) | |
d0c0c9a1 | 308 | |
b14b6260 | 309 | |
0ebc4cda | 310 | #ifdef CONFIG_CBE_RAS |
da2bc464 ME |
311 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300) |
312 | ||
313 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) | |
314 | ||
315 | #else /* CONFIG_CBE_RAS */ | |
316 | EXC_REAL_NONE(0x1200, 0x1300) | |
317 | #endif | |
b01c8b54 | 318 | |
da2bc464 | 319 | EXC_REAL(instruction_breakpoint, 0x1300, 0x1400) |
b01c8b54 | 320 | |
da2bc464 ME |
321 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
322 | ||
323 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600) | |
b92a66a6 | 324 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 325 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 326 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
327 | |
328 | #ifdef CONFIG_PPC_DENORMALISATION | |
329 | mfspr r10,SPRN_HSRR1 | |
330 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
331 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ | |
332 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
333 | bne+ denorm_assist | |
334 | #endif | |
335 | ||
da2bc464 | 336 | KVMTEST_PR(0x1500) |
b92a66a6 | 337 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) |
da2bc464 ME |
338 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600) |
339 | ||
340 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) | |
b92a66a6 | 341 | |
0ebc4cda | 342 | #ifdef CONFIG_CBE_RAS |
da2bc464 | 343 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700) |
b01c8b54 | 344 | |
da2bc464 ME |
345 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
346 | ||
347 | #else /* CONFIG_CBE_RAS */ | |
348 | EXC_REAL_NONE(0x1600, 0x1700) | |
349 | #endif | |
350 | ||
351 | EXC_REAL(altivec_assist, 0x1700, 0x1800) | |
352 | ||
353 | TRAMP_KVM(PACA_EXGEN, 0x1700) | |
b01c8b54 | 354 | |
0ebc4cda | 355 | #ifdef CONFIG_CBE_RAS |
da2bc464 ME |
356 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900) |
357 | ||
358 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) | |
359 | ||
360 | #else /* CONFIG_CBE_RAS */ | |
361 | EXC_REAL_NONE(0x1800, 0x1900) | |
faab4dd2 | 362 | . = 0x1800 |
da2bc464 | 363 | #endif |
0ebc4cda | 364 | |
0ebc4cda | 365 | |
b3e6b5df BH |
366 | /*** Out of line interrupts support ***/ |
367 | ||
b01c8b54 | 368 | /* moved from 0x200 */ |
da2bc464 | 369 | TRAMP_REAL_BEGIN(machine_check_powernv_early) |
1e9b4507 MS |
370 | BEGIN_FTR_SECTION |
371 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) | |
372 | /* | |
373 | * Register contents: | |
374 | * R13 = PACA | |
375 | * R9 = CR | |
376 | * Original R9 to R13 is saved on PACA_EXMC | |
377 | * | |
e75ad93a MS |
378 | * Switch to mc_emergency stack and handle re-entrancy (we limit |
379 | * the nested MCE upto level 4 to avoid stack overflow). | |
380 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
1e9b4507 MS |
381 | * |
382 | * We use paca->in_mce to check whether this is the first entry or | |
383 | * nested machine check. We increment paca->in_mce to track nested | |
384 | * machine checks. | |
385 | * | |
386 | * If this is the first entry then set stack pointer to | |
387 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
388 | * stack frame on mc_emergency stack. | |
389 | * | |
390 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
391 | * checkstop if we get another machine check exception before we do | |
392 | * rfid with MSR_ME=1. | |
393 | */ | |
394 | mr r11,r1 /* Save r1 */ | |
395 | lhz r10,PACA_IN_MCE(r13) | |
396 | cmpwi r10,0 /* Are we in nested machine check */ | |
397 | bne 0f /* Yes, we are. */ | |
398 | /* First machine check entry */ | |
399 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
400 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
401 | addi r10,r10,1 /* increment paca->in_mce */ | |
402 | sth r10,PACA_IN_MCE(r13) | |
e75ad93a MS |
403 | /* Limit nested MCE to level 4 to avoid stack overflow */ |
404 | cmpwi r10,4 | |
405 | bgt 2f /* Check if we hit limit of 4 */ | |
1e9b4507 MS |
406 | std r11,GPR1(r1) /* Save r1 on the stack. */ |
407 | std r11,0(r1) /* make stack chain pointer */ | |
408 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
409 | std r11,_NIP(r1) | |
410 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
411 | std r11,_MSR(r1) | |
412 | mfspr r11,SPRN_DAR /* Save DAR */ | |
413 | std r11,_DAR(r1) | |
414 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
415 | std r11,_DSISR(r1) | |
416 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
417 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
418 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
419 | mfmsr r11 /* get MSR value */ | |
420 | ori r11,r11,MSR_ME /* turn on ME bit */ | |
421 | ori r11,r11,MSR_RI /* turn on RI bit */ | |
1e9b4507 | 422 | LOAD_HANDLER(r12, machine_check_handle_early) |
e75ad93a | 423 | 1: mtspr SPRN_SRR0,r12 |
1e9b4507 MS |
424 | mtspr SPRN_SRR1,r11 |
425 | rfid | |
426 | b . /* prevent speculative execution */ | |
e75ad93a MS |
427 | 2: |
428 | /* Stack overflow. Stay on emergency stack and panic. | |
429 | * Keep the ME bit off while panic-ing, so that if we hit | |
430 | * another machine check we checkstop. | |
431 | */ | |
432 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
433 | ld r11,PACAKMSR(r13) | |
e75ad93a MS |
434 | LOAD_HANDLER(r12, unrecover_mce) |
435 | li r10,MSR_ME | |
436 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
437 | b 1b | |
438 | b . /* prevent speculative execution */ | |
1e9b4507 MS |
439 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
440 | ||
da2bc464 | 441 | TRAMP_REAL_BEGIN(machine_check_pSeries) |
b01c8b54 PM |
442 | .globl machine_check_fwnmi |
443 | machine_check_fwnmi: | |
b01c8b54 | 444 | SET_SCRATCH0(r13) /* save r13 */ |
1707dd16 PM |
445 | EXCEPTION_PROLOG_0(PACA_EXMC) |
446 | machine_check_pSeries_0: | |
da2bc464 | 447 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) |
a74599a5 NP |
448 | /* |
449 | * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the | |
450 | * difference that MSR_RI is not enabled, because PACA_EXMC is being | |
451 | * used, so nested machine check corrupts it. machine_check_common | |
452 | * enables MSR_RI. | |
453 | */ | |
a74599a5 NP |
454 | ld r10,PACAKMSR(r13) |
455 | xori r10,r10,MSR_RI | |
456 | mfspr r11,SPRN_SRR0 | |
457 | LOAD_HANDLER(r12, machine_check_common) | |
458 | mtspr SPRN_SRR0,r12 | |
459 | mfspr r12,SPRN_SRR1 | |
460 | mtspr SPRN_SRR1,r10 | |
461 | rfid | |
462 | b . /* prevent speculative execution */ | |
463 | ||
da2bc464 ME |
464 | |
465 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
466 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) | |
467 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) | |
468 | TRAMP_KVM(PACA_EXGEN, 0x400) | |
469 | TRAMP_KVM(PACA_EXSLB, 0x480) | |
470 | TRAMP_KVM(PACA_EXGEN, 0x900) | |
471 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) | |
b01c8b54 | 472 | |
b92a66a6 | 473 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 474 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
475 | BEGIN_FTR_SECTION |
476 | /* | |
477 | * To denormalise we need to move a copy of the register to itself. | |
478 | * For POWER6 do that here for all FP regs. | |
479 | */ | |
480 | mfmsr r10 | |
481 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
482 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
483 | mtmsrd r10 | |
484 | sync | |
d7c67fb1 MN |
485 | |
486 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
487 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
488 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
489 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
490 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
491 | FMR32(0) | |
492 | ||
b92a66a6 MN |
493 | FTR_SECTION_ELSE |
494 | /* | |
495 | * To denormalise we need to move a copy of the register to itself. | |
496 | * For POWER7 do that here for the first 32 VSX registers only. | |
497 | */ | |
498 | mfmsr r10 | |
499 | oris r10,r10,MSR_VSX@h | |
500 | mtmsrd r10 | |
501 | sync | |
d7c67fb1 MN |
502 | |
503 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
504 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
505 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
506 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
507 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
508 | XVCPSGNDP32(0) | |
509 | ||
b92a66a6 | 510 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
511 | |
512 | BEGIN_FTR_SECTION | |
513 | b denorm_done | |
514 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
515 | /* | |
516 | * To denormalise we need to move a copy of the register to itself. | |
517 | * For POWER8 we need to do that for all 64 VSX registers | |
518 | */ | |
519 | XVCPSGNDP32(32) | |
520 | denorm_done: | |
b92a66a6 MN |
521 | mtspr SPRN_HSRR0,r11 |
522 | mtcrf 0x80,r9 | |
523 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 524 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
525 | BEGIN_FTR_SECTION |
526 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
527 | mtspr SPRN_CFAR,r10 | |
528 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
529 | ld r10,PACA_EXGEN+EX_R10(r13) |
530 | ld r11,PACA_EXGEN+EX_R11(r13) | |
531 | ld r12,PACA_EXGEN+EX_R12(r13) | |
532 | ld r13,PACA_EXGEN+EX_R13(r13) | |
533 | HRFID | |
534 | b . | |
535 | #endif | |
536 | ||
b3e6b5df | 537 | /* moved from 0xe00 */ |
da2bc464 ME |
538 | __TRAMP_REAL_REAL_OOL_HV(h_data_storage, 0xe00) |
539 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) | |
540 | ||
541 | __TRAMP_REAL_REAL_OOL_HV(h_instr_storage, 0xe20) | |
542 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) | |
543 | ||
544 | __TRAMP_REAL_REAL_OOL_HV(emulation_assist, 0xe40) | |
545 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) | |
0869b6fd | 546 | |
da2bc464 ME |
547 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
548 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) | |
0ebc4cda | 549 | |
da2bc464 ME |
550 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80) |
551 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) | |
552 | ||
553 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0) | |
554 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) | |
9baaef0a | 555 | |
0ebc4cda | 556 | /* moved from 0xf00 */ |
da2bc464 ME |
557 | __TRAMP_REAL_REAL_OOL(performance_monitor, 0xf00) |
558 | TRAMP_KVM(PACA_EXGEN, 0xf00) | |
559 | ||
560 | __TRAMP_REAL_REAL_OOL(altivec_unavailable, 0xf20) | |
561 | TRAMP_KVM(PACA_EXGEN, 0xf20) | |
562 | ||
563 | __TRAMP_REAL_REAL_OOL(vsx_unavailable, 0xf40) | |
564 | TRAMP_KVM(PACA_EXGEN, 0xf40) | |
565 | ||
566 | __TRAMP_REAL_REAL_OOL(facility_unavailable, 0xf60) | |
567 | TRAMP_KVM(PACA_EXGEN, 0xf60) | |
568 | ||
569 | __TRAMP_REAL_REAL_OOL_HV(h_facility_unavailable, 0xf80) | |
570 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) | |
0ebc4cda BH |
571 | |
572 | /* | |
fe9e1d54 IM |
573 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
574 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
575 | * - If it was a doorbell we return immediately since doorbells are edge | |
576 | * triggered and won't automatically refire. | |
0869b6fd MS |
577 | * - If it was a HMI we return immediately since we handled it in realmode |
578 | * and it won't refire. | |
fe9e1d54 IM |
579 | * - else we hard disable and return. |
580 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 581 | */ |
7230c564 BH |
582 | #define MASKED_INTERRUPT(_H) \ |
583 | masked_##_H##interrupt: \ | |
584 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
585 | lbz r11,PACAIRQHAPPENED(r13); \ | |
586 | or r11,r11,r10; \ | |
587 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
588 | cmpwi r10,PACA_IRQ_DEC; \ |
589 | bne 1f; \ | |
7230c564 BH |
590 | lis r10,0x7fff; \ |
591 | ori r10,r10,0xffff; \ | |
592 | mtspr SPRN_DEC,r10; \ | |
593 | b 2f; \ | |
fe9e1d54 | 594 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
0869b6fd MS |
595 | beq 2f; \ |
596 | cmpwi r10,PACA_IRQ_HMI; \ | |
fe9e1d54 IM |
597 | beq 2f; \ |
598 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
599 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
600 | rotldi r10,r10,16; \ | |
601 | mtspr SPRN_##_H##SRR1,r10; \ | |
602 | 2: mtcrf 0x80,r9; \ | |
603 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
604 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
605 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
606 | GET_SCRATCH0(r13); \ | |
607 | ##_H##rfid; \ | |
0ebc4cda | 608 | b . |
7230c564 BH |
609 | |
610 | MASKED_INTERRUPT() | |
611 | MASKED_INTERRUPT(H) | |
0ebc4cda | 612 | |
7230c564 BH |
613 | /* |
614 | * Called from arch_local_irq_enable when an interrupt needs | |
fe9e1d54 IM |
615 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate |
616 | * which kind of interrupt. MSR:EE is already off. We generate a | |
7230c564 BH |
617 | * stackframe like if a real interrupt had happened. |
618 | * | |
619 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
620 | * in the generated frame has EE set to 1 or the exception | |
621 | * handler will not properly re-enable them. | |
622 | */ | |
623 | _GLOBAL(__replay_interrupt) | |
624 | /* We are going to jump to the exception common code which | |
625 | * will retrieve various register values from the PACA which | |
626 | * we don't give a damn about, so we don't bother storing them. | |
627 | */ | |
628 | mfmsr r12 | |
629 | mflr r11 | |
630 | mfcr r9 | |
631 | ori r12,r12,MSR_EE | |
fe9e1d54 IM |
632 | cmpwi r3,0x900 |
633 | beq decrementer_common | |
634 | cmpwi r3,0x500 | |
635 | beq hardware_interrupt_common | |
636 | BEGIN_FTR_SECTION | |
637 | cmpwi r3,0xe80 | |
638 | beq h_doorbell_common | |
9baaef0a BH |
639 | cmpwi r3,0xea0 |
640 | beq h_virt_irq_common | |
fd7bacbc MS |
641 | cmpwi r3,0xe60 |
642 | beq hmi_exception_common | |
fe9e1d54 IM |
643 | FTR_SECTION_ELSE |
644 | cmpwi r3,0xa00 | |
645 | beq doorbell_super_common | |
646 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
647 | blr | |
a5d4f3ad | 648 | |
0ebc4cda BH |
649 | #ifdef CONFIG_PPC_PSERIES |
650 | /* | |
651 | * Vectors for the FWNMI option. Share common code. | |
652 | */ | |
da2bc464 | 653 | TRAMP_REAL_BEGIN(system_reset_fwnmi) |
673b189a | 654 | SET_SCRATCH0(r13) /* save r13 */ |
b01c8b54 PM |
655 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
656 | NOTEST, 0x100) | |
0ebc4cda BH |
657 | |
658 | #endif /* CONFIG_PPC_PSERIES */ | |
659 | ||
4f6c11db | 660 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 661 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
662 | /* |
663 | * Here all GPRs are unchanged from when the interrupt happened | |
664 | * except for r13, which is saved in SPRG_SCRATCH0. | |
665 | */ | |
666 | mfspr r13, SPRN_SRR0 | |
667 | addi r13, r13, 4 | |
668 | mtspr SPRN_SRR0, r13 | |
669 | GET_SCRATCH0(r13) | |
670 | rfid | |
671 | b . | |
672 | ||
da2bc464 | 673 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
674 | /* |
675 | * Here all GPRs are unchanged from when the interrupt happened | |
676 | * except for r13, which is saved in SPRG_SCRATCH0. | |
677 | */ | |
678 | mfspr r13, SPRN_HSRR0 | |
679 | addi r13, r13, 4 | |
680 | mtspr SPRN_HSRR0, r13 | |
681 | GET_SCRATCH0(r13) | |
682 | hrfid | |
683 | b . | |
684 | #endif | |
685 | ||
0ebc4cda | 686 | /* |
057b6d7e HB |
687 | * Ensure that any handlers that get invoked from the exception prologs |
688 | * above are below the first 64KB (0x10000) of the kernel image because | |
689 | * the prologs assemble the addresses of these handlers using the | |
690 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
691 | */ |
692 | ||
693 | /*** Common interrupt handlers ***/ | |
694 | ||
da2bc464 | 695 | EXC_COMMON(system_reset_common, 0x100, system_reset_exception) |
da2bc464 | 696 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
da2bc464 | 697 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) |
da2bc464 | 698 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) |
0ebc4cda | 699 | |
1dbdafec | 700 | #ifdef CONFIG_PPC_DOORBELL |
da2bc464 | 701 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) |
1dbdafec | 702 | #else |
da2bc464 | 703 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) |
1dbdafec | 704 | #endif |
da2bc464 | 705 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
da2bc464 | 706 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
da2bc464 | 707 | EXC_COMMON(trap_0e_common, 0xe00, unknown_exception) |
da2bc464 | 708 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) |
da2bc464 | 709 | EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) |
655bb3f4 | 710 | #ifdef CONFIG_PPC_DOORBELL |
da2bc464 | 711 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) |
655bb3f4 | 712 | #else |
da2bc464 | 713 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) |
655bb3f4 | 714 | #endif |
da2bc464 | 715 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) |
da2bc464 | 716 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) |
da2bc464 | 717 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
da2bc464 | 718 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
0ebc4cda | 719 | #ifdef CONFIG_ALTIVEC |
da2bc464 | 720 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) |
0ebc4cda | 721 | #else |
da2bc464 | 722 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) |
0ebc4cda | 723 | #endif |
0ebc4cda | 724 | |
c1fb6816 MN |
725 | /* |
726 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
727 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
728 | * it. Addresses are the same as the original interrupt addresses, but | |
729 | * offset by 0xc000000000004000. | |
730 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
731 | * KVM: None of these traps are from the guest ; anything that escalated | |
732 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
733 | */ | |
734 | ||
735 | /* | |
736 | * This uses the standard macro, since the original 0x300 vector | |
737 | * only has extra guff for STAB-based processors -- which never | |
738 | * come here. | |
739 | */ | |
da2bc464 ME |
740 | EXC_VIRT_NONE(0x4100, 0x4200) |
741 | EXC_VIRT_NONE(0x4200, 0x4300) | |
742 | ||
743 | EXC_VIRT(data_access, 0x4300, 0x4380, 0x300) | |
744 | ||
745 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400) | |
c1fb6816 | 746 | SET_SCRATCH0(r13) |
1707dd16 | 747 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
748 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) |
749 | std r3,PACA_EXSLB+EX_R3(r13) | |
750 | mfspr r3,SPRN_DAR | |
751 | mfspr r12,SPRN_SRR1 | |
f0f558b1 | 752 | crset 4*cr6+eq |
c1fb6816 | 753 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 754 | b slb_miss_realmode |
c1fb6816 MN |
755 | #else |
756 | /* | |
ad0289e4 | 757 | * We can't just use a direct branch to slb_miss_realmode |
c1fb6816 MN |
758 | * because the distance from here to there depends on where |
759 | * the kernel ends up being put. | |
760 | */ | |
761 | mfctr r11 | |
ad0289e4 | 762 | LOAD_HANDLER(r10, slb_miss_realmode) |
c1fb6816 MN |
763 | mtctr r10 |
764 | bctr | |
765 | #endif | |
da2bc464 | 766 | EXC_VIRT_END(data_access_slb, 0x4380, 0x4400) |
c1fb6816 | 767 | |
da2bc464 ME |
768 | EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400) |
769 | ||
770 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500) | |
c1fb6816 | 771 | SET_SCRATCH0(r13) |
1707dd16 | 772 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
773 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) |
774 | std r3,PACA_EXSLB+EX_R3(r13) | |
775 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
776 | mfspr r12,SPRN_SRR1 | |
f0f558b1 | 777 | crclr 4*cr6+eq |
c1fb6816 | 778 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 779 | b slb_miss_realmode |
c1fb6816 MN |
780 | #else |
781 | mfctr r11 | |
ad0289e4 | 782 | LOAD_HANDLER(r10, slb_miss_realmode) |
c1fb6816 MN |
783 | mtctr r10 |
784 | bctr | |
785 | #endif | |
da2bc464 | 786 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500) |
c1fb6816 | 787 | |
da2bc464 | 788 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600) |
c1fb6816 | 789 | .globl hardware_interrupt_relon_hv; |
c1fb6816 MN |
790 | hardware_interrupt_relon_hv: |
791 | BEGIN_FTR_SECTION | |
da2bc464 | 792 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) |
c1fb6816 | 793 | FTR_SECTION_ELSE |
da2bc464 | 794 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) |
3e96ca7f | 795 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
da2bc464 ME |
796 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600) |
797 | ||
798 | EXC_VIRT(alignment, 0x4600, 0x4700, 0x600) | |
799 | EXC_VIRT(program_check, 0x4700, 0x4800, 0x700) | |
800 | EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800) | |
801 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) | |
802 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980) | |
803 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00) | |
804 | EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) | |
805 | ||
806 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00) | |
c1fb6816 MN |
807 | HMT_MEDIUM |
808 | SYSCALL_PSERIES_1 | |
809 | SYSCALL_PSERIES_2_DIRECT | |
810 | SYSCALL_PSERIES_3 | |
da2bc464 | 811 | EXC_VIRT_END(system_call, 0x4c00, 0x4d00) |
c1fb6816 | 812 | |
da2bc464 | 813 | EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00) |
c1fb6816 | 814 | |
da2bc464 ME |
815 | EXC_VIRT_BEGIN(unused, 0x4e00, 0x4e20) |
816 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ | |
817 | EXC_VIRT_END(unused, 0x4e00, 0x4e20) | |
c1fb6816 | 818 | |
da2bc464 ME |
819 | EXC_VIRT_BEGIN(unused, 0x4e20, 0x4e40) |
820 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ | |
821 | EXC_VIRT_END(unused, 0x4e20, 0x4e40) | |
c1fb6816 | 822 | |
da2bc464 | 823 | __EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60) |
c1fb6816 | 824 | |
da2bc464 ME |
825 | EXC_VIRT_BEGIN(unused, 0x4e60, 0x4e80) |
826 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ | |
827 | EXC_VIRT_END(unused, 0x4e60, 0x4e80) | |
c1fb6816 | 828 | |
da2bc464 | 829 | __EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0) |
c1fb6816 | 830 | |
da2bc464 | 831 | __EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0) |
9baaef0a | 832 | |
da2bc464 | 833 | EXC_VIRT_NONE(0x4ec0, 0x4f00) |
c1fb6816 | 834 | |
da2bc464 | 835 | __EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20) |
c1fb6816 | 836 | |
da2bc464 | 837 | __EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40) |
c1fb6816 | 838 | |
da2bc464 | 839 | __EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60) |
d0c0c9a1 | 840 | |
da2bc464 ME |
841 | __EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80) |
842 | ||
843 | __EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0) | |
844 | ||
845 | EXC_VIRT_NONE(0x4fa0, 0x5200) | |
846 | ||
847 | EXC_VIRT_NONE(0x5200, 0x5300) | |
848 | ||
849 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300) | |
b14b6260 | 850 | |
c1fb6816 | 851 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 ME |
852 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600) |
853 | b exc_real_0x1500_denorm_exception_hv | |
854 | EXC_VIRT_END(denorm_exception, 0x5500, 0x5600) | |
855 | #else | |
856 | EXC_VIRT_NONE(0x5500, 0x5600) | |
c1fb6816 | 857 | #endif |
c1fb6816 | 858 | |
da2bc464 ME |
859 | EXC_VIRT_NONE(0x5600, 0x5700) |
860 | ||
861 | EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700) | |
862 | ||
863 | EXC_VIRT_NONE(0x5800, 0x5900) | |
864 | ||
865 | TRAMP_REAL_BEGIN(ppc64_runlatch_on_trampoline) | |
b1576fec | 866 | b __ppc64_runlatch_on |
fe1952fc | 867 | |
0ebc4cda BH |
868 | /* |
869 | * Here r13 points to the paca, r9 contains the saved CR, | |
870 | * SRR0 and SRR1 are saved in r11 and r12, | |
871 | * r9 - r13 are saved in paca->exgen. | |
872 | */ | |
da2bc464 | 873 | EXC_COMMON_BEGIN(data_access_common) |
0ebc4cda BH |
874 | mfspr r10,SPRN_DAR |
875 | std r10,PACA_EXGEN+EX_DAR(r13) | |
876 | mfspr r10,SPRN_DSISR | |
877 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
878 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
9daf112b | 879 | RECONCILE_IRQ_STATE(r10, r11) |
a546498f | 880 | ld r12,_MSR(r1) |
0ebc4cda BH |
881 | ld r3,PACA_EXGEN+EX_DAR(r13) |
882 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
883 | li r5,0x300 | |
caca285e AK |
884 | std r3,_DAR(r1) |
885 | std r4,_DSISR(r1) | |
886 | BEGIN_MMU_FTR_SECTION | |
b1576fec | 887 | b do_hash_page /* Try to handle as hpte fault */ |
caca285e AK |
888 | MMU_FTR_SECTION_ELSE |
889 | b handle_page_fault | |
5a25b6f5 | 890 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) |
0ebc4cda | 891 | |
da2bc464 | 892 | EXC_COMMON_BEGIN(h_data_storage_common) |
278a6cdc MN |
893 | mfspr r10,SPRN_HDAR |
894 | std r10,PACA_EXGEN+EX_DAR(r13) | |
895 | mfspr r10,SPRN_HDSISR | |
896 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
897 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
b1576fec | 898 | bl save_nvgprs |
9daf112b | 899 | RECONCILE_IRQ_STATE(r10, r11) |
278a6cdc | 900 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
901 | bl unknown_exception |
902 | b ret_from_except | |
b3e6b5df | 903 | |
da2bc464 | 904 | EXC_COMMON_BEGIN(instruction_access_common) |
0ebc4cda | 905 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) |
9daf112b | 906 | RECONCILE_IRQ_STATE(r10, r11) |
a546498f | 907 | ld r12,_MSR(r1) |
0ebc4cda BH |
908 | ld r3,_NIP(r1) |
909 | andis. r4,r12,0x5820 | |
910 | li r5,0x400 | |
caca285e AK |
911 | std r3,_DAR(r1) |
912 | std r4,_DSISR(r1) | |
913 | BEGIN_MMU_FTR_SECTION | |
b1576fec | 914 | b do_hash_page /* Try to handle as hpte fault */ |
caca285e AK |
915 | MMU_FTR_SECTION_ELSE |
916 | b handle_page_fault | |
5a25b6f5 | 917 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) |
0ebc4cda | 918 | |
da2bc464 | 919 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) |
b3e6b5df | 920 | |
4e243b79 MS |
921 | /* |
922 | * Machine check is different because we use a different | |
923 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
924 | */ | |
da2bc464 | 925 | EXC_COMMON_BEGIN(machine_check_common) |
4e243b79 | 926 | mfspr r10,SPRN_DAR |
3f3b5dc1 | 927 | std r10,PACA_EXMC+EX_DAR(r13) |
4e243b79 | 928 | mfspr r10,SPRN_DSISR |
3f3b5dc1 | 929 | stw r10,PACA_EXMC+EX_DSISR(r13) |
4e243b79 MS |
930 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) |
931 | FINISH_NAP | |
9daf112b | 932 | RECONCILE_IRQ_STATE(r10, r11) |
3f3b5dc1 NP |
933 | ld r3,PACA_EXMC+EX_DAR(r13) |
934 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
a74599a5 NP |
935 | /* Enable MSR_RI when finished with PACA_EXMC */ |
936 | li r10,MSR_RI | |
937 | mtmsrd r10,1 | |
4e243b79 MS |
938 | std r3,_DAR(r1) |
939 | std r4,_DSISR(r1) | |
b1576fec | 940 | bl save_nvgprs |
4e243b79 | 941 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
942 | bl machine_check_exception |
943 | b ret_from_except | |
4e243b79 | 944 | |
da2bc464 | 945 | EXC_COMMON_BEGIN(alignment_common) |
0ebc4cda BH |
946 | mfspr r10,SPRN_DAR |
947 | std r10,PACA_EXGEN+EX_DAR(r13) | |
948 | mfspr r10,SPRN_DSISR | |
949 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
950 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
951 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
952 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
953 | std r3,_DAR(r1) | |
954 | std r4,_DSISR(r1) | |
b1576fec | 955 | bl save_nvgprs |
9daf112b | 956 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 957 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
958 | bl alignment_exception |
959 | b ret_from_except | |
0ebc4cda | 960 | |
da2bc464 | 961 | EXC_COMMON_BEGIN(program_check_common) |
0ebc4cda | 962 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) |
b1576fec | 963 | bl save_nvgprs |
9daf112b | 964 | RECONCILE_IRQ_STATE(r10, r11) |
922b9f86 | 965 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
966 | bl program_check_exception |
967 | b ret_from_except | |
0ebc4cda | 968 | |
da2bc464 | 969 | EXC_COMMON_BEGIN(fp_unavailable_common) |
0ebc4cda BH |
970 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) |
971 | bne 1f /* if from user, just load it up */ | |
b1576fec | 972 | bl save_nvgprs |
9daf112b | 973 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 974 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 975 | bl kernel_fp_unavailable_exception |
0ebc4cda | 976 | BUG_OPCODE |
bc2a9408 MN |
977 | 1: |
978 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
979 | BEGIN_FTR_SECTION | |
980 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
981 | * transaction), go do TM stuff | |
982 | */ | |
983 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
984 | bne- 2f | |
985 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
986 | #endif | |
b1576fec | 987 | bl load_up_fpu |
0ebc4cda | 988 | b fast_exception_return |
bc2a9408 MN |
989 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
990 | 2: /* User process was in a transaction */ | |
b1576fec | 991 | bl save_nvgprs |
9daf112b | 992 | RECONCILE_IRQ_STATE(r10, r11) |
bc2a9408 | 993 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
994 | bl fp_unavailable_tm |
995 | b ret_from_except | |
bc2a9408 | 996 | #endif |
da2bc464 | 997 | |
da2bc464 | 998 | EXC_COMMON_BEGIN(altivec_unavailable_common) |
0ebc4cda BH |
999 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) |
1000 | #ifdef CONFIG_ALTIVEC | |
1001 | BEGIN_FTR_SECTION | |
1002 | beq 1f | |
bc2a9408 MN |
1003 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1004 | BEGIN_FTR_SECTION_NESTED(69) | |
1005 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1006 | * transaction), go do TM stuff | |
1007 | */ | |
1008 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1009 | bne- 2f | |
1010 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1011 | #endif | |
b1576fec | 1012 | bl load_up_altivec |
0ebc4cda | 1013 | b fast_exception_return |
bc2a9408 MN |
1014 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1015 | 2: /* User process was in a transaction */ | |
b1576fec | 1016 | bl save_nvgprs |
9daf112b | 1017 | RECONCILE_IRQ_STATE(r10, r11) |
bc2a9408 | 1018 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1019 | bl altivec_unavailable_tm |
1020 | b ret_from_except | |
bc2a9408 | 1021 | #endif |
0ebc4cda BH |
1022 | 1: |
1023 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1024 | #endif | |
b1576fec | 1025 | bl save_nvgprs |
9daf112b | 1026 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 1027 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1028 | bl altivec_unavailable_exception |
1029 | b ret_from_except | |
0ebc4cda | 1030 | |
da2bc464 | 1031 | EXC_COMMON_BEGIN(vsx_unavailable_common) |
0ebc4cda BH |
1032 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) |
1033 | #ifdef CONFIG_VSX | |
1034 | BEGIN_FTR_SECTION | |
7230c564 | 1035 | beq 1f |
bc2a9408 MN |
1036 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1037 | BEGIN_FTR_SECTION_NESTED(69) | |
1038 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1039 | * transaction), go do TM stuff | |
1040 | */ | |
1041 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1042 | bne- 2f | |
1043 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1044 | #endif | |
b1576fec | 1045 | b load_up_vsx |
bc2a9408 MN |
1046 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1047 | 2: /* User process was in a transaction */ | |
b1576fec | 1048 | bl save_nvgprs |
9daf112b | 1049 | RECONCILE_IRQ_STATE(r10, r11) |
bc2a9408 | 1050 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1051 | bl vsx_unavailable_tm |
1052 | b ret_from_except | |
bc2a9408 | 1053 | #endif |
0ebc4cda BH |
1054 | 1: |
1055 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1056 | #endif | |
b1576fec | 1057 | bl save_nvgprs |
9daf112b | 1058 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 1059 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1060 | bl vsx_unavailable_exception |
1061 | b ret_from_except | |
0ebc4cda | 1062 | |
61383407 | 1063 | /* Equivalents to the above handlers for relocation-on interrupt vectors */ |
da2bc464 ME |
1064 | __TRAMP_REAL_VIRT_OOL_HV(emulation_assist, 0xe40) |
1065 | __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_doorbell, 0xe80) | |
1066 | __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0xea0) | |
1067 | __TRAMP_REAL_VIRT_OOL(performance_monitor, 0xf00) | |
1068 | __TRAMP_REAL_VIRT_OOL(altivec_unavailable, 0xf20) | |
1069 | __TRAMP_REAL_VIRT_OOL(vsx_unavailable, 0xf40) | |
1070 | __TRAMP_REAL_VIRT_OOL(facility_unavailable, 0xf60) | |
1071 | __TRAMP_REAL_VIRT_OOL_HV(h_facility_unavailable, 0xf80) | |
61383407 | 1072 | |
8ed8ab40 HB |
1073 | /* |
1074 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1075 | * handlers, so that they are copied to real address 0x100 when running | |
1076 | * a relocatable kernel. This ensures they can be reached from the short | |
1077 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1078 | * directly, without using LOAD_HANDLER(). | |
1079 | */ | |
1080 | .align 7 | |
1081 | .globl __end_interrupts | |
1082 | __end_interrupts: | |
1083 | ||
61383407 BH |
1084 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) |
1085 | /* | |
1086 | * Data area reserved for FWNMI option. | |
1087 | * This address (0x7000) is fixed by the RPA. | |
1088 | */ | |
1089 | .= 0x7000 | |
1090 | .globl fwnmi_data_area | |
1091 | fwnmi_data_area: | |
1092 | ||
1093 | /* pseries and powernv need to keep the whole page from | |
1094 | * 0x7000 to 0x8000 free for use by the firmware | |
1095 | */ | |
1096 | . = 0x8000 | |
1097 | #endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */ | |
1098 | ||
da2bc464 | 1099 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) |
da2bc464 | 1100 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) |
b88d4bce BH |
1101 | |
1102 | #ifdef CONFIG_CBE_RAS | |
da2bc464 | 1103 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1104 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
da2bc464 | 1105 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
b88d4bce BH |
1106 | #endif /* CONFIG_CBE_RAS */ |
1107 | ||
da2bc464 | 1108 | |
da2bc464 ME |
1109 | EXC_COMMON_BEGIN(hmi_exception_early) |
1110 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) | |
11d54904 GR |
1111 | mr r10,r1 /* Save r1 */ |
1112 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
1113 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
1114 | std r9,_CCR(r1) /* save CR in stackframe */ | |
1115 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ | |
1116 | std r11,_NIP(r1) /* save HSRR0 in stackframe */ | |
1117 | mfspr r12,SPRN_HSRR1 /* Save SRR1 */ | |
1118 | std r12,_MSR(r1) /* save SRR1 in stackframe */ | |
1119 | std r10,0(r1) /* make stack chain pointer */ | |
1120 | std r0,GPR0(r1) /* save r0 in stackframe */ | |
1121 | std r10,GPR1(r1) /* save r1 in stackframe */ | |
1122 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) | |
1123 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1124 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1125 | bl hmi_exception_realmode | |
1126 | /* Windup the stack. */ | |
11d54904 GR |
1127 | /* Move original HSRR0 and HSRR1 into the respective regs */ |
1128 | ld r9,_MSR(r1) | |
1129 | mtspr SPRN_HSRR1,r9 | |
1130 | ld r3,_NIP(r1) | |
1131 | mtspr SPRN_HSRR0,r3 | |
1132 | ld r9,_CTR(r1) | |
1133 | mtctr r9 | |
1134 | ld r9,_XER(r1) | |
1135 | mtxer r9 | |
1136 | ld r9,_LINK(r1) | |
1137 | mtlr r9 | |
1138 | REST_GPR(0, r1) | |
1139 | REST_8GPRS(2, r1) | |
1140 | REST_GPR(10, r1) | |
1141 | ld r11,_CCR(r1) | |
1142 | mtcr r11 | |
1143 | REST_GPR(11, r1) | |
1144 | REST_2GPRS(12, r1) | |
1145 | /* restore original r1. */ | |
1146 | ld r1,GPR1(r1) | |
1147 | ||
1148 | /* | |
1149 | * Go to virtual mode and pull the HMI event information from | |
1150 | * firmware. | |
1151 | */ | |
1152 | .globl hmi_exception_after_realmode | |
1153 | hmi_exception_after_realmode: | |
1154 | SET_SCRATCH0(r13) | |
1155 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
da2bc464 | 1156 | b tramp_real_hmi_exception |
11d54904 | 1157 | |
61383407 | 1158 | |
4e243b79 MS |
1159 | #define MACHINE_CHECK_HANDLER_WINDUP \ |
1160 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
1161 | li r0,MSR_RI; \ | |
1162 | mfmsr r9; /* get MSR value */ \ | |
1163 | andc r9,r9,r0; \ | |
1164 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
1165 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
1166 | ld r9,_MSR(r1); \ | |
1167 | mtspr SPRN_SRR1,r9; \ | |
1168 | ld r3,_NIP(r1); \ | |
1169 | mtspr SPRN_SRR0,r3; \ | |
1170 | ld r9,_CTR(r1); \ | |
1171 | mtctr r9; \ | |
1172 | ld r9,_XER(r1); \ | |
1173 | mtxer r9; \ | |
1174 | ld r9,_LINK(r1); \ | |
1175 | mtlr r9; \ | |
1176 | REST_GPR(0, r1); \ | |
1177 | REST_8GPRS(2, r1); \ | |
1178 | REST_GPR(10, r1); \ | |
1179 | ld r11,_CCR(r1); \ | |
1180 | mtcr r11; \ | |
1181 | /* Decrement paca->in_mce. */ \ | |
1182 | lhz r12,PACA_IN_MCE(r13); \ | |
1183 | subi r12,r12,1; \ | |
1184 | sth r12,PACA_IN_MCE(r13); \ | |
1185 | REST_GPR(11, r1); \ | |
1186 | REST_2GPRS(12, r1); \ | |
1187 | /* restore original r1. */ \ | |
1188 | ld r1,GPR1(r1) | |
1189 | ||
1190 | /* | |
1191 | * Handle machine check early in real mode. We come here with | |
1192 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
1193 | */ | |
da2bc464 | 1194 | EXC_COMMON_BEGIN(machine_check_handle_early) |
4e243b79 MS |
1195 | std r0,GPR0(r1) /* Save r0 */ |
1196 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
b1576fec | 1197 | bl save_nvgprs |
4e243b79 | 1198 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 1199 | bl machine_check_early |
2749a2f2 | 1200 | std r3,RESULT(r1) /* Save result */ |
4e243b79 MS |
1201 | ld r12,_MSR(r1) |
1202 | #ifdef CONFIG_PPC_P7_NAP | |
1203 | /* | |
1204 | * Check if thread was in power saving mode. We come here when any | |
1205 | * of the following is true: | |
1206 | * a. thread wasn't in power saving mode | |
bc14c491 MS |
1207 | * b. thread was in power saving mode with no state loss, |
1208 | * supervisor state loss or hypervisor state loss. | |
4e243b79 | 1209 | * |
bc14c491 | 1210 | * Go back to nap/sleep/winkle mode again if (b) is true. |
4e243b79 MS |
1211 | */ |
1212 | rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ | |
1213 | beq 4f /* No, it wasn;t */ | |
1214 | /* Thread was in power saving mode. Go back to nap again. */ | |
1215 | cmpwi r11,2 | |
bc14c491 MS |
1216 | blt 3f |
1217 | /* Supervisor/Hypervisor state loss */ | |
4e243b79 MS |
1218 | li r0,1 |
1219 | stb r0,PACA_NAPSTATELOST(r13) | |
b1576fec | 1220 | 3: bl machine_check_queue_event |
4e243b79 MS |
1221 | MACHINE_CHECK_HANDLER_WINDUP |
1222 | GET_PACA(r13) | |
1223 | ld r1,PACAR1(r13) | |
bc14c491 MS |
1224 | /* |
1225 | * Check what idle state this CPU was in and go back to same mode | |
1226 | * again. | |
1227 | */ | |
1228 | lbz r3,PACA_THREAD_IDLE_STATE(r13) | |
1229 | cmpwi r3,PNV_THREAD_NAP | |
1230 | bgt 10f | |
1231 | IDLE_STATE_ENTER_SEQ(PPC_NAP) | |
1232 | /* No return */ | |
1233 | 10: | |
1234 | cmpwi r3,PNV_THREAD_SLEEP | |
1235 | bgt 2f | |
1236 | IDLE_STATE_ENTER_SEQ(PPC_SLEEP) | |
1237 | /* No return */ | |
1238 | ||
1239 | 2: | |
1240 | /* | |
1241 | * Go back to winkle. Please note that this thread was woken up in | |
1242 | * machine check from winkle and have not restored the per-subcore | |
1243 | * state. Hence before going back to winkle, set last bit of HSPGR0 | |
1244 | * to 1. This will make sure that if this thread gets woken up | |
1245 | * again at reset vector 0x100 then it will get chance to restore | |
1246 | * the subcore state. | |
1247 | */ | |
1248 | ori r13,r13,1 | |
1249 | SET_PACA(r13) | |
1250 | IDLE_STATE_ENTER_SEQ(PPC_WINKLE) | |
1251 | /* No return */ | |
4e243b79 MS |
1252 | 4: |
1253 | #endif | |
1254 | /* | |
1255 | * Check if we are coming from hypervisor userspace. If yes then we | |
1256 | * continue in host kernel in V mode to deliver the MC event. | |
1257 | */ | |
1258 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
1259 | beq 5f | |
1260 | andi. r11,r12,MSR_PR /* See if coming from user. */ | |
1261 | bne 9f /* continue in V mode if we are. */ | |
1262 | ||
1263 | 5: | |
44d5f6f5 | 1264 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
4e243b79 MS |
1265 | /* |
1266 | * We are coming from kernel context. Check if we are coming from | |
1267 | * guest. if yes, then we can continue. We will fall through | |
1268 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
1269 | */ | |
1270 | lbz r11,HSTATE_IN_GUEST(r13) | |
1271 | cmpwi r11,0 /* Check if coming from guest */ | |
1272 | bne 9f /* continue if we are. */ | |
1273 | #endif | |
1274 | /* | |
1275 | * At this point we are not sure about what context we come from. | |
1276 | * Queue up the MCE event and return from the interrupt. | |
1277 | * But before that, check if this is an un-recoverable exception. | |
1278 | * If yes, then stay on emergency stack and panic. | |
1279 | */ | |
1280 | andi. r11,r12,MSR_RI | |
1281 | bne 2f | |
2749a2f2 | 1282 | 1: mfspr r11,SPRN_SRR0 |
2749a2f2 MS |
1283 | LOAD_HANDLER(r10,unrecover_mce) |
1284 | mtspr SPRN_SRR0,r10 | |
1285 | ld r10,PACAKMSR(r13) | |
1286 | /* | |
1287 | * We are going down. But there are chances that we might get hit by | |
1288 | * another MCE during panic path and we may run into unstable state | |
1289 | * with no way out. Hence, turn ME bit off while going down, so that | |
1290 | * when another MCE is hit during panic path, system will checkstop | |
1291 | * and hypervisor will get restarted cleanly by SP. | |
1292 | */ | |
1293 | li r3,MSR_ME | |
1294 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
1295 | mtspr SPRN_SRR1,r10 | |
1296 | rfid | |
1297 | b . | |
4e243b79 | 1298 | 2: |
2749a2f2 MS |
1299 | /* |
1300 | * Check if we have successfully handled/recovered from error, if not | |
1301 | * then stay on emergency stack and panic. | |
1302 | */ | |
1303 | ld r3,RESULT(r1) /* Load result */ | |
1304 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
1305 | ||
1306 | beq 1b /* if !handled then panic */ | |
4e243b79 MS |
1307 | /* |
1308 | * Return from MC interrupt. | |
1309 | * Queue up the MCE event so that we can log it later, while | |
1310 | * returning from kernel or opal call. | |
1311 | */ | |
b1576fec | 1312 | bl machine_check_queue_event |
4e243b79 MS |
1313 | MACHINE_CHECK_HANDLER_WINDUP |
1314 | rfid | |
1315 | 9: | |
1316 | /* Deliver the machine check to host kernel in V mode. */ | |
1317 | MACHINE_CHECK_HANDLER_WINDUP | |
1318 | b machine_check_pSeries | |
1319 | ||
da2bc464 | 1320 | EXC_COMMON_BEGIN(unrecover_mce) |
2749a2f2 MS |
1321 | /* Invoke machine_check_exception to print MCE event and panic. */ |
1322 | addi r3,r1,STACK_FRAME_OVERHEAD | |
ad718622 | 1323 | bl machine_check_exception |
2749a2f2 MS |
1324 | /* |
1325 | * We will not reach here. Even if we did, there is no way out. Call | |
1326 | * unrecoverable_exception and die. | |
1327 | */ | |
1328 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
ad718622 | 1329 | bl unrecoverable_exception |
2749a2f2 | 1330 | b 1b |
da2bc464 | 1331 | |
087aa036 CG |
1332 | /* |
1333 | * r13 points to the PACA, r9 contains the saved CR, | |
1334 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
1335 | * r3 has the faulting address | |
1336 | * r9 - r13 are saved in paca->exslb. | |
1337 | * r3 is saved in paca->slb_r3 | |
f0f558b1 | 1338 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss |
087aa036 CG |
1339 | * We assume we aren't going to take any exceptions during this procedure. |
1340 | */ | |
da2bc464 | 1341 | EXC_COMMON_BEGIN(slb_miss_realmode) |
087aa036 CG |
1342 | mflr r10 |
1343 | #ifdef CONFIG_RELOCATABLE | |
1344 | mtctr r11 | |
1345 | #endif | |
1346 | ||
1347 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1348 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
f0f558b1 | 1349 | std r3,PACA_EXSLB+EX_DAR(r13) |
087aa036 | 1350 | |
f0f558b1 | 1351 | crset 4*cr0+eq |
caca285e AK |
1352 | #ifdef CONFIG_PPC_STD_MMU_64 |
1353 | BEGIN_MMU_FTR_SECTION | |
b1576fec | 1354 | bl slb_allocate_realmode |
5a25b6f5 | 1355 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) |
caca285e | 1356 | #endif |
087aa036 CG |
1357 | |
1358 | ld r10,PACA_EXSLB+EX_LR(r13) | |
1359 | ld r3,PACA_EXSLB+EX_R3(r13) | |
1360 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
087aa036 | 1361 | mtlr r10 |
f0f558b1 PM |
1362 | |
1363 | beq 8f /* if bad address, make full stack frame */ | |
1364 | ||
087aa036 CG |
1365 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ |
1366 | beq- 2f | |
f0f558b1 PM |
1367 | |
1368 | /* All done -- return from exception. */ | |
087aa036 CG |
1369 | |
1370 | .machine push | |
1371 | .machine "power4" | |
1372 | mtcrf 0x80,r9 | |
f0f558b1 | 1373 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ |
087aa036 CG |
1374 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ |
1375 | .machine pop | |
1376 | ||
1377 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
1378 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1379 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1380 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1381 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1382 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1383 | rfid | |
1384 | b . /* prevent speculative execution */ | |
1385 | ||
1386 | 2: mfspr r11,SPRN_SRR0 | |
087aa036 CG |
1387 | LOAD_HANDLER(r10,unrecov_slb) |
1388 | mtspr SPRN_SRR0,r10 | |
1389 | ld r10,PACAKMSR(r13) | |
1390 | mtspr SPRN_SRR1,r10 | |
1391 | rfid | |
1392 | b . | |
1393 | ||
f0f558b1 | 1394 | 8: mfspr r11,SPRN_SRR0 |
f0f558b1 PM |
1395 | LOAD_HANDLER(r10,bad_addr_slb) |
1396 | mtspr SPRN_SRR0,r10 | |
1397 | ld r10,PACAKMSR(r13) | |
1398 | mtspr SPRN_SRR1,r10 | |
1399 | rfid | |
1400 | b . | |
1401 | ||
da2bc464 ME |
1402 | EXC_COMMON_BEGIN(unrecov_slb) |
1403 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
1404 | RECONCILE_IRQ_STATE(r10, r11) | |
1405 | bl save_nvgprs | |
1406 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1407 | bl unrecoverable_exception | |
1408 | b 1b | |
1409 | ||
1410 | ||
1411 | EXC_COMMON_BEGIN(bad_addr_slb) | |
f0f558b1 PM |
1412 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) |
1413 | RECONCILE_IRQ_STATE(r10, r11) | |
1414 | ld r3, PACA_EXSLB+EX_DAR(r13) | |
1415 | std r3, _DAR(r1) | |
1416 | beq cr6, 2f | |
1417 | li r10, 0x480 /* fix trap number for I-SLB miss */ | |
1418 | std r10, _TRAP(r1) | |
1419 | 2: bl save_nvgprs | |
1420 | addi r3, r1, STACK_FRAME_OVERHEAD | |
1421 | bl slb_miss_bad_addr | |
1422 | b ret_from_except | |
087aa036 CG |
1423 | |
1424 | #ifdef CONFIG_PPC_970_NAP | |
da2bc464 | 1425 | TRAMP_REAL_BEGIN(power4_fixup_nap) |
087aa036 CG |
1426 | andc r9,r9,r10 |
1427 | std r9,TI_LOCAL_FLAGS(r11) | |
1428 | ld r10,_LINK(r1) /* make idle task do the */ | |
1429 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1430 | blr | |
1431 | #endif | |
1432 | ||
0ebc4cda BH |
1433 | /* |
1434 | * Hash table stuff | |
1435 | */ | |
1436 | .align 7 | |
6a3bab90 | 1437 | do_hash_page: |
caca285e | 1438 | #ifdef CONFIG_PPC_STD_MMU_64 |
9c7cc234 | 1439 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1440 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1441 | andis. r0,r4,DSISR_DABRMATCH@h |
1442 | bne- handle_dabr_fault | |
9778b696 | 1443 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1444 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1445 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1446 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1447 | |
1448 | /* | |
1449 | * r3 contains the faulting address | |
106713a1 | 1450 | * r4 msr |
0ebc4cda | 1451 | * r5 contains the trap number |
aefa5688 | 1452 | * r6 contains dsisr |
0ebc4cda | 1453 | * |
7230c564 | 1454 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1455 | */ |
106713a1 | 1456 | mr r4,r12 |
aefa5688 | 1457 | ld r6,_DSISR(r1) |
106713a1 AK |
1458 | bl __hash_page /* build HPTE if possible */ |
1459 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1460 | |
7230c564 | 1461 | /* Success */ |
0ebc4cda | 1462 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1463 | |
7230c564 BH |
1464 | /* Error */ |
1465 | blt- 13f | |
caca285e | 1466 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
9c7cc234 | 1467 | |
0ebc4cda BH |
1468 | /* Here we have a page fault that hash_page can't handle. */ |
1469 | handle_page_fault: | |
0ebc4cda BH |
1470 | 11: ld r4,_DAR(r1) |
1471 | ld r5,_DSISR(r1) | |
1472 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1473 | bl do_page_fault |
0ebc4cda | 1474 | cmpdi r3,0 |
a546498f | 1475 | beq+ 12f |
b1576fec | 1476 | bl save_nvgprs |
0ebc4cda BH |
1477 | mr r5,r3 |
1478 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1479 | lwz r4,_DAR(r1) | |
b1576fec AB |
1480 | bl bad_page_fault |
1481 | b ret_from_except | |
0ebc4cda | 1482 | |
a546498f BH |
1483 | /* We have a data breakpoint exception - handle it */ |
1484 | handle_dabr_fault: | |
b1576fec | 1485 | bl save_nvgprs |
a546498f BH |
1486 | ld r4,_DAR(r1) |
1487 | ld r5,_DSISR(r1) | |
1488 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1489 | bl do_break |
1490 | 12: b ret_from_except_lite | |
a546498f | 1491 | |
0ebc4cda | 1492 | |
caca285e | 1493 | #ifdef CONFIG_PPC_STD_MMU_64 |
0ebc4cda BH |
1494 | /* We have a page fault that hash_page could handle but HV refused |
1495 | * the PTE insertion | |
1496 | */ | |
b1576fec | 1497 | 13: bl save_nvgprs |
0ebc4cda BH |
1498 | mr r5,r3 |
1499 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1500 | ld r4,_DAR(r1) | |
b1576fec AB |
1501 | bl low_hash_fault |
1502 | b ret_from_except | |
caca285e | 1503 | #endif |
0ebc4cda | 1504 | |
9c1e1052 PM |
1505 | /* |
1506 | * We come here as a result of a DSI at a point where we don't want | |
1507 | * to call hash_page, such as when we are accessing memory (possibly | |
1508 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1509 | * were soft-disabled. We want to invoke the exception handler for | |
1510 | * the access, or panic if there isn't a handler. | |
1511 | */ | |
b1576fec | 1512 | 77: bl save_nvgprs |
9c1e1052 PM |
1513 | mr r4,r3 |
1514 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1515 | li r5,SIGSEGV | |
b1576fec AB |
1516 | bl bad_page_fault |
1517 | b ret_from_except | |
4e2bf01b ME |
1518 | |
1519 | /* | |
1520 | * Here we have detected that the kernel stack pointer is bad. | |
1521 | * R9 contains the saved CR, r13 points to the paca, | |
1522 | * r10 contains the (bad) kernel stack pointer, | |
1523 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1524 | * We switch to using an emergency stack, save the registers there, | |
1525 | * and call kernel_bad_stack(), which panics. | |
1526 | */ | |
1527 | bad_stack: | |
1528 | ld r1,PACAEMERGSP(r13) | |
1529 | subi r1,r1,64+INT_FRAME_SIZE | |
1530 | std r9,_CCR(r1) | |
1531 | std r10,GPR1(r1) | |
1532 | std r11,_NIP(r1) | |
1533 | std r12,_MSR(r1) | |
1534 | mfspr r11,SPRN_DAR | |
1535 | mfspr r12,SPRN_DSISR | |
1536 | std r11,_DAR(r1) | |
1537 | std r12,_DSISR(r1) | |
1538 | mflr r10 | |
1539 | mfctr r11 | |
1540 | mfxer r12 | |
1541 | std r10,_LINK(r1) | |
1542 | std r11,_CTR(r1) | |
1543 | std r12,_XER(r1) | |
1544 | SAVE_GPR(0,r1) | |
1545 | SAVE_GPR(2,r1) | |
1546 | ld r10,EX_R3(r3) | |
1547 | std r10,GPR3(r1) | |
1548 | SAVE_GPR(4,r1) | |
1549 | SAVE_4GPRS(5,r1) | |
1550 | ld r9,EX_R9(r3) | |
1551 | ld r10,EX_R10(r3) | |
1552 | SAVE_2GPRS(9,r1) | |
1553 | ld r9,EX_R11(r3) | |
1554 | ld r10,EX_R12(r3) | |
1555 | ld r11,EX_R13(r3) | |
1556 | std r9,GPR11(r1) | |
1557 | std r10,GPR12(r1) | |
1558 | std r11,GPR13(r1) | |
1559 | BEGIN_FTR_SECTION | |
1560 | ld r10,EX_CFAR(r3) | |
1561 | std r10,ORIG_GPR3(r1) | |
1562 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1563 | SAVE_8GPRS(14,r1) | |
1564 | SAVE_10GPRS(22,r1) | |
1565 | lhz r12,PACA_TRAP_SAVE(r13) | |
1566 | std r12,_TRAP(r1) | |
1567 | addi r11,r1,INT_FRAME_SIZE | |
1568 | std r11,0(r1) | |
1569 | li r12,0 | |
1570 | std r12,0(r11) | |
1571 | ld r2,PACATOC(r13) | |
1572 | ld r11,exception_marker@toc(r2) | |
1573 | std r12,RESULT(r1) | |
1574 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1575 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1576 | bl kernel_bad_stack | |
1577 | b 1b |