qm-vcpu-list.adoc

   1 [[chapter_qm_vcpu_list]]
   2 Introduction
   3 -------------
   4
   5 This is a list of AMD and Intel x86-64/amd64 CPU types as defined in QEMU,
   6 going back to 2007.
   7
   8 Intel CPU Types
   9 ---------------
  10
  11 https://en.wikipedia.org/wiki/List_of_Intel_Xeon_processors[Intel processors]
  12
  13 * 'Nahelem' : https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)[1st generation of the Intel Core processor]
  14 +
  15 * 'Nahelem-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
  16 +
  17 * 'Westmere' : https://en.wikipedia.org/wiki/Westmere_(microarchitecture)[1st generation of the Intel Core processor (Xeon E7-)]
  18 +
  19 * 'Westmere-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
  20 +
  21 * 'SandyBridge' : https://en.wikipedia.org/wiki/Sandy_Bridge[2nd generation of the Intel Core processor]
  22 +
  23 * 'SandyBridge-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
  24 +
  25 * 'IvyBridge' : https://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)[3rd generation of the Intel Core processor]
  26 +
  27 * 'IvyBridge-IBRS (v2)': add Spectre v1 protection ('+spec-ctrl')
  28 +
  29 * 'Haswell' : https://en.wikipedia.org/wiki/Haswell_(microarchitecture)[4th generation of the Intel Core processor]
  30 +
  31 * 'Haswell-noTSX (v2)' : disable TSX ('-hle', '-rtm')
  32 +
  33 * 'Haswell-IBRS (v3)' : re-add TSX, add Spectre v1 protection ('+hle', '+rtm',
  34 '+spec-ctrl')
  35 +
  36 * 'Haswell-noTSX-IBRS (v4)' : disable TSX ('-hle', '-rtm')
  37 +
  38 * 'Broadwell': https://en.wikipedia.org/wiki/Broadwell_(microarchitecture)[5th generation of the Intel Core processor]
  39 +
  40 * 'Skylake': https://en.wikipedia.org/wiki/Skylake_(microarchitecture)[1st generation Xeon Scalable server processors]
  41 +
  42 * 'Skylake-IBRS (v2)' : add Spectre v1 protection, disable CLFLUSHOPT
  43 ('+spec-ctrl', '-clflushopt')
  44 +
  45 * 'Skylake-noTSX-IBRS (v3)' : disable TSX ('-hle', '-rtm')
  46 +
  47 * 'Skylake-v4': add EPT switching ('+vmx-eptp-switching')
  48 +
  49 * 'Cascadelake': https://en.wikipedia.org/wiki/Cascade_Lake_(microprocessor)[2nd generation Xeon Scalable processor]
  50 +
  51 * 'Cascadelake-v2' : add arch_capabilities msr ('+arch-capabilities',
  52 '+rdctl-no', '+ibrs-all', '+skip-l1dfl-vmentry', '+mds-no')
  53 +
  54 * 'Cascadelake-v3' : disable TSX ('-hle', '-rtm')
  55 +
  56 * 'Cascadelake-v4' : add EPT switching ('+vmx-eptp-switching')
  57 +
  58 * 'Cascadelake-v5' : add XSAVES ('+xsaves', '+vmx-xsaves')
  59 +
  60 * 'Cooperlake' : https://en.wikipedia.org/wiki/Cooper_Lake_(microprocessor)[3rd generation Xeon Scalable processors for 4 & 8 sockets servers]
  61 +
  62 * 'Cooperlake-v2' : add XSAVES ('+xsaves', '+vmx-xsaves')
  63 +
  64 * 'Icelake': https://en.wikipedia.org/wiki/Ice_Lake_(microprocessor)[3rd generation Xeon Scalable server processors]
  65 +
  66 * 'Icelake-v2' : disable TSX ('-hle', '-rtm')
  67 +
  68 * 'Icelake-v3' : add arch_capabilities msr ('+arch-capabilities', '+rdctl-no',
  69 '+ibrs-all', '+skip-l1dfl-vmentry', '+mds-no', '+pschange-mc-no', '+taa-no')
  70 +
  71 * 'Icelake-v4' : add missing flags ('+sha-ni', '+avx512ifma', '+rdpid', '+fsrm',
  72 '+vmx-rdseed-exit', '+vmx-pml', '+vmx-eptp-switching')
  73 +
  74 * 'Icelake-v5' : add XSAVES ('+xsaves', '+vmx-xsaves')
  75 +
  76 * 'Icelake-v6' : add "5-level EPT" ('+vmx-page-walk-5')
  77 +
  78 * 'SapphireRapids' : https://en.wikipedia.org/wiki/Sapphire_Rapids[4th generation Xeon Scalable server processors]
  79
  80
  81 AMD CPU Types
  82 -------------
  83
  84 https://en.wikipedia.org/wiki/List_of_AMD_processors[AMD processors]
  85
  86 * 'Opteron_G3' : https://en.wikipedia.org/wiki/AMD_10h[K10]
  87 +
  88 * 'Opteron_G4' : https://en.wikipedia.org/wiki/Bulldozer_(microarchitecture)[Bulldozer]
  89 +
  90 * 'Opteron_G5' :  https://en.wikipedia.org/wiki/Piledriver_(microarchitecture)[Piledriver]
  91 +
  92 * 'EPYC' : https://en.wikipedia.org/wiki/Zen_(first_generation)[1st generation of Zen processors]
  93 +
  94 * 'EPYC-IBPB (v2)' : add Spectre v1 protection ('+ibpb')
  95 +
  96 * 'EPYC-v3' : add missing flags ('+perfctr-core', '+clzero', '+xsaveerptr',
  97 '+xsaves')
  98 +
  99 * 'EPYC-Rome' : https://en.wikipedia.org/wiki/Zen_2[2nd generation of Zen processors]
 100 +
 101 * 'EPYC-Rome-v2' : add Spectre v2, v4 protection ('+ibrs', '+amd-ssbd')
 102 +
 103 * 'EPYC-Milan' : https://en.wikipedia.org/wiki/Zen_3[3rd generation of Zen processors]
 104 +
 105 * 'EPYC-Milan-v2' : add missing flags ('+vaes', '+vpclmulqdq',
 106 '+stibp-always-on', '+amd-psfd', '+no-nested-data-bp',
 107 '+lfence-always-serializing', '+null-sel-clr-base')
 108