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target-arm: Convert cp15 crn=2 registers
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
9ee6e8bb 2#include "gdbstub.h"
7b59220e 3#include "helper.h"
7bbcb0af 4#include "host-utils.h"
0b03bdfc
PM		 5#include "sysemu.h"
6
0ecb72a5 7static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 8{
9 int nregs;
10
11 /* VFP data registers are always little-endian. */
12 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
13 if (reg < nregs) {
14 stfq_le_p(buf, env->vfp.regs[reg]);
15 return 8;
16 }
17 if (arm_feature(env, ARM_FEATURE_NEON)) {
18 /* Aliases for Q regs. */
19 nregs += 16;
20 if (reg < nregs) {
21 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
22 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
23 return 16;
24 }
25 }
26 switch (reg - nregs) {
27 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
28 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
29 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
30 }
31 return 0;
32}
33
0ecb72a5 34static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 35{
36 int nregs;
37
38 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
39 if (reg < nregs) {
40 env->vfp.regs[reg] = ldfq_le_p(buf);
41 return 8;
42 }
43 if (arm_feature(env, ARM_FEATURE_NEON)) {
44 nregs += 16;
45 if (reg < nregs) {
46 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
47 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
48 return 16;
49 }
50 }
51 switch (reg - nregs) {
52 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
53 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 54 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 55 }
56 return 0;
57}
58
c983fe6c
PM		 59static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
60{
61 env->cp15.c3 = value;
62 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
63 return 0;
64}
65
e9aa6c21
PM		 66static const ARMCPRegInfo cp_reginfo[] = {
67 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
68 * version" bits will read as a reserved value, which should cause
69 * Linux to not try to use the debug hardware.
70 */
71 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
72 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 73 /* MMU Domain access control / MPU write buffer control */
74 { .name = "DACR", .cp = 15,
75 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
76 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
77 .resetvalue = 0, .writefn = dacr_write },
e9aa6c21
PM		 78 REGINFO_SENTINEL
79};
80
7d57f408
PM		 81static const ARMCPRegInfo not_v6_cp_reginfo[] = {
82 /* Not all pre-v6 cores implemented this WFI, so this is slightly
83 * over-broad.
84 */
85 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
86 .access = PL1_W, .type = ARM_CP_WFI },
87 REGINFO_SENTINEL
88};
89
90static const ARMCPRegInfo not_v7_cp_reginfo[] = {
91 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
92 * is UNPREDICTABLE; we choose to NOP as most implementations do).
93 */
94 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
95 .access = PL1_W, .type = ARM_CP_WFI },
96 REGINFO_SENTINEL
97};
98
99static const ARMCPRegInfo v6_cp_reginfo[] = {
100 /* prefetch by MVA in v6, NOP in v7 */
101 { .name = "MVA_prefetch",
102 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
103 .access = PL1_W, .type = ARM_CP_NOP },
104 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
105 .access = PL0_W, .type = ARM_CP_NOP },
106 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
107 .access = PL0_W, .type = ARM_CP_NOP },
108 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
109 .access = PL0_W, .type = ARM_CP_NOP },
110 REGINFO_SENTINEL
111};
112
200ac0ef
PM		 113static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
114 uint64_t *value)
115{
116 /* Generic performance monitor register read function for where
117 * user access may be allowed by PMUSERENR.
118 */
119 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
120 return EXCP_UDEF;
121 }
122 *value = CPREG_FIELD32(env, ri);
123 return 0;
124}
125
126static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
127 uint64_t value)
128{
129 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
130 return EXCP_UDEF;
131 }
132 /* only the DP, X, D and E bits are writable */
133 env->cp15.c9_pmcr &= ~0x39;
134 env->cp15.c9_pmcr |= (value & 0x39);
135 return 0;
136}
137
138static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
139 uint64_t value)
140{
141 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
142 return EXCP_UDEF;
143 }
144 value &= (1 << 31);
145 env->cp15.c9_pmcnten |= value;
146 return 0;
147}
148
149static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
150 uint64_t value)
151{
152 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
153 return EXCP_UDEF;
154 }
155 value &= (1 << 31);
156 env->cp15.c9_pmcnten &= ~value;
157 return 0;
158}
159
160static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
161 uint64_t value)
162{
163 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
164 return EXCP_UDEF;
165 }
166 env->cp15.c9_pmovsr &= ~value;
167 return 0;
168}
169
170static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
171 uint64_t value)
172{
173 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
174 return EXCP_UDEF;
175 }
176 env->cp15.c9_pmxevtyper = value & 0xff;
177 return 0;
178}
179
180static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
181 uint64_t value)
182{
183 env->cp15.c9_pmuserenr = value & 1;
184 return 0;
185}
186
187static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
188 uint64_t value)
189{
190 /* We have no event counters so only the C bit can be changed */
191 value &= (1 << 31);
192 env->cp15.c9_pminten |= value;
193 return 0;
194}
195
196static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
197 uint64_t value)
198{
199 value &= (1 << 31);
200 env->cp15.c9_pminten &= ~value;
201 return 0;
202}
203
e9aa6c21
PM		 204static const ARMCPRegInfo v7_cp_reginfo[] = {
205 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
206 * debug components
207 */
208 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
209 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
210 { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
211 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 212 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
213 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
214 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 215 /* Performance monitors are implementation defined in v7,
216 * but with an ARM recommended set of registers, which we
217 * follow (although we don't actually implement any counters)
218 *
219 * Performance registers fall into three categories:
220 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
221 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
222 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
223 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
224 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
225 */
226 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
227 .access = PL0_RW, .resetvalue = 0,
228 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
229 .readfn = pmreg_read, .writefn = pmcntenset_write },
230 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
231 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
232 .readfn = pmreg_read, .writefn = pmcntenclr_write },
233 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
234 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
235 .readfn = pmreg_read, .writefn = pmovsr_write },
236 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
237 * respect PMUSERENR.
238 */
239 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
240 .access = PL0_W, .type = ARM_CP_NOP },
241 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
242 * We choose to RAZ/WI. XXX should respect PMUSERENR.
243 */
244 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
245 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
246 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
247 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
248 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
249 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
250 .access = PL0_RW,
251 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
252 .readfn = pmreg_read, .writefn = pmxevtyper_write },
253 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
254 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
255 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
256 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
257 .access = PL0_R | PL1_RW,
258 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
259 .resetvalue = 0,
260 .writefn = pmuserenr_write },
261 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
262 .access = PL1_RW,
263 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
264 .resetvalue = 0,
265 .writefn = pmintenset_write },
266 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
267 .access = PL1_RW,
268 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
269 .resetvalue = 0,
270 .writefn = pmintenclr_write },
e9aa6c21
PM		 271 REGINFO_SENTINEL
272};
273
c326b979
PM		 274static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
275{
276 value &= 1;
277 env->teecr = value;
278 return 0;
279}
280
281static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
282 uint64_t *value)
283{
284 /* This is a helper function because the user access rights
285 * depend on the value of the TEECR.
286 */
287 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
288 return EXCP_UDEF;
289 }
290 *value = env->teehbr;
291 return 0;
292}
293
294static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
295 uint64_t value)
296{
297 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
298 return EXCP_UDEF;
299 }
300 env->teehbr = value;
301 return 0;
302}
303
304static const ARMCPRegInfo t2ee_cp_reginfo[] = {
305 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
306 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
307 .resetvalue = 0,
308 .writefn = teecr_write },
309 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
310 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
311 .resetvalue = 0,
312 .readfn = teehbr_read, .writefn = teehbr_write },
313 REGINFO_SENTINEL
314};
315
4d31c596
PM		 316static const ARMCPRegInfo v6k_cp_reginfo[] = {
317 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
318 .access = PL0_RW,
319 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
320 .resetvalue = 0 },
321 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
322 .access = PL0_R|PL1_W,
323 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
324 .resetvalue = 0 },
325 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
326 .access = PL1_RW,
327 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
328 .resetvalue = 0 },
329 REGINFO_SENTINEL
330};
331
6cc7a3ae
PM		 332static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
333 /* Dummy implementation: RAZ/WI the whole crn=14 space */
334 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
335 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
336 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
337 REGINFO_SENTINEL
338};
339
18032bec
PM		 340/* Return basic MPU access permission bits. */
341static uint32_t simple_mpu_ap_bits(uint32_t val)
342{
343 uint32_t ret;
344 uint32_t mask;
345 int i;
346 ret = 0;
347 mask = 3;
348 for (i = 0; i < 16; i += 2) {
349 ret |= (val >> i) & mask;
350 mask <<= 2;
351 }
352 return ret;
353}
354
355/* Pad basic MPU access permission bits to extended format. */
356static uint32_t extended_mpu_ap_bits(uint32_t val)
357{
358 uint32_t ret;
359 uint32_t mask;
360 int i;
361 ret = 0;
362 mask = 3;
363 for (i = 0; i < 16; i += 2) {
364 ret |= (val & mask) << i;
365 mask <<= 2;
366 }
367 return ret;
368}
369
370static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
371 uint64_t value)
372{
373 env->cp15.c5_data = extended_mpu_ap_bits(value);
374 return 0;
375}
376
377static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
378 uint64_t *value)
379{
380 *value = simple_mpu_ap_bits(env->cp15.c5_data);
381 return 0;
382}
383
384static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
385 uint64_t value)
386{
387 env->cp15.c5_insn = extended_mpu_ap_bits(value);
388 return 0;
389}
390
391static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
392 uint64_t *value)
393{
394 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
395 return 0;
396}
397
398static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
399 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
400 .access = PL1_RW,
401 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
402 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
403 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
404 .access = PL1_RW,
405 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
406 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
407 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
408 .access = PL1_RW,
409 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
410 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
411 .access = PL1_RW,
412 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 413 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
414 .access = PL1_RW,
415 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
416 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
417 .access = PL1_RW,
418 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
18032bec
PM		 419 REGINFO_SENTINEL
420};
421
ecce5c3c
PM		 422static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
423 uint64_t value)
424{
425 value &= 7;
426 env->cp15.c2_control = value;
427 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
428 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
429 return 0;
430}
431
432static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
433{
434 env->cp15.c2_base_mask = 0xffffc000u;
435 env->cp15.c2_control = 0;
436 env->cp15.c2_mask = 0;
437}
438
18032bec
PM		 439static const ARMCPRegInfo vmsa_cp_reginfo[] = {
440 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
441 .access = PL1_RW,
442 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
443 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
444 .access = PL1_RW,
445 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 446 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
447 .access = PL1_RW,
448 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
449 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
450 .access = PL1_RW,
451 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
452 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
453 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
454 .resetfn = vmsa_ttbcr_reset,
455 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
18032bec
PM		 456 REGINFO_SENTINEL
457};
458
459static const ARMCPRegInfo omap_cp_reginfo[] = {
460 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
461 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
462 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
463 REGINFO_SENTINEL
464};
465
2ceb98c0
PM		 466void register_cp_regs_for_features(ARMCPU *cpu)
467{
468 /* Register all the coprocessor registers based on feature bits */
469 CPUARMState *env = &cpu->env;
470 if (arm_feature(env, ARM_FEATURE_M)) {
471 /* M profile has no coprocessor registers */
472 return;
473 }
474
e9aa6c21 475 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408
PM		 476 if (arm_feature(env, ARM_FEATURE_V6)) {
477 define_arm_cp_regs(cpu, v6_cp_reginfo);
478 } else {
479 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
480 }
4d31c596
PM		 481 if (arm_feature(env, ARM_FEATURE_V6K)) {
482 define_arm_cp_regs(cpu, v6k_cp_reginfo);
483 }
e9aa6c21 484 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 485 /* v7 performance monitor control register: same implementor
486 * field as main ID register, and we implement no event counters.
487 */
488 ARMCPRegInfo pmcr = {
489 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
490 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
491 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
492 .readfn = pmreg_read, .writefn = pmcr_write
493 };
494 define_one_arm_cp_reg(cpu, &pmcr);
e9aa6c21 495 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 496 } else {
497 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 498 }
18032bec
PM		 499 if (arm_feature(env, ARM_FEATURE_MPU)) {
500 /* These are the MPU registers prior to PMSAv6. Any new
501 * PMSA core later than the ARM946 will require that we
502 * implement the PMSAv6 or PMSAv7 registers, which are
503 * completely different.
504 */
505 assert(!arm_feature(env, ARM_FEATURE_V6));
506 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
507 } else {
508 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
509 }
c326b979
PM		 510 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
511 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
512 }
6cc7a3ae
PM		 513 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
514 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
515 }
18032bec
PM		 516 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
517 define_arm_cp_regs(cpu, omap_cp_reginfo);
518 }
2ceb98c0
PM		 519}
520
778c3a06 521ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 522{
dec9c2d4 523 ARMCPU *cpu;
40f137e1 524 CPUARMState *env;
b26eefb6 525 static int inited = 0;
40f137e1 526
777dc784 527 if (!object_class_by_name(cpu_model)) {
aaed909a 528 return NULL;
777dc784
PM		 529 }
530 cpu = ARM_CPU(object_new(cpu_model));
dec9c2d4 531 env = &cpu->env;
777dc784 532 env->cpu_model_str = cpu_model;
581be094 533 arm_cpu_realize(cpu);
777dc784 534
f4fc247b 535 if (tcg_enabled() && !inited) {
b26eefb6
PB		 536 inited = 1;
537 arm_translate_init();
538 }
539
df90dadb 540 cpu_reset(CPU(cpu));
56aebc89
PB		 541 if (arm_feature(env, ARM_FEATURE_NEON)) {
542 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
543 51, "arm-neon.xml", 0);
544 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
545 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
546 35, "arm-vfp3.xml", 0);
547 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
548 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
549 19, "arm-vfp.xml", 0);
550 }
0bf46a40 551 qemu_init_vcpu(env);
778c3a06 552 return cpu;
40f137e1
PB		 553}
554
777dc784
PM		 555typedef struct ARMCPUListState {
556 fprintf_function cpu_fprintf;
557 FILE *file;
558} ARMCPUListState;
3371d272 559
777dc784
PM		 560/* Sort alphabetically by type name, except for "any". */
561static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 562{
777dc784
PM		 563 ObjectClass *class_a = (ObjectClass *)a;
564 ObjectClass *class_b = (ObjectClass *)b;
565 const char *name_a, *name_b;
5adb4839 566
777dc784
PM		 567 name_a = object_class_get_name(class_a);
568 name_b = object_class_get_name(class_b);
569 if (strcmp(name_a, "any") == 0) {
570 return 1;
571 } else if (strcmp(name_b, "any") == 0) {
572 return -1;
573 } else {
574 return strcmp(name_a, name_b);
5adb4839
PB		 575 }
576}
577
777dc784 578static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 579{
777dc784
PM		 580 ObjectClass *oc = data;
581 ARMCPUListState *s = user_data;
3371d272 582
777dc784
PM		 583 (*s->cpu_fprintf)(s->file, " %s\n",
584 object_class_get_name(oc));
585}
586
587void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
588{
589 ARMCPUListState s = {
590 .file = f,
591 .cpu_fprintf = cpu_fprintf,
592 };
593 GSList *list;
594
595 list = object_class_get_list(TYPE_ARM_CPU, false);
596 list = g_slist_sort(list, arm_cpu_list_compare);
597 (*cpu_fprintf)(f, "Available CPUs:\n");
598 g_slist_foreach(list, arm_cpu_list_entry, &s);
599 g_slist_free(list);
40f137e1
PB		 600}
601
4b6a83fb
PM		 602void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
603 const ARMCPRegInfo *r, void *opaque)
604{
605 /* Define implementations of coprocessor registers.
606 * We store these in a hashtable because typically
607 * there are less than 150 registers in a space which
608 * is 16*16*16*8*8 = 262144 in size.
609 * Wildcarding is supported for the crm, opc1 and opc2 fields.
610 * If a register is defined twice then the second definition is
611 * used, so this can be used to define some generic registers and
612 * then override them with implementation specific variations.
613 * At least one of the original and the second definition should
614 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
615 * against accidental use.
616 */
617 int crm, opc1, opc2;
618 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
619 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
620 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
621 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
622 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
623 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
624 /* 64 bit registers have only CRm and Opc1 fields */
625 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
626 /* Check that the register definition has enough info to handle
627 * reads and writes if they are permitted.
628 */
629 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
630 if (r->access & PL3_R) {
631 assert(r->fieldoffset || r->readfn);
632 }
633 if (r->access & PL3_W) {
634 assert(r->fieldoffset || r->writefn);
635 }
636 }
637 /* Bad type field probably means missing sentinel at end of reg list */
638 assert(cptype_valid(r->type));
639 for (crm = crmmin; crm <= crmmax; crm++) {
640 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
641 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
642 uint32_t *key = g_new(uint32_t, 1);
643 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
644 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
645 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
646 r2->opaque = opaque;
647 /* Make sure reginfo passed to helpers for wildcarded regs
648 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
649 */
650 r2->crm = crm;
651 r2->opc1 = opc1;
652 r2->opc2 = opc2;
653 /* Overriding of an existing definition must be explicitly
654 * requested.
655 */
656 if (!(r->type & ARM_CP_OVERRIDE)) {
657 ARMCPRegInfo *oldreg;
658 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
659 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
660 fprintf(stderr, "Register redefined: cp=%d %d bit "
661 "crn=%d crm=%d opc1=%d opc2=%d, "
662 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
663 r2->crn, r2->crm, r2->opc1, r2->opc2,
664 oldreg->name, r2->name);
665 assert(0);
666 }
667 }
668 g_hash_table_insert(cpu->cp_regs, key, r2);
669 }
670 }
671 }
672}
673
674void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
675 const ARMCPRegInfo *regs, void *opaque)
676{
677 /* Define a whole list of registers */
678 const ARMCPRegInfo *r;
679 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
680 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
681 }
682}
683
684const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
685{
686 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
687}
688
689int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
690 uint64_t value)
691{
692 /* Helper coprocessor write function for write-ignore registers */
693 return 0;
694}
695
696int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
697{
698 /* Helper coprocessor write function for read-as-zero registers */
699 *value = 0;
700 return 0;
701}
702
0ecb72a5 703static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 704{
705 /* Return true if it is not valid for us to switch to
706 * this CPU mode (ie all the UNPREDICTABLE cases in
707 * the ARM ARM CPSRWriteByInstr pseudocode).
708 */
709 switch (mode) {
710 case ARM_CPU_MODE_USR:
711 case ARM_CPU_MODE_SYS:
712 case ARM_CPU_MODE_SVC:
713 case ARM_CPU_MODE_ABT:
714 case ARM_CPU_MODE_UND:
715 case ARM_CPU_MODE_IRQ:
716 case ARM_CPU_MODE_FIQ:
717 return 0;
718 default:
719 return 1;
720 }
721}
722
2f4a40e5
AZ		 723uint32_t cpsr_read(CPUARMState *env)
724{
725 int ZF;
6fbe23d5
PB		 726 ZF = (env->ZF == 0);
727 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 728 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
729 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
730 | ((env->condexec_bits & 0xfc) << 8)
731 | (env->GE << 16);
732}
733
734void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
735{
2f4a40e5 736 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 737 env->ZF = (~val) & CPSR_Z;
738 env->NF = val;
2f4a40e5
AZ		 739 env->CF = (val >> 29) & 1;
740 env->VF = (val << 3) & 0x80000000;
741 }
742 if (mask & CPSR_Q)
743 env->QF = ((val & CPSR_Q) != 0);
744 if (mask & CPSR_T)
745 env->thumb = ((val & CPSR_T) != 0);
746 if (mask & CPSR_IT_0_1) {
747 env->condexec_bits &= ~3;
748 env->condexec_bits |= (val >> 25) & 3;
749 }
750 if (mask & CPSR_IT_2_7) {
751 env->condexec_bits &= 3;
752 env->condexec_bits |= (val >> 8) & 0xfc;
753 }
754 if (mask & CPSR_GE) {
755 env->GE = (val >> 16) & 0xf;
756 }
757
758 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 759 if (bad_mode_switch(env, val & CPSR_M)) {
760 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
761 * We choose to ignore the attempt and leave the CPSR M field
762 * untouched.
763 */
764 mask &= ~CPSR_M;
765 } else {
766 switch_mode(env, val & CPSR_M);
767 }
2f4a40e5
AZ		 768 }
769 mask &= ~CACHED_CPSR_BITS;
770 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
771}
772
b26eefb6
PB		 773/* Sign/zero extend */
774uint32_t HELPER(sxtb16)(uint32_t x)
775{
776 uint32_t res;
777 res = (uint16_t)(int8_t)x;
778 res |= (uint32_t)(int8_t)(x >> 16) << 16;
779 return res;
780}
781
782uint32_t HELPER(uxtb16)(uint32_t x)
783{
784 uint32_t res;
785 res = (uint16_t)(uint8_t)x;
786 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
787 return res;
788}
789
f51bbbfe
PB		 790uint32_t HELPER(clz)(uint32_t x)
791{
7bbcb0af 792 return clz32(x);
f51bbbfe
PB		 793}
794
3670669c
PB		 795int32_t HELPER(sdiv)(int32_t num, int32_t den)
796{
797 if (den == 0)
798 return 0;
686eeb93
AJ		 799 if (num == INT_MIN && den == -1)
800 return INT_MIN;
3670669c
PB		 801 return num / den;
802}
803
804uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
805{
806 if (den == 0)
807 return 0;
808 return num / den;
809}
810
811uint32_t HELPER(rbit)(uint32_t x)
812{
813 x = ((x & 0xff000000) >> 24)
814 | ((x & 0x00ff0000) >> 8)
815 | ((x & 0x0000ff00) << 8)
816 | ((x & 0x000000ff) << 24);
817 x = ((x & 0xf0f0f0f0) >> 4)
818 | ((x & 0x0f0f0f0f) << 4);
819 x = ((x & 0x88888888) >> 3)
820 | ((x & 0x44444444) >> 1)
821 | ((x & 0x22222222) << 1)
822 | ((x & 0x11111111) << 3);
823 return x;
824}
825
ad69471c
PB		 826uint32_t HELPER(abs)(uint32_t x)
827{
828 return ((int32_t)x < 0) ? -x : x;
829}
830
5fafdf24 831#if defined(CONFIG_USER_ONLY)
b5ff1b31 832
0ecb72a5 833void do_interrupt (CPUARMState *env)
b5ff1b31
FB		 834{
835 env->exception_index = -1;
836}
837
0ecb72a5 838int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 839 int mmu_idx)
b5ff1b31
FB		 840{
841 if (rw == 2) {
842 env->exception_index = EXCP_PREFETCH_ABORT;
843 env->cp15.c6_insn = address;
844 } else {
845 env->exception_index = EXCP_DATA_ABORT;
846 env->cp15.c6_data = address;
847 }
848 return 1;
849}
850
0ecb72a5 851void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 852{
853 cpu_abort(env, "cp15 insn %08x\n", insn);
854}
855
0ecb72a5 856uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31
FB		 857{
858 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 859}
860
9ee6e8bb 861/* These should probably raise undefined insn exceptions. */
0ecb72a5 862void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 863{
864 cpu_abort(env, "v7m_mrs %d\n", reg);
865}
866
0ecb72a5 867uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 868{
869 cpu_abort(env, "v7m_mrs %d\n", reg);
870 return 0;
871}
872
0ecb72a5 873void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 874{
875 if (mode != ARM_CPU_MODE_USR)
876 cpu_abort(env, "Tried to switch out of user mode\n");
877}
878
0ecb72a5 879void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 880{
881 cpu_abort(env, "banked r13 write\n");
882}
883
0ecb72a5 884uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 885{
886 cpu_abort(env, "banked r13 read\n");
887 return 0;
888}
889
b5ff1b31
FB		 890#else
891
892/* Map CPU modes onto saved register banks. */
0ecb72a5 893static inline int bank_number(CPUARMState *env, int mode)
b5ff1b31
FB		 894{
895 switch (mode) {
896 case ARM_CPU_MODE_USR:
897 case ARM_CPU_MODE_SYS:
898 return 0;
899 case ARM_CPU_MODE_SVC:
900 return 1;
901 case ARM_CPU_MODE_ABT:
902 return 2;
903 case ARM_CPU_MODE_UND:
904 return 3;
905 case ARM_CPU_MODE_IRQ:
906 return 4;
907 case ARM_CPU_MODE_FIQ:
908 return 5;
909 }
1b9e01c1 910 cpu_abort(env, "Bad mode %x\n", mode);
b5ff1b31
FB		 911 return -1;
912}
913
0ecb72a5 914void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 915{
916 int old_mode;
917 int i;
918
919 old_mode = env->uncached_cpsr & CPSR_M;
920 if (mode == old_mode)
921 return;
922
923 if (old_mode == ARM_CPU_MODE_FIQ) {
924 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 925 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 926 } else if (mode == ARM_CPU_MODE_FIQ) {
927 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 928 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 929 }
930
1b9e01c1 931 i = bank_number(env, old_mode);
b5ff1b31
FB		 932 env->banked_r13[i] = env->regs[13];
933 env->banked_r14[i] = env->regs[14];
934 env->banked_spsr[i] = env->spsr;
935
1b9e01c1 936 i = bank_number(env, mode);
b5ff1b31
FB		 937 env->regs[13] = env->banked_r13[i];
938 env->regs[14] = env->banked_r14[i];
939 env->spsr = env->banked_spsr[i];
940}
941
9ee6e8bb
PB		 942static void v7m_push(CPUARMState *env, uint32_t val)
943{
944 env->regs[13] -= 4;
945 stl_phys(env->regs[13], val);
946}
947
948static uint32_t v7m_pop(CPUARMState *env)
949{
950 uint32_t val;
951 val = ldl_phys(env->regs[13]);
952 env->regs[13] += 4;
953 return val;
954}
955
956/* Switch to V7M main or process stack pointer. */
957static void switch_v7m_sp(CPUARMState *env, int process)
958{
959 uint32_t tmp;
960 if (env->v7m.current_sp != process) {
961 tmp = env->v7m.other_sp;
962 env->v7m.other_sp = env->regs[13];
963 env->regs[13] = tmp;
964 env->v7m.current_sp = process;
965 }
966}
967
968static void do_v7m_exception_exit(CPUARMState *env)
969{
970 uint32_t type;
971 uint32_t xpsr;
972
973 type = env->regs[15];
974 if (env->v7m.exception != 0)
983fe826 975 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 976
977 /* Switch to the target stack. */
978 switch_v7m_sp(env, (type & 4) != 0);
979 /* Pop registers. */
980 env->regs[0] = v7m_pop(env);
981 env->regs[1] = v7m_pop(env);
982 env->regs[2] = v7m_pop(env);
983 env->regs[3] = v7m_pop(env);
984 env->regs[12] = v7m_pop(env);
985 env->regs[14] = v7m_pop(env);
986 env->regs[15] = v7m_pop(env);
987 xpsr = v7m_pop(env);
988 xpsr_write(env, xpsr, 0xfffffdff);
989 /* Undo stack alignment. */
990 if (xpsr & 0x200)
991 env->regs[13] |= 4;
992 /* ??? The exception return type specifies Thread/Handler mode. However
993 this is also implied by the xPSR value. Not sure what to do
994 if there is a mismatch. */
995 /* ??? Likewise for mismatches between the CONTROL register and the stack
996 pointer. */
997}
998
2b3ea315 999static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 1000{
1001 uint32_t xpsr = xpsr_read(env);
1002 uint32_t lr;
1003 uint32_t addr;
1004
1005 lr = 0xfffffff1;
1006 if (env->v7m.current_sp)
1007 lr |= 4;
1008 if (env->v7m.exception == 0)
1009 lr |= 8;
1010
1011 /* For exceptions we just mark as pending on the NVIC, and let that
1012 handle it. */
1013 /* TODO: Need to escalate if the current priority is higher than the
1014 one we're raising. */
1015 switch (env->exception_index) {
1016 case EXCP_UDEF:
983fe826 1017 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1018 return;
1019 case EXCP_SWI:
1020 env->regs[15] += 2;
983fe826 1021 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1022 return;
1023 case EXCP_PREFETCH_ABORT:
1024 case EXCP_DATA_ABORT:
983fe826 1025 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1026 return;
1027 case EXCP_BKPT:
2ad207d4
PB		 1028 if (semihosting_enabled) {
1029 int nr;
d8fd2954 1030 nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1031 if (nr == 0xab) {
1032 env->regs[15] += 2;
1033 env->regs[0] = do_arm_semihosting(env);
1034 return;
1035 }
1036 }
983fe826 1037 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 1038 return;
1039 case EXCP_IRQ:
983fe826 1040 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 1041 break;
1042 case EXCP_EXCEPTION_EXIT:
1043 do_v7m_exception_exit(env);
1044 return;
1045 default:
1046 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1047 return; /* Never happens. Keep compiler happy. */
1048 }
1049
1050 /* Align stack pointer. */
1051 /* ??? Should only do this if Configuration Control Register
1052 STACKALIGN bit is set. */
1053 if (env->regs[13] & 4) {
ab19b0ec 1054 env->regs[13] -= 4;
9ee6e8bb
PB		 1055 xpsr |= 0x200;
1056 }
6c95676b 1057 /* Switch to the handler mode. */
9ee6e8bb
PB		 1058 v7m_push(env, xpsr);
1059 v7m_push(env, env->regs[15]);
1060 v7m_push(env, env->regs[14]);
1061 v7m_push(env, env->regs[12]);
1062 v7m_push(env, env->regs[3]);
1063 v7m_push(env, env->regs[2]);
1064 v7m_push(env, env->regs[1]);
1065 v7m_push(env, env->regs[0]);
1066 switch_v7m_sp(env, 0);
c98d174c
PM		 1067 /* Clear IT bits */
1068 env->condexec_bits = 0;
9ee6e8bb
PB		 1069 env->regs[14] = lr;
1070 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1071 env->regs[15] = addr & 0xfffffffe;
1072 env->thumb = addr & 1;
1073}
1074
b5ff1b31
FB		 1075/* Handle a CPU exception. */
1076void do_interrupt(CPUARMState *env)
1077{
1078 uint32_t addr;
1079 uint32_t mask;
1080 int new_mode;
1081 uint32_t offset;
1082
9ee6e8bb
PB		 1083 if (IS_M(env)) {
1084 do_interrupt_v7m(env);
1085 return;
1086 }
b5ff1b31
FB		 1087 /* TODO: Vectored interrupt controller. */
1088 switch (env->exception_index) {
1089 case EXCP_UDEF:
1090 new_mode = ARM_CPU_MODE_UND;
1091 addr = 0x04;
1092 mask = CPSR_I;
1093 if (env->thumb)
1094 offset = 2;
1095 else
1096 offset = 4;
1097 break;
1098 case EXCP_SWI:
8e71621f
PB		 1099 if (semihosting_enabled) {
1100 /* Check for semihosting interrupt. */
1101 if (env->thumb) {
d8fd2954 1102 mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
8e71621f 1103 } else {
d8fd2954
PB		 1104 mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
1105 & 0xffffff;
8e71621f
PB		 1106 }
1107 /* Only intercept calls from privileged modes, to provide some
1108 semblance of security. */
1109 if (((mask == 0x123456 && !env->thumb)
1110 || (mask == 0xab && env->thumb))
1111 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1112 env->regs[0] = do_arm_semihosting(env);
1113 return;
1114 }
1115 }
b5ff1b31
FB		 1116 new_mode = ARM_CPU_MODE_SVC;
1117 addr = 0x08;
1118 mask = CPSR_I;
601d70b9 1119 /* The PC already points to the next instruction. */
b5ff1b31
FB		 1120 offset = 0;
1121 break;
06c949e6 1122 case EXCP_BKPT:
9ee6e8bb 1123 /* See if this is a semihosting syscall. */
2ad207d4 1124 if (env->thumb && semihosting_enabled) {
d8fd2954 1125 mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 1126 if (mask == 0xab
1127 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1128 env->regs[15] += 2;
1129 env->regs[0] = do_arm_semihosting(env);
1130 return;
1131 }
1132 }
81c05daf 1133 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 1134 /* Fall through to prefetch abort. */
1135 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 1136 new_mode = ARM_CPU_MODE_ABT;
1137 addr = 0x0c;
1138 mask = CPSR_A | CPSR_I;
1139 offset = 4;
1140 break;
1141 case EXCP_DATA_ABORT:
1142 new_mode = ARM_CPU_MODE_ABT;
1143 addr = 0x10;
1144 mask = CPSR_A | CPSR_I;
1145 offset = 8;
1146 break;
1147 case EXCP_IRQ:
1148 new_mode = ARM_CPU_MODE_IRQ;
1149 addr = 0x18;
1150 /* Disable IRQ and imprecise data aborts. */
1151 mask = CPSR_A | CPSR_I;
1152 offset = 4;
1153 break;
1154 case EXCP_FIQ:
1155 new_mode = ARM_CPU_MODE_FIQ;
1156 addr = 0x1c;
1157 /* Disable FIQ, IRQ and imprecise data aborts. */
1158 mask = CPSR_A | CPSR_I | CPSR_F;
1159 offset = 4;
1160 break;
1161 default:
1162 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1163 return; /* Never happens. Keep compiler happy. */
1164 }
1165 /* High vectors. */
1166 if (env->cp15.c1_sys & (1 << 13)) {
1167 addr += 0xffff0000;
1168 }
1169 switch_mode (env, new_mode);
1170 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1171 /* Clear IT bits. */
1172 env->condexec_bits = 0;
30a8cac1 1173 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1174 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1175 env->uncached_cpsr |= mask;
be5e7a76
DES		 1176 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1177 * and we should just guard the thumb mode on V4 */
1178 if (arm_feature(env, ARM_FEATURE_V4T)) {
1179 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1180 }
b5ff1b31
FB		 1181 env->regs[14] = env->regs[15] + offset;
1182 env->regs[15] = addr;
1183 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1184}
1185
1186/* Check section/page access permissions.
1187 Returns the page protection flags, or zero if the access is not
1188 permitted. */
0ecb72a5 1189static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1190 int access_type, int is_user)
b5ff1b31 1191{
9ee6e8bb
PB		 1192 int prot_ro;
1193
dd4ebc2e 1194 if (domain_prot == 3) {
b5ff1b31 1195 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1196 }
b5ff1b31 1197
9ee6e8bb
PB		 1198 if (access_type == 1)
1199 prot_ro = 0;
1200 else
1201 prot_ro = PAGE_READ;
1202
b5ff1b31
FB		 1203 switch (ap) {
1204 case 0:
78600320 1205 if (access_type == 1)
b5ff1b31
FB		 1206 return 0;
1207 switch ((env->cp15.c1_sys >> 8) & 3) {
1208 case 1:
1209 return is_user ? 0 : PAGE_READ;
1210 case 2:
1211 return PAGE_READ;
1212 default:
1213 return 0;
1214 }
1215 case 1:
1216 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1217 case 2:
1218 if (is_user)
9ee6e8bb 1219 return prot_ro;
b5ff1b31
FB		 1220 else
1221 return PAGE_READ | PAGE_WRITE;
1222 case 3:
1223 return PAGE_READ | PAGE_WRITE;
d4934d18 1224 case 4: /* Reserved. */
9ee6e8bb
PB		 1225 return 0;
1226 case 5:
1227 return is_user ? 0 : prot_ro;
1228 case 6:
1229 return prot_ro;
d4934d18 1230 case 7:
0ab06d83 1231 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1232 return 0;
1233 return prot_ro;
b5ff1b31
FB		 1234 default:
1235 abort();
1236 }
1237}
1238
0ecb72a5 1239static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1240{
1241 uint32_t table;
1242
1243 if (address & env->cp15.c2_mask)
1244 table = env->cp15.c2_base1 & 0xffffc000;
1245 else
1246 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1247
1248 table |= (address >> 18) & 0x3ffc;
1249 return table;
1250}
1251
0ecb72a5 1252static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1253 int is_user, uint32_t *phys_ptr, int *prot,
1254 target_ulong *page_size)
b5ff1b31
FB		 1255{
1256 int code;
1257 uint32_t table;
1258 uint32_t desc;
1259 int type;
1260 int ap;
1261 int domain;
dd4ebc2e 1262 int domain_prot;
b5ff1b31
FB		 1263 uint32_t phys_addr;
1264
9ee6e8bb
PB		 1265 /* Pagetable walk. */
1266 /* Lookup l1 descriptor. */
b2fa1797 1267 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1268 desc = ldl_phys(table);
1269 type = (desc & 3);
dd4ebc2e
JCD		 1270 domain = (desc >> 5) & 0x0f;
1271 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1272 if (type == 0) {
601d70b9 1273 /* Section translation fault. */
9ee6e8bb
PB		 1274 code = 5;
1275 goto do_fault;
1276 }
dd4ebc2e 1277 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1278 if (type == 2)
1279 code = 9; /* Section domain fault. */
1280 else
1281 code = 11; /* Page domain fault. */
1282 goto do_fault;
1283 }
1284 if (type == 2) {
1285 /* 1Mb section. */
1286 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1287 ap = (desc >> 10) & 3;
1288 code = 13;
d4c430a8 1289 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1290 } else {
1291 /* Lookup l2 entry. */
1292 if (type == 1) {
1293 /* Coarse pagetable. */
1294 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1295 } else {
1296 /* Fine pagetable. */
1297 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1298 }
1299 desc = ldl_phys(table);
1300 switch (desc & 3) {
1301 case 0: /* Page translation fault. */
1302 code = 7;
1303 goto do_fault;
1304 case 1: /* 64k page. */
1305 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1306 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1307 *page_size = 0x10000;
ce819861 1308 break;
9ee6e8bb
PB		 1309 case 2: /* 4k page. */
1310 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1311 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1312 *page_size = 0x1000;
ce819861 1313 break;
9ee6e8bb
PB		 1314 case 3: /* 1k page. */
1315 if (type == 1) {
1316 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1317 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1318 } else {
1319 /* Page translation fault. */
1320 code = 7;
1321 goto do_fault;
1322 }
1323 } else {
1324 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1325 }
1326 ap = (desc >> 4) & 3;
d4c430a8 1327 *page_size = 0x400;
ce819861
PB		 1328 break;
1329 default:
9ee6e8bb
PB		 1330 /* Never happens, but compiler isn't smart enough to tell. */
1331 abort();
ce819861 1332 }
9ee6e8bb
PB		 1333 code = 15;
1334 }
dd4ebc2e 1335 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 1336 if (!*prot) {
1337 /* Access permission fault. */
1338 goto do_fault;
1339 }
3ad493fc 1340 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1341 *phys_ptr = phys_addr;
1342 return 0;
1343do_fault:
1344 return code | (domain << 4);
1345}
1346
0ecb72a5 1347static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1348 int is_user, uint32_t *phys_ptr, int *prot,
1349 target_ulong *page_size)
9ee6e8bb
PB		 1350{
1351 int code;
1352 uint32_t table;
1353 uint32_t desc;
1354 uint32_t xn;
1355 int type;
1356 int ap;
1357 int domain;
dd4ebc2e 1358 int domain_prot;
9ee6e8bb
PB		 1359 uint32_t phys_addr;
1360
1361 /* Pagetable walk. */
1362 /* Lookup l1 descriptor. */
b2fa1797 1363 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1364 desc = ldl_phys(table);
1365 type = (desc & 3);
1366 if (type == 0) {
601d70b9 1367 /* Section translation fault. */
9ee6e8bb
PB		 1368 code = 5;
1369 domain = 0;
1370 goto do_fault;
1371 } else if (type == 2 && (desc & (1 << 18))) {
1372 /* Supersection. */
1373 domain = 0;
b5ff1b31 1374 } else {
9ee6e8bb 1375 /* Section or page. */
dd4ebc2e 1376 domain = (desc >> 5) & 0x0f;
9ee6e8bb 1377 }
dd4ebc2e
JCD		 1378 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1379 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1380 if (type == 2)
1381 code = 9; /* Section domain fault. */
1382 else
1383 code = 11; /* Page domain fault. */
1384 goto do_fault;
1385 }
1386 if (type == 2) {
1387 if (desc & (1 << 18)) {
1388 /* Supersection. */
1389 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1390 *page_size = 0x1000000;
b5ff1b31 1391 } else {
9ee6e8bb
PB		 1392 /* Section. */
1393 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1394 *page_size = 0x100000;
b5ff1b31 1395 }
9ee6e8bb
PB		 1396 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1397 xn = desc & (1 << 4);
1398 code = 13;
1399 } else {
1400 /* Lookup l2 entry. */
1401 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1402 desc = ldl_phys(table);
1403 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1404 switch (desc & 3) {
1405 case 0: /* Page translation fault. */
1406 code = 7;
b5ff1b31 1407 goto do_fault;
9ee6e8bb
PB		 1408 case 1: /* 64k page. */
1409 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1410 xn = desc & (1 << 15);
d4c430a8 1411 *page_size = 0x10000;
9ee6e8bb
PB		 1412 break;
1413 case 2: case 3: /* 4k page. */
1414 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1415 xn = desc & 1;
d4c430a8 1416 *page_size = 0x1000;
9ee6e8bb
PB		 1417 break;
1418 default:
1419 /* Never happens, but compiler isn't smart enough to tell. */
1420 abort();
b5ff1b31 1421 }
9ee6e8bb
PB		 1422 code = 15;
1423 }
dd4ebc2e 1424 if (domain_prot == 3) {
c0034328
JR		 1425 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1426 } else {
1427 if (xn && access_type == 2)
1428 goto do_fault;
9ee6e8bb 1429
c0034328
JR		 1430 /* The simplified model uses AP[0] as an access control bit. */
1431 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1432 /* Access flag fault. */
1433 code = (code == 15) ? 6 : 3;
1434 goto do_fault;
1435 }
dd4ebc2e 1436 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 1437 if (!*prot) {
1438 /* Access permission fault. */
1439 goto do_fault;
1440 }
1441 if (!xn) {
1442 *prot |= PAGE_EXEC;
1443 }
3ad493fc 1444 }
9ee6e8bb 1445 *phys_ptr = phys_addr;
b5ff1b31
FB		 1446 return 0;
1447do_fault:
1448 return code | (domain << 4);
1449}
1450
0ecb72a5 1451static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type,
9ee6e8bb
PB		 1452 int is_user, uint32_t *phys_ptr, int *prot)
1453{
1454 int n;
1455 uint32_t mask;
1456 uint32_t base;
1457
1458 *phys_ptr = address;
1459 for (n = 7; n >= 0; n--) {
1460 base = env->cp15.c6_region[n];
1461 if ((base & 1) == 0)
1462 continue;
1463 mask = 1 << ((base >> 1) & 0x1f);
1464 /* Keep this shift separate from the above to avoid an
1465 (undefined) << 32. */
1466 mask = (mask << 1) - 1;
1467 if (((base ^ address) & ~mask) == 0)
1468 break;
1469 }
1470 if (n < 0)
1471 return 2;
1472
1473 if (access_type == 2) {
1474 mask = env->cp15.c5_insn;
1475 } else {
1476 mask = env->cp15.c5_data;
1477 }
1478 mask = (mask >> (n * 4)) & 0xf;
1479 switch (mask) {
1480 case 0:
1481 return 1;
1482 case 1:
1483 if (is_user)
1484 return 1;
1485 *prot = PAGE_READ | PAGE_WRITE;
1486 break;
1487 case 2:
1488 *prot = PAGE_READ;
1489 if (!is_user)
1490 *prot |= PAGE_WRITE;
1491 break;
1492 case 3:
1493 *prot = PAGE_READ | PAGE_WRITE;
1494 break;
1495 case 5:
1496 if (is_user)
1497 return 1;
1498 *prot = PAGE_READ;
1499 break;
1500 case 6:
1501 *prot = PAGE_READ;
1502 break;
1503 default:
1504 /* Bad permission. */
1505 return 1;
1506 }
3ad493fc 1507 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1508 return 0;
1509}
1510
0ecb72a5 1511static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 1512 int access_type, int is_user,
d4c430a8
PB		 1513 uint32_t *phys_ptr, int *prot,
1514 target_ulong *page_size)
9ee6e8bb
PB		 1515{
1516 /* Fast Context Switch Extension. */
1517 if (address < 0x02000000)
1518 address += env->cp15.c13_fcse;
1519
1520 if ((env->cp15.c1_sys & 1) == 0) {
1521 /* MMU/MPU disabled. */
1522 *phys_ptr = address;
3ad493fc 1523 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1524 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1525 return 0;
1526 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1527 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1528 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1529 prot);
1530 } else if (env->cp15.c1_sys & (1 << 23)) {
1531 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1532 prot, page_size);
9ee6e8bb
PB		 1533 } else {
1534 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1535 prot, page_size);
9ee6e8bb
PB		 1536 }
1537}
1538
0ecb72a5 1539int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 1540 int access_type, int mmu_idx)
b5ff1b31
FB		 1541{
1542 uint32_t phys_addr;
d4c430a8 1543 target_ulong page_size;
b5ff1b31 1544 int prot;
6ebbf390 1545 int ret, is_user;
b5ff1b31 1546
6ebbf390 1547 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1548 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1549 &page_size);
b5ff1b31
FB		 1550 if (ret == 0) {
1551 /* Map a single [sub]page. */
1552 phys_addr &= ~(uint32_t)0x3ff;
1553 address &= ~(uint32_t)0x3ff;
3ad493fc 1554 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1555 return 0;
b5ff1b31
FB		 1556 }
1557
1558 if (access_type == 2) {
1559 env->cp15.c5_insn = ret;
1560 env->cp15.c6_insn = address;
1561 env->exception_index = EXCP_PREFETCH_ABORT;
1562 } else {
1563 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1564 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1565 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1566 env->cp15.c6_data = address;
1567 env->exception_index = EXCP_DATA_ABORT;
1568 }
1569 return 1;
1570}
1571
0ecb72a5 1572target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31
FB		 1573{
1574 uint32_t phys_addr;
d4c430a8 1575 target_ulong page_size;
b5ff1b31
FB		 1576 int prot;
1577 int ret;
1578
d4c430a8 1579 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1580
1581 if (ret != 0)
1582 return -1;
1583
1584 return phys_addr;
1585}
1586
0ecb72a5 1587void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31 1588{
9ee6e8bb
PB		 1589 int op1;
1590 int op2;
1591 int crm;
b5ff1b31 1592
9ee6e8bb 1593 op1 = (insn >> 21) & 7;
b5ff1b31 1594 op2 = (insn >> 5) & 7;
ce819861 1595 crm = insn & 0xf;
b5ff1b31 1596 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1597 case 0:
9ee6e8bb 1598 /* ID codes. */
610c3c8a
AZ		 1599 if (arm_feature(env, ARM_FEATURE_XSCALE))
1600 break;
c3d2689d
AZ		 1601 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1602 break;
a49ea279
PB		 1603 if (arm_feature(env, ARM_FEATURE_V7)
1604 && op1 == 2 && crm == 0 && op2 == 0) {
1605 env->cp15.c0_cssel = val & 0xf;
1606 break;
1607 }
b5ff1b31
FB		 1608 goto bad_reg;
1609 case 1: /* System configuration. */
2be27624
RH		 1610 if (arm_feature(env, ARM_FEATURE_V7)
1611 && op1 == 0 && crm == 1 && op2 == 0) {
1612 env->cp15.c1_scr = val;
1613 break;
1614 }
c3d2689d
AZ		 1615 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1616 op2 = 0;
b5ff1b31
FB		 1617 switch (op2) {
1618 case 0:
ce819861 1619 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1620 env->cp15.c1_sys = val;
b5ff1b31
FB		 1621 /* ??? Lots of these bits are not implemented. */
1622 /* This may enable/disable the MMU, so do a TLB flush. */
1623 tlb_flush(env, 1);
1624 break;
61cc8701 1625 case 1: /* Auxiliary control register. */
610c3c8a
AZ		 1626 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1627 env->cp15.c1_xscaleauxcr = val;
c1713132 1628 break;
610c3c8a 1629 }
9ee6e8bb
PB		 1630 /* Not implemented. */
1631 break;
b5ff1b31 1632 case 2:
610c3c8a
AZ		 1633 if (arm_feature(env, ARM_FEATURE_XSCALE))
1634 goto bad_reg;
4be27dbb
PB		 1635 if (env->cp15.c1_coproc != val) {
1636 env->cp15.c1_coproc = val;
1637 /* ??? Is this safe when called from within a TB? */
1638 tb_flush(env);
1639 }
c1713132 1640 break;
b5ff1b31
FB		 1641 default:
1642 goto bad_reg;
1643 }
1644 break;
b5ff1b31
FB		 1645 case 4: /* Reserved. */
1646 goto bad_reg;
ce819861
PB		 1647 case 6: /* MMU Fault address / MPU base/size. */
1648 if (arm_feature(env, ARM_FEATURE_MPU)) {
1649 if (crm >= 8)
1650 goto bad_reg;
1651 env->cp15.c6_region[crm] = val;
1652 } else {
c3d2689d
AZ		 1653 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1654 op2 = 0;
ce819861
PB		 1655 switch (op2) {
1656 case 0:
1657 env->cp15.c6_data = val;
1658 break;
9ee6e8bb
PB		 1659 case 1: /* ??? This is WFAR on armv6 */
1660 case 2:
ce819861
PB		 1661 env->cp15.c6_insn = val;
1662 break;
1663 default:
1664 goto bad_reg;
1665 }
1666 }
1667 break;
b5ff1b31 1668 case 7: /* Cache control. */
c3d2689d
AZ		 1669 env->cp15.c15_i_max = 0x000;
1670 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1671 if (op1 != 0) {
1672 goto bad_reg;
1673 }
1674 /* No cache, so nothing to do except VA->PA translations. */
906879a9 1675 if (arm_feature(env, ARM_FEATURE_VAPA)) {
f8bf8606
AL		 1676 switch (crm) {
1677 case 4:
1678 if (arm_feature(env, ARM_FEATURE_V7)) {
1679 env->cp15.c7_par = val & 0xfffff6ff;
1680 } else {
1681 env->cp15.c7_par = val & 0xfffff1ff;
1682 }
1683 break;
1684 case 8: {
1685 uint32_t phys_addr;
1686 target_ulong page_size;
1687 int prot;
1688 int ret, is_user = op2 & 2;
1689 int access_type = op2 & 1;
1690
1691 if (op2 & 4) {
1692 /* Other states are only available with TrustZone */
1693 goto bad_reg;
1694 }
1695 ret = get_phys_addr(env, val, access_type, is_user,
1696 &phys_addr, &prot, &page_size);
1697 if (ret == 0) {
1698 /* We do not set any attribute bits in the PAR */
1699 if (page_size == (1 << 24)
1700 && arm_feature(env, ARM_FEATURE_V7)) {
1701 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1702 } else {
1703 env->cp15.c7_par = phys_addr & 0xfffff000;
1704 }
1705 } else {
1706 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1707 ((ret & (12 << 1)) >> 6) |
1708 ((ret & 0xf) << 1) | 1;
1709 }
1710 break;
1711 }
1712 }
1713 }
b5ff1b31
FB		 1714 break;
1715 case 8: /* MMU TLB control. */
1716 switch (op2) {
dc8714ca
PM		 1717 case 0: /* Invalidate all (TLBIALL) */
1718 tlb_flush(env, 1);
b5ff1b31 1719 break;
dc8714ca 1720 case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
d4c430a8 1721 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1722 break;
dc8714ca 1723 case 2: /* Invalidate by ASID (TLBIASID) */
9ee6e8bb
PB		 1724 tlb_flush(env, val == 0);
1725 break;
dc8714ca
PM		 1726 case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
1727 tlb_flush_page(env, val & TARGET_PAGE_MASK);
9ee6e8bb 1728 break;
b5ff1b31
FB		 1729 default:
1730 goto bad_reg;
1731 }
1732 break;
ce819861 1733 case 9:
c3d2689d
AZ		 1734 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1735 break;
5bc95aa2
DES		 1736 if (arm_feature(env, ARM_FEATURE_STRONGARM))
1737 break; /* Ignore ReadBuffer access */
ce819861
PB		 1738 switch (crm) {
1739 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1740 switch (op1) {
1741 case 0: /* L1 cache. */
1742 switch (op2) {
1743 case 0:
1744 env->cp15.c9_data = val;
1745 break;
1746 case 1:
1747 env->cp15.c9_insn = val;
1748 break;
1749 default:
1750 goto bad_reg;
1751 }
1752 break;
1753 case 1: /* L2 cache. */
1754 /* Ignore writes to L2 lockdown/auxiliary registers. */
1755 break;
1756 default:
1757 goto bad_reg;
1758 }
1759 break;
ce819861
PB		 1760 case 1: /* TCM memory region registers. */
1761 /* Not implemented. */
1762 goto bad_reg;
b5ff1b31
FB		 1763 default:
1764 goto bad_reg;
1765 }
1766 break;
1767 case 10: /* MMU TLB lockdown. */
1768 /* ??? TLB lockdown not implemented. */
1769 break;
b5ff1b31
FB		 1770 case 12: /* Reserved. */
1771 goto bad_reg;
1772 case 13: /* Process ID. */
1773 switch (op2) {
1774 case 0:
d07edbfa
PB		 1775 /* Unlike real hardware the qemu TLB uses virtual addresses,
1776 not modified virtual addresses, so this causes a TLB flush.
1777 */
1778 if (env->cp15.c13_fcse != val)
1779 tlb_flush(env, 1);
1780 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1781 break;
1782 case 1:
d07edbfa 1783 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1784 if (env->cp15.c13_context != val
1785 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1786 tlb_flush(env, 0);
1787 env->cp15.c13_context = val;
b5ff1b31
FB		 1788 break;
1789 default:
1790 goto bad_reg;
1791 }
1792 break;
b5ff1b31 1793 case 15: /* Implementation specific. */
c1713132 1794 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1795 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1796 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1797 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1798 tb_flush(env);
1799 env->cp15.c15_cpar = val & 0x3fff;
1800 }
c1713132
AZ		 1801 break;
1802 }
1803 goto bad_reg;
1804 }
c3d2689d
AZ		 1805 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1806 switch (crm) {
1807 case 0:
1808 break;
1809 case 1: /* Set TI925T configuration. */
1810 env->cp15.c15_ticonfig = val & 0xe7;
1811 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1812 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1813 break;
1814 case 2: /* Set I_max. */
1815 env->cp15.c15_i_max = val;
1816 break;
1817 case 3: /* Set I_min. */
1818 env->cp15.c15_i_min = val;
1819 break;
1820 case 4: /* Set thread-ID. */
1821 env->cp15.c15_threadid = val & 0xffff;
1822 break;
1823 case 8: /* Wait-for-interrupt (deprecated). */
1824 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1825 break;
1826 default:
1827 goto bad_reg;
1828 }
1829 }
7da362d0
ML		 1830 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
1831 switch (crm) {
1832 case 0:
1833 if ((op1 == 0) && (op2 == 0)) {
1834 env->cp15.c15_power_control = val;
1835 } else if ((op1 == 0) && (op2 == 1)) {
1836 env->cp15.c15_diagnostic = val;
1837 } else if ((op1 == 0) && (op2 == 2)) {
1838 env->cp15.c15_power_diagnostic = val;
1839 }
1840 default:
1841 break;
1842 }
1843 }
b5ff1b31
FB		 1844 break;
1845 }
1846 return;
1847bad_reg:
1848 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1849 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1850 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1851}
1852
0ecb72a5 1853uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31 1854{
9ee6e8bb
PB		 1855 int op1;
1856 int op2;
1857 int crm;
b5ff1b31 1858
9ee6e8bb 1859 op1 = (insn >> 21) & 7;
b5ff1b31 1860 op2 = (insn >> 5) & 7;
c3d2689d 1861 crm = insn & 0xf;
b5ff1b31
FB		 1862 switch ((insn >> 16) & 0xf) {
1863 case 0: /* ID codes. */
9ee6e8bb
PB		 1864 switch (op1) {
1865 case 0:
1866 switch (crm) {
1867 case 0:
1868 switch (op2) {
1869 case 0: /* Device ID. */
1870 return env->cp15.c0_cpuid;
1871 case 1: /* Cache Type. */
1872 return env->cp15.c0_cachetype;
1873 case 2: /* TCM status. */
1874 return 0;
1875 case 3: /* TLB type register. */
1876 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1877 case 5: /* MPIDR */
1878 /* The MPIDR was standardised in v7; prior to
1879 * this it was implemented only in the 11MPCore.
1880 * For all other pre-v7 cores it does not exist.
1881 */
1882 if (arm_feature(env, ARM_FEATURE_V7) ||
1883 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1884 int mpidr = env->cpu_index;
1885 /* We don't support setting cluster ID ([8..11])
1886 * so these bits always RAZ.
1887 */
1888 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1889 mpidr |= (1 << 31);
1890 /* Cores which are uniprocessor (non-coherent)
1891 * but still implement the MP extensions set
1892 * bit 30. (For instance, A9UP.) However we do
1893 * not currently model any of those cores.
1894 */
1895 }
1896 return mpidr;
10055562 1897 }
607b4b08 1898 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1899 default:
1900 goto bad_reg;
1901 }
1902 case 1:
1903 if (!arm_feature(env, ARM_FEATURE_V6))
1904 goto bad_reg;
1905 return env->cp15.c0_c1[op2];
1906 case 2:
1907 if (!arm_feature(env, ARM_FEATURE_V6))
1908 goto bad_reg;
1909 return env->cp15.c0_c2[op2];
1910 case 3: case 4: case 5: case 6: case 7:
1911 return 0;
1912 default:
1913 goto bad_reg;
1914 }
1915 case 1:
1916 /* These registers aren't documented on arm11 cores. However
1917 Linux looks at them anyway. */
1918 if (!arm_feature(env, ARM_FEATURE_V6))
1919 goto bad_reg;
1920 if (crm != 0)
1921 goto bad_reg;
a49ea279
PB		 1922 if (!arm_feature(env, ARM_FEATURE_V7))
1923 return 0;
1924
1925 switch (op2) {
1926 case 0:
1927 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1928 case 1:
1929 return env->cp15.c0_clid;
1930 case 7:
1931 return 0;
1932 }
1933 goto bad_reg;
1934 case 2:
1935 if (op2 != 0 || crm != 0)
610c3c8a 1936 goto bad_reg;
a49ea279 1937 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1938 default:
1939 goto bad_reg;
b5ff1b31
FB		 1940 }
1941 case 1: /* System configuration. */
2be27624
RH		 1942 if (arm_feature(env, ARM_FEATURE_V7)
1943 && op1 == 0 && crm == 1 && op2 == 0) {
1944 return env->cp15.c1_scr;
1945 }
c3d2689d
AZ		 1946 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1947 op2 = 0;
b5ff1b31
FB		 1948 switch (op2) {
1949 case 0: /* Control register. */
1950 return env->cp15.c1_sys;
1951 case 1: /* Auxiliary control register. */
c1713132 1952 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1953 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1954 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1955 goto bad_reg;
1956 switch (ARM_CPUID(env)) {
1957 case ARM_CPUID_ARM1026:
1958 return 1;
1959 case ARM_CPUID_ARM1136:
827df9f3 1960 case ARM_CPUID_ARM1136_R2:
7807eed9 1961 case ARM_CPUID_ARM1176:
9ee6e8bb
PB		 1962 return 7;
1963 case ARM_CPUID_ARM11MPCORE:
1964 return 1;
1965 case ARM_CPUID_CORTEXA8:
533d177a 1966 return 2;
10055562 1967 case ARM_CPUID_CORTEXA9:
0b03bdfc 1968 case ARM_CPUID_CORTEXA15:
10055562 1969 return 0;
9ee6e8bb
PB		 1970 default:
1971 goto bad_reg;
1972 }
b5ff1b31 1973 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1974 if (arm_feature(env, ARM_FEATURE_XSCALE))
1975 goto bad_reg;
b5ff1b31
FB		 1976 return env->cp15.c1_coproc;
1977 default:
1978 goto bad_reg;
1979 }
b5ff1b31
FB		 1980 case 4: /* Reserved. */
1981 goto bad_reg;
9ee6e8bb 1982 case 6: /* MMU Fault address. */
ce819861 1983 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1984 if (crm >= 8)
ce819861 1985 goto bad_reg;
9ee6e8bb 1986 return env->cp15.c6_region[crm];
ce819861 1987 } else {
c3d2689d
AZ		 1988 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1989 op2 = 0;
9ee6e8bb
PB		 1990 switch (op2) {
1991 case 0:
1992 return env->cp15.c6_data;
1993 case 1:
1994 if (arm_feature(env, ARM_FEATURE_V6)) {
1995 /* Watchpoint Fault Adrress. */
1996 return 0; /* Not implemented. */
1997 } else {
1998 /* Instruction Fault Adrress. */
1999 /* Arm9 doesn't have an IFAR, but implementing it anyway
2000 shouldn't do any harm. */
2001 return env->cp15.c6_insn;
2002 }
2003 case 2:
2004 if (arm_feature(env, ARM_FEATURE_V6)) {
2005 /* Instruction Fault Adrress. */
2006 return env->cp15.c6_insn;
2007 } else {
2008 goto bad_reg;
2009 }
2010 default:
2011 goto bad_reg;
2012 }
b5ff1b31
FB		 2013 }
2014 case 7: /* Cache control. */
f8bf8606
AL		 2015 if (crm == 4 && op1 == 0 && op2 == 0) {
2016 return env->cp15.c7_par;
2017 }
6fbe23d5
PB		 2018 /* FIXME: Should only clear Z flag if destination is r15. */
2019 env->ZF = 0;
b5ff1b31
FB		 2020 return 0;
2021 case 8: /* MMU TLB control. */
2022 goto bad_reg;
74594c9d
PM		 2023 case 9:
2024 switch (crm) {
2025 case 0: /* Cache lockdown */
2026 switch (op1) {
2027 case 0: /* L1 cache. */
2028 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2029 return 0;
2030 }
2031 switch (op2) {
2032 case 0:
2033 return env->cp15.c9_data;
2034 case 1:
2035 return env->cp15.c9_insn;
2036 default:
2037 goto bad_reg;
2038 }
2039 case 1: /* L2 cache */
0b03bdfc
PM		 2040 /* L2 Lockdown and Auxiliary control. */
2041 switch (op2) {
2042 case 0:
2043 /* L2 cache lockdown (A8 only) */
2044 return 0;
2045 case 2:
2046 /* L2 cache auxiliary control (A8) or control (A15) */
2047 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA15) {
2048 /* Linux wants the number of processors from here.
2049 * Might as well set the interrupt-controller bit too.
2050 */
2051 return ((smp_cpus - 1) << 24) | (1 << 23);
2052 }
2053 return 0;
2054 case 3:
2055 /* L2 cache extended control (A15) */
2056 return 0;
2057 default:
74594c9d
PM		 2058 goto bad_reg;
2059 }
74594c9d
PM		 2060 default:
2061 goto bad_reg;
2062 }
2063 break;
b5ff1b31
FB		 2064 default:
2065 goto bad_reg;
2066 }
74594c9d 2067 break;
b5ff1b31
FB		 2068 case 10: /* MMU TLB lockdown. */
2069 /* ??? TLB lockdown not implemented. */
2070 return 0;
2071 case 11: /* TCM DMA control. */
2072 case 12: /* Reserved. */
2073 goto bad_reg;
2074 case 13: /* Process ID. */
2075 switch (op2) {
2076 case 0:
2077 return env->cp15.c13_fcse;
2078 case 1:
2079 return env->cp15.c13_context;
2080 default:
2081 goto bad_reg;
2082 }
b5ff1b31 2083 case 15: /* Implementation specific. */
c1713132 2084 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 2085 if (op2 == 0 && crm == 1)
c1713132
AZ		 2086 return env->cp15.c15_cpar;
2087
2088 goto bad_reg;
2089 }
c3d2689d
AZ		 2090 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2091 switch (crm) {
2092 case 0:
2093 return 0;
2094 case 1: /* Read TI925T configuration. */
2095 return env->cp15.c15_ticonfig;
2096 case 2: /* Read I_max. */
2097 return env->cp15.c15_i_max;
2098 case 3: /* Read I_min. */
2099 return env->cp15.c15_i_min;
2100 case 4: /* Read thread-ID. */
2101 return env->cp15.c15_threadid;
2102 case 8: /* TI925T_status */
2103 return 0;
2104 }
827df9f3
AZ		 2105 /* TODO: Peripheral port remap register:
2106 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2107 * controller base address at $rn & ~0xfff and map size of
2108 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 2109 goto bad_reg;
2110 }
7da362d0
ML		 2111 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
2112 switch (crm) {
2113 case 0:
2114 if ((op1 == 4) && (op2 == 0)) {
2115 /* The config_base_address should hold the value of
2116 * the peripheral base. ARM should get this from a CPU
2117 * object property, but that support isn't available in
2118 * December 2011. Default to 0 for now and board models
2119 * that care can set it by a private hook */
2120 return env->cp15.c15_config_base_address;
2121 } else if ((op1 == 0) && (op2 == 0)) {
2122 /* power_control should be set to maximum latency. Again,
2123 default to 0 and set by private hook */
2124 return env->cp15.c15_power_control;
2125 } else if ((op1 == 0) && (op2 == 1)) {
2126 return env->cp15.c15_diagnostic;
2127 } else if ((op1 == 0) && (op2 == 2)) {
2128 return env->cp15.c15_power_diagnostic;
2129 }
2130 break;
2131 case 1: /* NEON Busy */
2132 return 0;
2133 case 5: /* tlb lockdown */
2134 case 6:
2135 case 7:
2136 if ((op1 == 5) && (op2 == 2)) {
2137 return 0;
2138 }
2139 break;
2140 default:
2141 break;
2142 }
2143 goto bad_reg;
2144 }
b5ff1b31
FB		 2145 return 0;
2146 }
2147bad_reg:
2148 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2149 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2150 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2151 return 0;
2152}
2153
0ecb72a5 2154void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2155{
39ea3d4e
PM		 2156 if ((env->uncached_cpsr & CPSR_M) == mode) {
2157 env->regs[13] = val;
2158 } else {
1b9e01c1 2159 env->banked_r13[bank_number(env, mode)] = val;
39ea3d4e 2160 }
9ee6e8bb
PB		 2161}
2162
0ecb72a5 2163uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2164{
39ea3d4e
PM		 2165 if ((env->uncached_cpsr & CPSR_M) == mode) {
2166 return env->regs[13];
2167 } else {
1b9e01c1 2168 return env->banked_r13[bank_number(env, mode)];
39ea3d4e 2169 }
9ee6e8bb
PB		 2170}
2171
0ecb72a5 2172uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2173{
2174 switch (reg) {
2175 case 0: /* APSR */
2176 return xpsr_read(env) & 0xf8000000;
2177 case 1: /* IAPSR */
2178 return xpsr_read(env) & 0xf80001ff;
2179 case 2: /* EAPSR */
2180 return xpsr_read(env) & 0xff00fc00;
2181 case 3: /* xPSR */
2182 return xpsr_read(env) & 0xff00fdff;
2183 case 5: /* IPSR */
2184 return xpsr_read(env) & 0x000001ff;
2185 case 6: /* EPSR */
2186 return xpsr_read(env) & 0x0700fc00;
2187 case 7: /* IEPSR */
2188 return xpsr_read(env) & 0x0700edff;
2189 case 8: /* MSP */
2190 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2191 case 9: /* PSP */
2192 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2193 case 16: /* PRIMASK */
2194 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2195 case 17: /* BASEPRI */
2196 case 18: /* BASEPRI_MAX */
9ee6e8bb 2197 return env->v7m.basepri;
82845826
SH		 2198 case 19: /* FAULTMASK */
2199 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2200 case 20: /* CONTROL */
2201 return env->v7m.control;
2202 default:
2203 /* ??? For debugging only. */
2204 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2205 return 0;
2206 }
2207}
2208
0ecb72a5 2209void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2210{
2211 switch (reg) {
2212 case 0: /* APSR */
2213 xpsr_write(env, val, 0xf8000000);
2214 break;
2215 case 1: /* IAPSR */
2216 xpsr_write(env, val, 0xf8000000);
2217 break;
2218 case 2: /* EAPSR */
2219 xpsr_write(env, val, 0xfe00fc00);
2220 break;
2221 case 3: /* xPSR */
2222 xpsr_write(env, val, 0xfe00fc00);
2223 break;
2224 case 5: /* IPSR */
2225 /* IPSR bits are readonly. */
2226 break;
2227 case 6: /* EPSR */
2228 xpsr_write(env, val, 0x0600fc00);
2229 break;
2230 case 7: /* IEPSR */
2231 xpsr_write(env, val, 0x0600fc00);
2232 break;
2233 case 8: /* MSP */
2234 if (env->v7m.current_sp)
2235 env->v7m.other_sp = val;
2236 else
2237 env->regs[13] = val;
2238 break;
2239 case 9: /* PSP */
2240 if (env->v7m.current_sp)
2241 env->regs[13] = val;
2242 else
2243 env->v7m.other_sp = val;
2244 break;
2245 case 16: /* PRIMASK */
2246 if (val & 1)
2247 env->uncached_cpsr |= CPSR_I;
2248 else
2249 env->uncached_cpsr &= ~CPSR_I;
2250 break;
82845826 2251 case 17: /* BASEPRI */
9ee6e8bb
PB		 2252 env->v7m.basepri = val & 0xff;
2253 break;
82845826 2254 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2255 val &= 0xff;
2256 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2257 env->v7m.basepri = val;
2258 break;
82845826
SH		 2259 case 19: /* FAULTMASK */
2260 if (val & 1)
2261 env->uncached_cpsr |= CPSR_F;
2262 else
2263 env->uncached_cpsr &= ~CPSR_F;
2264 break;
9ee6e8bb
PB		 2265 case 20: /* CONTROL */
2266 env->v7m.control = val & 3;
2267 switch_v7m_sp(env, (val & 2) != 0);
2268 break;
2269 default:
2270 /* ??? For debugging only. */
2271 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2272 return;
2273 }
2274}
2275
b5ff1b31 2276#endif
6ddbc6e4
PB		 2277
2278/* Note that signed overflow is undefined in C. The following routines are
2279 careful to use unsigned types where modulo arithmetic is required.
2280 Failure to do so _will_ break on newer gcc. */
2281
2282/* Signed saturating arithmetic. */
2283
1654b2d6 2284/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2285static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2286{
2287 uint16_t res;
2288
2289 res = a + b;
2290 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2291 if (a & 0x8000)
2292 res = 0x8000;
2293 else
2294 res = 0x7fff;
2295 }
2296 return res;
2297}
2298
1654b2d6 2299/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2300static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2301{
2302 uint8_t res;
2303
2304 res = a + b;
2305 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2306 if (a & 0x80)
2307 res = 0x80;
2308 else
2309 res = 0x7f;
2310 }
2311 return res;
2312}
2313
1654b2d6 2314/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2315static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2316{
2317 uint16_t res;
2318
2319 res = a - b;
2320 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2321 if (a & 0x8000)
2322 res = 0x8000;
2323 else
2324 res = 0x7fff;
2325 }
2326 return res;
2327}
2328
1654b2d6 2329/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2330static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2331{
2332 uint8_t res;
2333
2334 res = a - b;
2335 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2336 if (a & 0x80)
2337 res = 0x80;
2338 else
2339 res = 0x7f;
2340 }
2341 return res;
2342}
2343
2344#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2345#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2346#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2347#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2348#define PFX q
2349
2350#include "op_addsub.h"
2351
2352/* Unsigned saturating arithmetic. */
460a09c1 2353static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2354{
2355 uint16_t res;
2356 res = a + b;
2357 if (res < a)
2358 res = 0xffff;
2359 return res;
2360}
2361
460a09c1 2362static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2363{
4c4fd3f8 2364 if (a > b)
6ddbc6e4
PB		 2365 return a - b;
2366 else
2367 return 0;
2368}
2369
2370static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2371{
2372 uint8_t res;
2373 res = a + b;
2374 if (res < a)
2375 res = 0xff;
2376 return res;
2377}
2378
2379static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2380{
4c4fd3f8 2381 if (a > b)
6ddbc6e4
PB		 2382 return a - b;
2383 else
2384 return 0;
2385}
2386
2387#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2388#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2389#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2390#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2391#define PFX uq
2392
2393#include "op_addsub.h"
2394
2395/* Signed modulo arithmetic. */
2396#define SARITH16(a, b, n, op) do { \
2397 int32_t sum; \
db6e2e65 2398 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2399 RESULT(sum, n, 16); \
2400 if (sum >= 0) \
2401 ge |= 3 << (n * 2); \
2402 } while(0)
2403
2404#define SARITH8(a, b, n, op) do { \
2405 int32_t sum; \
db6e2e65 2406 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2407 RESULT(sum, n, 8); \
2408 if (sum >= 0) \
2409 ge |= 1 << n; \
2410 } while(0)
2411
2412
2413#define ADD16(a, b, n) SARITH16(a, b, n, +)
2414#define SUB16(a, b, n) SARITH16(a, b, n, -)
2415#define ADD8(a, b, n) SARITH8(a, b, n, +)
2416#define SUB8(a, b, n) SARITH8(a, b, n, -)
2417#define PFX s
2418#define ARITH_GE
2419
2420#include "op_addsub.h"
2421
2422/* Unsigned modulo arithmetic. */
2423#define ADD16(a, b, n) do { \
2424 uint32_t sum; \
2425 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2426 RESULT(sum, n, 16); \
a87aa10b 2427 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2428 ge |= 3 << (n * 2); \
2429 } while(0)
2430
2431#define ADD8(a, b, n) do { \
2432 uint32_t sum; \
2433 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2434 RESULT(sum, n, 8); \
a87aa10b
AZ		 2435 if ((sum >> 8) == 1) \
2436 ge |= 1 << n; \
6ddbc6e4
PB		 2437 } while(0)
2438
2439#define SUB16(a, b, n) do { \
2440 uint32_t sum; \
2441 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2442 RESULT(sum, n, 16); \
2443 if ((sum >> 16) == 0) \
2444 ge |= 3 << (n * 2); \
2445 } while(0)
2446
2447#define SUB8(a, b, n) do { \
2448 uint32_t sum; \
2449 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2450 RESULT(sum, n, 8); \
2451 if ((sum >> 8) == 0) \
a87aa10b 2452 ge |= 1 << n; \
6ddbc6e4
PB		 2453 } while(0)
2454
2455#define PFX u
2456#define ARITH_GE
2457
2458#include "op_addsub.h"
2459
2460/* Halved signed arithmetic. */
2461#define ADD16(a, b, n) \
2462 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2463#define SUB16(a, b, n) \
2464 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2465#define ADD8(a, b, n) \
2466 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2467#define SUB8(a, b, n) \
2468 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2469#define PFX sh
2470
2471#include "op_addsub.h"
2472
2473/* Halved unsigned arithmetic. */
2474#define ADD16(a, b, n) \
2475 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2476#define SUB16(a, b, n) \
2477 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2478#define ADD8(a, b, n) \
2479 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2480#define SUB8(a, b, n) \
2481 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2482#define PFX uh
2483
2484#include "op_addsub.h"
2485
2486static inline uint8_t do_usad(uint8_t a, uint8_t b)
2487{
2488 if (a > b)
2489 return a - b;
2490 else
2491 return b - a;
2492}
2493
2494/* Unsigned sum of absolute byte differences. */
2495uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2496{
2497 uint32_t sum;
2498 sum = do_usad(a, b);
2499 sum += do_usad(a >> 8, b >> 8);
2500 sum += do_usad(a >> 16, b >>16);
2501 sum += do_usad(a >> 24, b >> 24);
2502 return sum;
2503}
2504
2505/* For ARMv6 SEL instruction. */
2506uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2507{
2508 uint32_t mask;
2509
2510 mask = 0;
2511 if (flags & 1)
2512 mask |= 0xff;
2513 if (flags & 2)
2514 mask |= 0xff00;
2515 if (flags & 4)
2516 mask |= 0xff0000;
2517 if (flags & 8)
2518 mask |= 0xff000000;
2519 return (a & mask) | (b & ~mask);
2520}
2521
5e3f878a
PB		 2522uint32_t HELPER(logicq_cc)(uint64_t val)
2523{
2524 return (val >> 32) | (val != 0);
2525}
4373f3ce
PB		 2526
2527/* VFP support. We follow the convention used for VFP instrunctions:
2528 Single precition routines have a "s" suffix, double precision a
2529 "d" suffix. */
2530
2531/* Convert host exception flags to vfp form. */
2532static inline int vfp_exceptbits_from_host(int host_bits)
2533{
2534 int target_bits = 0;
2535
2536 if (host_bits & float_flag_invalid)
2537 target_bits |= 1;
2538 if (host_bits & float_flag_divbyzero)
2539 target_bits |= 2;
2540 if (host_bits & float_flag_overflow)
2541 target_bits |= 4;
36802b6b 2542 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2543 target_bits |= 8;
2544 if (host_bits & float_flag_inexact)
2545 target_bits |= 0x10;
cecd8504
PM		 2546 if (host_bits & float_flag_input_denormal)
2547 target_bits |= 0x80;
4373f3ce
PB		 2548 return target_bits;
2549}
2550
0ecb72a5 2551uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2552{
2553 int i;
2554 uint32_t fpscr;
2555
2556 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2557 | (env->vfp.vec_len << 16)
2558 | (env->vfp.vec_stride << 20);
2559 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2560 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2561 fpscr |= vfp_exceptbits_from_host(i);
2562 return fpscr;
2563}
2564
0ecb72a5 2565uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2566{
2567 return HELPER(vfp_get_fpscr)(env);
2568}
2569
4373f3ce
PB		 2570/* Convert vfp exception flags to target form. */
2571static inline int vfp_exceptbits_to_host(int target_bits)
2572{
2573 int host_bits = 0;
2574
2575 if (target_bits & 1)
2576 host_bits |= float_flag_invalid;
2577 if (target_bits & 2)
2578 host_bits |= float_flag_divbyzero;
2579 if (target_bits & 4)
2580 host_bits |= float_flag_overflow;
2581 if (target_bits & 8)
2582 host_bits |= float_flag_underflow;
2583 if (target_bits & 0x10)
2584 host_bits |= float_flag_inexact;
cecd8504
PM		 2585 if (target_bits & 0x80)
2586 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2587 return host_bits;
2588}
2589
0ecb72a5 2590void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2591{
2592 int i;
2593 uint32_t changed;
2594
2595 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2596 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2597 env->vfp.vec_len = (val >> 16) & 7;
2598 env->vfp.vec_stride = (val >> 20) & 3;
2599
2600 changed ^= val;
2601 if (changed & (3 << 22)) {
2602 i = (val >> 22) & 3;
2603 switch (i) {
2604 case 0:
2605 i = float_round_nearest_even;
2606 break;
2607 case 1:
2608 i = float_round_up;
2609 break;
2610 case 2:
2611 i = float_round_down;
2612 break;
2613 case 3:
2614 i = float_round_to_zero;
2615 break;
2616 }
2617 set_float_rounding_mode(i, &env->vfp.fp_status);
2618 }
cecd8504 2619 if (changed & (1 << 24)) {
fe76d976 2620 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2621 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2622 }
5c7908ed
PB		 2623 if (changed & (1 << 25))
2624 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2625
b12c390b 2626 i = vfp_exceptbits_to_host(val);
4373f3ce 2627 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2628 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2629}
2630
0ecb72a5 2631void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 2632{
2633 HELPER(vfp_set_fpscr)(env, val);
2634}
2635
4373f3ce
PB		 2636#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2637
2638#define VFP_BINOP(name) \
ae1857ec 2639float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2640{ \
ae1857ec
PM		 2641 float_status *fpst = fpstp; \
2642 return float32_ ## name(a, b, fpst); \
4373f3ce 2643} \
ae1857ec 2644float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2645{ \
ae1857ec
PM		 2646 float_status *fpst = fpstp; \
2647 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2648}
2649VFP_BINOP(add)
2650VFP_BINOP(sub)
2651VFP_BINOP(mul)
2652VFP_BINOP(div)
2653#undef VFP_BINOP
2654
2655float32 VFP_HELPER(neg, s)(float32 a)
2656{
2657 return float32_chs(a);
2658}
2659
2660float64 VFP_HELPER(neg, d)(float64 a)
2661{
66230e0d 2662 return float64_chs(a);
4373f3ce
PB		 2663}
2664
2665float32 VFP_HELPER(abs, s)(float32 a)
2666{
2667 return float32_abs(a);
2668}
2669
2670float64 VFP_HELPER(abs, d)(float64 a)
2671{
66230e0d 2672 return float64_abs(a);
4373f3ce
PB		 2673}
2674
0ecb72a5 2675float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 2676{
2677 return float32_sqrt(a, &env->vfp.fp_status);
2678}
2679
0ecb72a5 2680float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 2681{
2682 return float64_sqrt(a, &env->vfp.fp_status);
2683}
2684
2685/* XXX: check quiet/signaling case */
2686#define DO_VFP_cmp(p, type) \
0ecb72a5 2687void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2688{ \
2689 uint32_t flags; \
2690 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2691 case 0: flags = 0x6; break; \
2692 case -1: flags = 0x8; break; \
2693 case 1: flags = 0x2; break; \
2694 default: case 2: flags = 0x3; break; \
2695 } \
2696 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2697 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2698} \
0ecb72a5 2699void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2700{ \
2701 uint32_t flags; \
2702 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2703 case 0: flags = 0x6; break; \
2704 case -1: flags = 0x8; break; \
2705 case 1: flags = 0x2; break; \
2706 default: case 2: flags = 0x3; break; \
2707 } \
2708 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2709 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2710}
2711DO_VFP_cmp(s, float32)
2712DO_VFP_cmp(d, float64)
2713#undef DO_VFP_cmp
2714
5500b06c 2715/* Integer to float and float to integer conversions */
4373f3ce 2716
5500b06c
PM		 2717#define CONV_ITOF(name, fsz, sign) \
2718 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2719{ \
2720 float_status *fpst = fpstp; \
85836979 2721 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 2722}
2723
5500b06c
PM		 2724#define CONV_FTOI(name, fsz, sign, round) \
2725uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2726{ \
2727 float_status *fpst = fpstp; \
2728 if (float##fsz##_is_any_nan(x)) { \
2729 float_raise(float_flag_invalid, fpst); \
2730 return 0; \
2731 } \
2732 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2733}
2734
5500b06c
PM		 2735#define FLOAT_CONVS(name, p, fsz, sign) \
2736CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2737CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2738CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2739
5500b06c
PM		 2740FLOAT_CONVS(si, s, 32, )
2741FLOAT_CONVS(si, d, 64, )
2742FLOAT_CONVS(ui, s, 32, u)
2743FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2744
5500b06c
PM		 2745#undef CONV_ITOF
2746#undef CONV_FTOI
2747#undef FLOAT_CONVS
4373f3ce
PB		 2748
2749/* floating point conversion */
0ecb72a5 2750float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 2751{
2d627737
PM		 2752 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2753 /* ARM requires that S<->D conversion of any kind of NaN generates
2754 * a quiet NaN by forcing the most significant frac bit to 1.
2755 */
2756 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2757}
2758
0ecb72a5 2759float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 2760{
2d627737
PM		 2761 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2762 /* ARM requires that S<->D conversion of any kind of NaN generates
2763 * a quiet NaN by forcing the most significant frac bit to 1.
2764 */
2765 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2766}
2767
2768/* VFP3 fixed point conversion. */
622465e1 2769#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2770float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2771 void *fpstp) \
4373f3ce 2772{ \
5500b06c 2773 float_status *fpst = fpstp; \
622465e1 2774 float##fsz tmp; \
5500b06c
PM		 2775 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2776 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2777} \
5500b06c
PM		 2778uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2779 void *fpstp) \
4373f3ce 2780{ \
5500b06c 2781 float_status *fpst = fpstp; \
622465e1
PM		 2782 float##fsz tmp; \
2783 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2784 float_raise(float_flag_invalid, fpst); \
622465e1 2785 return 0; \
09d9487f 2786 } \
5500b06c
PM		 2787 tmp = float##fsz##_scalbn(x, shift, fpst); \
2788 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2789}
2790
2791VFP_CONV_FIX(sh, d, 64, int16, )
2792VFP_CONV_FIX(sl, d, 64, int32, )
2793VFP_CONV_FIX(uh, d, 64, uint16, u)
2794VFP_CONV_FIX(ul, d, 64, uint32, u)
2795VFP_CONV_FIX(sh, s, 32, int16, )
2796VFP_CONV_FIX(sl, s, 32, int32, )
2797VFP_CONV_FIX(uh, s, 32, uint16, u)
2798VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2799#undef VFP_CONV_FIX
2800
60011498 2801/* Half precision conversions. */
0ecb72a5 2802static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 2803{
60011498 2804 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2805 float32 r = float16_to_float32(make_float16(a), ieee, s);
2806 if (ieee) {
2807 return float32_maybe_silence_nan(r);
2808 }
2809 return r;
60011498
PB		 2810}
2811
0ecb72a5 2812static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 2813{
60011498 2814 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2815 float16 r = float32_to_float16(a, ieee, s);
2816 if (ieee) {
2817 r = float16_maybe_silence_nan(r);
2818 }
2819 return float16_val(r);
60011498
PB		 2820}
2821
0ecb72a5 2822float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2823{
2824 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2825}
2826
0ecb72a5 2827uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2828{
2829 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2830}
2831
0ecb72a5 2832float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2833{
2834 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2835}
2836
0ecb72a5 2837uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2838{
2839 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2840}
2841
dda3ec49 2842#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2843#define float32_three make_float32(0x40400000)
2844#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2845
0ecb72a5 2846float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2847{
dda3ec49
PM		 2848 float_status *s = &env->vfp.standard_fp_status;
2849 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2850 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2851 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2852 float_raise(float_flag_input_denormal, s);
2853 }
dda3ec49
PM		 2854 return float32_two;
2855 }
2856 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2857}
2858
0ecb72a5 2859float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2860{
71826966 2861 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2862 float32 product;
2863 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2864 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2865 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2866 float_raise(float_flag_input_denormal, s);
2867 }
6aae3df1 2868 return float32_one_point_five;
9ea62f57 2869 }
6aae3df1
PM		 2870 product = float32_mul(a, b, s);
2871 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2872}
2873
8f8e3aa4
PB		 2874/* NEON helpers. */
2875
56bf4fe2
CL		 2876/* Constants 256 and 512 are used in some helpers; we avoid relying on
2877 * int->float conversions at run-time. */
2878#define float64_256 make_float64(0x4070000000000000LL)
2879#define float64_512 make_float64(0x4080000000000000LL)
2880
fe0e4872
CL		 2881/* The algorithm that must be used to calculate the estimate
2882 * is specified by the ARM ARM.
2883 */
0ecb72a5 2884static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 2885{
1146a817
PM		 2886 /* These calculations mustn't set any fp exception flags,
2887 * so we use a local copy of the fp_status.
2888 */
2889 float_status dummy_status = env->vfp.standard_fp_status;
2890 float_status *s = &dummy_status;
fe0e4872
CL		 2891 /* q = (int)(a * 512.0) */
2892 float64 q = float64_mul(float64_512, a, s);
2893 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2894
2895 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2896 q = int64_to_float64(q_int, s);
2897 q = float64_add(q, float64_half, s);
2898 q = float64_div(q, float64_512, s);
2899 q = float64_div(float64_one, q, s);
2900
2901 /* s = (int)(256.0 * r + 0.5) */
2902 q = float64_mul(q, float64_256, s);
2903 q = float64_add(q, float64_half, s);
2904 q_int = float64_to_int64_round_to_zero(q, s);
2905
2906 /* return (double)s / 256.0 */
2907 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2908}
2909
0ecb72a5 2910float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 2911{
fe0e4872
CL		 2912 float_status *s = &env->vfp.standard_fp_status;
2913 float64 f64;
2914 uint32_t val32 = float32_val(a);
2915
2916 int result_exp;
2917 int a_exp = (val32 & 0x7f800000) >> 23;
2918 int sign = val32 & 0x80000000;
2919
2920 if (float32_is_any_nan(a)) {
2921 if (float32_is_signaling_nan(a)) {
2922 float_raise(float_flag_invalid, s);
2923 }
2924 return float32_default_nan;
2925 } else if (float32_is_infinity(a)) {
2926 return float32_set_sign(float32_zero, float32_is_neg(a));
2927 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2928 if (!float32_is_zero(a)) {
2929 float_raise(float_flag_input_denormal, s);
2930 }
fe0e4872
CL		 2931 float_raise(float_flag_divbyzero, s);
2932 return float32_set_sign(float32_infinity, float32_is_neg(a));
2933 } else if (a_exp >= 253) {
2934 float_raise(float_flag_underflow, s);
2935 return float32_set_sign(float32_zero, float32_is_neg(a));
2936 }
2937
2938 f64 = make_float64((0x3feULL << 52)
2939 | ((int64_t)(val32 & 0x7fffff) << 29));
2940
2941 result_exp = 253 - a_exp;
2942
2943 f64 = recip_estimate(f64, env);
2944
2945 val32 = sign
2946 | ((result_exp & 0xff) << 23)
2947 | ((float64_val(f64) >> 29) & 0x7fffff);
2948 return make_float32(val32);
4373f3ce
PB		 2949}
2950
e07be5d2
CL		 2951/* The algorithm that must be used to calculate the estimate
2952 * is specified by the ARM ARM.
2953 */
0ecb72a5 2954static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 2955{
1146a817
PM		 2956 /* These calculations mustn't set any fp exception flags,
2957 * so we use a local copy of the fp_status.
2958 */
2959 float_status dummy_status = env->vfp.standard_fp_status;
2960 float_status *s = &dummy_status;
e07be5d2
CL		 2961 float64 q;
2962 int64_t q_int;
2963
2964 if (float64_lt(a, float64_half, s)) {
2965 /* range 0.25 <= a < 0.5 */
2966
2967 /* a in units of 1/512 rounded down */
2968 /* q0 = (int)(a * 512.0); */
2969 q = float64_mul(float64_512, a, s);
2970 q_int = float64_to_int64_round_to_zero(q, s);
2971
2972 /* reciprocal root r */
2973 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2974 q = int64_to_float64(q_int, s);
2975 q = float64_add(q, float64_half, s);
2976 q = float64_div(q, float64_512, s);
2977 q = float64_sqrt(q, s);
2978 q = float64_div(float64_one, q, s);
2979 } else {
2980 /* range 0.5 <= a < 1.0 */
2981
2982 /* a in units of 1/256 rounded down */
2983 /* q1 = (int)(a * 256.0); */
2984 q = float64_mul(float64_256, a, s);
2985 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2986
2987 /* reciprocal root r */
2988 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2989 q = int64_to_float64(q_int, s);
2990 q = float64_add(q, float64_half, s);
2991 q = float64_div(q, float64_256, s);
2992 q = float64_sqrt(q, s);
2993 q = float64_div(float64_one, q, s);
2994 }
2995 /* r in units of 1/256 rounded to nearest */
2996 /* s = (int)(256.0 * r + 0.5); */
2997
2998 q = float64_mul(q, float64_256,s );
2999 q = float64_add(q, float64_half, s);
3000 q_int = float64_to_int64_round_to_zero(q, s);
3001
3002 /* return (double)s / 256.0;*/
3003 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3004}
3005
0ecb72a5 3006float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3007{
e07be5d2
CL		 3008 float_status *s = &env->vfp.standard_fp_status;
3009 int result_exp;
3010 float64 f64;
3011 uint32_t val;
3012 uint64_t val64;
3013
3014 val = float32_val(a);
3015
3016 if (float32_is_any_nan(a)) {
3017 if (float32_is_signaling_nan(a)) {
3018 float_raise(float_flag_invalid, s);
3019 }
3020 return float32_default_nan;
3021 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3022 if (!float32_is_zero(a)) {
3023 float_raise(float_flag_input_denormal, s);
3024 }
e07be5d2
CL		 3025 float_raise(float_flag_divbyzero, s);
3026 return float32_set_sign(float32_infinity, float32_is_neg(a));
3027 } else if (float32_is_neg(a)) {
3028 float_raise(float_flag_invalid, s);
3029 return float32_default_nan;
3030 } else if (float32_is_infinity(a)) {
3031 return float32_zero;
3032 }
3033
3034 /* Normalize to a double-precision value between 0.25 and 1.0,
3035 * preserving the parity of the exponent. */
3036 if ((val & 0x800000) == 0) {
3037 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3038 | (0x3feULL << 52)
3039 | ((uint64_t)(val & 0x7fffff) << 29));
3040 } else {
3041 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3042 | (0x3fdULL << 52)
3043 | ((uint64_t)(val & 0x7fffff) << 29));
3044 }
3045
3046 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3047
3048 f64 = recip_sqrt_estimate(f64, env);
3049
3050 val64 = float64_val(f64);
3051
26cc6abf 3052 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3053 | ((val64 >> 29) & 0x7fffff);
3054 return make_float32(val);
4373f3ce
PB		 3055}
3056
0ecb72a5 3057uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3058{
fe0e4872
CL		 3059 float64 f64;
3060
3061 if ((a & 0x80000000) == 0) {
3062 return 0xffffffff;
3063 }
3064
3065 f64 = make_float64((0x3feULL << 52)
3066 | ((int64_t)(a & 0x7fffffff) << 21));
3067
3068 f64 = recip_estimate (f64, env);
3069
3070 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3071}
3072
0ecb72a5 3073uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3074{
e07be5d2
CL		 3075 float64 f64;
3076
3077 if ((a & 0xc0000000) == 0) {
3078 return 0xffffffff;
3079 }
3080
3081 if (a & 0x80000000) {
3082 f64 = make_float64((0x3feULL << 52)
3083 | ((uint64_t)(a & 0x7fffffff) << 21));
3084 } else { /* bits 31-30 == '01' */
3085 f64 = make_float64((0x3fdULL << 52)
3086 | ((uint64_t)(a & 0x3fffffff) << 22));
3087 }
3088
3089 f64 = recip_sqrt_estimate(f64, env);
3090
3091 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3092}
fe1479c3 3093
da97f52c
PM		 3094/* VFPv4 fused multiply-accumulate */
3095float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3096{
3097 float_status *fpst = fpstp;
3098 return float32_muladd(a, b, c, 0, fpst);
3099}
3100
3101float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3102{
3103 float_status *fpst = fpstp;
3104 return float64_muladd(a, b, c, 0, fpst);
3105}
Qemu copy for testing