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8bbf0f09 A |
1 | #/** @file\r |
2 | # ARM processor package.\r | |
3 | #\r | |
d6ebcab7 | 4 | # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r |
38a00bae | 5 | # Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.\r |
8bbf0f09 | 6 | #\r |
4059386c | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
8bbf0f09 A |
8 | #\r |
9 | #**/\r | |
10 | \r | |
2ef2b01e A |
11 | [Defines]\r |
12 | DEC_SPECIFICATION = 0x00010005\r | |
13 | PACKAGE_NAME = ArmPkg\r | |
14 | PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r | |
15 | PACKAGE_VERSION = 0.1\r | |
16 | \r | |
17 | ################################################################################\r | |
18 | #\r | |
19 | # Include Section - list of Include Paths that are provided by this package.\r | |
20 | # Comments are used for Keywords and Module Types.\r | |
21 | #\r | |
22 | # Supported Module Types:\r | |
23 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
24 | #\r | |
25 | ################################################################################\r | |
26 | [Includes.common]\r | |
27 | Include # Root include for the package\r | |
28 | \r | |
29 | [LibraryClasses.common]\r | |
8bbf0f09 | 30 | ArmLib|Include/Library/ArmLib.h\r |
12728e11 | 31 | ArmMmuLib|Include/Library/ArmMmuLib.h\r |
2ef2b01e | 32 | SemihostLib|Include/Library/Semihosting.h\r |
11c20f4e | 33 | DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r |
097bd461 | 34 | ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r |
8d13298b | 35 | ArmGicArchLib|Include/Library/ArmGicArchLib.h\r |
38a00bae | 36 | ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h\r |
4d163696 | 37 | ArmSvcLib|Include/Library/ArmSvcLib.h\r |
d65b78f1 | 38 | OpteeLib|Include/Library/OpteeLib.h\r |
eed947be | 39 | StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r |
c32aaba9 | 40 | \r |
2ef2b01e A |
41 | [Guids.common]\r |
42 | gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r | |
43 | \r | |
44788bae | 44 | ## ARM MPCore table\r |
45 | # Include/Guid/ArmMpCoreInfo.h\r | |
46 | gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r | |
47 | \r | |
4f2494cf GP |
48 | [Protocols.common]\r |
49 | ## Arm System Control and Management Interface(SCMI) Base protocol\r | |
50 | ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r | |
51 | gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r | |
52 | \r | |
53 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r | |
54 | ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r | |
55 | gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r | |
559a07d8 | 56 | gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r |
4f2494cf GP |
57 | \r |
58 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r | |
59 | ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r | |
60 | gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r | |
61 | \r | |
44788bae | 62 | [Ppis]\r |
63 | ## Include/Ppi/ArmMpCoreInfo.h\r | |
64 | gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r | |
65 | \r | |
2ef2b01e A |
66 | [PcdsFeatureFlag.common]\r |
67 | gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r | |
68 | \r | |
1bfda055 | 69 | # On ARM Architecture with the Security Extension, the address for the\r |
70 | # Vector Table can be mapped anywhere in the memory map. It means we can\r | |
71 | # point the Exception Vector Table to its location in CpuDxe.\r | |
f0bbcdf8 | 72 | # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r |
1bfda055 | 73 | gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r |
eeec69c5 | 74 | # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r |
75 | # it has been configured by the CPU DXE\r | |
76 | gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r | |
c32aaba9 | 77 | \r |
f6d46e29 AB |
78 | # Define if the GICv3 controller should use the GICv2 legacy\r |
79 | gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r | |
80 | \r | |
65ceda91 AB |
81 | [PcdsFeatureFlag.ARM]\r |
82 | # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r | |
83 | # TRUE may be appropriate to fix performance problems if you don't care about\r | |
84 | # hardware coherency (i.e., no virtualization or cache coherent DMA)\r | |
85 | gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r | |
86 | \r | |
ee283e33 SG |
87 | [PcdsFeatureFlag.AARCH64]\r |
88 | ## Used to select method for requesting services from S-EL1.<BR><BR>\r | |
89 | # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>\r | |
90 | # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>\r | |
91 | # @Prompt Enable FF-A support.\r | |
92 | gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B\r | |
93 | \r | |
2ef2b01e | 94 | [PcdsFixedAtBuild.common]\r |
12c5ae23 | 95 | gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r |
96 | \r | |
1bfda055 | 97 | # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r |
98 | # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r | |
99 | gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r | |
100 | \r | |
f0bbcdf8 | 101 | gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r |
2ef2b01e | 102 | gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r |
c32aaba9 | 103 | \r |
1bfda055 | 104 | #\r |
262a9b04 | 105 | # ARM Secure Firmware PCDs\r |
1bfda055 | 106 | #\r |
bb5420bb | 107 | gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r |
1bfda055 | 108 | gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r |
bb5420bb | 109 | gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r |
1ad14bc8 | 110 | gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r |
1bfda055 | 111 | \r |
7245b435 | 112 | #\r |
113 | # ARM Hypervisor Firmware PCDs\r | |
c32aaba9 | 114 | #\r |
7245b435 | 115 | gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r |
116 | gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r | |
117 | gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r | |
118 | gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r | |
d6dc67ba | 119 | \r |
0787bc61 | 120 | # Use ClusterId + CoreId to identify the PrimaryCore\r |
121 | gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r | |
c32aaba9 | 122 | # The Primary Core is ClusterId[0] & CoreId[0]\r |
0787bc61 | 123 | gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r |
124 | \r | |
660d4faa RC |
125 | #\r |
126 | # SMBIOS PCDs\r | |
127 | #\r | |
128 | gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053\r | |
129 | gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054\r | |
130 | gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055\r | |
131 | gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056\r | |
132 | gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057\r | |
133 | gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071\r | |
134 | gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072\r | |
135 | gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073\r | |
136 | gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074\r | |
137 | gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075\r | |
138 | \r | |
1bfda055 | 139 | #\r |
140 | # ARM L2x0 PCDs\r | |
141 | #\r | |
142 | gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r | |
c32aaba9 | 143 | \r |
523b5266 AB |
144 | #\r |
145 | # ARM Normal (or Non Secure) Firmware PCDs\r | |
146 | #\r | |
147 | gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r | |
148 | gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r | |
149 | \r | |
bfe34275 AB |
150 | #\r |
151 | # Value to add to a host address to obtain a device address, using\r | |
152 | # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r | |
153 | # means we can rely on truncation on overflow to specify negative\r | |
154 | # offsets.\r | |
155 | #\r | |
156 | gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r | |
157 | \r | |
523b5266 AB |
158 | [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r |
159 | gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r | |
160 | gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r | |
387653a4 | 161 | \r |
162 | [PcdsFixedAtBuild.ARM]\r | |
cc935544 OM |
163 | #\r |
164 | # ARM Security Extension\r | |
165 | #\r | |
166 | \r | |
167 | # Secure Configuration Register\r | |
168 | # - BIT0 : NS - Non Secure bit\r | |
169 | # - BIT1 : IRQ Handler\r | |
170 | # - BIT2 : FIQ Handler\r | |
171 | # - BIT3 : EA - External Abort\r | |
172 | # - BIT4 : FW - F bit writable\r | |
173 | # - BIT5 : AW - A bit writable\r | |
174 | # - BIT6 : nET - Not Early Termination\r | |
175 | # - BIT7 : SCD - Secure Monitor Call Disable\r | |
176 | # - BIT8 : HCE - Hyp Call enable\r | |
177 | # - BIT9 : SIF - Secure Instruction Fetch\r | |
178 | # 0x31 = NS | EA | FW\r | |
179 | gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r | |
180 | \r | |
387653a4 | 181 | # By default we do not do a transition to non-secure mode\r |
182 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r | |
2425e1d4 | 183 | \r |
d6dc67ba OM |
184 | # Non Secure Access Control Register\r |
185 | # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r | |
186 | # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r | |
187 | # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r | |
188 | # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r | |
189 | # 0xC00 = cp10 | cp11\r | |
190 | gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r | |
191 | \r | |
25402f5d | 192 | [PcdsFixedAtBuild.AARCH64]\r |
cc935544 OM |
193 | #\r |
194 | # AArch64 Security Extension\r | |
195 | #\r | |
196 | \r | |
197 | # Secure Configuration Register\r | |
198 | # - BIT0 : NS - Non Secure bit\r | |
199 | # - BIT1 : IRQ Handler\r | |
200 | # - BIT2 : FIQ Handler\r | |
201 | # - BIT3 : EA - External Abort\r | |
202 | # - BIT4 : FW - F bit writable\r | |
203 | # - BIT5 : AW - A bit writable\r | |
204 | # - BIT6 : nET - Not Early Termination\r | |
205 | # - BIT7 : SCD - Secure Monitor Call Disable\r | |
206 | # - BIT8 : HCE - Hyp Call enable\r | |
207 | # - BIT9 : SIF - Secure Instruction Fetch\r | |
208 | # - BIT10: RW - Register width control for lower exception levels\r | |
209 | # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r | |
210 | # - BIT12: TWI - Trap WFI\r | |
211 | # - BIT13: TWE - Trap WFE\r | |
212 | # 0x501 = NS | HCE | RW\r | |
213 | gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r | |
214 | \r | |
25402f5d HL |
215 | # By default we do transition to EL2 non-secure mode with Stack for EL2.\r |
216 | # Mode Description Bits\r | |
c32aaba9 OM |
217 | # NS EL2 SP2 all interrupts disabled = 0x3c9\r |
218 | # NS EL1 SP1 all interrupts disabled = 0x3c5\r | |
25402f5d HL |
219 | # Other modes include using SP0 or switching to Aarch32, but these are\r |
220 | # not currently supported.\r | |
221 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r | |
e1e2e66c AB |
222 | \r |
223 | \r | |
dc63be24 | 224 | #\r |
523b5266 AB |
225 | # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r |
226 | # redefined when using UEFI in a context of virtual machine.\r | |
dc63be24 | 227 | #\r |
523b5266 AB |
228 | [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r |
229 | \r | |
f8d7d6e1 | 230 | # System Memory (DRAM): These PCDs define the region of in-built system memory\r |
142fa386 AB |
231 | # Some platforms can get DRAM extensions, these additional regions may be\r |
232 | # declared to UEFI using separate resource descriptor HOBs\r | |
f8d7d6e1 AB |
233 | gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r |
234 | gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r | |
235 | \r | |
767febf8 AG |
236 | gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r |
237 | gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r | |
238 | \r | |
660d4faa RC |
239 | gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058\r |
240 | gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059\r | |
241 | \r | |
523b5266 | 242 | [PcdsFixedAtBuild.common, PcdsDynamic.common]\r |
e1e2e66c AB |
243 | #\r |
244 | # ARM Architectural Timer\r | |
245 | #\r | |
246 | gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r | |
247 | \r | |
248 | # ARM Architectural Timer Interrupt(GIC PPI) numbers\r | |
249 | gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r | |
250 | gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r | |
251 | gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r | |
252 | gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r | |
dc63be24 | 253 | \r |
0b4d97a0 RC |
254 | #\r |
255 | # ARM Generic Watchdog\r | |
256 | #\r | |
257 | \r | |
7c609a14 A |
258 | gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r |
259 | gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r | |
0b4d97a0 RC |
260 | gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r |
261 | \r | |
dc63be24 AB |
262 | #\r |
263 | # ARM Generic Interrupt Controller\r | |
264 | #\r | |
8a1f2378 | 265 | gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r |
919697ae | 266 | # Base address for the GIC Redistributor region that contains the boot CPU\r |
8a1f2378 DC |
267 | gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r |
268 | gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r | |
dc63be24 | 269 | gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r |
d7c06eb0 AB |
270 | \r |
271 | #\r | |
272 | # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r | |
273 | # Note that "IO" is just another MMIO range that simulates IO space; there\r | |
274 | # are no special instructions to access it.\r | |
275 | #\r | |
276 | # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r | |
277 | # specific to their containing address spaces. In order to get the physical\r | |
278 | # address for the CPU, for a given access, the respective translation value\r | |
279 | # has to be added.\r | |
280 | #\r | |
281 | # The translations always have to be initialized like this, using UINT64:\r | |
282 | #\r | |
283 | # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r | |
284 | # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r | |
285 | # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r | |
286 | #\r | |
287 | # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r | |
288 | # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r | |
289 | # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r | |
290 | #\r | |
291 | # because (a) the target address space (ie. the cpu-physical space) is\r | |
292 | # 64-bit, and (b) the translation values are meant as offsets for *modular*\r | |
293 | # arithmetic.\r | |
294 | #\r | |
295 | # Accordingly, the translation itself needs to be implemented as:\r | |
296 | #\r | |
297 | # UINT64 UntranslatedIoAddress; // input parameter\r | |
298 | # UINT32 UntranslatedMmio32Address; // input parameter\r | |
299 | # UINT64 UntranslatedMmio64Address; // input parameter\r | |
300 | #\r | |
301 | # UINT64 TranslatedIoAddress; // output parameter\r | |
302 | # UINT64 TranslatedMmio32Address; // output parameter\r | |
303 | # UINT64 TranslatedMmio64Address; // output parameter\r | |
304 | #\r | |
305 | # TranslatedIoAddress = UntranslatedIoAddress +\r | |
306 | # PcdPciIoTranslation;\r | |
307 | # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r | |
308 | # PcdPciMmio32Translation;\r | |
309 | # TranslatedMmio64Address = UntranslatedMmio64Address +\r | |
310 | # PcdPciMmio64Translation;\r | |
311 | #\r | |
312 | # The modular arithmetic performed in UINT64 ensures that the translation\r | |
313 | # works correctly regardless of the relation between IoCpuBase and\r | |
314 | # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r | |
315 | # PcdPciMmio64Base.\r | |
316 | #\r | |
317 | gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r | |
318 | gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r | |
319 | gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r | |
320 | gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r | |
321 | gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r | |
322 | gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r | |
323 | gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r | |
324 | gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r | |
325 | gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r | |
326 | \r | |
327 | #\r | |
328 | # Inclusive range of allowed PCI buses.\r | |
329 | #\r | |
330 | gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r | |
331 | gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r |