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eb290d02 FT |
1 | /** @file\r |
2 | NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r | |
3 | NVM Express specification.\r | |
4 | \r | |
35f910f0 | 5 | (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>\r |
5f5bba14 | 6 | Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>\r |
eb290d02 FT |
7 | This program and the accompanying materials\r |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php.\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include "NvmExpress.h"\r | |
18 | \r | |
eb290d02 FT |
19 | /**\r |
20 | Dump the execution status from a given completion queue entry.\r | |
21 | \r | |
22 | @param[in] Cq A pointer to the NVME_CQ item.\r | |
23 | \r | |
24 | **/\r | |
25 | VOID\r | |
26 | NvmeDumpStatus (\r | |
27 | IN NVME_CQ *Cq\r | |
28 | )\r | |
29 | {\r | |
30 | DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));\r | |
31 | \r | |
32 | DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));\r | |
33 | \r | |
34 | DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));\r | |
35 | \r | |
36 | switch (Cq->Sct) {\r | |
37 | case 0x0:\r | |
38 | switch (Cq->Sc) {\r | |
39 | case 0x0:\r | |
40 | DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));\r | |
41 | break;\r | |
42 | case 0x1:\r | |
43 | DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));\r | |
44 | break;\r | |
45 | case 0x2:\r | |
46 | DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));\r | |
47 | break;\r | |
48 | case 0x3:\r | |
49 | DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));\r | |
50 | break;\r | |
51 | case 0x4:\r | |
52 | DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));\r | |
53 | break;\r | |
54 | case 0x5:\r | |
55 | DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));\r | |
56 | break;\r | |
57 | case 0x6:\r | |
58 | DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));\r | |
59 | break;\r | |
60 | case 0x7:\r | |
61 | DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));\r | |
62 | break;\r | |
63 | case 0x8:\r | |
64 | DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));\r | |
65 | break;\r | |
66 | case 0x9:\r | |
67 | DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));\r | |
68 | break;\r | |
69 | case 0xA:\r | |
70 | DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));\r | |
71 | break;\r | |
72 | case 0xB:\r | |
73 | DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));\r | |
74 | break;\r | |
75 | case 0xC:\r | |
76 | DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));\r | |
77 | break;\r | |
78 | case 0xD:\r | |
79 | DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));\r | |
80 | break;\r | |
81 | case 0xE:\r | |
82 | DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));\r | |
83 | break;\r | |
84 | case 0xF:\r | |
85 | DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));\r | |
86 | break;\r | |
87 | case 0x10:\r | |
88 | DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));\r | |
89 | break;\r | |
90 | case 0x11:\r | |
91 | DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));\r | |
92 | break;\r | |
93 | case 0x80:\r | |
94 | DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));\r | |
95 | break;\r | |
96 | case 0x81:\r | |
97 | DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));\r | |
98 | break;\r | |
99 | case 0x82:\r | |
100 | DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));\r | |
101 | break;\r | |
102 | case 0x83:\r | |
103 | DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));\r | |
104 | break;\r | |
105 | }\r | |
106 | break;\r | |
107 | \r | |
108 | case 0x1:\r | |
109 | switch (Cq->Sc) {\r | |
110 | case 0x0:\r | |
111 | DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));\r | |
112 | break;\r | |
113 | case 0x1:\r | |
114 | DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));\r | |
115 | break;\r | |
116 | case 0x2:\r | |
117 | DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));\r | |
118 | break;\r | |
119 | case 0x3:\r | |
120 | DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));\r | |
121 | break;\r | |
122 | case 0x5:\r | |
123 | DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));\r | |
124 | break;\r | |
125 | case 0x6:\r | |
126 | DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));\r | |
127 | break;\r | |
128 | case 0x7:\r | |
129 | DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));\r | |
130 | break;\r | |
131 | case 0x8:\r | |
132 | DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));\r | |
133 | break;\r | |
134 | case 0x9:\r | |
135 | DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));\r | |
136 | break;\r | |
137 | case 0xA:\r | |
138 | DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));\r | |
139 | break;\r | |
140 | case 0xB:\r | |
141 | DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));\r | |
142 | break;\r | |
143 | case 0xC:\r | |
144 | DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));\r | |
145 | break;\r | |
146 | case 0xD:\r | |
147 | DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));\r | |
148 | break;\r | |
149 | case 0xE:\r | |
150 | DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));\r | |
151 | break;\r | |
152 | case 0xF:\r | |
153 | DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));\r | |
154 | break;\r | |
155 | case 0x10:\r | |
156 | DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));\r | |
157 | break;\r | |
158 | case 0x80:\r | |
159 | DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));\r | |
160 | break;\r | |
161 | case 0x81:\r | |
162 | DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));\r | |
163 | break;\r | |
164 | case 0x82:\r | |
165 | DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));\r | |
166 | break;\r | |
167 | }\r | |
168 | break;\r | |
169 | \r | |
170 | case 0x2:\r | |
171 | switch (Cq->Sc) {\r | |
172 | case 0x80:\r | |
173 | DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));\r | |
174 | break;\r | |
175 | case 0x81:\r | |
176 | DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));\r | |
177 | break;\r | |
178 | case 0x82:\r | |
179 | DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));\r | |
180 | break;\r | |
181 | case 0x83:\r | |
182 | DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));\r | |
183 | break;\r | |
184 | case 0x84:\r | |
185 | DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));\r | |
186 | break;\r | |
187 | case 0x85:\r | |
188 | DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));\r | |
189 | break;\r | |
190 | case 0x86:\r | |
191 | DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));\r | |
192 | break;\r | |
193 | }\r | |
194 | break;\r | |
195 | \r | |
196 | default:\r | |
197 | break;\r | |
198 | }\r | |
199 | }\r | |
200 | \r | |
201 | /**\r | |
202 | Create PRP lists for data transfer which is larger than 2 memory pages.\r | |
203 | Note here we calcuate the number of required PRP lists and allocate them at one time.\r | |
204 | \r | |
205 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
206 | @param[in] PhysicalAddr The physical base address of data buffer.\r | |
207 | @param[in] Pages The number of pages to be transfered.\r | |
208 | @param[out] PrpListHost The host base address of PRP lists.\r | |
209 | @param[in,out] PrpListNo The number of PRP List.\r | |
210 | @param[out] Mapping The mapping value returned from PciIo.Map().\r | |
211 | \r | |
212 | @retval The pointer to the first PRP List of the PRP lists.\r | |
213 | \r | |
214 | **/\r | |
215 | VOID*\r | |
216 | NvmeCreatePrpList (\r | |
217 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
218 | IN EFI_PHYSICAL_ADDRESS PhysicalAddr,\r | |
219 | IN UINTN Pages,\r | |
220 | OUT VOID **PrpListHost,\r | |
221 | IN OUT UINTN *PrpListNo,\r | |
222 | OUT VOID **Mapping\r | |
223 | )\r | |
224 | {\r | |
225 | UINTN PrpEntryNo;\r | |
226 | UINT64 PrpListBase;\r | |
227 | UINTN PrpListIndex;\r | |
228 | UINTN PrpEntryIndex;\r | |
229 | UINT64 Remainder;\r | |
230 | EFI_PHYSICAL_ADDRESS PrpListPhyAddr;\r | |
231 | UINTN Bytes;\r | |
232 | EFI_STATUS Status;\r | |
233 | \r | |
234 | //\r | |
235 | // The number of Prp Entry in a memory page.\r | |
236 | //\r | |
237 | PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);\r | |
238 | \r | |
239 | //\r | |
240 | // Calculate total PrpList number.\r | |
241 | //\r | |
769402ef FT |
242 | *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);\r |
243 | if (*PrpListNo == 0) {\r | |
244 | *PrpListNo = 1;\r | |
a9ec6d65 | 245 | } else if ((Remainder != 0) && (Remainder != 1)) {\r |
eb290d02 | 246 | *PrpListNo += 1;\r |
769402ef FT |
247 | } else if (Remainder == 1) {\r |
248 | Remainder = PrpEntryNo;\r | |
249 | } else if (Remainder == 0) {\r | |
250 | Remainder = PrpEntryNo - 1;\r | |
eb290d02 FT |
251 | }\r |
252 | \r | |
253 | Status = PciIo->AllocateBuffer (\r | |
254 | PciIo,\r | |
255 | AllocateAnyPages,\r | |
256 | EfiBootServicesData,\r | |
257 | *PrpListNo,\r | |
258 | PrpListHost,\r | |
259 | 0\r | |
260 | );\r | |
261 | \r | |
262 | if (EFI_ERROR (Status)) {\r | |
263 | return NULL;\r | |
264 | }\r | |
265 | \r | |
266 | Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);\r | |
267 | Status = PciIo->Map (\r | |
268 | PciIo,\r | |
269 | EfiPciIoOperationBusMasterCommonBuffer,\r | |
270 | *PrpListHost,\r | |
271 | &Bytes,\r | |
272 | &PrpListPhyAddr,\r | |
273 | Mapping\r | |
274 | );\r | |
275 | \r | |
276 | if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {\r | |
277 | DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));\r | |
278 | goto EXIT;\r | |
279 | }\r | |
280 | //\r | |
281 | // Fill all PRP lists except of last one.\r | |
282 | //\r | |
283 | ZeroMem (*PrpListHost, Bytes);\r | |
284 | for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {\r | |
769402ef | 285 | PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r |
eb290d02 FT |
286 | \r |
287 | for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {\r | |
288 | if (PrpEntryIndex != PrpEntryNo - 1) {\r | |
289 | //\r | |
290 | // Fill all PRP entries except of last one.\r | |
291 | //\r | |
292 | *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r | |
293 | PhysicalAddr += EFI_PAGE_SIZE;\r | |
294 | } else {\r | |
295 | //\r | |
296 | // Fill last PRP entries with next PRP List pointer.\r | |
297 | //\r | |
298 | *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;\r | |
299 | }\r | |
300 | }\r | |
301 | }\r | |
302 | //\r | |
303 | // Fill last PRP list.\r | |
304 | //\r | |
305 | PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r | |
769402ef | 306 | for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {\r |
eb290d02 FT |
307 | *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r |
308 | PhysicalAddr += EFI_PAGE_SIZE;\r | |
309 | }\r | |
310 | \r | |
311 | return (VOID*)(UINTN)PrpListPhyAddr;\r | |
312 | \r | |
313 | EXIT:\r | |
314 | PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);\r | |
315 | return NULL;\r | |
316 | }\r | |
317 | \r | |
318 | \r | |
5f5bba14 HW |
319 | /**\r |
320 | Aborts the asynchronous PassThru requests.\r | |
321 | \r | |
322 | @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA\r | |
323 | data structure.\r | |
324 | \r | |
325 | @retval EFI_SUCCESS The asynchronous PassThru requests have been aborted.\r | |
326 | @return EFI_DEVICE_ERROR Fail to abort all the asynchronous PassThru requests.\r | |
327 | \r | |
328 | **/\r | |
329 | EFI_STATUS\r | |
330 | AbortAsyncPassThruTasks (\r | |
331 | IN NVME_CONTROLLER_PRIVATE_DATA *Private\r | |
332 | )\r | |
333 | {\r | |
334 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
335 | LIST_ENTRY *Link;\r | |
336 | LIST_ENTRY *NextLink;\r | |
337 | NVME_BLKIO2_SUBTASK *Subtask;\r | |
338 | NVME_BLKIO2_REQUEST *BlkIo2Request;\r | |
339 | NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;\r | |
340 | EFI_BLOCK_IO2_TOKEN *Token;\r | |
341 | EFI_TPL OldTpl;\r | |
342 | EFI_STATUS Status;\r | |
343 | \r | |
344 | PciIo = Private->PciIo;\r | |
345 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r | |
346 | \r | |
347 | //\r | |
348 | // Cancel the unsubmitted subtasks.\r | |
349 | //\r | |
350 | for (Link = GetFirstNode (&Private->UnsubmittedSubtasks);\r | |
351 | !IsNull (&Private->UnsubmittedSubtasks, Link);\r | |
352 | Link = NextLink) {\r | |
353 | NextLink = GetNextNode (&Private->UnsubmittedSubtasks, Link);\r | |
354 | Subtask = NVME_BLKIO2_SUBTASK_FROM_LINK (Link);\r | |
355 | BlkIo2Request = Subtask->BlockIo2Request;\r | |
356 | Token = BlkIo2Request->Token;\r | |
357 | \r | |
358 | BlkIo2Request->UnsubmittedSubtaskNum--;\r | |
359 | if (Subtask->IsLast) {\r | |
360 | BlkIo2Request->LastSubtaskSubmitted = TRUE;\r | |
361 | }\r | |
362 | Token->TransactionStatus = EFI_ABORTED;\r | |
363 | \r | |
364 | RemoveEntryList (Link);\r | |
365 | InsertTailList (&BlkIo2Request->SubtasksQueue, Link);\r | |
366 | gBS->SignalEvent (Subtask->Event);\r | |
367 | }\r | |
368 | \r | |
369 | //\r | |
370 | // Cleanup the resources for the asynchronous PassThru requests.\r | |
371 | //\r | |
372 | for (Link = GetFirstNode (&Private->AsyncPassThruQueue);\r | |
373 | !IsNull (&Private->AsyncPassThruQueue, Link);\r | |
374 | Link = NextLink) {\r | |
375 | NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);\r | |
376 | AsyncRequest = NVME_PASS_THRU_ASYNC_REQ_FROM_THIS (Link);\r | |
377 | \r | |
378 | if (AsyncRequest->MapData != NULL) {\r | |
379 | PciIo->Unmap (PciIo, AsyncRequest->MapData);\r | |
380 | }\r | |
381 | if (AsyncRequest->MapMeta != NULL) {\r | |
382 | PciIo->Unmap (PciIo, AsyncRequest->MapMeta);\r | |
383 | }\r | |
384 | if (AsyncRequest->MapPrpList != NULL) {\r | |
385 | PciIo->Unmap (PciIo, AsyncRequest->MapPrpList);\r | |
386 | }\r | |
387 | if (AsyncRequest->PrpListHost != NULL) {\r | |
388 | PciIo->FreeBuffer (\r | |
389 | PciIo,\r | |
390 | AsyncRequest->PrpListNo,\r | |
391 | AsyncRequest->PrpListHost\r | |
392 | );\r | |
393 | }\r | |
394 | \r | |
395 | RemoveEntryList (Link);\r | |
396 | gBS->SignalEvent (AsyncRequest->CallerEvent);\r | |
397 | FreePool (AsyncRequest);\r | |
398 | }\r | |
399 | \r | |
400 | if (IsListEmpty (&Private->AsyncPassThruQueue) &&\r | |
401 | IsListEmpty (&Private->UnsubmittedSubtasks)) {\r | |
402 | Status = EFI_SUCCESS;\r | |
403 | } else {\r | |
404 | Status = EFI_DEVICE_ERROR;\r | |
405 | }\r | |
406 | \r | |
407 | gBS->RestoreTPL (OldTpl);\r | |
408 | \r | |
409 | return Status;\r | |
410 | }\r | |
411 | \r | |
412 | \r | |
eb290d02 FT |
413 | /**\r |
414 | Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r | |
d6c55989 | 415 | both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking\r |
eb290d02 FT |
416 | I/O functionality is optional.\r |
417 | \r | |
d6c55989 FT |
418 | \r |
419 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r | |
420 | @param[in] NamespaceId A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command\r | |
421 | Packet will be sent. A value of 0 denotes the NVM Express controller, a value of all 0xFF's\r | |
422 | (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to\r | |
423 | all valid namespaces.\r | |
424 | @param[in,out] Packet A pointer to the NVM Express Command Packet.\r | |
425 | @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.\r | |
426 | If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O\r | |
427 | is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM\r | |
eb290d02 FT |
428 | Express Command Packet completes.\r |
429 | \r | |
430 | @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r | |
431 | to, or from DataBuffer.\r | |
432 | @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred\r | |
433 | is returned in TransferLength.\r | |
434 | @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r | |
435 | may retry again later.\r | |
436 | @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.\r | |
d6c55989 | 437 | @retval EFI_INVALID_PARAMETER NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r |
eb290d02 | 438 | Express Command Packet was not sent, so no additional status information is available.\r |
d6c55989 FT |
439 | @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the NVM Express\r |
440 | controller. The NVM Express Command Packet was not sent so no additional status information\r | |
441 | is available.\r | |
eb290d02 FT |
442 | @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.\r |
443 | \r | |
444 | **/\r | |
445 | EFI_STATUS\r | |
446 | EFIAPI\r | |
447 | NvmExpressPassThru (\r | |
d6c55989 | 448 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
eb290d02 | 449 | IN UINT32 NamespaceId,\r |
d6c55989 | 450 | IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,\r |
eb290d02 FT |
451 | IN EFI_EVENT Event OPTIONAL\r |
452 | )\r | |
453 | {\r | |
3c52deaf HW |
454 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r |
455 | EFI_STATUS Status;\r | |
456 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
457 | NVME_SQ *Sq;\r | |
458 | NVME_CQ *Cq;\r | |
459 | UINT16 QueueId;\r | |
460 | UINT32 Bytes;\r | |
461 | UINT16 Offset;\r | |
462 | EFI_EVENT TimerEvent;\r | |
463 | EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r | |
464 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
465 | VOID *MapData;\r | |
466 | VOID *MapMeta;\r | |
467 | VOID *MapPrpList;\r | |
468 | UINTN MapLength;\r | |
469 | UINT64 *Prp;\r | |
470 | VOID *PrpListHost;\r | |
471 | UINTN PrpListNo;\r | |
491f6026 | 472 | UINT32 Attributes;\r |
3c52deaf | 473 | UINT32 IoAlign;\r |
b7f82a3a | 474 | UINT32 MaxTransLen;\r |
3c52deaf HW |
475 | UINT32 Data;\r |
476 | NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;\r | |
477 | EFI_TPL OldTpl;\r | |
eb290d02 FT |
478 | \r |
479 | //\r | |
480 | // check the data fields in Packet parameter.\r | |
481 | //\r | |
482 | if ((This == NULL) || (Packet == NULL)) {\r | |
483 | return EFI_INVALID_PARAMETER;\r | |
484 | }\r | |
485 | \r | |
d6c55989 | 486 | if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {\r |
eb290d02 FT |
487 | return EFI_INVALID_PARAMETER;\r |
488 | }\r | |
489 | \r | |
d6c55989 | 490 | if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {\r |
eb290d02 FT |
491 | return EFI_INVALID_PARAMETER;\r |
492 | }\r | |
493 | \r | |
491f6026 HW |
494 | //\r |
495 | // 'Attributes' with neither EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL nor\r | |
496 | // EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal\r | |
497 | // configuration.\r | |
498 | //\r | |
499 | Attributes = This->Mode->Attributes;\r | |
500 | if ((Attributes & (EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |\r | |
501 | EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0) {\r | |
502 | return EFI_INVALID_PARAMETER;\r | |
503 | }\r | |
504 | \r | |
3c52deaf HW |
505 | //\r |
506 | // Buffer alignment check for TransferBuffer & MetadataBuffer.\r | |
507 | //\r | |
491f6026 | 508 | IoAlign = This->Mode->IoAlign;\r |
3c52deaf HW |
509 | if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {\r |
510 | return EFI_INVALID_PARAMETER;\r | |
511 | }\r | |
512 | \r | |
513 | if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {\r | |
514 | return EFI_INVALID_PARAMETER;\r | |
515 | }\r | |
516 | \r | |
eb290d02 | 517 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r |
b7f82a3a HW |
518 | \r |
519 | //\r | |
80b405a6 HW |
520 | // Check NamespaceId is valid or not.\r |
521 | //\r | |
522 | if ((NamespaceId > Private->ControllerData->Nn) &&\r | |
523 | (NamespaceId != (UINT32) -1)) {\r | |
524 | return EFI_INVALID_PARAMETER;\r | |
525 | }\r | |
526 | \r | |
527 | //\r | |
b7f82a3a HW |
528 | // Check whether TransferLength exceeds the maximum data transfer size.\r |
529 | //\r | |
530 | if (Private->ControllerData->Mdts != 0) {\r | |
531 | MaxTransLen = (1 << (Private->ControllerData->Mdts)) *\r | |
532 | (1 << (Private->Cap.Mpsmin + 12));\r | |
533 | if (Packet->TransferLength > MaxTransLen) {\r | |
534 | Packet->TransferLength = MaxTransLen;\r | |
535 | return EFI_BAD_BUFFER_SIZE;\r | |
536 | }\r | |
537 | }\r | |
538 | \r | |
eb290d02 FT |
539 | PciIo = Private->PciIo;\r |
540 | MapData = NULL;\r | |
541 | MapMeta = NULL;\r | |
542 | MapPrpList = NULL;\r | |
543 | PrpListHost = NULL;\r | |
544 | PrpListNo = 0;\r | |
545 | Prp = NULL;\r | |
546 | TimerEvent = NULL;\r | |
547 | Status = EFI_SUCCESS;\r | |
548 | \r | |
758ea946 HW |
549 | if (Packet->QueueType == NVME_ADMIN_QUEUE) {\r |
550 | QueueId = 0;\r | |
551 | } else {\r | |
552 | if (Event == NULL) {\r | |
553 | QueueId = 1;\r | |
554 | } else {\r | |
555 | QueueId = 2;\r | |
556 | \r | |
557 | //\r | |
558 | // Submission queue full check.\r | |
559 | //\r | |
560 | if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==\r | |
561 | Private->AsyncSqHead) {\r | |
562 | return EFI_NOT_READY;\r | |
563 | }\r | |
564 | }\r | |
565 | }\r | |
566 | Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;\r | |
567 | Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;\r | |
eb290d02 FT |
568 | \r |
569 | if (Packet->NvmeCmd->Nsid != NamespaceId) {\r | |
570 | return EFI_INVALID_PARAMETER;\r | |
571 | }\r | |
572 | \r | |
573 | ZeroMem (Sq, sizeof (NVME_SQ));\r | |
d6c55989 FT |
574 | Sq->Opc = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;\r |
575 | Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;\r | |
758ea946 | 576 | Sq->Cid = Private->Cid[QueueId]++;\r |
eb290d02 FT |
577 | Sq->Nsid = Packet->NvmeCmd->Nsid;\r |
578 | \r | |
579 | //\r | |
580 | // Currently we only support PRP for data transfer, SGL is NOT supported.\r | |
581 | //\r | |
7b8883c6 FT |
582 | ASSERT (Sq->Psdt == 0);\r |
583 | if (Sq->Psdt != 0) {\r | |
eb290d02 FT |
584 | DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));\r |
585 | return EFI_UNSUPPORTED;\r | |
586 | }\r | |
587 | \r | |
588 | Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;\r | |
589 | //\r | |
590 | // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.\r | |
591 | // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because\r | |
592 | // these two cmds are special which requires their data buffer must support simultaneous access by both the\r | |
593 | // processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r | |
594 | //\r | |
754b489b | 595 | if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {\r |
b7f82a3a HW |
596 | if ((Packet->TransferLength == 0) || (Packet->TransferBuffer == NULL)) {\r |
597 | return EFI_INVALID_PARAMETER;\r | |
598 | }\r | |
599 | \r | |
eb290d02 FT |
600 | if ((Sq->Opc & BIT0) != 0) {\r |
601 | Flag = EfiPciIoOperationBusMasterRead;\r | |
602 | } else {\r | |
603 | Flag = EfiPciIoOperationBusMasterWrite;\r | |
604 | }\r | |
605 | \r | |
606 | MapLength = Packet->TransferLength;\r | |
607 | Status = PciIo->Map (\r | |
608 | PciIo,\r | |
609 | Flag,\r | |
610 | Packet->TransferBuffer,\r | |
611 | &MapLength,\r | |
612 | &PhyAddr,\r | |
613 | &MapData\r | |
614 | );\r | |
615 | if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {\r | |
616 | return EFI_OUT_OF_RESOURCES;\r | |
617 | }\r | |
618 | \r | |
619 | Sq->Prp[0] = PhyAddr;\r | |
620 | Sq->Prp[1] = 0;\r | |
621 | \r | |
b7f82a3a | 622 | if((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {\r |
eb290d02 FT |
623 | MapLength = Packet->MetadataLength;\r |
624 | Status = PciIo->Map (\r | |
625 | PciIo,\r | |
626 | Flag,\r | |
627 | Packet->MetadataBuffer,\r | |
628 | &MapLength,\r | |
629 | &PhyAddr,\r | |
630 | &MapMeta\r | |
631 | );\r | |
632 | if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {\r | |
633 | PciIo->Unmap (\r | |
634 | PciIo,\r | |
635 | MapData\r | |
636 | );\r | |
637 | \r | |
638 | return EFI_OUT_OF_RESOURCES;\r | |
639 | }\r | |
640 | Sq->Mptr = PhyAddr;\r | |
641 | }\r | |
642 | }\r | |
643 | //\r | |
644 | // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),\r | |
645 | // then build a PRP list in the second PRP submission queue entry.\r | |
646 | //\r | |
647 | Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);\r | |
648 | Bytes = Packet->TransferLength;\r | |
649 | \r | |
650 | if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {\r | |
651 | //\r | |
652 | // Create PrpList for remaining data buffer.\r | |
653 | //\r | |
654 | PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r | |
655 | Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);\r | |
656 | if (Prp == NULL) {\r | |
657 | goto EXIT;\r | |
658 | }\r | |
659 | \r | |
660 | Sq->Prp[1] = (UINT64)(UINTN)Prp;\r | |
661 | } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {\r | |
662 | Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r | |
663 | }\r | |
664 | \r | |
d6c55989 FT |
665 | if(Packet->NvmeCmd->Flags & CDW2_VALID) {\r |
666 | Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;\r | |
667 | }\r | |
668 | if(Packet->NvmeCmd->Flags & CDW3_VALID) {\r | |
669 | Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);\r | |
670 | }\r | |
eb290d02 FT |
671 | if(Packet->NvmeCmd->Flags & CDW10_VALID) {\r |
672 | Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;\r | |
673 | }\r | |
674 | if(Packet->NvmeCmd->Flags & CDW11_VALID) {\r | |
675 | Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;\r | |
676 | }\r | |
677 | if(Packet->NvmeCmd->Flags & CDW12_VALID) {\r | |
678 | Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;\r | |
679 | }\r | |
680 | if(Packet->NvmeCmd->Flags & CDW13_VALID) {\r | |
681 | Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;\r | |
682 | }\r | |
683 | if(Packet->NvmeCmd->Flags & CDW14_VALID) {\r | |
684 | Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;\r | |
685 | }\r | |
686 | if(Packet->NvmeCmd->Flags & CDW15_VALID) {\r | |
687 | Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;\r | |
688 | }\r | |
689 | \r | |
690 | //\r | |
691 | // Ring the submission queue doorbell.\r | |
692 | //\r | |
aec53afb | 693 | if ((Event != NULL) && (QueueId != 0)) {\r |
758ea946 HW |
694 | Private->SqTdbl[QueueId].Sqt =\r |
695 | (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);\r | |
696 | } else {\r | |
697 | Private->SqTdbl[QueueId].Sqt ^= 1;\r | |
698 | }\r | |
699 | Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);\r | |
f6b139bd | 700 | Status = PciIo->Mem.Write (\r |
eb290d02 FT |
701 | PciIo,\r |
702 | EfiPciIoWidthUint32,\r | |
703 | NVME_BAR,\r | |
758ea946 | 704 | NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),\r |
eb290d02 | 705 | 1,\r |
7b8883c6 | 706 | &Data\r |
eb290d02 FT |
707 | );\r |
708 | \r | |
f6b139bd SP |
709 | if (EFI_ERROR (Status)) {\r |
710 | goto EXIT;\r | |
711 | }\r | |
712 | \r | |
758ea946 HW |
713 | //\r |
714 | // For non-blocking requests, return directly if the command is placed\r | |
715 | // in the submission queue.\r | |
716 | //\r | |
aec53afb | 717 | if ((Event != NULL) && (QueueId != 0)) {\r |
758ea946 HW |
718 | AsyncRequest = AllocateZeroPool (sizeof (NVME_PASS_THRU_ASYNC_REQ));\r |
719 | if (AsyncRequest == NULL) {\r | |
720 | Status = EFI_DEVICE_ERROR;\r | |
721 | goto EXIT;\r | |
722 | }\r | |
723 | \r | |
724 | AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;\r | |
725 | AsyncRequest->Packet = Packet;\r | |
726 | AsyncRequest->CommandId = Sq->Cid;\r | |
727 | AsyncRequest->CallerEvent = Event;\r | |
f2333c70 SP |
728 | AsyncRequest->MapData = MapData;\r |
729 | AsyncRequest->MapMeta = MapMeta;\r | |
730 | AsyncRequest->MapPrpList = MapPrpList;\r | |
731 | AsyncRequest->PrpListNo = PrpListNo;\r | |
732 | AsyncRequest->PrpListHost = PrpListHost;\r | |
758ea946 HW |
733 | \r |
734 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r | |
735 | InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);\r | |
736 | gBS->RestoreTPL (OldTpl);\r | |
737 | \r | |
738 | return EFI_SUCCESS;\r | |
739 | }\r | |
740 | \r | |
eb290d02 FT |
741 | Status = gBS->CreateEvent (\r |
742 | EVT_TIMER,\r | |
743 | TPL_CALLBACK,\r | |
744 | NULL,\r | |
745 | NULL,\r | |
746 | &TimerEvent\r | |
747 | );\r | |
748 | if (EFI_ERROR (Status)) {\r | |
749 | goto EXIT;\r | |
750 | }\r | |
751 | \r | |
752 | Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);\r | |
753 | \r | |
754 | if (EFI_ERROR(Status)) {\r | |
eb290d02 FT |
755 | goto EXIT;\r |
756 | }\r | |
757 | \r | |
758 | //\r | |
759 | // Wait for completion queue to get filled in.\r | |
760 | //\r | |
761 | Status = EFI_TIMEOUT;\r | |
eb290d02 | 762 | while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {\r |
758ea946 | 763 | if (Cq->Pt != Private->Pt[QueueId]) {\r |
eb290d02 | 764 | Status = EFI_SUCCESS;\r |
eb290d02 FT |
765 | break;\r |
766 | }\r | |
767 | }\r | |
768 | \r | |
eb290d02 | 769 | //\r |
754b489b | 770 | // Check the NVMe cmd execution result\r |
eb290d02 | 771 | //\r |
754b489b TF |
772 | if (Status != EFI_TIMEOUT) {\r |
773 | if ((Cq->Sct == 0) && (Cq->Sc == 0)) {\r | |
774 | Status = EFI_SUCCESS;\r | |
775 | } else {\r | |
776 | Status = EFI_DEVICE_ERROR;\r | |
777 | //\r | |
778 | // Copy the Respose Queue entry for this command to the callers response buffer\r | |
779 | //\r | |
780 | CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r | |
781 | \r | |
782 | //\r | |
783 | // Dump every completion entry status for debugging.\r | |
784 | //\r | |
785 | DEBUG_CODE_BEGIN();\r | |
786 | NvmeDumpStatus(Cq);\r | |
787 | DEBUG_CODE_END();\r | |
788 | }\r | |
5f5bba14 HW |
789 | } else {\r |
790 | //\r | |
791 | // Timeout occurs for an NVMe command. Reset the controller to abort the\r | |
792 | // outstanding commands.\r | |
793 | //\r | |
794 | DEBUG ((DEBUG_ERROR, "NvmExpressPassThru: Timeout occurs for an NVMe command.\n"));\r | |
795 | \r | |
796 | //\r | |
797 | // Disable the timer to trigger the process of async transfers temporarily.\r | |
798 | //\r | |
799 | Status = gBS->SetTimer (Private->TimerEvent, TimerCancel, 0);\r | |
800 | if (EFI_ERROR (Status)) {\r | |
801 | goto EXIT;\r | |
802 | }\r | |
803 | \r | |
804 | //\r | |
805 | // Reset the NVMe controller.\r | |
806 | //\r | |
807 | Status = NvmeControllerInit (Private);\r | |
808 | if (!EFI_ERROR (Status)) {\r | |
809 | Status = AbortAsyncPassThruTasks (Private);\r | |
810 | if (!EFI_ERROR (Status)) {\r | |
811 | //\r | |
812 | // Re-enable the timer to trigger the process of async transfers.\r | |
813 | //\r | |
814 | Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, NVME_HC_ASYNC_TIMER);\r | |
815 | if (!EFI_ERROR (Status)) {\r | |
816 | //\r | |
817 | // Return EFI_TIMEOUT to indicate a timeout occurs for NVMe PassThru command.\r | |
818 | //\r | |
819 | Status = EFI_TIMEOUT;\r | |
820 | }\r | |
821 | }\r | |
822 | } else {\r | |
823 | Status = EFI_DEVICE_ERROR;\r | |
824 | }\r | |
825 | \r | |
826 | goto EXIT;\r | |
754b489b | 827 | }\r |
eb290d02 | 828 | \r |
758ea946 HW |
829 | if ((Private->CqHdbl[QueueId].Cqh ^= 1) == 0) {\r |
830 | Private->Pt[QueueId] ^= 1;\r | |
754b489b | 831 | }\r |
eb290d02 | 832 | \r |
758ea946 | 833 | Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);\r |
f6b139bd | 834 | Status = PciIo->Mem.Write (\r |
eb290d02 FT |
835 | PciIo,\r |
836 | EfiPciIoWidthUint32,\r | |
837 | NVME_BAR,\r | |
758ea946 | 838 | NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),\r |
eb290d02 | 839 | 1,\r |
7b8883c6 | 840 | &Data\r |
eb290d02 FT |
841 | );\r |
842 | \r | |
aec53afb HW |
843 | //\r |
844 | // For now, the code does not support the non-blocking feature for admin queue.\r | |
845 | // If Event is not NULL for admin queue, signal the caller's event here.\r | |
846 | //\r | |
847 | if (Event != NULL) {\r | |
848 | ASSERT (QueueId == 0);\r | |
849 | gBS->SignalEvent (Event);\r | |
850 | }\r | |
851 | \r | |
eb290d02 FT |
852 | EXIT:\r |
853 | if (MapData != NULL) {\r | |
854 | PciIo->Unmap (\r | |
855 | PciIo,\r | |
856 | MapData\r | |
857 | );\r | |
858 | }\r | |
859 | \r | |
860 | if (MapMeta != NULL) {\r | |
861 | PciIo->Unmap (\r | |
862 | PciIo,\r | |
863 | MapMeta\r | |
864 | );\r | |
865 | }\r | |
866 | \r | |
867 | if (MapPrpList != NULL) {\r | |
868 | PciIo->Unmap (\r | |
869 | PciIo,\r | |
870 | MapPrpList\r | |
871 | );\r | |
872 | }\r | |
873 | \r | |
874 | if (Prp != NULL) {\r | |
875 | PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);\r | |
876 | }\r | |
877 | \r | |
878 | if (TimerEvent != NULL) {\r | |
879 | gBS->CloseEvent (TimerEvent);\r | |
880 | }\r | |
881 | return Status;\r | |
882 | }\r | |
883 | \r | |
884 | /**\r | |
d6c55989 | 885 | Used to retrieve the next namespace ID for this NVM Express controller.\r |
eb290d02 | 886 | \r |
d6c55989 FT |
887 | The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid\r |
888 | namespace ID on this NVM Express controller.\r | |
eb290d02 | 889 | \r |
d6c55989 FT |
890 | If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace\r |
891 | ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId\r | |
892 | and a status of EFI_SUCCESS is returned.\r | |
eb290d02 | 893 | \r |
d6c55989 FT |
894 | If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,\r |
895 | then EFI_INVALID_PARAMETER is returned.\r | |
eb290d02 | 896 | \r |
d6c55989 FT |
897 | If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid\r |
898 | namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,\r | |
899 | and EFI_SUCCESS is returned.\r | |
eb290d02 | 900 | \r |
d6c55989 FT |
901 | If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM\r |
902 | Express controller, then EFI_NOT_FOUND is returned.\r | |
903 | \r | |
904 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r | |
eb290d02 FT |
905 | @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express\r |
906 | namespace present on the NVM Express controller. On output, a\r | |
907 | pointer to the next NamespaceId of an NVM Express namespace on\r | |
908 | an NVM Express controller. An input value of 0xFFFFFFFF retrieves\r | |
909 | the first NamespaceId for an NVM Express namespace present on an\r | |
910 | NVM Express controller.\r | |
eb290d02 | 911 | \r |
d6c55989 | 912 | @retval EFI_SUCCESS The Namespace ID of the next Namespace was returned.\r |
eb290d02 | 913 | @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.\r |
d6c55989 | 914 | @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.\r |
eb290d02 FT |
915 | \r |
916 | **/\r | |
917 | EFI_STATUS\r | |
918 | EFIAPI\r | |
919 | NvmExpressGetNextNamespace (\r | |
d6c55989 FT |
920 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
921 | IN OUT UINT32 *NamespaceId\r | |
eb290d02 FT |
922 | )\r |
923 | {\r | |
924 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r | |
925 | NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r | |
926 | UINT32 NextNamespaceId;\r | |
927 | EFI_STATUS Status;\r | |
928 | \r | |
929 | if ((This == NULL) || (NamespaceId == NULL)) {\r | |
930 | return EFI_INVALID_PARAMETER;\r | |
931 | }\r | |
932 | \r | |
933 | NamespaceData = NULL;\r | |
934 | Status = EFI_NOT_FOUND;\r | |
935 | \r | |
936 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r | |
937 | //\r | |
938 | // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID\r | |
939 | //\r | |
940 | if (*NamespaceId == 0xFFFFFFFF) {\r | |
941 | //\r | |
942 | // Start with the first namespace ID\r | |
943 | //\r | |
944 | NextNamespaceId = 1;\r | |
945 | //\r | |
946 | // Allocate buffer for Identify Namespace data.\r | |
947 | //\r | |
948 | NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r | |
949 | \r | |
950 | if (NamespaceData == NULL) {\r | |
951 | return EFI_NOT_FOUND;\r | |
952 | }\r | |
953 | \r | |
954 | Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r | |
955 | if (EFI_ERROR(Status)) {\r | |
956 | goto Done;\r | |
957 | }\r | |
958 | \r | |
959 | *NamespaceId = NextNamespaceId;\r | |
eb290d02 | 960 | } else {\r |
114358ea | 961 | if (*NamespaceId > Private->ControllerData->Nn) {\r |
eb290d02 FT |
962 | return EFI_INVALID_PARAMETER;\r |
963 | }\r | |
964 | \r | |
965 | NextNamespaceId = *NamespaceId + 1;\r | |
114358ea HW |
966 | if (NextNamespaceId > Private->ControllerData->Nn) {\r |
967 | return EFI_NOT_FOUND;\r | |
968 | }\r | |
969 | \r | |
eb290d02 FT |
970 | //\r |
971 | // Allocate buffer for Identify Namespace data.\r | |
972 | //\r | |
973 | NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r | |
974 | if (NamespaceData == NULL) {\r | |
975 | return EFI_NOT_FOUND;\r | |
976 | }\r | |
977 | \r | |
978 | Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r | |
979 | if (EFI_ERROR(Status)) {\r | |
980 | goto Done;\r | |
981 | }\r | |
982 | \r | |
983 | *NamespaceId = NextNamespaceId;\r | |
eb290d02 FT |
984 | }\r |
985 | \r | |
986 | Done:\r | |
987 | if (NamespaceData != NULL) {\r | |
988 | FreePool(NamespaceData);\r | |
989 | }\r | |
990 | \r | |
991 | return Status;\r | |
992 | }\r | |
993 | \r | |
994 | /**\r | |
d6c55989 FT |
995 | Used to translate a device path node to a namespace ID.\r |
996 | \r | |
997 | The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the\r | |
998 | namespace described by DevicePath.\r | |
eb290d02 | 999 | \r |
d6c55989 FT |
1000 | If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express\r |
1001 | Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.\r | |
eb290d02 | 1002 | \r |
d6c55989 FT |
1003 | If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned\r |
1004 | \r | |
1005 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r | |
eb290d02 FT |
1006 | @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on\r |
1007 | the NVM Express controller.\r | |
1008 | @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.\r | |
eb290d02 | 1009 | \r |
d6c55989 FT |
1010 | @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId.\r |
1011 | @retval EFI_INVALID_PARAMETER If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.\r | |
eb290d02 FT |
1012 | @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver\r |
1013 | supports, then EFI_UNSUPPORTED is returned.\r | |
d6c55989 FT |
1014 | @retval EFI_NOT_FOUND If DevicePath is a device path node type that the NVM Express Pass Thru driver\r |
1015 | supports, but there is not a valid translation from DevicePath to a namespace ID,\r | |
1016 | then EFI_NOT_FOUND is returned.\r | |
eb290d02 FT |
1017 | **/\r |
1018 | EFI_STATUS\r | |
1019 | EFIAPI\r | |
1020 | NvmExpressGetNamespace (\r | |
d6c55989 | 1021 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
eb290d02 | 1022 | IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r |
d6c55989 | 1023 | OUT UINT32 *NamespaceId\r |
eb290d02 FT |
1024 | )\r |
1025 | {\r | |
1026 | NVME_NAMESPACE_DEVICE_PATH *Node;\r | |
284dc9bf | 1027 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r |
eb290d02 | 1028 | \r |
d6c55989 | 1029 | if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {\r |
eb290d02 FT |
1030 | return EFI_INVALID_PARAMETER;\r |
1031 | }\r | |
1032 | \r | |
1033 | if (DevicePath->Type != MESSAGING_DEVICE_PATH) {\r | |
1034 | return EFI_UNSUPPORTED;\r | |
1035 | }\r | |
1036 | \r | |
284dc9bf HW |
1037 | Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;\r |
1038 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r | |
eb290d02 FT |
1039 | \r |
1040 | if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {\r | |
1041 | if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {\r | |
1042 | return EFI_NOT_FOUND;\r | |
1043 | }\r | |
1044 | \r | |
284dc9bf HW |
1045 | //\r |
1046 | // Check NamespaceId in the device path node is valid or not.\r | |
1047 | //\r | |
1048 | if ((Node->NamespaceId == 0) ||\r | |
1049 | (Node->NamespaceId > Private->ControllerData->Nn)) {\r | |
1050 | return EFI_NOT_FOUND;\r | |
1051 | }\r | |
1052 | \r | |
d6c55989 | 1053 | *NamespaceId = Node->NamespaceId;\r |
eb290d02 FT |
1054 | \r |
1055 | return EFI_SUCCESS;\r | |
1056 | } else {\r | |
1057 | return EFI_UNSUPPORTED;\r | |
1058 | }\r | |
1059 | }\r | |
1060 | \r | |
1061 | /**\r | |
1062 | Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.\r | |
1063 | \r | |
d6c55989 | 1064 | The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device\r |
eb290d02 FT |
1065 | path node for the NVM Express namespace specified by NamespaceId.\r |
1066 | \r | |
d6c55989 | 1067 | If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.\r |
eb290d02 FT |
1068 | \r |
1069 | If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.\r | |
1070 | \r | |
1071 | If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.\r | |
1072 | \r | |
1073 | Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are\r | |
1074 | initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.\r | |
1075 | \r | |
d6c55989 | 1076 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r |
eb290d02 FT |
1077 | @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be\r |
1078 | allocated and built. Caller must set the NamespaceId to zero if the\r | |
1079 | device path node will contain a valid UUID.\r | |
eb290d02 FT |
1080 | @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express\r |
1081 | namespace specified by NamespaceId. This function is responsible for\r | |
1082 | allocating the buffer DevicePath with the boot service AllocatePool().\r | |
1083 | It is the caller's responsibility to free DevicePath when the caller\r | |
1084 | is finished with DevicePath.\r | |
1085 | @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified\r | |
1086 | by NamespaceId was allocated and returned in DevicePath.\r | |
d6c55989 | 1087 | @retval EFI_NOT_FOUND The NamespaceId is not valid.\r |
eb290d02 FT |
1088 | @retval EFI_INVALID_PARAMETER DevicePath is NULL.\r |
1089 | @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.\r | |
1090 | \r | |
1091 | **/\r | |
1092 | EFI_STATUS\r | |
1093 | EFIAPI\r | |
1094 | NvmExpressBuildDevicePath (\r | |
d6c55989 | 1095 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
eb290d02 | 1096 | IN UINT32 NamespaceId,\r |
eb290d02 FT |
1097 | IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r |
1098 | )\r | |
1099 | {\r | |
eb290d02 | 1100 | NVME_NAMESPACE_DEVICE_PATH *Node;\r |
d6c55989 FT |
1101 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r |
1102 | EFI_STATUS Status;\r | |
1103 | NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r | |
eb290d02 FT |
1104 | \r |
1105 | //\r | |
1106 | // Validate parameters\r | |
1107 | //\r | |
1108 | if ((This == NULL) || (DevicePath == NULL)) {\r | |
1109 | return EFI_INVALID_PARAMETER;\r | |
1110 | }\r | |
1111 | \r | |
d6c55989 FT |
1112 | Status = EFI_SUCCESS;\r |
1113 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r | |
eb290d02 | 1114 | \r |
946f48eb HW |
1115 | //\r |
1116 | // Check NamespaceId is valid or not.\r | |
1117 | //\r | |
1118 | if ((NamespaceId == 0) ||\r | |
1119 | (NamespaceId > Private->ControllerData->Nn)) {\r | |
1120 | return EFI_NOT_FOUND;\r | |
1121 | }\r | |
1122 | \r | |
d6c55989 | 1123 | Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));\r |
eb290d02 FT |
1124 | if (Node == NULL) {\r |
1125 | return EFI_OUT_OF_RESOURCES;\r | |
1126 | }\r | |
1127 | \r | |
1128 | Node->Header.Type = MESSAGING_DEVICE_PATH;\r | |
1129 | Node->Header.SubType = MSG_NVME_NAMESPACE_DP;\r | |
1130 | SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));\r | |
1131 | Node->NamespaceId = NamespaceId;\r | |
d6c55989 FT |
1132 | \r |
1133 | //\r | |
1134 | // Allocate a buffer for Identify Namespace data.\r | |
1135 | //\r | |
1136 | NamespaceData = NULL;\r | |
1137 | NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));\r | |
1138 | if(NamespaceData == NULL) {\r | |
1139 | Status = EFI_OUT_OF_RESOURCES;\r | |
1140 | goto Exit;\r | |
1141 | }\r | |
1142 | \r | |
1143 | //\r | |
1144 | // Get UUID from specified Identify Namespace data.\r | |
1145 | //\r | |
1146 | Status = NvmeIdentifyNamespace (\r | |
1147 | Private,\r | |
1148 | NamespaceId,\r | |
1149 | (VOID *)NamespaceData\r | |
1150 | );\r | |
1151 | \r | |
1152 | if (EFI_ERROR(Status)) {\r | |
1153 | goto Exit;\r | |
1154 | }\r | |
1155 | \r | |
1156 | Node->NamespaceUuid = NamespaceData->Eui64;\r | |
eb290d02 FT |
1157 | \r |
1158 | *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;\r | |
d6c55989 FT |
1159 | \r |
1160 | Exit:\r | |
1161 | if(NamespaceData != NULL) {\r | |
1162 | FreePool (NamespaceData);\r | |
1163 | }\r | |
1164 | \r | |
1165 | if (EFI_ERROR (Status)) {\r | |
1166 | FreePool (Node);\r | |
1167 | }\r | |
1168 | \r | |
1169 | return Status;\r | |
eb290d02 FT |
1170 | }\r |
1171 | \r |