]>
Commit | Line | Data |
---|---|---|
5d73d92f | 1 | /** @file\r |
2 | Main file for Pci shell Debug1 function.\r | |
3 | \r | |
f056e4c1 | 4 | (C) Copyright 2013-2014 Hewlett-Packard Development Company, L.P.\r |
705bffb5 | 5 | Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR>\r |
5d73d92f | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "UefiShellDebug1CommandsLib.h"\r | |
17 | #include <Protocol/PciRootBridgeIo.h>\r | |
18 | #include <Library/ShellLib.h>\r | |
19 | #include <IndustryStandard/Pci.h>\r | |
20 | #include <IndustryStandard/Acpi.h>\r | |
21 | #include "Pci.h"\r | |
22 | \r | |
5d73d92f | 23 | //\r |
24 | // Printable strings for Pci class code\r | |
25 | //\r | |
26 | typedef struct {\r | |
27 | CHAR16 *BaseClass; // Pointer to the PCI base class string\r | |
28 | CHAR16 *SubClass; // Pointer to the PCI sub class string\r | |
29 | CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r | |
30 | } PCI_CLASS_STRINGS;\r | |
31 | \r | |
32 | //\r | |
33 | // a structure holding a single entry, which also points to its lower level\r | |
34 | // class\r | |
35 | //\r | |
36 | typedef struct PCI_CLASS_ENTRY_TAG {\r | |
37 | UINT8 Code; // Class, subclass or I/F code\r | |
38 | CHAR16 *DescText; // Description string\r | |
39 | struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r | |
40 | } PCI_CLASS_ENTRY;\r | |
41 | \r | |
42 | //\r | |
43 | // Declarations of entries which contain printable strings for class codes\r | |
44 | // in PCI configuration space\r | |
45 | //\r | |
46 | PCI_CLASS_ENTRY PCIBlankEntry[];\r | |
47 | PCI_CLASS_ENTRY PCISubClass_00[];\r | |
48 | PCI_CLASS_ENTRY PCISubClass_01[];\r | |
49 | PCI_CLASS_ENTRY PCISubClass_02[];\r | |
50 | PCI_CLASS_ENTRY PCISubClass_03[];\r | |
51 | PCI_CLASS_ENTRY PCISubClass_04[];\r | |
52 | PCI_CLASS_ENTRY PCISubClass_05[];\r | |
53 | PCI_CLASS_ENTRY PCISubClass_06[];\r | |
54 | PCI_CLASS_ENTRY PCISubClass_07[];\r | |
55 | PCI_CLASS_ENTRY PCISubClass_08[];\r | |
56 | PCI_CLASS_ENTRY PCISubClass_09[];\r | |
57 | PCI_CLASS_ENTRY PCISubClass_0a[];\r | |
58 | PCI_CLASS_ENTRY PCISubClass_0b[];\r | |
59 | PCI_CLASS_ENTRY PCISubClass_0c[];\r | |
60 | PCI_CLASS_ENTRY PCISubClass_0d[];\r | |
61 | PCI_CLASS_ENTRY PCISubClass_0e[];\r | |
62 | PCI_CLASS_ENTRY PCISubClass_0f[];\r | |
63 | PCI_CLASS_ENTRY PCISubClass_10[];\r | |
64 | PCI_CLASS_ENTRY PCISubClass_11[];\r | |
f056e4c1 JC |
65 | PCI_CLASS_ENTRY PCISubClass_12[];\r |
66 | PCI_CLASS_ENTRY PCISubClass_13[];\r | |
67 | PCI_CLASS_ENTRY PCIPIFClass_0100[];\r | |
5d73d92f | 68 | PCI_CLASS_ENTRY PCIPIFClass_0101[];\r |
f056e4c1 JC |
69 | PCI_CLASS_ENTRY PCIPIFClass_0105[];\r |
70 | PCI_CLASS_ENTRY PCIPIFClass_0106[];\r | |
71 | PCI_CLASS_ENTRY PCIPIFClass_0107[];\r | |
72 | PCI_CLASS_ENTRY PCIPIFClass_0108[];\r | |
73 | PCI_CLASS_ENTRY PCIPIFClass_0109[];\r | |
5d73d92f | 74 | PCI_CLASS_ENTRY PCIPIFClass_0300[];\r |
75 | PCI_CLASS_ENTRY PCIPIFClass_0604[];\r | |
f056e4c1 JC |
76 | PCI_CLASS_ENTRY PCIPIFClass_0609[];\r |
77 | PCI_CLASS_ENTRY PCIPIFClass_060b[];\r | |
5d73d92f | 78 | PCI_CLASS_ENTRY PCIPIFClass_0700[];\r |
79 | PCI_CLASS_ENTRY PCIPIFClass_0701[];\r | |
80 | PCI_CLASS_ENTRY PCIPIFClass_0703[];\r | |
81 | PCI_CLASS_ENTRY PCIPIFClass_0800[];\r | |
82 | PCI_CLASS_ENTRY PCIPIFClass_0801[];\r | |
83 | PCI_CLASS_ENTRY PCIPIFClass_0802[];\r | |
84 | PCI_CLASS_ENTRY PCIPIFClass_0803[];\r | |
85 | PCI_CLASS_ENTRY PCIPIFClass_0904[];\r | |
86 | PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r | |
87 | PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r | |
f056e4c1 JC |
88 | PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r |
89 | PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r | |
5d73d92f | 90 | PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r |
91 | \r | |
92 | //\r | |
93 | // Base class strings entries\r | |
94 | //\r | |
95 | PCI_CLASS_ENTRY gClassStringList[] = {\r | |
96 | {\r | |
97 | 0x00,\r | |
98 | L"Pre 2.0 device",\r | |
99 | PCISubClass_00\r | |
100 | },\r | |
101 | {\r | |
102 | 0x01,\r | |
103 | L"Mass Storage Controller",\r | |
104 | PCISubClass_01\r | |
105 | },\r | |
106 | {\r | |
107 | 0x02,\r | |
108 | L"Network Controller",\r | |
109 | PCISubClass_02\r | |
110 | },\r | |
111 | {\r | |
112 | 0x03,\r | |
113 | L"Display Controller",\r | |
114 | PCISubClass_03\r | |
115 | },\r | |
116 | {\r | |
117 | 0x04,\r | |
118 | L"Multimedia Device",\r | |
119 | PCISubClass_04\r | |
120 | },\r | |
121 | {\r | |
122 | 0x05,\r | |
123 | L"Memory Controller",\r | |
124 | PCISubClass_05\r | |
125 | },\r | |
126 | {\r | |
127 | 0x06,\r | |
128 | L"Bridge Device",\r | |
129 | PCISubClass_06\r | |
130 | },\r | |
131 | {\r | |
132 | 0x07,\r | |
133 | L"Simple Communications Controllers",\r | |
134 | PCISubClass_07\r | |
135 | },\r | |
136 | {\r | |
137 | 0x08,\r | |
138 | L"Base System Peripherals",\r | |
139 | PCISubClass_08\r | |
140 | },\r | |
141 | {\r | |
142 | 0x09,\r | |
143 | L"Input Devices",\r | |
144 | PCISubClass_09\r | |
145 | },\r | |
146 | {\r | |
147 | 0x0a,\r | |
148 | L"Docking Stations",\r | |
149 | PCISubClass_0a\r | |
150 | },\r | |
151 | {\r | |
152 | 0x0b,\r | |
153 | L"Processors",\r | |
154 | PCISubClass_0b\r | |
155 | },\r | |
156 | {\r | |
157 | 0x0c,\r | |
158 | L"Serial Bus Controllers",\r | |
159 | PCISubClass_0c\r | |
160 | },\r | |
161 | {\r | |
162 | 0x0d,\r | |
163 | L"Wireless Controllers",\r | |
164 | PCISubClass_0d\r | |
165 | },\r | |
166 | {\r | |
167 | 0x0e,\r | |
168 | L"Intelligent IO Controllers",\r | |
169 | PCISubClass_0e\r | |
170 | },\r | |
171 | {\r | |
172 | 0x0f,\r | |
173 | L"Satellite Communications Controllers",\r | |
174 | PCISubClass_0f\r | |
175 | },\r | |
176 | {\r | |
177 | 0x10,\r | |
178 | L"Encryption/Decryption Controllers",\r | |
179 | PCISubClass_10\r | |
180 | },\r | |
181 | {\r | |
182 | 0x11,\r | |
183 | L"Data Acquisition & Signal Processing Controllers",\r | |
184 | PCISubClass_11\r | |
185 | },\r | |
f056e4c1 JC |
186 | {\r |
187 | 0x12,\r | |
188 | L"Processing Accelerators",\r | |
189 | PCISubClass_12\r | |
190 | },\r | |
191 | {\r | |
192 | 0x13,\r | |
193 | L"Non-Essential Instrumentation",\r | |
194 | PCISubClass_13\r | |
195 | },\r | |
5d73d92f | 196 | {\r |
197 | 0xff,\r | |
198 | L"Device does not fit in any defined classes",\r | |
199 | PCIBlankEntry\r | |
200 | },\r | |
201 | {\r | |
202 | 0x00,\r | |
203 | NULL,\r | |
204 | /* null string ends the list */NULL\r | |
205 | }\r | |
206 | };\r | |
207 | \r | |
208 | //\r | |
209 | // Subclass strings entries\r | |
210 | //\r | |
211 | PCI_CLASS_ENTRY PCIBlankEntry[] = {\r | |
212 | {\r | |
213 | 0x00,\r | |
214 | L"",\r | |
215 | PCIBlankEntry\r | |
216 | },\r | |
217 | {\r | |
218 | 0x00,\r | |
219 | NULL,\r | |
220 | /* null string ends the list */NULL\r | |
221 | }\r | |
222 | };\r | |
223 | \r | |
224 | PCI_CLASS_ENTRY PCISubClass_00[] = {\r | |
225 | {\r | |
226 | 0x00,\r | |
227 | L"All devices other than VGA",\r | |
228 | PCIBlankEntry\r | |
229 | },\r | |
230 | {\r | |
231 | 0x01,\r | |
232 | L"VGA-compatible devices",\r | |
233 | PCIBlankEntry\r | |
234 | },\r | |
235 | {\r | |
236 | 0x00,\r | |
237 | NULL,\r | |
238 | /* null string ends the list */NULL\r | |
239 | }\r | |
240 | };\r | |
241 | \r | |
242 | PCI_CLASS_ENTRY PCISubClass_01[] = {\r | |
243 | {\r | |
244 | 0x00,\r | |
f056e4c1 JC |
245 | L"SCSI",\r |
246 | PCIPIFClass_0100\r | |
5d73d92f | 247 | },\r |
248 | {\r | |
249 | 0x01,\r | |
250 | L"IDE controller",\r | |
251 | PCIPIFClass_0101\r | |
252 | },\r | |
253 | {\r | |
254 | 0x02,\r | |
255 | L"Floppy disk controller",\r | |
256 | PCIBlankEntry\r | |
257 | },\r | |
258 | {\r | |
259 | 0x03,\r | |
260 | L"IPI controller",\r | |
261 | PCIBlankEntry\r | |
262 | },\r | |
263 | {\r | |
264 | 0x04,\r | |
265 | L"RAID controller",\r | |
266 | PCIBlankEntry\r | |
267 | },\r | |
f056e4c1 JC |
268 | {\r |
269 | 0x05,\r | |
270 | L"ATA controller with ADMA interface",\r | |
271 | PCIPIFClass_0105\r | |
272 | },\r | |
273 | {\r | |
274 | 0x06,\r | |
275 | L"Serial ATA controller",\r | |
276 | PCIPIFClass_0106\r | |
277 | },\r | |
278 | {\r | |
279 | 0x07,\r | |
280 | L"Serial Attached SCSI (SAS) controller ",\r | |
281 | PCIPIFClass_0107\r | |
282 | },\r | |
283 | {\r | |
284 | 0x08,\r | |
285 | L"Non-volatile memory subsystem",\r | |
286 | PCIPIFClass_0108\r | |
287 | },\r | |
288 | {\r | |
289 | 0x09,\r | |
290 | L"Universal Flash Storage (UFS) controller ",\r | |
291 | PCIPIFClass_0109\r | |
292 | },\r | |
5d73d92f | 293 | {\r |
294 | 0x80,\r | |
295 | L"Other mass storage controller",\r | |
296 | PCIBlankEntry\r | |
297 | },\r | |
298 | {\r | |
299 | 0x00,\r | |
300 | NULL,\r | |
301 | /* null string ends the list */NULL\r | |
302 | }\r | |
303 | };\r | |
304 | \r | |
305 | PCI_CLASS_ENTRY PCISubClass_02[] = {\r | |
306 | {\r | |
307 | 0x00,\r | |
308 | L"Ethernet controller",\r | |
309 | PCIBlankEntry\r | |
310 | },\r | |
311 | {\r | |
312 | 0x01,\r | |
313 | L"Token ring controller",\r | |
314 | PCIBlankEntry\r | |
315 | },\r | |
316 | {\r | |
317 | 0x02,\r | |
318 | L"FDDI controller",\r | |
319 | PCIBlankEntry\r | |
320 | },\r | |
321 | {\r | |
322 | 0x03,\r | |
323 | L"ATM controller",\r | |
324 | PCIBlankEntry\r | |
325 | },\r | |
326 | {\r | |
327 | 0x04,\r | |
328 | L"ISDN controller",\r | |
329 | PCIBlankEntry\r | |
330 | },\r | |
f056e4c1 JC |
331 | {\r |
332 | 0x05,\r | |
333 | L"WorldFip controller",\r | |
334 | PCIBlankEntry\r | |
335 | },\r | |
336 | {\r | |
337 | 0x06,\r | |
338 | L"PICMG 2.14 Multi Computing",\r | |
339 | PCIBlankEntry\r | |
340 | },\r | |
341 | {\r | |
342 | 0x07,\r | |
343 | L"InfiniBand controller",\r | |
344 | PCIBlankEntry\r | |
345 | },\r | |
5d73d92f | 346 | {\r |
347 | 0x80,\r | |
348 | L"Other network controller",\r | |
349 | PCIBlankEntry\r | |
350 | },\r | |
351 | {\r | |
352 | 0x00,\r | |
353 | NULL,\r | |
354 | /* null string ends the list */NULL\r | |
355 | }\r | |
356 | };\r | |
357 | \r | |
358 | PCI_CLASS_ENTRY PCISubClass_03[] = {\r | |
359 | {\r | |
360 | 0x00,\r | |
361 | L"VGA/8514 controller",\r | |
362 | PCIPIFClass_0300\r | |
363 | },\r | |
364 | {\r | |
365 | 0x01,\r | |
366 | L"XGA controller",\r | |
367 | PCIBlankEntry\r | |
368 | },\r | |
369 | {\r | |
370 | 0x02,\r | |
371 | L"3D controller",\r | |
372 | PCIBlankEntry\r | |
373 | },\r | |
374 | {\r | |
375 | 0x80,\r | |
376 | L"Other display controller",\r | |
377 | PCIBlankEntry\r | |
378 | },\r | |
379 | {\r | |
380 | 0x00,\r | |
381 | NULL,\r | |
382 | /* null string ends the list */PCIBlankEntry\r | |
383 | }\r | |
384 | };\r | |
385 | \r | |
386 | PCI_CLASS_ENTRY PCISubClass_04[] = {\r | |
387 | {\r | |
388 | 0x00,\r | |
389 | L"Video device",\r | |
390 | PCIBlankEntry\r | |
391 | },\r | |
392 | {\r | |
393 | 0x01,\r | |
394 | L"Audio device",\r | |
395 | PCIBlankEntry\r | |
396 | },\r | |
397 | {\r | |
398 | 0x02,\r | |
399 | L"Computer Telephony device",\r | |
400 | PCIBlankEntry\r | |
401 | },\r | |
f056e4c1 JC |
402 | {\r |
403 | 0x03,\r | |
404 | L"Mixed mode device",\r | |
405 | PCIBlankEntry\r | |
406 | },\r | |
5d73d92f | 407 | {\r |
408 | 0x80,\r | |
409 | L"Other multimedia device",\r | |
410 | PCIBlankEntry\r | |
411 | },\r | |
412 | {\r | |
413 | 0x00,\r | |
414 | NULL,\r | |
415 | /* null string ends the list */NULL\r | |
416 | }\r | |
417 | };\r | |
418 | \r | |
419 | PCI_CLASS_ENTRY PCISubClass_05[] = {\r | |
420 | {\r | |
421 | 0x00,\r | |
422 | L"RAM memory controller",\r | |
423 | PCIBlankEntry\r | |
424 | },\r | |
425 | {\r | |
426 | 0x01,\r | |
427 | L"Flash memory controller",\r | |
428 | PCIBlankEntry\r | |
429 | },\r | |
430 | {\r | |
431 | 0x80,\r | |
432 | L"Other memory controller",\r | |
433 | PCIBlankEntry\r | |
434 | },\r | |
435 | {\r | |
436 | 0x00,\r | |
437 | NULL,\r | |
438 | /* null string ends the list */NULL\r | |
439 | }\r | |
440 | };\r | |
441 | \r | |
442 | PCI_CLASS_ENTRY PCISubClass_06[] = {\r | |
443 | {\r | |
444 | 0x00,\r | |
445 | L"Host/PCI bridge",\r | |
446 | PCIBlankEntry\r | |
447 | },\r | |
448 | {\r | |
449 | 0x01,\r | |
450 | L"PCI/ISA bridge",\r | |
451 | PCIBlankEntry\r | |
452 | },\r | |
453 | {\r | |
454 | 0x02,\r | |
455 | L"PCI/EISA bridge",\r | |
456 | PCIBlankEntry\r | |
457 | },\r | |
458 | {\r | |
459 | 0x03,\r | |
460 | L"PCI/Micro Channel bridge",\r | |
461 | PCIBlankEntry\r | |
462 | },\r | |
463 | {\r | |
464 | 0x04,\r | |
465 | L"PCI/PCI bridge",\r | |
466 | PCIPIFClass_0604\r | |
467 | },\r | |
468 | {\r | |
469 | 0x05,\r | |
470 | L"PCI/PCMCIA bridge",\r | |
471 | PCIBlankEntry\r | |
472 | },\r | |
473 | {\r | |
474 | 0x06,\r | |
475 | L"NuBus bridge",\r | |
476 | PCIBlankEntry\r | |
477 | },\r | |
478 | {\r | |
479 | 0x07,\r | |
480 | L"CardBus bridge",\r | |
481 | PCIBlankEntry\r | |
482 | },\r | |
483 | {\r | |
484 | 0x08,\r | |
485 | L"RACEway bridge",\r | |
486 | PCIBlankEntry\r | |
487 | },\r | |
f056e4c1 JC |
488 | {\r |
489 | 0x09,\r | |
490 | L"Semi-transparent PCI-to-PCI bridge",\r | |
491 | PCIPIFClass_0609\r | |
492 | },\r | |
493 | {\r | |
494 | 0x0A,\r | |
495 | L"InfiniBand-to-PCI host bridge",\r | |
496 | PCIBlankEntry\r | |
497 | },\r | |
498 | {\r | |
499 | 0x0B,\r | |
500 | L"Advanced Switching to PCI host bridge",\r | |
501 | PCIPIFClass_060b\r | |
502 | },\r | |
5d73d92f | 503 | {\r |
504 | 0x80,\r | |
505 | L"Other bridge type",\r | |
506 | PCIBlankEntry\r | |
507 | },\r | |
508 | {\r | |
509 | 0x00,\r | |
510 | NULL,\r | |
511 | /* null string ends the list */NULL\r | |
512 | }\r | |
513 | };\r | |
514 | \r | |
515 | PCI_CLASS_ENTRY PCISubClass_07[] = {\r | |
516 | {\r | |
517 | 0x00,\r | |
518 | L"Serial controller",\r | |
519 | PCIPIFClass_0700\r | |
520 | },\r | |
521 | {\r | |
522 | 0x01,\r | |
523 | L"Parallel port",\r | |
524 | PCIPIFClass_0701\r | |
525 | },\r | |
526 | {\r | |
527 | 0x02,\r | |
528 | L"Multiport serial controller",\r | |
529 | PCIBlankEntry\r | |
530 | },\r | |
531 | {\r | |
532 | 0x03,\r | |
533 | L"Modem",\r | |
534 | PCIPIFClass_0703\r | |
535 | },\r | |
f056e4c1 JC |
536 | {\r |
537 | 0x04,\r | |
538 | L"GPIB (IEEE 488.1/2) controller",\r | |
539 | PCIBlankEntry\r | |
540 | },\r | |
541 | {\r | |
542 | 0x05,\r | |
543 | L"Smart Card",\r | |
544 | PCIBlankEntry\r | |
545 | },\r | |
5d73d92f | 546 | {\r |
547 | 0x80,\r | |
548 | L"Other communication device",\r | |
549 | PCIBlankEntry\r | |
550 | },\r | |
551 | {\r | |
552 | 0x00,\r | |
553 | NULL,\r | |
554 | /* null string ends the list */NULL\r | |
555 | }\r | |
556 | };\r | |
557 | \r | |
558 | PCI_CLASS_ENTRY PCISubClass_08[] = {\r | |
559 | {\r | |
560 | 0x00,\r | |
561 | L"PIC",\r | |
562 | PCIPIFClass_0800\r | |
563 | },\r | |
564 | {\r | |
565 | 0x01,\r | |
566 | L"DMA controller",\r | |
567 | PCIPIFClass_0801\r | |
568 | },\r | |
569 | {\r | |
570 | 0x02,\r | |
571 | L"System timer",\r | |
572 | PCIPIFClass_0802\r | |
573 | },\r | |
574 | {\r | |
575 | 0x03,\r | |
576 | L"RTC controller",\r | |
577 | PCIPIFClass_0803\r | |
578 | },\r | |
579 | {\r | |
580 | 0x04,\r | |
581 | L"Generic PCI Hot-Plug controller",\r | |
582 | PCIBlankEntry\r | |
583 | },\r | |
f056e4c1 JC |
584 | {\r |
585 | 0x05,\r | |
586 | L"SD Host controller",\r | |
587 | PCIBlankEntry\r | |
588 | },\r | |
589 | {\r | |
590 | 0x06,\r | |
591 | L"IOMMU",\r | |
592 | PCIBlankEntry\r | |
593 | },\r | |
594 | {\r | |
595 | 0x07,\r | |
596 | L"Root Complex Event Collector",\r | |
597 | PCIBlankEntry\r | |
598 | },\r | |
5d73d92f | 599 | {\r |
600 | 0x80,\r | |
601 | L"Other system peripheral",\r | |
602 | PCIBlankEntry\r | |
603 | },\r | |
604 | {\r | |
605 | 0x00,\r | |
606 | NULL,\r | |
607 | /* null string ends the list */NULL\r | |
608 | }\r | |
609 | };\r | |
610 | \r | |
611 | PCI_CLASS_ENTRY PCISubClass_09[] = {\r | |
612 | {\r | |
613 | 0x00,\r | |
614 | L"Keyboard controller",\r | |
615 | PCIBlankEntry\r | |
616 | },\r | |
617 | {\r | |
618 | 0x01,\r | |
619 | L"Digitizer (pen)",\r | |
620 | PCIBlankEntry\r | |
621 | },\r | |
622 | {\r | |
623 | 0x02,\r | |
624 | L"Mouse controller",\r | |
625 | PCIBlankEntry\r | |
626 | },\r | |
627 | {\r | |
628 | 0x03,\r | |
629 | L"Scanner controller",\r | |
630 | PCIBlankEntry\r | |
631 | },\r | |
632 | {\r | |
633 | 0x04,\r | |
634 | L"Gameport controller",\r | |
635 | PCIPIFClass_0904\r | |
636 | },\r | |
637 | {\r | |
638 | 0x80,\r | |
639 | L"Other input controller",\r | |
640 | PCIBlankEntry\r | |
641 | },\r | |
642 | {\r | |
643 | 0x00,\r | |
644 | NULL,\r | |
645 | /* null string ends the list */NULL\r | |
646 | }\r | |
647 | };\r | |
648 | \r | |
649 | PCI_CLASS_ENTRY PCISubClass_0a[] = {\r | |
650 | {\r | |
651 | 0x00,\r | |
652 | L"Generic docking station",\r | |
653 | PCIBlankEntry\r | |
654 | },\r | |
655 | {\r | |
656 | 0x80,\r | |
657 | L"Other type of docking station",\r | |
658 | PCIBlankEntry\r | |
659 | },\r | |
660 | {\r | |
661 | 0x00,\r | |
662 | NULL,\r | |
663 | /* null string ends the list */NULL\r | |
664 | }\r | |
665 | };\r | |
666 | \r | |
667 | PCI_CLASS_ENTRY PCISubClass_0b[] = {\r | |
668 | {\r | |
669 | 0x00,\r | |
670 | L"386",\r | |
671 | PCIBlankEntry\r | |
672 | },\r | |
673 | {\r | |
674 | 0x01,\r | |
675 | L"486",\r | |
676 | PCIBlankEntry\r | |
677 | },\r | |
678 | {\r | |
679 | 0x02,\r | |
680 | L"Pentium",\r | |
681 | PCIBlankEntry\r | |
682 | },\r | |
683 | {\r | |
684 | 0x10,\r | |
685 | L"Alpha",\r | |
686 | PCIBlankEntry\r | |
687 | },\r | |
688 | {\r | |
689 | 0x20,\r | |
690 | L"PowerPC",\r | |
691 | PCIBlankEntry\r | |
692 | },\r | |
693 | {\r | |
694 | 0x30,\r | |
695 | L"MIPS",\r | |
696 | PCIBlankEntry\r | |
697 | },\r | |
698 | {\r | |
699 | 0x40,\r | |
700 | L"Co-processor",\r | |
701 | PCIBlankEntry\r | |
702 | },\r | |
703 | {\r | |
704 | 0x80,\r | |
705 | L"Other processor",\r | |
706 | PCIBlankEntry\r | |
707 | },\r | |
708 | {\r | |
709 | 0x00,\r | |
710 | NULL,\r | |
711 | /* null string ends the list */NULL\r | |
712 | }\r | |
713 | };\r | |
714 | \r | |
715 | PCI_CLASS_ENTRY PCISubClass_0c[] = {\r | |
716 | {\r | |
717 | 0x00,\r | |
f056e4c1 JC |
718 | L"IEEE 1394",\r |
719 | PCIPIFClass_0c00\r | |
5d73d92f | 720 | },\r |
721 | {\r | |
722 | 0x01,\r | |
723 | L"ACCESS.bus",\r | |
724 | PCIBlankEntry\r | |
725 | },\r | |
726 | {\r | |
727 | 0x02,\r | |
728 | L"SSA",\r | |
729 | PCIBlankEntry\r | |
730 | },\r | |
731 | {\r | |
732 | 0x03,\r | |
733 | L"USB",\r | |
f056e4c1 | 734 | PCIPIFClass_0c03\r |
5d73d92f | 735 | },\r |
736 | {\r | |
737 | 0x04,\r | |
738 | L"Fibre Channel",\r | |
739 | PCIBlankEntry\r | |
740 | },\r | |
741 | {\r | |
742 | 0x05,\r | |
743 | L"System Management Bus",\r | |
744 | PCIBlankEntry\r | |
745 | },\r | |
f056e4c1 JC |
746 | {\r |
747 | 0x06,\r | |
748 | L"InfiniBand",\r | |
749 | PCIBlankEntry\r | |
750 | },\r | |
751 | {\r | |
752 | 0x07,\r | |
753 | L"IPMI",\r | |
754 | PCIPIFClass_0c07\r | |
755 | },\r | |
756 | {\r | |
757 | 0x08,\r | |
758 | L"SERCOS Interface Standard (IEC 61491)",\r | |
759 | PCIBlankEntry\r | |
760 | },\r | |
761 | {\r | |
762 | 0x09,\r | |
763 | L"CANbus",\r | |
764 | PCIBlankEntry\r | |
765 | },\r | |
5d73d92f | 766 | {\r |
767 | 0x80,\r | |
768 | L"Other bus type",\r | |
769 | PCIBlankEntry\r | |
770 | },\r | |
771 | {\r | |
772 | 0x00,\r | |
773 | NULL,\r | |
774 | /* null string ends the list */NULL\r | |
775 | }\r | |
776 | };\r | |
777 | \r | |
778 | PCI_CLASS_ENTRY PCISubClass_0d[] = {\r | |
779 | {\r | |
780 | 0x00,\r | |
781 | L"iRDA compatible controller",\r | |
782 | PCIBlankEntry\r | |
783 | },\r | |
784 | {\r | |
785 | 0x01,\r | |
f056e4c1 JC |
786 | L"",\r |
787 | PCIPIFClass_0d01\r | |
5d73d92f | 788 | },\r |
789 | {\r | |
790 | 0x10,\r | |
791 | L"RF controller",\r | |
792 | PCIBlankEntry\r | |
793 | },\r | |
f056e4c1 JC |
794 | {\r |
795 | 0x11,\r | |
796 | L"Bluetooth",\r | |
797 | PCIBlankEntry\r | |
798 | },\r | |
799 | {\r | |
800 | 0x12,\r | |
801 | L"Broadband",\r | |
802 | PCIBlankEntry\r | |
803 | },\r | |
804 | {\r | |
805 | 0x20,\r | |
59577231 | 806 | L"Ethernet (802.11a - 5 GHz)",\r |
f056e4c1 JC |
807 | PCIBlankEntry\r |
808 | },\r | |
809 | {\r | |
810 | 0x21,\r | |
59577231 | 811 | L"Ethernet (802.11b - 2.4 GHz)",\r |
f056e4c1 JC |
812 | PCIBlankEntry\r |
813 | },\r | |
5d73d92f | 814 | {\r |
815 | 0x80,\r | |
816 | L"Other type of wireless controller",\r | |
817 | PCIBlankEntry\r | |
818 | },\r | |
819 | {\r | |
820 | 0x00,\r | |
821 | NULL,\r | |
822 | /* null string ends the list */NULL\r | |
823 | }\r | |
824 | };\r | |
825 | \r | |
826 | PCI_CLASS_ENTRY PCISubClass_0e[] = {\r | |
827 | {\r | |
828 | 0x00,\r | |
829 | L"I2O Architecture",\r | |
830 | PCIPIFClass_0e00\r | |
831 | },\r | |
832 | {\r | |
833 | 0x00,\r | |
834 | NULL,\r | |
835 | /* null string ends the list */NULL\r | |
836 | }\r | |
837 | };\r | |
838 | \r | |
839 | PCI_CLASS_ENTRY PCISubClass_0f[] = {\r | |
840 | {\r | |
f056e4c1 | 841 | 0x01,\r |
5d73d92f | 842 | L"TV",\r |
843 | PCIBlankEntry\r | |
844 | },\r | |
845 | {\r | |
f056e4c1 | 846 | 0x02,\r |
5d73d92f | 847 | L"Audio",\r |
848 | PCIBlankEntry\r | |
849 | },\r | |
850 | {\r | |
f056e4c1 | 851 | 0x03,\r |
5d73d92f | 852 | L"Voice",\r |
853 | PCIBlankEntry\r | |
854 | },\r | |
855 | {\r | |
f056e4c1 | 856 | 0x04,\r |
5d73d92f | 857 | L"Data",\r |
858 | PCIBlankEntry\r | |
859 | },\r | |
f056e4c1 JC |
860 | {\r |
861 | 0x80,\r | |
862 | L"Other satellite communication controller",\r | |
863 | PCIBlankEntry\r | |
864 | },\r | |
5d73d92f | 865 | {\r |
866 | 0x00,\r | |
867 | NULL,\r | |
868 | /* null string ends the list */NULL\r | |
869 | }\r | |
870 | };\r | |
871 | \r | |
872 | PCI_CLASS_ENTRY PCISubClass_10[] = {\r | |
873 | {\r | |
874 | 0x00,\r | |
875 | L"Network & computing Encrypt/Decrypt",\r | |
876 | PCIBlankEntry\r | |
877 | },\r | |
878 | {\r | |
879 | 0x01,\r | |
880 | L"Entertainment Encrypt/Decrypt",\r | |
881 | PCIBlankEntry\r | |
882 | },\r | |
883 | {\r | |
884 | 0x80,\r | |
885 | L"Other Encrypt/Decrypt",\r | |
886 | PCIBlankEntry\r | |
887 | },\r | |
888 | {\r | |
889 | 0x00,\r | |
890 | NULL,\r | |
891 | /* null string ends the list */NULL\r | |
892 | }\r | |
893 | };\r | |
894 | \r | |
895 | PCI_CLASS_ENTRY PCISubClass_11[] = {\r | |
896 | {\r | |
897 | 0x00,\r | |
898 | L"DPIO modules",\r | |
899 | PCIBlankEntry\r | |
900 | },\r | |
f056e4c1 JC |
901 | {\r |
902 | 0x01,\r | |
903 | L"Performance Counters",\r | |
904 | PCIBlankEntry\r | |
905 | },\r | |
906 | {\r | |
907 | 0x10,\r | |
908 | L"Communications synchronization plus time and frequency test/measurement ",\r | |
909 | PCIBlankEntry\r | |
910 | },\r | |
911 | {\r | |
912 | 0x20,\r | |
913 | L"Management card",\r | |
914 | PCIBlankEntry\r | |
915 | },\r | |
5d73d92f | 916 | {\r |
917 | 0x80,\r | |
918 | L"Other DAQ & SP controllers",\r | |
919 | PCIBlankEntry\r | |
920 | },\r | |
921 | {\r | |
922 | 0x00,\r | |
923 | NULL,\r | |
924 | /* null string ends the list */NULL\r | |
925 | }\r | |
926 | };\r | |
927 | \r | |
f056e4c1 JC |
928 | PCI_CLASS_ENTRY PCISubClass_12[] = {\r |
929 | {\r | |
930 | 0x00,\r | |
931 | L"Processing Accelerator",\r | |
932 | PCIBlankEntry\r | |
933 | },\r | |
934 | {\r | |
935 | 0x00,\r | |
936 | NULL,\r | |
937 | /* null string ends the list */NULL\r | |
938 | }\r | |
939 | };\r | |
940 | \r | |
941 | PCI_CLASS_ENTRY PCISubClass_13[] = {\r | |
942 | {\r | |
943 | 0x00,\r | |
944 | L"Non-Essential Instrumentation Function",\r | |
945 | PCIBlankEntry\r | |
946 | },\r | |
947 | {\r | |
948 | 0x00,\r | |
949 | NULL,\r | |
950 | /* null string ends the list */NULL\r | |
951 | }\r | |
952 | };\r | |
953 | \r | |
5d73d92f | 954 | //\r |
955 | // Programming Interface entries\r | |
956 | //\r | |
f056e4c1 JC |
957 | PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r |
958 | {\r | |
959 | 0x00,\r | |
960 | L"SCSI controller",\r | |
961 | PCIBlankEntry\r | |
962 | },\r | |
963 | {\r | |
964 | 0x11,\r | |
965 | L"SCSI storage device SOP using PQI",\r | |
966 | PCIBlankEntry\r | |
967 | },\r | |
968 | {\r | |
969 | 0x12,\r | |
970 | L"SCSI controller SOP using PQI",\r | |
971 | PCIBlankEntry\r | |
972 | },\r | |
973 | {\r | |
974 | 0x13,\r | |
975 | L"SCSI storage device and controller SOP using PQI",\r | |
976 | PCIBlankEntry\r | |
977 | },\r | |
978 | {\r | |
979 | 0x21,\r | |
980 | L"SCSI storage device SOP using NVMe",\r | |
981 | PCIBlankEntry\r | |
982 | },\r | |
983 | {\r | |
984 | 0x00,\r | |
985 | NULL,\r | |
986 | /* null string ends the list */NULL\r | |
987 | }\r | |
988 | };\r | |
989 | \r | |
5d73d92f | 990 | PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r |
991 | {\r | |
992 | 0x00,\r | |
993 | L"",\r | |
994 | PCIBlankEntry\r | |
995 | },\r | |
996 | {\r | |
997 | 0x01,\r | |
998 | L"OM-primary",\r | |
999 | PCIBlankEntry\r | |
1000 | },\r | |
1001 | {\r | |
1002 | 0x02,\r | |
1003 | L"PI-primary",\r | |
1004 | PCIBlankEntry\r | |
1005 | },\r | |
1006 | {\r | |
1007 | 0x03,\r | |
1008 | L"OM/PI-primary",\r | |
1009 | PCIBlankEntry\r | |
1010 | },\r | |
1011 | {\r | |
1012 | 0x04,\r | |
1013 | L"OM-secondary",\r | |
1014 | PCIBlankEntry\r | |
1015 | },\r | |
1016 | {\r | |
1017 | 0x05,\r | |
1018 | L"OM-primary, OM-secondary",\r | |
1019 | PCIBlankEntry\r | |
1020 | },\r | |
1021 | {\r | |
1022 | 0x06,\r | |
1023 | L"PI-primary, OM-secondary",\r | |
1024 | PCIBlankEntry\r | |
1025 | },\r | |
1026 | {\r | |
1027 | 0x07,\r | |
1028 | L"OM/PI-primary, OM-secondary",\r | |
1029 | PCIBlankEntry\r | |
1030 | },\r | |
1031 | {\r | |
1032 | 0x08,\r | |
1033 | L"OM-secondary",\r | |
1034 | PCIBlankEntry\r | |
1035 | },\r | |
1036 | {\r | |
1037 | 0x09,\r | |
1038 | L"OM-primary, PI-secondary",\r | |
1039 | PCIBlankEntry\r | |
1040 | },\r | |
1041 | {\r | |
1042 | 0x0a,\r | |
1043 | L"PI-primary, PI-secondary",\r | |
1044 | PCIBlankEntry\r | |
1045 | },\r | |
1046 | {\r | |
1047 | 0x0b,\r | |
1048 | L"OM/PI-primary, PI-secondary",\r | |
1049 | PCIBlankEntry\r | |
1050 | },\r | |
1051 | {\r | |
1052 | 0x0c,\r | |
1053 | L"OM-secondary",\r | |
1054 | PCIBlankEntry\r | |
1055 | },\r | |
1056 | {\r | |
1057 | 0x0d,\r | |
1058 | L"OM-primary, OM/PI-secondary",\r | |
1059 | PCIBlankEntry\r | |
1060 | },\r | |
1061 | {\r | |
1062 | 0x0e,\r | |
1063 | L"PI-primary, OM/PI-secondary",\r | |
1064 | PCIBlankEntry\r | |
1065 | },\r | |
1066 | {\r | |
1067 | 0x0f,\r | |
1068 | L"OM/PI-primary, OM/PI-secondary",\r | |
1069 | PCIBlankEntry\r | |
1070 | },\r | |
1071 | {\r | |
1072 | 0x80,\r | |
1073 | L"Master",\r | |
1074 | PCIBlankEntry\r | |
1075 | },\r | |
1076 | {\r | |
1077 | 0x81,\r | |
1078 | L"Master, OM-primary",\r | |
1079 | PCIBlankEntry\r | |
1080 | },\r | |
1081 | {\r | |
1082 | 0x82,\r | |
1083 | L"Master, PI-primary",\r | |
1084 | PCIBlankEntry\r | |
1085 | },\r | |
1086 | {\r | |
1087 | 0x83,\r | |
1088 | L"Master, OM/PI-primary",\r | |
1089 | PCIBlankEntry\r | |
1090 | },\r | |
1091 | {\r | |
1092 | 0x84,\r | |
1093 | L"Master, OM-secondary",\r | |
1094 | PCIBlankEntry\r | |
1095 | },\r | |
1096 | {\r | |
1097 | 0x85,\r | |
1098 | L"Master, OM-primary, OM-secondary",\r | |
1099 | PCIBlankEntry\r | |
1100 | },\r | |
1101 | {\r | |
1102 | 0x86,\r | |
1103 | L"Master, PI-primary, OM-secondary",\r | |
1104 | PCIBlankEntry\r | |
1105 | },\r | |
1106 | {\r | |
1107 | 0x87,\r | |
1108 | L"Master, OM/PI-primary, OM-secondary",\r | |
1109 | PCIBlankEntry\r | |
1110 | },\r | |
1111 | {\r | |
1112 | 0x88,\r | |
1113 | L"Master, OM-secondary",\r | |
1114 | PCIBlankEntry\r | |
1115 | },\r | |
1116 | {\r | |
1117 | 0x89,\r | |
1118 | L"Master, OM-primary, PI-secondary",\r | |
1119 | PCIBlankEntry\r | |
1120 | },\r | |
1121 | {\r | |
1122 | 0x8a,\r | |
1123 | L"Master, PI-primary, PI-secondary",\r | |
1124 | PCIBlankEntry\r | |
1125 | },\r | |
1126 | {\r | |
1127 | 0x8b,\r | |
1128 | L"Master, OM/PI-primary, PI-secondary",\r | |
1129 | PCIBlankEntry\r | |
1130 | },\r | |
1131 | {\r | |
1132 | 0x8c,\r | |
1133 | L"Master, OM-secondary",\r | |
1134 | PCIBlankEntry\r | |
1135 | },\r | |
1136 | {\r | |
1137 | 0x8d,\r | |
1138 | L"Master, OM-primary, OM/PI-secondary",\r | |
1139 | PCIBlankEntry\r | |
1140 | },\r | |
1141 | {\r | |
1142 | 0x8e,\r | |
1143 | L"Master, PI-primary, OM/PI-secondary",\r | |
1144 | PCIBlankEntry\r | |
1145 | },\r | |
1146 | {\r | |
1147 | 0x8f,\r | |
1148 | L"Master, OM/PI-primary, OM/PI-secondary",\r | |
1149 | PCIBlankEntry\r | |
1150 | },\r | |
1151 | {\r | |
1152 | 0x00,\r | |
1153 | NULL,\r | |
1154 | /* null string ends the list */NULL\r | |
1155 | }\r | |
1156 | };\r | |
1157 | \r | |
f056e4c1 JC |
1158 | PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r |
1159 | {\r | |
1160 | 0x20,\r | |
1161 | L"Single stepping",\r | |
1162 | PCIBlankEntry\r | |
1163 | },\r | |
1164 | {\r | |
1165 | 0x30,\r | |
1166 | L"Continuous operation",\r | |
1167 | PCIBlankEntry\r | |
1168 | },\r | |
1169 | {\r | |
1170 | 0x00,\r | |
1171 | NULL,\r | |
1172 | /* null string ends the list */NULL\r | |
1173 | }\r | |
1174 | };\r | |
1175 | \r | |
1176 | PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r | |
1177 | {\r | |
1178 | 0x00,\r | |
1179 | L"",\r | |
1180 | PCIBlankEntry\r | |
1181 | },\r | |
1182 | {\r | |
1183 | 0x01,\r | |
1184 | L"AHCI",\r | |
1185 | PCIBlankEntry\r | |
1186 | },\r | |
1187 | {\r | |
1188 | 0x02,\r | |
1189 | L"Serial Storage Bus",\r | |
1190 | PCIBlankEntry\r | |
1191 | },\r | |
1192 | {\r | |
1193 | 0x00,\r | |
1194 | NULL,\r | |
1195 | /* null string ends the list */NULL\r | |
1196 | }\r | |
1197 | };\r | |
1198 | \r | |
1199 | PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r | |
1200 | {\r | |
1201 | 0x00,\r | |
1202 | L"",\r | |
1203 | PCIBlankEntry\r | |
1204 | },\r | |
1205 | {\r | |
1206 | 0x01,\r | |
1207 | L"Obsolete",\r | |
1208 | PCIBlankEntry\r | |
1209 | },\r | |
1210 | {\r | |
1211 | 0x00,\r | |
1212 | NULL,\r | |
1213 | /* null string ends the list */NULL\r | |
1214 | }\r | |
1215 | };\r | |
1216 | \r | |
1217 | PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r | |
1218 | {\r | |
1219 | 0x00,\r | |
1220 | L"",\r | |
1221 | PCIBlankEntry\r | |
1222 | },\r | |
1223 | {\r | |
1224 | 0x01,\r | |
1225 | L"NVMHCI",\r | |
1226 | PCIBlankEntry\r | |
1227 | },\r | |
1228 | {\r | |
1229 | 0x02,\r | |
1230 | L"NVM Express",\r | |
1231 | PCIBlankEntry\r | |
1232 | },\r | |
1233 | {\r | |
1234 | 0x00,\r | |
1235 | NULL,\r | |
1236 | /* null string ends the list */NULL\r | |
1237 | }\r | |
1238 | };\r | |
1239 | \r | |
1240 | PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r | |
1241 | {\r | |
1242 | 0x00,\r | |
1243 | L"",\r | |
1244 | PCIBlankEntry\r | |
1245 | },\r | |
1246 | {\r | |
1247 | 0x01,\r | |
1248 | L"UFSHCI",\r | |
1249 | PCIBlankEntry\r | |
1250 | },\r | |
1251 | {\r | |
1252 | 0x00,\r | |
1253 | NULL,\r | |
1254 | /* null string ends the list */NULL\r | |
1255 | }\r | |
1256 | };\r | |
1257 | \r | |
5d73d92f | 1258 | PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r |
1259 | {\r | |
1260 | 0x00,\r | |
1261 | L"VGA compatible",\r | |
1262 | PCIBlankEntry\r | |
1263 | },\r | |
1264 | {\r | |
1265 | 0x01,\r | |
1266 | L"8514 compatible",\r | |
1267 | PCIBlankEntry\r | |
1268 | },\r | |
1269 | {\r | |
1270 | 0x00,\r | |
1271 | NULL,\r | |
1272 | /* null string ends the list */NULL\r | |
1273 | }\r | |
1274 | };\r | |
1275 | \r | |
1276 | PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r | |
1277 | {\r | |
1278 | 0x00,\r | |
1279 | L"",\r | |
1280 | PCIBlankEntry\r | |
1281 | },\r | |
1282 | {\r | |
1283 | 0x01,\r | |
1284 | L"Subtractive decode",\r | |
1285 | PCIBlankEntry\r | |
1286 | },\r | |
1287 | {\r | |
1288 | 0x00,\r | |
1289 | NULL,\r | |
1290 | /* null string ends the list */NULL\r | |
1291 | }\r | |
1292 | };\r | |
1293 | \r | |
f056e4c1 JC |
1294 | PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r |
1295 | {\r | |
1296 | 0x40,\r | |
1297 | L"Primary PCI bus side facing the system host processor",\r | |
1298 | PCIBlankEntry\r | |
1299 | },\r | |
1300 | {\r | |
1301 | 0x80,\r | |
1302 | L"Secondary PCI bus side facing the system host processor",\r | |
1303 | PCIBlankEntry\r | |
1304 | },\r | |
1305 | {\r | |
1306 | 0x00,\r | |
1307 | NULL,\r | |
1308 | /* null string ends the list */NULL\r | |
1309 | }\r | |
1310 | };\r | |
1311 | \r | |
1312 | PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r | |
1313 | {\r | |
1314 | 0x00,\r | |
1315 | L"Custom",\r | |
1316 | PCIBlankEntry\r | |
1317 | },\r | |
1318 | {\r | |
1319 | 0x01,\r | |
1320 | L"ASI-SIG Defined Portal",\r | |
1321 | PCIBlankEntry\r | |
1322 | },\r | |
1323 | {\r | |
1324 | 0x00,\r | |
1325 | NULL,\r | |
1326 | /* null string ends the list */NULL\r | |
1327 | }\r | |
1328 | };\r | |
1329 | \r | |
5d73d92f | 1330 | PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r |
1331 | {\r | |
1332 | 0x00,\r | |
1333 | L"Generic XT-compatible",\r | |
1334 | PCIBlankEntry\r | |
1335 | },\r | |
1336 | {\r | |
1337 | 0x01,\r | |
1338 | L"16450-compatible",\r | |
1339 | PCIBlankEntry\r | |
1340 | },\r | |
1341 | {\r | |
1342 | 0x02,\r | |
1343 | L"16550-compatible",\r | |
1344 | PCIBlankEntry\r | |
1345 | },\r | |
1346 | {\r | |
1347 | 0x03,\r | |
1348 | L"16650-compatible",\r | |
1349 | PCIBlankEntry\r | |
1350 | },\r | |
1351 | {\r | |
1352 | 0x04,\r | |
1353 | L"16750-compatible",\r | |
1354 | PCIBlankEntry\r | |
1355 | },\r | |
1356 | {\r | |
1357 | 0x05,\r | |
1358 | L"16850-compatible",\r | |
1359 | PCIBlankEntry\r | |
1360 | },\r | |
1361 | {\r | |
1362 | 0x06,\r | |
1363 | L"16950-compatible",\r | |
1364 | PCIBlankEntry\r | |
1365 | },\r | |
1366 | {\r | |
1367 | 0x00,\r | |
1368 | NULL,\r | |
1369 | /* null string ends the list */NULL\r | |
1370 | }\r | |
1371 | };\r | |
1372 | \r | |
1373 | PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r | |
1374 | {\r | |
1375 | 0x00,\r | |
1376 | L"",\r | |
1377 | PCIBlankEntry\r | |
1378 | },\r | |
1379 | {\r | |
1380 | 0x01,\r | |
1381 | L"Bi-directional",\r | |
1382 | PCIBlankEntry\r | |
1383 | },\r | |
1384 | {\r | |
1385 | 0x02,\r | |
1386 | L"ECP 1.X-compliant",\r | |
1387 | PCIBlankEntry\r | |
1388 | },\r | |
1389 | {\r | |
1390 | 0x03,\r | |
1391 | L"IEEE 1284",\r | |
1392 | PCIBlankEntry\r | |
1393 | },\r | |
1394 | {\r | |
1395 | 0xfe,\r | |
1396 | L"IEEE 1284 target (not a controller)",\r | |
1397 | PCIBlankEntry\r | |
1398 | },\r | |
1399 | {\r | |
1400 | 0x00,\r | |
1401 | NULL,\r | |
1402 | /* null string ends the list */NULL\r | |
1403 | }\r | |
1404 | };\r | |
1405 | \r | |
1406 | PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r | |
1407 | {\r | |
1408 | 0x00,\r | |
1409 | L"Generic",\r | |
1410 | PCIBlankEntry\r | |
1411 | },\r | |
1412 | {\r | |
1413 | 0x01,\r | |
1414 | L"Hayes-compatible 16450",\r | |
1415 | PCIBlankEntry\r | |
1416 | },\r | |
1417 | {\r | |
1418 | 0x02,\r | |
1419 | L"Hayes-compatible 16550",\r | |
1420 | PCIBlankEntry\r | |
1421 | },\r | |
1422 | {\r | |
1423 | 0x03,\r | |
1424 | L"Hayes-compatible 16650",\r | |
1425 | PCIBlankEntry\r | |
1426 | },\r | |
1427 | {\r | |
1428 | 0x04,\r | |
1429 | L"Hayes-compatible 16750",\r | |
1430 | PCIBlankEntry\r | |
1431 | },\r | |
1432 | {\r | |
1433 | 0x00,\r | |
1434 | NULL,\r | |
1435 | /* null string ends the list */NULL\r | |
1436 | }\r | |
1437 | };\r | |
1438 | \r | |
1439 | PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r | |
1440 | {\r | |
1441 | 0x00,\r | |
1442 | L"Generic 8259",\r | |
1443 | PCIBlankEntry\r | |
1444 | },\r | |
1445 | {\r | |
1446 | 0x01,\r | |
1447 | L"ISA",\r | |
1448 | PCIBlankEntry\r | |
1449 | },\r | |
1450 | {\r | |
1451 | 0x02,\r | |
1452 | L"EISA",\r | |
1453 | PCIBlankEntry\r | |
1454 | },\r | |
1455 | {\r | |
1456 | 0x10,\r | |
1457 | L"IO APIC",\r | |
1458 | PCIBlankEntry\r | |
1459 | },\r | |
1460 | {\r | |
1461 | 0x20,\r | |
1462 | L"IO(x) APIC interrupt controller",\r | |
1463 | PCIBlankEntry\r | |
1464 | },\r | |
1465 | {\r | |
1466 | 0x00,\r | |
1467 | NULL,\r | |
1468 | /* null string ends the list */NULL\r | |
1469 | }\r | |
1470 | };\r | |
1471 | \r | |
1472 | PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r | |
1473 | {\r | |
1474 | 0x00,\r | |
1475 | L"Generic 8237",\r | |
1476 | PCIBlankEntry\r | |
1477 | },\r | |
1478 | {\r | |
1479 | 0x01,\r | |
1480 | L"ISA",\r | |
1481 | PCIBlankEntry\r | |
1482 | },\r | |
1483 | {\r | |
1484 | 0x02,\r | |
1485 | L"EISA",\r | |
1486 | PCIBlankEntry\r | |
1487 | },\r | |
1488 | {\r | |
1489 | 0x00,\r | |
1490 | NULL,\r | |
1491 | /* null string ends the list */NULL\r | |
1492 | }\r | |
1493 | };\r | |
1494 | \r | |
1495 | PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r | |
1496 | {\r | |
1497 | 0x00,\r | |
1498 | L"Generic 8254",\r | |
1499 | PCIBlankEntry\r | |
1500 | },\r | |
1501 | {\r | |
1502 | 0x01,\r | |
1503 | L"ISA",\r | |
1504 | PCIBlankEntry\r | |
1505 | },\r | |
1506 | {\r | |
1507 | 0x02,\r | |
1508 | L"EISA",\r | |
1509 | PCIBlankEntry\r | |
1510 | },\r | |
1511 | {\r | |
1512 | 0x00,\r | |
1513 | NULL,\r | |
1514 | /* null string ends the list */NULL\r | |
1515 | }\r | |
1516 | };\r | |
1517 | \r | |
1518 | PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r | |
1519 | {\r | |
1520 | 0x00,\r | |
1521 | L"Generic",\r | |
1522 | PCIBlankEntry\r | |
1523 | },\r | |
1524 | {\r | |
1525 | 0x01,\r | |
1526 | L"ISA",\r | |
1527 | PCIBlankEntry\r | |
1528 | },\r | |
1529 | {\r | |
1530 | 0x02,\r | |
1531 | L"EISA",\r | |
1532 | PCIBlankEntry\r | |
1533 | },\r | |
1534 | {\r | |
1535 | 0x00,\r | |
1536 | NULL,\r | |
1537 | /* null string ends the list */NULL\r | |
1538 | }\r | |
1539 | };\r | |
1540 | \r | |
1541 | PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r | |
1542 | {\r | |
1543 | 0x00,\r | |
1544 | L"Generic",\r | |
1545 | PCIBlankEntry\r | |
1546 | },\r | |
1547 | {\r | |
1548 | 0x10,\r | |
1549 | L"",\r | |
1550 | PCIBlankEntry\r | |
1551 | },\r | |
1552 | {\r | |
1553 | 0x00,\r | |
1554 | NULL,\r | |
1555 | /* null string ends the list */NULL\r | |
1556 | }\r | |
1557 | };\r | |
1558 | \r | |
1559 | PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r | |
1560 | {\r | |
1561 | 0x00,\r | |
f056e4c1 JC |
1562 | L"",\r |
1563 | PCIBlankEntry\r | |
1564 | },\r | |
1565 | {\r | |
1566 | 0x10,\r | |
1567 | L"Using 1394 OpenHCI spec",\r | |
1568 | PCIBlankEntry\r | |
1569 | },\r | |
1570 | {\r | |
1571 | 0x00,\r | |
1572 | NULL,\r | |
1573 | /* null string ends the list */NULL\r | |
1574 | }\r | |
1575 | };\r | |
1576 | \r | |
1577 | PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r | |
1578 | {\r | |
1579 | 0x00,\r | |
1580 | L"UHCI",\r | |
5d73d92f | 1581 | PCIBlankEntry\r |
1582 | },\r | |
1583 | {\r | |
1584 | 0x10,\r | |
f056e4c1 JC |
1585 | L"OHCI",\r |
1586 | PCIBlankEntry\r | |
1587 | },\r | |
1588 | {\r | |
1589 | 0x20,\r | |
1590 | L"EHCI",\r | |
1591 | PCIBlankEntry\r | |
1592 | },\r | |
1593 | {\r | |
1594 | 0x30,\r | |
1595 | L"xHCI",\r | |
5d73d92f | 1596 | PCIBlankEntry\r |
1597 | },\r | |
1598 | {\r | |
1599 | 0x80,\r | |
1600 | L"No specific programming interface",\r | |
1601 | PCIBlankEntry\r | |
1602 | },\r | |
1603 | {\r | |
1604 | 0xfe,\r | |
1605 | L"(Not Host Controller)",\r | |
1606 | PCIBlankEntry\r | |
1607 | },\r | |
1608 | {\r | |
1609 | 0x00,\r | |
1610 | NULL,\r | |
1611 | /* null string ends the list */NULL\r | |
1612 | }\r | |
1613 | };\r | |
1614 | \r | |
f056e4c1 | 1615 | PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r |
5d73d92f | 1616 | {\r |
1617 | 0x00,\r | |
f056e4c1 JC |
1618 | L"SMIC",\r |
1619 | PCIBlankEntry\r | |
1620 | },\r | |
1621 | {\r | |
1622 | 0x01,\r | |
1623 | L"Keyboard Controller Style",\r | |
1624 | PCIBlankEntry\r | |
1625 | },\r | |
1626 | {\r | |
1627 | 0x02,\r | |
1628 | L"Block Transfer",\r | |
1629 | PCIBlankEntry\r | |
1630 | },\r | |
1631 | {\r | |
1632 | 0x00,\r | |
1633 | NULL,\r | |
1634 | /* null string ends the list */NULL\r | |
1635 | }\r | |
1636 | };\r | |
1637 | \r | |
1638 | PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r | |
1639 | {\r | |
1640 | 0x00,\r | |
1641 | L"Consumer IR controller",\r | |
5d73d92f | 1642 | PCIBlankEntry\r |
1643 | },\r | |
1644 | {\r | |
1645 | 0x10,\r | |
f056e4c1 | 1646 | L"UWB Radio controller",\r |
5d73d92f | 1647 | PCIBlankEntry\r |
1648 | },\r | |
1649 | {\r | |
1650 | 0x00,\r | |
1651 | NULL,\r | |
1652 | /* null string ends the list */NULL\r | |
1653 | }\r | |
1654 | };\r | |
1655 | \r | |
1656 | PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r | |
1657 | {\r | |
1658 | 0x00,\r | |
1659 | L"Message FIFO at offset 40h",\r | |
1660 | PCIBlankEntry\r | |
1661 | },\r | |
1662 | {\r | |
1663 | 0x01,\r | |
1664 | L"",\r | |
1665 | PCIBlankEntry\r | |
1666 | },\r | |
1667 | {\r | |
1668 | 0x00,\r | |
1669 | NULL,\r | |
1670 | /* null string ends the list */NULL\r | |
1671 | }\r | |
1672 | };\r | |
1673 | \r | |
5d73d92f | 1674 | \r |
a1d4bfcc | 1675 | /**\r |
5d73d92f | 1676 | Generates printable Unicode strings that represent PCI device class,\r |
1677 | subclass and programmed I/F based on a value passed to the function.\r | |
1678 | \r | |
a1d4bfcc | 1679 | @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r |
5d73d92f | 1680 | PCI device. The encodings are:\r |
1681 | bits 23:16 - Base Class Code\r | |
1682 | bits 15:8 - Sub-Class Code\r | |
1683 | bits 7:0 - Programming Interface\r | |
4ff7e37b | 1684 | @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r |
5d73d92f | 1685 | printable class strings corresponding to ClassCode. The\r |
1686 | caller must not modify the strings that are pointed by\r | |
1687 | the fields in ClassStrings.\r | |
5d73d92f | 1688 | **/\r |
a1d4bfcc | 1689 | VOID\r |
1690 | PciGetClassStrings (\r | |
1691 | IN UINT32 ClassCode,\r | |
1692 | IN OUT PCI_CLASS_STRINGS *ClassStrings\r | |
1693 | )\r | |
5d73d92f | 1694 | {\r |
1695 | INTN Index;\r | |
1696 | UINT8 Code;\r | |
1697 | PCI_CLASS_ENTRY *CurrentClass;\r | |
1698 | \r | |
1699 | //\r | |
1700 | // Assume no strings found\r | |
1701 | //\r | |
1702 | ClassStrings->BaseClass = L"UNDEFINED";\r | |
1703 | ClassStrings->SubClass = L"UNDEFINED";\r | |
1704 | ClassStrings->PIFClass = L"UNDEFINED";\r | |
1705 | \r | |
1706 | CurrentClass = gClassStringList;\r | |
1707 | Code = (UINT8) (ClassCode >> 16);\r | |
1708 | Index = 0;\r | |
1709 | \r | |
1710 | //\r | |
1711 | // Go through all entries of the base class, until the entry with a matching\r | |
1712 | // base class code is found. If reaches an entry with a null description\r | |
1713 | // text, the last entry is met, which means no text for the base class was\r | |
1714 | // found, so no more action is needed.\r | |
1715 | //\r | |
1716 | while (Code != CurrentClass[Index].Code) {\r | |
1717 | if (NULL == CurrentClass[Index].DescText) {\r | |
1718 | return ;\r | |
1719 | }\r | |
1720 | \r | |
1721 | Index++;\r | |
1722 | }\r | |
1723 | //\r | |
1724 | // A base class was found. Assign description, and check if this class has\r | |
1725 | // sub-class defined. If sub-class defined, no more action is needed,\r | |
1726 | // otherwise, continue to find description for the sub-class code.\r | |
1727 | //\r | |
1728 | ClassStrings->BaseClass = CurrentClass[Index].DescText;\r | |
1729 | if (NULL == CurrentClass[Index].LowerLevelClass) {\r | |
1730 | return ;\r | |
1731 | }\r | |
1732 | //\r | |
1733 | // find Subclass entry\r | |
1734 | //\r | |
1735 | CurrentClass = CurrentClass[Index].LowerLevelClass;\r | |
1736 | Code = (UINT8) (ClassCode >> 8);\r | |
1737 | Index = 0;\r | |
1738 | \r | |
1739 | //\r | |
1740 | // Go through all entries of the sub-class, until the entry with a matching\r | |
1741 | // sub-class code is found. If reaches an entry with a null description\r | |
1742 | // text, the last entry is met, which means no text for the sub-class was\r | |
1743 | // found, so no more action is needed.\r | |
1744 | //\r | |
1745 | while (Code != CurrentClass[Index].Code) {\r | |
1746 | if (NULL == CurrentClass[Index].DescText) {\r | |
1747 | return ;\r | |
1748 | }\r | |
1749 | \r | |
1750 | Index++;\r | |
1751 | }\r | |
1752 | //\r | |
1753 | // A class was found for the sub-class code. Assign description, and check if\r | |
1754 | // this sub-class has programming interface defined. If no, no more action is\r | |
1755 | // needed, otherwise, continue to find description for the programming\r | |
1756 | // interface.\r | |
1757 | //\r | |
1758 | ClassStrings->SubClass = CurrentClass[Index].DescText;\r | |
1759 | if (NULL == CurrentClass[Index].LowerLevelClass) {\r | |
1760 | return ;\r | |
1761 | }\r | |
1762 | //\r | |
1763 | // Find programming interface entry\r | |
1764 | //\r | |
1765 | CurrentClass = CurrentClass[Index].LowerLevelClass;\r | |
1766 | Code = (UINT8) ClassCode;\r | |
1767 | Index = 0;\r | |
1768 | \r | |
1769 | //\r | |
1770 | // Go through all entries of the I/F entries, until the entry with a\r | |
1771 | // matching I/F code is found. If reaches an entry with a null description\r | |
1772 | // text, the last entry is met, which means no text was found, so no more\r | |
1773 | // action is needed.\r | |
1774 | //\r | |
1775 | while (Code != CurrentClass[Index].Code) {\r | |
1776 | if (NULL == CurrentClass[Index].DescText) {\r | |
1777 | return ;\r | |
1778 | }\r | |
1779 | \r | |
1780 | Index++;\r | |
1781 | }\r | |
1782 | //\r | |
1783 | // A class was found for the I/F code. Assign description, done!\r | |
1784 | //\r | |
1785 | ClassStrings->PIFClass = CurrentClass[Index].DescText;\r | |
1786 | return ;\r | |
1787 | }\r | |
1788 | \r | |
a1d4bfcc | 1789 | /**\r |
1790 | Print strings that represent PCI device class, subclass and programmed I/F.\r | |
1791 | \r | |
1792 | @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r | |
e8a57ade | 1793 | configuration space.\r |
a1d4bfcc | 1794 | @param[in] IncludePIF If the printed string should include the programming I/F part\r |
1795 | **/\r | |
5d73d92f | 1796 | VOID\r |
1797 | PciPrintClassCode (\r | |
1798 | IN UINT8 *ClassCodePtr,\r | |
1799 | IN BOOLEAN IncludePIF\r | |
1800 | )\r | |
5d73d92f | 1801 | {\r |
1802 | UINT32 ClassCode;\r | |
1803 | PCI_CLASS_STRINGS ClassStrings;\r | |
5d73d92f | 1804 | \r |
1805 | ClassCode = 0;\r | |
e8a57ade JC |
1806 | ClassCode |= (UINT32)ClassCodePtr[0];\r |
1807 | ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r | |
1808 | ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r | |
5d73d92f | 1809 | \r |
1810 | //\r | |
1811 | // Get name from class code\r | |
1812 | //\r | |
1813 | PciGetClassStrings (ClassCode, &ClassStrings);\r | |
1814 | \r | |
1815 | if (IncludePIF) {\r | |
1816 | //\r | |
c37e0f16 | 1817 | // Print base class, sub class, and programming inferface name\r |
5d73d92f | 1818 | //\r |
c37e0f16 | 1819 | ShellPrintEx (-1, -1, L"%s - %s - %s",\r |
5d73d92f | 1820 | ClassStrings.BaseClass,\r |
1821 | ClassStrings.SubClass,\r | |
1822 | ClassStrings.PIFClass\r | |
1823 | );\r | |
1824 | \r | |
1825 | } else {\r | |
1826 | //\r | |
c37e0f16 | 1827 | // Only print base class and sub class name\r |
5d73d92f | 1828 | //\r |
c37e0f16 | 1829 | ShellPrintEx (-1, -1, L"%s - %s",\r |
5d73d92f | 1830 | ClassStrings.BaseClass,\r |
1831 | ClassStrings.SubClass\r | |
c37e0f16 | 1832 | );\r |
5d73d92f | 1833 | }\r |
1834 | }\r | |
1835 | \r | |
a1d4bfcc | 1836 | /**\r |
1837 | This function finds out the protocol which is in charge of the given\r | |
1838 | segment, and its bus range covers the current bus number. It lookes\r | |
1839 | each instances of RootBridgeIoProtocol handle, until the one meets the\r | |
1840 | criteria is found.\r | |
1841 | \r | |
1842 | @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
1843 | @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
1844 | @param[in] Segment Segment number of device we are dealing with.\r | |
1845 | @param[in] Bus Bus number of device we are dealing with.\r | |
1846 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
1847 | \r | |
1848 | @retval EFI_SUCCESS The command completed successfully.\r | |
1849 | @retval EFI_INVALID_PARAMETER Invalid parameter.\r | |
5d73d92f | 1850 | \r |
a1d4bfcc | 1851 | **/\r |
5d73d92f | 1852 | EFI_STATUS\r |
1853 | PciFindProtocolInterface (\r | |
1854 | IN EFI_HANDLE *HandleBuf,\r | |
1855 | IN UINTN HandleCount,\r | |
1856 | IN UINT16 Segment,\r | |
1857 | IN UINT16 Bus,\r | |
1858 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r | |
1859 | );\r | |
1860 | \r | |
a1d4bfcc | 1861 | /**\r |
1862 | This function gets the protocol interface from the given handle, and\r | |
1863 | obtains its address space descriptors.\r | |
1864 | \r | |
1865 | @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r | |
1866 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
1867 | @param[out] Descriptors Points to the address space descriptors.\r | |
1868 | \r | |
1869 | @retval EFI_SUCCESS The command completed successfully\r | |
1870 | **/\r | |
5d73d92f | 1871 | EFI_STATUS\r |
1872 | PciGetProtocolAndResource (\r | |
1873 | IN EFI_HANDLE Handle,\r | |
1874 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r | |
1875 | OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r | |
1876 | );\r | |
1877 | \r | |
a1d4bfcc | 1878 | /**\r |
1879 | This function get the next bus range of given address space descriptors.\r | |
1880 | It also moves the pointer backward a node, to get prepared to be called\r | |
1881 | again.\r | |
1882 | \r | |
4ff7e37b ED |
1883 | @param[in, out] Descriptors Points to current position of a serial of address space\r |
1884 | descriptors.\r | |
1885 | @param[out] MinBus The lower range of bus number.\r | |
1886 | @param[out] MaxBus The upper range of bus number.\r | |
1887 | @param[out] IsEnd Meet end of the serial of descriptors.\r | |
a1d4bfcc | 1888 | \r |
1889 | @retval EFI_SUCCESS The command completed successfully.\r | |
1890 | **/\r | |
5d73d92f | 1891 | EFI_STATUS\r |
1892 | PciGetNextBusRange (\r | |
1893 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r | |
1894 | OUT UINT16 *MinBus,\r | |
1895 | OUT UINT16 *MaxBus,\r | |
1896 | OUT BOOLEAN *IsEnd\r | |
1897 | );\r | |
1898 | \r | |
a1d4bfcc | 1899 | /**\r |
1900 | Explain the data in PCI configuration space. The part which is common for\r | |
1901 | PCI device and bridge is interpreted in this function. It calls other\r | |
1902 | functions to interpret data unique for device or bridge.\r | |
1903 | \r | |
1904 | @param[in] ConfigSpace Data in PCI configuration space.\r | |
1905 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1906 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
f614ce7e | 1907 | @param[in] EnhancedDump The print format for the dump data.\r |
a1d4bfcc | 1908 | \r |
1909 | @retval EFI_SUCCESS The command completed successfully.\r | |
1910 | **/\r | |
5d73d92f | 1911 | EFI_STATUS\r |
1912 | PciExplainData (\r | |
1913 | IN PCI_CONFIG_SPACE *ConfigSpace,\r | |
1914 | IN UINT64 Address,\r | |
705bffb5 JC |
1915 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r |
1916 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 1917 | );\r |
1918 | \r | |
a1d4bfcc | 1919 | /**\r |
1920 | Explain the device specific part of data in PCI configuration space.\r | |
1921 | \r | |
1922 | @param[in] Device Data in PCI configuration space.\r | |
1923 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1924 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1925 | \r | |
1926 | @retval EFI_SUCCESS The command completed successfully.\r | |
1927 | **/\r | |
5d73d92f | 1928 | EFI_STATUS\r |
1929 | PciExplainDeviceData (\r | |
1930 | IN PCI_DEVICE_HEADER *Device,\r | |
1931 | IN UINT64 Address,\r | |
1932 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
1933 | );\r | |
1934 | \r | |
a1d4bfcc | 1935 | /**\r |
1936 | Explain the bridge specific part of data in PCI configuration space.\r | |
1937 | \r | |
1938 | @param[in] Bridge Bridge specific data region in PCI configuration space.\r | |
1939 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1940 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1941 | \r | |
1942 | @retval EFI_SUCCESS The command completed successfully.\r | |
1943 | **/\r | |
5d73d92f | 1944 | EFI_STATUS\r |
1945 | PciExplainBridgeData (\r | |
a1d4bfcc | 1946 | IN PCI_BRIDGE_HEADER *Bridge,\r |
1947 | IN UINT64 Address,\r | |
1948 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 1949 | );\r |
1950 | \r | |
a1d4bfcc | 1951 | /**\r |
1952 | Explain the Base Address Register(Bar) in PCI configuration space.\r | |
1953 | \r | |
4ff7e37b ED |
1954 | @param[in] Bar Points to the Base Address Register intended to interpret.\r |
1955 | @param[in] Command Points to the register Command.\r | |
1956 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1957 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1958 | @param[in, out] Index The Index.\r | |
a1d4bfcc | 1959 | \r |
1960 | @retval EFI_SUCCESS The command completed successfully.\r | |
1961 | **/\r | |
5d73d92f | 1962 | EFI_STATUS\r |
1963 | PciExplainBar (\r | |
1964 | IN UINT32 *Bar,\r | |
1965 | IN UINT16 *Command,\r | |
1966 | IN UINT64 Address,\r | |
1967 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
1968 | IN OUT UINTN *Index\r | |
1969 | );\r | |
1970 | \r | |
a1d4bfcc | 1971 | /**\r |
1972 | Explain the cardbus specific part of data in PCI configuration space.\r | |
1973 | \r | |
1974 | @param[in] CardBus CardBus specific region of PCI configuration space.\r | |
1975 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1976 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1977 | \r | |
1978 | @retval EFI_SUCCESS The command completed successfully.\r | |
1979 | **/\r | |
5d73d92f | 1980 | EFI_STATUS\r |
1981 | PciExplainCardBusData (\r | |
1982 | IN PCI_CARDBUS_HEADER *CardBus,\r | |
1983 | IN UINT64 Address,\r | |
1984 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
1985 | );\r | |
1986 | \r | |
a1d4bfcc | 1987 | /**\r |
1988 | Explain each meaningful bit of register Status. The definition of Status is\r | |
1989 | slightly different depending on the PCI header type.\r | |
1990 | \r | |
1991 | @param[in] Status Points to the content of register Status.\r | |
1992 | @param[in] MainStatus Indicates if this register is main status(not secondary\r | |
1993 | status).\r | |
1994 | @param[in] HeaderType Header type of this PCI device.\r | |
1995 | \r | |
1996 | @retval EFI_SUCCESS The command completed successfully.\r | |
1997 | **/\r | |
5d73d92f | 1998 | EFI_STATUS\r |
1999 | PciExplainStatus (\r | |
2000 | IN UINT16 *Status,\r | |
2001 | IN BOOLEAN MainStatus,\r | |
2002 | IN PCI_HEADER_TYPE HeaderType\r | |
2003 | );\r | |
2004 | \r | |
a1d4bfcc | 2005 | /**\r |
2006 | Explain each meaningful bit of register Command.\r | |
2007 | \r | |
2008 | @param[in] Command Points to the content of register Command.\r | |
2009 | \r | |
2010 | @retval EFI_SUCCESS The command completed successfully.\r | |
2011 | **/\r | |
5d73d92f | 2012 | EFI_STATUS\r |
2013 | PciExplainCommand (\r | |
2014 | IN UINT16 *Command\r | |
2015 | );\r | |
2016 | \r | |
a1d4bfcc | 2017 | /**\r |
2018 | Explain each meaningful bit of register Bridge Control.\r | |
2019 | \r | |
2020 | @param[in] BridgeControl Points to the content of register Bridge Control.\r | |
2021 | @param[in] HeaderType The headertype.\r | |
2022 | \r | |
2023 | @retval EFI_SUCCESS The command completed successfully.\r | |
2024 | **/\r | |
5d73d92f | 2025 | EFI_STATUS\r |
2026 | PciExplainBridgeControl (\r | |
2027 | IN UINT16 *BridgeControl,\r | |
2028 | IN PCI_HEADER_TYPE HeaderType\r | |
2029 | );\r | |
2030 | \r | |
a1d4bfcc | 2031 | /**\r |
2032 | Print each capability structure.\r | |
2033 | \r | |
f614ce7e SQ |
2034 | @param[in] IoDev The pointer to the deivce.\r |
2035 | @param[in] Address The address to start at.\r | |
2036 | @param[in] CapPtr The offset from the address.\r | |
2037 | @param[in] EnhancedDump The print format for the dump data.\r | |
a1d4bfcc | 2038 | \r |
f614ce7e | 2039 | @retval EFI_SUCCESS The operation was successful.\r |
a1d4bfcc | 2040 | **/\r |
5d73d92f | 2041 | EFI_STATUS\r |
2042 | PciExplainCapabilityStruct (\r | |
2043 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
2044 | IN UINT64 Address,\r | |
705bffb5 JC |
2045 | IN UINT8 CapPtr,\r |
2046 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 2047 | );\r |
2048 | \r | |
a1d4bfcc | 2049 | /**\r |
2050 | Display Pcie device structure.\r | |
2051 | \r | |
f614ce7e SQ |
2052 | @param[in] IoDev The pointer to the root pci protocol.\r |
2053 | @param[in] Address The Address to start at.\r | |
2054 | @param[in] CapabilityPtr The offset from the address to start.\r | |
2055 | @param[in] EnhancedDump The print format for the dump data.\r | |
2056 | \r | |
2057 | @retval EFI_SUCCESS The command completed successfully.\r | |
2058 | @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted. \r | |
a1d4bfcc | 2059 | **/\r |
5d73d92f | 2060 | EFI_STATUS\r |
2061 | PciExplainPciExpress (\r | |
2062 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
2063 | IN UINT64 Address,\r | |
705bffb5 JC |
2064 | IN UINT8 CapabilityPtr,\r |
2065 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 2066 | );\r |
2067 | \r | |
a1d4bfcc | 2068 | /**\r |
2069 | Print out information of the capability information.\r | |
2070 | \r | |
2071 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2072 | \r | |
2073 | @retval EFI_SUCCESS The operation was successful.\r | |
2074 | **/\r | |
5d73d92f | 2075 | EFI_STATUS\r |
2076 | ExplainPcieCapReg (\r | |
2412c297 | 2077 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2078 | );\r |
2079 | \r | |
2080 | /**\r | |
2081 | Print out information of the device capability information.\r | |
2082 | \r | |
2083 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2084 | \r |
a1d4bfcc | 2085 | @retval EFI_SUCCESS The operation was successful.\r |
2086 | **/\r | |
5d73d92f | 2087 | EFI_STATUS\r |
2088 | ExplainPcieDeviceCap (\r | |
2412c297 | 2089 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2090 | );\r |
2091 | \r | |
2092 | /**\r | |
2093 | Print out information of the device control information.\r | |
5d73d92f | 2094 | \r |
a1d4bfcc | 2095 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2096 | \r | |
2097 | @retval EFI_SUCCESS The operation was successful.\r | |
2098 | **/\r | |
5d73d92f | 2099 | EFI_STATUS\r |
2100 | ExplainPcieDeviceControl (\r | |
2412c297 | 2101 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2102 | );\r |
5d73d92f | 2103 | \r |
a1d4bfcc | 2104 | /**\r |
2105 | Print out information of the device status information.\r | |
2106 | \r | |
2107 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2108 | \r | |
2109 | @retval EFI_SUCCESS The operation was successful.\r | |
2110 | **/\r | |
5d73d92f | 2111 | EFI_STATUS\r |
2112 | ExplainPcieDeviceStatus (\r | |
2412c297 | 2113 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2114 | );\r |
2115 | \r | |
2116 | /**\r | |
2117 | Print out information of the device link information.\r | |
2118 | \r | |
2119 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2120 | \r |
a1d4bfcc | 2121 | @retval EFI_SUCCESS The operation was successful.\r |
2122 | **/\r | |
5d73d92f | 2123 | EFI_STATUS\r |
2124 | ExplainPcieLinkCap (\r | |
2412c297 | 2125 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2126 | );\r |
2127 | \r | |
2128 | /**\r | |
2129 | Print out information of the device link control information.\r | |
5d73d92f | 2130 | \r |
a1d4bfcc | 2131 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2132 | \r | |
2133 | @retval EFI_SUCCESS The operation was successful.\r | |
2134 | **/\r | |
5d73d92f | 2135 | EFI_STATUS\r |
2136 | ExplainPcieLinkControl (\r | |
2412c297 | 2137 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2138 | );\r |
5d73d92f | 2139 | \r |
a1d4bfcc | 2140 | /**\r |
2141 | Print out information of the device link status information.\r | |
2142 | \r | |
2143 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2144 | \r | |
2145 | @retval EFI_SUCCESS The operation was successful.\r | |
2146 | **/\r | |
5d73d92f | 2147 | EFI_STATUS\r |
2148 | ExplainPcieLinkStatus (\r | |
2412c297 | 2149 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2150 | );\r |
2151 | \r | |
2152 | /**\r | |
2153 | Print out information of the device slot information.\r | |
2154 | \r | |
2155 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2156 | \r |
a1d4bfcc | 2157 | @retval EFI_SUCCESS The operation was successful.\r |
2158 | **/\r | |
5d73d92f | 2159 | EFI_STATUS\r |
2160 | ExplainPcieSlotCap (\r | |
2412c297 | 2161 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2162 | );\r |
2163 | \r | |
2164 | /**\r | |
2165 | Print out information of the device slot control information.\r | |
5d73d92f | 2166 | \r |
a1d4bfcc | 2167 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2168 | \r | |
2169 | @retval EFI_SUCCESS The operation was successful.\r | |
2170 | **/\r | |
5d73d92f | 2171 | EFI_STATUS\r |
2172 | ExplainPcieSlotControl (\r | |
2412c297 | 2173 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2174 | );\r |
5d73d92f | 2175 | \r |
a1d4bfcc | 2176 | /**\r |
2177 | Print out information of the device slot status information.\r | |
2178 | \r | |
2179 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2180 | \r | |
2181 | @retval EFI_SUCCESS The operation was successful.\r | |
2182 | **/\r | |
5d73d92f | 2183 | EFI_STATUS\r |
2184 | ExplainPcieSlotStatus (\r | |
2412c297 | 2185 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2186 | );\r |
2187 | \r | |
2188 | /**\r | |
2189 | Print out information of the device root information.\r | |
2190 | \r | |
2191 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2192 | \r |
a1d4bfcc | 2193 | @retval EFI_SUCCESS The operation was successful.\r |
2194 | **/\r | |
5d73d92f | 2195 | EFI_STATUS\r |
2196 | ExplainPcieRootControl (\r | |
2412c297 | 2197 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2198 | );\r |
2199 | \r | |
2200 | /**\r | |
2201 | Print out information of the device root capability information.\r | |
5d73d92f | 2202 | \r |
a1d4bfcc | 2203 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2204 | \r | |
2205 | @retval EFI_SUCCESS The operation was successful.\r | |
2206 | **/\r | |
5d73d92f | 2207 | EFI_STATUS\r |
2208 | ExplainPcieRootCap (\r | |
2412c297 | 2209 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2210 | );\r |
5d73d92f | 2211 | \r |
a1d4bfcc | 2212 | /**\r |
2213 | Print out information of the device root status information.\r | |
2214 | \r | |
2215 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2216 | \r | |
2217 | @retval EFI_SUCCESS The operation was successful.\r | |
2218 | **/\r | |
5d73d92f | 2219 | EFI_STATUS\r |
2220 | ExplainPcieRootStatus (\r | |
2412c297 | 2221 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2222 | );\r |
5d73d92f | 2223 | \r |
2412c297 | 2224 | typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STRUCTURE *PciExpressCap);\r |
5d73d92f | 2225 | \r |
2226 | typedef enum {\r | |
2227 | FieldWidthUINT8,\r | |
2228 | FieldWidthUINT16,\r | |
2229 | FieldWidthUINT32\r | |
2230 | } PCIE_CAPREG_FIELD_WIDTH;\r | |
2231 | \r | |
2232 | typedef enum {\r | |
2233 | PcieExplainTypeCommon,\r | |
2234 | PcieExplainTypeDevice,\r | |
2235 | PcieExplainTypeLink,\r | |
2236 | PcieExplainTypeSlot,\r | |
2237 | PcieExplainTypeRoot,\r | |
2238 | PcieExplainTypeMax\r | |
2239 | } PCIE_EXPLAIN_TYPE;\r | |
2240 | \r | |
2241 | typedef struct\r | |
2242 | {\r | |
2243 | UINT16 Token;\r | |
2244 | UINTN Offset;\r | |
2245 | PCIE_CAPREG_FIELD_WIDTH Width;\r | |
2246 | PCIE_EXPLAIN_FUNCTION Func;\r | |
2247 | PCIE_EXPLAIN_TYPE Type;\r | |
2248 | } PCIE_EXPLAIN_STRUCT;\r | |
2249 | \r | |
2250 | PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r | |
2251 | {\r | |
2252 | STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r | |
2253 | 0x00,\r | |
2254 | FieldWidthUINT8,\r | |
2255 | NULL,\r | |
2256 | PcieExplainTypeCommon\r | |
2257 | },\r | |
2258 | {\r | |
2259 | STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r | |
2260 | 0x01,\r | |
2261 | FieldWidthUINT8,\r | |
2262 | NULL,\r | |
2263 | PcieExplainTypeCommon\r | |
2264 | },\r | |
2265 | {\r | |
2266 | STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r | |
2267 | 0x02,\r | |
2268 | FieldWidthUINT16,\r | |
2269 | ExplainPcieCapReg,\r | |
2270 | PcieExplainTypeCommon\r | |
2271 | },\r | |
2272 | {\r | |
2273 | STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r | |
2274 | 0x04,\r | |
2275 | FieldWidthUINT32,\r | |
2276 | ExplainPcieDeviceCap,\r | |
2277 | PcieExplainTypeDevice\r | |
2278 | },\r | |
2279 | {\r | |
2280 | STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r | |
2281 | 0x08,\r | |
2282 | FieldWidthUINT16,\r | |
2283 | ExplainPcieDeviceControl,\r | |
2284 | PcieExplainTypeDevice\r | |
2285 | },\r | |
2286 | {\r | |
2287 | STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r | |
2288 | 0x0a,\r | |
2289 | FieldWidthUINT16,\r | |
2290 | ExplainPcieDeviceStatus,\r | |
2291 | PcieExplainTypeDevice\r | |
2292 | },\r | |
2293 | {\r | |
2294 | STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r | |
2295 | 0x0c,\r | |
2296 | FieldWidthUINT32,\r | |
2297 | ExplainPcieLinkCap,\r | |
2298 | PcieExplainTypeLink\r | |
2299 | },\r | |
2300 | {\r | |
2301 | STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r | |
2302 | 0x10,\r | |
2303 | FieldWidthUINT16,\r | |
2304 | ExplainPcieLinkControl,\r | |
2305 | PcieExplainTypeLink\r | |
2306 | },\r | |
2307 | {\r | |
2308 | STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r | |
2309 | 0x12,\r | |
2310 | FieldWidthUINT16,\r | |
2311 | ExplainPcieLinkStatus,\r | |
2312 | PcieExplainTypeLink\r | |
2313 | },\r | |
2314 | {\r | |
2315 | STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r | |
2316 | 0x14,\r | |
2317 | FieldWidthUINT32,\r | |
2318 | ExplainPcieSlotCap,\r | |
2319 | PcieExplainTypeSlot\r | |
2320 | },\r | |
2321 | {\r | |
2322 | STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r | |
2323 | 0x18,\r | |
2324 | FieldWidthUINT16,\r | |
2325 | ExplainPcieSlotControl,\r | |
2326 | PcieExplainTypeSlot\r | |
2327 | },\r | |
2328 | {\r | |
2329 | STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r | |
2330 | 0x1a,\r | |
2331 | FieldWidthUINT16,\r | |
2332 | ExplainPcieSlotStatus,\r | |
2333 | PcieExplainTypeSlot\r | |
2334 | },\r | |
2335 | {\r | |
2336 | STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r | |
2337 | 0x1c,\r | |
2338 | FieldWidthUINT16,\r | |
2339 | ExplainPcieRootControl,\r | |
2340 | PcieExplainTypeRoot\r | |
2341 | },\r | |
2342 | {\r | |
2343 | STRING_TOKEN (STR_PCIEX_RSVDP),\r | |
2344 | 0x1e,\r | |
2345 | FieldWidthUINT16,\r | |
2346 | ExplainPcieRootCap,\r | |
2347 | PcieExplainTypeRoot\r | |
2348 | },\r | |
2349 | {\r | |
2350 | STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r | |
2351 | 0x20,\r | |
2352 | FieldWidthUINT32,\r | |
2353 | ExplainPcieRootStatus,\r | |
2354 | PcieExplainTypeRoot\r | |
2355 | },\r | |
2356 | {\r | |
2357 | 0,\r | |
2358 | 0,\r | |
2359 | (PCIE_CAPREG_FIELD_WIDTH)0,\r | |
2360 | NULL,\r | |
2361 | PcieExplainTypeMax\r | |
2362 | }\r | |
2363 | };\r | |
2364 | \r | |
2365 | //\r | |
2366 | // Global Variables\r | |
2367 | //\r | |
2368 | PCI_CONFIG_SPACE *mConfigSpace = NULL;\r | |
2369 | STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r | |
2370 | {L"-s", TypeValue},\r | |
2371 | {L"-i", TypeFlag},\r | |
2372 | {NULL, TypeMax}\r | |
2373 | };\r | |
2374 | \r | |
2375 | CHAR16 *DevicePortTypeTable[] = {\r | |
2376 | L"PCI Express Endpoint",\r | |
2377 | L"Legacy PCI Express Endpoint",\r | |
2378 | L"Unknown Type",\r | |
2379 | L"Unknonw Type",\r | |
2380 | L"Root Port of PCI Express Root Complex",\r | |
2381 | L"Upstream Port of PCI Express Switch",\r | |
2382 | L"Downstream Port of PCI Express Switch",\r | |
2383 | L"PCI Express to PCI/PCI-X Bridge",\r | |
2384 | L"PCI/PCI-X to PCI Express Bridge",\r | |
2385 | L"Root Complex Integrated Endpoint",\r | |
2386 | L"Root Complex Event Collector"\r | |
2387 | };\r | |
2388 | \r | |
2389 | CHAR16 *L0sLatencyStrTable[] = {\r | |
2390 | L"Less than 64ns",\r | |
2391 | L"64ns to less than 128ns",\r | |
2392 | L"128ns to less than 256ns",\r | |
2393 | L"256ns to less than 512ns",\r | |
2394 | L"512ns to less than 1us",\r | |
2395 | L"1us to less than 2us",\r | |
2396 | L"2us-4us",\r | |
2397 | L"More than 4us"\r | |
2398 | };\r | |
2399 | \r | |
2400 | CHAR16 *L1LatencyStrTable[] = {\r | |
2401 | L"Less than 1us",\r | |
2402 | L"1us to less than 2us",\r | |
2403 | L"2us to less than 4us",\r | |
2404 | L"4us to less than 8us",\r | |
2405 | L"8us to less than 16us",\r | |
2406 | L"16us to less than 32us",\r | |
2407 | L"32us-64us",\r | |
2408 | L"More than 64us"\r | |
2409 | };\r | |
2410 | \r | |
2411 | CHAR16 *ASPMCtrlStrTable[] = {\r | |
2412 | L"Disabled",\r | |
2413 | L"L0s Entry Enabled",\r | |
2414 | L"L1 Entry Enabled",\r | |
2415 | L"L0s and L1 Entry Enabled"\r | |
2416 | };\r | |
2417 | \r | |
2418 | CHAR16 *SlotPwrLmtScaleTable[] = {\r | |
2419 | L"1.0x",\r | |
2420 | L"0.1x",\r | |
2421 | L"0.01x",\r | |
2422 | L"0.001x"\r | |
2423 | };\r | |
2424 | \r | |
2425 | CHAR16 *IndicatorTable[] = {\r | |
2426 | L"Reserved",\r | |
2427 | L"On",\r | |
2428 | L"Blink",\r | |
2429 | L"Off"\r | |
2430 | };\r | |
2431 | \r | |
2432 | \r | |
a1d4bfcc | 2433 | /**\r |
2434 | Function for 'pci' command.\r | |
2435 | \r | |
2436 | @param[in] ImageHandle Handle to the Image (NULL if Internal).\r | |
2437 | @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r | |
2438 | **/\r | |
5d73d92f | 2439 | SHELL_STATUS\r |
2440 | EFIAPI\r | |
2441 | ShellCommandRunPci (\r | |
2442 | IN EFI_HANDLE ImageHandle,\r | |
2443 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
2444 | )\r | |
2445 | {\r | |
2446 | UINT16 Segment;\r | |
2447 | UINT16 Bus;\r | |
2448 | UINT16 Device;\r | |
2449 | UINT16 Func;\r | |
2450 | UINT64 Address;\r | |
2451 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r | |
2452 | EFI_STATUS Status;\r | |
2453 | PCI_COMMON_HEADER PciHeader;\r | |
2454 | PCI_CONFIG_SPACE ConfigSpace;\r | |
2455 | UINTN ScreenCount;\r | |
2456 | UINTN TempColumn;\r | |
2457 | UINTN ScreenSize;\r | |
2458 | BOOLEAN ExplainData;\r | |
2459 | UINTN Index;\r | |
2460 | UINTN SizeOfHeader;\r | |
2461 | BOOLEAN PrintTitle;\r | |
2462 | UINTN HandleBufSize;\r | |
2463 | EFI_HANDLE *HandleBuf;\r | |
2464 | UINTN HandleCount;\r | |
2465 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r | |
2466 | UINT16 MinBus;\r | |
2467 | UINT16 MaxBus;\r | |
2468 | BOOLEAN IsEnd;\r | |
2469 | LIST_ENTRY *Package;\r | |
2470 | CHAR16 *ProblemParam;\r | |
2471 | SHELL_STATUS ShellStatus;\r | |
5d73d92f | 2472 | CONST CHAR16 *Temp;\r |
6855763e | 2473 | UINT64 RetVal;\r |
705bffb5 | 2474 | UINT16 EnhancedDump;\r |
5d73d92f | 2475 | \r |
2476 | ShellStatus = SHELL_SUCCESS;\r | |
2477 | Status = EFI_SUCCESS;\r | |
2478 | Address = 0;\r | |
5d73d92f | 2479 | IoDev = NULL;\r |
2480 | HandleBuf = NULL;\r | |
2481 | Package = NULL;\r | |
2482 | \r | |
2483 | //\r | |
2484 | // initialize the shell lib (we must be in non-auto-init...)\r | |
2485 | //\r | |
2486 | Status = ShellInitialize();\r | |
2487 | ASSERT_EFI_ERROR(Status);\r | |
2488 | \r | |
2489 | Status = CommandInit();\r | |
2490 | ASSERT_EFI_ERROR(Status);\r | |
2491 | \r | |
2492 | //\r | |
2493 | // parse the command line\r | |
2494 | //\r | |
2495 | Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r | |
2496 | if (EFI_ERROR(Status)) {\r | |
2497 | if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r | |
2498 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r | |
2499 | FreePool(ProblemParam);\r | |
2500 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2501 | } else {\r | |
2502 | ASSERT(FALSE);\r | |
2503 | }\r | |
2504 | } else {\r | |
2505 | \r | |
3737ac2b | 2506 | if (ShellCommandLineGetCount(Package) == 2) {\r |
2507 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r | |
2508 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2509 | goto Done;\r | |
2510 | }\r | |
5d73d92f | 2511 | \r |
3737ac2b | 2512 | if (ShellCommandLineGetCount(Package) > 4) {\r |
2513 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r | |
2514 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2515 | goto Done;\r | |
2516 | }\r | |
2517 | if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r | |
2518 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r | |
2519 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2520 | goto Done;\r | |
2521 | }\r | |
5d73d92f | 2522 | //\r |
2523 | // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r | |
2524 | // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r | |
2525 | // space for handles and call it again.\r | |
2526 | //\r | |
2527 | HandleBufSize = sizeof (EFI_HANDLE);\r | |
3737ac2b | 2528 | HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r |
5d73d92f | 2529 | if (HandleBuf == NULL) {\r |
2530 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r | |
2531 | ShellStatus = SHELL_OUT_OF_RESOURCES;\r | |
2532 | goto Done;\r | |
2533 | }\r | |
2534 | \r | |
2535 | Status = gBS->LocateHandle (\r | |
2536 | ByProtocol,\r | |
2537 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2538 | NULL,\r | |
2539 | &HandleBufSize,\r | |
2540 | HandleBuf\r | |
2541 | );\r | |
2542 | \r | |
2543 | if (Status == EFI_BUFFER_TOO_SMALL) {\r | |
2544 | HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r | |
2545 | if (HandleBuf == NULL) {\r | |
2546 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r | |
2547 | ShellStatus = SHELL_OUT_OF_RESOURCES;\r | |
2548 | goto Done;\r | |
2549 | }\r | |
2550 | \r | |
2551 | Status = gBS->LocateHandle (\r | |
2552 | ByProtocol,\r | |
2553 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2554 | NULL,\r | |
2555 | &HandleBufSize,\r | |
2556 | HandleBuf\r | |
2557 | );\r | |
2558 | }\r | |
2559 | \r | |
2560 | if (EFI_ERROR (Status)) {\r | |
2561 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r | |
2562 | ShellStatus = SHELL_NOT_FOUND;\r | |
2563 | goto Done;\r | |
2564 | }\r | |
2565 | \r | |
2566 | HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r | |
2567 | //\r | |
2568 | // Argument Count == 1(no other argument): enumerate all pci functions\r | |
2569 | //\r | |
3737ac2b | 2570 | if (ShellCommandLineGetCount(Package) == 1) {\r |
5d73d92f | 2571 | gST->ConOut->QueryMode (\r |
2572 | gST->ConOut,\r | |
2573 | gST->ConOut->Mode->Mode,\r | |
2574 | &TempColumn,\r | |
2575 | &ScreenSize\r | |
2576 | );\r | |
2577 | \r | |
2578 | ScreenCount = 0;\r | |
2579 | ScreenSize -= 4;\r | |
2580 | if ((ScreenSize & 1) == 1) {\r | |
2581 | ScreenSize -= 1;\r | |
2582 | }\r | |
2583 | \r | |
2584 | PrintTitle = TRUE;\r | |
2585 | \r | |
2586 | //\r | |
2587 | // For each handle, which decides a segment and a bus number range,\r | |
2588 | // enumerate all devices on it.\r | |
2589 | //\r | |
2590 | for (Index = 0; Index < HandleCount; Index++) {\r | |
2591 | Status = PciGetProtocolAndResource (\r | |
2592 | HandleBuf[Index],\r | |
2593 | &IoDev,\r | |
2594 | &Descriptors\r | |
2595 | );\r | |
2596 | if (EFI_ERROR (Status)) {\r | |
2597 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r | |
2598 | ShellStatus = SHELL_NOT_FOUND;\r | |
2599 | goto Done;\r | |
2600 | }\r | |
2601 | //\r | |
2602 | // No document say it's impossible for a RootBridgeIo protocol handle\r | |
2603 | // to have more than one address space descriptors, so find out every\r | |
2604 | // bus range and for each of them do device enumeration.\r | |
2605 | //\r | |
2606 | while (TRUE) {\r | |
2607 | Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r | |
2608 | \r | |
2609 | if (EFI_ERROR (Status)) {\r | |
2610 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r | |
2611 | ShellStatus = SHELL_NOT_FOUND;\r | |
2612 | goto Done;\r | |
2613 | }\r | |
2614 | \r | |
2615 | if (IsEnd) {\r | |
2616 | break;\r | |
2617 | }\r | |
2618 | \r | |
2619 | for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r | |
2620 | //\r | |
2621 | // For each devices, enumerate all functions it contains\r | |
2622 | //\r | |
2623 | for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r | |
2624 | //\r | |
2625 | // For each function, read its configuration space and print summary\r | |
2626 | //\r | |
2627 | for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r | |
2628 | if (ShellGetExecutionBreakFlag ()) {\r | |
2629 | ShellStatus = SHELL_ABORTED;\r | |
2630 | goto Done;\r | |
2631 | }\r | |
2632 | Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r | |
2633 | IoDev->Pci.Read (\r | |
2634 | IoDev,\r | |
2635 | EfiPciWidthUint16,\r | |
2636 | Address,\r | |
2637 | 1,\r | |
2638 | &PciHeader.VendorId\r | |
2639 | );\r | |
2640 | \r | |
2641 | //\r | |
2642 | // If VendorId = 0xffff, there does not exist a device at this\r | |
2643 | // location. For each device, if there is any function on it,\r | |
2644 | // there must be 1 function at Function 0. So if Func = 0, there\r | |
2645 | // will be no more functions in the same device, so we can break\r | |
2646 | // loop to deal with the next device.\r | |
2647 | //\r | |
2648 | if (PciHeader.VendorId == 0xffff && Func == 0) {\r | |
2649 | break;\r | |
2650 | }\r | |
2651 | \r | |
2652 | if (PciHeader.VendorId != 0xffff) {\r | |
2653 | \r | |
2654 | if (PrintTitle) {\r | |
2655 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r | |
2656 | PrintTitle = FALSE;\r | |
2657 | }\r | |
2658 | \r | |
2659 | IoDev->Pci.Read (\r | |
2660 | IoDev,\r | |
2661 | EfiPciWidthUint32,\r | |
2662 | Address,\r | |
2663 | sizeof (PciHeader) / sizeof (UINT32),\r | |
2664 | &PciHeader\r | |
2665 | );\r | |
2666 | \r | |
2667 | ShellPrintHiiEx(\r | |
2668 | -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r | |
2669 | IoDev->SegmentNumber,\r | |
2670 | Bus,\r | |
2671 | Device,\r | |
2672 | Func\r | |
2673 | );\r | |
2674 | \r | |
2675 | PciPrintClassCode (PciHeader.ClassCode, FALSE);\r | |
2676 | ShellPrintHiiEx(\r | |
2677 | -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r | |
2678 | PciHeader.VendorId,\r | |
2679 | PciHeader.DeviceId,\r | |
2680 | PciHeader.ClassCode[0]\r | |
2681 | );\r | |
2682 | \r | |
2683 | ScreenCount += 2;\r | |
2684 | if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r | |
2685 | //\r | |
2686 | // If ScreenSize == 0 we have the console redirected so don't\r | |
2687 | // block updates\r | |
2688 | //\r | |
2689 | ScreenCount = 0;\r | |
2690 | }\r | |
2691 | //\r | |
2692 | // If this is not a multi-function device, we can leave the loop\r | |
2693 | // to deal with the next device.\r | |
2694 | //\r | |
2695 | if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r | |
2696 | break;\r | |
2697 | }\r | |
2698 | }\r | |
2699 | }\r | |
2700 | }\r | |
2701 | }\r | |
2702 | //\r | |
2703 | // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r | |
2704 | // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r | |
2705 | // devices on all bus, we can leave loop.\r | |
2706 | //\r | |
2707 | if (Descriptors == NULL) {\r | |
2708 | break;\r | |
2709 | }\r | |
2710 | }\r | |
2711 | }\r | |
2712 | \r | |
2713 | Status = EFI_SUCCESS;\r | |
2714 | goto Done;\r | |
2715 | }\r | |
2716 | \r | |
5d73d92f | 2717 | ExplainData = FALSE;\r |
2718 | Segment = 0;\r | |
2719 | Bus = 0;\r | |
2720 | Device = 0;\r | |
2721 | Func = 0;\r | |
2722 | if (ShellCommandLineGetFlag(Package, L"-i")) {\r | |
2723 | ExplainData = TRUE;\r | |
2724 | }\r | |
2725 | \r | |
2726 | Temp = ShellCommandLineGetValue(Package, L"-s");\r | |
2727 | if (Temp != NULL) {\r | |
6855763e CP |
2728 | //\r |
2729 | // Input converted to hexadecimal number.\r | |
2730 | //\r | |
2731 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2732 | Segment = (UINT16) RetVal;\r | |
2733 | } else {\r | |
2734 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r | |
2735 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2736 | goto Done;\r | |
2737 | }\r | |
5d73d92f | 2738 | }\r |
2739 | \r | |
2740 | //\r | |
2741 | // The first Argument(except "-i") is assumed to be Bus number, second\r | |
2742 | // to be Device number, and third to be Func number.\r | |
2743 | //\r | |
2744 | Temp = ShellCommandLineGetRawValue(Package, 1);\r | |
2745 | if (Temp != NULL) {\r | |
6855763e CP |
2746 | //\r |
2747 | // Input converted to hexadecimal number.\r | |
2748 | //\r | |
2749 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2750 | Bus = (UINT16) RetVal;\r | |
2751 | } else {\r | |
2752 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r | |
2753 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2754 | goto Done;\r | |
2755 | }\r | |
2756 | \r | |
5d73d92f | 2757 | if (Bus > MAX_BUS_NUMBER) {\r |
2758 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r | |
2759 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2760 | goto Done;\r | |
2761 | }\r | |
2762 | }\r | |
2763 | Temp = ShellCommandLineGetRawValue(Package, 2);\r | |
2764 | if (Temp != NULL) {\r | |
6855763e CP |
2765 | //\r |
2766 | // Input converted to hexadecimal number.\r | |
2767 | //\r | |
2768 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2769 | Device = (UINT16) RetVal;\r | |
2770 | } else {\r | |
2771 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r | |
2772 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2773 | goto Done;\r | |
2774 | }\r | |
2775 | \r | |
5d73d92f | 2776 | if (Device > MAX_DEVICE_NUMBER){\r |
2777 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r | |
2778 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2779 | goto Done;\r | |
2780 | }\r | |
2781 | }\r | |
2782 | \r | |
2783 | Temp = ShellCommandLineGetRawValue(Package, 3);\r | |
2784 | if (Temp != NULL) {\r | |
6855763e CP |
2785 | //\r |
2786 | // Input converted to hexadecimal number.\r | |
2787 | //\r | |
2788 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2789 | Func = (UINT16) RetVal;\r | |
2790 | } else {\r | |
2791 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r | |
2792 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2793 | goto Done;\r | |
2794 | }\r | |
2795 | \r | |
5d73d92f | 2796 | if (Func > MAX_FUNCTION_NUMBER){\r |
2797 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r | |
2798 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2799 | goto Done;\r | |
2800 | }\r | |
2801 | }\r | |
2802 | \r | |
2803 | //\r | |
2804 | // Find the protocol interface who's in charge of current segment, and its\r | |
2805 | // bus range covers the current bus\r | |
2806 | //\r | |
2807 | Status = PciFindProtocolInterface (\r | |
2808 | HandleBuf,\r | |
2809 | HandleCount,\r | |
2810 | Segment,\r | |
2811 | Bus,\r | |
2812 | &IoDev\r | |
2813 | );\r | |
2814 | \r | |
2815 | if (EFI_ERROR (Status)) {\r | |
2816 | ShellPrintHiiEx(\r | |
2817 | -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r | |
5d73d92f | 2818 | Segment,\r |
2819 | Bus\r | |
2820 | );\r | |
2821 | ShellStatus = SHELL_NOT_FOUND;\r | |
2822 | goto Done;\r | |
2823 | }\r | |
2824 | \r | |
2825 | Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r | |
2826 | Status = IoDev->Pci.Read (\r | |
2827 | IoDev,\r | |
2828 | EfiPciWidthUint8,\r | |
2829 | Address,\r | |
2830 | sizeof (ConfigSpace),\r | |
2831 | &ConfigSpace\r | |
2832 | );\r | |
2833 | \r | |
2834 | if (EFI_ERROR (Status)) {\r | |
2835 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r | |
2836 | ShellStatus = SHELL_ACCESS_DENIED;\r | |
2837 | goto Done;\r | |
2838 | }\r | |
2839 | \r | |
2840 | mConfigSpace = &ConfigSpace;\r | |
2841 | ShellPrintHiiEx(\r | |
2842 | -1,\r | |
2843 | -1,\r | |
2844 | NULL,\r | |
2845 | STRING_TOKEN (STR_PCI_INFO),\r | |
2846 | gShellDebug1HiiHandle,\r | |
2847 | Segment,\r | |
2848 | Bus,\r | |
2849 | Device,\r | |
2850 | Func,\r | |
2851 | Segment,\r | |
2852 | Bus,\r | |
2853 | Device,\r | |
2854 | Func\r | |
2855 | );\r | |
2856 | \r | |
2857 | //\r | |
2858 | // Dump standard header of configuration space\r | |
2859 | //\r | |
2860 | SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r | |
2861 | \r | |
a1d4bfcc | 2862 | DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r |
5d73d92f | 2863 | ShellPrintEx(-1,-1, L"\r\n");\r |
2864 | \r | |
2865 | //\r | |
2866 | // Dump device dependent Part of configuration space\r | |
2867 | //\r | |
a1d4bfcc | 2868 | DumpHex (\r |
5d73d92f | 2869 | 2,\r |
2870 | SizeOfHeader,\r | |
2871 | sizeof (ConfigSpace) - SizeOfHeader,\r | |
2872 | ConfigSpace.Data\r | |
2873 | );\r | |
2874 | \r | |
2875 | //\r | |
2876 | // If "-i" appears in command line, interpret data in configuration space\r | |
2877 | //\r | |
2878 | if (ExplainData) {\r | |
705bffb5 JC |
2879 | EnhancedDump = 0;\r |
2880 | if (ShellCommandLineGetFlag(Package, L"-_e")) {\r | |
2881 | EnhancedDump = 0xFFFF;\r | |
2882 | Temp = ShellCommandLineGetValue(Package, L"-_e");\r | |
2883 | if (Temp != NULL) {\r | |
2884 | EnhancedDump = (UINT16) ShellHexStrToUintn (Temp);\r | |
2885 | }\r | |
2886 | }\r | |
2887 | Status = PciExplainData (&ConfigSpace, Address, IoDev, EnhancedDump);\r | |
5d73d92f | 2888 | }\r |
2889 | }\r | |
2890 | Done:\r | |
2891 | if (HandleBuf != NULL) {\r | |
2892 | FreePool (HandleBuf);\r | |
2893 | }\r | |
2894 | if (Package != NULL) {\r | |
2895 | ShellCommandLineFreeVarList (Package);\r | |
2896 | }\r | |
2897 | mConfigSpace = NULL;\r | |
2898 | return ShellStatus;\r | |
2899 | }\r | |
2900 | \r | |
a1d4bfcc | 2901 | /**\r |
5d73d92f | 2902 | This function finds out the protocol which is in charge of the given\r |
2903 | segment, and its bus range covers the current bus number. It lookes\r | |
2904 | each instances of RootBridgeIoProtocol handle, until the one meets the\r | |
2905 | criteria is found.\r | |
2906 | \r | |
a1d4bfcc | 2907 | @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r |
2908 | @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
2909 | @param[in] Segment Segment number of device we are dealing with.\r | |
2910 | @param[in] Bus Bus number of device we are dealing with.\r | |
2911 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
5d73d92f | 2912 | \r |
a1d4bfcc | 2913 | @retval EFI_SUCCESS The command completed successfully.\r |
2914 | @retval EFI_INVALID_PARAMETER Invalid parameter.\r | |
5d73d92f | 2915 | \r |
2916 | **/\r | |
a1d4bfcc | 2917 | EFI_STATUS\r |
2918 | PciFindProtocolInterface (\r | |
2919 | IN EFI_HANDLE *HandleBuf,\r | |
2920 | IN UINTN HandleCount,\r | |
2921 | IN UINT16 Segment,\r | |
2922 | IN UINT16 Bus,\r | |
2923 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r | |
2924 | )\r | |
5d73d92f | 2925 | {\r |
2926 | UINTN Index;\r | |
2927 | EFI_STATUS Status;\r | |
5d73d92f | 2928 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r |
2929 | UINT16 MinBus;\r | |
2930 | UINT16 MaxBus;\r | |
2931 | BOOLEAN IsEnd;\r | |
2932 | \r | |
5d73d92f | 2933 | //\r |
2934 | // Go through all handles, until the one meets the criteria is found\r | |
2935 | //\r | |
2936 | for (Index = 0; Index < HandleCount; Index++) {\r | |
2937 | Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r | |
2938 | if (EFI_ERROR (Status)) {\r | |
2939 | return Status;\r | |
2940 | }\r | |
2941 | //\r | |
2942 | // When Descriptors == NULL, the Configuration() is not implemented,\r | |
2943 | // so we only check the Segment number\r | |
2944 | //\r | |
2945 | if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r | |
2946 | return EFI_SUCCESS;\r | |
2947 | }\r | |
2948 | \r | |
2949 | if ((*IoDev)->SegmentNumber != Segment) {\r | |
2950 | continue;\r | |
2951 | }\r | |
2952 | \r | |
2953 | while (TRUE) {\r | |
2954 | Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r | |
2955 | if (EFI_ERROR (Status)) {\r | |
2956 | return Status;\r | |
2957 | }\r | |
2958 | \r | |
2959 | if (IsEnd) {\r | |
2960 | break;\r | |
2961 | }\r | |
2962 | \r | |
2963 | if (MinBus <= Bus && MaxBus >= Bus) {\r | |
2c46dd23 | 2964 | return EFI_SUCCESS;\r |
5d73d92f | 2965 | }\r |
2966 | }\r | |
2967 | }\r | |
2968 | \r | |
2c46dd23 | 2969 | return EFI_NOT_FOUND;\r |
5d73d92f | 2970 | }\r |
2971 | \r | |
a1d4bfcc | 2972 | /**\r |
2973 | This function gets the protocol interface from the given handle, and\r | |
2974 | obtains its address space descriptors.\r | |
2975 | \r | |
2976 | @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r | |
2977 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
2978 | @param[out] Descriptors Points to the address space descriptors.\r | |
2979 | \r | |
2980 | @retval EFI_SUCCESS The command completed successfully\r | |
2981 | **/\r | |
5d73d92f | 2982 | EFI_STATUS\r |
2983 | PciGetProtocolAndResource (\r | |
2984 | IN EFI_HANDLE Handle,\r | |
2985 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r | |
2986 | OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r | |
2987 | )\r | |
5d73d92f | 2988 | {\r |
2989 | EFI_STATUS Status;\r | |
2990 | \r | |
2991 | //\r | |
2992 | // Get inferface from protocol\r | |
2993 | //\r | |
2994 | Status = gBS->HandleProtocol (\r | |
2995 | Handle,\r | |
2996 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2997 | (VOID**)IoDev\r | |
2998 | );\r | |
2999 | \r | |
3000 | if (EFI_ERROR (Status)) {\r | |
3001 | return Status;\r | |
3002 | }\r | |
3003 | //\r | |
3004 | // Call Configuration() to get address space descriptors\r | |
3005 | //\r | |
3006 | Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r | |
3007 | if (Status == EFI_UNSUPPORTED) {\r | |
3008 | *Descriptors = NULL;\r | |
3009 | return EFI_SUCCESS;\r | |
3010 | \r | |
3011 | } else {\r | |
3012 | return Status;\r | |
3013 | }\r | |
3014 | }\r | |
3015 | \r | |
a1d4bfcc | 3016 | /**\r |
3017 | This function get the next bus range of given address space descriptors.\r | |
3018 | It also moves the pointer backward a node, to get prepared to be called\r | |
3019 | again.\r | |
3020 | \r | |
4ff7e37b ED |
3021 | @param[in, out] Descriptors Points to current position of a serial of address space\r |
3022 | descriptors.\r | |
3023 | @param[out] MinBus The lower range of bus number.\r | |
3024 | @param[out] MaxBus The upper range of bus number.\r | |
3025 | @param[out] IsEnd Meet end of the serial of descriptors.\r | |
a1d4bfcc | 3026 | \r |
3027 | @retval EFI_SUCCESS The command completed successfully.\r | |
3028 | **/\r | |
5d73d92f | 3029 | EFI_STATUS\r |
3030 | PciGetNextBusRange (\r | |
3031 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r | |
3032 | OUT UINT16 *MinBus,\r | |
3033 | OUT UINT16 *MaxBus,\r | |
3034 | OUT BOOLEAN *IsEnd\r | |
3035 | )\r | |
5d73d92f | 3036 | {\r |
3037 | *IsEnd = FALSE;\r | |
3038 | \r | |
3039 | //\r | |
3040 | // When *Descriptors is NULL, Configuration() is not implemented, so assume\r | |
3041 | // range is 0~PCI_MAX_BUS\r | |
3042 | //\r | |
3043 | if ((*Descriptors) == NULL) {\r | |
3044 | *MinBus = 0;\r | |
3045 | *MaxBus = PCI_MAX_BUS;\r | |
3046 | return EFI_SUCCESS;\r | |
3047 | }\r | |
3048 | //\r | |
3049 | // *Descriptors points to one or more address space descriptors, which\r | |
3050 | // ends with a end tagged descriptor. Examine each of the descriptors,\r | |
3051 | // if a bus typed one is found and its bus range covers bus, this handle\r | |
3052 | // is the handle we are looking for.\r | |
3053 | //\r | |
5d73d92f | 3054 | \r |
3055 | while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r | |
3056 | if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r | |
3057 | *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r | |
3058 | *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r | |
3059 | (*Descriptors)++;\r | |
3737ac2b | 3060 | return (EFI_SUCCESS);\r |
5d73d92f | 3061 | }\r |
3062 | \r | |
3063 | (*Descriptors)++;\r | |
3064 | }\r | |
3065 | \r | |
3737ac2b | 3066 | if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r |
3067 | *IsEnd = TRUE;\r | |
3068 | }\r | |
3069 | \r | |
5d73d92f | 3070 | return EFI_SUCCESS;\r |
3071 | }\r | |
3072 | \r | |
a1d4bfcc | 3073 | /**\r |
5d73d92f | 3074 | Explain the data in PCI configuration space. The part which is common for\r |
3075 | PCI device and bridge is interpreted in this function. It calls other\r | |
3076 | functions to interpret data unique for device or bridge.\r | |
3077 | \r | |
a1d4bfcc | 3078 | @param[in] ConfigSpace Data in PCI configuration space.\r |
3079 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3080 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
f614ce7e | 3081 | @param[in] EnhancedDump The print format for the dump data.\r |
5d73d92f | 3082 | \r |
a1d4bfcc | 3083 | @retval EFI_SUCCESS The command completed successfully.\r |
5d73d92f | 3084 | **/\r |
a1d4bfcc | 3085 | EFI_STATUS\r |
3086 | PciExplainData (\r | |
3087 | IN PCI_CONFIG_SPACE *ConfigSpace,\r | |
3088 | IN UINT64 Address,\r | |
705bffb5 JC |
3089 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r |
3090 | IN CONST UINT16 EnhancedDump\r | |
a1d4bfcc | 3091 | )\r |
5d73d92f | 3092 | {\r |
3093 | PCI_COMMON_HEADER *Common;\r | |
3094 | PCI_HEADER_TYPE HeaderType;\r | |
3095 | EFI_STATUS Status;\r | |
3096 | UINT8 CapPtr;\r | |
3097 | \r | |
3098 | Common = &(ConfigSpace->Common);\r | |
3099 | \r | |
c37e0f16 | 3100 | ShellPrintEx (-1, -1, L"\r\n");\r |
5d73d92f | 3101 | \r |
3102 | //\r | |
3103 | // Print Vendor Id and Device Id\r | |
3104 | //\r | |
3105 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r | |
3106 | INDEX_OF (&(Common->VendorId)),\r | |
3107 | Common->VendorId,\r | |
3108 | INDEX_OF (&(Common->DeviceId)),\r | |
3109 | Common->DeviceId\r | |
3110 | );\r | |
3111 | \r | |
3112 | //\r | |
3113 | // Print register Command\r | |
3114 | //\r | |
3115 | PciExplainCommand (&(Common->Command));\r | |
3116 | \r | |
3117 | //\r | |
3118 | // Print register Status\r | |
3119 | //\r | |
3120 | PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r | |
3121 | \r | |
3122 | //\r | |
3123 | // Print register Revision ID\r | |
3124 | //\r | |
14b5e3fd | 3125 | ShellPrintEx(-1, -1, L"\r\n");\r |
5d73d92f | 3126 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r |
3127 | INDEX_OF (&(Common->RevisionId)),\r | |
3128 | Common->RevisionId\r | |
3129 | );\r | |
3130 | \r | |
3131 | //\r | |
3132 | // Print register BIST\r | |
3133 | //\r | |
a1d4bfcc | 3134 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r |
3135 | if ((Common->Bist & PCI_BIT_7) != 0) {\r | |
3136 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r | |
5d73d92f | 3137 | } else {\r |
3138 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r | |
3139 | }\r | |
3140 | //\r | |
3141 | // Print register Cache Line Size\r | |
3142 | //\r | |
3143 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3144 | STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r | |
3145 | gShellDebug1HiiHandle,\r | |
3146 | INDEX_OF (&(Common->CacheLineSize)),\r | |
3147 | Common->CacheLineSize\r | |
3148 | );\r | |
3149 | \r | |
3150 | //\r | |
3151 | // Print register Latency Timer\r | |
3152 | //\r | |
3153 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3154 | STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r | |
3155 | gShellDebug1HiiHandle,\r | |
3156 | INDEX_OF (&(Common->PrimaryLatencyTimer)),\r | |
3157 | Common->PrimaryLatencyTimer\r | |
3158 | );\r | |
3159 | \r | |
3160 | //\r | |
3161 | // Print register Header Type\r | |
3162 | //\r | |
3163 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3164 | STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r | |
3165 | gShellDebug1HiiHandle,\r | |
3166 | INDEX_OF (&(Common->HeaderType)),\r | |
3167 | Common->HeaderType\r | |
3168 | );\r | |
3169 | \r | |
3170 | if ((Common->HeaderType & PCI_BIT_7) != 0) {\r | |
3171 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r | |
3172 | \r | |
3173 | } else {\r | |
3174 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r | |
3175 | }\r | |
3176 | \r | |
3177 | HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r | |
3178 | switch (HeaderType) {\r | |
3179 | case PciDevice:\r | |
3180 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r | |
3181 | break;\r | |
3182 | \r | |
3183 | case PciP2pBridge:\r | |
3184 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r | |
3185 | break;\r | |
3186 | \r | |
3187 | case PciCardBusBridge:\r | |
3188 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r | |
3189 | break;\r | |
3190 | \r | |
3191 | default:\r | |
3192 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r | |
3193 | HeaderType = PciUndefined;\r | |
3194 | }\r | |
3195 | \r | |
3196 | //\r | |
3197 | // Print register Class Code\r | |
3198 | //\r | |
3199 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r | |
3200 | PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r | |
c37e0f16 | 3201 | ShellPrintEx (-1, -1, L"\r\n");\r |
5d73d92f | 3202 | \r |
3203 | if (ShellGetExecutionBreakFlag()) {\r | |
3204 | return EFI_SUCCESS;\r | |
3205 | }\r | |
3206 | \r | |
3207 | //\r | |
3208 | // Interpret remaining part of PCI configuration header depending on\r | |
3209 | // HeaderType\r | |
3210 | //\r | |
3211 | CapPtr = 0;\r | |
3212 | Status = EFI_SUCCESS;\r | |
3213 | switch (HeaderType) {\r | |
3214 | case PciDevice:\r | |
3215 | Status = PciExplainDeviceData (\r | |
3216 | &(ConfigSpace->NonCommon.Device),\r | |
3217 | Address,\r | |
3218 | IoDev\r | |
3219 | );\r | |
3220 | CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r | |
3221 | break;\r | |
3222 | \r | |
3223 | case PciP2pBridge:\r | |
3224 | Status = PciExplainBridgeData (\r | |
3225 | &(ConfigSpace->NonCommon.Bridge),\r | |
3226 | Address,\r | |
3227 | IoDev\r | |
3228 | );\r | |
3229 | CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r | |
3230 | break;\r | |
3231 | \r | |
3232 | case PciCardBusBridge:\r | |
3233 | Status = PciExplainCardBusData (\r | |
3234 | &(ConfigSpace->NonCommon.CardBus),\r | |
3235 | Address,\r | |
3236 | IoDev\r | |
3237 | );\r | |
3238 | CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r | |
3239 | break;\r | |
d8f8021c | 3240 | case PciUndefined:\r |
3241 | default:\r | |
3242 | break;\r | |
5d73d92f | 3243 | }\r |
3244 | //\r | |
3245 | // If Status bit4 is 1, dump or explain capability structure\r | |
3246 | //\r | |
3247 | if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r | |
705bffb5 | 3248 | PciExplainCapabilityStruct (IoDev, Address, CapPtr, EnhancedDump);\r |
5d73d92f | 3249 | }\r |
3250 | \r | |
3251 | return Status;\r | |
3252 | }\r | |
3253 | \r | |
a1d4bfcc | 3254 | /**\r |
3255 | Explain the device specific part of data in PCI configuration space.\r | |
3256 | \r | |
3257 | @param[in] Device Data in PCI configuration space.\r | |
3258 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3259 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3260 | \r | |
3261 | @retval EFI_SUCCESS The command completed successfully.\r | |
3262 | **/\r | |
5d73d92f | 3263 | EFI_STATUS\r |
3264 | PciExplainDeviceData (\r | |
3265 | IN PCI_DEVICE_HEADER *Device,\r | |
3266 | IN UINT64 Address,\r | |
3267 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
3268 | )\r | |
5d73d92f | 3269 | {\r |
3270 | UINTN Index;\r | |
3271 | BOOLEAN BarExist;\r | |
3272 | EFI_STATUS Status;\r | |
3273 | UINTN BarCount;\r | |
3274 | \r | |
3275 | //\r | |
3276 | // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r | |
3277 | // exist. If these no Bar for this function, print "none", otherwise\r | |
3278 | // list detail information about this Bar.\r | |
3279 | //\r | |
3280 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r | |
3281 | \r | |
3282 | BarExist = FALSE;\r | |
3283 | BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r | |
3284 | for (Index = 0; Index < BarCount; Index++) {\r | |
3285 | if (Device->Bar[Index] == 0) {\r | |
3286 | continue;\r | |
3287 | }\r | |
3288 | \r | |
3289 | if (!BarExist) {\r | |
3290 | BarExist = TRUE;\r | |
3291 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3292 | ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r |
5d73d92f | 3293 | }\r |
3294 | \r | |
3295 | Status = PciExplainBar (\r | |
3296 | &(Device->Bar[Index]),\r | |
3297 | &(mConfigSpace->Common.Command),\r | |
3298 | Address,\r | |
3299 | IoDev,\r | |
3300 | &Index\r | |
3301 | );\r | |
3302 | \r | |
3303 | if (EFI_ERROR (Status)) {\r | |
3304 | break;\r | |
3305 | }\r | |
3306 | }\r | |
3307 | \r | |
3308 | if (!BarExist) {\r | |
3309 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r | |
3310 | \r | |
3311 | } else {\r | |
c37e0f16 | 3312 | ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r |
5d73d92f | 3313 | }\r |
3314 | \r | |
3315 | //\r | |
3316 | // Print register Expansion ROM Base Address\r | |
3317 | //\r | |
3318 | if ((Device->ROMBar & PCI_BIT_0) == 0) {\r | |
3319 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r | |
3320 | \r | |
3321 | } else {\r | |
3322 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3323 | STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r | |
3324 | gShellDebug1HiiHandle,\r | |
3325 | INDEX_OF (&(Device->ROMBar)),\r | |
3326 | Device->ROMBar\r | |
3327 | );\r | |
3328 | }\r | |
3329 | //\r | |
3330 | // Print register Cardbus CIS ptr\r | |
3331 | //\r | |
3332 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3333 | STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r | |
3334 | gShellDebug1HiiHandle,\r | |
3335 | INDEX_OF (&(Device->CardBusCISPtr)),\r | |
3336 | Device->CardBusCISPtr\r | |
3337 | );\r | |
3338 | \r | |
3339 | //\r | |
3340 | // Print register Sub-vendor ID and subsystem ID\r | |
3341 | //\r | |
3342 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3343 | STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r | |
3344 | gShellDebug1HiiHandle,\r | |
3345 | INDEX_OF (&(Device->SubVendorId)),\r | |
3346 | Device->SubVendorId\r | |
3347 | );\r | |
3348 | \r | |
3349 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3350 | STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r | |
3351 | gShellDebug1HiiHandle,\r | |
3352 | INDEX_OF (&(Device->SubSystemId)),\r | |
3353 | Device->SubSystemId\r | |
3354 | );\r | |
3355 | \r | |
3356 | //\r | |
3357 | // Print register Capabilities Ptr\r | |
3358 | //\r | |
3359 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3360 | STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r | |
3361 | gShellDebug1HiiHandle,\r | |
3362 | INDEX_OF (&(Device->CapabilitiesPtr)),\r | |
3363 | Device->CapabilitiesPtr\r | |
3364 | );\r | |
3365 | \r | |
3366 | //\r | |
3367 | // Print register Interrupt Line and interrupt pin\r | |
3368 | //\r | |
3369 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3370 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r | |
3371 | gShellDebug1HiiHandle,\r | |
3372 | INDEX_OF (&(Device->InterruptLine)),\r | |
3373 | Device->InterruptLine\r | |
3374 | );\r | |
3375 | \r | |
3376 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3377 | STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r | |
3378 | gShellDebug1HiiHandle,\r | |
3379 | INDEX_OF (&(Device->InterruptPin)),\r | |
3380 | Device->InterruptPin\r | |
3381 | );\r | |
3382 | \r | |
3383 | //\r | |
3384 | // Print register Min_Gnt and Max_Lat\r | |
3385 | //\r | |
3386 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3387 | STRING_TOKEN (STR_PCI2_MIN_GNT),\r | |
3388 | gShellDebug1HiiHandle,\r | |
3389 | INDEX_OF (&(Device->MinGnt)),\r | |
3390 | Device->MinGnt\r | |
3391 | );\r | |
3392 | \r | |
3393 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3394 | STRING_TOKEN (STR_PCI2_MAX_LAT),\r | |
3395 | gShellDebug1HiiHandle,\r | |
3396 | INDEX_OF (&(Device->MaxLat)),\r | |
3397 | Device->MaxLat\r | |
3398 | );\r | |
3399 | \r | |
3400 | return EFI_SUCCESS;\r | |
3401 | }\r | |
3402 | \r | |
a1d4bfcc | 3403 | /**\r |
3404 | Explain the bridge specific part of data in PCI configuration space.\r | |
3405 | \r | |
3406 | @param[in] Bridge Bridge specific data region in PCI configuration space.\r | |
3407 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3408 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3409 | \r | |
3410 | @retval EFI_SUCCESS The command completed successfully.\r | |
3411 | **/\r | |
5d73d92f | 3412 | EFI_STATUS\r |
3413 | PciExplainBridgeData (\r | |
3414 | IN PCI_BRIDGE_HEADER *Bridge,\r | |
3415 | IN UINT64 Address,\r | |
3416 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
3417 | )\r | |
5d73d92f | 3418 | {\r |
3419 | UINTN Index;\r | |
3420 | BOOLEAN BarExist;\r | |
3421 | UINTN BarCount;\r | |
3422 | UINT32 IoAddress32;\r | |
3423 | EFI_STATUS Status;\r | |
3424 | \r | |
3425 | //\r | |
3426 | // Print Base Address Registers. When Bar = 0, this Bar does not\r | |
3427 | // exist. If these no Bar for this function, print "none", otherwise\r | |
3428 | // list detail information about this Bar.\r | |
3429 | //\r | |
3430 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r | |
3431 | \r | |
3432 | BarExist = FALSE;\r | |
3433 | BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r | |
3434 | \r | |
3435 | for (Index = 0; Index < BarCount; Index++) {\r | |
3436 | if (Bridge->Bar[Index] == 0) {\r | |
3437 | continue;\r | |
3438 | }\r | |
3439 | \r | |
3440 | if (!BarExist) {\r | |
3441 | BarExist = TRUE;\r | |
3442 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3443 | ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r |
5d73d92f | 3444 | }\r |
3445 | \r | |
3446 | Status = PciExplainBar (\r | |
3447 | &(Bridge->Bar[Index]),\r | |
3448 | &(mConfigSpace->Common.Command),\r | |
3449 | Address,\r | |
3450 | IoDev,\r | |
3451 | &Index\r | |
3452 | );\r | |
3453 | \r | |
3454 | if (EFI_ERROR (Status)) {\r | |
3455 | break;\r | |
3456 | }\r | |
3457 | }\r | |
3458 | \r | |
3459 | if (!BarExist) {\r | |
3460 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r | |
3461 | } else {\r | |
c37e0f16 | 3462 | ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r |
5d73d92f | 3463 | }\r |
3464 | \r | |
3465 | //\r | |
3466 | // Expansion register ROM Base Address\r | |
3467 | //\r | |
3468 | if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r | |
3469 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r | |
3470 | \r | |
3471 | } else {\r | |
3472 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3473 | STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r | |
3474 | gShellDebug1HiiHandle,\r | |
3475 | INDEX_OF (&(Bridge->ROMBar)),\r | |
3476 | Bridge->ROMBar\r | |
3477 | );\r | |
3478 | }\r | |
3479 | //\r | |
3480 | // Print Bus Numbers(Primary, Secondary, and Subordinate\r | |
3481 | //\r | |
3482 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3483 | STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r | |
3484 | gShellDebug1HiiHandle,\r | |
3485 | INDEX_OF (&(Bridge->PrimaryBus)),\r | |
3486 | INDEX_OF (&(Bridge->SecondaryBus)),\r | |
3487 | INDEX_OF (&(Bridge->SubordinateBus))\r | |
3488 | );\r | |
3489 | \r | |
c37e0f16 | 3490 | ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r |
5d73d92f | 3491 | \r |
3492 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r | |
3493 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r | |
3494 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r | |
3495 | \r | |
3496 | //\r | |
3497 | // Print register Secondary Latency Timer\r | |
3498 | //\r | |
3499 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3500 | STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r | |
3501 | gShellDebug1HiiHandle,\r | |
3502 | INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r | |
3503 | Bridge->SecondaryLatencyTimer\r | |
3504 | );\r | |
3505 | \r | |
3506 | //\r | |
3507 | // Print register Secondary Status\r | |
3508 | //\r | |
3509 | PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r | |
3510 | \r | |
3511 | //\r | |
3512 | // Print I/O and memory ranges this bridge forwards. There are 3 resource\r | |
3513 | // types: I/O, memory, and pre-fetchable memory. For each resource type,\r | |
3514 | // base and limit address are listed.\r | |
3515 | //\r | |
3516 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3517 | ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r |
5d73d92f | 3518 | \r |
3519 | //\r | |
3520 | // IO Base & Limit\r | |
3521 | //\r | |
3522 | IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r | |
3523 | IoAddress32 &= 0xfffff000;\r | |
3524 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3525 | STRING_TOKEN (STR_PCI2_TWO_VARS),\r | |
3526 | gShellDebug1HiiHandle,\r | |
3527 | INDEX_OF (&(Bridge->IoBase)),\r | |
3528 | IoAddress32\r | |
3529 | );\r | |
3530 | \r | |
3531 | IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r | |
3532 | IoAddress32 |= 0x00000fff;\r | |
3533 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r | |
3534 | \r | |
3535 | //\r | |
3536 | // Memory Base & Limit\r | |
3537 | //\r | |
3538 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3539 | STRING_TOKEN (STR_PCI2_MEMORY),\r | |
3540 | gShellDebug1HiiHandle,\r | |
3541 | INDEX_OF (&(Bridge->MemoryBase)),\r | |
3542 | (Bridge->MemoryBase << 16) & 0xfff00000\r | |
3543 | );\r | |
3544 | \r | |
3545 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3546 | STRING_TOKEN (STR_PCI2_ONE_VAR),\r | |
3547 | gShellDebug1HiiHandle,\r | |
3548 | (Bridge->MemoryLimit << 16) | 0x000fffff\r | |
3549 | );\r | |
3550 | \r | |
3551 | //\r | |
3552 | // Pre-fetch-able Memory Base & Limit\r | |
3553 | //\r | |
3554 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3555 | STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r | |
3556 | gShellDebug1HiiHandle,\r | |
3557 | INDEX_OF (&(Bridge->PrefetchableMemBase)),\r | |
3558 | Bridge->PrefetchableBaseUpper,\r | |
3559 | (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r | |
3560 | );\r | |
3561 | \r | |
3562 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3563 | STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r | |
3564 | gShellDebug1HiiHandle,\r | |
3565 | Bridge->PrefetchableLimitUpper,\r | |
3566 | (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r | |
3567 | );\r | |
3568 | \r | |
3569 | //\r | |
3570 | // Print register Capabilities Pointer\r | |
3571 | //\r | |
3572 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3573 | STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r | |
3574 | gShellDebug1HiiHandle,\r | |
3575 | INDEX_OF (&(Bridge->CapabilitiesPtr)),\r | |
3576 | Bridge->CapabilitiesPtr\r | |
3577 | );\r | |
3578 | \r | |
3579 | //\r | |
3580 | // Print register Bridge Control\r | |
3581 | //\r | |
3582 | PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r | |
3583 | \r | |
3584 | //\r | |
3585 | // Print register Interrupt Line & PIN\r | |
3586 | //\r | |
3587 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3588 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r | |
3589 | gShellDebug1HiiHandle,\r | |
3590 | INDEX_OF (&(Bridge->InterruptLine)),\r | |
3591 | Bridge->InterruptLine\r | |
3592 | );\r | |
3593 | \r | |
3594 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3595 | STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r | |
3596 | gShellDebug1HiiHandle,\r | |
3597 | INDEX_OF (&(Bridge->InterruptPin)),\r | |
3598 | Bridge->InterruptPin\r | |
3599 | );\r | |
3600 | \r | |
3601 | return EFI_SUCCESS;\r | |
3602 | }\r | |
3603 | \r | |
a1d4bfcc | 3604 | /**\r |
3605 | Explain the Base Address Register(Bar) in PCI configuration space.\r | |
3606 | \r | |
4ff7e37b ED |
3607 | @param[in] Bar Points to the Base Address Register intended to interpret.\r |
3608 | @param[in] Command Points to the register Command.\r | |
3609 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3610 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3611 | @param[in, out] Index The Index.\r | |
a1d4bfcc | 3612 | \r |
3613 | @retval EFI_SUCCESS The command completed successfully.\r | |
3614 | **/\r | |
5d73d92f | 3615 | EFI_STATUS\r |
3616 | PciExplainBar (\r | |
3617 | IN UINT32 *Bar,\r | |
3618 | IN UINT16 *Command,\r | |
3619 | IN UINT64 Address,\r | |
3620 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
3621 | IN OUT UINTN *Index\r | |
3622 | )\r | |
5d73d92f | 3623 | {\r |
3624 | UINT16 OldCommand;\r | |
3625 | UINT16 NewCommand;\r | |
3626 | UINT64 Bar64;\r | |
3627 | UINT32 OldBar32;\r | |
3628 | UINT32 NewBar32;\r | |
3629 | UINT64 OldBar64;\r | |
3630 | UINT64 NewBar64;\r | |
3631 | BOOLEAN IsMem;\r | |
3632 | BOOLEAN IsBar32;\r | |
3633 | UINT64 RegAddress;\r | |
3634 | \r | |
3635 | IsBar32 = TRUE;\r | |
3636 | Bar64 = 0;\r | |
3637 | NewBar32 = 0;\r | |
3638 | NewBar64 = 0;\r | |
3639 | \r | |
3640 | //\r | |
3641 | // According the bar type, list detail about this bar, for example: 32 or\r | |
3642 | // 64 bits; pre-fetchable or not.\r | |
3643 | //\r | |
3644 | if ((*Bar & PCI_BIT_0) == 0) {\r | |
3645 | //\r | |
3646 | // This bar is of memory type\r | |
3647 | //\r | |
3648 | IsMem = TRUE;\r | |
3649 | \r | |
3650 | if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r | |
3651 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r | |
3652 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r | |
3653 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r | |
3654 | \r | |
3655 | } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r | |
3656 | Bar64 = 0x0;\r | |
3657 | CopyMem (&Bar64, Bar, sizeof (UINT64));\r | |
46cb4043 | 3658 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r |
2b578de0 | 3659 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r |
5d73d92f | 3660 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r |
3661 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r | |
3662 | IsBar32 = FALSE;\r | |
3663 | *Index += 1;\r | |
3664 | \r | |
3665 | } else {\r | |
3666 | //\r | |
3667 | // Reserved\r | |
3668 | //\r | |
3669 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r | |
3670 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r | |
3671 | }\r | |
3672 | \r | |
3673 | if ((*Bar & PCI_BIT_3) == 0) {\r | |
3674 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r | |
3675 | \r | |
3676 | } else {\r | |
3677 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r | |
3678 | }\r | |
3679 | \r | |
3680 | } else {\r | |
3681 | //\r | |
3682 | // This bar is of io type\r | |
3683 | //\r | |
3684 | IsMem = FALSE;\r | |
3685 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r | |
c37e0f16 | 3686 | ShellPrintEx (-1, -1, L"I/O ");\r |
5d73d92f | 3687 | }\r |
3688 | \r | |
3689 | //\r | |
3690 | // Get BAR length(or the amount of resource this bar demands for). To get\r | |
3691 | // Bar length, first we should temporarily disable I/O and memory access\r | |
3692 | // of this function(by set bits in the register Command), then write all\r | |
3693 | // "1"s to this bar. The bar value read back is the amount of resource\r | |
3694 | // this bar demands for.\r | |
3695 | //\r | |
3696 | //\r | |
3697 | // Disable io & mem access\r | |
3698 | //\r | |
3699 | OldCommand = *Command;\r | |
3700 | NewCommand = (UINT16) (OldCommand & 0xfffc);\r | |
3701 | RegAddress = Address | INDEX_OF (Command);\r | |
3702 | IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r | |
3703 | \r | |
3704 | RegAddress = Address | INDEX_OF (Bar);\r | |
3705 | \r | |
3706 | //\r | |
3707 | // Read after write the BAR to get the size\r | |
3708 | //\r | |
3709 | if (IsBar32) {\r | |
3710 | OldBar32 = *Bar;\r | |
3711 | NewBar32 = 0xffffffff;\r | |
3712 | \r | |
3713 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r | |
3714 | IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r | |
3715 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r | |
3716 | \r | |
3717 | if (IsMem) {\r | |
3718 | NewBar32 = NewBar32 & 0xfffffff0;\r | |
3719 | NewBar32 = (~NewBar32) + 1;\r | |
3720 | \r | |
3721 | } else {\r | |
3722 | NewBar32 = NewBar32 & 0xfffffffc;\r | |
3723 | NewBar32 = (~NewBar32) + 1;\r | |
3724 | NewBar32 = NewBar32 & 0x0000ffff;\r | |
3725 | }\r | |
3726 | } else {\r | |
3727 | \r | |
3728 | OldBar64 = 0x0;\r | |
3729 | CopyMem (&OldBar64, Bar, sizeof (UINT64));\r | |
2b578de0 | 3730 | NewBar64 = 0xffffffffffffffffULL;\r |
5d73d92f | 3731 | \r |
3732 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r | |
3733 | IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r | |
3734 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r | |
3735 | \r | |
3736 | if (IsMem) {\r | |
2b578de0 | 3737 | NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r |
5d73d92f | 3738 | NewBar64 = (~NewBar64) + 1;\r |
3739 | \r | |
3740 | } else {\r | |
2b578de0 | 3741 | NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r |
5d73d92f | 3742 | NewBar64 = (~NewBar64) + 1;\r |
3743 | NewBar64 = NewBar64 & 0x000000000000ffff;\r | |
3744 | }\r | |
3745 | }\r | |
3746 | //\r | |
3747 | // Enable io & mem access\r | |
3748 | //\r | |
3749 | RegAddress = Address | INDEX_OF (Command);\r | |
3750 | IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r | |
3751 | \r | |
3752 | if (IsMem) {\r | |
3753 | if (IsBar32) {\r | |
3754 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r | |
3755 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r | |
3756 | \r | |
3757 | } else {\r | |
46cb4043 | 3758 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r |
5d73d92f | 3759 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r |
c37e0f16 | 3760 | ShellPrintEx (-1, -1, L" ");\r |
5d73d92f | 3761 | ShellPrintHiiEx(-1, -1, NULL,\r |
3762 | STRING_TOKEN (STR_PCI2_RSHIFT),\r | |
3763 | gShellDebug1HiiHandle,\r | |
46cb4043 | 3764 | (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r |
5d73d92f | 3765 | );\r |
2b578de0 | 3766 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r |
5d73d92f | 3767 | \r |
3768 | }\r | |
3769 | } else {\r | |
3770 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r | |
3771 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r | |
3772 | }\r | |
3773 | \r | |
3774 | return EFI_SUCCESS;\r | |
3775 | }\r | |
3776 | \r | |
a1d4bfcc | 3777 | /**\r |
3778 | Explain the cardbus specific part of data in PCI configuration space.\r | |
3779 | \r | |
3780 | @param[in] CardBus CardBus specific region of PCI configuration space.\r | |
3781 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3782 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3783 | \r | |
3784 | @retval EFI_SUCCESS The command completed successfully.\r | |
3785 | **/\r | |
5d73d92f | 3786 | EFI_STATUS\r |
3787 | PciExplainCardBusData (\r | |
3788 | IN PCI_CARDBUS_HEADER *CardBus,\r | |
3789 | IN UINT64 Address,\r | |
3790 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
3791 | )\r | |
5d73d92f | 3792 | {\r |
3793 | BOOLEAN Io32Bit;\r | |
3794 | PCI_CARDBUS_DATA *CardBusData;\r | |
3795 | \r | |
3796 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3797 | STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r | |
3798 | gShellDebug1HiiHandle,\r | |
3799 | INDEX_OF (&(CardBus->CardBusSocketReg)),\r | |
3800 | CardBus->CardBusSocketReg\r | |
3801 | );\r | |
3802 | \r | |
3803 | //\r | |
3804 | // Print Secondary Status\r | |
3805 | //\r | |
3806 | PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r | |
3807 | \r | |
3808 | //\r | |
3809 | // Print Bus Numbers(Primary bus number, CardBus bus number, and\r | |
3810 | // Subordinate bus number\r | |
3811 | //\r | |
3812 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3813 | STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r | |
3814 | gShellDebug1HiiHandle,\r | |
3815 | INDEX_OF (&(CardBus->PciBusNumber)),\r | |
3816 | INDEX_OF (&(CardBus->CardBusBusNumber)),\r | |
3817 | INDEX_OF (&(CardBus->SubordinateBusNumber))\r | |
3818 | );\r | |
3819 | \r | |
c37e0f16 | 3820 | ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r |
5d73d92f | 3821 | \r |
3822 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r | |
3823 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r | |
3824 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r | |
3825 | \r | |
3826 | //\r | |
3827 | // Print CardBus Latency Timer\r | |
3828 | //\r | |
3829 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3830 | STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r | |
3831 | gShellDebug1HiiHandle,\r | |
3832 | INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r | |
3833 | CardBus->CardBusLatencyTimer\r | |
3834 | );\r | |
3835 | \r | |
3836 | //\r | |
3837 | // Print Memory/Io ranges this cardbus bridge forwards\r | |
3838 | //\r | |
3839 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3840 | ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r |
5d73d92f | 3841 | \r |
3842 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3843 | STRING_TOKEN (STR_PCI2_MEM_3),\r | |
3844 | gShellDebug1HiiHandle,\r | |
3845 | INDEX_OF (&(CardBus->MemoryBase0)),\r | |
3846 | CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r | |
3847 | CardBus->MemoryBase0 & 0xfffff000,\r | |
3848 | CardBus->MemoryLimit0 | 0x00000fff\r | |
3849 | );\r | |
3850 | \r | |
3851 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3852 | STRING_TOKEN (STR_PCI2_MEM_3),\r | |
3853 | gShellDebug1HiiHandle,\r | |
3854 | INDEX_OF (&(CardBus->MemoryBase1)),\r | |
3855 | CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r | |
3856 | CardBus->MemoryBase1 & 0xfffff000,\r | |
3857 | CardBus->MemoryLimit1 | 0x00000fff\r | |
3858 | );\r | |
3859 | \r | |
3860 | Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r | |
3861 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3862 | STRING_TOKEN (STR_PCI2_IO_2),\r | |
3863 | gShellDebug1HiiHandle,\r | |
3864 | INDEX_OF (&(CardBus->IoBase0)),\r | |
3865 | Io32Bit ? L" 32 bit" : L" 16 bit",\r | |
3866 | CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r | |
d8f8021c | 3867 | (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r |
5d73d92f | 3868 | );\r |
3869 | \r | |
3870 | Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r | |
3871 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3872 | STRING_TOKEN (STR_PCI2_IO_2),\r | |
3873 | gShellDebug1HiiHandle,\r | |
3874 | INDEX_OF (&(CardBus->IoBase1)),\r | |
3875 | Io32Bit ? L" 32 bit" : L" 16 bit",\r | |
3876 | CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r | |
d8f8021c | 3877 | (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r |
5d73d92f | 3878 | );\r |
3879 | \r | |
3880 | //\r | |
3881 | // Print register Interrupt Line & PIN\r | |
3882 | //\r | |
3883 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3884 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r | |
3885 | gShellDebug1HiiHandle,\r | |
3886 | INDEX_OF (&(CardBus->InterruptLine)),\r | |
3887 | CardBus->InterruptLine,\r | |
3888 | INDEX_OF (&(CardBus->InterruptPin)),\r | |
3889 | CardBus->InterruptPin\r | |
3890 | );\r | |
3891 | \r | |
3892 | //\r | |
3893 | // Print register Bridge Control\r | |
3894 | //\r | |
3895 | PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r | |
3896 | \r | |
3897 | //\r | |
3898 | // Print some registers in data region of PCI configuration space for cardbus\r | |
3899 | // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r | |
3900 | // Address.\r | |
3901 | //\r | |
3902 | CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r | |
3903 | \r | |
3904 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3905 | STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r | |
3906 | gShellDebug1HiiHandle,\r | |
3907 | INDEX_OF (&(CardBusData->SubVendorId)),\r | |
3908 | CardBusData->SubVendorId,\r | |
3909 | INDEX_OF (&(CardBusData->SubSystemId)),\r | |
3910 | CardBusData->SubSystemId\r | |
3911 | );\r | |
3912 | \r | |
3913 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3914 | STRING_TOKEN (STR_PCI2_OPTIONAL),\r | |
3915 | gShellDebug1HiiHandle,\r | |
3916 | INDEX_OF (&(CardBusData->LegacyBase)),\r | |
3917 | CardBusData->LegacyBase\r | |
3918 | );\r | |
3919 | \r | |
3920 | return EFI_SUCCESS;\r | |
3921 | }\r | |
3922 | \r | |
a1d4bfcc | 3923 | /**\r |
3924 | Explain each meaningful bit of register Status. The definition of Status is\r | |
3925 | slightly different depending on the PCI header type.\r | |
3926 | \r | |
3927 | @param[in] Status Points to the content of register Status.\r | |
3928 | @param[in] MainStatus Indicates if this register is main status(not secondary\r | |
3929 | status).\r | |
3930 | @param[in] HeaderType Header type of this PCI device.\r | |
3931 | \r | |
3932 | @retval EFI_SUCCESS The command completed successfully.\r | |
3933 | **/\r | |
5d73d92f | 3934 | EFI_STATUS\r |
3935 | PciExplainStatus (\r | |
3936 | IN UINT16 *Status,\r | |
3937 | IN BOOLEAN MainStatus,\r | |
3938 | IN PCI_HEADER_TYPE HeaderType\r | |
3939 | )\r | |
5d73d92f | 3940 | {\r |
3941 | if (MainStatus) {\r | |
3942 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r | |
3943 | \r | |
3944 | } else {\r | |
3945 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r | |
3946 | }\r | |
3947 | \r | |
3948 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r | |
3949 | \r | |
3950 | //\r | |
3951 | // Bit 5 is meaningless for CardBus Bridge\r | |
3952 | //\r | |
3953 | if (HeaderType == PciCardBusBridge) {\r | |
3954 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r | |
3955 | \r | |
3956 | } else {\r | |
3957 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r | |
3958 | }\r | |
3959 | \r | |
3960 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r | |
3961 | \r | |
3962 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r | |
3963 | //\r | |
3964 | // Bit 9 and bit 10 together decides the DEVSEL timing\r | |
3965 | //\r | |
3966 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r | |
3967 | if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r | |
3968 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r | |
3969 | \r | |
3970 | } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r | |
3971 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r | |
3972 | \r | |
3973 | } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r | |
3974 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r | |
3975 | \r | |
3976 | } else {\r | |
3977 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r | |
3978 | }\r | |
3979 | \r | |
3980 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3981 | STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r | |
3982 | gShellDebug1HiiHandle,\r | |
3983 | (*Status & PCI_BIT_11) != 0\r | |
3984 | );\r | |
3985 | \r | |
3986 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3987 | STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r | |
3988 | gShellDebug1HiiHandle,\r | |
3989 | (*Status & PCI_BIT_12) != 0\r | |
3990 | );\r | |
3991 | \r | |
3992 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3993 | STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r | |
3994 | gShellDebug1HiiHandle,\r | |
3995 | (*Status & PCI_BIT_13) != 0\r | |
3996 | );\r | |
3997 | \r | |
3998 | if (MainStatus) {\r | |
3999 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4000 | STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r | |
4001 | gShellDebug1HiiHandle,\r | |
4002 | (*Status & PCI_BIT_14) != 0\r | |
4003 | );\r | |
4004 | \r | |
4005 | } else {\r | |
4006 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4007 | STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r | |
4008 | gShellDebug1HiiHandle,\r | |
4009 | (*Status & PCI_BIT_14) != 0\r | |
4010 | );\r | |
4011 | }\r | |
4012 | \r | |
4013 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4014 | STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r | |
4015 | gShellDebug1HiiHandle,\r | |
4016 | (*Status & PCI_BIT_15) != 0\r | |
4017 | );\r | |
4018 | \r | |
4019 | return EFI_SUCCESS;\r | |
4020 | }\r | |
4021 | \r | |
a1d4bfcc | 4022 | /**\r |
5d73d92f | 4023 | Explain each meaningful bit of register Command.\r |
4024 | \r | |
a1d4bfcc | 4025 | @param[in] Command Points to the content of register Command.\r |
5d73d92f | 4026 | \r |
a1d4bfcc | 4027 | @retval EFI_SUCCESS The command completed successfully.\r |
5d73d92f | 4028 | **/\r |
a1d4bfcc | 4029 | EFI_STATUS\r |
4030 | PciExplainCommand (\r | |
4031 | IN UINT16 *Command\r | |
4032 | )\r | |
5d73d92f | 4033 | {\r |
4034 | //\r | |
4035 | // Print the binary value of register Command\r | |
4036 | //\r | |
4037 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r | |
4038 | \r | |
4039 | //\r | |
4040 | // Explain register Command bit by bit\r | |
4041 | //\r | |
4042 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4043 | STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r | |
4044 | gShellDebug1HiiHandle,\r | |
4045 | (*Command & PCI_BIT_0) != 0\r | |
4046 | );\r | |
4047 | \r | |
4048 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4049 | STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r | |
4050 | gShellDebug1HiiHandle,\r | |
4051 | (*Command & PCI_BIT_1) != 0\r | |
4052 | );\r | |
4053 | \r | |
4054 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4055 | STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r | |
4056 | gShellDebug1HiiHandle,\r | |
4057 | (*Command & PCI_BIT_2) != 0\r | |
4058 | );\r | |
4059 | \r | |
4060 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4061 | STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r | |
4062 | gShellDebug1HiiHandle,\r | |
4063 | (*Command & PCI_BIT_3) != 0\r | |
4064 | );\r | |
4065 | \r | |
4066 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4067 | STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r | |
4068 | gShellDebug1HiiHandle,\r | |
4069 | (*Command & PCI_BIT_4) != 0\r | |
4070 | );\r | |
4071 | \r | |
4072 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4073 | STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r | |
4074 | gShellDebug1HiiHandle,\r | |
4075 | (*Command & PCI_BIT_5) != 0\r | |
4076 | );\r | |
4077 | \r | |
4078 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4079 | STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r | |
4080 | gShellDebug1HiiHandle,\r | |
4081 | (*Command & PCI_BIT_6) != 0\r | |
4082 | );\r | |
4083 | \r | |
4084 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4085 | STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r | |
4086 | gShellDebug1HiiHandle,\r | |
4087 | (*Command & PCI_BIT_7) != 0\r | |
4088 | );\r | |
4089 | \r | |
4090 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4091 | STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r | |
4092 | gShellDebug1HiiHandle,\r | |
4093 | (*Command & PCI_BIT_8) != 0\r | |
4094 | );\r | |
4095 | \r | |
4096 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4097 | STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r | |
4098 | gShellDebug1HiiHandle,\r | |
4099 | (*Command & PCI_BIT_9) != 0\r | |
4100 | );\r | |
4101 | \r | |
4102 | return EFI_SUCCESS;\r | |
4103 | }\r | |
4104 | \r | |
a1d4bfcc | 4105 | /**\r |
4106 | Explain each meaningful bit of register Bridge Control.\r | |
4107 | \r | |
4108 | @param[in] BridgeControl Points to the content of register Bridge Control.\r | |
4109 | @param[in] HeaderType The headertype.\r | |
4110 | \r | |
4111 | @retval EFI_SUCCESS The command completed successfully.\r | |
4112 | **/\r | |
5d73d92f | 4113 | EFI_STATUS\r |
4114 | PciExplainBridgeControl (\r | |
4115 | IN UINT16 *BridgeControl,\r | |
4116 | IN PCI_HEADER_TYPE HeaderType\r | |
4117 | )\r | |
5d73d92f | 4118 | {\r |
4119 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4120 | STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r | |
4121 | gShellDebug1HiiHandle,\r | |
4122 | INDEX_OF (BridgeControl),\r | |
4123 | *BridgeControl\r | |
4124 | );\r | |
4125 | \r | |
4126 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4127 | STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r | |
4128 | gShellDebug1HiiHandle,\r | |
4129 | (*BridgeControl & PCI_BIT_0) != 0\r | |
4130 | );\r | |
4131 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4132 | STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r | |
4133 | gShellDebug1HiiHandle,\r | |
4134 | (*BridgeControl & PCI_BIT_1) != 0\r | |
4135 | );\r | |
4136 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4137 | STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r | |
4138 | gShellDebug1HiiHandle,\r | |
4139 | (*BridgeControl & PCI_BIT_2) != 0\r | |
4140 | );\r | |
4141 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4142 | STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r | |
4143 | gShellDebug1HiiHandle,\r | |
4144 | (*BridgeControl & PCI_BIT_3) != 0\r | |
4145 | );\r | |
4146 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4147 | STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r | |
4148 | gShellDebug1HiiHandle,\r | |
4149 | (*BridgeControl & PCI_BIT_5) != 0\r | |
4150 | );\r | |
4151 | \r | |
4152 | //\r | |
4153 | // Register Bridge Control has some slight differences between P2P bridge\r | |
4154 | // and Cardbus bridge from bit 6 to bit 11.\r | |
4155 | //\r | |
4156 | if (HeaderType == PciP2pBridge) {\r | |
4157 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4158 | STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r | |
4159 | gShellDebug1HiiHandle,\r | |
4160 | (*BridgeControl & PCI_BIT_6) != 0\r | |
4161 | );\r | |
4162 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4163 | STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r | |
4164 | gShellDebug1HiiHandle,\r | |
4165 | (*BridgeControl & PCI_BIT_7) != 0\r | |
4166 | );\r | |
4167 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4168 | STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r | |
4169 | gShellDebug1HiiHandle,\r | |
4170 | (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r | |
4171 | );\r | |
4172 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4173 | STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r | |
4174 | gShellDebug1HiiHandle,\r | |
4175 | (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r | |
4176 | );\r | |
4177 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4178 | STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r | |
4179 | gShellDebug1HiiHandle,\r | |
4180 | (*BridgeControl & PCI_BIT_10) != 0\r | |
4181 | );\r | |
4182 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4183 | STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r | |
4184 | gShellDebug1HiiHandle,\r | |
4185 | (*BridgeControl & PCI_BIT_11) != 0\r | |
4186 | );\r | |
4187 | \r | |
4188 | } else {\r | |
4189 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4190 | STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r | |
4191 | gShellDebug1HiiHandle,\r | |
4192 | (*BridgeControl & PCI_BIT_6) != 0\r | |
4193 | );\r | |
4194 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4195 | STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r | |
4196 | gShellDebug1HiiHandle,\r | |
4197 | (*BridgeControl & PCI_BIT_7) != 0\r | |
4198 | );\r | |
4199 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4200 | STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r | |
4201 | gShellDebug1HiiHandle,\r | |
4202 | (*BridgeControl & PCI_BIT_10) != 0\r | |
4203 | );\r | |
4204 | }\r | |
4205 | \r | |
4206 | return EFI_SUCCESS;\r | |
4207 | }\r | |
4208 | \r | |
a1d4bfcc | 4209 | /**\r |
4210 | Print each capability structure.\r | |
4211 | \r | |
f614ce7e SQ |
4212 | @param[in] IoDev The pointer to the deivce.\r |
4213 | @param[in] Address The address to start at.\r | |
4214 | @param[in] CapPtr The offset from the address.\r | |
4215 | @param[in] EnhancedDump The print format for the dump data.\r | |
a1d4bfcc | 4216 | \r |
4217 | @retval EFI_SUCCESS The operation was successful.\r | |
4218 | **/\r | |
5d73d92f | 4219 | EFI_STATUS\r |
4220 | PciExplainCapabilityStruct (\r | |
4221 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
4222 | IN UINT64 Address,\r | |
705bffb5 JC |
4223 | IN UINT8 CapPtr,\r |
4224 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 4225 | )\r |
4226 | {\r | |
4227 | UINT8 CapabilityPtr;\r | |
4228 | UINT16 CapabilityEntry;\r | |
4229 | UINT8 CapabilityID;\r | |
4230 | UINT64 RegAddress;\r | |
4231 | \r | |
4232 | CapabilityPtr = CapPtr;\r | |
4233 | \r | |
4234 | //\r | |
4235 | // Go through the Capability list\r | |
4236 | //\r | |
4237 | while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r | |
4238 | RegAddress = Address + CapabilityPtr;\r | |
4239 | IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r | |
4240 | \r | |
4241 | CapabilityID = (UINT8) CapabilityEntry;\r | |
4242 | \r | |
4243 | //\r | |
4244 | // Explain PciExpress data\r | |
4245 | //\r | |
4246 | if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r | |
705bffb5 | 4247 | PciExplainPciExpress (IoDev, Address, CapabilityPtr, EnhancedDump);\r |
5d73d92f | 4248 | return EFI_SUCCESS;\r |
4249 | }\r | |
4250 | //\r | |
4251 | // Explain other capabilities here\r | |
4252 | //\r | |
4253 | CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r | |
4254 | }\r | |
4255 | \r | |
4256 | return EFI_SUCCESS;\r | |
4257 | }\r | |
4258 | \r | |
a1d4bfcc | 4259 | /**\r |
4260 | Print out information of the capability information.\r | |
4261 | \r | |
4262 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4263 | \r | |
4264 | @retval EFI_SUCCESS The operation was successful.\r | |
4265 | **/\r | |
5d73d92f | 4266 | EFI_STATUS\r |
4267 | ExplainPcieCapReg (\r | |
2412c297 | 4268 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4269 | )\r |
5d73d92f | 4270 | {\r |
4271 | UINT16 PcieCapReg;\r | |
4272 | CHAR16 *DevicePortType;\r | |
4273 | \r | |
4274 | PcieCapReg = PciExpressCap->PcieCapReg;\r | |
c37e0f16 CP |
4275 | ShellPrintEx (-1, -1,\r |
4276 | L" Capability Version(3:0): %E0x%04x%N\r\n",\r | |
5d73d92f | 4277 | PCIE_CAP_VERSION (PcieCapReg)\r |
4278 | );\r | |
4279 | if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r | |
4280 | DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r | |
4281 | } else {\r | |
4282 | DevicePortType = L"Unknown Type";\r | |
4283 | }\r | |
c37e0f16 CP |
4284 | ShellPrintEx (-1, -1,\r |
4285 | L" Device/PortType(7:4): %E%s%N\r\n",\r | |
5d73d92f | 4286 | DevicePortType\r |
4287 | );\r | |
4288 | //\r | |
4289 | // 'Slot Implemented' is only valid for:\r | |
4290 | // a) Root Port of PCI Express Root Complex, or\r | |
4291 | // b) Downstream Port of PCI Express Switch\r | |
4292 | //\r | |
4293 | if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r | |
4294 | PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r | |
c37e0f16 CP |
4295 | ShellPrintEx (-1, -1,\r |
4296 | L" Slot Implemented(8): %E%d%N\r\n",\r | |
5d73d92f | 4297 | PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r |
4298 | );\r | |
4299 | }\r | |
c37e0f16 CP |
4300 | ShellPrintEx (-1, -1,\r |
4301 | L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r | |
5d73d92f | 4302 | PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r |
4303 | );\r | |
4304 | return EFI_SUCCESS;\r | |
4305 | }\r | |
4306 | \r | |
a1d4bfcc | 4307 | /**\r |
4308 | Print out information of the device capability information.\r | |
4309 | \r | |
4310 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4311 | \r | |
4312 | @retval EFI_SUCCESS The operation was successful.\r | |
4313 | **/\r | |
5d73d92f | 4314 | EFI_STATUS\r |
4315 | ExplainPcieDeviceCap (\r | |
2412c297 | 4316 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4317 | )\r |
5d73d92f | 4318 | {\r |
4319 | UINT16 PcieCapReg;\r | |
4320 | UINT32 PcieDeviceCap;\r | |
4321 | UINT8 DevicePortType;\r | |
4322 | UINT8 L0sLatency;\r | |
4323 | UINT8 L1Latency;\r | |
4324 | \r | |
4325 | PcieCapReg = PciExpressCap->PcieCapReg;\r | |
4326 | PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r | |
4327 | DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r | |
c37e0f16 | 4328 | ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r |
5d73d92f | 4329 | if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r |
c37e0f16 | 4330 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r |
5d73d92f | 4331 | } else {\r |
c37e0f16 | 4332 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4333 | }\r |
c37e0f16 CP |
4334 | ShellPrintEx (-1, -1,\r |
4335 | L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r | |
5d73d92f | 4336 | PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r |
4337 | );\r | |
c37e0f16 CP |
4338 | ShellPrintEx (-1, -1,\r |
4339 | L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r | |
5d73d92f | 4340 | PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r |
4341 | );\r | |
4342 | //\r | |
4343 | // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r | |
4344 | //\r | |
4345 | if (IS_PCIE_ENDPOINT (DevicePortType)) {\r | |
a1d4bfcc | 4346 | L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r |
4347 | L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r | |
c37e0f16 | 4348 | ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r |
5d73d92f | 4349 | if (L0sLatency < 4) {\r |
c37e0f16 | 4350 | ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r |
5d73d92f | 4351 | } else {\r |
4352 | if (L0sLatency < 7) {\r | |
c37e0f16 | 4353 | ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r |
5d73d92f | 4354 | } else {\r |
c37e0f16 | 4355 | ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r |
5d73d92f | 4356 | }\r |
4357 | }\r | |
c37e0f16 | 4358 | ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r |
5d73d92f | 4359 | if (L1Latency < 7) {\r |
c37e0f16 | 4360 | ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r |
5d73d92f | 4361 | } else {\r |
c37e0f16 | 4362 | ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r |
5d73d92f | 4363 | }\r |
4364 | }\r | |
c37e0f16 CP |
4365 | ShellPrintEx (-1, -1,\r |
4366 | L" Role-based Error Reporting(15): %E%d%N\r\n",\r | |
5d73d92f | 4367 | PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r |
4368 | );\r | |
4369 | //\r | |
4370 | // Only valid for Upstream Port:\r | |
4371 | // a) Captured Slot Power Limit Value\r | |
4372 | // b) Captured Slot Power Scale\r | |
4373 | //\r | |
4374 | if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r | |
c37e0f16 CP |
4375 | ShellPrintEx (-1, -1,\r |
4376 | L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r | |
5d73d92f | 4377 | PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r |
4378 | );\r | |
c37e0f16 CP |
4379 | ShellPrintEx (-1, -1,\r |
4380 | L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r | |
5d73d92f | 4381 | SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r |
4382 | );\r | |
4383 | }\r | |
4384 | //\r | |
4385 | // Function Level Reset Capability is only valid for Endpoint\r | |
4386 | //\r | |
4387 | if (IS_PCIE_ENDPOINT (DevicePortType)) {\r | |
c37e0f16 CP |
4388 | ShellPrintEx (-1, -1,\r |
4389 | L" Function Level Reset Capability(28): %E%d%N\r\n",\r | |
5d73d92f | 4390 | PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r |
4391 | );\r | |
4392 | }\r | |
4393 | return EFI_SUCCESS;\r | |
4394 | }\r | |
4395 | \r | |
a1d4bfcc | 4396 | /**\r |
4397 | Print out information of the device control information.\r | |
4398 | \r | |
4399 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4400 | \r | |
4401 | @retval EFI_SUCCESS The operation was successful.\r | |
4402 | **/\r | |
5d73d92f | 4403 | EFI_STATUS\r |
4404 | ExplainPcieDeviceControl (\r | |
2412c297 | 4405 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4406 | )\r |
5d73d92f | 4407 | {\r |
4408 | UINT16 PcieCapReg;\r | |
4409 | UINT16 PcieDeviceControl;\r | |
4410 | \r | |
4411 | PcieCapReg = PciExpressCap->PcieCapReg;\r | |
4412 | PcieDeviceControl = PciExpressCap->DeviceControl;\r | |
c37e0f16 CP |
4413 | ShellPrintEx (-1, -1,\r |
4414 | L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r | |
5d73d92f | 4415 | PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r |
4416 | );\r | |
c37e0f16 CP |
4417 | ShellPrintEx (-1, -1,\r |
4418 | L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r | |
5d73d92f | 4419 | PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r |
4420 | );\r | |
c37e0f16 CP |
4421 | ShellPrintEx (-1, -1,\r |
4422 | L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r | |
5d73d92f | 4423 | PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r |
4424 | );\r | |
c37e0f16 CP |
4425 | ShellPrintEx (-1, -1,\r |
4426 | L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r | |
5d73d92f | 4427 | PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r |
4428 | );\r | |
c37e0f16 CP |
4429 | ShellPrintEx (-1, -1,\r |
4430 | L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r | |
5d73d92f | 4431 | PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r |
4432 | );\r | |
c37e0f16 | 4433 | ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r |
5d73d92f | 4434 | if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r |
c37e0f16 | 4435 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r |
5d73d92f | 4436 | } else {\r |
c37e0f16 | 4437 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4438 | }\r |
c37e0f16 CP |
4439 | ShellPrintEx (-1, -1,\r |
4440 | L" Extended Tag Field Enable(8): %E%d%N\r\n",\r | |
5d73d92f | 4441 | PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r |
4442 | );\r | |
c37e0f16 CP |
4443 | ShellPrintEx (-1, -1,\r |
4444 | L" Phantom Functions Enable(9): %E%d%N\r\n",\r | |
5d73d92f | 4445 | PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r |
4446 | );\r | |
c37e0f16 CP |
4447 | ShellPrintEx (-1, -1,\r |
4448 | L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r | |
5d73d92f | 4449 | PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r |
4450 | );\r | |
c37e0f16 CP |
4451 | ShellPrintEx (-1, -1,\r |
4452 | L" Enable No Snoop(11): %E%d%N\r\n",\r | |
5d73d92f | 4453 | PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r |
4454 | );\r | |
c37e0f16 | 4455 | ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r |
5d73d92f | 4456 | if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r |
c37e0f16 | 4457 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r |
5d73d92f | 4458 | } else {\r |
c37e0f16 | 4459 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4460 | }\r |
4461 | //\r | |
4462 | // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r | |
4463 | //\r | |
4464 | if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r | |
c37e0f16 CP |
4465 | ShellPrintEx (-1, -1,\r |
4466 | L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r | |
5d73d92f | 4467 | PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r |
4468 | );\r | |
4469 | }\r | |
4470 | return EFI_SUCCESS;\r | |
4471 | }\r | |
4472 | \r | |
a1d4bfcc | 4473 | /**\r |
4474 | Print out information of the device status information.\r | |
4475 | \r | |
4476 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4477 | \r | |
4478 | @retval EFI_SUCCESS The operation was successful.\r | |
4479 | **/\r | |
5d73d92f | 4480 | EFI_STATUS\r |
4481 | ExplainPcieDeviceStatus (\r | |
2412c297 | 4482 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4483 | )\r |
5d73d92f | 4484 | {\r |
4485 | UINT16 PcieDeviceStatus;\r | |
4486 | \r | |
4487 | PcieDeviceStatus = PciExpressCap->DeviceStatus;\r | |
c37e0f16 CP |
4488 | ShellPrintEx (-1, -1,\r |
4489 | L" Correctable Error Detected(0): %E%d%N\r\n",\r | |
5d73d92f | 4490 | PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r |
4491 | );\r | |
c37e0f16 CP |
4492 | ShellPrintEx (-1, -1,\r |
4493 | L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r | |
5d73d92f | 4494 | PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r |
4495 | );\r | |
c37e0f16 CP |
4496 | ShellPrintEx (-1, -1,\r |
4497 | L" Fatal Error Detected(2): %E%d%N\r\n",\r | |
5d73d92f | 4498 | PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r |
4499 | );\r | |
c37e0f16 CP |
4500 | ShellPrintEx (-1, -1,\r |
4501 | L" Unsupported Request Detected(3): %E%d%N\r\n",\r | |
5d73d92f | 4502 | PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r |
4503 | );\r | |
c37e0f16 CP |
4504 | ShellPrintEx (-1, -1,\r |
4505 | L" AUX Power Detected(4): %E%d%N\r\n",\r | |
5d73d92f | 4506 | PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r |
4507 | );\r | |
c37e0f16 CP |
4508 | ShellPrintEx (-1, -1,\r |
4509 | L" Transactions Pending(5): %E%d%N\r\n",\r | |
5d73d92f | 4510 | PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r |
4511 | );\r | |
4512 | return EFI_SUCCESS;\r | |
4513 | }\r | |
4514 | \r | |
a1d4bfcc | 4515 | /**\r |
4516 | Print out information of the device link information.\r | |
4517 | \r | |
4518 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4519 | \r | |
4520 | @retval EFI_SUCCESS The operation was successful.\r | |
4521 | **/\r | |
5d73d92f | 4522 | EFI_STATUS\r |
4523 | ExplainPcieLinkCap (\r | |
2412c297 | 4524 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4525 | )\r |
5d73d92f | 4526 | {\r |
4527 | UINT32 PcieLinkCap;\r | |
541ddf44 | 4528 | CHAR16 *MaxLinkSpeed;\r |
a1d4bfcc | 4529 | CHAR16 *AspmValue;\r |
5d73d92f | 4530 | \r |
4531 | PcieLinkCap = PciExpressCap->LinkCap;\r | |
541ddf44 | 4532 | switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r |
5d73d92f | 4533 | case 1:\r |
541ddf44 | 4534 | MaxLinkSpeed = L"2.5 GT/s";\r |
5d73d92f | 4535 | break;\r |
4536 | case 2:\r | |
541ddf44 CP |
4537 | MaxLinkSpeed = L"5.0 GT/s";\r |
4538 | break;\r | |
4539 | case 3:\r | |
4540 | MaxLinkSpeed = L"8.0 GT/s";\r | |
5d73d92f | 4541 | break;\r |
4542 | default:\r | |
541ddf44 | 4543 | MaxLinkSpeed = L"Unknown";\r |
5d73d92f | 4544 | break;\r |
4545 | }\r | |
c37e0f16 | 4546 | ShellPrintEx (-1, -1,\r |
541ddf44 CP |
4547 | L" Maximum Link Speed(3:0): %E%s%N\r\n",\r |
4548 | MaxLinkSpeed\r | |
5d73d92f | 4549 | );\r |
c37e0f16 CP |
4550 | ShellPrintEx (-1, -1,\r |
4551 | L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r | |
5d73d92f | 4552 | PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r |
4553 | );\r | |
4554 | switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r | |
541ddf44 CP |
4555 | case 0:\r |
4556 | AspmValue = L"Not";\r | |
4557 | break;\r | |
5d73d92f | 4558 | case 1:\r |
541ddf44 CP |
4559 | AspmValue = L"L0s";\r |
4560 | break;\r | |
4561 | case 2:\r | |
4562 | AspmValue = L"L1";\r | |
5d73d92f | 4563 | break;\r |
4564 | case 3:\r | |
a1d4bfcc | 4565 | AspmValue = L"L0s and L1";\r |
5d73d92f | 4566 | break;\r |
4567 | default:\r | |
a1d4bfcc | 4568 | AspmValue = L"Reserved";\r |
5d73d92f | 4569 | break;\r |
4570 | }\r | |
c37e0f16 CP |
4571 | ShellPrintEx (-1, -1,\r |
4572 | L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r | |
a1d4bfcc | 4573 | AspmValue\r |
5d73d92f | 4574 | );\r |
c37e0f16 CP |
4575 | ShellPrintEx (-1, -1,\r |
4576 | L" L0s Exit Latency(14:12): %E%s%N\r\n",\r | |
a1d4bfcc | 4577 | L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r |
5d73d92f | 4578 | );\r |
c37e0f16 CP |
4579 | ShellPrintEx (-1, -1,\r |
4580 | L" L1 Exit Latency(17:15): %E%s%N\r\n",\r | |
a1d4bfcc | 4581 | L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r |
5d73d92f | 4582 | );\r |
c37e0f16 CP |
4583 | ShellPrintEx (-1, -1,\r |
4584 | L" Clock Power Management(18): %E%d%N\r\n",\r | |
5d73d92f | 4585 | PCIE_CAP_CLOCK_PM (PcieLinkCap)\r |
4586 | );\r | |
c37e0f16 CP |
4587 | ShellPrintEx (-1, -1,\r |
4588 | L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r | |
5d73d92f | 4589 | PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r |
4590 | );\r | |
c37e0f16 CP |
4591 | ShellPrintEx (-1, -1,\r |
4592 | L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r | |
5d73d92f | 4593 | PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r |
4594 | );\r | |
c37e0f16 CP |
4595 | ShellPrintEx (-1, -1,\r |
4596 | L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r | |
5d73d92f | 4597 | PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r |
4598 | );\r | |
c37e0f16 CP |
4599 | ShellPrintEx (-1, -1,\r |
4600 | L" Port Number(31:24): %E0x%02x%N\r\n",\r | |
5d73d92f | 4601 | PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r |
4602 | );\r | |
4603 | return EFI_SUCCESS;\r | |
4604 | }\r | |
4605 | \r | |
a1d4bfcc | 4606 | /**\r |
4607 | Print out information of the device link control information.\r | |
4608 | \r | |
4609 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4610 | \r | |
4611 | @retval EFI_SUCCESS The operation was successful.\r | |
4612 | **/\r | |
5d73d92f | 4613 | EFI_STATUS\r |
4614 | ExplainPcieLinkControl (\r | |
2412c297 | 4615 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4616 | )\r |
5d73d92f | 4617 | {\r |
4618 | UINT16 PcieLinkControl;\r | |
4619 | UINT8 DevicePortType;\r | |
4620 | \r | |
4621 | PcieLinkControl = PciExpressCap->LinkControl;\r | |
4622 | DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r | |
c37e0f16 CP |
4623 | ShellPrintEx (-1, -1,\r |
4624 | L" Active State Power Management Control(1:0): %E%s%N\r\n",\r | |
5d73d92f | 4625 | ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r |
4626 | );\r | |
4627 | //\r | |
4628 | // RCB is not applicable to switches\r | |
4629 | //\r | |
4630 | if (!IS_PCIE_SWITCH(DevicePortType)) {\r | |
c37e0f16 CP |
4631 | ShellPrintEx (-1, -1,\r |
4632 | L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r | |
5d73d92f | 4633 | 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r |
4634 | );\r | |
4635 | }\r | |
4636 | //\r | |
4637 | // Link Disable is reserved on\r | |
4638 | // a) Endpoints\r | |
4639 | // b) PCI Express to PCI/PCI-X bridges\r | |
4640 | // c) Upstream Ports of Switches\r | |
4641 | //\r | |
4642 | if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r | |
4643 | DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r | |
4644 | DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r | |
c37e0f16 CP |
4645 | ShellPrintEx (-1, -1,\r |
4646 | L" Link Disable(4): %E%d%N\r\n",\r | |
5d73d92f | 4647 | PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r |
4648 | );\r | |
4649 | }\r | |
c37e0f16 CP |
4650 | ShellPrintEx (-1, -1,\r |
4651 | L" Common Clock Configuration(6): %E%d%N\r\n",\r | |
5d73d92f | 4652 | PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r |
4653 | );\r | |
c37e0f16 CP |
4654 | ShellPrintEx (-1, -1,\r |
4655 | L" Extended Synch(7): %E%d%N\r\n",\r | |
5d73d92f | 4656 | PCIE_CAP_EXT_SYNC (PcieLinkControl)\r |
4657 | );\r | |
c37e0f16 CP |
4658 | ShellPrintEx (-1, -1,\r |
4659 | L" Enable Clock Power Management(8): %E%d%N\r\n",\r | |
5d73d92f | 4660 | PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r |
4661 | );\r | |
c37e0f16 CP |
4662 | ShellPrintEx (-1, -1,\r |
4663 | L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r | |
5d73d92f | 4664 | PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r |
4665 | );\r | |
c37e0f16 CP |
4666 | ShellPrintEx (-1, -1,\r |
4667 | L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r | |
5d73d92f | 4668 | PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r |
4669 | );\r | |
c37e0f16 CP |
4670 | ShellPrintEx (-1, -1,\r |
4671 | L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r | |
5d73d92f | 4672 | PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r |
4673 | );\r | |
4674 | return EFI_SUCCESS;\r | |
4675 | }\r | |
4676 | \r | |
a1d4bfcc | 4677 | /**\r |
4678 | Print out information of the device link status information.\r | |
4679 | \r | |
4680 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4681 | \r | |
4682 | @retval EFI_SUCCESS The operation was successful.\r | |
4683 | **/\r | |
5d73d92f | 4684 | EFI_STATUS\r |
4685 | ExplainPcieLinkStatus (\r | |
2412c297 | 4686 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4687 | )\r |
5d73d92f | 4688 | {\r |
4689 | UINT16 PcieLinkStatus;\r | |
541ddf44 | 4690 | CHAR16 *CurLinkSpeed;\r |
5d73d92f | 4691 | \r |
4692 | PcieLinkStatus = PciExpressCap->LinkStatus;\r | |
4693 | switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r | |
4694 | case 1:\r | |
541ddf44 | 4695 | CurLinkSpeed = L"2.5 GT/s";\r |
5d73d92f | 4696 | break;\r |
4697 | case 2:\r | |
541ddf44 CP |
4698 | CurLinkSpeed = L"5.0 GT/s";\r |
4699 | break;\r | |
4700 | case 3:\r | |
4701 | CurLinkSpeed = L"8.0 GT/s";\r | |
5d73d92f | 4702 | break;\r |
4703 | default:\r | |
541ddf44 | 4704 | CurLinkSpeed = L"Reserved";\r |
5d73d92f | 4705 | break;\r |
4706 | }\r | |
c37e0f16 CP |
4707 | ShellPrintEx (-1, -1,\r |
4708 | L" Current Link Speed(3:0): %E%s%N\r\n",\r | |
541ddf44 | 4709 | CurLinkSpeed\r |
5d73d92f | 4710 | );\r |
c37e0f16 CP |
4711 | ShellPrintEx (-1, -1,\r |
4712 | L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r | |
5d73d92f | 4713 | PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r |
4714 | );\r | |
c37e0f16 CP |
4715 | ShellPrintEx (-1, -1,\r |
4716 | L" Link Training(11): %E%d%N\r\n",\r | |
5d73d92f | 4717 | PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r |
4718 | );\r | |
c37e0f16 CP |
4719 | ShellPrintEx (-1, -1,\r |
4720 | L" Slot Clock Configuration(12): %E%d%N\r\n",\r | |
5d73d92f | 4721 | PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r |
4722 | );\r | |
c37e0f16 CP |
4723 | ShellPrintEx (-1, -1,\r |
4724 | L" Data Link Layer Link Active(13): %E%d%N\r\n",\r | |
5d73d92f | 4725 | PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r |
4726 | );\r | |
c37e0f16 CP |
4727 | ShellPrintEx (-1, -1,\r |
4728 | L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r | |
5d73d92f | 4729 | PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r |
4730 | );\r | |
c37e0f16 CP |
4731 | ShellPrintEx (-1, -1,\r |
4732 | L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r | |
5d73d92f | 4733 | PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r |
4734 | );\r | |
4735 | return EFI_SUCCESS;\r | |
4736 | }\r | |
4737 | \r | |
a1d4bfcc | 4738 | /**\r |
4739 | Print out information of the device slot information.\r | |
4740 | \r | |
4741 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4742 | \r | |
4743 | @retval EFI_SUCCESS The operation was successful.\r | |
4744 | **/\r | |
5d73d92f | 4745 | EFI_STATUS\r |
4746 | ExplainPcieSlotCap (\r | |
2412c297 | 4747 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4748 | )\r |
5d73d92f | 4749 | {\r |
4750 | UINT32 PcieSlotCap;\r | |
4751 | \r | |
4752 | PcieSlotCap = PciExpressCap->SlotCap;\r | |
4753 | \r | |
c37e0f16 CP |
4754 | ShellPrintEx (-1, -1,\r |
4755 | L" Attention Button Present(0): %E%d%N\r\n",\r | |
5d73d92f | 4756 | PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r |
4757 | );\r | |
c37e0f16 CP |
4758 | ShellPrintEx (-1, -1,\r |
4759 | L" Power Controller Present(1): %E%d%N\r\n",\r | |
5d73d92f | 4760 | PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r |
4761 | );\r | |
c37e0f16 CP |
4762 | ShellPrintEx (-1, -1,\r |
4763 | L" MRL Sensor Present(2): %E%d%N\r\n",\r | |
5d73d92f | 4764 | PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r |
4765 | );\r | |
c37e0f16 CP |
4766 | ShellPrintEx (-1, -1,\r |
4767 | L" Attention Indicator Present(3): %E%d%N\r\n",\r | |
5d73d92f | 4768 | PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r |
4769 | );\r | |
c37e0f16 CP |
4770 | ShellPrintEx (-1, -1,\r |
4771 | L" Power Indicator Present(4): %E%d%N\r\n",\r | |
5d73d92f | 4772 | PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r |
4773 | );\r | |
c37e0f16 CP |
4774 | ShellPrintEx (-1, -1,\r |
4775 | L" Hot-Plug Surprise(5): %E%d%N\r\n",\r | |
5d73d92f | 4776 | PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r |
4777 | );\r | |
c37e0f16 CP |
4778 | ShellPrintEx (-1, -1,\r |
4779 | L" Hot-Plug Capable(6): %E%d%N\r\n",\r | |
5d73d92f | 4780 | PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r |
4781 | );\r | |
c37e0f16 CP |
4782 | ShellPrintEx (-1, -1,\r |
4783 | L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r | |
5d73d92f | 4784 | PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r |
4785 | );\r | |
c37e0f16 CP |
4786 | ShellPrintEx (-1, -1,\r |
4787 | L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r | |
5d73d92f | 4788 | SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r |
4789 | );\r | |
c37e0f16 CP |
4790 | ShellPrintEx (-1, -1,\r |
4791 | L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r | |
5d73d92f | 4792 | PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r |
4793 | );\r | |
c37e0f16 CP |
4794 | ShellPrintEx (-1, -1,\r |
4795 | L" No Command Completed Support(18): %E%d%N\r\n",\r | |
5d73d92f | 4796 | PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r |
4797 | );\r | |
c37e0f16 CP |
4798 | ShellPrintEx (-1, -1,\r |
4799 | L" Physical Slot Number(31:19): %E%d%N\r\n",\r | |
5d73d92f | 4800 | PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r |
4801 | );\r | |
4802 | \r | |
4803 | return EFI_SUCCESS;\r | |
4804 | }\r | |
4805 | \r | |
a1d4bfcc | 4806 | /**\r |
4807 | Print out information of the device slot control information.\r | |
4808 | \r | |
4809 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4810 | \r | |
4811 | @retval EFI_SUCCESS The operation was successful.\r | |
4812 | **/\r | |
5d73d92f | 4813 | EFI_STATUS\r |
4814 | ExplainPcieSlotControl (\r | |
2412c297 | 4815 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4816 | )\r |
5d73d92f | 4817 | {\r |
4818 | UINT16 PcieSlotControl;\r | |
4819 | \r | |
4820 | PcieSlotControl = PciExpressCap->SlotControl;\r | |
c37e0f16 CP |
4821 | ShellPrintEx (-1, -1,\r |
4822 | L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r | |
5d73d92f | 4823 | PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r |
4824 | );\r | |
c37e0f16 CP |
4825 | ShellPrintEx (-1, -1,\r |
4826 | L" Power Fault Detected Enable(1): %E%d%N\r\n",\r | |
5d73d92f | 4827 | PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r |
4828 | );\r | |
c37e0f16 CP |
4829 | ShellPrintEx (-1, -1,\r |
4830 | L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r | |
5d73d92f | 4831 | PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r |
4832 | );\r | |
c37e0f16 CP |
4833 | ShellPrintEx (-1, -1,\r |
4834 | L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r | |
5d73d92f | 4835 | PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r |
4836 | );\r | |
c37e0f16 CP |
4837 | ShellPrintEx (-1, -1,\r |
4838 | L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r | |
5d73d92f | 4839 | PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r |
4840 | );\r | |
c37e0f16 CP |
4841 | ShellPrintEx (-1, -1,\r |
4842 | L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r | |
5d73d92f | 4843 | PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r |
4844 | );\r | |
c37e0f16 CP |
4845 | ShellPrintEx (-1, -1,\r |
4846 | L" Attention Indicator Control(7:6): %E%s%N\r\n",\r | |
5d73d92f | 4847 | IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r |
4848 | );\r | |
c37e0f16 CP |
4849 | ShellPrintEx (-1, -1,\r |
4850 | L" Power Indicator Control(9:8): %E%s%N\r\n",\r | |
5d73d92f | 4851 | IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r |
4852 | );\r | |
c37e0f16 | 4853 | ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r |
5d73d92f | 4854 | if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r |
c37e0f16 | 4855 | ShellPrintEx (-1, -1, L"Off%N\r\n");\r |
5d73d92f | 4856 | } else {\r |
c37e0f16 | 4857 | ShellPrintEx (-1, -1, L"On%N\r\n");\r |
5d73d92f | 4858 | }\r |
c37e0f16 CP |
4859 | ShellPrintEx (-1, -1,\r |
4860 | L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r | |
5d73d92f | 4861 | PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r |
4862 | );\r | |
c37e0f16 CP |
4863 | ShellPrintEx (-1, -1,\r |
4864 | L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r | |
5d73d92f | 4865 | PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r |
4866 | );\r | |
4867 | return EFI_SUCCESS;\r | |
4868 | }\r | |
4869 | \r | |
a1d4bfcc | 4870 | /**\r |
4871 | Print out information of the device slot status information.\r | |
4872 | \r | |
4873 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4874 | \r | |
4875 | @retval EFI_SUCCESS The operation was successful.\r | |
4876 | **/\r | |
5d73d92f | 4877 | EFI_STATUS\r |
4878 | ExplainPcieSlotStatus (\r | |
2412c297 | 4879 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4880 | )\r |
5d73d92f | 4881 | {\r |
4882 | UINT16 PcieSlotStatus;\r | |
4883 | \r | |
4884 | PcieSlotStatus = PciExpressCap->SlotStatus;\r | |
4885 | \r | |
c37e0f16 CP |
4886 | ShellPrintEx (-1, -1,\r |
4887 | L" Attention Button Pressed(0): %E%d%N\r\n",\r | |
5d73d92f | 4888 | PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r |
4889 | );\r | |
c37e0f16 CP |
4890 | ShellPrintEx (-1, -1,\r |
4891 | L" Power Fault Detected(1): %E%d%N\r\n",\r | |
5d73d92f | 4892 | PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r |
4893 | );\r | |
c37e0f16 CP |
4894 | ShellPrintEx (-1, -1,\r |
4895 | L" MRL Sensor Changed(2): %E%d%N\r\n",\r | |
5d73d92f | 4896 | PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r |
4897 | );\r | |
c37e0f16 CP |
4898 | ShellPrintEx (-1, -1,\r |
4899 | L" Presence Detect Changed(3): %E%d%N\r\n",\r | |
5d73d92f | 4900 | PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r |
4901 | );\r | |
c37e0f16 CP |
4902 | ShellPrintEx (-1, -1,\r |
4903 | L" Command Completed(4): %E%d%N\r\n",\r | |
5d73d92f | 4904 | PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r |
4905 | );\r | |
c37e0f16 | 4906 | ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r |
5d73d92f | 4907 | if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r |
c37e0f16 | 4908 | ShellPrintEx (-1, -1, L" Opened%N\r\n");\r |
5d73d92f | 4909 | } else {\r |
c37e0f16 | 4910 | ShellPrintEx (-1, -1, L" Closed%N\r\n");\r |
5d73d92f | 4911 | }\r |
c37e0f16 | 4912 | ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r |
5d73d92f | 4913 | if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r |
c37e0f16 | 4914 | ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r |
5d73d92f | 4915 | } else {\r |
c37e0f16 | 4916 | ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r |
5d73d92f | 4917 | }\r |
c37e0f16 | 4918 | ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r |
5d73d92f | 4919 | if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r |
c37e0f16 | 4920 | ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r |
5d73d92f | 4921 | } else {\r |
c37e0f16 | 4922 | ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r |
5d73d92f | 4923 | }\r |
c37e0f16 CP |
4924 | ShellPrintEx (-1, -1,\r |
4925 | L" Data Link Layer State Changed(8): %E%d%N\r\n",\r | |
5d73d92f | 4926 | PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r |
4927 | );\r | |
4928 | return EFI_SUCCESS;\r | |
4929 | }\r | |
4930 | \r | |
a1d4bfcc | 4931 | /**\r |
4932 | Print out information of the device root information.\r | |
4933 | \r | |
4934 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4935 | \r | |
4936 | @retval EFI_SUCCESS The operation was successful.\r | |
4937 | **/\r | |
5d73d92f | 4938 | EFI_STATUS\r |
4939 | ExplainPcieRootControl (\r | |
2412c297 | 4940 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4941 | )\r |
5d73d92f | 4942 | {\r |
4943 | UINT16 PcieRootControl;\r | |
4944 | \r | |
4945 | PcieRootControl = PciExpressCap->RootControl;\r | |
4946 | \r | |
c37e0f16 CP |
4947 | ShellPrintEx (-1, -1,\r |
4948 | L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r | |
5d73d92f | 4949 | PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r |
4950 | );\r | |
c37e0f16 CP |
4951 | ShellPrintEx (-1, -1,\r |
4952 | L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r | |
5d73d92f | 4953 | PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r |
4954 | );\r | |
c37e0f16 CP |
4955 | ShellPrintEx (-1, -1,\r |
4956 | L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r | |
5d73d92f | 4957 | PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r |
4958 | );\r | |
c37e0f16 CP |
4959 | ShellPrintEx (-1, -1,\r |
4960 | L" PME Interrupt Enable(3): %E%d%N\r\n",\r | |
5d73d92f | 4961 | PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r |
4962 | );\r | |
c37e0f16 CP |
4963 | ShellPrintEx (-1, -1,\r |
4964 | L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r | |
5d73d92f | 4965 | PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r |
4966 | );\r | |
4967 | \r | |
4968 | return EFI_SUCCESS;\r | |
4969 | }\r | |
4970 | \r | |
a1d4bfcc | 4971 | /**\r |
4972 | Print out information of the device root capability information.\r | |
4973 | \r | |
4974 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4975 | \r | |
4976 | @retval EFI_SUCCESS The operation was successful.\r | |
4977 | **/\r | |
5d73d92f | 4978 | EFI_STATUS\r |
4979 | ExplainPcieRootCap (\r | |
2412c297 | 4980 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4981 | )\r |
5d73d92f | 4982 | {\r |
4983 | UINT16 PcieRootCap;\r | |
4984 | \r | |
4985 | PcieRootCap = PciExpressCap->RsvdP;\r | |
4986 | \r | |
c37e0f16 CP |
4987 | ShellPrintEx (-1, -1,\r |
4988 | L" CRS Software Visibility(0): %E%d%N\r\n",\r | |
5d73d92f | 4989 | PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r |
4990 | );\r | |
4991 | \r | |
4992 | return EFI_SUCCESS;\r | |
4993 | }\r | |
4994 | \r | |
a1d4bfcc | 4995 | /**\r |
4996 | Print out information of the device root status information.\r | |
4997 | \r | |
4998 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4999 | \r | |
5000 | @retval EFI_SUCCESS The operation was successful.\r | |
5001 | **/\r | |
5d73d92f | 5002 | EFI_STATUS\r |
5003 | ExplainPcieRootStatus (\r | |
2412c297 | 5004 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 5005 | )\r |
5d73d92f | 5006 | {\r |
5007 | UINT32 PcieRootStatus;\r | |
5008 | \r | |
5009 | PcieRootStatus = PciExpressCap->RootStatus;\r | |
5010 | \r | |
c37e0f16 CP |
5011 | ShellPrintEx (-1, -1,\r |
5012 | L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r | |
5d73d92f | 5013 | PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r |
5014 | );\r | |
c37e0f16 CP |
5015 | ShellPrintEx (-1, -1,\r |
5016 | L" PME Status(16): %E%d%N\r\n",\r | |
5d73d92f | 5017 | PCIE_CAP_PME_STATUS (PcieRootStatus)\r |
5018 | );\r | |
c37e0f16 CP |
5019 | ShellPrintEx (-1, -1,\r |
5020 | L" PME Pending(17): %E%d%N\r\n",\r | |
5d73d92f | 5021 | PCIE_CAP_PME_PENDING (PcieRootStatus)\r |
5022 | );\r | |
5023 | return EFI_SUCCESS;\r | |
5024 | }\r | |
5025 | \r | |
705bffb5 JC |
5026 | /**\r |
5027 | Function to interpret and print out the link control structure\r | |
5028 | \r | |
5029 | @param[in] HeaderAddress The Address of this capability header.\r | |
5030 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5031 | **/\r | |
5032 | EFI_STATUS\r | |
5033 | EFIAPI\r | |
5034 | PrintInterpretedExtendedCompatibilityLinkControl (\r | |
5035 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5036 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5037 | )\r | |
5038 | {\r | |
5039 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r | |
5040 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r | |
5041 | \r | |
5042 | ShellPrintHiiEx(\r | |
5043 | -1, -1, NULL, \r | |
5044 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r | |
5045 | gShellDebug1HiiHandle, \r | |
5046 | Header->RootComplexLinkCapabilities,\r | |
5047 | Header->RootComplexLinkControl,\r | |
5048 | Header->RootComplexLinkStatus\r | |
5049 | ); \r | |
5050 | DumpHex (\r | |
5051 | 4,\r | |
5052 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5053 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r | |
5054 | (VOID *) (HeaderAddress)\r | |
5055 | );\r | |
5056 | return (EFI_SUCCESS);\r | |
5057 | }\r | |
5058 | \r | |
5059 | /**\r | |
5060 | Function to interpret and print out the power budgeting structure\r | |
5061 | \r | |
5062 | @param[in] HeaderAddress The Address of this capability header.\r | |
5063 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5064 | **/\r | |
5065 | EFI_STATUS\r | |
5066 | EFIAPI\r | |
5067 | PrintInterpretedExtendedCompatibilityPowerBudgeting (\r | |
5068 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5069 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5070 | )\r | |
5071 | {\r | |
5072 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r | |
5073 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r | |
5074 | \r | |
5075 | ShellPrintHiiEx(\r | |
5076 | -1, -1, NULL, \r | |
5077 | STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r | |
5078 | gShellDebug1HiiHandle, \r | |
5079 | Header->DataSelect,\r | |
5080 | Header->Data,\r | |
5081 | Header->PowerBudgetCapability\r | |
5082 | ); \r | |
5083 | DumpHex (\r | |
5084 | 4,\r | |
5085 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5086 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r | |
5087 | (VOID *) (HeaderAddress)\r | |
5088 | );\r | |
5089 | return (EFI_SUCCESS);\r | |
5090 | }\r | |
5091 | \r | |
5092 | /**\r | |
5093 | Function to interpret and print out the ACS structure\r | |
5094 | \r | |
5095 | @param[in] HeaderAddress The Address of this capability header.\r | |
5096 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5097 | **/\r | |
5098 | EFI_STATUS\r | |
5099 | EFIAPI\r | |
5100 | PrintInterpretedExtendedCompatibilityAcs (\r | |
5101 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5102 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5103 | )\r | |
5104 | {\r | |
5105 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r | |
5106 | UINT16 VectorSize;\r | |
5107 | UINT16 LoopCounter;\r | |
5108 | \r | |
5109 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r | |
5110 | VectorSize = 0;\r | |
5111 | \r | |
5112 | ShellPrintHiiEx(\r | |
5113 | -1, -1, NULL, \r | |
5114 | STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r | |
5115 | gShellDebug1HiiHandle, \r | |
5116 | Header->AcsCapability,\r | |
5117 | Header->AcsControl\r | |
5118 | ); \r | |
5119 | if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r | |
5120 | VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r | |
5121 | if (VectorSize == 0) {\r | |
5122 | VectorSize = 256;\r | |
5123 | }\r | |
5124 | for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r | |
5125 | ShellPrintHiiEx(\r | |
5126 | -1, -1, NULL, \r | |
5127 | STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r | |
5128 | gShellDebug1HiiHandle, \r | |
5129 | LoopCounter + 1,\r | |
5130 | Header->EgressControlVectorArray[LoopCounter]\r | |
5131 | ); \r | |
5132 | }\r | |
5133 | }\r | |
5134 | DumpHex (\r | |
5135 | 4,\r | |
5136 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5137 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r | |
5138 | (VOID *) (HeaderAddress)\r | |
5139 | );\r | |
5140 | return (EFI_SUCCESS);\r | |
5141 | }\r | |
5142 | \r | |
5143 | /**\r | |
5144 | Function to interpret and print out the latency tolerance reporting structure\r | |
5145 | \r | |
5146 | @param[in] HeaderAddress The Address of this capability header.\r | |
5147 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5148 | **/\r | |
5149 | EFI_STATUS\r | |
5150 | EFIAPI\r | |
5151 | PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r | |
5152 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5153 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5154 | )\r | |
5155 | {\r | |
5156 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r | |
5157 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r | |
5158 | \r | |
5159 | ShellPrintHiiEx(\r | |
5160 | -1, -1, NULL, \r | |
5161 | STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r | |
5162 | gShellDebug1HiiHandle, \r | |
5163 | Header->MaxSnoopLatency,\r | |
5164 | Header->MaxNoSnoopLatency\r | |
5165 | ); \r | |
5166 | DumpHex (\r | |
5167 | 4,\r | |
5168 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5169 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r | |
5170 | (VOID *) (HeaderAddress)\r | |
5171 | );\r | |
5172 | return (EFI_SUCCESS);\r | |
5173 | }\r | |
5174 | \r | |
5175 | /**\r | |
5176 | Function to interpret and print out the serial number structure\r | |
5177 | \r | |
5178 | @param[in] HeaderAddress The Address of this capability header.\r | |
5179 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5180 | **/\r | |
5181 | EFI_STATUS\r | |
5182 | EFIAPI\r | |
5183 | PrintInterpretedExtendedCompatibilitySerialNumber (\r | |
5184 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5185 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5186 | )\r | |
5187 | {\r | |
5188 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r | |
5189 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r | |
5190 | \r | |
5191 | ShellPrintHiiEx(\r | |
5192 | -1, -1, NULL, \r | |
5193 | STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r | |
5194 | gShellDebug1HiiHandle, \r | |
5195 | Header->SerialNumber\r | |
5196 | ); \r | |
5197 | DumpHex (\r | |
5198 | 4,\r | |
5199 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5200 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r | |
5201 | (VOID *) (HeaderAddress)\r | |
5202 | );\r | |
5203 | return (EFI_SUCCESS);\r | |
5204 | }\r | |
5205 | \r | |
5206 | /**\r | |
5207 | Function to interpret and print out the RCRB structure\r | |
5208 | \r | |
5209 | @param[in] HeaderAddress The Address of this capability header.\r | |
5210 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5211 | **/\r | |
5212 | EFI_STATUS\r | |
5213 | EFIAPI\r | |
5214 | PrintInterpretedExtendedCompatibilityRcrb (\r | |
5215 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5216 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5217 | )\r | |
5218 | {\r | |
5219 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r | |
5220 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r | |
5221 | \r | |
5222 | ShellPrintHiiEx(\r | |
5223 | -1, -1, NULL, \r | |
5224 | STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r | |
5225 | gShellDebug1HiiHandle, \r | |
5226 | Header->VendorId,\r | |
5227 | Header->DeviceId,\r | |
5228 | Header->RcrbCapabilities,\r | |
5229 | Header->RcrbControl\r | |
5230 | ); \r | |
5231 | DumpHex (\r | |
5232 | 4,\r | |
5233 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5234 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r | |
5235 | (VOID *) (HeaderAddress)\r | |
5236 | );\r | |
5237 | return (EFI_SUCCESS);\r | |
5238 | }\r | |
5239 | \r | |
5240 | /**\r | |
5241 | Function to interpret and print out the vendor specific structure\r | |
5242 | \r | |
5243 | @param[in] HeaderAddress The Address of this capability header.\r | |
5244 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5245 | **/\r | |
5246 | EFI_STATUS\r | |
5247 | EFIAPI\r | |
5248 | PrintInterpretedExtendedCompatibilityVendorSpecific (\r | |
5249 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5250 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5251 | )\r | |
5252 | {\r | |
5253 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r | |
5254 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r | |
5255 | \r | |
5256 | ShellPrintHiiEx(\r | |
5257 | -1, -1, NULL, \r | |
5258 | STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r | |
5259 | gShellDebug1HiiHandle, \r | |
5260 | Header->VendorSpecificHeader\r | |
5261 | ); \r | |
5262 | DumpHex (\r | |
5263 | 4,\r | |
5264 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5265 | PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r | |
5266 | (VOID *) (HeaderAddress)\r | |
5267 | );\r | |
5268 | return (EFI_SUCCESS);\r | |
5269 | }\r | |
5270 | \r | |
5271 | /**\r | |
5272 | Function to interpret and print out the Event Collector Endpoint Association structure\r | |
5273 | \r | |
5274 | @param[in] HeaderAddress The Address of this capability header.\r | |
5275 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5276 | **/\r | |
5277 | EFI_STATUS\r | |
5278 | EFIAPI\r | |
5279 | PrintInterpretedExtendedCompatibilityECEA (\r | |
5280 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5281 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5282 | )\r | |
5283 | {\r | |
5284 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r | |
5285 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r | |
5286 | \r | |
5287 | ShellPrintHiiEx(\r | |
5288 | -1, -1, NULL, \r | |
5289 | STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r | |
5290 | gShellDebug1HiiHandle, \r | |
5291 | Header->AssociationBitmap\r | |
5292 | ); \r | |
5293 | DumpHex (\r | |
5294 | 4,\r | |
5295 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5296 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r | |
5297 | (VOID *) (HeaderAddress)\r | |
5298 | );\r | |
5299 | return (EFI_SUCCESS);\r | |
5300 | }\r | |
5301 | \r | |
5302 | /**\r | |
5303 | Function to interpret and print out the ARI structure\r | |
5304 | \r | |
5305 | @param[in] HeaderAddress The Address of this capability header.\r | |
5306 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5307 | **/\r | |
5308 | EFI_STATUS\r | |
5309 | EFIAPI\r | |
5310 | PrintInterpretedExtendedCompatibilityAri (\r | |
5311 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5312 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5313 | )\r | |
5314 | {\r | |
5315 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r | |
5316 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r | |
5317 | \r | |
5318 | ShellPrintHiiEx(\r | |
5319 | -1, -1, NULL, \r | |
5320 | STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r | |
5321 | gShellDebug1HiiHandle, \r | |
5322 | Header->AriCapability,\r | |
5323 | Header->AriControl\r | |
5324 | ); \r | |
5325 | DumpHex (\r | |
5326 | 4,\r | |
5327 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5328 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r | |
5329 | (VOID *) (HeaderAddress)\r | |
5330 | );\r | |
5331 | return (EFI_SUCCESS);\r | |
5332 | }\r | |
5333 | \r | |
5334 | /**\r | |
5335 | Function to interpret and print out the DPA structure\r | |
5336 | \r | |
5337 | @param[in] HeaderAddress The Address of this capability header.\r | |
5338 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5339 | **/\r | |
5340 | EFI_STATUS\r | |
5341 | EFIAPI\r | |
5342 | PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r | |
5343 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5344 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5345 | )\r | |
5346 | {\r | |
5347 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r | |
5348 | UINT8 LinkCount;\r | |
5349 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r | |
5350 | \r | |
5351 | ShellPrintHiiEx(\r | |
5352 | -1, -1, NULL, \r | |
5353 | STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r | |
5354 | gShellDebug1HiiHandle, \r | |
5355 | Header->DpaCapability,\r | |
5356 | Header->DpaLatencyIndicator,\r | |
5357 | Header->DpaStatus,\r | |
5358 | Header->DpaControl\r | |
5359 | ); \r | |
5360 | for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r | |
5361 | ShellPrintHiiEx(\r | |
5362 | -1, -1, NULL, \r | |
5363 | STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r | |
5364 | gShellDebug1HiiHandle, \r | |
5365 | LinkCount+1,\r | |
5366 | Header->DpaPowerAllocationArray[LinkCount]\r | |
5367 | );\r | |
5368 | }\r | |
5369 | DumpHex (\r | |
5370 | 4,\r | |
5371 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5372 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r | |
5373 | (VOID *) (HeaderAddress)\r | |
5374 | );\r | |
5375 | return (EFI_SUCCESS);\r | |
5376 | }\r | |
5377 | \r | |
5378 | /**\r | |
5379 | Function to interpret and print out the link declaration structure\r | |
5380 | \r | |
5381 | @param[in] HeaderAddress The Address of this capability header.\r | |
5382 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5383 | **/\r | |
5384 | EFI_STATUS\r | |
5385 | EFIAPI\r | |
5386 | PrintInterpretedExtendedCompatibilityLinkDeclaration (\r | |
5387 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5388 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5389 | )\r | |
5390 | {\r | |
5391 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r | |
5392 | UINT8 LinkCount;\r | |
5393 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r | |
5394 | \r | |
5395 | ShellPrintHiiEx(\r | |
5396 | -1, -1, NULL, \r | |
5397 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r | |
5398 | gShellDebug1HiiHandle, \r | |
5399 | Header->ElementSelfDescription\r | |
5400 | );\r | |
5401 | \r | |
5402 | for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r | |
5403 | ShellPrintHiiEx(\r | |
5404 | -1, -1, NULL, \r | |
5405 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r | |
5406 | gShellDebug1HiiHandle, \r | |
5407 | LinkCount+1,\r | |
5408 | Header->LinkEntry[LinkCount]\r | |
5409 | );\r | |
5410 | }\r | |
5411 | DumpHex (\r | |
5412 | 4,\r | |
5413 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5414 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r | |
5415 | (VOID *) (HeaderAddress)\r | |
5416 | );\r | |
5417 | return (EFI_SUCCESS);\r | |
5418 | }\r | |
5419 | \r | |
5420 | /**\r | |
5421 | Function to interpret and print out the Advanced Error Reporting structure\r | |
5422 | \r | |
5423 | @param[in] HeaderAddress The Address of this capability header.\r | |
5424 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5425 | **/\r | |
5426 | EFI_STATUS\r | |
5427 | EFIAPI\r | |
5428 | PrintInterpretedExtendedCompatibilityAer (\r | |
5429 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5430 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5431 | )\r | |
5432 | {\r | |
5433 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r | |
5434 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r | |
5435 | \r | |
5436 | ShellPrintHiiEx(\r | |
5437 | -1, -1, NULL, \r | |
5438 | STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r | |
5439 | gShellDebug1HiiHandle, \r | |
5440 | Header->UncorrectableErrorStatus,\r | |
5441 | Header->UncorrectableErrorMask,\r | |
5442 | Header->UncorrectableErrorSeverity,\r | |
5443 | Header->CorrectableErrorStatus,\r | |
5444 | Header->CorrectableErrorMask,\r | |
5445 | Header->AdvancedErrorCapabilitiesAndControl,\r | |
5446 | Header->HeaderLog,\r | |
5447 | Header->RootErrorCommand,\r | |
5448 | Header->RootErrorStatus,\r | |
5449 | Header->ErrorSourceIdentification,\r | |
5450 | Header->CorrectableErrorSourceIdentification,\r | |
5451 | Header->TlpPrefixLog[0],\r | |
5452 | Header->TlpPrefixLog[1],\r | |
5453 | Header->TlpPrefixLog[2],\r | |
5454 | Header->TlpPrefixLog[3]\r | |
5455 | );\r | |
5456 | DumpHex (\r | |
5457 | 4,\r | |
5458 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5459 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r | |
5460 | (VOID *) (HeaderAddress)\r | |
5461 | );\r | |
5462 | return (EFI_SUCCESS);\r | |
5463 | }\r | |
5464 | \r | |
9f7f0697 JC |
5465 | /**\r |
5466 | Function to interpret and print out the multicast structure\r | |
5467 | \r | |
5468 | @param[in] HeaderAddress The Address of this capability header.\r | |
5469 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5470 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5471 | **/\r | |
5472 | EFI_STATUS\r | |
5473 | EFIAPI\r | |
5474 | PrintInterpretedExtendedCompatibilityMulticast (\r | |
5475 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5476 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r | |
2412c297 | 5477 | IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r |
9f7f0697 JC |
5478 | )\r |
5479 | {\r | |
5480 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r | |
5481 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r | |
5482 | \r | |
5483 | ShellPrintHiiEx(\r | |
5484 | -1, -1, NULL, \r | |
5485 | STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r | |
5486 | gShellDebug1HiiHandle, \r | |
5487 | Header->MultiCastCapability,\r | |
5488 | Header->MulticastControl,\r | |
5489 | Header->McBaseAddress,\r | |
5490 | Header->McReceiveAddress,\r | |
5491 | Header->McBlockAll,\r | |
5492 | Header->McBlockUntranslated,\r | |
5493 | Header->McOverlayBar\r | |
5494 | );\r | |
5495 | \r | |
5496 | DumpHex (\r | |
5497 | 4,\r | |
5498 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5499 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r | |
5500 | (VOID *) (HeaderAddress)\r | |
5501 | );\r | |
5502 | \r | |
5503 | return (EFI_SUCCESS);\r | |
5504 | }\r | |
5505 | \r | |
5506 | /**\r | |
5507 | Function to interpret and print out the virtual channel and multi virtual channel structure\r | |
5508 | \r | |
5509 | @param[in] HeaderAddress The Address of this capability header.\r | |
5510 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5511 | **/\r | |
5512 | EFI_STATUS\r | |
5513 | EFIAPI\r | |
5514 | PrintInterpretedExtendedCompatibilityVirtualChannel (\r | |
5515 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5516 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5517 | )\r | |
5518 | {\r | |
5519 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r | |
5520 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r | |
5521 | UINT32 ItemCount;\r | |
5522 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r | |
5523 | \r | |
5524 | ShellPrintHiiEx(\r | |
5525 | -1, -1, NULL, \r | |
5526 | STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r | |
5527 | gShellDebug1HiiHandle, \r | |
5528 | Header->ExtendedVcCount,\r | |
5529 | Header->PortVcCapability1,\r | |
5530 | Header->PortVcCapability2,\r | |
5531 | Header->VcArbTableOffset,\r | |
5532 | Header->PortVcControl,\r | |
5533 | Header->PortVcStatus\r | |
5534 | );\r | |
5535 | for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r | |
5536 | CapabilityItem = &Header->Capability[ItemCount];\r | |
5537 | ShellPrintHiiEx(\r | |
5538 | -1, -1, NULL, \r | |
5539 | STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r | |
5540 | gShellDebug1HiiHandle, \r | |
5541 | ItemCount+1,\r | |
5542 | CapabilityItem->VcResourceCapability,\r | |
5543 | CapabilityItem->PortArbTableOffset,\r | |
5544 | CapabilityItem->VcResourceControl,\r | |
5545 | CapabilityItem->VcResourceStatus\r | |
5546 | );\r | |
5547 | }\r | |
5548 | \r | |
5549 | DumpHex (\r | |
5550 | 4,\r | |
5551 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5552 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),\r | |
5553 | (VOID *) (HeaderAddress)\r | |
5554 | );\r | |
5555 | \r | |
5556 | return (EFI_SUCCESS);\r | |
5557 | }\r | |
5558 | \r | |
5559 | /**\r | |
5560 | Function to interpret and print out the resizeable bar structure\r | |
5561 | \r | |
5562 | @param[in] HeaderAddress The Address of this capability header.\r | |
5563 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5564 | **/\r | |
5565 | EFI_STATUS\r | |
5566 | EFIAPI\r | |
5567 | PrintInterpretedExtendedCompatibilityResizeableBar (\r | |
5568 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5569 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5570 | )\r | |
5571 | {\r | |
5572 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r | |
5573 | UINT32 ItemCount;\r | |
5574 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r | |
5575 | \r | |
5576 | for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r | |
5577 | ShellPrintHiiEx(\r | |
5578 | -1, -1, NULL, \r | |
5579 | STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r | |
5580 | gShellDebug1HiiHandle, \r | |
5581 | ItemCount+1,\r | |
5582 | Header->Capability[ItemCount].ResizableBarCapability,\r | |
5583 | Header->Capability[ItemCount].ResizableBarControl\r | |
5584 | );\r | |
5585 | }\r | |
5586 | \r | |
5587 | DumpHex (\r | |
5588 | 4,\r | |
5589 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5590 | (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r | |
5591 | (VOID *) (HeaderAddress)\r | |
5592 | );\r | |
5593 | \r | |
5594 | return (EFI_SUCCESS);\r | |
5595 | }\r | |
5596 | \r | |
5597 | /**\r | |
5598 | Function to interpret and print out the TPH structure\r | |
5599 | \r | |
5600 | @param[in] HeaderAddress The Address of this capability header.\r | |
5601 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5602 | **/\r | |
5603 | EFI_STATUS\r | |
5604 | EFIAPI\r | |
5605 | PrintInterpretedExtendedCompatibilityTph (\r | |
5606 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5607 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5608 | )\r | |
5609 | {\r | |
5610 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r | |
5611 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r | |
5612 | \r | |
5613 | ShellPrintHiiEx(\r | |
5614 | -1, -1, NULL, \r | |
5615 | STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r | |
5616 | gShellDebug1HiiHandle, \r | |
5617 | Header->TphRequesterCapability,\r | |
5618 | Header->TphRequesterControl\r | |
5619 | );\r | |
5620 | DumpHex (\r | |
5621 | 8,\r | |
5622 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r | |
5623 | GET_TPH_TABLE_SIZE(Header),\r | |
5624 | (VOID *)Header->TphStTable\r | |
5625 | );\r | |
5626 | \r | |
5627 | DumpHex (\r | |
5628 | 4,\r | |
5629 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5630 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r | |
5631 | (VOID *) (HeaderAddress)\r | |
5632 | );\r | |
5633 | \r | |
5634 | return (EFI_SUCCESS);\r | |
5635 | }\r | |
5636 | \r | |
5637 | /**\r | |
5638 | Function to interpret and print out the secondary PCIe capability structure\r | |
5639 | \r | |
5640 | @param[in] HeaderAddress The Address of this capability header.\r | |
5641 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5642 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5643 | **/\r | |
5644 | EFI_STATUS\r | |
5645 | EFIAPI\r | |
5646 | PrintInterpretedExtendedCompatibilitySecondary (\r | |
5647 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5648 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r | |
2412c297 | 5649 | IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r |
9f7f0697 JC |
5650 | )\r |
5651 | {\r | |
5652 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r | |
5653 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r | |
5654 | \r | |
5655 | ShellPrintHiiEx(\r | |
5656 | -1, -1, NULL, \r | |
5657 | STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r | |
5658 | gShellDebug1HiiHandle, \r | |
5659 | Header->LinkControl3,\r | |
5660 | Header->LaneErrorStatus\r | |
5661 | );\r | |
5662 | DumpHex (\r | |
5663 | 8,\r | |
5664 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r | |
5665 | PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r | |
5666 | (VOID *)Header->EqualizationControl\r | |
5667 | );\r | |
5668 | \r | |
5669 | DumpHex (\r | |
5670 | 4,\r | |
5671 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5672 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r | |
5673 | (VOID *) (HeaderAddress)\r | |
5674 | );\r | |
5675 | \r | |
5676 | return (EFI_SUCCESS);\r | |
5677 | }\r | |
5678 | \r | |
705bffb5 JC |
5679 | /**\r |
5680 | Display Pcie extended capability details\r | |
5681 | \r | |
5682 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5683 | @param[in] HeaderAddress The address of this capability header.\r | |
5684 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5685 | **/\r | |
5686 | EFI_STATUS\r | |
5687 | EFIAPI\r | |
5688 | PrintPciExtendedCapabilityDetails(\r | |
5689 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r | |
5690 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
2412c297 | 5691 | IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r |
705bffb5 JC |
5692 | )\r |
5693 | {\r | |
5694 | switch (HeaderAddress->CapabilityId){\r | |
5695 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r | |
5696 | return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5697 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r |
5698 | return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5699 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r |
5700 | return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5701 | case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r |
5702 | return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5703 | case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r |
5704 | return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5705 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r |
5706 | return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5707 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r |
5708 | return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5709 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r |
5710 | return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5711 | case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r |
5712 | return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5713 | case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r |
5714 | return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5715 | case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r |
5716 | return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5717 | case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r |
5718 | return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5719 | case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r |
5720 | case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r | |
9f7f0697 | 5721 | return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 5722 | case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r |
9f7f0697 JC |
5723 | //\r |
5724 | // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r | |
5725 | //\r | |
5726 | return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r | |
705bffb5 | 5727 | case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r |
9f7f0697 | 5728 | return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 5729 | case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r |
9f7f0697 | 5730 | return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 5731 | case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r |
9f7f0697 | 5732 | return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r |
705bffb5 JC |
5733 | default:\r |
5734 | ShellPrintEx (-1, -1,\r | |
5735 | L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r | |
5736 | HeaderAddress->CapabilityId\r | |
5737 | );\r | |
5738 | return EFI_SUCCESS;\r | |
705bffb5 JC |
5739 | };\r |
5740 | \r | |
5741 | }\r | |
5742 | \r | |
a1d4bfcc | 5743 | /**\r |
5744 | Display Pcie device structure.\r | |
5745 | \r | |
5746 | @param[in] IoDev The pointer to the root pci protocol.\r | |
5747 | @param[in] Address The Address to start at.\r | |
5748 | @param[in] CapabilityPtr The offset from the address to start.\r | |
f614ce7e SQ |
5749 | @param[in] EnhancedDump The print format for the dump data.\r |
5750 | \r | |
a1d4bfcc | 5751 | **/\r |
5d73d92f | 5752 | EFI_STATUS\r |
5753 | PciExplainPciExpress (\r | |
5754 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
5755 | IN UINT64 Address,\r | |
705bffb5 JC |
5756 | IN UINT8 CapabilityPtr,\r |
5757 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 5758 | )\r |
5759 | {\r | |
5760 | \r | |
2412c297 | 5761 | PCIE_CAP_STRUCTURE PciExpressCap;\r |
5d73d92f | 5762 | EFI_STATUS Status;\r |
5763 | UINT64 CapRegAddress;\r | |
5764 | UINT8 Bus;\r | |
5765 | UINT8 Dev;\r | |
5766 | UINT8 Func;\r | |
5767 | UINT8 *ExRegBuffer;\r | |
5768 | UINTN ExtendRegSize;\r | |
5769 | UINT64 Pciex_Address;\r | |
5770 | UINT8 DevicePortType;\r | |
5771 | UINTN Index;\r | |
5772 | UINT8 *RegAddr;\r | |
5773 | UINTN RegValue;\r | |
705bffb5 | 5774 | PCI_EXP_EXT_HDR *ExtHdr;\r |
5d73d92f | 5775 | \r |
5776 | CapRegAddress = Address + CapabilityPtr;\r | |
5777 | IoDev->Pci.Read (\r | |
5778 | IoDev,\r | |
5779 | EfiPciWidthUint32,\r | |
5780 | CapRegAddress,\r | |
5781 | sizeof (PciExpressCap) / sizeof (UINT32),\r | |
5782 | &PciExpressCap\r | |
5783 | );\r | |
5784 | \r | |
5785 | DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r | |
5786 | \r | |
c37e0f16 | 5787 | ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r |
5d73d92f | 5788 | \r |
5789 | for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r | |
5790 | if (ShellGetExecutionBreakFlag()) {\r | |
5791 | goto Done;\r | |
5792 | }\r | |
5793 | RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r | |
5794 | switch (PcieExplainList[Index].Width) {\r | |
5795 | case FieldWidthUINT8:\r | |
5796 | RegValue = *(UINT8 *) RegAddr;\r | |
5797 | break;\r | |
5798 | case FieldWidthUINT16:\r | |
5799 | RegValue = *(UINT16 *) RegAddr;\r | |
5800 | break;\r | |
5801 | case FieldWidthUINT32:\r | |
5802 | RegValue = *(UINT32 *) RegAddr;\r | |
5803 | break;\r | |
5804 | default:\r | |
5805 | RegValue = 0;\r | |
5806 | break;\r | |
5807 | }\r | |
5808 | ShellPrintHiiEx(-1, -1, NULL,\r | |
5809 | PcieExplainList[Index].Token,\r | |
5810 | gShellDebug1HiiHandle,\r | |
5811 | PcieExplainList[Index].Offset,\r | |
5812 | RegValue\r | |
5813 | );\r | |
5814 | if (PcieExplainList[Index].Func == NULL) {\r | |
5815 | continue;\r | |
5816 | }\r | |
5817 | switch (PcieExplainList[Index].Type) {\r | |
5818 | case PcieExplainTypeLink:\r | |
5819 | //\r | |
5820 | // Link registers should not be used by\r | |
5821 | // a) Root Complex Integrated Endpoint\r | |
5822 | // b) Root Complex Event Collector\r | |
5823 | //\r | |
5824 | if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r | |
5825 | DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r | |
5826 | continue;\r | |
5827 | }\r | |
5828 | break;\r | |
5829 | case PcieExplainTypeSlot:\r | |
5830 | //\r | |
5831 | // Slot registers are only valid for\r | |
5832 | // a) Root Port of PCI Express Root Complex\r | |
5833 | // b) Downstream Port of PCI Express Switch\r | |
5834 | // and when SlotImplemented bit is set in PCIE cap register.\r | |
5835 | //\r | |
5836 | if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r | |
5837 | DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r | |
5838 | !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r | |
5839 | continue;\r | |
5840 | }\r | |
5841 | break;\r | |
5842 | case PcieExplainTypeRoot:\r | |
5843 | //\r | |
5844 | // Root registers are only valid for\r | |
5845 | // Root Port of PCI Express Root Complex\r | |
5846 | //\r | |
5847 | if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r | |
5848 | continue;\r | |
5849 | }\r | |
5850 | break;\r | |
5851 | default:\r | |
5852 | break;\r | |
5853 | }\r | |
5854 | PcieExplainList[Index].Func (&PciExpressCap);\r | |
5855 | }\r | |
5856 | \r | |
5857 | Bus = (UINT8) (RShiftU64 (Address, 24));\r | |
5858 | Dev = (UINT8) (RShiftU64 (Address, 16));\r | |
5859 | Func = (UINT8) (RShiftU64 (Address, 8));\r | |
5860 | \r | |
705bffb5 | 5861 | Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET);\r |
5d73d92f | 5862 | \r |
705bffb5 | 5863 | ExtendRegSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r |
5d73d92f | 5864 | \r |
3737ac2b | 5865 | ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r |
5d73d92f | 5866 | \r |
5867 | //\r | |
5868 | // PciRootBridgeIo protocol should support pci express extend space IO\r | |
705bffb5 | 5869 | // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)\r |
5d73d92f | 5870 | //\r |
5871 | Status = IoDev->Pci.Read (\r | |
5872 | IoDev,\r | |
5873 | EfiPciWidthUint32,\r | |
5874 | Pciex_Address,\r | |
5875 | (ExtendRegSize) / sizeof (UINT32),\r | |
5876 | (VOID *) (ExRegBuffer)\r | |
5877 | );\r | |
705bffb5 JC |
5878 | if (EFI_ERROR (Status) || ExRegBuffer == NULL) {\r |
5879 | SHELL_FREE_NON_NULL(ExRegBuffer);\r | |
5d73d92f | 5880 | return EFI_UNSUPPORTED;\r |
5881 | }\r | |
5d73d92f | 5882 | \r |
705bffb5 JC |
5883 | if (EnhancedDump == 0) {\r |
5884 | //\r | |
5885 | // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r | |
5886 | //\r | |
5887 | ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r | |
5888 | \r | |
d8f8021c | 5889 | DumpHex (\r |
5890 | 2,\r | |
705bffb5 | 5891 | EFI_PCIE_CAPABILITY_BASE_OFFSET,\r |
d8f8021c | 5892 | ExtendRegSize,\r |
5893 | (VOID *) (ExRegBuffer)\r | |
705bffb5 JC |
5894 | );\r |
5895 | } else {\r | |
5896 | ExtHdr = (PCI_EXP_EXT_HDR*)ExRegBuffer;\r | |
5897 | while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r | |
5898 | //\r | |
5899 | // Process this item\r | |
5900 | //\r | |
5901 | if (EnhancedDump == 0xFFFF || EnhancedDump == ExtHdr->CapabilityId) {\r | |
5902 | //\r | |
5903 | // Print this item\r | |
5904 | //\r | |
5905 | PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExRegBuffer, ExtHdr, &PciExpressCap);\r | |
5906 | }\r | |
5d73d92f | 5907 | \r |
705bffb5 JC |
5908 | //\r |
5909 | // Advance to the next item if it exists\r | |
5910 | //\r | |
5911 | if (ExtHdr->NextCapabilityOffset != 0) {\r | |
5912 | ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + ExtHdr->NextCapabilityOffset);\r | |
5913 | } else {\r | |
5914 | break;\r | |
5915 | }\r | |
5916 | }\r | |
d8f8021c | 5917 | }\r |
705bffb5 | 5918 | SHELL_FREE_NON_NULL(ExRegBuffer);\r |
5d73d92f | 5919 | \r |
5920 | Done:\r | |
5921 | return EFI_SUCCESS;\r | |
5922 | }\r |