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5d73d92f | 1 | /** @file\r |
2 | Main file for Pci shell Debug1 function.\r | |
3 | \r | |
231ad7d8 QS |
4 | Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>\r |
5 | (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r | |
6 | (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR> \r | |
5d73d92f | 7 | This program and the accompanying materials\r |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include "UefiShellDebug1CommandsLib.h"\r | |
18 | #include <Protocol/PciRootBridgeIo.h>\r | |
19 | #include <Library/ShellLib.h>\r | |
20 | #include <IndustryStandard/Pci.h>\r | |
21 | #include <IndustryStandard/Acpi.h>\r | |
22 | #include "Pci.h"\r | |
23 | \r | |
5d73d92f | 24 | //\r |
25 | // Printable strings for Pci class code\r | |
26 | //\r | |
27 | typedef struct {\r | |
28 | CHAR16 *BaseClass; // Pointer to the PCI base class string\r | |
29 | CHAR16 *SubClass; // Pointer to the PCI sub class string\r | |
30 | CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r | |
31 | } PCI_CLASS_STRINGS;\r | |
32 | \r | |
33 | //\r | |
34 | // a structure holding a single entry, which also points to its lower level\r | |
35 | // class\r | |
36 | //\r | |
37 | typedef struct PCI_CLASS_ENTRY_TAG {\r | |
38 | UINT8 Code; // Class, subclass or I/F code\r | |
39 | CHAR16 *DescText; // Description string\r | |
40 | struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r | |
41 | } PCI_CLASS_ENTRY;\r | |
42 | \r | |
43 | //\r | |
44 | // Declarations of entries which contain printable strings for class codes\r | |
45 | // in PCI configuration space\r | |
46 | //\r | |
47 | PCI_CLASS_ENTRY PCIBlankEntry[];\r | |
48 | PCI_CLASS_ENTRY PCISubClass_00[];\r | |
49 | PCI_CLASS_ENTRY PCISubClass_01[];\r | |
50 | PCI_CLASS_ENTRY PCISubClass_02[];\r | |
51 | PCI_CLASS_ENTRY PCISubClass_03[];\r | |
52 | PCI_CLASS_ENTRY PCISubClass_04[];\r | |
53 | PCI_CLASS_ENTRY PCISubClass_05[];\r | |
54 | PCI_CLASS_ENTRY PCISubClass_06[];\r | |
55 | PCI_CLASS_ENTRY PCISubClass_07[];\r | |
56 | PCI_CLASS_ENTRY PCISubClass_08[];\r | |
57 | PCI_CLASS_ENTRY PCISubClass_09[];\r | |
58 | PCI_CLASS_ENTRY PCISubClass_0a[];\r | |
59 | PCI_CLASS_ENTRY PCISubClass_0b[];\r | |
60 | PCI_CLASS_ENTRY PCISubClass_0c[];\r | |
61 | PCI_CLASS_ENTRY PCISubClass_0d[];\r | |
62 | PCI_CLASS_ENTRY PCISubClass_0e[];\r | |
63 | PCI_CLASS_ENTRY PCISubClass_0f[];\r | |
64 | PCI_CLASS_ENTRY PCISubClass_10[];\r | |
65 | PCI_CLASS_ENTRY PCISubClass_11[];\r | |
f056e4c1 JC |
66 | PCI_CLASS_ENTRY PCISubClass_12[];\r |
67 | PCI_CLASS_ENTRY PCISubClass_13[];\r | |
68 | PCI_CLASS_ENTRY PCIPIFClass_0100[];\r | |
5d73d92f | 69 | PCI_CLASS_ENTRY PCIPIFClass_0101[];\r |
f056e4c1 JC |
70 | PCI_CLASS_ENTRY PCIPIFClass_0105[];\r |
71 | PCI_CLASS_ENTRY PCIPIFClass_0106[];\r | |
72 | PCI_CLASS_ENTRY PCIPIFClass_0107[];\r | |
73 | PCI_CLASS_ENTRY PCIPIFClass_0108[];\r | |
74 | PCI_CLASS_ENTRY PCIPIFClass_0109[];\r | |
5d73d92f | 75 | PCI_CLASS_ENTRY PCIPIFClass_0300[];\r |
76 | PCI_CLASS_ENTRY PCIPIFClass_0604[];\r | |
f056e4c1 JC |
77 | PCI_CLASS_ENTRY PCIPIFClass_0609[];\r |
78 | PCI_CLASS_ENTRY PCIPIFClass_060b[];\r | |
5d73d92f | 79 | PCI_CLASS_ENTRY PCIPIFClass_0700[];\r |
80 | PCI_CLASS_ENTRY PCIPIFClass_0701[];\r | |
81 | PCI_CLASS_ENTRY PCIPIFClass_0703[];\r | |
82 | PCI_CLASS_ENTRY PCIPIFClass_0800[];\r | |
83 | PCI_CLASS_ENTRY PCIPIFClass_0801[];\r | |
84 | PCI_CLASS_ENTRY PCIPIFClass_0802[];\r | |
85 | PCI_CLASS_ENTRY PCIPIFClass_0803[];\r | |
86 | PCI_CLASS_ENTRY PCIPIFClass_0904[];\r | |
87 | PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r | |
88 | PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r | |
f056e4c1 JC |
89 | PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r |
90 | PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r | |
5d73d92f | 91 | PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r |
92 | \r | |
93 | //\r | |
94 | // Base class strings entries\r | |
95 | //\r | |
96 | PCI_CLASS_ENTRY gClassStringList[] = {\r | |
97 | {\r | |
98 | 0x00,\r | |
99 | L"Pre 2.0 device",\r | |
100 | PCISubClass_00\r | |
101 | },\r | |
102 | {\r | |
103 | 0x01,\r | |
104 | L"Mass Storage Controller",\r | |
105 | PCISubClass_01\r | |
106 | },\r | |
107 | {\r | |
108 | 0x02,\r | |
109 | L"Network Controller",\r | |
110 | PCISubClass_02\r | |
111 | },\r | |
112 | {\r | |
113 | 0x03,\r | |
114 | L"Display Controller",\r | |
115 | PCISubClass_03\r | |
116 | },\r | |
117 | {\r | |
118 | 0x04,\r | |
119 | L"Multimedia Device",\r | |
120 | PCISubClass_04\r | |
121 | },\r | |
122 | {\r | |
123 | 0x05,\r | |
124 | L"Memory Controller",\r | |
125 | PCISubClass_05\r | |
126 | },\r | |
127 | {\r | |
128 | 0x06,\r | |
129 | L"Bridge Device",\r | |
130 | PCISubClass_06\r | |
131 | },\r | |
132 | {\r | |
133 | 0x07,\r | |
134 | L"Simple Communications Controllers",\r | |
135 | PCISubClass_07\r | |
136 | },\r | |
137 | {\r | |
138 | 0x08,\r | |
139 | L"Base System Peripherals",\r | |
140 | PCISubClass_08\r | |
141 | },\r | |
142 | {\r | |
143 | 0x09,\r | |
144 | L"Input Devices",\r | |
145 | PCISubClass_09\r | |
146 | },\r | |
147 | {\r | |
148 | 0x0a,\r | |
149 | L"Docking Stations",\r | |
150 | PCISubClass_0a\r | |
151 | },\r | |
152 | {\r | |
153 | 0x0b,\r | |
154 | L"Processors",\r | |
155 | PCISubClass_0b\r | |
156 | },\r | |
157 | {\r | |
158 | 0x0c,\r | |
159 | L"Serial Bus Controllers",\r | |
160 | PCISubClass_0c\r | |
161 | },\r | |
162 | {\r | |
163 | 0x0d,\r | |
164 | L"Wireless Controllers",\r | |
165 | PCISubClass_0d\r | |
166 | },\r | |
167 | {\r | |
168 | 0x0e,\r | |
169 | L"Intelligent IO Controllers",\r | |
170 | PCISubClass_0e\r | |
171 | },\r | |
172 | {\r | |
173 | 0x0f,\r | |
174 | L"Satellite Communications Controllers",\r | |
175 | PCISubClass_0f\r | |
176 | },\r | |
177 | {\r | |
178 | 0x10,\r | |
179 | L"Encryption/Decryption Controllers",\r | |
180 | PCISubClass_10\r | |
181 | },\r | |
182 | {\r | |
183 | 0x11,\r | |
184 | L"Data Acquisition & Signal Processing Controllers",\r | |
185 | PCISubClass_11\r | |
186 | },\r | |
f056e4c1 JC |
187 | {\r |
188 | 0x12,\r | |
189 | L"Processing Accelerators",\r | |
190 | PCISubClass_12\r | |
191 | },\r | |
192 | {\r | |
193 | 0x13,\r | |
194 | L"Non-Essential Instrumentation",\r | |
195 | PCISubClass_13\r | |
196 | },\r | |
5d73d92f | 197 | {\r |
198 | 0xff,\r | |
199 | L"Device does not fit in any defined classes",\r | |
200 | PCIBlankEntry\r | |
201 | },\r | |
202 | {\r | |
203 | 0x00,\r | |
204 | NULL,\r | |
205 | /* null string ends the list */NULL\r | |
206 | }\r | |
207 | };\r | |
208 | \r | |
209 | //\r | |
210 | // Subclass strings entries\r | |
211 | //\r | |
212 | PCI_CLASS_ENTRY PCIBlankEntry[] = {\r | |
213 | {\r | |
214 | 0x00,\r | |
215 | L"",\r | |
216 | PCIBlankEntry\r | |
217 | },\r | |
218 | {\r | |
219 | 0x00,\r | |
220 | NULL,\r | |
221 | /* null string ends the list */NULL\r | |
222 | }\r | |
223 | };\r | |
224 | \r | |
225 | PCI_CLASS_ENTRY PCISubClass_00[] = {\r | |
226 | {\r | |
227 | 0x00,\r | |
228 | L"All devices other than VGA",\r | |
229 | PCIBlankEntry\r | |
230 | },\r | |
231 | {\r | |
232 | 0x01,\r | |
233 | L"VGA-compatible devices",\r | |
234 | PCIBlankEntry\r | |
235 | },\r | |
236 | {\r | |
237 | 0x00,\r | |
238 | NULL,\r | |
239 | /* null string ends the list */NULL\r | |
240 | }\r | |
241 | };\r | |
242 | \r | |
243 | PCI_CLASS_ENTRY PCISubClass_01[] = {\r | |
244 | {\r | |
245 | 0x00,\r | |
f056e4c1 JC |
246 | L"SCSI",\r |
247 | PCIPIFClass_0100\r | |
5d73d92f | 248 | },\r |
249 | {\r | |
250 | 0x01,\r | |
251 | L"IDE controller",\r | |
252 | PCIPIFClass_0101\r | |
253 | },\r | |
254 | {\r | |
255 | 0x02,\r | |
256 | L"Floppy disk controller",\r | |
257 | PCIBlankEntry\r | |
258 | },\r | |
259 | {\r | |
260 | 0x03,\r | |
261 | L"IPI controller",\r | |
262 | PCIBlankEntry\r | |
263 | },\r | |
264 | {\r | |
265 | 0x04,\r | |
266 | L"RAID controller",\r | |
267 | PCIBlankEntry\r | |
268 | },\r | |
f056e4c1 JC |
269 | {\r |
270 | 0x05,\r | |
271 | L"ATA controller with ADMA interface",\r | |
272 | PCIPIFClass_0105\r | |
273 | },\r | |
274 | {\r | |
275 | 0x06,\r | |
276 | L"Serial ATA controller",\r | |
277 | PCIPIFClass_0106\r | |
278 | },\r | |
279 | {\r | |
280 | 0x07,\r | |
281 | L"Serial Attached SCSI (SAS) controller ",\r | |
282 | PCIPIFClass_0107\r | |
283 | },\r | |
284 | {\r | |
285 | 0x08,\r | |
286 | L"Non-volatile memory subsystem",\r | |
287 | PCIPIFClass_0108\r | |
288 | },\r | |
289 | {\r | |
290 | 0x09,\r | |
291 | L"Universal Flash Storage (UFS) controller ",\r | |
292 | PCIPIFClass_0109\r | |
293 | },\r | |
5d73d92f | 294 | {\r |
295 | 0x80,\r | |
296 | L"Other mass storage controller",\r | |
297 | PCIBlankEntry\r | |
298 | },\r | |
299 | {\r | |
300 | 0x00,\r | |
301 | NULL,\r | |
302 | /* null string ends the list */NULL\r | |
303 | }\r | |
304 | };\r | |
305 | \r | |
306 | PCI_CLASS_ENTRY PCISubClass_02[] = {\r | |
307 | {\r | |
308 | 0x00,\r | |
309 | L"Ethernet controller",\r | |
310 | PCIBlankEntry\r | |
311 | },\r | |
312 | {\r | |
313 | 0x01,\r | |
314 | L"Token ring controller",\r | |
315 | PCIBlankEntry\r | |
316 | },\r | |
317 | {\r | |
318 | 0x02,\r | |
319 | L"FDDI controller",\r | |
320 | PCIBlankEntry\r | |
321 | },\r | |
322 | {\r | |
323 | 0x03,\r | |
324 | L"ATM controller",\r | |
325 | PCIBlankEntry\r | |
326 | },\r | |
327 | {\r | |
328 | 0x04,\r | |
329 | L"ISDN controller",\r | |
330 | PCIBlankEntry\r | |
331 | },\r | |
f056e4c1 JC |
332 | {\r |
333 | 0x05,\r | |
334 | L"WorldFip controller",\r | |
335 | PCIBlankEntry\r | |
336 | },\r | |
337 | {\r | |
338 | 0x06,\r | |
339 | L"PICMG 2.14 Multi Computing",\r | |
340 | PCIBlankEntry\r | |
341 | },\r | |
342 | {\r | |
343 | 0x07,\r | |
344 | L"InfiniBand controller",\r | |
345 | PCIBlankEntry\r | |
346 | },\r | |
5d73d92f | 347 | {\r |
348 | 0x80,\r | |
349 | L"Other network controller",\r | |
350 | PCIBlankEntry\r | |
351 | },\r | |
352 | {\r | |
353 | 0x00,\r | |
354 | NULL,\r | |
355 | /* null string ends the list */NULL\r | |
356 | }\r | |
357 | };\r | |
358 | \r | |
359 | PCI_CLASS_ENTRY PCISubClass_03[] = {\r | |
360 | {\r | |
361 | 0x00,\r | |
362 | L"VGA/8514 controller",\r | |
363 | PCIPIFClass_0300\r | |
364 | },\r | |
365 | {\r | |
366 | 0x01,\r | |
367 | L"XGA controller",\r | |
368 | PCIBlankEntry\r | |
369 | },\r | |
370 | {\r | |
371 | 0x02,\r | |
372 | L"3D controller",\r | |
373 | PCIBlankEntry\r | |
374 | },\r | |
375 | {\r | |
376 | 0x80,\r | |
377 | L"Other display controller",\r | |
378 | PCIBlankEntry\r | |
379 | },\r | |
380 | {\r | |
381 | 0x00,\r | |
382 | NULL,\r | |
383 | /* null string ends the list */PCIBlankEntry\r | |
384 | }\r | |
385 | };\r | |
386 | \r | |
387 | PCI_CLASS_ENTRY PCISubClass_04[] = {\r | |
388 | {\r | |
389 | 0x00,\r | |
390 | L"Video device",\r | |
391 | PCIBlankEntry\r | |
392 | },\r | |
393 | {\r | |
394 | 0x01,\r | |
395 | L"Audio device",\r | |
396 | PCIBlankEntry\r | |
397 | },\r | |
398 | {\r | |
399 | 0x02,\r | |
400 | L"Computer Telephony device",\r | |
401 | PCIBlankEntry\r | |
402 | },\r | |
f056e4c1 JC |
403 | {\r |
404 | 0x03,\r | |
405 | L"Mixed mode device",\r | |
406 | PCIBlankEntry\r | |
407 | },\r | |
5d73d92f | 408 | {\r |
409 | 0x80,\r | |
410 | L"Other multimedia device",\r | |
411 | PCIBlankEntry\r | |
412 | },\r | |
413 | {\r | |
414 | 0x00,\r | |
415 | NULL,\r | |
416 | /* null string ends the list */NULL\r | |
417 | }\r | |
418 | };\r | |
419 | \r | |
420 | PCI_CLASS_ENTRY PCISubClass_05[] = {\r | |
421 | {\r | |
422 | 0x00,\r | |
423 | L"RAM memory controller",\r | |
424 | PCIBlankEntry\r | |
425 | },\r | |
426 | {\r | |
427 | 0x01,\r | |
428 | L"Flash memory controller",\r | |
429 | PCIBlankEntry\r | |
430 | },\r | |
431 | {\r | |
432 | 0x80,\r | |
433 | L"Other memory controller",\r | |
434 | PCIBlankEntry\r | |
435 | },\r | |
436 | {\r | |
437 | 0x00,\r | |
438 | NULL,\r | |
439 | /* null string ends the list */NULL\r | |
440 | }\r | |
441 | };\r | |
442 | \r | |
443 | PCI_CLASS_ENTRY PCISubClass_06[] = {\r | |
444 | {\r | |
445 | 0x00,\r | |
446 | L"Host/PCI bridge",\r | |
447 | PCIBlankEntry\r | |
448 | },\r | |
449 | {\r | |
450 | 0x01,\r | |
451 | L"PCI/ISA bridge",\r | |
452 | PCIBlankEntry\r | |
453 | },\r | |
454 | {\r | |
455 | 0x02,\r | |
456 | L"PCI/EISA bridge",\r | |
457 | PCIBlankEntry\r | |
458 | },\r | |
459 | {\r | |
460 | 0x03,\r | |
461 | L"PCI/Micro Channel bridge",\r | |
462 | PCIBlankEntry\r | |
463 | },\r | |
464 | {\r | |
465 | 0x04,\r | |
466 | L"PCI/PCI bridge",\r | |
467 | PCIPIFClass_0604\r | |
468 | },\r | |
469 | {\r | |
470 | 0x05,\r | |
471 | L"PCI/PCMCIA bridge",\r | |
472 | PCIBlankEntry\r | |
473 | },\r | |
474 | {\r | |
475 | 0x06,\r | |
476 | L"NuBus bridge",\r | |
477 | PCIBlankEntry\r | |
478 | },\r | |
479 | {\r | |
480 | 0x07,\r | |
481 | L"CardBus bridge",\r | |
482 | PCIBlankEntry\r | |
483 | },\r | |
484 | {\r | |
485 | 0x08,\r | |
486 | L"RACEway bridge",\r | |
487 | PCIBlankEntry\r | |
488 | },\r | |
f056e4c1 JC |
489 | {\r |
490 | 0x09,\r | |
491 | L"Semi-transparent PCI-to-PCI bridge",\r | |
492 | PCIPIFClass_0609\r | |
493 | },\r | |
494 | {\r | |
495 | 0x0A,\r | |
496 | L"InfiniBand-to-PCI host bridge",\r | |
497 | PCIBlankEntry\r | |
498 | },\r | |
499 | {\r | |
500 | 0x0B,\r | |
501 | L"Advanced Switching to PCI host bridge",\r | |
502 | PCIPIFClass_060b\r | |
503 | },\r | |
5d73d92f | 504 | {\r |
505 | 0x80,\r | |
506 | L"Other bridge type",\r | |
507 | PCIBlankEntry\r | |
508 | },\r | |
509 | {\r | |
510 | 0x00,\r | |
511 | NULL,\r | |
512 | /* null string ends the list */NULL\r | |
513 | }\r | |
514 | };\r | |
515 | \r | |
516 | PCI_CLASS_ENTRY PCISubClass_07[] = {\r | |
517 | {\r | |
518 | 0x00,\r | |
519 | L"Serial controller",\r | |
520 | PCIPIFClass_0700\r | |
521 | },\r | |
522 | {\r | |
523 | 0x01,\r | |
524 | L"Parallel port",\r | |
525 | PCIPIFClass_0701\r | |
526 | },\r | |
527 | {\r | |
528 | 0x02,\r | |
529 | L"Multiport serial controller",\r | |
530 | PCIBlankEntry\r | |
531 | },\r | |
532 | {\r | |
533 | 0x03,\r | |
534 | L"Modem",\r | |
535 | PCIPIFClass_0703\r | |
536 | },\r | |
f056e4c1 JC |
537 | {\r |
538 | 0x04,\r | |
539 | L"GPIB (IEEE 488.1/2) controller",\r | |
540 | PCIBlankEntry\r | |
541 | },\r | |
542 | {\r | |
543 | 0x05,\r | |
544 | L"Smart Card",\r | |
545 | PCIBlankEntry\r | |
546 | },\r | |
5d73d92f | 547 | {\r |
548 | 0x80,\r | |
549 | L"Other communication device",\r | |
550 | PCIBlankEntry\r | |
551 | },\r | |
552 | {\r | |
553 | 0x00,\r | |
554 | NULL,\r | |
555 | /* null string ends the list */NULL\r | |
556 | }\r | |
557 | };\r | |
558 | \r | |
559 | PCI_CLASS_ENTRY PCISubClass_08[] = {\r | |
560 | {\r | |
561 | 0x00,\r | |
562 | L"PIC",\r | |
563 | PCIPIFClass_0800\r | |
564 | },\r | |
565 | {\r | |
566 | 0x01,\r | |
567 | L"DMA controller",\r | |
568 | PCIPIFClass_0801\r | |
569 | },\r | |
570 | {\r | |
571 | 0x02,\r | |
572 | L"System timer",\r | |
573 | PCIPIFClass_0802\r | |
574 | },\r | |
575 | {\r | |
576 | 0x03,\r | |
577 | L"RTC controller",\r | |
578 | PCIPIFClass_0803\r | |
579 | },\r | |
580 | {\r | |
581 | 0x04,\r | |
582 | L"Generic PCI Hot-Plug controller",\r | |
583 | PCIBlankEntry\r | |
584 | },\r | |
f056e4c1 JC |
585 | {\r |
586 | 0x05,\r | |
587 | L"SD Host controller",\r | |
588 | PCIBlankEntry\r | |
589 | },\r | |
590 | {\r | |
591 | 0x06,\r | |
592 | L"IOMMU",\r | |
593 | PCIBlankEntry\r | |
594 | },\r | |
595 | {\r | |
596 | 0x07,\r | |
597 | L"Root Complex Event Collector",\r | |
598 | PCIBlankEntry\r | |
599 | },\r | |
5d73d92f | 600 | {\r |
601 | 0x80,\r | |
602 | L"Other system peripheral",\r | |
603 | PCIBlankEntry\r | |
604 | },\r | |
605 | {\r | |
606 | 0x00,\r | |
607 | NULL,\r | |
608 | /* null string ends the list */NULL\r | |
609 | }\r | |
610 | };\r | |
611 | \r | |
612 | PCI_CLASS_ENTRY PCISubClass_09[] = {\r | |
613 | {\r | |
614 | 0x00,\r | |
615 | L"Keyboard controller",\r | |
616 | PCIBlankEntry\r | |
617 | },\r | |
618 | {\r | |
619 | 0x01,\r | |
620 | L"Digitizer (pen)",\r | |
621 | PCIBlankEntry\r | |
622 | },\r | |
623 | {\r | |
624 | 0x02,\r | |
625 | L"Mouse controller",\r | |
626 | PCIBlankEntry\r | |
627 | },\r | |
628 | {\r | |
629 | 0x03,\r | |
630 | L"Scanner controller",\r | |
631 | PCIBlankEntry\r | |
632 | },\r | |
633 | {\r | |
634 | 0x04,\r | |
635 | L"Gameport controller",\r | |
636 | PCIPIFClass_0904\r | |
637 | },\r | |
638 | {\r | |
639 | 0x80,\r | |
640 | L"Other input controller",\r | |
641 | PCIBlankEntry\r | |
642 | },\r | |
643 | {\r | |
644 | 0x00,\r | |
645 | NULL,\r | |
646 | /* null string ends the list */NULL\r | |
647 | }\r | |
648 | };\r | |
649 | \r | |
650 | PCI_CLASS_ENTRY PCISubClass_0a[] = {\r | |
651 | {\r | |
652 | 0x00,\r | |
653 | L"Generic docking station",\r | |
654 | PCIBlankEntry\r | |
655 | },\r | |
656 | {\r | |
657 | 0x80,\r | |
658 | L"Other type of docking station",\r | |
659 | PCIBlankEntry\r | |
660 | },\r | |
661 | {\r | |
662 | 0x00,\r | |
663 | NULL,\r | |
664 | /* null string ends the list */NULL\r | |
665 | }\r | |
666 | };\r | |
667 | \r | |
668 | PCI_CLASS_ENTRY PCISubClass_0b[] = {\r | |
669 | {\r | |
670 | 0x00,\r | |
671 | L"386",\r | |
672 | PCIBlankEntry\r | |
673 | },\r | |
674 | {\r | |
675 | 0x01,\r | |
676 | L"486",\r | |
677 | PCIBlankEntry\r | |
678 | },\r | |
679 | {\r | |
680 | 0x02,\r | |
681 | L"Pentium",\r | |
682 | PCIBlankEntry\r | |
683 | },\r | |
684 | {\r | |
685 | 0x10,\r | |
686 | L"Alpha",\r | |
687 | PCIBlankEntry\r | |
688 | },\r | |
689 | {\r | |
690 | 0x20,\r | |
691 | L"PowerPC",\r | |
692 | PCIBlankEntry\r | |
693 | },\r | |
694 | {\r | |
695 | 0x30,\r | |
696 | L"MIPS",\r | |
697 | PCIBlankEntry\r | |
698 | },\r | |
699 | {\r | |
700 | 0x40,\r | |
701 | L"Co-processor",\r | |
702 | PCIBlankEntry\r | |
703 | },\r | |
704 | {\r | |
705 | 0x80,\r | |
706 | L"Other processor",\r | |
707 | PCIBlankEntry\r | |
708 | },\r | |
709 | {\r | |
710 | 0x00,\r | |
711 | NULL,\r | |
712 | /* null string ends the list */NULL\r | |
713 | }\r | |
714 | };\r | |
715 | \r | |
716 | PCI_CLASS_ENTRY PCISubClass_0c[] = {\r | |
717 | {\r | |
718 | 0x00,\r | |
f056e4c1 JC |
719 | L"IEEE 1394",\r |
720 | PCIPIFClass_0c00\r | |
5d73d92f | 721 | },\r |
722 | {\r | |
723 | 0x01,\r | |
724 | L"ACCESS.bus",\r | |
725 | PCIBlankEntry\r | |
726 | },\r | |
727 | {\r | |
728 | 0x02,\r | |
729 | L"SSA",\r | |
730 | PCIBlankEntry\r | |
731 | },\r | |
732 | {\r | |
733 | 0x03,\r | |
734 | L"USB",\r | |
f056e4c1 | 735 | PCIPIFClass_0c03\r |
5d73d92f | 736 | },\r |
737 | {\r | |
738 | 0x04,\r | |
739 | L"Fibre Channel",\r | |
740 | PCIBlankEntry\r | |
741 | },\r | |
742 | {\r | |
743 | 0x05,\r | |
744 | L"System Management Bus",\r | |
745 | PCIBlankEntry\r | |
746 | },\r | |
f056e4c1 JC |
747 | {\r |
748 | 0x06,\r | |
749 | L"InfiniBand",\r | |
750 | PCIBlankEntry\r | |
751 | },\r | |
752 | {\r | |
753 | 0x07,\r | |
754 | L"IPMI",\r | |
755 | PCIPIFClass_0c07\r | |
756 | },\r | |
757 | {\r | |
758 | 0x08,\r | |
759 | L"SERCOS Interface Standard (IEC 61491)",\r | |
760 | PCIBlankEntry\r | |
761 | },\r | |
762 | {\r | |
763 | 0x09,\r | |
764 | L"CANbus",\r | |
765 | PCIBlankEntry\r | |
766 | },\r | |
5d73d92f | 767 | {\r |
768 | 0x80,\r | |
769 | L"Other bus type",\r | |
770 | PCIBlankEntry\r | |
771 | },\r | |
772 | {\r | |
773 | 0x00,\r | |
774 | NULL,\r | |
775 | /* null string ends the list */NULL\r | |
776 | }\r | |
777 | };\r | |
778 | \r | |
779 | PCI_CLASS_ENTRY PCISubClass_0d[] = {\r | |
780 | {\r | |
781 | 0x00,\r | |
782 | L"iRDA compatible controller",\r | |
783 | PCIBlankEntry\r | |
784 | },\r | |
785 | {\r | |
786 | 0x01,\r | |
f056e4c1 JC |
787 | L"",\r |
788 | PCIPIFClass_0d01\r | |
5d73d92f | 789 | },\r |
790 | {\r | |
791 | 0x10,\r | |
792 | L"RF controller",\r | |
793 | PCIBlankEntry\r | |
794 | },\r | |
f056e4c1 JC |
795 | {\r |
796 | 0x11,\r | |
797 | L"Bluetooth",\r | |
798 | PCIBlankEntry\r | |
799 | },\r | |
800 | {\r | |
801 | 0x12,\r | |
802 | L"Broadband",\r | |
803 | PCIBlankEntry\r | |
804 | },\r | |
805 | {\r | |
806 | 0x20,\r | |
59577231 | 807 | L"Ethernet (802.11a - 5 GHz)",\r |
f056e4c1 JC |
808 | PCIBlankEntry\r |
809 | },\r | |
810 | {\r | |
811 | 0x21,\r | |
59577231 | 812 | L"Ethernet (802.11b - 2.4 GHz)",\r |
f056e4c1 JC |
813 | PCIBlankEntry\r |
814 | },\r | |
5d73d92f | 815 | {\r |
816 | 0x80,\r | |
817 | L"Other type of wireless controller",\r | |
818 | PCIBlankEntry\r | |
819 | },\r | |
820 | {\r | |
821 | 0x00,\r | |
822 | NULL,\r | |
823 | /* null string ends the list */NULL\r | |
824 | }\r | |
825 | };\r | |
826 | \r | |
827 | PCI_CLASS_ENTRY PCISubClass_0e[] = {\r | |
828 | {\r | |
829 | 0x00,\r | |
830 | L"I2O Architecture",\r | |
831 | PCIPIFClass_0e00\r | |
832 | },\r | |
833 | {\r | |
834 | 0x00,\r | |
835 | NULL,\r | |
836 | /* null string ends the list */NULL\r | |
837 | }\r | |
838 | };\r | |
839 | \r | |
840 | PCI_CLASS_ENTRY PCISubClass_0f[] = {\r | |
841 | {\r | |
f056e4c1 | 842 | 0x01,\r |
5d73d92f | 843 | L"TV",\r |
844 | PCIBlankEntry\r | |
845 | },\r | |
846 | {\r | |
f056e4c1 | 847 | 0x02,\r |
5d73d92f | 848 | L"Audio",\r |
849 | PCIBlankEntry\r | |
850 | },\r | |
851 | {\r | |
f056e4c1 | 852 | 0x03,\r |
5d73d92f | 853 | L"Voice",\r |
854 | PCIBlankEntry\r | |
855 | },\r | |
856 | {\r | |
f056e4c1 | 857 | 0x04,\r |
5d73d92f | 858 | L"Data",\r |
859 | PCIBlankEntry\r | |
860 | },\r | |
f056e4c1 JC |
861 | {\r |
862 | 0x80,\r | |
863 | L"Other satellite communication controller",\r | |
864 | PCIBlankEntry\r | |
865 | },\r | |
5d73d92f | 866 | {\r |
867 | 0x00,\r | |
868 | NULL,\r | |
869 | /* null string ends the list */NULL\r | |
870 | }\r | |
871 | };\r | |
872 | \r | |
873 | PCI_CLASS_ENTRY PCISubClass_10[] = {\r | |
874 | {\r | |
875 | 0x00,\r | |
876 | L"Network & computing Encrypt/Decrypt",\r | |
877 | PCIBlankEntry\r | |
878 | },\r | |
879 | {\r | |
880 | 0x01,\r | |
881 | L"Entertainment Encrypt/Decrypt",\r | |
882 | PCIBlankEntry\r | |
883 | },\r | |
884 | {\r | |
885 | 0x80,\r | |
886 | L"Other Encrypt/Decrypt",\r | |
887 | PCIBlankEntry\r | |
888 | },\r | |
889 | {\r | |
890 | 0x00,\r | |
891 | NULL,\r | |
892 | /* null string ends the list */NULL\r | |
893 | }\r | |
894 | };\r | |
895 | \r | |
896 | PCI_CLASS_ENTRY PCISubClass_11[] = {\r | |
897 | {\r | |
898 | 0x00,\r | |
899 | L"DPIO modules",\r | |
900 | PCIBlankEntry\r | |
901 | },\r | |
f056e4c1 JC |
902 | {\r |
903 | 0x01,\r | |
904 | L"Performance Counters",\r | |
905 | PCIBlankEntry\r | |
906 | },\r | |
907 | {\r | |
908 | 0x10,\r | |
909 | L"Communications synchronization plus time and frequency test/measurement ",\r | |
910 | PCIBlankEntry\r | |
911 | },\r | |
912 | {\r | |
913 | 0x20,\r | |
914 | L"Management card",\r | |
915 | PCIBlankEntry\r | |
916 | },\r | |
5d73d92f | 917 | {\r |
918 | 0x80,\r | |
919 | L"Other DAQ & SP controllers",\r | |
920 | PCIBlankEntry\r | |
921 | },\r | |
922 | {\r | |
923 | 0x00,\r | |
924 | NULL,\r | |
925 | /* null string ends the list */NULL\r | |
926 | }\r | |
927 | };\r | |
928 | \r | |
f056e4c1 JC |
929 | PCI_CLASS_ENTRY PCISubClass_12[] = {\r |
930 | {\r | |
931 | 0x00,\r | |
932 | L"Processing Accelerator",\r | |
933 | PCIBlankEntry\r | |
934 | },\r | |
935 | {\r | |
936 | 0x00,\r | |
937 | NULL,\r | |
938 | /* null string ends the list */NULL\r | |
939 | }\r | |
940 | };\r | |
941 | \r | |
942 | PCI_CLASS_ENTRY PCISubClass_13[] = {\r | |
943 | {\r | |
944 | 0x00,\r | |
945 | L"Non-Essential Instrumentation Function",\r | |
946 | PCIBlankEntry\r | |
947 | },\r | |
948 | {\r | |
949 | 0x00,\r | |
950 | NULL,\r | |
951 | /* null string ends the list */NULL\r | |
952 | }\r | |
953 | };\r | |
954 | \r | |
5d73d92f | 955 | //\r |
956 | // Programming Interface entries\r | |
957 | //\r | |
f056e4c1 JC |
958 | PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r |
959 | {\r | |
960 | 0x00,\r | |
961 | L"SCSI controller",\r | |
962 | PCIBlankEntry\r | |
963 | },\r | |
964 | {\r | |
965 | 0x11,\r | |
966 | L"SCSI storage device SOP using PQI",\r | |
967 | PCIBlankEntry\r | |
968 | },\r | |
969 | {\r | |
970 | 0x12,\r | |
971 | L"SCSI controller SOP using PQI",\r | |
972 | PCIBlankEntry\r | |
973 | },\r | |
974 | {\r | |
975 | 0x13,\r | |
976 | L"SCSI storage device and controller SOP using PQI",\r | |
977 | PCIBlankEntry\r | |
978 | },\r | |
979 | {\r | |
980 | 0x21,\r | |
981 | L"SCSI storage device SOP using NVMe",\r | |
982 | PCIBlankEntry\r | |
983 | },\r | |
984 | {\r | |
985 | 0x00,\r | |
986 | NULL,\r | |
987 | /* null string ends the list */NULL\r | |
988 | }\r | |
989 | };\r | |
990 | \r | |
5d73d92f | 991 | PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r |
992 | {\r | |
993 | 0x00,\r | |
994 | L"",\r | |
995 | PCIBlankEntry\r | |
996 | },\r | |
997 | {\r | |
998 | 0x01,\r | |
999 | L"OM-primary",\r | |
1000 | PCIBlankEntry\r | |
1001 | },\r | |
1002 | {\r | |
1003 | 0x02,\r | |
1004 | L"PI-primary",\r | |
1005 | PCIBlankEntry\r | |
1006 | },\r | |
1007 | {\r | |
1008 | 0x03,\r | |
1009 | L"OM/PI-primary",\r | |
1010 | PCIBlankEntry\r | |
1011 | },\r | |
1012 | {\r | |
1013 | 0x04,\r | |
1014 | L"OM-secondary",\r | |
1015 | PCIBlankEntry\r | |
1016 | },\r | |
1017 | {\r | |
1018 | 0x05,\r | |
1019 | L"OM-primary, OM-secondary",\r | |
1020 | PCIBlankEntry\r | |
1021 | },\r | |
1022 | {\r | |
1023 | 0x06,\r | |
1024 | L"PI-primary, OM-secondary",\r | |
1025 | PCIBlankEntry\r | |
1026 | },\r | |
1027 | {\r | |
1028 | 0x07,\r | |
1029 | L"OM/PI-primary, OM-secondary",\r | |
1030 | PCIBlankEntry\r | |
1031 | },\r | |
1032 | {\r | |
1033 | 0x08,\r | |
1034 | L"OM-secondary",\r | |
1035 | PCIBlankEntry\r | |
1036 | },\r | |
1037 | {\r | |
1038 | 0x09,\r | |
1039 | L"OM-primary, PI-secondary",\r | |
1040 | PCIBlankEntry\r | |
1041 | },\r | |
1042 | {\r | |
1043 | 0x0a,\r | |
1044 | L"PI-primary, PI-secondary",\r | |
1045 | PCIBlankEntry\r | |
1046 | },\r | |
1047 | {\r | |
1048 | 0x0b,\r | |
1049 | L"OM/PI-primary, PI-secondary",\r | |
1050 | PCIBlankEntry\r | |
1051 | },\r | |
1052 | {\r | |
1053 | 0x0c,\r | |
1054 | L"OM-secondary",\r | |
1055 | PCIBlankEntry\r | |
1056 | },\r | |
1057 | {\r | |
1058 | 0x0d,\r | |
1059 | L"OM-primary, OM/PI-secondary",\r | |
1060 | PCIBlankEntry\r | |
1061 | },\r | |
1062 | {\r | |
1063 | 0x0e,\r | |
1064 | L"PI-primary, OM/PI-secondary",\r | |
1065 | PCIBlankEntry\r | |
1066 | },\r | |
1067 | {\r | |
1068 | 0x0f,\r | |
1069 | L"OM/PI-primary, OM/PI-secondary",\r | |
1070 | PCIBlankEntry\r | |
1071 | },\r | |
1072 | {\r | |
1073 | 0x80,\r | |
1074 | L"Master",\r | |
1075 | PCIBlankEntry\r | |
1076 | },\r | |
1077 | {\r | |
1078 | 0x81,\r | |
1079 | L"Master, OM-primary",\r | |
1080 | PCIBlankEntry\r | |
1081 | },\r | |
1082 | {\r | |
1083 | 0x82,\r | |
1084 | L"Master, PI-primary",\r | |
1085 | PCIBlankEntry\r | |
1086 | },\r | |
1087 | {\r | |
1088 | 0x83,\r | |
1089 | L"Master, OM/PI-primary",\r | |
1090 | PCIBlankEntry\r | |
1091 | },\r | |
1092 | {\r | |
1093 | 0x84,\r | |
1094 | L"Master, OM-secondary",\r | |
1095 | PCIBlankEntry\r | |
1096 | },\r | |
1097 | {\r | |
1098 | 0x85,\r | |
1099 | L"Master, OM-primary, OM-secondary",\r | |
1100 | PCIBlankEntry\r | |
1101 | },\r | |
1102 | {\r | |
1103 | 0x86,\r | |
1104 | L"Master, PI-primary, OM-secondary",\r | |
1105 | PCIBlankEntry\r | |
1106 | },\r | |
1107 | {\r | |
1108 | 0x87,\r | |
1109 | L"Master, OM/PI-primary, OM-secondary",\r | |
1110 | PCIBlankEntry\r | |
1111 | },\r | |
1112 | {\r | |
1113 | 0x88,\r | |
1114 | L"Master, OM-secondary",\r | |
1115 | PCIBlankEntry\r | |
1116 | },\r | |
1117 | {\r | |
1118 | 0x89,\r | |
1119 | L"Master, OM-primary, PI-secondary",\r | |
1120 | PCIBlankEntry\r | |
1121 | },\r | |
1122 | {\r | |
1123 | 0x8a,\r | |
1124 | L"Master, PI-primary, PI-secondary",\r | |
1125 | PCIBlankEntry\r | |
1126 | },\r | |
1127 | {\r | |
1128 | 0x8b,\r | |
1129 | L"Master, OM/PI-primary, PI-secondary",\r | |
1130 | PCIBlankEntry\r | |
1131 | },\r | |
1132 | {\r | |
1133 | 0x8c,\r | |
1134 | L"Master, OM-secondary",\r | |
1135 | PCIBlankEntry\r | |
1136 | },\r | |
1137 | {\r | |
1138 | 0x8d,\r | |
1139 | L"Master, OM-primary, OM/PI-secondary",\r | |
1140 | PCIBlankEntry\r | |
1141 | },\r | |
1142 | {\r | |
1143 | 0x8e,\r | |
1144 | L"Master, PI-primary, OM/PI-secondary",\r | |
1145 | PCIBlankEntry\r | |
1146 | },\r | |
1147 | {\r | |
1148 | 0x8f,\r | |
1149 | L"Master, OM/PI-primary, OM/PI-secondary",\r | |
1150 | PCIBlankEntry\r | |
1151 | },\r | |
1152 | {\r | |
1153 | 0x00,\r | |
1154 | NULL,\r | |
1155 | /* null string ends the list */NULL\r | |
1156 | }\r | |
1157 | };\r | |
1158 | \r | |
f056e4c1 JC |
1159 | PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r |
1160 | {\r | |
1161 | 0x20,\r | |
1162 | L"Single stepping",\r | |
1163 | PCIBlankEntry\r | |
1164 | },\r | |
1165 | {\r | |
1166 | 0x30,\r | |
1167 | L"Continuous operation",\r | |
1168 | PCIBlankEntry\r | |
1169 | },\r | |
1170 | {\r | |
1171 | 0x00,\r | |
1172 | NULL,\r | |
1173 | /* null string ends the list */NULL\r | |
1174 | }\r | |
1175 | };\r | |
1176 | \r | |
1177 | PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r | |
1178 | {\r | |
1179 | 0x00,\r | |
1180 | L"",\r | |
1181 | PCIBlankEntry\r | |
1182 | },\r | |
1183 | {\r | |
1184 | 0x01,\r | |
1185 | L"AHCI",\r | |
1186 | PCIBlankEntry\r | |
1187 | },\r | |
1188 | {\r | |
1189 | 0x02,\r | |
1190 | L"Serial Storage Bus",\r | |
1191 | PCIBlankEntry\r | |
1192 | },\r | |
1193 | {\r | |
1194 | 0x00,\r | |
1195 | NULL,\r | |
1196 | /* null string ends the list */NULL\r | |
1197 | }\r | |
1198 | };\r | |
1199 | \r | |
1200 | PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r | |
1201 | {\r | |
1202 | 0x00,\r | |
1203 | L"",\r | |
1204 | PCIBlankEntry\r | |
1205 | },\r | |
1206 | {\r | |
1207 | 0x01,\r | |
1208 | L"Obsolete",\r | |
1209 | PCIBlankEntry\r | |
1210 | },\r | |
1211 | {\r | |
1212 | 0x00,\r | |
1213 | NULL,\r | |
1214 | /* null string ends the list */NULL\r | |
1215 | }\r | |
1216 | };\r | |
1217 | \r | |
1218 | PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r | |
1219 | {\r | |
1220 | 0x00,\r | |
1221 | L"",\r | |
1222 | PCIBlankEntry\r | |
1223 | },\r | |
1224 | {\r | |
1225 | 0x01,\r | |
1226 | L"NVMHCI",\r | |
1227 | PCIBlankEntry\r | |
1228 | },\r | |
1229 | {\r | |
1230 | 0x02,\r | |
1231 | L"NVM Express",\r | |
1232 | PCIBlankEntry\r | |
1233 | },\r | |
1234 | {\r | |
1235 | 0x00,\r | |
1236 | NULL,\r | |
1237 | /* null string ends the list */NULL\r | |
1238 | }\r | |
1239 | };\r | |
1240 | \r | |
1241 | PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r | |
1242 | {\r | |
1243 | 0x00,\r | |
1244 | L"",\r | |
1245 | PCIBlankEntry\r | |
1246 | },\r | |
1247 | {\r | |
1248 | 0x01,\r | |
1249 | L"UFSHCI",\r | |
1250 | PCIBlankEntry\r | |
1251 | },\r | |
1252 | {\r | |
1253 | 0x00,\r | |
1254 | NULL,\r | |
1255 | /* null string ends the list */NULL\r | |
1256 | }\r | |
1257 | };\r | |
1258 | \r | |
5d73d92f | 1259 | PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r |
1260 | {\r | |
1261 | 0x00,\r | |
1262 | L"VGA compatible",\r | |
1263 | PCIBlankEntry\r | |
1264 | },\r | |
1265 | {\r | |
1266 | 0x01,\r | |
1267 | L"8514 compatible",\r | |
1268 | PCIBlankEntry\r | |
1269 | },\r | |
1270 | {\r | |
1271 | 0x00,\r | |
1272 | NULL,\r | |
1273 | /* null string ends the list */NULL\r | |
1274 | }\r | |
1275 | };\r | |
1276 | \r | |
1277 | PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r | |
1278 | {\r | |
1279 | 0x00,\r | |
1280 | L"",\r | |
1281 | PCIBlankEntry\r | |
1282 | },\r | |
1283 | {\r | |
1284 | 0x01,\r | |
1285 | L"Subtractive decode",\r | |
1286 | PCIBlankEntry\r | |
1287 | },\r | |
1288 | {\r | |
1289 | 0x00,\r | |
1290 | NULL,\r | |
1291 | /* null string ends the list */NULL\r | |
1292 | }\r | |
1293 | };\r | |
1294 | \r | |
f056e4c1 JC |
1295 | PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r |
1296 | {\r | |
1297 | 0x40,\r | |
1298 | L"Primary PCI bus side facing the system host processor",\r | |
1299 | PCIBlankEntry\r | |
1300 | },\r | |
1301 | {\r | |
1302 | 0x80,\r | |
1303 | L"Secondary PCI bus side facing the system host processor",\r | |
1304 | PCIBlankEntry\r | |
1305 | },\r | |
1306 | {\r | |
1307 | 0x00,\r | |
1308 | NULL,\r | |
1309 | /* null string ends the list */NULL\r | |
1310 | }\r | |
1311 | };\r | |
1312 | \r | |
1313 | PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r | |
1314 | {\r | |
1315 | 0x00,\r | |
1316 | L"Custom",\r | |
1317 | PCIBlankEntry\r | |
1318 | },\r | |
1319 | {\r | |
1320 | 0x01,\r | |
1321 | L"ASI-SIG Defined Portal",\r | |
1322 | PCIBlankEntry\r | |
1323 | },\r | |
1324 | {\r | |
1325 | 0x00,\r | |
1326 | NULL,\r | |
1327 | /* null string ends the list */NULL\r | |
1328 | }\r | |
1329 | };\r | |
1330 | \r | |
5d73d92f | 1331 | PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r |
1332 | {\r | |
1333 | 0x00,\r | |
1334 | L"Generic XT-compatible",\r | |
1335 | PCIBlankEntry\r | |
1336 | },\r | |
1337 | {\r | |
1338 | 0x01,\r | |
1339 | L"16450-compatible",\r | |
1340 | PCIBlankEntry\r | |
1341 | },\r | |
1342 | {\r | |
1343 | 0x02,\r | |
1344 | L"16550-compatible",\r | |
1345 | PCIBlankEntry\r | |
1346 | },\r | |
1347 | {\r | |
1348 | 0x03,\r | |
1349 | L"16650-compatible",\r | |
1350 | PCIBlankEntry\r | |
1351 | },\r | |
1352 | {\r | |
1353 | 0x04,\r | |
1354 | L"16750-compatible",\r | |
1355 | PCIBlankEntry\r | |
1356 | },\r | |
1357 | {\r | |
1358 | 0x05,\r | |
1359 | L"16850-compatible",\r | |
1360 | PCIBlankEntry\r | |
1361 | },\r | |
1362 | {\r | |
1363 | 0x06,\r | |
1364 | L"16950-compatible",\r | |
1365 | PCIBlankEntry\r | |
1366 | },\r | |
1367 | {\r | |
1368 | 0x00,\r | |
1369 | NULL,\r | |
1370 | /* null string ends the list */NULL\r | |
1371 | }\r | |
1372 | };\r | |
1373 | \r | |
1374 | PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r | |
1375 | {\r | |
1376 | 0x00,\r | |
1377 | L"",\r | |
1378 | PCIBlankEntry\r | |
1379 | },\r | |
1380 | {\r | |
1381 | 0x01,\r | |
1382 | L"Bi-directional",\r | |
1383 | PCIBlankEntry\r | |
1384 | },\r | |
1385 | {\r | |
1386 | 0x02,\r | |
1387 | L"ECP 1.X-compliant",\r | |
1388 | PCIBlankEntry\r | |
1389 | },\r | |
1390 | {\r | |
1391 | 0x03,\r | |
1392 | L"IEEE 1284",\r | |
1393 | PCIBlankEntry\r | |
1394 | },\r | |
1395 | {\r | |
1396 | 0xfe,\r | |
1397 | L"IEEE 1284 target (not a controller)",\r | |
1398 | PCIBlankEntry\r | |
1399 | },\r | |
1400 | {\r | |
1401 | 0x00,\r | |
1402 | NULL,\r | |
1403 | /* null string ends the list */NULL\r | |
1404 | }\r | |
1405 | };\r | |
1406 | \r | |
1407 | PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r | |
1408 | {\r | |
1409 | 0x00,\r | |
1410 | L"Generic",\r | |
1411 | PCIBlankEntry\r | |
1412 | },\r | |
1413 | {\r | |
1414 | 0x01,\r | |
1415 | L"Hayes-compatible 16450",\r | |
1416 | PCIBlankEntry\r | |
1417 | },\r | |
1418 | {\r | |
1419 | 0x02,\r | |
1420 | L"Hayes-compatible 16550",\r | |
1421 | PCIBlankEntry\r | |
1422 | },\r | |
1423 | {\r | |
1424 | 0x03,\r | |
1425 | L"Hayes-compatible 16650",\r | |
1426 | PCIBlankEntry\r | |
1427 | },\r | |
1428 | {\r | |
1429 | 0x04,\r | |
1430 | L"Hayes-compatible 16750",\r | |
1431 | PCIBlankEntry\r | |
1432 | },\r | |
1433 | {\r | |
1434 | 0x00,\r | |
1435 | NULL,\r | |
1436 | /* null string ends the list */NULL\r | |
1437 | }\r | |
1438 | };\r | |
1439 | \r | |
1440 | PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r | |
1441 | {\r | |
1442 | 0x00,\r | |
1443 | L"Generic 8259",\r | |
1444 | PCIBlankEntry\r | |
1445 | },\r | |
1446 | {\r | |
1447 | 0x01,\r | |
1448 | L"ISA",\r | |
1449 | PCIBlankEntry\r | |
1450 | },\r | |
1451 | {\r | |
1452 | 0x02,\r | |
1453 | L"EISA",\r | |
1454 | PCIBlankEntry\r | |
1455 | },\r | |
1456 | {\r | |
1457 | 0x10,\r | |
1458 | L"IO APIC",\r | |
1459 | PCIBlankEntry\r | |
1460 | },\r | |
1461 | {\r | |
1462 | 0x20,\r | |
1463 | L"IO(x) APIC interrupt controller",\r | |
1464 | PCIBlankEntry\r | |
1465 | },\r | |
1466 | {\r | |
1467 | 0x00,\r | |
1468 | NULL,\r | |
1469 | /* null string ends the list */NULL\r | |
1470 | }\r | |
1471 | };\r | |
1472 | \r | |
1473 | PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r | |
1474 | {\r | |
1475 | 0x00,\r | |
1476 | L"Generic 8237",\r | |
1477 | PCIBlankEntry\r | |
1478 | },\r | |
1479 | {\r | |
1480 | 0x01,\r | |
1481 | L"ISA",\r | |
1482 | PCIBlankEntry\r | |
1483 | },\r | |
1484 | {\r | |
1485 | 0x02,\r | |
1486 | L"EISA",\r | |
1487 | PCIBlankEntry\r | |
1488 | },\r | |
1489 | {\r | |
1490 | 0x00,\r | |
1491 | NULL,\r | |
1492 | /* null string ends the list */NULL\r | |
1493 | }\r | |
1494 | };\r | |
1495 | \r | |
1496 | PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r | |
1497 | {\r | |
1498 | 0x00,\r | |
1499 | L"Generic 8254",\r | |
1500 | PCIBlankEntry\r | |
1501 | },\r | |
1502 | {\r | |
1503 | 0x01,\r | |
1504 | L"ISA",\r | |
1505 | PCIBlankEntry\r | |
1506 | },\r | |
1507 | {\r | |
1508 | 0x02,\r | |
1509 | L"EISA",\r | |
1510 | PCIBlankEntry\r | |
1511 | },\r | |
1512 | {\r | |
1513 | 0x00,\r | |
1514 | NULL,\r | |
1515 | /* null string ends the list */NULL\r | |
1516 | }\r | |
1517 | };\r | |
1518 | \r | |
1519 | PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r | |
1520 | {\r | |
1521 | 0x00,\r | |
1522 | L"Generic",\r | |
1523 | PCIBlankEntry\r | |
1524 | },\r | |
1525 | {\r | |
1526 | 0x01,\r | |
1527 | L"ISA",\r | |
1528 | PCIBlankEntry\r | |
1529 | },\r | |
1530 | {\r | |
1531 | 0x02,\r | |
1532 | L"EISA",\r | |
1533 | PCIBlankEntry\r | |
1534 | },\r | |
1535 | {\r | |
1536 | 0x00,\r | |
1537 | NULL,\r | |
1538 | /* null string ends the list */NULL\r | |
1539 | }\r | |
1540 | };\r | |
1541 | \r | |
1542 | PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r | |
1543 | {\r | |
1544 | 0x00,\r | |
1545 | L"Generic",\r | |
1546 | PCIBlankEntry\r | |
1547 | },\r | |
1548 | {\r | |
1549 | 0x10,\r | |
1550 | L"",\r | |
1551 | PCIBlankEntry\r | |
1552 | },\r | |
1553 | {\r | |
1554 | 0x00,\r | |
1555 | NULL,\r | |
1556 | /* null string ends the list */NULL\r | |
1557 | }\r | |
1558 | };\r | |
1559 | \r | |
1560 | PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r | |
1561 | {\r | |
1562 | 0x00,\r | |
f056e4c1 JC |
1563 | L"",\r |
1564 | PCIBlankEntry\r | |
1565 | },\r | |
1566 | {\r | |
1567 | 0x10,\r | |
1568 | L"Using 1394 OpenHCI spec",\r | |
1569 | PCIBlankEntry\r | |
1570 | },\r | |
1571 | {\r | |
1572 | 0x00,\r | |
1573 | NULL,\r | |
1574 | /* null string ends the list */NULL\r | |
1575 | }\r | |
1576 | };\r | |
1577 | \r | |
1578 | PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r | |
1579 | {\r | |
1580 | 0x00,\r | |
1581 | L"UHCI",\r | |
5d73d92f | 1582 | PCIBlankEntry\r |
1583 | },\r | |
1584 | {\r | |
1585 | 0x10,\r | |
f056e4c1 JC |
1586 | L"OHCI",\r |
1587 | PCIBlankEntry\r | |
1588 | },\r | |
1589 | {\r | |
1590 | 0x20,\r | |
1591 | L"EHCI",\r | |
1592 | PCIBlankEntry\r | |
1593 | },\r | |
1594 | {\r | |
1595 | 0x30,\r | |
1596 | L"xHCI",\r | |
5d73d92f | 1597 | PCIBlankEntry\r |
1598 | },\r | |
1599 | {\r | |
1600 | 0x80,\r | |
1601 | L"No specific programming interface",\r | |
1602 | PCIBlankEntry\r | |
1603 | },\r | |
1604 | {\r | |
1605 | 0xfe,\r | |
1606 | L"(Not Host Controller)",\r | |
1607 | PCIBlankEntry\r | |
1608 | },\r | |
1609 | {\r | |
1610 | 0x00,\r | |
1611 | NULL,\r | |
1612 | /* null string ends the list */NULL\r | |
1613 | }\r | |
1614 | };\r | |
1615 | \r | |
f056e4c1 | 1616 | PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r |
5d73d92f | 1617 | {\r |
1618 | 0x00,\r | |
f056e4c1 JC |
1619 | L"SMIC",\r |
1620 | PCIBlankEntry\r | |
1621 | },\r | |
1622 | {\r | |
1623 | 0x01,\r | |
1624 | L"Keyboard Controller Style",\r | |
1625 | PCIBlankEntry\r | |
1626 | },\r | |
1627 | {\r | |
1628 | 0x02,\r | |
1629 | L"Block Transfer",\r | |
1630 | PCIBlankEntry\r | |
1631 | },\r | |
1632 | {\r | |
1633 | 0x00,\r | |
1634 | NULL,\r | |
1635 | /* null string ends the list */NULL\r | |
1636 | }\r | |
1637 | };\r | |
1638 | \r | |
1639 | PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r | |
1640 | {\r | |
1641 | 0x00,\r | |
1642 | L"Consumer IR controller",\r | |
5d73d92f | 1643 | PCIBlankEntry\r |
1644 | },\r | |
1645 | {\r | |
1646 | 0x10,\r | |
f056e4c1 | 1647 | L"UWB Radio controller",\r |
5d73d92f | 1648 | PCIBlankEntry\r |
1649 | },\r | |
1650 | {\r | |
1651 | 0x00,\r | |
1652 | NULL,\r | |
1653 | /* null string ends the list */NULL\r | |
1654 | }\r | |
1655 | };\r | |
1656 | \r | |
1657 | PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r | |
1658 | {\r | |
1659 | 0x00,\r | |
1660 | L"Message FIFO at offset 40h",\r | |
1661 | PCIBlankEntry\r | |
1662 | },\r | |
1663 | {\r | |
1664 | 0x01,\r | |
1665 | L"",\r | |
1666 | PCIBlankEntry\r | |
1667 | },\r | |
1668 | {\r | |
1669 | 0x00,\r | |
1670 | NULL,\r | |
1671 | /* null string ends the list */NULL\r | |
1672 | }\r | |
1673 | };\r | |
1674 | \r | |
5d73d92f | 1675 | \r |
a1d4bfcc | 1676 | /**\r |
5d73d92f | 1677 | Generates printable Unicode strings that represent PCI device class,\r |
1678 | subclass and programmed I/F based on a value passed to the function.\r | |
1679 | \r | |
a1d4bfcc | 1680 | @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r |
5d73d92f | 1681 | PCI device. The encodings are:\r |
1682 | bits 23:16 - Base Class Code\r | |
1683 | bits 15:8 - Sub-Class Code\r | |
1684 | bits 7:0 - Programming Interface\r | |
4ff7e37b | 1685 | @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r |
5d73d92f | 1686 | printable class strings corresponding to ClassCode. The\r |
1687 | caller must not modify the strings that are pointed by\r | |
1688 | the fields in ClassStrings.\r | |
5d73d92f | 1689 | **/\r |
a1d4bfcc | 1690 | VOID\r |
1691 | PciGetClassStrings (\r | |
1692 | IN UINT32 ClassCode,\r | |
1693 | IN OUT PCI_CLASS_STRINGS *ClassStrings\r | |
1694 | )\r | |
5d73d92f | 1695 | {\r |
1696 | INTN Index;\r | |
1697 | UINT8 Code;\r | |
1698 | PCI_CLASS_ENTRY *CurrentClass;\r | |
1699 | \r | |
1700 | //\r | |
1701 | // Assume no strings found\r | |
1702 | //\r | |
1703 | ClassStrings->BaseClass = L"UNDEFINED";\r | |
1704 | ClassStrings->SubClass = L"UNDEFINED";\r | |
1705 | ClassStrings->PIFClass = L"UNDEFINED";\r | |
1706 | \r | |
1707 | CurrentClass = gClassStringList;\r | |
1708 | Code = (UINT8) (ClassCode >> 16);\r | |
1709 | Index = 0;\r | |
1710 | \r | |
1711 | //\r | |
1712 | // Go through all entries of the base class, until the entry with a matching\r | |
1713 | // base class code is found. If reaches an entry with a null description\r | |
1714 | // text, the last entry is met, which means no text for the base class was\r | |
1715 | // found, so no more action is needed.\r | |
1716 | //\r | |
1717 | while (Code != CurrentClass[Index].Code) {\r | |
1718 | if (NULL == CurrentClass[Index].DescText) {\r | |
1719 | return ;\r | |
1720 | }\r | |
1721 | \r | |
1722 | Index++;\r | |
1723 | }\r | |
1724 | //\r | |
1725 | // A base class was found. Assign description, and check if this class has\r | |
1726 | // sub-class defined. If sub-class defined, no more action is needed,\r | |
1727 | // otherwise, continue to find description for the sub-class code.\r | |
1728 | //\r | |
1729 | ClassStrings->BaseClass = CurrentClass[Index].DescText;\r | |
1730 | if (NULL == CurrentClass[Index].LowerLevelClass) {\r | |
1731 | return ;\r | |
1732 | }\r | |
1733 | //\r | |
1734 | // find Subclass entry\r | |
1735 | //\r | |
1736 | CurrentClass = CurrentClass[Index].LowerLevelClass;\r | |
1737 | Code = (UINT8) (ClassCode >> 8);\r | |
1738 | Index = 0;\r | |
1739 | \r | |
1740 | //\r | |
1741 | // Go through all entries of the sub-class, until the entry with a matching\r | |
1742 | // sub-class code is found. If reaches an entry with a null description\r | |
1743 | // text, the last entry is met, which means no text for the sub-class was\r | |
1744 | // found, so no more action is needed.\r | |
1745 | //\r | |
1746 | while (Code != CurrentClass[Index].Code) {\r | |
1747 | if (NULL == CurrentClass[Index].DescText) {\r | |
1748 | return ;\r | |
1749 | }\r | |
1750 | \r | |
1751 | Index++;\r | |
1752 | }\r | |
1753 | //\r | |
1754 | // A class was found for the sub-class code. Assign description, and check if\r | |
1755 | // this sub-class has programming interface defined. If no, no more action is\r | |
1756 | // needed, otherwise, continue to find description for the programming\r | |
1757 | // interface.\r | |
1758 | //\r | |
1759 | ClassStrings->SubClass = CurrentClass[Index].DescText;\r | |
1760 | if (NULL == CurrentClass[Index].LowerLevelClass) {\r | |
1761 | return ;\r | |
1762 | }\r | |
1763 | //\r | |
1764 | // Find programming interface entry\r | |
1765 | //\r | |
1766 | CurrentClass = CurrentClass[Index].LowerLevelClass;\r | |
1767 | Code = (UINT8) ClassCode;\r | |
1768 | Index = 0;\r | |
1769 | \r | |
1770 | //\r | |
1771 | // Go through all entries of the I/F entries, until the entry with a\r | |
1772 | // matching I/F code is found. If reaches an entry with a null description\r | |
1773 | // text, the last entry is met, which means no text was found, so no more\r | |
1774 | // action is needed.\r | |
1775 | //\r | |
1776 | while (Code != CurrentClass[Index].Code) {\r | |
1777 | if (NULL == CurrentClass[Index].DescText) {\r | |
1778 | return ;\r | |
1779 | }\r | |
1780 | \r | |
1781 | Index++;\r | |
1782 | }\r | |
1783 | //\r | |
1784 | // A class was found for the I/F code. Assign description, done!\r | |
1785 | //\r | |
1786 | ClassStrings->PIFClass = CurrentClass[Index].DescText;\r | |
1787 | return ;\r | |
1788 | }\r | |
1789 | \r | |
a1d4bfcc | 1790 | /**\r |
1791 | Print strings that represent PCI device class, subclass and programmed I/F.\r | |
1792 | \r | |
1793 | @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r | |
e8a57ade | 1794 | configuration space.\r |
a1d4bfcc | 1795 | @param[in] IncludePIF If the printed string should include the programming I/F part\r |
1796 | **/\r | |
5d73d92f | 1797 | VOID\r |
1798 | PciPrintClassCode (\r | |
1799 | IN UINT8 *ClassCodePtr,\r | |
1800 | IN BOOLEAN IncludePIF\r | |
1801 | )\r | |
5d73d92f | 1802 | {\r |
1803 | UINT32 ClassCode;\r | |
1804 | PCI_CLASS_STRINGS ClassStrings;\r | |
5d73d92f | 1805 | \r |
1806 | ClassCode = 0;\r | |
e8a57ade JC |
1807 | ClassCode |= (UINT32)ClassCodePtr[0];\r |
1808 | ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r | |
1809 | ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r | |
5d73d92f | 1810 | \r |
1811 | //\r | |
1812 | // Get name from class code\r | |
1813 | //\r | |
1814 | PciGetClassStrings (ClassCode, &ClassStrings);\r | |
1815 | \r | |
1816 | if (IncludePIF) {\r | |
1817 | //\r | |
c37e0f16 | 1818 | // Print base class, sub class, and programming inferface name\r |
5d73d92f | 1819 | //\r |
c37e0f16 | 1820 | ShellPrintEx (-1, -1, L"%s - %s - %s",\r |
5d73d92f | 1821 | ClassStrings.BaseClass,\r |
1822 | ClassStrings.SubClass,\r | |
1823 | ClassStrings.PIFClass\r | |
1824 | );\r | |
1825 | \r | |
1826 | } else {\r | |
1827 | //\r | |
c37e0f16 | 1828 | // Only print base class and sub class name\r |
5d73d92f | 1829 | //\r |
c37e0f16 | 1830 | ShellPrintEx (-1, -1, L"%s - %s",\r |
5d73d92f | 1831 | ClassStrings.BaseClass,\r |
1832 | ClassStrings.SubClass\r | |
c37e0f16 | 1833 | );\r |
5d73d92f | 1834 | }\r |
1835 | }\r | |
1836 | \r | |
a1d4bfcc | 1837 | /**\r |
1838 | This function finds out the protocol which is in charge of the given\r | |
1839 | segment, and its bus range covers the current bus number. It lookes\r | |
1840 | each instances of RootBridgeIoProtocol handle, until the one meets the\r | |
1841 | criteria is found.\r | |
1842 | \r | |
1843 | @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
1844 | @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
1845 | @param[in] Segment Segment number of device we are dealing with.\r | |
1846 | @param[in] Bus Bus number of device we are dealing with.\r | |
1847 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
1848 | \r | |
1849 | @retval EFI_SUCCESS The command completed successfully.\r | |
1850 | @retval EFI_INVALID_PARAMETER Invalid parameter.\r | |
5d73d92f | 1851 | \r |
a1d4bfcc | 1852 | **/\r |
5d73d92f | 1853 | EFI_STATUS\r |
1854 | PciFindProtocolInterface (\r | |
1855 | IN EFI_HANDLE *HandleBuf,\r | |
1856 | IN UINTN HandleCount,\r | |
1857 | IN UINT16 Segment,\r | |
1858 | IN UINT16 Bus,\r | |
1859 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r | |
1860 | );\r | |
1861 | \r | |
a1d4bfcc | 1862 | /**\r |
1863 | This function gets the protocol interface from the given handle, and\r | |
1864 | obtains its address space descriptors.\r | |
1865 | \r | |
1866 | @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r | |
1867 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
1868 | @param[out] Descriptors Points to the address space descriptors.\r | |
1869 | \r | |
1870 | @retval EFI_SUCCESS The command completed successfully\r | |
1871 | **/\r | |
5d73d92f | 1872 | EFI_STATUS\r |
1873 | PciGetProtocolAndResource (\r | |
1874 | IN EFI_HANDLE Handle,\r | |
1875 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r | |
1876 | OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r | |
1877 | );\r | |
1878 | \r | |
a1d4bfcc | 1879 | /**\r |
1880 | This function get the next bus range of given address space descriptors.\r | |
1881 | It also moves the pointer backward a node, to get prepared to be called\r | |
1882 | again.\r | |
1883 | \r | |
4ff7e37b ED |
1884 | @param[in, out] Descriptors Points to current position of a serial of address space\r |
1885 | descriptors.\r | |
1886 | @param[out] MinBus The lower range of bus number.\r | |
1887 | @param[out] MaxBus The upper range of bus number.\r | |
1888 | @param[out] IsEnd Meet end of the serial of descriptors.\r | |
a1d4bfcc | 1889 | \r |
1890 | @retval EFI_SUCCESS The command completed successfully.\r | |
1891 | **/\r | |
5d73d92f | 1892 | EFI_STATUS\r |
1893 | PciGetNextBusRange (\r | |
1894 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r | |
1895 | OUT UINT16 *MinBus,\r | |
1896 | OUT UINT16 *MaxBus,\r | |
1897 | OUT BOOLEAN *IsEnd\r | |
1898 | );\r | |
1899 | \r | |
a1d4bfcc | 1900 | /**\r |
1901 | Explain the data in PCI configuration space. The part which is common for\r | |
1902 | PCI device and bridge is interpreted in this function. It calls other\r | |
1903 | functions to interpret data unique for device or bridge.\r | |
1904 | \r | |
1905 | @param[in] ConfigSpace Data in PCI configuration space.\r | |
1906 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1907 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
f614ce7e | 1908 | @param[in] EnhancedDump The print format for the dump data.\r |
a1d4bfcc | 1909 | \r |
1910 | @retval EFI_SUCCESS The command completed successfully.\r | |
1911 | **/\r | |
5d73d92f | 1912 | EFI_STATUS\r |
1913 | PciExplainData (\r | |
1914 | IN PCI_CONFIG_SPACE *ConfigSpace,\r | |
1915 | IN UINT64 Address,\r | |
705bffb5 JC |
1916 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r |
1917 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 1918 | );\r |
1919 | \r | |
a1d4bfcc | 1920 | /**\r |
1921 | Explain the device specific part of data in PCI configuration space.\r | |
1922 | \r | |
1923 | @param[in] Device Data in PCI configuration space.\r | |
1924 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1925 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1926 | \r | |
1927 | @retval EFI_SUCCESS The command completed successfully.\r | |
1928 | **/\r | |
5d73d92f | 1929 | EFI_STATUS\r |
1930 | PciExplainDeviceData (\r | |
1931 | IN PCI_DEVICE_HEADER *Device,\r | |
1932 | IN UINT64 Address,\r | |
1933 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
1934 | );\r | |
1935 | \r | |
a1d4bfcc | 1936 | /**\r |
1937 | Explain the bridge specific part of data in PCI configuration space.\r | |
1938 | \r | |
1939 | @param[in] Bridge Bridge specific data region in PCI configuration space.\r | |
1940 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1941 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1942 | \r | |
1943 | @retval EFI_SUCCESS The command completed successfully.\r | |
1944 | **/\r | |
5d73d92f | 1945 | EFI_STATUS\r |
1946 | PciExplainBridgeData (\r | |
a1d4bfcc | 1947 | IN PCI_BRIDGE_HEADER *Bridge,\r |
1948 | IN UINT64 Address,\r | |
1949 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 1950 | );\r |
1951 | \r | |
a1d4bfcc | 1952 | /**\r |
1953 | Explain the Base Address Register(Bar) in PCI configuration space.\r | |
1954 | \r | |
4ff7e37b ED |
1955 | @param[in] Bar Points to the Base Address Register intended to interpret.\r |
1956 | @param[in] Command Points to the register Command.\r | |
1957 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1958 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1959 | @param[in, out] Index The Index.\r | |
a1d4bfcc | 1960 | \r |
1961 | @retval EFI_SUCCESS The command completed successfully.\r | |
1962 | **/\r | |
5d73d92f | 1963 | EFI_STATUS\r |
1964 | PciExplainBar (\r | |
1965 | IN UINT32 *Bar,\r | |
1966 | IN UINT16 *Command,\r | |
1967 | IN UINT64 Address,\r | |
1968 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
1969 | IN OUT UINTN *Index\r | |
1970 | );\r | |
1971 | \r | |
a1d4bfcc | 1972 | /**\r |
1973 | Explain the cardbus specific part of data in PCI configuration space.\r | |
1974 | \r | |
1975 | @param[in] CardBus CardBus specific region of PCI configuration space.\r | |
1976 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1977 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1978 | \r | |
1979 | @retval EFI_SUCCESS The command completed successfully.\r | |
1980 | **/\r | |
5d73d92f | 1981 | EFI_STATUS\r |
1982 | PciExplainCardBusData (\r | |
1983 | IN PCI_CARDBUS_HEADER *CardBus,\r | |
1984 | IN UINT64 Address,\r | |
1985 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
1986 | );\r | |
1987 | \r | |
a1d4bfcc | 1988 | /**\r |
1989 | Explain each meaningful bit of register Status. The definition of Status is\r | |
1990 | slightly different depending on the PCI header type.\r | |
1991 | \r | |
1992 | @param[in] Status Points to the content of register Status.\r | |
1993 | @param[in] MainStatus Indicates if this register is main status(not secondary\r | |
1994 | status).\r | |
1995 | @param[in] HeaderType Header type of this PCI device.\r | |
1996 | \r | |
1997 | @retval EFI_SUCCESS The command completed successfully.\r | |
1998 | **/\r | |
5d73d92f | 1999 | EFI_STATUS\r |
2000 | PciExplainStatus (\r | |
2001 | IN UINT16 *Status,\r | |
2002 | IN BOOLEAN MainStatus,\r | |
2003 | IN PCI_HEADER_TYPE HeaderType\r | |
2004 | );\r | |
2005 | \r | |
a1d4bfcc | 2006 | /**\r |
2007 | Explain each meaningful bit of register Command.\r | |
2008 | \r | |
2009 | @param[in] Command Points to the content of register Command.\r | |
2010 | \r | |
2011 | @retval EFI_SUCCESS The command completed successfully.\r | |
2012 | **/\r | |
5d73d92f | 2013 | EFI_STATUS\r |
2014 | PciExplainCommand (\r | |
2015 | IN UINT16 *Command\r | |
2016 | );\r | |
2017 | \r | |
a1d4bfcc | 2018 | /**\r |
2019 | Explain each meaningful bit of register Bridge Control.\r | |
2020 | \r | |
2021 | @param[in] BridgeControl Points to the content of register Bridge Control.\r | |
2022 | @param[in] HeaderType The headertype.\r | |
2023 | \r | |
2024 | @retval EFI_SUCCESS The command completed successfully.\r | |
2025 | **/\r | |
5d73d92f | 2026 | EFI_STATUS\r |
2027 | PciExplainBridgeControl (\r | |
2028 | IN UINT16 *BridgeControl,\r | |
2029 | IN PCI_HEADER_TYPE HeaderType\r | |
2030 | );\r | |
2031 | \r | |
a1d4bfcc | 2032 | /**\r |
2033 | Print each capability structure.\r | |
2034 | \r | |
f614ce7e SQ |
2035 | @param[in] IoDev The pointer to the deivce.\r |
2036 | @param[in] Address The address to start at.\r | |
2037 | @param[in] CapPtr The offset from the address.\r | |
2038 | @param[in] EnhancedDump The print format for the dump data.\r | |
a1d4bfcc | 2039 | \r |
f614ce7e | 2040 | @retval EFI_SUCCESS The operation was successful.\r |
a1d4bfcc | 2041 | **/\r |
5d73d92f | 2042 | EFI_STATUS\r |
2043 | PciExplainCapabilityStruct (\r | |
2044 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
2045 | IN UINT64 Address,\r | |
705bffb5 JC |
2046 | IN UINT8 CapPtr,\r |
2047 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 2048 | );\r |
2049 | \r | |
a1d4bfcc | 2050 | /**\r |
2051 | Display Pcie device structure.\r | |
2052 | \r | |
f614ce7e SQ |
2053 | @param[in] IoDev The pointer to the root pci protocol.\r |
2054 | @param[in] Address The Address to start at.\r | |
2055 | @param[in] CapabilityPtr The offset from the address to start.\r | |
2056 | @param[in] EnhancedDump The print format for the dump data.\r | |
2057 | \r | |
2058 | @retval EFI_SUCCESS The command completed successfully.\r | |
2059 | @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted. \r | |
a1d4bfcc | 2060 | **/\r |
5d73d92f | 2061 | EFI_STATUS\r |
2062 | PciExplainPciExpress (\r | |
2063 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
2064 | IN UINT64 Address,\r | |
705bffb5 JC |
2065 | IN UINT8 CapabilityPtr,\r |
2066 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 2067 | );\r |
2068 | \r | |
a1d4bfcc | 2069 | /**\r |
2070 | Print out information of the capability information.\r | |
2071 | \r | |
2072 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2073 | \r | |
2074 | @retval EFI_SUCCESS The operation was successful.\r | |
2075 | **/\r | |
5d73d92f | 2076 | EFI_STATUS\r |
2077 | ExplainPcieCapReg (\r | |
2412c297 | 2078 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2079 | );\r |
2080 | \r | |
2081 | /**\r | |
2082 | Print out information of the device capability information.\r | |
2083 | \r | |
2084 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2085 | \r |
a1d4bfcc | 2086 | @retval EFI_SUCCESS The operation was successful.\r |
2087 | **/\r | |
5d73d92f | 2088 | EFI_STATUS\r |
2089 | ExplainPcieDeviceCap (\r | |
2412c297 | 2090 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2091 | );\r |
2092 | \r | |
2093 | /**\r | |
2094 | Print out information of the device control information.\r | |
5d73d92f | 2095 | \r |
a1d4bfcc | 2096 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2097 | \r | |
2098 | @retval EFI_SUCCESS The operation was successful.\r | |
2099 | **/\r | |
5d73d92f | 2100 | EFI_STATUS\r |
2101 | ExplainPcieDeviceControl (\r | |
2412c297 | 2102 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2103 | );\r |
5d73d92f | 2104 | \r |
a1d4bfcc | 2105 | /**\r |
2106 | Print out information of the device status information.\r | |
2107 | \r | |
2108 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2109 | \r | |
2110 | @retval EFI_SUCCESS The operation was successful.\r | |
2111 | **/\r | |
5d73d92f | 2112 | EFI_STATUS\r |
2113 | ExplainPcieDeviceStatus (\r | |
2412c297 | 2114 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2115 | );\r |
2116 | \r | |
2117 | /**\r | |
2118 | Print out information of the device link information.\r | |
2119 | \r | |
2120 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2121 | \r |
a1d4bfcc | 2122 | @retval EFI_SUCCESS The operation was successful.\r |
2123 | **/\r | |
5d73d92f | 2124 | EFI_STATUS\r |
2125 | ExplainPcieLinkCap (\r | |
2412c297 | 2126 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2127 | );\r |
2128 | \r | |
2129 | /**\r | |
2130 | Print out information of the device link control information.\r | |
5d73d92f | 2131 | \r |
a1d4bfcc | 2132 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2133 | \r | |
2134 | @retval EFI_SUCCESS The operation was successful.\r | |
2135 | **/\r | |
5d73d92f | 2136 | EFI_STATUS\r |
2137 | ExplainPcieLinkControl (\r | |
2412c297 | 2138 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2139 | );\r |
5d73d92f | 2140 | \r |
a1d4bfcc | 2141 | /**\r |
2142 | Print out information of the device link status information.\r | |
2143 | \r | |
2144 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2145 | \r | |
2146 | @retval EFI_SUCCESS The operation was successful.\r | |
2147 | **/\r | |
5d73d92f | 2148 | EFI_STATUS\r |
2149 | ExplainPcieLinkStatus (\r | |
2412c297 | 2150 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2151 | );\r |
2152 | \r | |
2153 | /**\r | |
2154 | Print out information of the device slot information.\r | |
2155 | \r | |
2156 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2157 | \r |
a1d4bfcc | 2158 | @retval EFI_SUCCESS The operation was successful.\r |
2159 | **/\r | |
5d73d92f | 2160 | EFI_STATUS\r |
2161 | ExplainPcieSlotCap (\r | |
2412c297 | 2162 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2163 | );\r |
2164 | \r | |
2165 | /**\r | |
2166 | Print out information of the device slot control information.\r | |
5d73d92f | 2167 | \r |
a1d4bfcc | 2168 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2169 | \r | |
2170 | @retval EFI_SUCCESS The operation was successful.\r | |
2171 | **/\r | |
5d73d92f | 2172 | EFI_STATUS\r |
2173 | ExplainPcieSlotControl (\r | |
2412c297 | 2174 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2175 | );\r |
5d73d92f | 2176 | \r |
a1d4bfcc | 2177 | /**\r |
2178 | Print out information of the device slot status information.\r | |
2179 | \r | |
2180 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2181 | \r | |
2182 | @retval EFI_SUCCESS The operation was successful.\r | |
2183 | **/\r | |
5d73d92f | 2184 | EFI_STATUS\r |
2185 | ExplainPcieSlotStatus (\r | |
2412c297 | 2186 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2187 | );\r |
2188 | \r | |
2189 | /**\r | |
2190 | Print out information of the device root information.\r | |
2191 | \r | |
2192 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2193 | \r |
a1d4bfcc | 2194 | @retval EFI_SUCCESS The operation was successful.\r |
2195 | **/\r | |
5d73d92f | 2196 | EFI_STATUS\r |
2197 | ExplainPcieRootControl (\r | |
2412c297 | 2198 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2199 | );\r |
2200 | \r | |
2201 | /**\r | |
2202 | Print out information of the device root capability information.\r | |
5d73d92f | 2203 | \r |
a1d4bfcc | 2204 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2205 | \r | |
2206 | @retval EFI_SUCCESS The operation was successful.\r | |
2207 | **/\r | |
5d73d92f | 2208 | EFI_STATUS\r |
2209 | ExplainPcieRootCap (\r | |
2412c297 | 2210 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2211 | );\r |
5d73d92f | 2212 | \r |
a1d4bfcc | 2213 | /**\r |
2214 | Print out information of the device root status information.\r | |
2215 | \r | |
2216 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2217 | \r | |
2218 | @retval EFI_SUCCESS The operation was successful.\r | |
2219 | **/\r | |
5d73d92f | 2220 | EFI_STATUS\r |
2221 | ExplainPcieRootStatus (\r | |
2412c297 | 2222 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 2223 | );\r |
5d73d92f | 2224 | \r |
2412c297 | 2225 | typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STRUCTURE *PciExpressCap);\r |
5d73d92f | 2226 | \r |
2227 | typedef enum {\r | |
2228 | FieldWidthUINT8,\r | |
2229 | FieldWidthUINT16,\r | |
2230 | FieldWidthUINT32\r | |
2231 | } PCIE_CAPREG_FIELD_WIDTH;\r | |
2232 | \r | |
2233 | typedef enum {\r | |
2234 | PcieExplainTypeCommon,\r | |
2235 | PcieExplainTypeDevice,\r | |
2236 | PcieExplainTypeLink,\r | |
2237 | PcieExplainTypeSlot,\r | |
2238 | PcieExplainTypeRoot,\r | |
2239 | PcieExplainTypeMax\r | |
2240 | } PCIE_EXPLAIN_TYPE;\r | |
2241 | \r | |
2242 | typedef struct\r | |
2243 | {\r | |
2244 | UINT16 Token;\r | |
2245 | UINTN Offset;\r | |
2246 | PCIE_CAPREG_FIELD_WIDTH Width;\r | |
2247 | PCIE_EXPLAIN_FUNCTION Func;\r | |
2248 | PCIE_EXPLAIN_TYPE Type;\r | |
2249 | } PCIE_EXPLAIN_STRUCT;\r | |
2250 | \r | |
2251 | PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r | |
2252 | {\r | |
2253 | STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r | |
2254 | 0x00,\r | |
2255 | FieldWidthUINT8,\r | |
2256 | NULL,\r | |
2257 | PcieExplainTypeCommon\r | |
2258 | },\r | |
2259 | {\r | |
2260 | STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r | |
2261 | 0x01,\r | |
2262 | FieldWidthUINT8,\r | |
2263 | NULL,\r | |
2264 | PcieExplainTypeCommon\r | |
2265 | },\r | |
2266 | {\r | |
2267 | STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r | |
2268 | 0x02,\r | |
2269 | FieldWidthUINT16,\r | |
2270 | ExplainPcieCapReg,\r | |
2271 | PcieExplainTypeCommon\r | |
2272 | },\r | |
2273 | {\r | |
2274 | STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r | |
2275 | 0x04,\r | |
2276 | FieldWidthUINT32,\r | |
2277 | ExplainPcieDeviceCap,\r | |
2278 | PcieExplainTypeDevice\r | |
2279 | },\r | |
2280 | {\r | |
2281 | STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r | |
2282 | 0x08,\r | |
2283 | FieldWidthUINT16,\r | |
2284 | ExplainPcieDeviceControl,\r | |
2285 | PcieExplainTypeDevice\r | |
2286 | },\r | |
2287 | {\r | |
2288 | STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r | |
2289 | 0x0a,\r | |
2290 | FieldWidthUINT16,\r | |
2291 | ExplainPcieDeviceStatus,\r | |
2292 | PcieExplainTypeDevice\r | |
2293 | },\r | |
2294 | {\r | |
2295 | STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r | |
2296 | 0x0c,\r | |
2297 | FieldWidthUINT32,\r | |
2298 | ExplainPcieLinkCap,\r | |
2299 | PcieExplainTypeLink\r | |
2300 | },\r | |
2301 | {\r | |
2302 | STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r | |
2303 | 0x10,\r | |
2304 | FieldWidthUINT16,\r | |
2305 | ExplainPcieLinkControl,\r | |
2306 | PcieExplainTypeLink\r | |
2307 | },\r | |
2308 | {\r | |
2309 | STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r | |
2310 | 0x12,\r | |
2311 | FieldWidthUINT16,\r | |
2312 | ExplainPcieLinkStatus,\r | |
2313 | PcieExplainTypeLink\r | |
2314 | },\r | |
2315 | {\r | |
2316 | STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r | |
2317 | 0x14,\r | |
2318 | FieldWidthUINT32,\r | |
2319 | ExplainPcieSlotCap,\r | |
2320 | PcieExplainTypeSlot\r | |
2321 | },\r | |
2322 | {\r | |
2323 | STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r | |
2324 | 0x18,\r | |
2325 | FieldWidthUINT16,\r | |
2326 | ExplainPcieSlotControl,\r | |
2327 | PcieExplainTypeSlot\r | |
2328 | },\r | |
2329 | {\r | |
2330 | STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r | |
2331 | 0x1a,\r | |
2332 | FieldWidthUINT16,\r | |
2333 | ExplainPcieSlotStatus,\r | |
2334 | PcieExplainTypeSlot\r | |
2335 | },\r | |
2336 | {\r | |
2337 | STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r | |
2338 | 0x1c,\r | |
2339 | FieldWidthUINT16,\r | |
2340 | ExplainPcieRootControl,\r | |
2341 | PcieExplainTypeRoot\r | |
2342 | },\r | |
2343 | {\r | |
2344 | STRING_TOKEN (STR_PCIEX_RSVDP),\r | |
2345 | 0x1e,\r | |
2346 | FieldWidthUINT16,\r | |
2347 | ExplainPcieRootCap,\r | |
2348 | PcieExplainTypeRoot\r | |
2349 | },\r | |
2350 | {\r | |
2351 | STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r | |
2352 | 0x20,\r | |
2353 | FieldWidthUINT32,\r | |
2354 | ExplainPcieRootStatus,\r | |
2355 | PcieExplainTypeRoot\r | |
2356 | },\r | |
2357 | {\r | |
2358 | 0,\r | |
2359 | 0,\r | |
2360 | (PCIE_CAPREG_FIELD_WIDTH)0,\r | |
2361 | NULL,\r | |
2362 | PcieExplainTypeMax\r | |
2363 | }\r | |
2364 | };\r | |
2365 | \r | |
2366 | //\r | |
2367 | // Global Variables\r | |
2368 | //\r | |
2369 | PCI_CONFIG_SPACE *mConfigSpace = NULL;\r | |
2370 | STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r | |
2371 | {L"-s", TypeValue},\r | |
2372 | {L"-i", TypeFlag},\r | |
9b7143c9 | 2373 | {L"-_e", TypeFlag},\r |
5d73d92f | 2374 | {NULL, TypeMax}\r |
2375 | };\r | |
2376 | \r | |
2377 | CHAR16 *DevicePortTypeTable[] = {\r | |
2378 | L"PCI Express Endpoint",\r | |
2379 | L"Legacy PCI Express Endpoint",\r | |
2380 | L"Unknown Type",\r | |
2381 | L"Unknonw Type",\r | |
2382 | L"Root Port of PCI Express Root Complex",\r | |
2383 | L"Upstream Port of PCI Express Switch",\r | |
2384 | L"Downstream Port of PCI Express Switch",\r | |
2385 | L"PCI Express to PCI/PCI-X Bridge",\r | |
2386 | L"PCI/PCI-X to PCI Express Bridge",\r | |
2387 | L"Root Complex Integrated Endpoint",\r | |
2388 | L"Root Complex Event Collector"\r | |
2389 | };\r | |
2390 | \r | |
2391 | CHAR16 *L0sLatencyStrTable[] = {\r | |
2392 | L"Less than 64ns",\r | |
2393 | L"64ns to less than 128ns",\r | |
2394 | L"128ns to less than 256ns",\r | |
2395 | L"256ns to less than 512ns",\r | |
2396 | L"512ns to less than 1us",\r | |
2397 | L"1us to less than 2us",\r | |
2398 | L"2us-4us",\r | |
2399 | L"More than 4us"\r | |
2400 | };\r | |
2401 | \r | |
2402 | CHAR16 *L1LatencyStrTable[] = {\r | |
2403 | L"Less than 1us",\r | |
2404 | L"1us to less than 2us",\r | |
2405 | L"2us to less than 4us",\r | |
2406 | L"4us to less than 8us",\r | |
2407 | L"8us to less than 16us",\r | |
2408 | L"16us to less than 32us",\r | |
2409 | L"32us-64us",\r | |
2410 | L"More than 64us"\r | |
2411 | };\r | |
2412 | \r | |
2413 | CHAR16 *ASPMCtrlStrTable[] = {\r | |
2414 | L"Disabled",\r | |
2415 | L"L0s Entry Enabled",\r | |
2416 | L"L1 Entry Enabled",\r | |
2417 | L"L0s and L1 Entry Enabled"\r | |
2418 | };\r | |
2419 | \r | |
2420 | CHAR16 *SlotPwrLmtScaleTable[] = {\r | |
2421 | L"1.0x",\r | |
2422 | L"0.1x",\r | |
2423 | L"0.01x",\r | |
2424 | L"0.001x"\r | |
2425 | };\r | |
2426 | \r | |
2427 | CHAR16 *IndicatorTable[] = {\r | |
2428 | L"Reserved",\r | |
2429 | L"On",\r | |
2430 | L"Blink",\r | |
2431 | L"Off"\r | |
2432 | };\r | |
2433 | \r | |
2434 | \r | |
a1d4bfcc | 2435 | /**\r |
2436 | Function for 'pci' command.\r | |
2437 | \r | |
2438 | @param[in] ImageHandle Handle to the Image (NULL if Internal).\r | |
2439 | @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r | |
2440 | **/\r | |
5d73d92f | 2441 | SHELL_STATUS\r |
2442 | EFIAPI\r | |
2443 | ShellCommandRunPci (\r | |
2444 | IN EFI_HANDLE ImageHandle,\r | |
2445 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
2446 | )\r | |
2447 | {\r | |
2448 | UINT16 Segment;\r | |
2449 | UINT16 Bus;\r | |
2450 | UINT16 Device;\r | |
2451 | UINT16 Func;\r | |
2452 | UINT64 Address;\r | |
2453 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r | |
2454 | EFI_STATUS Status;\r | |
2455 | PCI_COMMON_HEADER PciHeader;\r | |
2456 | PCI_CONFIG_SPACE ConfigSpace;\r | |
2457 | UINTN ScreenCount;\r | |
2458 | UINTN TempColumn;\r | |
2459 | UINTN ScreenSize;\r | |
2460 | BOOLEAN ExplainData;\r | |
2461 | UINTN Index;\r | |
2462 | UINTN SizeOfHeader;\r | |
2463 | BOOLEAN PrintTitle;\r | |
2464 | UINTN HandleBufSize;\r | |
2465 | EFI_HANDLE *HandleBuf;\r | |
2466 | UINTN HandleCount;\r | |
2467 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r | |
2468 | UINT16 MinBus;\r | |
2469 | UINT16 MaxBus;\r | |
2470 | BOOLEAN IsEnd;\r | |
2471 | LIST_ENTRY *Package;\r | |
2472 | CHAR16 *ProblemParam;\r | |
2473 | SHELL_STATUS ShellStatus;\r | |
5d73d92f | 2474 | CONST CHAR16 *Temp;\r |
6855763e | 2475 | UINT64 RetVal;\r |
705bffb5 | 2476 | UINT16 EnhancedDump;\r |
5d73d92f | 2477 | \r |
2478 | ShellStatus = SHELL_SUCCESS;\r | |
2479 | Status = EFI_SUCCESS;\r | |
2480 | Address = 0;\r | |
5d73d92f | 2481 | IoDev = NULL;\r |
2482 | HandleBuf = NULL;\r | |
2483 | Package = NULL;\r | |
2484 | \r | |
2485 | //\r | |
2486 | // initialize the shell lib (we must be in non-auto-init...)\r | |
2487 | //\r | |
2488 | Status = ShellInitialize();\r | |
2489 | ASSERT_EFI_ERROR(Status);\r | |
2490 | \r | |
2491 | Status = CommandInit();\r | |
2492 | ASSERT_EFI_ERROR(Status);\r | |
2493 | \r | |
2494 | //\r | |
2495 | // parse the command line\r | |
2496 | //\r | |
2497 | Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r | |
2498 | if (EFI_ERROR(Status)) {\r | |
2499 | if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r | |
4092a8f6 | 2500 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam); \r |
5d73d92f | 2501 | FreePool(ProblemParam);\r |
2502 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2503 | } else {\r | |
2504 | ASSERT(FALSE);\r | |
2505 | }\r | |
2506 | } else {\r | |
2507 | \r | |
3737ac2b | 2508 | if (ShellCommandLineGetCount(Package) == 2) {\r |
4092a8f6 | 2509 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci"); \r |
3737ac2b | 2510 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2511 | goto Done;\r | |
2512 | }\r | |
5d73d92f | 2513 | \r |
3737ac2b | 2514 | if (ShellCommandLineGetCount(Package) > 4) {\r |
4092a8f6 | 2515 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci"); \r |
3737ac2b | 2516 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2517 | goto Done;\r | |
2518 | }\r | |
2519 | if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r | |
4092a8f6 | 2520 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s"); \r |
3737ac2b | 2521 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2522 | goto Done;\r | |
2523 | }\r | |
5d73d92f | 2524 | //\r |
2525 | // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r | |
2526 | // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r | |
2527 | // space for handles and call it again.\r | |
2528 | //\r | |
2529 | HandleBufSize = sizeof (EFI_HANDLE);\r | |
3737ac2b | 2530 | HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r |
5d73d92f | 2531 | if (HandleBuf == NULL) {\r |
4092a8f6 | 2532 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r |
5d73d92f | 2533 | ShellStatus = SHELL_OUT_OF_RESOURCES;\r |
2534 | goto Done;\r | |
2535 | }\r | |
2536 | \r | |
2537 | Status = gBS->LocateHandle (\r | |
2538 | ByProtocol,\r | |
2539 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2540 | NULL,\r | |
2541 | &HandleBufSize,\r | |
2542 | HandleBuf\r | |
2543 | );\r | |
2544 | \r | |
2545 | if (Status == EFI_BUFFER_TOO_SMALL) {\r | |
2546 | HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r | |
2547 | if (HandleBuf == NULL) {\r | |
4092a8f6 | 2548 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r |
5d73d92f | 2549 | ShellStatus = SHELL_OUT_OF_RESOURCES;\r |
2550 | goto Done;\r | |
2551 | }\r | |
2552 | \r | |
2553 | Status = gBS->LocateHandle (\r | |
2554 | ByProtocol,\r | |
2555 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2556 | NULL,\r | |
2557 | &HandleBufSize,\r | |
2558 | HandleBuf\r | |
2559 | );\r | |
2560 | }\r | |
2561 | \r | |
2562 | if (EFI_ERROR (Status)) {\r | |
4092a8f6 | 2563 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci"); \r |
5d73d92f | 2564 | ShellStatus = SHELL_NOT_FOUND;\r |
2565 | goto Done;\r | |
2566 | }\r | |
2567 | \r | |
2568 | HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r | |
2569 | //\r | |
2570 | // Argument Count == 1(no other argument): enumerate all pci functions\r | |
2571 | //\r | |
3737ac2b | 2572 | if (ShellCommandLineGetCount(Package) == 1) {\r |
5d73d92f | 2573 | gST->ConOut->QueryMode (\r |
2574 | gST->ConOut,\r | |
2575 | gST->ConOut->Mode->Mode,\r | |
2576 | &TempColumn,\r | |
2577 | &ScreenSize\r | |
2578 | );\r | |
2579 | \r | |
2580 | ScreenCount = 0;\r | |
2581 | ScreenSize -= 4;\r | |
2582 | if ((ScreenSize & 1) == 1) {\r | |
2583 | ScreenSize -= 1;\r | |
2584 | }\r | |
2585 | \r | |
2586 | PrintTitle = TRUE;\r | |
2587 | \r | |
2588 | //\r | |
2589 | // For each handle, which decides a segment and a bus number range,\r | |
2590 | // enumerate all devices on it.\r | |
2591 | //\r | |
2592 | for (Index = 0; Index < HandleCount; Index++) {\r | |
2593 | Status = PciGetProtocolAndResource (\r | |
2594 | HandleBuf[Index],\r | |
2595 | &IoDev,\r | |
2596 | &Descriptors\r | |
2597 | );\r | |
2598 | if (EFI_ERROR (Status)) {\r | |
4092a8f6 | 2599 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci"); \r |
5d73d92f | 2600 | ShellStatus = SHELL_NOT_FOUND;\r |
2601 | goto Done;\r | |
2602 | }\r | |
2603 | //\r | |
2604 | // No document say it's impossible for a RootBridgeIo protocol handle\r | |
2605 | // to have more than one address space descriptors, so find out every\r | |
2606 | // bus range and for each of them do device enumeration.\r | |
2607 | //\r | |
2608 | while (TRUE) {\r | |
2609 | Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r | |
2610 | \r | |
2611 | if (EFI_ERROR (Status)) {\r | |
4092a8f6 | 2612 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci"); \r |
5d73d92f | 2613 | ShellStatus = SHELL_NOT_FOUND;\r |
2614 | goto Done;\r | |
2615 | }\r | |
2616 | \r | |
2617 | if (IsEnd) {\r | |
2618 | break;\r | |
2619 | }\r | |
2620 | \r | |
2621 | for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r | |
2622 | //\r | |
2623 | // For each devices, enumerate all functions it contains\r | |
2624 | //\r | |
2625 | for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r | |
2626 | //\r | |
2627 | // For each function, read its configuration space and print summary\r | |
2628 | //\r | |
2629 | for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r | |
2630 | if (ShellGetExecutionBreakFlag ()) {\r | |
2631 | ShellStatus = SHELL_ABORTED;\r | |
2632 | goto Done;\r | |
2633 | }\r | |
2634 | Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r | |
2635 | IoDev->Pci.Read (\r | |
2636 | IoDev,\r | |
2637 | EfiPciWidthUint16,\r | |
2638 | Address,\r | |
2639 | 1,\r | |
2640 | &PciHeader.VendorId\r | |
2641 | );\r | |
2642 | \r | |
2643 | //\r | |
2644 | // If VendorId = 0xffff, there does not exist a device at this\r | |
2645 | // location. For each device, if there is any function on it,\r | |
2646 | // there must be 1 function at Function 0. So if Func = 0, there\r | |
2647 | // will be no more functions in the same device, so we can break\r | |
2648 | // loop to deal with the next device.\r | |
2649 | //\r | |
2650 | if (PciHeader.VendorId == 0xffff && Func == 0) {\r | |
2651 | break;\r | |
2652 | }\r | |
2653 | \r | |
2654 | if (PciHeader.VendorId != 0xffff) {\r | |
2655 | \r | |
2656 | if (PrintTitle) {\r | |
2657 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r | |
2658 | PrintTitle = FALSE;\r | |
2659 | }\r | |
2660 | \r | |
2661 | IoDev->Pci.Read (\r | |
2662 | IoDev,\r | |
2663 | EfiPciWidthUint32,\r | |
2664 | Address,\r | |
2665 | sizeof (PciHeader) / sizeof (UINT32),\r | |
2666 | &PciHeader\r | |
2667 | );\r | |
2668 | \r | |
2669 | ShellPrintHiiEx(\r | |
2670 | -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r | |
2671 | IoDev->SegmentNumber,\r | |
2672 | Bus,\r | |
2673 | Device,\r | |
2674 | Func\r | |
2675 | );\r | |
2676 | \r | |
2677 | PciPrintClassCode (PciHeader.ClassCode, FALSE);\r | |
2678 | ShellPrintHiiEx(\r | |
2679 | -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r | |
2680 | PciHeader.VendorId,\r | |
2681 | PciHeader.DeviceId,\r | |
2682 | PciHeader.ClassCode[0]\r | |
2683 | );\r | |
2684 | \r | |
2685 | ScreenCount += 2;\r | |
2686 | if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r | |
2687 | //\r | |
2688 | // If ScreenSize == 0 we have the console redirected so don't\r | |
2689 | // block updates\r | |
2690 | //\r | |
2691 | ScreenCount = 0;\r | |
2692 | }\r | |
2693 | //\r | |
2694 | // If this is not a multi-function device, we can leave the loop\r | |
2695 | // to deal with the next device.\r | |
2696 | //\r | |
2697 | if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r | |
2698 | break;\r | |
2699 | }\r | |
2700 | }\r | |
2701 | }\r | |
2702 | }\r | |
2703 | }\r | |
2704 | //\r | |
2705 | // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r | |
2706 | // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r | |
2707 | // devices on all bus, we can leave loop.\r | |
2708 | //\r | |
2709 | if (Descriptors == NULL) {\r | |
2710 | break;\r | |
2711 | }\r | |
2712 | }\r | |
2713 | }\r | |
2714 | \r | |
2715 | Status = EFI_SUCCESS;\r | |
2716 | goto Done;\r | |
2717 | }\r | |
2718 | \r | |
5d73d92f | 2719 | ExplainData = FALSE;\r |
2720 | Segment = 0;\r | |
2721 | Bus = 0;\r | |
2722 | Device = 0;\r | |
2723 | Func = 0;\r | |
2724 | if (ShellCommandLineGetFlag(Package, L"-i")) {\r | |
2725 | ExplainData = TRUE;\r | |
2726 | }\r | |
2727 | \r | |
2728 | Temp = ShellCommandLineGetValue(Package, L"-s");\r | |
2729 | if (Temp != NULL) {\r | |
6855763e CP |
2730 | //\r |
2731 | // Input converted to hexadecimal number.\r | |
2732 | //\r | |
2733 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2734 | Segment = (UINT16) RetVal;\r | |
2735 | } else {\r | |
4092a8f6 | 2736 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r |
6855763e CP |
2737 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2738 | goto Done;\r | |
2739 | }\r | |
5d73d92f | 2740 | }\r |
2741 | \r | |
2742 | //\r | |
2743 | // The first Argument(except "-i") is assumed to be Bus number, second\r | |
2744 | // to be Device number, and third to be Func number.\r | |
2745 | //\r | |
2746 | Temp = ShellCommandLineGetRawValue(Package, 1);\r | |
2747 | if (Temp != NULL) {\r | |
6855763e CP |
2748 | //\r |
2749 | // Input converted to hexadecimal number.\r | |
2750 | //\r | |
2751 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2752 | Bus = (UINT16) RetVal;\r | |
2753 | } else {\r | |
4092a8f6 | 2754 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r |
6855763e CP |
2755 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2756 | goto Done;\r | |
2757 | }\r | |
2758 | \r | |
5d73d92f | 2759 | if (Bus > MAX_BUS_NUMBER) {\r |
4092a8f6 | 2760 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r |
5d73d92f | 2761 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2762 | goto Done;\r | |
2763 | }\r | |
2764 | }\r | |
2765 | Temp = ShellCommandLineGetRawValue(Package, 2);\r | |
2766 | if (Temp != NULL) {\r | |
6855763e CP |
2767 | //\r |
2768 | // Input converted to hexadecimal number.\r | |
2769 | //\r | |
2770 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2771 | Device = (UINT16) RetVal;\r | |
2772 | } else {\r | |
4092a8f6 | 2773 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r |
6855763e CP |
2774 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2775 | goto Done;\r | |
2776 | }\r | |
2777 | \r | |
5d73d92f | 2778 | if (Device > MAX_DEVICE_NUMBER){\r |
4092a8f6 | 2779 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r |
5d73d92f | 2780 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2781 | goto Done;\r | |
2782 | }\r | |
2783 | }\r | |
2784 | \r | |
2785 | Temp = ShellCommandLineGetRawValue(Package, 3);\r | |
2786 | if (Temp != NULL) {\r | |
6855763e CP |
2787 | //\r |
2788 | // Input converted to hexadecimal number.\r | |
2789 | //\r | |
2790 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2791 | Func = (UINT16) RetVal;\r | |
2792 | } else {\r | |
4092a8f6 | 2793 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r |
6855763e CP |
2794 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2795 | goto Done;\r | |
2796 | }\r | |
2797 | \r | |
5d73d92f | 2798 | if (Func > MAX_FUNCTION_NUMBER){\r |
4092a8f6 | 2799 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r |
5d73d92f | 2800 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2801 | goto Done;\r | |
2802 | }\r | |
2803 | }\r | |
2804 | \r | |
2805 | //\r | |
2806 | // Find the protocol interface who's in charge of current segment, and its\r | |
2807 | // bus range covers the current bus\r | |
2808 | //\r | |
2809 | Status = PciFindProtocolInterface (\r | |
2810 | HandleBuf,\r | |
2811 | HandleCount,\r | |
2812 | Segment,\r | |
2813 | Bus,\r | |
2814 | &IoDev\r | |
2815 | );\r | |
2816 | \r | |
2817 | if (EFI_ERROR (Status)) {\r | |
2818 | ShellPrintHiiEx(\r | |
4092a8f6 | 2819 | -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci", \r |
5d73d92f | 2820 | Segment,\r |
2821 | Bus\r | |
2822 | );\r | |
2823 | ShellStatus = SHELL_NOT_FOUND;\r | |
2824 | goto Done;\r | |
2825 | }\r | |
2826 | \r | |
2827 | Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r | |
2828 | Status = IoDev->Pci.Read (\r | |
2829 | IoDev,\r | |
2830 | EfiPciWidthUint8,\r | |
2831 | Address,\r | |
2832 | sizeof (ConfigSpace),\r | |
2833 | &ConfigSpace\r | |
2834 | );\r | |
2835 | \r | |
2836 | if (EFI_ERROR (Status)) {\r | |
4092a8f6 | 2837 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci"); \r |
5d73d92f | 2838 | ShellStatus = SHELL_ACCESS_DENIED;\r |
2839 | goto Done;\r | |
2840 | }\r | |
2841 | \r | |
2842 | mConfigSpace = &ConfigSpace;\r | |
2843 | ShellPrintHiiEx(\r | |
2844 | -1,\r | |
2845 | -1,\r | |
2846 | NULL,\r | |
2847 | STRING_TOKEN (STR_PCI_INFO),\r | |
2848 | gShellDebug1HiiHandle,\r | |
2849 | Segment,\r | |
2850 | Bus,\r | |
2851 | Device,\r | |
2852 | Func,\r | |
2853 | Segment,\r | |
2854 | Bus,\r | |
2855 | Device,\r | |
2856 | Func\r | |
2857 | );\r | |
2858 | \r | |
2859 | //\r | |
2860 | // Dump standard header of configuration space\r | |
2861 | //\r | |
2862 | SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r | |
2863 | \r | |
a1d4bfcc | 2864 | DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r |
5d73d92f | 2865 | ShellPrintEx(-1,-1, L"\r\n");\r |
2866 | \r | |
2867 | //\r | |
2868 | // Dump device dependent Part of configuration space\r | |
2869 | //\r | |
a1d4bfcc | 2870 | DumpHex (\r |
5d73d92f | 2871 | 2,\r |
2872 | SizeOfHeader,\r | |
2873 | sizeof (ConfigSpace) - SizeOfHeader,\r | |
2874 | ConfigSpace.Data\r | |
2875 | );\r | |
2876 | \r | |
2877 | //\r | |
2878 | // If "-i" appears in command line, interpret data in configuration space\r | |
2879 | //\r | |
2880 | if (ExplainData) {\r | |
705bffb5 JC |
2881 | EnhancedDump = 0;\r |
2882 | if (ShellCommandLineGetFlag(Package, L"-_e")) {\r | |
2883 | EnhancedDump = 0xFFFF;\r | |
2884 | Temp = ShellCommandLineGetValue(Package, L"-_e");\r | |
2885 | if (Temp != NULL) {\r | |
2886 | EnhancedDump = (UINT16) ShellHexStrToUintn (Temp);\r | |
2887 | }\r | |
2888 | }\r | |
2889 | Status = PciExplainData (&ConfigSpace, Address, IoDev, EnhancedDump);\r | |
5d73d92f | 2890 | }\r |
2891 | }\r | |
2892 | Done:\r | |
2893 | if (HandleBuf != NULL) {\r | |
2894 | FreePool (HandleBuf);\r | |
2895 | }\r | |
2896 | if (Package != NULL) {\r | |
2897 | ShellCommandLineFreeVarList (Package);\r | |
2898 | }\r | |
2899 | mConfigSpace = NULL;\r | |
2900 | return ShellStatus;\r | |
2901 | }\r | |
2902 | \r | |
a1d4bfcc | 2903 | /**\r |
5d73d92f | 2904 | This function finds out the protocol which is in charge of the given\r |
2905 | segment, and its bus range covers the current bus number. It lookes\r | |
2906 | each instances of RootBridgeIoProtocol handle, until the one meets the\r | |
2907 | criteria is found.\r | |
2908 | \r | |
a1d4bfcc | 2909 | @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r |
2910 | @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
2911 | @param[in] Segment Segment number of device we are dealing with.\r | |
2912 | @param[in] Bus Bus number of device we are dealing with.\r | |
2913 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
5d73d92f | 2914 | \r |
a1d4bfcc | 2915 | @retval EFI_SUCCESS The command completed successfully.\r |
2916 | @retval EFI_INVALID_PARAMETER Invalid parameter.\r | |
5d73d92f | 2917 | \r |
2918 | **/\r | |
a1d4bfcc | 2919 | EFI_STATUS\r |
2920 | PciFindProtocolInterface (\r | |
2921 | IN EFI_HANDLE *HandleBuf,\r | |
2922 | IN UINTN HandleCount,\r | |
2923 | IN UINT16 Segment,\r | |
2924 | IN UINT16 Bus,\r | |
2925 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r | |
2926 | )\r | |
5d73d92f | 2927 | {\r |
2928 | UINTN Index;\r | |
2929 | EFI_STATUS Status;\r | |
5d73d92f | 2930 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r |
2931 | UINT16 MinBus;\r | |
2932 | UINT16 MaxBus;\r | |
2933 | BOOLEAN IsEnd;\r | |
2934 | \r | |
5d73d92f | 2935 | //\r |
2936 | // Go through all handles, until the one meets the criteria is found\r | |
2937 | //\r | |
2938 | for (Index = 0; Index < HandleCount; Index++) {\r | |
2939 | Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r | |
2940 | if (EFI_ERROR (Status)) {\r | |
2941 | return Status;\r | |
2942 | }\r | |
2943 | //\r | |
2944 | // When Descriptors == NULL, the Configuration() is not implemented,\r | |
2945 | // so we only check the Segment number\r | |
2946 | //\r | |
2947 | if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r | |
2948 | return EFI_SUCCESS;\r | |
2949 | }\r | |
2950 | \r | |
2951 | if ((*IoDev)->SegmentNumber != Segment) {\r | |
2952 | continue;\r | |
2953 | }\r | |
2954 | \r | |
2955 | while (TRUE) {\r | |
2956 | Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r | |
2957 | if (EFI_ERROR (Status)) {\r | |
2958 | return Status;\r | |
2959 | }\r | |
2960 | \r | |
2961 | if (IsEnd) {\r | |
2962 | break;\r | |
2963 | }\r | |
2964 | \r | |
2965 | if (MinBus <= Bus && MaxBus >= Bus) {\r | |
2c46dd23 | 2966 | return EFI_SUCCESS;\r |
5d73d92f | 2967 | }\r |
2968 | }\r | |
2969 | }\r | |
2970 | \r | |
2c46dd23 | 2971 | return EFI_NOT_FOUND;\r |
5d73d92f | 2972 | }\r |
2973 | \r | |
a1d4bfcc | 2974 | /**\r |
2975 | This function gets the protocol interface from the given handle, and\r | |
2976 | obtains its address space descriptors.\r | |
2977 | \r | |
2978 | @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r | |
2979 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
2980 | @param[out] Descriptors Points to the address space descriptors.\r | |
2981 | \r | |
2982 | @retval EFI_SUCCESS The command completed successfully\r | |
2983 | **/\r | |
5d73d92f | 2984 | EFI_STATUS\r |
2985 | PciGetProtocolAndResource (\r | |
2986 | IN EFI_HANDLE Handle,\r | |
2987 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r | |
2988 | OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r | |
2989 | )\r | |
5d73d92f | 2990 | {\r |
2991 | EFI_STATUS Status;\r | |
2992 | \r | |
2993 | //\r | |
2994 | // Get inferface from protocol\r | |
2995 | //\r | |
2996 | Status = gBS->HandleProtocol (\r | |
2997 | Handle,\r | |
2998 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2999 | (VOID**)IoDev\r | |
3000 | );\r | |
3001 | \r | |
3002 | if (EFI_ERROR (Status)) {\r | |
3003 | return Status;\r | |
3004 | }\r | |
3005 | //\r | |
3006 | // Call Configuration() to get address space descriptors\r | |
3007 | //\r | |
3008 | Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r | |
3009 | if (Status == EFI_UNSUPPORTED) {\r | |
3010 | *Descriptors = NULL;\r | |
3011 | return EFI_SUCCESS;\r | |
3012 | \r | |
3013 | } else {\r | |
3014 | return Status;\r | |
3015 | }\r | |
3016 | }\r | |
3017 | \r | |
a1d4bfcc | 3018 | /**\r |
3019 | This function get the next bus range of given address space descriptors.\r | |
3020 | It also moves the pointer backward a node, to get prepared to be called\r | |
3021 | again.\r | |
3022 | \r | |
4ff7e37b ED |
3023 | @param[in, out] Descriptors Points to current position of a serial of address space\r |
3024 | descriptors.\r | |
3025 | @param[out] MinBus The lower range of bus number.\r | |
3026 | @param[out] MaxBus The upper range of bus number.\r | |
3027 | @param[out] IsEnd Meet end of the serial of descriptors.\r | |
a1d4bfcc | 3028 | \r |
3029 | @retval EFI_SUCCESS The command completed successfully.\r | |
3030 | **/\r | |
5d73d92f | 3031 | EFI_STATUS\r |
3032 | PciGetNextBusRange (\r | |
3033 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r | |
3034 | OUT UINT16 *MinBus,\r | |
3035 | OUT UINT16 *MaxBus,\r | |
3036 | OUT BOOLEAN *IsEnd\r | |
3037 | )\r | |
5d73d92f | 3038 | {\r |
3039 | *IsEnd = FALSE;\r | |
3040 | \r | |
3041 | //\r | |
3042 | // When *Descriptors is NULL, Configuration() is not implemented, so assume\r | |
3043 | // range is 0~PCI_MAX_BUS\r | |
3044 | //\r | |
3045 | if ((*Descriptors) == NULL) {\r | |
3046 | *MinBus = 0;\r | |
3047 | *MaxBus = PCI_MAX_BUS;\r | |
3048 | return EFI_SUCCESS;\r | |
3049 | }\r | |
3050 | //\r | |
3051 | // *Descriptors points to one or more address space descriptors, which\r | |
3052 | // ends with a end tagged descriptor. Examine each of the descriptors,\r | |
3053 | // if a bus typed one is found and its bus range covers bus, this handle\r | |
3054 | // is the handle we are looking for.\r | |
3055 | //\r | |
5d73d92f | 3056 | \r |
3057 | while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r | |
3058 | if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r | |
3059 | *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r | |
3060 | *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r | |
3061 | (*Descriptors)++;\r | |
3737ac2b | 3062 | return (EFI_SUCCESS);\r |
5d73d92f | 3063 | }\r |
3064 | \r | |
3065 | (*Descriptors)++;\r | |
3066 | }\r | |
3067 | \r | |
3737ac2b | 3068 | if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r |
3069 | *IsEnd = TRUE;\r | |
3070 | }\r | |
3071 | \r | |
5d73d92f | 3072 | return EFI_SUCCESS;\r |
3073 | }\r | |
3074 | \r | |
a1d4bfcc | 3075 | /**\r |
5d73d92f | 3076 | Explain the data in PCI configuration space. The part which is common for\r |
3077 | PCI device and bridge is interpreted in this function. It calls other\r | |
3078 | functions to interpret data unique for device or bridge.\r | |
3079 | \r | |
a1d4bfcc | 3080 | @param[in] ConfigSpace Data in PCI configuration space.\r |
3081 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3082 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
f614ce7e | 3083 | @param[in] EnhancedDump The print format for the dump data.\r |
5d73d92f | 3084 | \r |
a1d4bfcc | 3085 | @retval EFI_SUCCESS The command completed successfully.\r |
5d73d92f | 3086 | **/\r |
a1d4bfcc | 3087 | EFI_STATUS\r |
3088 | PciExplainData (\r | |
3089 | IN PCI_CONFIG_SPACE *ConfigSpace,\r | |
3090 | IN UINT64 Address,\r | |
705bffb5 JC |
3091 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r |
3092 | IN CONST UINT16 EnhancedDump\r | |
a1d4bfcc | 3093 | )\r |
5d73d92f | 3094 | {\r |
3095 | PCI_COMMON_HEADER *Common;\r | |
3096 | PCI_HEADER_TYPE HeaderType;\r | |
3097 | EFI_STATUS Status;\r | |
3098 | UINT8 CapPtr;\r | |
3099 | \r | |
3100 | Common = &(ConfigSpace->Common);\r | |
3101 | \r | |
c37e0f16 | 3102 | ShellPrintEx (-1, -1, L"\r\n");\r |
5d73d92f | 3103 | \r |
3104 | //\r | |
3105 | // Print Vendor Id and Device Id\r | |
3106 | //\r | |
3107 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r | |
3108 | INDEX_OF (&(Common->VendorId)),\r | |
3109 | Common->VendorId,\r | |
3110 | INDEX_OF (&(Common->DeviceId)),\r | |
3111 | Common->DeviceId\r | |
3112 | );\r | |
3113 | \r | |
3114 | //\r | |
3115 | // Print register Command\r | |
3116 | //\r | |
3117 | PciExplainCommand (&(Common->Command));\r | |
3118 | \r | |
3119 | //\r | |
3120 | // Print register Status\r | |
3121 | //\r | |
3122 | PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r | |
3123 | \r | |
3124 | //\r | |
3125 | // Print register Revision ID\r | |
3126 | //\r | |
14b5e3fd | 3127 | ShellPrintEx(-1, -1, L"\r\n");\r |
5d73d92f | 3128 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r |
3129 | INDEX_OF (&(Common->RevisionId)),\r | |
3130 | Common->RevisionId\r | |
3131 | );\r | |
3132 | \r | |
3133 | //\r | |
3134 | // Print register BIST\r | |
3135 | //\r | |
a1d4bfcc | 3136 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r |
3137 | if ((Common->Bist & PCI_BIT_7) != 0) {\r | |
3138 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r | |
5d73d92f | 3139 | } else {\r |
3140 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r | |
3141 | }\r | |
3142 | //\r | |
3143 | // Print register Cache Line Size\r | |
3144 | //\r | |
3145 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3146 | STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r | |
3147 | gShellDebug1HiiHandle,\r | |
3148 | INDEX_OF (&(Common->CacheLineSize)),\r | |
3149 | Common->CacheLineSize\r | |
3150 | );\r | |
3151 | \r | |
3152 | //\r | |
3153 | // Print register Latency Timer\r | |
3154 | //\r | |
3155 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3156 | STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r | |
3157 | gShellDebug1HiiHandle,\r | |
3158 | INDEX_OF (&(Common->PrimaryLatencyTimer)),\r | |
3159 | Common->PrimaryLatencyTimer\r | |
3160 | );\r | |
3161 | \r | |
3162 | //\r | |
3163 | // Print register Header Type\r | |
3164 | //\r | |
3165 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3166 | STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r | |
3167 | gShellDebug1HiiHandle,\r | |
3168 | INDEX_OF (&(Common->HeaderType)),\r | |
3169 | Common->HeaderType\r | |
3170 | );\r | |
3171 | \r | |
3172 | if ((Common->HeaderType & PCI_BIT_7) != 0) {\r | |
3173 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r | |
3174 | \r | |
3175 | } else {\r | |
3176 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r | |
3177 | }\r | |
3178 | \r | |
3179 | HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r | |
3180 | switch (HeaderType) {\r | |
3181 | case PciDevice:\r | |
3182 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r | |
3183 | break;\r | |
3184 | \r | |
3185 | case PciP2pBridge:\r | |
3186 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r | |
3187 | break;\r | |
3188 | \r | |
3189 | case PciCardBusBridge:\r | |
3190 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r | |
3191 | break;\r | |
3192 | \r | |
3193 | default:\r | |
3194 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r | |
3195 | HeaderType = PciUndefined;\r | |
3196 | }\r | |
3197 | \r | |
3198 | //\r | |
3199 | // Print register Class Code\r | |
3200 | //\r | |
3201 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r | |
3202 | PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r | |
c37e0f16 | 3203 | ShellPrintEx (-1, -1, L"\r\n");\r |
5d73d92f | 3204 | \r |
3205 | if (ShellGetExecutionBreakFlag()) {\r | |
3206 | return EFI_SUCCESS;\r | |
3207 | }\r | |
3208 | \r | |
3209 | //\r | |
3210 | // Interpret remaining part of PCI configuration header depending on\r | |
3211 | // HeaderType\r | |
3212 | //\r | |
3213 | CapPtr = 0;\r | |
3214 | Status = EFI_SUCCESS;\r | |
3215 | switch (HeaderType) {\r | |
3216 | case PciDevice:\r | |
3217 | Status = PciExplainDeviceData (\r | |
3218 | &(ConfigSpace->NonCommon.Device),\r | |
3219 | Address,\r | |
3220 | IoDev\r | |
3221 | );\r | |
3222 | CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r | |
3223 | break;\r | |
3224 | \r | |
3225 | case PciP2pBridge:\r | |
3226 | Status = PciExplainBridgeData (\r | |
3227 | &(ConfigSpace->NonCommon.Bridge),\r | |
3228 | Address,\r | |
3229 | IoDev\r | |
3230 | );\r | |
3231 | CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r | |
3232 | break;\r | |
3233 | \r | |
3234 | case PciCardBusBridge:\r | |
3235 | Status = PciExplainCardBusData (\r | |
3236 | &(ConfigSpace->NonCommon.CardBus),\r | |
3237 | Address,\r | |
3238 | IoDev\r | |
3239 | );\r | |
3240 | CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r | |
3241 | break;\r | |
d8f8021c | 3242 | case PciUndefined:\r |
3243 | default:\r | |
3244 | break;\r | |
5d73d92f | 3245 | }\r |
3246 | //\r | |
3247 | // If Status bit4 is 1, dump or explain capability structure\r | |
3248 | //\r | |
3249 | if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r | |
705bffb5 | 3250 | PciExplainCapabilityStruct (IoDev, Address, CapPtr, EnhancedDump);\r |
5d73d92f | 3251 | }\r |
3252 | \r | |
3253 | return Status;\r | |
3254 | }\r | |
3255 | \r | |
a1d4bfcc | 3256 | /**\r |
3257 | Explain the device specific part of data in PCI configuration space.\r | |
3258 | \r | |
3259 | @param[in] Device Data in PCI configuration space.\r | |
3260 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3261 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3262 | \r | |
3263 | @retval EFI_SUCCESS The command completed successfully.\r | |
3264 | **/\r | |
5d73d92f | 3265 | EFI_STATUS\r |
3266 | PciExplainDeviceData (\r | |
3267 | IN PCI_DEVICE_HEADER *Device,\r | |
3268 | IN UINT64 Address,\r | |
3269 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
3270 | )\r | |
5d73d92f | 3271 | {\r |
3272 | UINTN Index;\r | |
3273 | BOOLEAN BarExist;\r | |
3274 | EFI_STATUS Status;\r | |
3275 | UINTN BarCount;\r | |
3276 | \r | |
3277 | //\r | |
3278 | // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r | |
3279 | // exist. If these no Bar for this function, print "none", otherwise\r | |
3280 | // list detail information about this Bar.\r | |
3281 | //\r | |
3282 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r | |
3283 | \r | |
3284 | BarExist = FALSE;\r | |
3285 | BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r | |
3286 | for (Index = 0; Index < BarCount; Index++) {\r | |
3287 | if (Device->Bar[Index] == 0) {\r | |
3288 | continue;\r | |
3289 | }\r | |
3290 | \r | |
3291 | if (!BarExist) {\r | |
3292 | BarExist = TRUE;\r | |
3293 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3294 | ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r |
5d73d92f | 3295 | }\r |
3296 | \r | |
3297 | Status = PciExplainBar (\r | |
3298 | &(Device->Bar[Index]),\r | |
3299 | &(mConfigSpace->Common.Command),\r | |
3300 | Address,\r | |
3301 | IoDev,\r | |
3302 | &Index\r | |
3303 | );\r | |
3304 | \r | |
3305 | if (EFI_ERROR (Status)) {\r | |
3306 | break;\r | |
3307 | }\r | |
3308 | }\r | |
3309 | \r | |
3310 | if (!BarExist) {\r | |
3311 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r | |
3312 | \r | |
3313 | } else {\r | |
c37e0f16 | 3314 | ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r |
5d73d92f | 3315 | }\r |
3316 | \r | |
3317 | //\r | |
3318 | // Print register Expansion ROM Base Address\r | |
3319 | //\r | |
3320 | if ((Device->ROMBar & PCI_BIT_0) == 0) {\r | |
3321 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r | |
3322 | \r | |
3323 | } else {\r | |
3324 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3325 | STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r | |
3326 | gShellDebug1HiiHandle,\r | |
3327 | INDEX_OF (&(Device->ROMBar)),\r | |
3328 | Device->ROMBar\r | |
3329 | );\r | |
3330 | }\r | |
3331 | //\r | |
3332 | // Print register Cardbus CIS ptr\r | |
3333 | //\r | |
3334 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3335 | STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r | |
3336 | gShellDebug1HiiHandle,\r | |
3337 | INDEX_OF (&(Device->CardBusCISPtr)),\r | |
3338 | Device->CardBusCISPtr\r | |
3339 | );\r | |
3340 | \r | |
3341 | //\r | |
3342 | // Print register Sub-vendor ID and subsystem ID\r | |
3343 | //\r | |
3344 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3345 | STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r | |
3346 | gShellDebug1HiiHandle,\r | |
3347 | INDEX_OF (&(Device->SubVendorId)),\r | |
3348 | Device->SubVendorId\r | |
3349 | );\r | |
3350 | \r | |
3351 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3352 | STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r | |
3353 | gShellDebug1HiiHandle,\r | |
3354 | INDEX_OF (&(Device->SubSystemId)),\r | |
3355 | Device->SubSystemId\r | |
3356 | );\r | |
3357 | \r | |
3358 | //\r | |
3359 | // Print register Capabilities Ptr\r | |
3360 | //\r | |
3361 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3362 | STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r | |
3363 | gShellDebug1HiiHandle,\r | |
3364 | INDEX_OF (&(Device->CapabilitiesPtr)),\r | |
3365 | Device->CapabilitiesPtr\r | |
3366 | );\r | |
3367 | \r | |
3368 | //\r | |
3369 | // Print register Interrupt Line and interrupt pin\r | |
3370 | //\r | |
3371 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3372 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r | |
3373 | gShellDebug1HiiHandle,\r | |
3374 | INDEX_OF (&(Device->InterruptLine)),\r | |
3375 | Device->InterruptLine\r | |
3376 | );\r | |
3377 | \r | |
3378 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3379 | STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r | |
3380 | gShellDebug1HiiHandle,\r | |
3381 | INDEX_OF (&(Device->InterruptPin)),\r | |
3382 | Device->InterruptPin\r | |
3383 | );\r | |
3384 | \r | |
3385 | //\r | |
3386 | // Print register Min_Gnt and Max_Lat\r | |
3387 | //\r | |
3388 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3389 | STRING_TOKEN (STR_PCI2_MIN_GNT),\r | |
3390 | gShellDebug1HiiHandle,\r | |
3391 | INDEX_OF (&(Device->MinGnt)),\r | |
3392 | Device->MinGnt\r | |
3393 | );\r | |
3394 | \r | |
3395 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3396 | STRING_TOKEN (STR_PCI2_MAX_LAT),\r | |
3397 | gShellDebug1HiiHandle,\r | |
3398 | INDEX_OF (&(Device->MaxLat)),\r | |
3399 | Device->MaxLat\r | |
3400 | );\r | |
3401 | \r | |
3402 | return EFI_SUCCESS;\r | |
3403 | }\r | |
3404 | \r | |
a1d4bfcc | 3405 | /**\r |
3406 | Explain the bridge specific part of data in PCI configuration space.\r | |
3407 | \r | |
3408 | @param[in] Bridge Bridge specific data region in PCI configuration space.\r | |
3409 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3410 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3411 | \r | |
3412 | @retval EFI_SUCCESS The command completed successfully.\r | |
3413 | **/\r | |
5d73d92f | 3414 | EFI_STATUS\r |
3415 | PciExplainBridgeData (\r | |
3416 | IN PCI_BRIDGE_HEADER *Bridge,\r | |
3417 | IN UINT64 Address,\r | |
3418 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
3419 | )\r | |
5d73d92f | 3420 | {\r |
3421 | UINTN Index;\r | |
3422 | BOOLEAN BarExist;\r | |
3423 | UINTN BarCount;\r | |
3424 | UINT32 IoAddress32;\r | |
3425 | EFI_STATUS Status;\r | |
3426 | \r | |
3427 | //\r | |
3428 | // Print Base Address Registers. When Bar = 0, this Bar does not\r | |
3429 | // exist. If these no Bar for this function, print "none", otherwise\r | |
3430 | // list detail information about this Bar.\r | |
3431 | //\r | |
3432 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r | |
3433 | \r | |
3434 | BarExist = FALSE;\r | |
3435 | BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r | |
3436 | \r | |
3437 | for (Index = 0; Index < BarCount; Index++) {\r | |
3438 | if (Bridge->Bar[Index] == 0) {\r | |
3439 | continue;\r | |
3440 | }\r | |
3441 | \r | |
3442 | if (!BarExist) {\r | |
3443 | BarExist = TRUE;\r | |
3444 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3445 | ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r |
5d73d92f | 3446 | }\r |
3447 | \r | |
3448 | Status = PciExplainBar (\r | |
3449 | &(Bridge->Bar[Index]),\r | |
3450 | &(mConfigSpace->Common.Command),\r | |
3451 | Address,\r | |
3452 | IoDev,\r | |
3453 | &Index\r | |
3454 | );\r | |
3455 | \r | |
3456 | if (EFI_ERROR (Status)) {\r | |
3457 | break;\r | |
3458 | }\r | |
3459 | }\r | |
3460 | \r | |
3461 | if (!BarExist) {\r | |
3462 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r | |
3463 | } else {\r | |
c37e0f16 | 3464 | ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r |
5d73d92f | 3465 | }\r |
3466 | \r | |
3467 | //\r | |
3468 | // Expansion register ROM Base Address\r | |
3469 | //\r | |
3470 | if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r | |
3471 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r | |
3472 | \r | |
3473 | } else {\r | |
3474 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3475 | STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r | |
3476 | gShellDebug1HiiHandle,\r | |
3477 | INDEX_OF (&(Bridge->ROMBar)),\r | |
3478 | Bridge->ROMBar\r | |
3479 | );\r | |
3480 | }\r | |
3481 | //\r | |
3482 | // Print Bus Numbers(Primary, Secondary, and Subordinate\r | |
3483 | //\r | |
3484 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3485 | STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r | |
3486 | gShellDebug1HiiHandle,\r | |
3487 | INDEX_OF (&(Bridge->PrimaryBus)),\r | |
3488 | INDEX_OF (&(Bridge->SecondaryBus)),\r | |
3489 | INDEX_OF (&(Bridge->SubordinateBus))\r | |
3490 | );\r | |
3491 | \r | |
c37e0f16 | 3492 | ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r |
5d73d92f | 3493 | \r |
3494 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r | |
3495 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r | |
3496 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r | |
3497 | \r | |
3498 | //\r | |
3499 | // Print register Secondary Latency Timer\r | |
3500 | //\r | |
3501 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3502 | STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r | |
3503 | gShellDebug1HiiHandle,\r | |
3504 | INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r | |
3505 | Bridge->SecondaryLatencyTimer\r | |
3506 | );\r | |
3507 | \r | |
3508 | //\r | |
3509 | // Print register Secondary Status\r | |
3510 | //\r | |
3511 | PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r | |
3512 | \r | |
3513 | //\r | |
3514 | // Print I/O and memory ranges this bridge forwards. There are 3 resource\r | |
3515 | // types: I/O, memory, and pre-fetchable memory. For each resource type,\r | |
3516 | // base and limit address are listed.\r | |
3517 | //\r | |
3518 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3519 | ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r |
5d73d92f | 3520 | \r |
3521 | //\r | |
3522 | // IO Base & Limit\r | |
3523 | //\r | |
3524 | IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r | |
3525 | IoAddress32 &= 0xfffff000;\r | |
3526 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3527 | STRING_TOKEN (STR_PCI2_TWO_VARS),\r | |
3528 | gShellDebug1HiiHandle,\r | |
3529 | INDEX_OF (&(Bridge->IoBase)),\r | |
3530 | IoAddress32\r | |
3531 | );\r | |
3532 | \r | |
3533 | IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r | |
3534 | IoAddress32 |= 0x00000fff;\r | |
3535 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r | |
3536 | \r | |
3537 | //\r | |
3538 | // Memory Base & Limit\r | |
3539 | //\r | |
3540 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3541 | STRING_TOKEN (STR_PCI2_MEMORY),\r | |
3542 | gShellDebug1HiiHandle,\r | |
3543 | INDEX_OF (&(Bridge->MemoryBase)),\r | |
3544 | (Bridge->MemoryBase << 16) & 0xfff00000\r | |
3545 | );\r | |
3546 | \r | |
3547 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3548 | STRING_TOKEN (STR_PCI2_ONE_VAR),\r | |
3549 | gShellDebug1HiiHandle,\r | |
3550 | (Bridge->MemoryLimit << 16) | 0x000fffff\r | |
3551 | );\r | |
3552 | \r | |
3553 | //\r | |
3554 | // Pre-fetch-able Memory Base & Limit\r | |
3555 | //\r | |
3556 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3557 | STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r | |
3558 | gShellDebug1HiiHandle,\r | |
3559 | INDEX_OF (&(Bridge->PrefetchableMemBase)),\r | |
3560 | Bridge->PrefetchableBaseUpper,\r | |
3561 | (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r | |
3562 | );\r | |
3563 | \r | |
3564 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3565 | STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r | |
3566 | gShellDebug1HiiHandle,\r | |
3567 | Bridge->PrefetchableLimitUpper,\r | |
3568 | (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r | |
3569 | );\r | |
3570 | \r | |
3571 | //\r | |
3572 | // Print register Capabilities Pointer\r | |
3573 | //\r | |
3574 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3575 | STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r | |
3576 | gShellDebug1HiiHandle,\r | |
3577 | INDEX_OF (&(Bridge->CapabilitiesPtr)),\r | |
3578 | Bridge->CapabilitiesPtr\r | |
3579 | );\r | |
3580 | \r | |
3581 | //\r | |
3582 | // Print register Bridge Control\r | |
3583 | //\r | |
3584 | PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r | |
3585 | \r | |
3586 | //\r | |
3587 | // Print register Interrupt Line & PIN\r | |
3588 | //\r | |
3589 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3590 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r | |
3591 | gShellDebug1HiiHandle,\r | |
3592 | INDEX_OF (&(Bridge->InterruptLine)),\r | |
3593 | Bridge->InterruptLine\r | |
3594 | );\r | |
3595 | \r | |
3596 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3597 | STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r | |
3598 | gShellDebug1HiiHandle,\r | |
3599 | INDEX_OF (&(Bridge->InterruptPin)),\r | |
3600 | Bridge->InterruptPin\r | |
3601 | );\r | |
3602 | \r | |
3603 | return EFI_SUCCESS;\r | |
3604 | }\r | |
3605 | \r | |
a1d4bfcc | 3606 | /**\r |
3607 | Explain the Base Address Register(Bar) in PCI configuration space.\r | |
3608 | \r | |
4ff7e37b ED |
3609 | @param[in] Bar Points to the Base Address Register intended to interpret.\r |
3610 | @param[in] Command Points to the register Command.\r | |
3611 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3612 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3613 | @param[in, out] Index The Index.\r | |
a1d4bfcc | 3614 | \r |
3615 | @retval EFI_SUCCESS The command completed successfully.\r | |
3616 | **/\r | |
5d73d92f | 3617 | EFI_STATUS\r |
3618 | PciExplainBar (\r | |
3619 | IN UINT32 *Bar,\r | |
3620 | IN UINT16 *Command,\r | |
3621 | IN UINT64 Address,\r | |
3622 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
3623 | IN OUT UINTN *Index\r | |
3624 | )\r | |
5d73d92f | 3625 | {\r |
3626 | UINT16 OldCommand;\r | |
3627 | UINT16 NewCommand;\r | |
3628 | UINT64 Bar64;\r | |
3629 | UINT32 OldBar32;\r | |
3630 | UINT32 NewBar32;\r | |
3631 | UINT64 OldBar64;\r | |
3632 | UINT64 NewBar64;\r | |
3633 | BOOLEAN IsMem;\r | |
3634 | BOOLEAN IsBar32;\r | |
3635 | UINT64 RegAddress;\r | |
3636 | \r | |
3637 | IsBar32 = TRUE;\r | |
3638 | Bar64 = 0;\r | |
3639 | NewBar32 = 0;\r | |
3640 | NewBar64 = 0;\r | |
3641 | \r | |
3642 | //\r | |
3643 | // According the bar type, list detail about this bar, for example: 32 or\r | |
3644 | // 64 bits; pre-fetchable or not.\r | |
3645 | //\r | |
3646 | if ((*Bar & PCI_BIT_0) == 0) {\r | |
3647 | //\r | |
3648 | // This bar is of memory type\r | |
3649 | //\r | |
3650 | IsMem = TRUE;\r | |
3651 | \r | |
3652 | if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r | |
3653 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r | |
3654 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r | |
3655 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r | |
3656 | \r | |
3657 | } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r | |
3658 | Bar64 = 0x0;\r | |
3659 | CopyMem (&Bar64, Bar, sizeof (UINT64));\r | |
46cb4043 | 3660 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r |
2b578de0 | 3661 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r |
5d73d92f | 3662 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r |
3663 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r | |
3664 | IsBar32 = FALSE;\r | |
3665 | *Index += 1;\r | |
3666 | \r | |
3667 | } else {\r | |
3668 | //\r | |
3669 | // Reserved\r | |
3670 | //\r | |
3671 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r | |
3672 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r | |
3673 | }\r | |
3674 | \r | |
3675 | if ((*Bar & PCI_BIT_3) == 0) {\r | |
3676 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r | |
3677 | \r | |
3678 | } else {\r | |
3679 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r | |
3680 | }\r | |
3681 | \r | |
3682 | } else {\r | |
3683 | //\r | |
3684 | // This bar is of io type\r | |
3685 | //\r | |
3686 | IsMem = FALSE;\r | |
3687 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r | |
c37e0f16 | 3688 | ShellPrintEx (-1, -1, L"I/O ");\r |
5d73d92f | 3689 | }\r |
3690 | \r | |
3691 | //\r | |
3692 | // Get BAR length(or the amount of resource this bar demands for). To get\r | |
3693 | // Bar length, first we should temporarily disable I/O and memory access\r | |
3694 | // of this function(by set bits in the register Command), then write all\r | |
3695 | // "1"s to this bar. The bar value read back is the amount of resource\r | |
3696 | // this bar demands for.\r | |
3697 | //\r | |
3698 | //\r | |
3699 | // Disable io & mem access\r | |
3700 | //\r | |
3701 | OldCommand = *Command;\r | |
3702 | NewCommand = (UINT16) (OldCommand & 0xfffc);\r | |
3703 | RegAddress = Address | INDEX_OF (Command);\r | |
3704 | IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r | |
3705 | \r | |
3706 | RegAddress = Address | INDEX_OF (Bar);\r | |
3707 | \r | |
3708 | //\r | |
3709 | // Read after write the BAR to get the size\r | |
3710 | //\r | |
3711 | if (IsBar32) {\r | |
3712 | OldBar32 = *Bar;\r | |
3713 | NewBar32 = 0xffffffff;\r | |
3714 | \r | |
3715 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r | |
3716 | IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r | |
3717 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r | |
3718 | \r | |
3719 | if (IsMem) {\r | |
3720 | NewBar32 = NewBar32 & 0xfffffff0;\r | |
3721 | NewBar32 = (~NewBar32) + 1;\r | |
3722 | \r | |
3723 | } else {\r | |
3724 | NewBar32 = NewBar32 & 0xfffffffc;\r | |
3725 | NewBar32 = (~NewBar32) + 1;\r | |
3726 | NewBar32 = NewBar32 & 0x0000ffff;\r | |
3727 | }\r | |
3728 | } else {\r | |
3729 | \r | |
3730 | OldBar64 = 0x0;\r | |
3731 | CopyMem (&OldBar64, Bar, sizeof (UINT64));\r | |
2b578de0 | 3732 | NewBar64 = 0xffffffffffffffffULL;\r |
5d73d92f | 3733 | \r |
3734 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r | |
3735 | IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r | |
3736 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r | |
3737 | \r | |
3738 | if (IsMem) {\r | |
2b578de0 | 3739 | NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r |
5d73d92f | 3740 | NewBar64 = (~NewBar64) + 1;\r |
3741 | \r | |
3742 | } else {\r | |
2b578de0 | 3743 | NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r |
5d73d92f | 3744 | NewBar64 = (~NewBar64) + 1;\r |
3745 | NewBar64 = NewBar64 & 0x000000000000ffff;\r | |
3746 | }\r | |
3747 | }\r | |
3748 | //\r | |
3749 | // Enable io & mem access\r | |
3750 | //\r | |
3751 | RegAddress = Address | INDEX_OF (Command);\r | |
3752 | IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r | |
3753 | \r | |
3754 | if (IsMem) {\r | |
3755 | if (IsBar32) {\r | |
3756 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r | |
3757 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r | |
3758 | \r | |
3759 | } else {\r | |
46cb4043 | 3760 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r |
5d73d92f | 3761 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r |
c37e0f16 | 3762 | ShellPrintEx (-1, -1, L" ");\r |
5d73d92f | 3763 | ShellPrintHiiEx(-1, -1, NULL,\r |
3764 | STRING_TOKEN (STR_PCI2_RSHIFT),\r | |
3765 | gShellDebug1HiiHandle,\r | |
46cb4043 | 3766 | (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r |
5d73d92f | 3767 | );\r |
2b578de0 | 3768 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r |
5d73d92f | 3769 | \r |
3770 | }\r | |
3771 | } else {\r | |
3772 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r | |
3773 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r | |
3774 | }\r | |
3775 | \r | |
3776 | return EFI_SUCCESS;\r | |
3777 | }\r | |
3778 | \r | |
a1d4bfcc | 3779 | /**\r |
3780 | Explain the cardbus specific part of data in PCI configuration space.\r | |
3781 | \r | |
3782 | @param[in] CardBus CardBus specific region of PCI configuration space.\r | |
3783 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3784 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3785 | \r | |
3786 | @retval EFI_SUCCESS The command completed successfully.\r | |
3787 | **/\r | |
5d73d92f | 3788 | EFI_STATUS\r |
3789 | PciExplainCardBusData (\r | |
3790 | IN PCI_CARDBUS_HEADER *CardBus,\r | |
3791 | IN UINT64 Address,\r | |
3792 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
3793 | )\r | |
5d73d92f | 3794 | {\r |
3795 | BOOLEAN Io32Bit;\r | |
3796 | PCI_CARDBUS_DATA *CardBusData;\r | |
3797 | \r | |
3798 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3799 | STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r | |
3800 | gShellDebug1HiiHandle,\r | |
3801 | INDEX_OF (&(CardBus->CardBusSocketReg)),\r | |
3802 | CardBus->CardBusSocketReg\r | |
3803 | );\r | |
3804 | \r | |
3805 | //\r | |
3806 | // Print Secondary Status\r | |
3807 | //\r | |
3808 | PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r | |
3809 | \r | |
3810 | //\r | |
3811 | // Print Bus Numbers(Primary bus number, CardBus bus number, and\r | |
3812 | // Subordinate bus number\r | |
3813 | //\r | |
3814 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3815 | STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r | |
3816 | gShellDebug1HiiHandle,\r | |
3817 | INDEX_OF (&(CardBus->PciBusNumber)),\r | |
3818 | INDEX_OF (&(CardBus->CardBusBusNumber)),\r | |
3819 | INDEX_OF (&(CardBus->SubordinateBusNumber))\r | |
3820 | );\r | |
3821 | \r | |
c37e0f16 | 3822 | ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r |
5d73d92f | 3823 | \r |
3824 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r | |
3825 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r | |
3826 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r | |
3827 | \r | |
3828 | //\r | |
3829 | // Print CardBus Latency Timer\r | |
3830 | //\r | |
3831 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3832 | STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r | |
3833 | gShellDebug1HiiHandle,\r | |
3834 | INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r | |
3835 | CardBus->CardBusLatencyTimer\r | |
3836 | );\r | |
3837 | \r | |
3838 | //\r | |
3839 | // Print Memory/Io ranges this cardbus bridge forwards\r | |
3840 | //\r | |
3841 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3842 | ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r |
5d73d92f | 3843 | \r |
3844 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3845 | STRING_TOKEN (STR_PCI2_MEM_3),\r | |
3846 | gShellDebug1HiiHandle,\r | |
3847 | INDEX_OF (&(CardBus->MemoryBase0)),\r | |
3848 | CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r | |
3849 | CardBus->MemoryBase0 & 0xfffff000,\r | |
3850 | CardBus->MemoryLimit0 | 0x00000fff\r | |
3851 | );\r | |
3852 | \r | |
3853 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3854 | STRING_TOKEN (STR_PCI2_MEM_3),\r | |
3855 | gShellDebug1HiiHandle,\r | |
3856 | INDEX_OF (&(CardBus->MemoryBase1)),\r | |
3857 | CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r | |
3858 | CardBus->MemoryBase1 & 0xfffff000,\r | |
3859 | CardBus->MemoryLimit1 | 0x00000fff\r | |
3860 | );\r | |
3861 | \r | |
3862 | Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r | |
3863 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3864 | STRING_TOKEN (STR_PCI2_IO_2),\r | |
3865 | gShellDebug1HiiHandle,\r | |
3866 | INDEX_OF (&(CardBus->IoBase0)),\r | |
3867 | Io32Bit ? L" 32 bit" : L" 16 bit",\r | |
3868 | CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r | |
d8f8021c | 3869 | (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r |
5d73d92f | 3870 | );\r |
3871 | \r | |
3872 | Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r | |
3873 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3874 | STRING_TOKEN (STR_PCI2_IO_2),\r | |
3875 | gShellDebug1HiiHandle,\r | |
3876 | INDEX_OF (&(CardBus->IoBase1)),\r | |
3877 | Io32Bit ? L" 32 bit" : L" 16 bit",\r | |
3878 | CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r | |
d8f8021c | 3879 | (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r |
5d73d92f | 3880 | );\r |
3881 | \r | |
3882 | //\r | |
3883 | // Print register Interrupt Line & PIN\r | |
3884 | //\r | |
3885 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3886 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r | |
3887 | gShellDebug1HiiHandle,\r | |
3888 | INDEX_OF (&(CardBus->InterruptLine)),\r | |
3889 | CardBus->InterruptLine,\r | |
3890 | INDEX_OF (&(CardBus->InterruptPin)),\r | |
3891 | CardBus->InterruptPin\r | |
3892 | );\r | |
3893 | \r | |
3894 | //\r | |
3895 | // Print register Bridge Control\r | |
3896 | //\r | |
3897 | PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r | |
3898 | \r | |
3899 | //\r | |
3900 | // Print some registers in data region of PCI configuration space for cardbus\r | |
3901 | // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r | |
3902 | // Address.\r | |
3903 | //\r | |
3904 | CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r | |
3905 | \r | |
3906 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3907 | STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r | |
3908 | gShellDebug1HiiHandle,\r | |
3909 | INDEX_OF (&(CardBusData->SubVendorId)),\r | |
3910 | CardBusData->SubVendorId,\r | |
3911 | INDEX_OF (&(CardBusData->SubSystemId)),\r | |
3912 | CardBusData->SubSystemId\r | |
3913 | );\r | |
3914 | \r | |
3915 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3916 | STRING_TOKEN (STR_PCI2_OPTIONAL),\r | |
3917 | gShellDebug1HiiHandle,\r | |
3918 | INDEX_OF (&(CardBusData->LegacyBase)),\r | |
3919 | CardBusData->LegacyBase\r | |
3920 | );\r | |
3921 | \r | |
3922 | return EFI_SUCCESS;\r | |
3923 | }\r | |
3924 | \r | |
a1d4bfcc | 3925 | /**\r |
3926 | Explain each meaningful bit of register Status. The definition of Status is\r | |
3927 | slightly different depending on the PCI header type.\r | |
3928 | \r | |
3929 | @param[in] Status Points to the content of register Status.\r | |
3930 | @param[in] MainStatus Indicates if this register is main status(not secondary\r | |
3931 | status).\r | |
3932 | @param[in] HeaderType Header type of this PCI device.\r | |
3933 | \r | |
3934 | @retval EFI_SUCCESS The command completed successfully.\r | |
3935 | **/\r | |
5d73d92f | 3936 | EFI_STATUS\r |
3937 | PciExplainStatus (\r | |
3938 | IN UINT16 *Status,\r | |
3939 | IN BOOLEAN MainStatus,\r | |
3940 | IN PCI_HEADER_TYPE HeaderType\r | |
3941 | )\r | |
5d73d92f | 3942 | {\r |
3943 | if (MainStatus) {\r | |
3944 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r | |
3945 | \r | |
3946 | } else {\r | |
3947 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r | |
3948 | }\r | |
3949 | \r | |
3950 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r | |
3951 | \r | |
3952 | //\r | |
3953 | // Bit 5 is meaningless for CardBus Bridge\r | |
3954 | //\r | |
3955 | if (HeaderType == PciCardBusBridge) {\r | |
3956 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r | |
3957 | \r | |
3958 | } else {\r | |
3959 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r | |
3960 | }\r | |
3961 | \r | |
3962 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r | |
3963 | \r | |
3964 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r | |
3965 | //\r | |
3966 | // Bit 9 and bit 10 together decides the DEVSEL timing\r | |
3967 | //\r | |
3968 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r | |
3969 | if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r | |
3970 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r | |
3971 | \r | |
3972 | } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r | |
3973 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r | |
3974 | \r | |
3975 | } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r | |
3976 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r | |
3977 | \r | |
3978 | } else {\r | |
3979 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r | |
3980 | }\r | |
3981 | \r | |
3982 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3983 | STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r | |
3984 | gShellDebug1HiiHandle,\r | |
3985 | (*Status & PCI_BIT_11) != 0\r | |
3986 | );\r | |
3987 | \r | |
3988 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3989 | STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r | |
3990 | gShellDebug1HiiHandle,\r | |
3991 | (*Status & PCI_BIT_12) != 0\r | |
3992 | );\r | |
3993 | \r | |
3994 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3995 | STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r | |
3996 | gShellDebug1HiiHandle,\r | |
3997 | (*Status & PCI_BIT_13) != 0\r | |
3998 | );\r | |
3999 | \r | |
4000 | if (MainStatus) {\r | |
4001 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4002 | STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r | |
4003 | gShellDebug1HiiHandle,\r | |
4004 | (*Status & PCI_BIT_14) != 0\r | |
4005 | );\r | |
4006 | \r | |
4007 | } else {\r | |
4008 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4009 | STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r | |
4010 | gShellDebug1HiiHandle,\r | |
4011 | (*Status & PCI_BIT_14) != 0\r | |
4012 | );\r | |
4013 | }\r | |
4014 | \r | |
4015 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4016 | STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r | |
4017 | gShellDebug1HiiHandle,\r | |
4018 | (*Status & PCI_BIT_15) != 0\r | |
4019 | );\r | |
4020 | \r | |
4021 | return EFI_SUCCESS;\r | |
4022 | }\r | |
4023 | \r | |
a1d4bfcc | 4024 | /**\r |
5d73d92f | 4025 | Explain each meaningful bit of register Command.\r |
4026 | \r | |
a1d4bfcc | 4027 | @param[in] Command Points to the content of register Command.\r |
5d73d92f | 4028 | \r |
a1d4bfcc | 4029 | @retval EFI_SUCCESS The command completed successfully.\r |
5d73d92f | 4030 | **/\r |
a1d4bfcc | 4031 | EFI_STATUS\r |
4032 | PciExplainCommand (\r | |
4033 | IN UINT16 *Command\r | |
4034 | )\r | |
5d73d92f | 4035 | {\r |
4036 | //\r | |
4037 | // Print the binary value of register Command\r | |
4038 | //\r | |
4039 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r | |
4040 | \r | |
4041 | //\r | |
4042 | // Explain register Command bit by bit\r | |
4043 | //\r | |
4044 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4045 | STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r | |
4046 | gShellDebug1HiiHandle,\r | |
4047 | (*Command & PCI_BIT_0) != 0\r | |
4048 | );\r | |
4049 | \r | |
4050 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4051 | STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r | |
4052 | gShellDebug1HiiHandle,\r | |
4053 | (*Command & PCI_BIT_1) != 0\r | |
4054 | );\r | |
4055 | \r | |
4056 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4057 | STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r | |
4058 | gShellDebug1HiiHandle,\r | |
4059 | (*Command & PCI_BIT_2) != 0\r | |
4060 | );\r | |
4061 | \r | |
4062 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4063 | STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r | |
4064 | gShellDebug1HiiHandle,\r | |
4065 | (*Command & PCI_BIT_3) != 0\r | |
4066 | );\r | |
4067 | \r | |
4068 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4069 | STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r | |
4070 | gShellDebug1HiiHandle,\r | |
4071 | (*Command & PCI_BIT_4) != 0\r | |
4072 | );\r | |
4073 | \r | |
4074 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4075 | STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r | |
4076 | gShellDebug1HiiHandle,\r | |
4077 | (*Command & PCI_BIT_5) != 0\r | |
4078 | );\r | |
4079 | \r | |
4080 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4081 | STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r | |
4082 | gShellDebug1HiiHandle,\r | |
4083 | (*Command & PCI_BIT_6) != 0\r | |
4084 | );\r | |
4085 | \r | |
4086 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4087 | STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r | |
4088 | gShellDebug1HiiHandle,\r | |
4089 | (*Command & PCI_BIT_7) != 0\r | |
4090 | );\r | |
4091 | \r | |
4092 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4093 | STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r | |
4094 | gShellDebug1HiiHandle,\r | |
4095 | (*Command & PCI_BIT_8) != 0\r | |
4096 | );\r | |
4097 | \r | |
4098 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4099 | STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r | |
4100 | gShellDebug1HiiHandle,\r | |
4101 | (*Command & PCI_BIT_9) != 0\r | |
4102 | );\r | |
4103 | \r | |
4104 | return EFI_SUCCESS;\r | |
4105 | }\r | |
4106 | \r | |
a1d4bfcc | 4107 | /**\r |
4108 | Explain each meaningful bit of register Bridge Control.\r | |
4109 | \r | |
4110 | @param[in] BridgeControl Points to the content of register Bridge Control.\r | |
4111 | @param[in] HeaderType The headertype.\r | |
4112 | \r | |
4113 | @retval EFI_SUCCESS The command completed successfully.\r | |
4114 | **/\r | |
5d73d92f | 4115 | EFI_STATUS\r |
4116 | PciExplainBridgeControl (\r | |
4117 | IN UINT16 *BridgeControl,\r | |
4118 | IN PCI_HEADER_TYPE HeaderType\r | |
4119 | )\r | |
5d73d92f | 4120 | {\r |
4121 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4122 | STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r | |
4123 | gShellDebug1HiiHandle,\r | |
4124 | INDEX_OF (BridgeControl),\r | |
4125 | *BridgeControl\r | |
4126 | );\r | |
4127 | \r | |
4128 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4129 | STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r | |
4130 | gShellDebug1HiiHandle,\r | |
4131 | (*BridgeControl & PCI_BIT_0) != 0\r | |
4132 | );\r | |
4133 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4134 | STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r | |
4135 | gShellDebug1HiiHandle,\r | |
4136 | (*BridgeControl & PCI_BIT_1) != 0\r | |
4137 | );\r | |
4138 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4139 | STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r | |
4140 | gShellDebug1HiiHandle,\r | |
4141 | (*BridgeControl & PCI_BIT_2) != 0\r | |
4142 | );\r | |
4143 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4144 | STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r | |
4145 | gShellDebug1HiiHandle,\r | |
4146 | (*BridgeControl & PCI_BIT_3) != 0\r | |
4147 | );\r | |
4148 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4149 | STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r | |
4150 | gShellDebug1HiiHandle,\r | |
4151 | (*BridgeControl & PCI_BIT_5) != 0\r | |
4152 | );\r | |
4153 | \r | |
4154 | //\r | |
4155 | // Register Bridge Control has some slight differences between P2P bridge\r | |
4156 | // and Cardbus bridge from bit 6 to bit 11.\r | |
4157 | //\r | |
4158 | if (HeaderType == PciP2pBridge) {\r | |
4159 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4160 | STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r | |
4161 | gShellDebug1HiiHandle,\r | |
4162 | (*BridgeControl & PCI_BIT_6) != 0\r | |
4163 | );\r | |
4164 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4165 | STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r | |
4166 | gShellDebug1HiiHandle,\r | |
4167 | (*BridgeControl & PCI_BIT_7) != 0\r | |
4168 | );\r | |
4169 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4170 | STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r | |
4171 | gShellDebug1HiiHandle,\r | |
4172 | (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r | |
4173 | );\r | |
4174 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4175 | STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r | |
4176 | gShellDebug1HiiHandle,\r | |
4177 | (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r | |
4178 | );\r | |
4179 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4180 | STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r | |
4181 | gShellDebug1HiiHandle,\r | |
4182 | (*BridgeControl & PCI_BIT_10) != 0\r | |
4183 | );\r | |
4184 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4185 | STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r | |
4186 | gShellDebug1HiiHandle,\r | |
4187 | (*BridgeControl & PCI_BIT_11) != 0\r | |
4188 | );\r | |
4189 | \r | |
4190 | } else {\r | |
4191 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4192 | STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r | |
4193 | gShellDebug1HiiHandle,\r | |
4194 | (*BridgeControl & PCI_BIT_6) != 0\r | |
4195 | );\r | |
4196 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4197 | STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r | |
4198 | gShellDebug1HiiHandle,\r | |
4199 | (*BridgeControl & PCI_BIT_7) != 0\r | |
4200 | );\r | |
4201 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4202 | STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r | |
4203 | gShellDebug1HiiHandle,\r | |
4204 | (*BridgeControl & PCI_BIT_10) != 0\r | |
4205 | );\r | |
4206 | }\r | |
4207 | \r | |
4208 | return EFI_SUCCESS;\r | |
4209 | }\r | |
4210 | \r | |
a1d4bfcc | 4211 | /**\r |
4212 | Print each capability structure.\r | |
4213 | \r | |
f614ce7e SQ |
4214 | @param[in] IoDev The pointer to the deivce.\r |
4215 | @param[in] Address The address to start at.\r | |
4216 | @param[in] CapPtr The offset from the address.\r | |
4217 | @param[in] EnhancedDump The print format for the dump data.\r | |
a1d4bfcc | 4218 | \r |
4219 | @retval EFI_SUCCESS The operation was successful.\r | |
4220 | **/\r | |
5d73d92f | 4221 | EFI_STATUS\r |
4222 | PciExplainCapabilityStruct (\r | |
4223 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
4224 | IN UINT64 Address,\r | |
705bffb5 JC |
4225 | IN UINT8 CapPtr,\r |
4226 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 4227 | )\r |
4228 | {\r | |
4229 | UINT8 CapabilityPtr;\r | |
4230 | UINT16 CapabilityEntry;\r | |
4231 | UINT8 CapabilityID;\r | |
4232 | UINT64 RegAddress;\r | |
4233 | \r | |
4234 | CapabilityPtr = CapPtr;\r | |
4235 | \r | |
4236 | //\r | |
4237 | // Go through the Capability list\r | |
4238 | //\r | |
4239 | while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r | |
4240 | RegAddress = Address + CapabilityPtr;\r | |
4241 | IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r | |
4242 | \r | |
4243 | CapabilityID = (UINT8) CapabilityEntry;\r | |
4244 | \r | |
4245 | //\r | |
4246 | // Explain PciExpress data\r | |
4247 | //\r | |
4248 | if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r | |
705bffb5 | 4249 | PciExplainPciExpress (IoDev, Address, CapabilityPtr, EnhancedDump);\r |
5d73d92f | 4250 | return EFI_SUCCESS;\r |
4251 | }\r | |
4252 | //\r | |
4253 | // Explain other capabilities here\r | |
4254 | //\r | |
4255 | CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r | |
4256 | }\r | |
4257 | \r | |
4258 | return EFI_SUCCESS;\r | |
4259 | }\r | |
4260 | \r | |
a1d4bfcc | 4261 | /**\r |
4262 | Print out information of the capability information.\r | |
4263 | \r | |
4264 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4265 | \r | |
4266 | @retval EFI_SUCCESS The operation was successful.\r | |
4267 | **/\r | |
5d73d92f | 4268 | EFI_STATUS\r |
4269 | ExplainPcieCapReg (\r | |
2412c297 | 4270 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4271 | )\r |
5d73d92f | 4272 | {\r |
4273 | UINT16 PcieCapReg;\r | |
4274 | CHAR16 *DevicePortType;\r | |
4275 | \r | |
4276 | PcieCapReg = PciExpressCap->PcieCapReg;\r | |
c37e0f16 CP |
4277 | ShellPrintEx (-1, -1,\r |
4278 | L" Capability Version(3:0): %E0x%04x%N\r\n",\r | |
5d73d92f | 4279 | PCIE_CAP_VERSION (PcieCapReg)\r |
4280 | );\r | |
4281 | if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r | |
4282 | DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r | |
4283 | } else {\r | |
4284 | DevicePortType = L"Unknown Type";\r | |
4285 | }\r | |
c37e0f16 CP |
4286 | ShellPrintEx (-1, -1,\r |
4287 | L" Device/PortType(7:4): %E%s%N\r\n",\r | |
5d73d92f | 4288 | DevicePortType\r |
4289 | );\r | |
4290 | //\r | |
4291 | // 'Slot Implemented' is only valid for:\r | |
4292 | // a) Root Port of PCI Express Root Complex, or\r | |
4293 | // b) Downstream Port of PCI Express Switch\r | |
4294 | //\r | |
4295 | if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r | |
4296 | PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r | |
c37e0f16 CP |
4297 | ShellPrintEx (-1, -1,\r |
4298 | L" Slot Implemented(8): %E%d%N\r\n",\r | |
5d73d92f | 4299 | PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r |
4300 | );\r | |
4301 | }\r | |
c37e0f16 CP |
4302 | ShellPrintEx (-1, -1,\r |
4303 | L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r | |
5d73d92f | 4304 | PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r |
4305 | );\r | |
4306 | return EFI_SUCCESS;\r | |
4307 | }\r | |
4308 | \r | |
a1d4bfcc | 4309 | /**\r |
4310 | Print out information of the device capability information.\r | |
4311 | \r | |
4312 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4313 | \r | |
4314 | @retval EFI_SUCCESS The operation was successful.\r | |
4315 | **/\r | |
5d73d92f | 4316 | EFI_STATUS\r |
4317 | ExplainPcieDeviceCap (\r | |
2412c297 | 4318 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4319 | )\r |
5d73d92f | 4320 | {\r |
4321 | UINT16 PcieCapReg;\r | |
4322 | UINT32 PcieDeviceCap;\r | |
4323 | UINT8 DevicePortType;\r | |
4324 | UINT8 L0sLatency;\r | |
4325 | UINT8 L1Latency;\r | |
4326 | \r | |
4327 | PcieCapReg = PciExpressCap->PcieCapReg;\r | |
4328 | PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r | |
4329 | DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r | |
c37e0f16 | 4330 | ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r |
5d73d92f | 4331 | if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r |
c37e0f16 | 4332 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r |
5d73d92f | 4333 | } else {\r |
c37e0f16 | 4334 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4335 | }\r |
c37e0f16 CP |
4336 | ShellPrintEx (-1, -1,\r |
4337 | L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r | |
5d73d92f | 4338 | PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r |
4339 | );\r | |
c37e0f16 CP |
4340 | ShellPrintEx (-1, -1,\r |
4341 | L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r | |
5d73d92f | 4342 | PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r |
4343 | );\r | |
4344 | //\r | |
4345 | // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r | |
4346 | //\r | |
4347 | if (IS_PCIE_ENDPOINT (DevicePortType)) {\r | |
a1d4bfcc | 4348 | L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r |
4349 | L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r | |
c37e0f16 | 4350 | ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r |
5d73d92f | 4351 | if (L0sLatency < 4) {\r |
c37e0f16 | 4352 | ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r |
5d73d92f | 4353 | } else {\r |
4354 | if (L0sLatency < 7) {\r | |
c37e0f16 | 4355 | ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r |
5d73d92f | 4356 | } else {\r |
c37e0f16 | 4357 | ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r |
5d73d92f | 4358 | }\r |
4359 | }\r | |
c37e0f16 | 4360 | ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r |
5d73d92f | 4361 | if (L1Latency < 7) {\r |
c37e0f16 | 4362 | ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r |
5d73d92f | 4363 | } else {\r |
c37e0f16 | 4364 | ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r |
5d73d92f | 4365 | }\r |
4366 | }\r | |
c37e0f16 CP |
4367 | ShellPrintEx (-1, -1,\r |
4368 | L" Role-based Error Reporting(15): %E%d%N\r\n",\r | |
5d73d92f | 4369 | PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r |
4370 | );\r | |
4371 | //\r | |
4372 | // Only valid for Upstream Port:\r | |
4373 | // a) Captured Slot Power Limit Value\r | |
4374 | // b) Captured Slot Power Scale\r | |
4375 | //\r | |
4376 | if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r | |
c37e0f16 CP |
4377 | ShellPrintEx (-1, -1,\r |
4378 | L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r | |
5d73d92f | 4379 | PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r |
4380 | );\r | |
c37e0f16 CP |
4381 | ShellPrintEx (-1, -1,\r |
4382 | L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r | |
5d73d92f | 4383 | SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r |
4384 | );\r | |
4385 | }\r | |
4386 | //\r | |
4387 | // Function Level Reset Capability is only valid for Endpoint\r | |
4388 | //\r | |
4389 | if (IS_PCIE_ENDPOINT (DevicePortType)) {\r | |
c37e0f16 CP |
4390 | ShellPrintEx (-1, -1,\r |
4391 | L" Function Level Reset Capability(28): %E%d%N\r\n",\r | |
5d73d92f | 4392 | PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r |
4393 | );\r | |
4394 | }\r | |
4395 | return EFI_SUCCESS;\r | |
4396 | }\r | |
4397 | \r | |
a1d4bfcc | 4398 | /**\r |
4399 | Print out information of the device control information.\r | |
4400 | \r | |
4401 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4402 | \r | |
4403 | @retval EFI_SUCCESS The operation was successful.\r | |
4404 | **/\r | |
5d73d92f | 4405 | EFI_STATUS\r |
4406 | ExplainPcieDeviceControl (\r | |
2412c297 | 4407 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4408 | )\r |
5d73d92f | 4409 | {\r |
4410 | UINT16 PcieCapReg;\r | |
4411 | UINT16 PcieDeviceControl;\r | |
4412 | \r | |
4413 | PcieCapReg = PciExpressCap->PcieCapReg;\r | |
4414 | PcieDeviceControl = PciExpressCap->DeviceControl;\r | |
c37e0f16 CP |
4415 | ShellPrintEx (-1, -1,\r |
4416 | L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r | |
5d73d92f | 4417 | PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r |
4418 | );\r | |
c37e0f16 CP |
4419 | ShellPrintEx (-1, -1,\r |
4420 | L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r | |
5d73d92f | 4421 | PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r |
4422 | );\r | |
c37e0f16 CP |
4423 | ShellPrintEx (-1, -1,\r |
4424 | L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r | |
5d73d92f | 4425 | PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r |
4426 | );\r | |
c37e0f16 CP |
4427 | ShellPrintEx (-1, -1,\r |
4428 | L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r | |
5d73d92f | 4429 | PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r |
4430 | );\r | |
c37e0f16 CP |
4431 | ShellPrintEx (-1, -1,\r |
4432 | L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r | |
5d73d92f | 4433 | PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r |
4434 | );\r | |
c37e0f16 | 4435 | ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r |
5d73d92f | 4436 | if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r |
c37e0f16 | 4437 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r |
5d73d92f | 4438 | } else {\r |
c37e0f16 | 4439 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4440 | }\r |
c37e0f16 CP |
4441 | ShellPrintEx (-1, -1,\r |
4442 | L" Extended Tag Field Enable(8): %E%d%N\r\n",\r | |
5d73d92f | 4443 | PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r |
4444 | );\r | |
c37e0f16 CP |
4445 | ShellPrintEx (-1, -1,\r |
4446 | L" Phantom Functions Enable(9): %E%d%N\r\n",\r | |
5d73d92f | 4447 | PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r |
4448 | );\r | |
c37e0f16 CP |
4449 | ShellPrintEx (-1, -1,\r |
4450 | L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r | |
5d73d92f | 4451 | PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r |
4452 | );\r | |
c37e0f16 CP |
4453 | ShellPrintEx (-1, -1,\r |
4454 | L" Enable No Snoop(11): %E%d%N\r\n",\r | |
5d73d92f | 4455 | PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r |
4456 | );\r | |
c37e0f16 | 4457 | ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r |
5d73d92f | 4458 | if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r |
c37e0f16 | 4459 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r |
5d73d92f | 4460 | } else {\r |
c37e0f16 | 4461 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4462 | }\r |
4463 | //\r | |
4464 | // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r | |
4465 | //\r | |
4466 | if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r | |
c37e0f16 CP |
4467 | ShellPrintEx (-1, -1,\r |
4468 | L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r | |
5d73d92f | 4469 | PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r |
4470 | );\r | |
4471 | }\r | |
4472 | return EFI_SUCCESS;\r | |
4473 | }\r | |
4474 | \r | |
a1d4bfcc | 4475 | /**\r |
4476 | Print out information of the device status information.\r | |
4477 | \r | |
4478 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4479 | \r | |
4480 | @retval EFI_SUCCESS The operation was successful.\r | |
4481 | **/\r | |
5d73d92f | 4482 | EFI_STATUS\r |
4483 | ExplainPcieDeviceStatus (\r | |
2412c297 | 4484 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4485 | )\r |
5d73d92f | 4486 | {\r |
4487 | UINT16 PcieDeviceStatus;\r | |
4488 | \r | |
4489 | PcieDeviceStatus = PciExpressCap->DeviceStatus;\r | |
c37e0f16 CP |
4490 | ShellPrintEx (-1, -1,\r |
4491 | L" Correctable Error Detected(0): %E%d%N\r\n",\r | |
5d73d92f | 4492 | PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r |
4493 | );\r | |
c37e0f16 CP |
4494 | ShellPrintEx (-1, -1,\r |
4495 | L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r | |
5d73d92f | 4496 | PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r |
4497 | );\r | |
c37e0f16 CP |
4498 | ShellPrintEx (-1, -1,\r |
4499 | L" Fatal Error Detected(2): %E%d%N\r\n",\r | |
5d73d92f | 4500 | PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r |
4501 | );\r | |
c37e0f16 CP |
4502 | ShellPrintEx (-1, -1,\r |
4503 | L" Unsupported Request Detected(3): %E%d%N\r\n",\r | |
5d73d92f | 4504 | PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r |
4505 | );\r | |
c37e0f16 CP |
4506 | ShellPrintEx (-1, -1,\r |
4507 | L" AUX Power Detected(4): %E%d%N\r\n",\r | |
5d73d92f | 4508 | PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r |
4509 | );\r | |
c37e0f16 CP |
4510 | ShellPrintEx (-1, -1,\r |
4511 | L" Transactions Pending(5): %E%d%N\r\n",\r | |
5d73d92f | 4512 | PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r |
4513 | );\r | |
4514 | return EFI_SUCCESS;\r | |
4515 | }\r | |
4516 | \r | |
a1d4bfcc | 4517 | /**\r |
4518 | Print out information of the device link information.\r | |
4519 | \r | |
4520 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4521 | \r | |
4522 | @retval EFI_SUCCESS The operation was successful.\r | |
4523 | **/\r | |
5d73d92f | 4524 | EFI_STATUS\r |
4525 | ExplainPcieLinkCap (\r | |
2412c297 | 4526 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4527 | )\r |
5d73d92f | 4528 | {\r |
4529 | UINT32 PcieLinkCap;\r | |
541ddf44 | 4530 | CHAR16 *MaxLinkSpeed;\r |
a1d4bfcc | 4531 | CHAR16 *AspmValue;\r |
5d73d92f | 4532 | \r |
4533 | PcieLinkCap = PciExpressCap->LinkCap;\r | |
541ddf44 | 4534 | switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r |
5d73d92f | 4535 | case 1:\r |
541ddf44 | 4536 | MaxLinkSpeed = L"2.5 GT/s";\r |
5d73d92f | 4537 | break;\r |
4538 | case 2:\r | |
541ddf44 CP |
4539 | MaxLinkSpeed = L"5.0 GT/s";\r |
4540 | break;\r | |
4541 | case 3:\r | |
4542 | MaxLinkSpeed = L"8.0 GT/s";\r | |
5d73d92f | 4543 | break;\r |
4544 | default:\r | |
541ddf44 | 4545 | MaxLinkSpeed = L"Unknown";\r |
5d73d92f | 4546 | break;\r |
4547 | }\r | |
c37e0f16 | 4548 | ShellPrintEx (-1, -1,\r |
541ddf44 CP |
4549 | L" Maximum Link Speed(3:0): %E%s%N\r\n",\r |
4550 | MaxLinkSpeed\r | |
5d73d92f | 4551 | );\r |
c37e0f16 CP |
4552 | ShellPrintEx (-1, -1,\r |
4553 | L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r | |
5d73d92f | 4554 | PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r |
4555 | );\r | |
4556 | switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r | |
541ddf44 CP |
4557 | case 0:\r |
4558 | AspmValue = L"Not";\r | |
4559 | break;\r | |
5d73d92f | 4560 | case 1:\r |
541ddf44 CP |
4561 | AspmValue = L"L0s";\r |
4562 | break;\r | |
4563 | case 2:\r | |
4564 | AspmValue = L"L1";\r | |
5d73d92f | 4565 | break;\r |
4566 | case 3:\r | |
a1d4bfcc | 4567 | AspmValue = L"L0s and L1";\r |
5d73d92f | 4568 | break;\r |
4569 | default:\r | |
a1d4bfcc | 4570 | AspmValue = L"Reserved";\r |
5d73d92f | 4571 | break;\r |
4572 | }\r | |
c37e0f16 CP |
4573 | ShellPrintEx (-1, -1,\r |
4574 | L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r | |
a1d4bfcc | 4575 | AspmValue\r |
5d73d92f | 4576 | );\r |
c37e0f16 CP |
4577 | ShellPrintEx (-1, -1,\r |
4578 | L" L0s Exit Latency(14:12): %E%s%N\r\n",\r | |
a1d4bfcc | 4579 | L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r |
5d73d92f | 4580 | );\r |
c37e0f16 CP |
4581 | ShellPrintEx (-1, -1,\r |
4582 | L" L1 Exit Latency(17:15): %E%s%N\r\n",\r | |
a1d4bfcc | 4583 | L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r |
5d73d92f | 4584 | );\r |
c37e0f16 CP |
4585 | ShellPrintEx (-1, -1,\r |
4586 | L" Clock Power Management(18): %E%d%N\r\n",\r | |
5d73d92f | 4587 | PCIE_CAP_CLOCK_PM (PcieLinkCap)\r |
4588 | );\r | |
c37e0f16 CP |
4589 | ShellPrintEx (-1, -1,\r |
4590 | L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r | |
5d73d92f | 4591 | PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r |
4592 | );\r | |
c37e0f16 CP |
4593 | ShellPrintEx (-1, -1,\r |
4594 | L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r | |
5d73d92f | 4595 | PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r |
4596 | );\r | |
c37e0f16 CP |
4597 | ShellPrintEx (-1, -1,\r |
4598 | L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r | |
5d73d92f | 4599 | PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r |
4600 | );\r | |
c37e0f16 CP |
4601 | ShellPrintEx (-1, -1,\r |
4602 | L" Port Number(31:24): %E0x%02x%N\r\n",\r | |
5d73d92f | 4603 | PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r |
4604 | );\r | |
4605 | return EFI_SUCCESS;\r | |
4606 | }\r | |
4607 | \r | |
a1d4bfcc | 4608 | /**\r |
4609 | Print out information of the device link control information.\r | |
4610 | \r | |
4611 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4612 | \r | |
4613 | @retval EFI_SUCCESS The operation was successful.\r | |
4614 | **/\r | |
5d73d92f | 4615 | EFI_STATUS\r |
4616 | ExplainPcieLinkControl (\r | |
2412c297 | 4617 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4618 | )\r |
5d73d92f | 4619 | {\r |
4620 | UINT16 PcieLinkControl;\r | |
4621 | UINT8 DevicePortType;\r | |
4622 | \r | |
4623 | PcieLinkControl = PciExpressCap->LinkControl;\r | |
4624 | DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r | |
c37e0f16 CP |
4625 | ShellPrintEx (-1, -1,\r |
4626 | L" Active State Power Management Control(1:0): %E%s%N\r\n",\r | |
5d73d92f | 4627 | ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r |
4628 | );\r | |
4629 | //\r | |
4630 | // RCB is not applicable to switches\r | |
4631 | //\r | |
4632 | if (!IS_PCIE_SWITCH(DevicePortType)) {\r | |
c37e0f16 CP |
4633 | ShellPrintEx (-1, -1,\r |
4634 | L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r | |
5d73d92f | 4635 | 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r |
4636 | );\r | |
4637 | }\r | |
4638 | //\r | |
4639 | // Link Disable is reserved on\r | |
4640 | // a) Endpoints\r | |
4641 | // b) PCI Express to PCI/PCI-X bridges\r | |
4642 | // c) Upstream Ports of Switches\r | |
4643 | //\r | |
4644 | if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r | |
4645 | DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r | |
4646 | DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r | |
c37e0f16 CP |
4647 | ShellPrintEx (-1, -1,\r |
4648 | L" Link Disable(4): %E%d%N\r\n",\r | |
5d73d92f | 4649 | PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r |
4650 | );\r | |
4651 | }\r | |
c37e0f16 CP |
4652 | ShellPrintEx (-1, -1,\r |
4653 | L" Common Clock Configuration(6): %E%d%N\r\n",\r | |
5d73d92f | 4654 | PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r |
4655 | );\r | |
c37e0f16 CP |
4656 | ShellPrintEx (-1, -1,\r |
4657 | L" Extended Synch(7): %E%d%N\r\n",\r | |
5d73d92f | 4658 | PCIE_CAP_EXT_SYNC (PcieLinkControl)\r |
4659 | );\r | |
c37e0f16 CP |
4660 | ShellPrintEx (-1, -1,\r |
4661 | L" Enable Clock Power Management(8): %E%d%N\r\n",\r | |
5d73d92f | 4662 | PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r |
4663 | );\r | |
c37e0f16 CP |
4664 | ShellPrintEx (-1, -1,\r |
4665 | L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r | |
5d73d92f | 4666 | PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r |
4667 | );\r | |
c37e0f16 CP |
4668 | ShellPrintEx (-1, -1,\r |
4669 | L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r | |
5d73d92f | 4670 | PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r |
4671 | );\r | |
c37e0f16 CP |
4672 | ShellPrintEx (-1, -1,\r |
4673 | L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r | |
5d73d92f | 4674 | PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r |
4675 | );\r | |
4676 | return EFI_SUCCESS;\r | |
4677 | }\r | |
4678 | \r | |
a1d4bfcc | 4679 | /**\r |
4680 | Print out information of the device link status information.\r | |
4681 | \r | |
4682 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4683 | \r | |
4684 | @retval EFI_SUCCESS The operation was successful.\r | |
4685 | **/\r | |
5d73d92f | 4686 | EFI_STATUS\r |
4687 | ExplainPcieLinkStatus (\r | |
2412c297 | 4688 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4689 | )\r |
5d73d92f | 4690 | {\r |
4691 | UINT16 PcieLinkStatus;\r | |
541ddf44 | 4692 | CHAR16 *CurLinkSpeed;\r |
5d73d92f | 4693 | \r |
4694 | PcieLinkStatus = PciExpressCap->LinkStatus;\r | |
4695 | switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r | |
4696 | case 1:\r | |
541ddf44 | 4697 | CurLinkSpeed = L"2.5 GT/s";\r |
5d73d92f | 4698 | break;\r |
4699 | case 2:\r | |
541ddf44 CP |
4700 | CurLinkSpeed = L"5.0 GT/s";\r |
4701 | break;\r | |
4702 | case 3:\r | |
4703 | CurLinkSpeed = L"8.0 GT/s";\r | |
5d73d92f | 4704 | break;\r |
4705 | default:\r | |
541ddf44 | 4706 | CurLinkSpeed = L"Reserved";\r |
5d73d92f | 4707 | break;\r |
4708 | }\r | |
c37e0f16 CP |
4709 | ShellPrintEx (-1, -1,\r |
4710 | L" Current Link Speed(3:0): %E%s%N\r\n",\r | |
541ddf44 | 4711 | CurLinkSpeed\r |
5d73d92f | 4712 | );\r |
c37e0f16 CP |
4713 | ShellPrintEx (-1, -1,\r |
4714 | L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r | |
5d73d92f | 4715 | PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r |
4716 | );\r | |
c37e0f16 CP |
4717 | ShellPrintEx (-1, -1,\r |
4718 | L" Link Training(11): %E%d%N\r\n",\r | |
5d73d92f | 4719 | PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r |
4720 | );\r | |
c37e0f16 CP |
4721 | ShellPrintEx (-1, -1,\r |
4722 | L" Slot Clock Configuration(12): %E%d%N\r\n",\r | |
5d73d92f | 4723 | PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r |
4724 | );\r | |
c37e0f16 CP |
4725 | ShellPrintEx (-1, -1,\r |
4726 | L" Data Link Layer Link Active(13): %E%d%N\r\n",\r | |
5d73d92f | 4727 | PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r |
4728 | );\r | |
c37e0f16 CP |
4729 | ShellPrintEx (-1, -1,\r |
4730 | L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r | |
5d73d92f | 4731 | PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r |
4732 | );\r | |
c37e0f16 CP |
4733 | ShellPrintEx (-1, -1,\r |
4734 | L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r | |
5d73d92f | 4735 | PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r |
4736 | );\r | |
4737 | return EFI_SUCCESS;\r | |
4738 | }\r | |
4739 | \r | |
a1d4bfcc | 4740 | /**\r |
4741 | Print out information of the device slot information.\r | |
4742 | \r | |
4743 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4744 | \r | |
4745 | @retval EFI_SUCCESS The operation was successful.\r | |
4746 | **/\r | |
5d73d92f | 4747 | EFI_STATUS\r |
4748 | ExplainPcieSlotCap (\r | |
2412c297 | 4749 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4750 | )\r |
5d73d92f | 4751 | {\r |
4752 | UINT32 PcieSlotCap;\r | |
4753 | \r | |
4754 | PcieSlotCap = PciExpressCap->SlotCap;\r | |
4755 | \r | |
c37e0f16 CP |
4756 | ShellPrintEx (-1, -1,\r |
4757 | L" Attention Button Present(0): %E%d%N\r\n",\r | |
5d73d92f | 4758 | PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r |
4759 | );\r | |
c37e0f16 CP |
4760 | ShellPrintEx (-1, -1,\r |
4761 | L" Power Controller Present(1): %E%d%N\r\n",\r | |
5d73d92f | 4762 | PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r |
4763 | );\r | |
c37e0f16 CP |
4764 | ShellPrintEx (-1, -1,\r |
4765 | L" MRL Sensor Present(2): %E%d%N\r\n",\r | |
5d73d92f | 4766 | PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r |
4767 | );\r | |
c37e0f16 CP |
4768 | ShellPrintEx (-1, -1,\r |
4769 | L" Attention Indicator Present(3): %E%d%N\r\n",\r | |
5d73d92f | 4770 | PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r |
4771 | );\r | |
c37e0f16 CP |
4772 | ShellPrintEx (-1, -1,\r |
4773 | L" Power Indicator Present(4): %E%d%N\r\n",\r | |
5d73d92f | 4774 | PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r |
4775 | );\r | |
c37e0f16 CP |
4776 | ShellPrintEx (-1, -1,\r |
4777 | L" Hot-Plug Surprise(5): %E%d%N\r\n",\r | |
5d73d92f | 4778 | PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r |
4779 | );\r | |
c37e0f16 CP |
4780 | ShellPrintEx (-1, -1,\r |
4781 | L" Hot-Plug Capable(6): %E%d%N\r\n",\r | |
5d73d92f | 4782 | PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r |
4783 | );\r | |
c37e0f16 CP |
4784 | ShellPrintEx (-1, -1,\r |
4785 | L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r | |
5d73d92f | 4786 | PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r |
4787 | );\r | |
c37e0f16 CP |
4788 | ShellPrintEx (-1, -1,\r |
4789 | L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r | |
5d73d92f | 4790 | SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r |
4791 | );\r | |
c37e0f16 CP |
4792 | ShellPrintEx (-1, -1,\r |
4793 | L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r | |
5d73d92f | 4794 | PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r |
4795 | );\r | |
c37e0f16 CP |
4796 | ShellPrintEx (-1, -1,\r |
4797 | L" No Command Completed Support(18): %E%d%N\r\n",\r | |
5d73d92f | 4798 | PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r |
4799 | );\r | |
c37e0f16 CP |
4800 | ShellPrintEx (-1, -1,\r |
4801 | L" Physical Slot Number(31:19): %E%d%N\r\n",\r | |
5d73d92f | 4802 | PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r |
4803 | );\r | |
4804 | \r | |
4805 | return EFI_SUCCESS;\r | |
4806 | }\r | |
4807 | \r | |
a1d4bfcc | 4808 | /**\r |
4809 | Print out information of the device slot control information.\r | |
4810 | \r | |
4811 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4812 | \r | |
4813 | @retval EFI_SUCCESS The operation was successful.\r | |
4814 | **/\r | |
5d73d92f | 4815 | EFI_STATUS\r |
4816 | ExplainPcieSlotControl (\r | |
2412c297 | 4817 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4818 | )\r |
5d73d92f | 4819 | {\r |
4820 | UINT16 PcieSlotControl;\r | |
4821 | \r | |
4822 | PcieSlotControl = PciExpressCap->SlotControl;\r | |
c37e0f16 CP |
4823 | ShellPrintEx (-1, -1,\r |
4824 | L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r | |
5d73d92f | 4825 | PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r |
4826 | );\r | |
c37e0f16 CP |
4827 | ShellPrintEx (-1, -1,\r |
4828 | L" Power Fault Detected Enable(1): %E%d%N\r\n",\r | |
5d73d92f | 4829 | PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r |
4830 | );\r | |
c37e0f16 CP |
4831 | ShellPrintEx (-1, -1,\r |
4832 | L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r | |
5d73d92f | 4833 | PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r |
4834 | );\r | |
c37e0f16 CP |
4835 | ShellPrintEx (-1, -1,\r |
4836 | L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r | |
5d73d92f | 4837 | PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r |
4838 | );\r | |
c37e0f16 CP |
4839 | ShellPrintEx (-1, -1,\r |
4840 | L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r | |
5d73d92f | 4841 | PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r |
4842 | );\r | |
c37e0f16 CP |
4843 | ShellPrintEx (-1, -1,\r |
4844 | L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r | |
5d73d92f | 4845 | PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r |
4846 | );\r | |
c37e0f16 CP |
4847 | ShellPrintEx (-1, -1,\r |
4848 | L" Attention Indicator Control(7:6): %E%s%N\r\n",\r | |
5d73d92f | 4849 | IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r |
4850 | );\r | |
c37e0f16 CP |
4851 | ShellPrintEx (-1, -1,\r |
4852 | L" Power Indicator Control(9:8): %E%s%N\r\n",\r | |
5d73d92f | 4853 | IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r |
4854 | );\r | |
c37e0f16 | 4855 | ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r |
5d73d92f | 4856 | if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r |
c37e0f16 | 4857 | ShellPrintEx (-1, -1, L"Off%N\r\n");\r |
5d73d92f | 4858 | } else {\r |
c37e0f16 | 4859 | ShellPrintEx (-1, -1, L"On%N\r\n");\r |
5d73d92f | 4860 | }\r |
c37e0f16 CP |
4861 | ShellPrintEx (-1, -1,\r |
4862 | L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r | |
5d73d92f | 4863 | PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r |
4864 | );\r | |
c37e0f16 CP |
4865 | ShellPrintEx (-1, -1,\r |
4866 | L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r | |
5d73d92f | 4867 | PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r |
4868 | );\r | |
4869 | return EFI_SUCCESS;\r | |
4870 | }\r | |
4871 | \r | |
a1d4bfcc | 4872 | /**\r |
4873 | Print out information of the device slot status information.\r | |
4874 | \r | |
4875 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4876 | \r | |
4877 | @retval EFI_SUCCESS The operation was successful.\r | |
4878 | **/\r | |
5d73d92f | 4879 | EFI_STATUS\r |
4880 | ExplainPcieSlotStatus (\r | |
2412c297 | 4881 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4882 | )\r |
5d73d92f | 4883 | {\r |
4884 | UINT16 PcieSlotStatus;\r | |
4885 | \r | |
4886 | PcieSlotStatus = PciExpressCap->SlotStatus;\r | |
4887 | \r | |
c37e0f16 CP |
4888 | ShellPrintEx (-1, -1,\r |
4889 | L" Attention Button Pressed(0): %E%d%N\r\n",\r | |
5d73d92f | 4890 | PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r |
4891 | );\r | |
c37e0f16 CP |
4892 | ShellPrintEx (-1, -1,\r |
4893 | L" Power Fault Detected(1): %E%d%N\r\n",\r | |
5d73d92f | 4894 | PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r |
4895 | );\r | |
c37e0f16 CP |
4896 | ShellPrintEx (-1, -1,\r |
4897 | L" MRL Sensor Changed(2): %E%d%N\r\n",\r | |
5d73d92f | 4898 | PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r |
4899 | );\r | |
c37e0f16 CP |
4900 | ShellPrintEx (-1, -1,\r |
4901 | L" Presence Detect Changed(3): %E%d%N\r\n",\r | |
5d73d92f | 4902 | PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r |
4903 | );\r | |
c37e0f16 CP |
4904 | ShellPrintEx (-1, -1,\r |
4905 | L" Command Completed(4): %E%d%N\r\n",\r | |
5d73d92f | 4906 | PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r |
4907 | );\r | |
c37e0f16 | 4908 | ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r |
5d73d92f | 4909 | if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r |
c37e0f16 | 4910 | ShellPrintEx (-1, -1, L" Opened%N\r\n");\r |
5d73d92f | 4911 | } else {\r |
c37e0f16 | 4912 | ShellPrintEx (-1, -1, L" Closed%N\r\n");\r |
5d73d92f | 4913 | }\r |
c37e0f16 | 4914 | ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r |
5d73d92f | 4915 | if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r |
c37e0f16 | 4916 | ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r |
5d73d92f | 4917 | } else {\r |
c37e0f16 | 4918 | ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r |
5d73d92f | 4919 | }\r |
c37e0f16 | 4920 | ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r |
5d73d92f | 4921 | if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r |
c37e0f16 | 4922 | ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r |
5d73d92f | 4923 | } else {\r |
c37e0f16 | 4924 | ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r |
5d73d92f | 4925 | }\r |
c37e0f16 CP |
4926 | ShellPrintEx (-1, -1,\r |
4927 | L" Data Link Layer State Changed(8): %E%d%N\r\n",\r | |
5d73d92f | 4928 | PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r |
4929 | );\r | |
4930 | return EFI_SUCCESS;\r | |
4931 | }\r | |
4932 | \r | |
a1d4bfcc | 4933 | /**\r |
4934 | Print out information of the device root information.\r | |
4935 | \r | |
4936 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4937 | \r | |
4938 | @retval EFI_SUCCESS The operation was successful.\r | |
4939 | **/\r | |
5d73d92f | 4940 | EFI_STATUS\r |
4941 | ExplainPcieRootControl (\r | |
2412c297 | 4942 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4943 | )\r |
5d73d92f | 4944 | {\r |
4945 | UINT16 PcieRootControl;\r | |
4946 | \r | |
4947 | PcieRootControl = PciExpressCap->RootControl;\r | |
4948 | \r | |
c37e0f16 CP |
4949 | ShellPrintEx (-1, -1,\r |
4950 | L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r | |
5d73d92f | 4951 | PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r |
4952 | );\r | |
c37e0f16 CP |
4953 | ShellPrintEx (-1, -1,\r |
4954 | L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r | |
5d73d92f | 4955 | PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r |
4956 | );\r | |
c37e0f16 CP |
4957 | ShellPrintEx (-1, -1,\r |
4958 | L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r | |
5d73d92f | 4959 | PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r |
4960 | );\r | |
c37e0f16 CP |
4961 | ShellPrintEx (-1, -1,\r |
4962 | L" PME Interrupt Enable(3): %E%d%N\r\n",\r | |
5d73d92f | 4963 | PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r |
4964 | );\r | |
c37e0f16 CP |
4965 | ShellPrintEx (-1, -1,\r |
4966 | L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r | |
5d73d92f | 4967 | PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r |
4968 | );\r | |
4969 | \r | |
4970 | return EFI_SUCCESS;\r | |
4971 | }\r | |
4972 | \r | |
a1d4bfcc | 4973 | /**\r |
4974 | Print out information of the device root capability information.\r | |
4975 | \r | |
4976 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4977 | \r | |
4978 | @retval EFI_SUCCESS The operation was successful.\r | |
4979 | **/\r | |
5d73d92f | 4980 | EFI_STATUS\r |
4981 | ExplainPcieRootCap (\r | |
2412c297 | 4982 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 4983 | )\r |
5d73d92f | 4984 | {\r |
4985 | UINT16 PcieRootCap;\r | |
4986 | \r | |
4987 | PcieRootCap = PciExpressCap->RsvdP;\r | |
4988 | \r | |
c37e0f16 CP |
4989 | ShellPrintEx (-1, -1,\r |
4990 | L" CRS Software Visibility(0): %E%d%N\r\n",\r | |
5d73d92f | 4991 | PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r |
4992 | );\r | |
4993 | \r | |
4994 | return EFI_SUCCESS;\r | |
4995 | }\r | |
4996 | \r | |
a1d4bfcc | 4997 | /**\r |
4998 | Print out information of the device root status information.\r | |
4999 | \r | |
5000 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5001 | \r | |
5002 | @retval EFI_SUCCESS The operation was successful.\r | |
5003 | **/\r | |
5d73d92f | 5004 | EFI_STATUS\r |
5005 | ExplainPcieRootStatus (\r | |
2412c297 | 5006 | IN PCIE_CAP_STRUCTURE *PciExpressCap\r |
a1d4bfcc | 5007 | )\r |
5d73d92f | 5008 | {\r |
5009 | UINT32 PcieRootStatus;\r | |
5010 | \r | |
5011 | PcieRootStatus = PciExpressCap->RootStatus;\r | |
5012 | \r | |
c37e0f16 CP |
5013 | ShellPrintEx (-1, -1,\r |
5014 | L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r | |
5d73d92f | 5015 | PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r |
5016 | );\r | |
c37e0f16 CP |
5017 | ShellPrintEx (-1, -1,\r |
5018 | L" PME Status(16): %E%d%N\r\n",\r | |
5d73d92f | 5019 | PCIE_CAP_PME_STATUS (PcieRootStatus)\r |
5020 | );\r | |
c37e0f16 CP |
5021 | ShellPrintEx (-1, -1,\r |
5022 | L" PME Pending(17): %E%d%N\r\n",\r | |
5d73d92f | 5023 | PCIE_CAP_PME_PENDING (PcieRootStatus)\r |
5024 | );\r | |
5025 | return EFI_SUCCESS;\r | |
5026 | }\r | |
5027 | \r | |
705bffb5 JC |
5028 | /**\r |
5029 | Function to interpret and print out the link control structure\r | |
5030 | \r | |
5031 | @param[in] HeaderAddress The Address of this capability header.\r | |
5032 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5033 | **/\r | |
5034 | EFI_STATUS\r | |
5035 | EFIAPI\r | |
5036 | PrintInterpretedExtendedCompatibilityLinkControl (\r | |
5037 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5038 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5039 | )\r | |
5040 | {\r | |
5041 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r | |
5042 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r | |
5043 | \r | |
5044 | ShellPrintHiiEx(\r | |
5045 | -1, -1, NULL, \r | |
5046 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r | |
5047 | gShellDebug1HiiHandle, \r | |
5048 | Header->RootComplexLinkCapabilities,\r | |
5049 | Header->RootComplexLinkControl,\r | |
5050 | Header->RootComplexLinkStatus\r | |
5051 | ); \r | |
5052 | DumpHex (\r | |
5053 | 4,\r | |
5054 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5055 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r | |
5056 | (VOID *) (HeaderAddress)\r | |
5057 | );\r | |
5058 | return (EFI_SUCCESS);\r | |
5059 | }\r | |
5060 | \r | |
5061 | /**\r | |
5062 | Function to interpret and print out the power budgeting structure\r | |
5063 | \r | |
5064 | @param[in] HeaderAddress The Address of this capability header.\r | |
5065 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5066 | **/\r | |
5067 | EFI_STATUS\r | |
5068 | EFIAPI\r | |
5069 | PrintInterpretedExtendedCompatibilityPowerBudgeting (\r | |
5070 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5071 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5072 | )\r | |
5073 | {\r | |
5074 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r | |
5075 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r | |
5076 | \r | |
5077 | ShellPrintHiiEx(\r | |
5078 | -1, -1, NULL, \r | |
5079 | STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r | |
5080 | gShellDebug1HiiHandle, \r | |
5081 | Header->DataSelect,\r | |
5082 | Header->Data,\r | |
5083 | Header->PowerBudgetCapability\r | |
5084 | ); \r | |
5085 | DumpHex (\r | |
5086 | 4,\r | |
5087 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5088 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r | |
5089 | (VOID *) (HeaderAddress)\r | |
5090 | );\r | |
5091 | return (EFI_SUCCESS);\r | |
5092 | }\r | |
5093 | \r | |
5094 | /**\r | |
5095 | Function to interpret and print out the ACS structure\r | |
5096 | \r | |
5097 | @param[in] HeaderAddress The Address of this capability header.\r | |
5098 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5099 | **/\r | |
5100 | EFI_STATUS\r | |
5101 | EFIAPI\r | |
5102 | PrintInterpretedExtendedCompatibilityAcs (\r | |
5103 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5104 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5105 | )\r | |
5106 | {\r | |
5107 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r | |
5108 | UINT16 VectorSize;\r | |
5109 | UINT16 LoopCounter;\r | |
5110 | \r | |
5111 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r | |
5112 | VectorSize = 0;\r | |
5113 | \r | |
5114 | ShellPrintHiiEx(\r | |
5115 | -1, -1, NULL, \r | |
5116 | STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r | |
5117 | gShellDebug1HiiHandle, \r | |
5118 | Header->AcsCapability,\r | |
5119 | Header->AcsControl\r | |
5120 | ); \r | |
5121 | if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r | |
5122 | VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r | |
5123 | if (VectorSize == 0) {\r | |
5124 | VectorSize = 256;\r | |
5125 | }\r | |
5126 | for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r | |
5127 | ShellPrintHiiEx(\r | |
5128 | -1, -1, NULL, \r | |
5129 | STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r | |
5130 | gShellDebug1HiiHandle, \r | |
5131 | LoopCounter + 1,\r | |
5132 | Header->EgressControlVectorArray[LoopCounter]\r | |
5133 | ); \r | |
5134 | }\r | |
5135 | }\r | |
5136 | DumpHex (\r | |
5137 | 4,\r | |
5138 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5139 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r | |
5140 | (VOID *) (HeaderAddress)\r | |
5141 | );\r | |
5142 | return (EFI_SUCCESS);\r | |
5143 | }\r | |
5144 | \r | |
5145 | /**\r | |
5146 | Function to interpret and print out the latency tolerance reporting structure\r | |
5147 | \r | |
5148 | @param[in] HeaderAddress The Address of this capability header.\r | |
5149 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5150 | **/\r | |
5151 | EFI_STATUS\r | |
5152 | EFIAPI\r | |
5153 | PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r | |
5154 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5155 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5156 | )\r | |
5157 | {\r | |
5158 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r | |
5159 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r | |
5160 | \r | |
5161 | ShellPrintHiiEx(\r | |
5162 | -1, -1, NULL, \r | |
5163 | STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r | |
5164 | gShellDebug1HiiHandle, \r | |
5165 | Header->MaxSnoopLatency,\r | |
5166 | Header->MaxNoSnoopLatency\r | |
5167 | ); \r | |
5168 | DumpHex (\r | |
5169 | 4,\r | |
5170 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5171 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r | |
5172 | (VOID *) (HeaderAddress)\r | |
5173 | );\r | |
5174 | return (EFI_SUCCESS);\r | |
5175 | }\r | |
5176 | \r | |
5177 | /**\r | |
5178 | Function to interpret and print out the serial number structure\r | |
5179 | \r | |
5180 | @param[in] HeaderAddress The Address of this capability header.\r | |
5181 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5182 | **/\r | |
5183 | EFI_STATUS\r | |
5184 | EFIAPI\r | |
5185 | PrintInterpretedExtendedCompatibilitySerialNumber (\r | |
5186 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5187 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5188 | )\r | |
5189 | {\r | |
5190 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r | |
5191 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r | |
5192 | \r | |
5193 | ShellPrintHiiEx(\r | |
5194 | -1, -1, NULL, \r | |
5195 | STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r | |
5196 | gShellDebug1HiiHandle, \r | |
5197 | Header->SerialNumber\r | |
5198 | ); \r | |
5199 | DumpHex (\r | |
5200 | 4,\r | |
5201 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5202 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r | |
5203 | (VOID *) (HeaderAddress)\r | |
5204 | );\r | |
5205 | return (EFI_SUCCESS);\r | |
5206 | }\r | |
5207 | \r | |
5208 | /**\r | |
5209 | Function to interpret and print out the RCRB structure\r | |
5210 | \r | |
5211 | @param[in] HeaderAddress The Address of this capability header.\r | |
5212 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5213 | **/\r | |
5214 | EFI_STATUS\r | |
5215 | EFIAPI\r | |
5216 | PrintInterpretedExtendedCompatibilityRcrb (\r | |
5217 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5218 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5219 | )\r | |
5220 | {\r | |
5221 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r | |
5222 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r | |
5223 | \r | |
5224 | ShellPrintHiiEx(\r | |
5225 | -1, -1, NULL, \r | |
5226 | STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r | |
5227 | gShellDebug1HiiHandle, \r | |
5228 | Header->VendorId,\r | |
5229 | Header->DeviceId,\r | |
5230 | Header->RcrbCapabilities,\r | |
5231 | Header->RcrbControl\r | |
5232 | ); \r | |
5233 | DumpHex (\r | |
5234 | 4,\r | |
5235 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5236 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r | |
5237 | (VOID *) (HeaderAddress)\r | |
5238 | );\r | |
5239 | return (EFI_SUCCESS);\r | |
5240 | }\r | |
5241 | \r | |
5242 | /**\r | |
5243 | Function to interpret and print out the vendor specific structure\r | |
5244 | \r | |
5245 | @param[in] HeaderAddress The Address of this capability header.\r | |
5246 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5247 | **/\r | |
5248 | EFI_STATUS\r | |
5249 | EFIAPI\r | |
5250 | PrintInterpretedExtendedCompatibilityVendorSpecific (\r | |
5251 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5252 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5253 | )\r | |
5254 | {\r | |
5255 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r | |
5256 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r | |
5257 | \r | |
5258 | ShellPrintHiiEx(\r | |
5259 | -1, -1, NULL, \r | |
5260 | STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r | |
5261 | gShellDebug1HiiHandle, \r | |
5262 | Header->VendorSpecificHeader\r | |
5263 | ); \r | |
5264 | DumpHex (\r | |
5265 | 4,\r | |
5266 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5267 | PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r | |
5268 | (VOID *) (HeaderAddress)\r | |
5269 | );\r | |
5270 | return (EFI_SUCCESS);\r | |
5271 | }\r | |
5272 | \r | |
5273 | /**\r | |
5274 | Function to interpret and print out the Event Collector Endpoint Association structure\r | |
5275 | \r | |
5276 | @param[in] HeaderAddress The Address of this capability header.\r | |
5277 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5278 | **/\r | |
5279 | EFI_STATUS\r | |
5280 | EFIAPI\r | |
5281 | PrintInterpretedExtendedCompatibilityECEA (\r | |
5282 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5283 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5284 | )\r | |
5285 | {\r | |
5286 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r | |
5287 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r | |
5288 | \r | |
5289 | ShellPrintHiiEx(\r | |
5290 | -1, -1, NULL, \r | |
5291 | STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r | |
5292 | gShellDebug1HiiHandle, \r | |
5293 | Header->AssociationBitmap\r | |
5294 | ); \r | |
5295 | DumpHex (\r | |
5296 | 4,\r | |
5297 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5298 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r | |
5299 | (VOID *) (HeaderAddress)\r | |
5300 | );\r | |
5301 | return (EFI_SUCCESS);\r | |
5302 | }\r | |
5303 | \r | |
5304 | /**\r | |
5305 | Function to interpret and print out the ARI structure\r | |
5306 | \r | |
5307 | @param[in] HeaderAddress The Address of this capability header.\r | |
5308 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5309 | **/\r | |
5310 | EFI_STATUS\r | |
5311 | EFIAPI\r | |
5312 | PrintInterpretedExtendedCompatibilityAri (\r | |
5313 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5314 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5315 | )\r | |
5316 | {\r | |
5317 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r | |
5318 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r | |
5319 | \r | |
5320 | ShellPrintHiiEx(\r | |
5321 | -1, -1, NULL, \r | |
5322 | STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r | |
5323 | gShellDebug1HiiHandle, \r | |
5324 | Header->AriCapability,\r | |
5325 | Header->AriControl\r | |
5326 | ); \r | |
5327 | DumpHex (\r | |
5328 | 4,\r | |
5329 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5330 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r | |
5331 | (VOID *) (HeaderAddress)\r | |
5332 | );\r | |
5333 | return (EFI_SUCCESS);\r | |
5334 | }\r | |
5335 | \r | |
5336 | /**\r | |
5337 | Function to interpret and print out the DPA structure\r | |
5338 | \r | |
5339 | @param[in] HeaderAddress The Address of this capability header.\r | |
5340 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5341 | **/\r | |
5342 | EFI_STATUS\r | |
5343 | EFIAPI\r | |
5344 | PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r | |
5345 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5346 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5347 | )\r | |
5348 | {\r | |
5349 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r | |
5350 | UINT8 LinkCount;\r | |
5351 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r | |
5352 | \r | |
5353 | ShellPrintHiiEx(\r | |
5354 | -1, -1, NULL, \r | |
5355 | STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r | |
5356 | gShellDebug1HiiHandle, \r | |
5357 | Header->DpaCapability,\r | |
5358 | Header->DpaLatencyIndicator,\r | |
5359 | Header->DpaStatus,\r | |
5360 | Header->DpaControl\r | |
5361 | ); \r | |
5362 | for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r | |
5363 | ShellPrintHiiEx(\r | |
5364 | -1, -1, NULL, \r | |
5365 | STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r | |
5366 | gShellDebug1HiiHandle, \r | |
5367 | LinkCount+1,\r | |
5368 | Header->DpaPowerAllocationArray[LinkCount]\r | |
5369 | );\r | |
5370 | }\r | |
5371 | DumpHex (\r | |
5372 | 4,\r | |
5373 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5374 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r | |
5375 | (VOID *) (HeaderAddress)\r | |
5376 | );\r | |
5377 | return (EFI_SUCCESS);\r | |
5378 | }\r | |
5379 | \r | |
5380 | /**\r | |
5381 | Function to interpret and print out the link declaration structure\r | |
5382 | \r | |
5383 | @param[in] HeaderAddress The Address of this capability header.\r | |
5384 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5385 | **/\r | |
5386 | EFI_STATUS\r | |
5387 | EFIAPI\r | |
5388 | PrintInterpretedExtendedCompatibilityLinkDeclaration (\r | |
5389 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5390 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5391 | )\r | |
5392 | {\r | |
5393 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r | |
5394 | UINT8 LinkCount;\r | |
5395 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r | |
5396 | \r | |
5397 | ShellPrintHiiEx(\r | |
5398 | -1, -1, NULL, \r | |
5399 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r | |
5400 | gShellDebug1HiiHandle, \r | |
5401 | Header->ElementSelfDescription\r | |
5402 | );\r | |
5403 | \r | |
5404 | for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r | |
5405 | ShellPrintHiiEx(\r | |
5406 | -1, -1, NULL, \r | |
5407 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r | |
5408 | gShellDebug1HiiHandle, \r | |
5409 | LinkCount+1,\r | |
5410 | Header->LinkEntry[LinkCount]\r | |
5411 | );\r | |
5412 | }\r | |
5413 | DumpHex (\r | |
5414 | 4,\r | |
5415 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5416 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r | |
5417 | (VOID *) (HeaderAddress)\r | |
5418 | );\r | |
5419 | return (EFI_SUCCESS);\r | |
5420 | }\r | |
5421 | \r | |
5422 | /**\r | |
5423 | Function to interpret and print out the Advanced Error Reporting structure\r | |
5424 | \r | |
5425 | @param[in] HeaderAddress The Address of this capability header.\r | |
5426 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5427 | **/\r | |
5428 | EFI_STATUS\r | |
5429 | EFIAPI\r | |
5430 | PrintInterpretedExtendedCompatibilityAer (\r | |
5431 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5432 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5433 | )\r | |
5434 | {\r | |
5435 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r | |
5436 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r | |
5437 | \r | |
5438 | ShellPrintHiiEx(\r | |
5439 | -1, -1, NULL, \r | |
5440 | STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r | |
5441 | gShellDebug1HiiHandle, \r | |
5442 | Header->UncorrectableErrorStatus,\r | |
5443 | Header->UncorrectableErrorMask,\r | |
5444 | Header->UncorrectableErrorSeverity,\r | |
5445 | Header->CorrectableErrorStatus,\r | |
5446 | Header->CorrectableErrorMask,\r | |
5447 | Header->AdvancedErrorCapabilitiesAndControl,\r | |
231ad7d8 QS |
5448 | Header->HeaderLog[0],\r |
5449 | Header->HeaderLog[1],\r | |
5450 | Header->HeaderLog[2],\r | |
5451 | Header->HeaderLog[3],\r | |
705bffb5 JC |
5452 | Header->RootErrorCommand,\r |
5453 | Header->RootErrorStatus,\r | |
5454 | Header->ErrorSourceIdentification,\r | |
5455 | Header->CorrectableErrorSourceIdentification,\r | |
5456 | Header->TlpPrefixLog[0],\r | |
5457 | Header->TlpPrefixLog[1],\r | |
5458 | Header->TlpPrefixLog[2],\r | |
5459 | Header->TlpPrefixLog[3]\r | |
5460 | );\r | |
5461 | DumpHex (\r | |
5462 | 4,\r | |
5463 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5464 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r | |
5465 | (VOID *) (HeaderAddress)\r | |
5466 | );\r | |
5467 | return (EFI_SUCCESS);\r | |
5468 | }\r | |
5469 | \r | |
9f7f0697 JC |
5470 | /**\r |
5471 | Function to interpret and print out the multicast structure\r | |
5472 | \r | |
5473 | @param[in] HeaderAddress The Address of this capability header.\r | |
5474 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5475 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5476 | **/\r | |
5477 | EFI_STATUS\r | |
5478 | EFIAPI\r | |
5479 | PrintInterpretedExtendedCompatibilityMulticast (\r | |
5480 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5481 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r | |
2412c297 | 5482 | IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r |
9f7f0697 JC |
5483 | )\r |
5484 | {\r | |
5485 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r | |
5486 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r | |
5487 | \r | |
5488 | ShellPrintHiiEx(\r | |
5489 | -1, -1, NULL, \r | |
5490 | STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r | |
5491 | gShellDebug1HiiHandle, \r | |
5492 | Header->MultiCastCapability,\r | |
5493 | Header->MulticastControl,\r | |
5494 | Header->McBaseAddress,\r | |
5495 | Header->McReceiveAddress,\r | |
5496 | Header->McBlockAll,\r | |
5497 | Header->McBlockUntranslated,\r | |
5498 | Header->McOverlayBar\r | |
5499 | );\r | |
5500 | \r | |
5501 | DumpHex (\r | |
5502 | 4,\r | |
5503 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5504 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r | |
5505 | (VOID *) (HeaderAddress)\r | |
5506 | );\r | |
5507 | \r | |
5508 | return (EFI_SUCCESS);\r | |
5509 | }\r | |
5510 | \r | |
5511 | /**\r | |
5512 | Function to interpret and print out the virtual channel and multi virtual channel structure\r | |
5513 | \r | |
5514 | @param[in] HeaderAddress The Address of this capability header.\r | |
5515 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5516 | **/\r | |
5517 | EFI_STATUS\r | |
5518 | EFIAPI\r | |
5519 | PrintInterpretedExtendedCompatibilityVirtualChannel (\r | |
5520 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5521 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5522 | )\r | |
5523 | {\r | |
5524 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r | |
5525 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r | |
5526 | UINT32 ItemCount;\r | |
5527 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r | |
5528 | \r | |
5529 | ShellPrintHiiEx(\r | |
5530 | -1, -1, NULL, \r | |
5531 | STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r | |
5532 | gShellDebug1HiiHandle, \r | |
5533 | Header->ExtendedVcCount,\r | |
5534 | Header->PortVcCapability1,\r | |
5535 | Header->PortVcCapability2,\r | |
5536 | Header->VcArbTableOffset,\r | |
5537 | Header->PortVcControl,\r | |
5538 | Header->PortVcStatus\r | |
5539 | );\r | |
5540 | for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r | |
5541 | CapabilityItem = &Header->Capability[ItemCount];\r | |
5542 | ShellPrintHiiEx(\r | |
5543 | -1, -1, NULL, \r | |
5544 | STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r | |
5545 | gShellDebug1HiiHandle, \r | |
5546 | ItemCount+1,\r | |
5547 | CapabilityItem->VcResourceCapability,\r | |
5548 | CapabilityItem->PortArbTableOffset,\r | |
5549 | CapabilityItem->VcResourceControl,\r | |
5550 | CapabilityItem->VcResourceStatus\r | |
5551 | );\r | |
5552 | }\r | |
5553 | \r | |
5554 | DumpHex (\r | |
5555 | 4,\r | |
5556 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5557 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),\r | |
5558 | (VOID *) (HeaderAddress)\r | |
5559 | );\r | |
5560 | \r | |
5561 | return (EFI_SUCCESS);\r | |
5562 | }\r | |
5563 | \r | |
5564 | /**\r | |
5565 | Function to interpret and print out the resizeable bar structure\r | |
5566 | \r | |
5567 | @param[in] HeaderAddress The Address of this capability header.\r | |
5568 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5569 | **/\r | |
5570 | EFI_STATUS\r | |
5571 | EFIAPI\r | |
5572 | PrintInterpretedExtendedCompatibilityResizeableBar (\r | |
5573 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5574 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5575 | )\r | |
5576 | {\r | |
5577 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r | |
5578 | UINT32 ItemCount;\r | |
5579 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r | |
5580 | \r | |
5581 | for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r | |
5582 | ShellPrintHiiEx(\r | |
5583 | -1, -1, NULL, \r | |
5584 | STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r | |
5585 | gShellDebug1HiiHandle, \r | |
5586 | ItemCount+1,\r | |
5587 | Header->Capability[ItemCount].ResizableBarCapability,\r | |
5588 | Header->Capability[ItemCount].ResizableBarControl\r | |
5589 | );\r | |
5590 | }\r | |
5591 | \r | |
5592 | DumpHex (\r | |
5593 | 4,\r | |
5594 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5595 | (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r | |
5596 | (VOID *) (HeaderAddress)\r | |
5597 | );\r | |
5598 | \r | |
5599 | return (EFI_SUCCESS);\r | |
5600 | }\r | |
5601 | \r | |
5602 | /**\r | |
5603 | Function to interpret and print out the TPH structure\r | |
5604 | \r | |
5605 | @param[in] HeaderAddress The Address of this capability header.\r | |
5606 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5607 | **/\r | |
5608 | EFI_STATUS\r | |
5609 | EFIAPI\r | |
5610 | PrintInterpretedExtendedCompatibilityTph (\r | |
5611 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5612 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5613 | )\r | |
5614 | {\r | |
5615 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r | |
5616 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r | |
5617 | \r | |
5618 | ShellPrintHiiEx(\r | |
5619 | -1, -1, NULL, \r | |
5620 | STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r | |
5621 | gShellDebug1HiiHandle, \r | |
5622 | Header->TphRequesterCapability,\r | |
5623 | Header->TphRequesterControl\r | |
5624 | );\r | |
5625 | DumpHex (\r | |
5626 | 8,\r | |
5627 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r | |
5628 | GET_TPH_TABLE_SIZE(Header),\r | |
5629 | (VOID *)Header->TphStTable\r | |
5630 | );\r | |
5631 | \r | |
5632 | DumpHex (\r | |
5633 | 4,\r | |
5634 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5635 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r | |
5636 | (VOID *) (HeaderAddress)\r | |
5637 | );\r | |
5638 | \r | |
5639 | return (EFI_SUCCESS);\r | |
5640 | }\r | |
5641 | \r | |
5642 | /**\r | |
5643 | Function to interpret and print out the secondary PCIe capability structure\r | |
5644 | \r | |
5645 | @param[in] HeaderAddress The Address of this capability header.\r | |
5646 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5647 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5648 | **/\r | |
5649 | EFI_STATUS\r | |
5650 | EFIAPI\r | |
5651 | PrintInterpretedExtendedCompatibilitySecondary (\r | |
5652 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5653 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r | |
2412c297 | 5654 | IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r |
9f7f0697 JC |
5655 | )\r |
5656 | {\r | |
5657 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r | |
5658 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r | |
5659 | \r | |
5660 | ShellPrintHiiEx(\r | |
5661 | -1, -1, NULL, \r | |
5662 | STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r | |
5663 | gShellDebug1HiiHandle, \r | |
5664 | Header->LinkControl3,\r | |
5665 | Header->LaneErrorStatus\r | |
5666 | );\r | |
5667 | DumpHex (\r | |
5668 | 8,\r | |
5669 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r | |
5670 | PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r | |
5671 | (VOID *)Header->EqualizationControl\r | |
5672 | );\r | |
5673 | \r | |
5674 | DumpHex (\r | |
5675 | 4,\r | |
5676 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5677 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r | |
5678 | (VOID *) (HeaderAddress)\r | |
5679 | );\r | |
5680 | \r | |
5681 | return (EFI_SUCCESS);\r | |
5682 | }\r | |
5683 | \r | |
705bffb5 JC |
5684 | /**\r |
5685 | Display Pcie extended capability details\r | |
5686 | \r | |
5687 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5688 | @param[in] HeaderAddress The address of this capability header.\r | |
5689 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5690 | **/\r | |
5691 | EFI_STATUS\r | |
5692 | EFIAPI\r | |
5693 | PrintPciExtendedCapabilityDetails(\r | |
5694 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r | |
5695 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
2412c297 | 5696 | IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r |
705bffb5 JC |
5697 | )\r |
5698 | {\r | |
5699 | switch (HeaderAddress->CapabilityId){\r | |
5700 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r | |
5701 | return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5702 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r |
5703 | return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5704 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r |
5705 | return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5706 | case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r |
5707 | return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5708 | case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r |
5709 | return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5710 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r |
5711 | return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5712 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r |
5713 | return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5714 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r |
5715 | return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5716 | case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r |
5717 | return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5718 | case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r |
5719 | return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5720 | case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r |
5721 | return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5722 | case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r |
5723 | return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5724 | case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r |
5725 | case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r | |
9f7f0697 | 5726 | return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 5727 | case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r |
9f7f0697 JC |
5728 | //\r |
5729 | // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r | |
5730 | //\r | |
5731 | return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r | |
705bffb5 | 5732 | case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r |
9f7f0697 | 5733 | return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 5734 | case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r |
9f7f0697 | 5735 | return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 5736 | case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r |
9f7f0697 | 5737 | return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r |
705bffb5 JC |
5738 | default:\r |
5739 | ShellPrintEx (-1, -1,\r | |
5740 | L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r | |
5741 | HeaderAddress->CapabilityId\r | |
5742 | );\r | |
5743 | return EFI_SUCCESS;\r | |
705bffb5 JC |
5744 | };\r |
5745 | \r | |
5746 | }\r | |
5747 | \r | |
a1d4bfcc | 5748 | /**\r |
5749 | Display Pcie device structure.\r | |
5750 | \r | |
5751 | @param[in] IoDev The pointer to the root pci protocol.\r | |
5752 | @param[in] Address The Address to start at.\r | |
5753 | @param[in] CapabilityPtr The offset from the address to start.\r | |
f614ce7e SQ |
5754 | @param[in] EnhancedDump The print format for the dump data.\r |
5755 | \r | |
a1d4bfcc | 5756 | **/\r |
5d73d92f | 5757 | EFI_STATUS\r |
5758 | PciExplainPciExpress (\r | |
5759 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
5760 | IN UINT64 Address,\r | |
705bffb5 JC |
5761 | IN UINT8 CapabilityPtr,\r |
5762 | IN CONST UINT16 EnhancedDump\r | |
5d73d92f | 5763 | )\r |
5764 | {\r | |
5765 | \r | |
2412c297 | 5766 | PCIE_CAP_STRUCTURE PciExpressCap;\r |
5d73d92f | 5767 | EFI_STATUS Status;\r |
5768 | UINT64 CapRegAddress;\r | |
5769 | UINT8 Bus;\r | |
5770 | UINT8 Dev;\r | |
5771 | UINT8 Func;\r | |
5772 | UINT8 *ExRegBuffer;\r | |
5773 | UINTN ExtendRegSize;\r | |
5774 | UINT64 Pciex_Address;\r | |
5775 | UINT8 DevicePortType;\r | |
5776 | UINTN Index;\r | |
5777 | UINT8 *RegAddr;\r | |
5778 | UINTN RegValue;\r | |
705bffb5 | 5779 | PCI_EXP_EXT_HDR *ExtHdr;\r |
5d73d92f | 5780 | \r |
5781 | CapRegAddress = Address + CapabilityPtr;\r | |
5782 | IoDev->Pci.Read (\r | |
5783 | IoDev,\r | |
5784 | EfiPciWidthUint32,\r | |
5785 | CapRegAddress,\r | |
5786 | sizeof (PciExpressCap) / sizeof (UINT32),\r | |
5787 | &PciExpressCap\r | |
5788 | );\r | |
5789 | \r | |
5790 | DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r | |
5791 | \r | |
c37e0f16 | 5792 | ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r |
5d73d92f | 5793 | \r |
5794 | for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r | |
5795 | if (ShellGetExecutionBreakFlag()) {\r | |
5796 | goto Done;\r | |
5797 | }\r | |
5798 | RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r | |
5799 | switch (PcieExplainList[Index].Width) {\r | |
5800 | case FieldWidthUINT8:\r | |
5801 | RegValue = *(UINT8 *) RegAddr;\r | |
5802 | break;\r | |
5803 | case FieldWidthUINT16:\r | |
5804 | RegValue = *(UINT16 *) RegAddr;\r | |
5805 | break;\r | |
5806 | case FieldWidthUINT32:\r | |
5807 | RegValue = *(UINT32 *) RegAddr;\r | |
5808 | break;\r | |
5809 | default:\r | |
5810 | RegValue = 0;\r | |
5811 | break;\r | |
5812 | }\r | |
5813 | ShellPrintHiiEx(-1, -1, NULL,\r | |
5814 | PcieExplainList[Index].Token,\r | |
5815 | gShellDebug1HiiHandle,\r | |
5816 | PcieExplainList[Index].Offset,\r | |
5817 | RegValue\r | |
5818 | );\r | |
5819 | if (PcieExplainList[Index].Func == NULL) {\r | |
5820 | continue;\r | |
5821 | }\r | |
5822 | switch (PcieExplainList[Index].Type) {\r | |
5823 | case PcieExplainTypeLink:\r | |
5824 | //\r | |
5825 | // Link registers should not be used by\r | |
5826 | // a) Root Complex Integrated Endpoint\r | |
5827 | // b) Root Complex Event Collector\r | |
5828 | //\r | |
5829 | if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r | |
5830 | DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r | |
5831 | continue;\r | |
5832 | }\r | |
5833 | break;\r | |
5834 | case PcieExplainTypeSlot:\r | |
5835 | //\r | |
5836 | // Slot registers are only valid for\r | |
5837 | // a) Root Port of PCI Express Root Complex\r | |
5838 | // b) Downstream Port of PCI Express Switch\r | |
5839 | // and when SlotImplemented bit is set in PCIE cap register.\r | |
5840 | //\r | |
5841 | if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r | |
5842 | DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r | |
5843 | !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r | |
5844 | continue;\r | |
5845 | }\r | |
5846 | break;\r | |
5847 | case PcieExplainTypeRoot:\r | |
5848 | //\r | |
5849 | // Root registers are only valid for\r | |
5850 | // Root Port of PCI Express Root Complex\r | |
5851 | //\r | |
5852 | if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r | |
5853 | continue;\r | |
5854 | }\r | |
5855 | break;\r | |
5856 | default:\r | |
5857 | break;\r | |
5858 | }\r | |
5859 | PcieExplainList[Index].Func (&PciExpressCap);\r | |
5860 | }\r | |
5861 | \r | |
5862 | Bus = (UINT8) (RShiftU64 (Address, 24));\r | |
5863 | Dev = (UINT8) (RShiftU64 (Address, 16));\r | |
5864 | Func = (UINT8) (RShiftU64 (Address, 8));\r | |
5865 | \r | |
705bffb5 | 5866 | Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET);\r |
5d73d92f | 5867 | \r |
705bffb5 | 5868 | ExtendRegSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r |
5d73d92f | 5869 | \r |
3737ac2b | 5870 | ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r |
5d73d92f | 5871 | \r |
5872 | //\r | |
5873 | // PciRootBridgeIo protocol should support pci express extend space IO\r | |
705bffb5 | 5874 | // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)\r |
5d73d92f | 5875 | //\r |
5876 | Status = IoDev->Pci.Read (\r | |
5877 | IoDev,\r | |
5878 | EfiPciWidthUint32,\r | |
5879 | Pciex_Address,\r | |
5880 | (ExtendRegSize) / sizeof (UINT32),\r | |
5881 | (VOID *) (ExRegBuffer)\r | |
5882 | );\r | |
705bffb5 JC |
5883 | if (EFI_ERROR (Status) || ExRegBuffer == NULL) {\r |
5884 | SHELL_FREE_NON_NULL(ExRegBuffer);\r | |
5d73d92f | 5885 | return EFI_UNSUPPORTED;\r |
5886 | }\r | |
5d73d92f | 5887 | \r |
705bffb5 JC |
5888 | if (EnhancedDump == 0) {\r |
5889 | //\r | |
5890 | // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r | |
5891 | //\r | |
5892 | ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r | |
5893 | \r | |
d8f8021c | 5894 | DumpHex (\r |
5895 | 2,\r | |
705bffb5 | 5896 | EFI_PCIE_CAPABILITY_BASE_OFFSET,\r |
d8f8021c | 5897 | ExtendRegSize,\r |
5898 | (VOID *) (ExRegBuffer)\r | |
705bffb5 JC |
5899 | );\r |
5900 | } else {\r | |
5901 | ExtHdr = (PCI_EXP_EXT_HDR*)ExRegBuffer;\r | |
5902 | while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r | |
5903 | //\r | |
5904 | // Process this item\r | |
5905 | //\r | |
5906 | if (EnhancedDump == 0xFFFF || EnhancedDump == ExtHdr->CapabilityId) {\r | |
5907 | //\r | |
5908 | // Print this item\r | |
5909 | //\r | |
5910 | PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExRegBuffer, ExtHdr, &PciExpressCap);\r | |
5911 | }\r | |
5d73d92f | 5912 | \r |
705bffb5 JC |
5913 | //\r |
5914 | // Advance to the next item if it exists\r | |
5915 | //\r | |
5916 | if (ExtHdr->NextCapabilityOffset != 0) {\r | |
5917 | ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + ExtHdr->NextCapabilityOffset);\r | |
5918 | } else {\r | |
5919 | break;\r | |
5920 | }\r | |
5921 | }\r | |
d8f8021c | 5922 | }\r |
705bffb5 | 5923 | SHELL_FREE_NON_NULL(ExRegBuffer);\r |
5d73d92f | 5924 | \r |
5925 | Done:\r | |
5926 | return EFI_SUCCESS;\r | |
5927 | }\r |