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5d73d92f | 1 | /** @file\r |
2 | Main file for Pci shell Debug1 function.\r | |
3 | \r | |
adb59b63 | 4 | Copyright (c) 2005 - 2019, Intel Corporation. All rights reserved.<BR>\r |
231ad7d8 | 5 | (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r |
ba0014b9 | 6 | (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r |
56ba3746 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
5d73d92f | 8 | \r |
9 | **/\r | |
10 | \r | |
11 | #include "UefiShellDebug1CommandsLib.h"\r | |
12 | #include <Protocol/PciRootBridgeIo.h>\r | |
13 | #include <Library/ShellLib.h>\r | |
14 | #include <IndustryStandard/Pci.h>\r | |
15 | #include <IndustryStandard/Acpi.h>\r | |
16 | #include "Pci.h"\r | |
17 | \r | |
5d73d92f | 18 | //\r |
19 | // Printable strings for Pci class code\r | |
20 | //\r | |
21 | typedef struct {\r | |
22 | CHAR16 *BaseClass; // Pointer to the PCI base class string\r | |
23 | CHAR16 *SubClass; // Pointer to the PCI sub class string\r | |
24 | CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r | |
25 | } PCI_CLASS_STRINGS;\r | |
26 | \r | |
27 | //\r | |
28 | // a structure holding a single entry, which also points to its lower level\r | |
29 | // class\r | |
30 | //\r | |
31 | typedef struct PCI_CLASS_ENTRY_TAG {\r | |
32 | UINT8 Code; // Class, subclass or I/F code\r | |
33 | CHAR16 *DescText; // Description string\r | |
34 | struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r | |
35 | } PCI_CLASS_ENTRY;\r | |
36 | \r | |
37 | //\r | |
38 | // Declarations of entries which contain printable strings for class codes\r | |
39 | // in PCI configuration space\r | |
40 | //\r | |
41 | PCI_CLASS_ENTRY PCIBlankEntry[];\r | |
42 | PCI_CLASS_ENTRY PCISubClass_00[];\r | |
43 | PCI_CLASS_ENTRY PCISubClass_01[];\r | |
44 | PCI_CLASS_ENTRY PCISubClass_02[];\r | |
45 | PCI_CLASS_ENTRY PCISubClass_03[];\r | |
46 | PCI_CLASS_ENTRY PCISubClass_04[];\r | |
47 | PCI_CLASS_ENTRY PCISubClass_05[];\r | |
48 | PCI_CLASS_ENTRY PCISubClass_06[];\r | |
49 | PCI_CLASS_ENTRY PCISubClass_07[];\r | |
50 | PCI_CLASS_ENTRY PCISubClass_08[];\r | |
51 | PCI_CLASS_ENTRY PCISubClass_09[];\r | |
52 | PCI_CLASS_ENTRY PCISubClass_0a[];\r | |
53 | PCI_CLASS_ENTRY PCISubClass_0b[];\r | |
54 | PCI_CLASS_ENTRY PCISubClass_0c[];\r | |
55 | PCI_CLASS_ENTRY PCISubClass_0d[];\r | |
56 | PCI_CLASS_ENTRY PCISubClass_0e[];\r | |
57 | PCI_CLASS_ENTRY PCISubClass_0f[];\r | |
58 | PCI_CLASS_ENTRY PCISubClass_10[];\r | |
59 | PCI_CLASS_ENTRY PCISubClass_11[];\r | |
f056e4c1 JC |
60 | PCI_CLASS_ENTRY PCISubClass_12[];\r |
61 | PCI_CLASS_ENTRY PCISubClass_13[];\r | |
62 | PCI_CLASS_ENTRY PCIPIFClass_0100[];\r | |
5d73d92f | 63 | PCI_CLASS_ENTRY PCIPIFClass_0101[];\r |
f056e4c1 JC |
64 | PCI_CLASS_ENTRY PCIPIFClass_0105[];\r |
65 | PCI_CLASS_ENTRY PCIPIFClass_0106[];\r | |
66 | PCI_CLASS_ENTRY PCIPIFClass_0107[];\r | |
67 | PCI_CLASS_ENTRY PCIPIFClass_0108[];\r | |
68 | PCI_CLASS_ENTRY PCIPIFClass_0109[];\r | |
5d73d92f | 69 | PCI_CLASS_ENTRY PCIPIFClass_0300[];\r |
70 | PCI_CLASS_ENTRY PCIPIFClass_0604[];\r | |
f056e4c1 JC |
71 | PCI_CLASS_ENTRY PCIPIFClass_0609[];\r |
72 | PCI_CLASS_ENTRY PCIPIFClass_060b[];\r | |
5d73d92f | 73 | PCI_CLASS_ENTRY PCIPIFClass_0700[];\r |
74 | PCI_CLASS_ENTRY PCIPIFClass_0701[];\r | |
75 | PCI_CLASS_ENTRY PCIPIFClass_0703[];\r | |
76 | PCI_CLASS_ENTRY PCIPIFClass_0800[];\r | |
77 | PCI_CLASS_ENTRY PCIPIFClass_0801[];\r | |
78 | PCI_CLASS_ENTRY PCIPIFClass_0802[];\r | |
79 | PCI_CLASS_ENTRY PCIPIFClass_0803[];\r | |
80 | PCI_CLASS_ENTRY PCIPIFClass_0904[];\r | |
81 | PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r | |
82 | PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r | |
f056e4c1 JC |
83 | PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r |
84 | PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r | |
5d73d92f | 85 | PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r |
86 | \r | |
87 | //\r | |
88 | // Base class strings entries\r | |
89 | //\r | |
90 | PCI_CLASS_ENTRY gClassStringList[] = {\r | |
91 | {\r | |
92 | 0x00,\r | |
93 | L"Pre 2.0 device",\r | |
94 | PCISubClass_00\r | |
95 | },\r | |
96 | {\r | |
97 | 0x01,\r | |
98 | L"Mass Storage Controller",\r | |
99 | PCISubClass_01\r | |
100 | },\r | |
101 | {\r | |
102 | 0x02,\r | |
103 | L"Network Controller",\r | |
104 | PCISubClass_02\r | |
105 | },\r | |
106 | {\r | |
107 | 0x03,\r | |
108 | L"Display Controller",\r | |
109 | PCISubClass_03\r | |
110 | },\r | |
111 | {\r | |
112 | 0x04,\r | |
113 | L"Multimedia Device",\r | |
114 | PCISubClass_04\r | |
115 | },\r | |
116 | {\r | |
117 | 0x05,\r | |
118 | L"Memory Controller",\r | |
119 | PCISubClass_05\r | |
120 | },\r | |
121 | {\r | |
122 | 0x06,\r | |
123 | L"Bridge Device",\r | |
124 | PCISubClass_06\r | |
125 | },\r | |
126 | {\r | |
127 | 0x07,\r | |
128 | L"Simple Communications Controllers",\r | |
129 | PCISubClass_07\r | |
130 | },\r | |
131 | {\r | |
132 | 0x08,\r | |
133 | L"Base System Peripherals",\r | |
134 | PCISubClass_08\r | |
135 | },\r | |
136 | {\r | |
137 | 0x09,\r | |
138 | L"Input Devices",\r | |
139 | PCISubClass_09\r | |
140 | },\r | |
141 | {\r | |
142 | 0x0a,\r | |
143 | L"Docking Stations",\r | |
144 | PCISubClass_0a\r | |
145 | },\r | |
146 | {\r | |
147 | 0x0b,\r | |
148 | L"Processors",\r | |
149 | PCISubClass_0b\r | |
150 | },\r | |
151 | {\r | |
152 | 0x0c,\r | |
153 | L"Serial Bus Controllers",\r | |
154 | PCISubClass_0c\r | |
155 | },\r | |
156 | {\r | |
157 | 0x0d,\r | |
158 | L"Wireless Controllers",\r | |
159 | PCISubClass_0d\r | |
160 | },\r | |
161 | {\r | |
162 | 0x0e,\r | |
163 | L"Intelligent IO Controllers",\r | |
164 | PCISubClass_0e\r | |
165 | },\r | |
166 | {\r | |
167 | 0x0f,\r | |
168 | L"Satellite Communications Controllers",\r | |
169 | PCISubClass_0f\r | |
170 | },\r | |
171 | {\r | |
172 | 0x10,\r | |
173 | L"Encryption/Decryption Controllers",\r | |
174 | PCISubClass_10\r | |
175 | },\r | |
176 | {\r | |
177 | 0x11,\r | |
178 | L"Data Acquisition & Signal Processing Controllers",\r | |
179 | PCISubClass_11\r | |
180 | },\r | |
f056e4c1 JC |
181 | {\r |
182 | 0x12,\r | |
183 | L"Processing Accelerators",\r | |
184 | PCISubClass_12\r | |
185 | },\r | |
186 | {\r | |
187 | 0x13,\r | |
188 | L"Non-Essential Instrumentation",\r | |
189 | PCISubClass_13\r | |
190 | },\r | |
5d73d92f | 191 | {\r |
192 | 0xff,\r | |
193 | L"Device does not fit in any defined classes",\r | |
194 | PCIBlankEntry\r | |
195 | },\r | |
196 | {\r | |
197 | 0x00,\r | |
198 | NULL,\r | |
199 | /* null string ends the list */NULL\r | |
200 | }\r | |
201 | };\r | |
202 | \r | |
203 | //\r | |
204 | // Subclass strings entries\r | |
205 | //\r | |
206 | PCI_CLASS_ENTRY PCIBlankEntry[] = {\r | |
207 | {\r | |
208 | 0x00,\r | |
209 | L"",\r | |
210 | PCIBlankEntry\r | |
211 | },\r | |
212 | {\r | |
213 | 0x00,\r | |
214 | NULL,\r | |
215 | /* null string ends the list */NULL\r | |
216 | }\r | |
217 | };\r | |
218 | \r | |
219 | PCI_CLASS_ENTRY PCISubClass_00[] = {\r | |
220 | {\r | |
221 | 0x00,\r | |
222 | L"All devices other than VGA",\r | |
223 | PCIBlankEntry\r | |
224 | },\r | |
225 | {\r | |
226 | 0x01,\r | |
227 | L"VGA-compatible devices",\r | |
228 | PCIBlankEntry\r | |
229 | },\r | |
230 | {\r | |
231 | 0x00,\r | |
232 | NULL,\r | |
233 | /* null string ends the list */NULL\r | |
234 | }\r | |
235 | };\r | |
236 | \r | |
237 | PCI_CLASS_ENTRY PCISubClass_01[] = {\r | |
238 | {\r | |
239 | 0x00,\r | |
f056e4c1 JC |
240 | L"SCSI",\r |
241 | PCIPIFClass_0100\r | |
5d73d92f | 242 | },\r |
243 | {\r | |
244 | 0x01,\r | |
245 | L"IDE controller",\r | |
246 | PCIPIFClass_0101\r | |
247 | },\r | |
248 | {\r | |
249 | 0x02,\r | |
250 | L"Floppy disk controller",\r | |
251 | PCIBlankEntry\r | |
252 | },\r | |
253 | {\r | |
254 | 0x03,\r | |
255 | L"IPI controller",\r | |
256 | PCIBlankEntry\r | |
257 | },\r | |
258 | {\r | |
259 | 0x04,\r | |
260 | L"RAID controller",\r | |
261 | PCIBlankEntry\r | |
262 | },\r | |
f056e4c1 JC |
263 | {\r |
264 | 0x05,\r | |
265 | L"ATA controller with ADMA interface",\r | |
266 | PCIPIFClass_0105\r | |
267 | },\r | |
268 | {\r | |
269 | 0x06,\r | |
270 | L"Serial ATA controller",\r | |
271 | PCIPIFClass_0106\r | |
272 | },\r | |
273 | {\r | |
274 | 0x07,\r | |
275 | L"Serial Attached SCSI (SAS) controller ",\r | |
276 | PCIPIFClass_0107\r | |
277 | },\r | |
278 | {\r | |
279 | 0x08,\r | |
280 | L"Non-volatile memory subsystem",\r | |
281 | PCIPIFClass_0108\r | |
282 | },\r | |
283 | {\r | |
284 | 0x09,\r | |
285 | L"Universal Flash Storage (UFS) controller ",\r | |
286 | PCIPIFClass_0109\r | |
287 | },\r | |
5d73d92f | 288 | {\r |
289 | 0x80,\r | |
290 | L"Other mass storage controller",\r | |
291 | PCIBlankEntry\r | |
292 | },\r | |
293 | {\r | |
294 | 0x00,\r | |
295 | NULL,\r | |
296 | /* null string ends the list */NULL\r | |
297 | }\r | |
298 | };\r | |
299 | \r | |
300 | PCI_CLASS_ENTRY PCISubClass_02[] = {\r | |
301 | {\r | |
302 | 0x00,\r | |
303 | L"Ethernet controller",\r | |
304 | PCIBlankEntry\r | |
305 | },\r | |
306 | {\r | |
307 | 0x01,\r | |
308 | L"Token ring controller",\r | |
309 | PCIBlankEntry\r | |
310 | },\r | |
311 | {\r | |
312 | 0x02,\r | |
313 | L"FDDI controller",\r | |
314 | PCIBlankEntry\r | |
315 | },\r | |
316 | {\r | |
317 | 0x03,\r | |
318 | L"ATM controller",\r | |
319 | PCIBlankEntry\r | |
320 | },\r | |
321 | {\r | |
322 | 0x04,\r | |
323 | L"ISDN controller",\r | |
324 | PCIBlankEntry\r | |
325 | },\r | |
f056e4c1 JC |
326 | {\r |
327 | 0x05,\r | |
328 | L"WorldFip controller",\r | |
329 | PCIBlankEntry\r | |
330 | },\r | |
331 | {\r | |
332 | 0x06,\r | |
333 | L"PICMG 2.14 Multi Computing",\r | |
334 | PCIBlankEntry\r | |
335 | },\r | |
336 | {\r | |
337 | 0x07,\r | |
338 | L"InfiniBand controller",\r | |
339 | PCIBlankEntry\r | |
340 | },\r | |
5d73d92f | 341 | {\r |
342 | 0x80,\r | |
343 | L"Other network controller",\r | |
344 | PCIBlankEntry\r | |
345 | },\r | |
346 | {\r | |
347 | 0x00,\r | |
348 | NULL,\r | |
349 | /* null string ends the list */NULL\r | |
350 | }\r | |
351 | };\r | |
352 | \r | |
353 | PCI_CLASS_ENTRY PCISubClass_03[] = {\r | |
354 | {\r | |
355 | 0x00,\r | |
356 | L"VGA/8514 controller",\r | |
357 | PCIPIFClass_0300\r | |
358 | },\r | |
359 | {\r | |
360 | 0x01,\r | |
361 | L"XGA controller",\r | |
362 | PCIBlankEntry\r | |
363 | },\r | |
364 | {\r | |
365 | 0x02,\r | |
366 | L"3D controller",\r | |
367 | PCIBlankEntry\r | |
368 | },\r | |
369 | {\r | |
370 | 0x80,\r | |
371 | L"Other display controller",\r | |
372 | PCIBlankEntry\r | |
373 | },\r | |
374 | {\r | |
375 | 0x00,\r | |
376 | NULL,\r | |
377 | /* null string ends the list */PCIBlankEntry\r | |
378 | }\r | |
379 | };\r | |
380 | \r | |
381 | PCI_CLASS_ENTRY PCISubClass_04[] = {\r | |
382 | {\r | |
383 | 0x00,\r | |
384 | L"Video device",\r | |
385 | PCIBlankEntry\r | |
386 | },\r | |
387 | {\r | |
388 | 0x01,\r | |
389 | L"Audio device",\r | |
390 | PCIBlankEntry\r | |
391 | },\r | |
392 | {\r | |
393 | 0x02,\r | |
394 | L"Computer Telephony device",\r | |
395 | PCIBlankEntry\r | |
396 | },\r | |
f056e4c1 JC |
397 | {\r |
398 | 0x03,\r | |
399 | L"Mixed mode device",\r | |
400 | PCIBlankEntry\r | |
401 | },\r | |
5d73d92f | 402 | {\r |
403 | 0x80,\r | |
404 | L"Other multimedia device",\r | |
405 | PCIBlankEntry\r | |
406 | },\r | |
407 | {\r | |
408 | 0x00,\r | |
409 | NULL,\r | |
410 | /* null string ends the list */NULL\r | |
411 | }\r | |
412 | };\r | |
413 | \r | |
414 | PCI_CLASS_ENTRY PCISubClass_05[] = {\r | |
415 | {\r | |
416 | 0x00,\r | |
417 | L"RAM memory controller",\r | |
418 | PCIBlankEntry\r | |
419 | },\r | |
420 | {\r | |
421 | 0x01,\r | |
422 | L"Flash memory controller",\r | |
423 | PCIBlankEntry\r | |
424 | },\r | |
425 | {\r | |
426 | 0x80,\r | |
427 | L"Other memory controller",\r | |
428 | PCIBlankEntry\r | |
429 | },\r | |
430 | {\r | |
431 | 0x00,\r | |
432 | NULL,\r | |
433 | /* null string ends the list */NULL\r | |
434 | }\r | |
435 | };\r | |
436 | \r | |
437 | PCI_CLASS_ENTRY PCISubClass_06[] = {\r | |
438 | {\r | |
439 | 0x00,\r | |
440 | L"Host/PCI bridge",\r | |
441 | PCIBlankEntry\r | |
442 | },\r | |
443 | {\r | |
444 | 0x01,\r | |
445 | L"PCI/ISA bridge",\r | |
446 | PCIBlankEntry\r | |
447 | },\r | |
448 | {\r | |
449 | 0x02,\r | |
450 | L"PCI/EISA bridge",\r | |
451 | PCIBlankEntry\r | |
452 | },\r | |
453 | {\r | |
454 | 0x03,\r | |
455 | L"PCI/Micro Channel bridge",\r | |
456 | PCIBlankEntry\r | |
457 | },\r | |
458 | {\r | |
459 | 0x04,\r | |
460 | L"PCI/PCI bridge",\r | |
461 | PCIPIFClass_0604\r | |
462 | },\r | |
463 | {\r | |
464 | 0x05,\r | |
465 | L"PCI/PCMCIA bridge",\r | |
466 | PCIBlankEntry\r | |
467 | },\r | |
468 | {\r | |
469 | 0x06,\r | |
470 | L"NuBus bridge",\r | |
471 | PCIBlankEntry\r | |
472 | },\r | |
473 | {\r | |
474 | 0x07,\r | |
475 | L"CardBus bridge",\r | |
476 | PCIBlankEntry\r | |
477 | },\r | |
478 | {\r | |
479 | 0x08,\r | |
480 | L"RACEway bridge",\r | |
481 | PCIBlankEntry\r | |
482 | },\r | |
f056e4c1 JC |
483 | {\r |
484 | 0x09,\r | |
485 | L"Semi-transparent PCI-to-PCI bridge",\r | |
486 | PCIPIFClass_0609\r | |
487 | },\r | |
488 | {\r | |
489 | 0x0A,\r | |
490 | L"InfiniBand-to-PCI host bridge",\r | |
491 | PCIBlankEntry\r | |
492 | },\r | |
493 | {\r | |
494 | 0x0B,\r | |
495 | L"Advanced Switching to PCI host bridge",\r | |
496 | PCIPIFClass_060b\r | |
497 | },\r | |
5d73d92f | 498 | {\r |
499 | 0x80,\r | |
500 | L"Other bridge type",\r | |
501 | PCIBlankEntry\r | |
502 | },\r | |
503 | {\r | |
504 | 0x00,\r | |
505 | NULL,\r | |
506 | /* null string ends the list */NULL\r | |
507 | }\r | |
508 | };\r | |
509 | \r | |
510 | PCI_CLASS_ENTRY PCISubClass_07[] = {\r | |
511 | {\r | |
512 | 0x00,\r | |
513 | L"Serial controller",\r | |
514 | PCIPIFClass_0700\r | |
515 | },\r | |
516 | {\r | |
517 | 0x01,\r | |
518 | L"Parallel port",\r | |
519 | PCIPIFClass_0701\r | |
520 | },\r | |
521 | {\r | |
522 | 0x02,\r | |
523 | L"Multiport serial controller",\r | |
524 | PCIBlankEntry\r | |
525 | },\r | |
526 | {\r | |
527 | 0x03,\r | |
528 | L"Modem",\r | |
529 | PCIPIFClass_0703\r | |
530 | },\r | |
f056e4c1 JC |
531 | {\r |
532 | 0x04,\r | |
533 | L"GPIB (IEEE 488.1/2) controller",\r | |
534 | PCIBlankEntry\r | |
535 | },\r | |
536 | {\r | |
537 | 0x05,\r | |
538 | L"Smart Card",\r | |
539 | PCIBlankEntry\r | |
540 | },\r | |
5d73d92f | 541 | {\r |
542 | 0x80,\r | |
543 | L"Other communication device",\r | |
544 | PCIBlankEntry\r | |
545 | },\r | |
546 | {\r | |
547 | 0x00,\r | |
548 | NULL,\r | |
549 | /* null string ends the list */NULL\r | |
550 | }\r | |
551 | };\r | |
552 | \r | |
553 | PCI_CLASS_ENTRY PCISubClass_08[] = {\r | |
554 | {\r | |
555 | 0x00,\r | |
556 | L"PIC",\r | |
557 | PCIPIFClass_0800\r | |
558 | },\r | |
559 | {\r | |
560 | 0x01,\r | |
561 | L"DMA controller",\r | |
562 | PCIPIFClass_0801\r | |
563 | },\r | |
564 | {\r | |
565 | 0x02,\r | |
566 | L"System timer",\r | |
567 | PCIPIFClass_0802\r | |
568 | },\r | |
569 | {\r | |
570 | 0x03,\r | |
571 | L"RTC controller",\r | |
572 | PCIPIFClass_0803\r | |
573 | },\r | |
574 | {\r | |
575 | 0x04,\r | |
576 | L"Generic PCI Hot-Plug controller",\r | |
577 | PCIBlankEntry\r | |
578 | },\r | |
f056e4c1 JC |
579 | {\r |
580 | 0x05,\r | |
581 | L"SD Host controller",\r | |
582 | PCIBlankEntry\r | |
583 | },\r | |
584 | {\r | |
585 | 0x06,\r | |
586 | L"IOMMU",\r | |
587 | PCIBlankEntry\r | |
588 | },\r | |
589 | {\r | |
590 | 0x07,\r | |
591 | L"Root Complex Event Collector",\r | |
592 | PCIBlankEntry\r | |
593 | },\r | |
5d73d92f | 594 | {\r |
595 | 0x80,\r | |
596 | L"Other system peripheral",\r | |
597 | PCIBlankEntry\r | |
598 | },\r | |
599 | {\r | |
600 | 0x00,\r | |
601 | NULL,\r | |
602 | /* null string ends the list */NULL\r | |
603 | }\r | |
604 | };\r | |
605 | \r | |
606 | PCI_CLASS_ENTRY PCISubClass_09[] = {\r | |
607 | {\r | |
608 | 0x00,\r | |
609 | L"Keyboard controller",\r | |
610 | PCIBlankEntry\r | |
611 | },\r | |
612 | {\r | |
613 | 0x01,\r | |
614 | L"Digitizer (pen)",\r | |
615 | PCIBlankEntry\r | |
616 | },\r | |
617 | {\r | |
618 | 0x02,\r | |
619 | L"Mouse controller",\r | |
620 | PCIBlankEntry\r | |
621 | },\r | |
622 | {\r | |
623 | 0x03,\r | |
624 | L"Scanner controller",\r | |
625 | PCIBlankEntry\r | |
626 | },\r | |
627 | {\r | |
628 | 0x04,\r | |
629 | L"Gameport controller",\r | |
630 | PCIPIFClass_0904\r | |
631 | },\r | |
632 | {\r | |
633 | 0x80,\r | |
634 | L"Other input controller",\r | |
635 | PCIBlankEntry\r | |
636 | },\r | |
637 | {\r | |
638 | 0x00,\r | |
639 | NULL,\r | |
640 | /* null string ends the list */NULL\r | |
641 | }\r | |
642 | };\r | |
643 | \r | |
644 | PCI_CLASS_ENTRY PCISubClass_0a[] = {\r | |
645 | {\r | |
646 | 0x00,\r | |
647 | L"Generic docking station",\r | |
648 | PCIBlankEntry\r | |
649 | },\r | |
650 | {\r | |
651 | 0x80,\r | |
652 | L"Other type of docking station",\r | |
653 | PCIBlankEntry\r | |
654 | },\r | |
655 | {\r | |
656 | 0x00,\r | |
657 | NULL,\r | |
658 | /* null string ends the list */NULL\r | |
659 | }\r | |
660 | };\r | |
661 | \r | |
662 | PCI_CLASS_ENTRY PCISubClass_0b[] = {\r | |
663 | {\r | |
664 | 0x00,\r | |
665 | L"386",\r | |
666 | PCIBlankEntry\r | |
667 | },\r | |
668 | {\r | |
669 | 0x01,\r | |
670 | L"486",\r | |
671 | PCIBlankEntry\r | |
672 | },\r | |
673 | {\r | |
674 | 0x02,\r | |
675 | L"Pentium",\r | |
676 | PCIBlankEntry\r | |
677 | },\r | |
678 | {\r | |
679 | 0x10,\r | |
680 | L"Alpha",\r | |
681 | PCIBlankEntry\r | |
682 | },\r | |
683 | {\r | |
684 | 0x20,\r | |
685 | L"PowerPC",\r | |
686 | PCIBlankEntry\r | |
687 | },\r | |
688 | {\r | |
689 | 0x30,\r | |
690 | L"MIPS",\r | |
691 | PCIBlankEntry\r | |
692 | },\r | |
693 | {\r | |
694 | 0x40,\r | |
695 | L"Co-processor",\r | |
696 | PCIBlankEntry\r | |
697 | },\r | |
698 | {\r | |
699 | 0x80,\r | |
700 | L"Other processor",\r | |
701 | PCIBlankEntry\r | |
702 | },\r | |
703 | {\r | |
704 | 0x00,\r | |
705 | NULL,\r | |
706 | /* null string ends the list */NULL\r | |
707 | }\r | |
708 | };\r | |
709 | \r | |
710 | PCI_CLASS_ENTRY PCISubClass_0c[] = {\r | |
711 | {\r | |
712 | 0x00,\r | |
f056e4c1 JC |
713 | L"IEEE 1394",\r |
714 | PCIPIFClass_0c00\r | |
5d73d92f | 715 | },\r |
716 | {\r | |
717 | 0x01,\r | |
718 | L"ACCESS.bus",\r | |
719 | PCIBlankEntry\r | |
720 | },\r | |
721 | {\r | |
722 | 0x02,\r | |
723 | L"SSA",\r | |
724 | PCIBlankEntry\r | |
725 | },\r | |
726 | {\r | |
727 | 0x03,\r | |
728 | L"USB",\r | |
f056e4c1 | 729 | PCIPIFClass_0c03\r |
5d73d92f | 730 | },\r |
731 | {\r | |
732 | 0x04,\r | |
733 | L"Fibre Channel",\r | |
734 | PCIBlankEntry\r | |
735 | },\r | |
736 | {\r | |
737 | 0x05,\r | |
738 | L"System Management Bus",\r | |
739 | PCIBlankEntry\r | |
740 | },\r | |
f056e4c1 JC |
741 | {\r |
742 | 0x06,\r | |
743 | L"InfiniBand",\r | |
744 | PCIBlankEntry\r | |
745 | },\r | |
746 | {\r | |
747 | 0x07,\r | |
748 | L"IPMI",\r | |
749 | PCIPIFClass_0c07\r | |
750 | },\r | |
751 | {\r | |
752 | 0x08,\r | |
753 | L"SERCOS Interface Standard (IEC 61491)",\r | |
754 | PCIBlankEntry\r | |
755 | },\r | |
756 | {\r | |
757 | 0x09,\r | |
758 | L"CANbus",\r | |
759 | PCIBlankEntry\r | |
760 | },\r | |
5d73d92f | 761 | {\r |
762 | 0x80,\r | |
763 | L"Other bus type",\r | |
764 | PCIBlankEntry\r | |
765 | },\r | |
766 | {\r | |
767 | 0x00,\r | |
768 | NULL,\r | |
769 | /* null string ends the list */NULL\r | |
770 | }\r | |
771 | };\r | |
772 | \r | |
773 | PCI_CLASS_ENTRY PCISubClass_0d[] = {\r | |
774 | {\r | |
775 | 0x00,\r | |
776 | L"iRDA compatible controller",\r | |
777 | PCIBlankEntry\r | |
778 | },\r | |
779 | {\r | |
780 | 0x01,\r | |
f056e4c1 JC |
781 | L"",\r |
782 | PCIPIFClass_0d01\r | |
5d73d92f | 783 | },\r |
784 | {\r | |
785 | 0x10,\r | |
786 | L"RF controller",\r | |
787 | PCIBlankEntry\r | |
788 | },\r | |
f056e4c1 JC |
789 | {\r |
790 | 0x11,\r | |
791 | L"Bluetooth",\r | |
792 | PCIBlankEntry\r | |
793 | },\r | |
794 | {\r | |
795 | 0x12,\r | |
796 | L"Broadband",\r | |
797 | PCIBlankEntry\r | |
798 | },\r | |
799 | {\r | |
800 | 0x20,\r | |
59577231 | 801 | L"Ethernet (802.11a - 5 GHz)",\r |
f056e4c1 JC |
802 | PCIBlankEntry\r |
803 | },\r | |
804 | {\r | |
805 | 0x21,\r | |
59577231 | 806 | L"Ethernet (802.11b - 2.4 GHz)",\r |
f056e4c1 JC |
807 | PCIBlankEntry\r |
808 | },\r | |
5d73d92f | 809 | {\r |
810 | 0x80,\r | |
811 | L"Other type of wireless controller",\r | |
812 | PCIBlankEntry\r | |
813 | },\r | |
814 | {\r | |
815 | 0x00,\r | |
816 | NULL,\r | |
817 | /* null string ends the list */NULL\r | |
818 | }\r | |
819 | };\r | |
820 | \r | |
821 | PCI_CLASS_ENTRY PCISubClass_0e[] = {\r | |
822 | {\r | |
823 | 0x00,\r | |
824 | L"I2O Architecture",\r | |
825 | PCIPIFClass_0e00\r | |
826 | },\r | |
827 | {\r | |
828 | 0x00,\r | |
829 | NULL,\r | |
830 | /* null string ends the list */NULL\r | |
831 | }\r | |
832 | };\r | |
833 | \r | |
834 | PCI_CLASS_ENTRY PCISubClass_0f[] = {\r | |
835 | {\r | |
f056e4c1 | 836 | 0x01,\r |
5d73d92f | 837 | L"TV",\r |
838 | PCIBlankEntry\r | |
839 | },\r | |
840 | {\r | |
f056e4c1 | 841 | 0x02,\r |
5d73d92f | 842 | L"Audio",\r |
843 | PCIBlankEntry\r | |
844 | },\r | |
845 | {\r | |
f056e4c1 | 846 | 0x03,\r |
5d73d92f | 847 | L"Voice",\r |
848 | PCIBlankEntry\r | |
849 | },\r | |
850 | {\r | |
f056e4c1 | 851 | 0x04,\r |
5d73d92f | 852 | L"Data",\r |
853 | PCIBlankEntry\r | |
854 | },\r | |
f056e4c1 JC |
855 | {\r |
856 | 0x80,\r | |
857 | L"Other satellite communication controller",\r | |
858 | PCIBlankEntry\r | |
859 | },\r | |
5d73d92f | 860 | {\r |
861 | 0x00,\r | |
862 | NULL,\r | |
863 | /* null string ends the list */NULL\r | |
864 | }\r | |
865 | };\r | |
866 | \r | |
867 | PCI_CLASS_ENTRY PCISubClass_10[] = {\r | |
868 | {\r | |
869 | 0x00,\r | |
870 | L"Network & computing Encrypt/Decrypt",\r | |
871 | PCIBlankEntry\r | |
872 | },\r | |
873 | {\r | |
874 | 0x01,\r | |
875 | L"Entertainment Encrypt/Decrypt",\r | |
876 | PCIBlankEntry\r | |
877 | },\r | |
878 | {\r | |
879 | 0x80,\r | |
880 | L"Other Encrypt/Decrypt",\r | |
881 | PCIBlankEntry\r | |
882 | },\r | |
883 | {\r | |
884 | 0x00,\r | |
885 | NULL,\r | |
886 | /* null string ends the list */NULL\r | |
887 | }\r | |
888 | };\r | |
889 | \r | |
890 | PCI_CLASS_ENTRY PCISubClass_11[] = {\r | |
891 | {\r | |
892 | 0x00,\r | |
893 | L"DPIO modules",\r | |
894 | PCIBlankEntry\r | |
895 | },\r | |
f056e4c1 JC |
896 | {\r |
897 | 0x01,\r | |
898 | L"Performance Counters",\r | |
899 | PCIBlankEntry\r | |
900 | },\r | |
901 | {\r | |
902 | 0x10,\r | |
903 | L"Communications synchronization plus time and frequency test/measurement ",\r | |
904 | PCIBlankEntry\r | |
905 | },\r | |
906 | {\r | |
907 | 0x20,\r | |
908 | L"Management card",\r | |
909 | PCIBlankEntry\r | |
910 | },\r | |
5d73d92f | 911 | {\r |
912 | 0x80,\r | |
913 | L"Other DAQ & SP controllers",\r | |
914 | PCIBlankEntry\r | |
915 | },\r | |
916 | {\r | |
917 | 0x00,\r | |
918 | NULL,\r | |
919 | /* null string ends the list */NULL\r | |
920 | }\r | |
921 | };\r | |
922 | \r | |
f056e4c1 JC |
923 | PCI_CLASS_ENTRY PCISubClass_12[] = {\r |
924 | {\r | |
925 | 0x00,\r | |
926 | L"Processing Accelerator",\r | |
927 | PCIBlankEntry\r | |
928 | },\r | |
929 | {\r | |
930 | 0x00,\r | |
931 | NULL,\r | |
932 | /* null string ends the list */NULL\r | |
933 | }\r | |
934 | };\r | |
935 | \r | |
936 | PCI_CLASS_ENTRY PCISubClass_13[] = {\r | |
937 | {\r | |
938 | 0x00,\r | |
939 | L"Non-Essential Instrumentation Function",\r | |
940 | PCIBlankEntry\r | |
941 | },\r | |
942 | {\r | |
943 | 0x00,\r | |
944 | NULL,\r | |
945 | /* null string ends the list */NULL\r | |
946 | }\r | |
947 | };\r | |
948 | \r | |
5d73d92f | 949 | //\r |
950 | // Programming Interface entries\r | |
951 | //\r | |
f056e4c1 JC |
952 | PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r |
953 | {\r | |
954 | 0x00,\r | |
955 | L"SCSI controller",\r | |
956 | PCIBlankEntry\r | |
957 | },\r | |
958 | {\r | |
959 | 0x11,\r | |
960 | L"SCSI storage device SOP using PQI",\r | |
961 | PCIBlankEntry\r | |
962 | },\r | |
963 | {\r | |
964 | 0x12,\r | |
965 | L"SCSI controller SOP using PQI",\r | |
966 | PCIBlankEntry\r | |
967 | },\r | |
968 | {\r | |
969 | 0x13,\r | |
970 | L"SCSI storage device and controller SOP using PQI",\r | |
971 | PCIBlankEntry\r | |
972 | },\r | |
973 | {\r | |
974 | 0x21,\r | |
975 | L"SCSI storage device SOP using NVMe",\r | |
976 | PCIBlankEntry\r | |
977 | },\r | |
978 | {\r | |
979 | 0x00,\r | |
980 | NULL,\r | |
981 | /* null string ends the list */NULL\r | |
982 | }\r | |
983 | };\r | |
984 | \r | |
5d73d92f | 985 | PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r |
986 | {\r | |
987 | 0x00,\r | |
988 | L"",\r | |
989 | PCIBlankEntry\r | |
990 | },\r | |
991 | {\r | |
992 | 0x01,\r | |
993 | L"OM-primary",\r | |
994 | PCIBlankEntry\r | |
995 | },\r | |
996 | {\r | |
997 | 0x02,\r | |
998 | L"PI-primary",\r | |
999 | PCIBlankEntry\r | |
1000 | },\r | |
1001 | {\r | |
1002 | 0x03,\r | |
1003 | L"OM/PI-primary",\r | |
1004 | PCIBlankEntry\r | |
1005 | },\r | |
1006 | {\r | |
1007 | 0x04,\r | |
1008 | L"OM-secondary",\r | |
1009 | PCIBlankEntry\r | |
1010 | },\r | |
1011 | {\r | |
1012 | 0x05,\r | |
1013 | L"OM-primary, OM-secondary",\r | |
1014 | PCIBlankEntry\r | |
1015 | },\r | |
1016 | {\r | |
1017 | 0x06,\r | |
1018 | L"PI-primary, OM-secondary",\r | |
1019 | PCIBlankEntry\r | |
1020 | },\r | |
1021 | {\r | |
1022 | 0x07,\r | |
1023 | L"OM/PI-primary, OM-secondary",\r | |
1024 | PCIBlankEntry\r | |
1025 | },\r | |
1026 | {\r | |
1027 | 0x08,\r | |
1028 | L"OM-secondary",\r | |
1029 | PCIBlankEntry\r | |
1030 | },\r | |
1031 | {\r | |
1032 | 0x09,\r | |
1033 | L"OM-primary, PI-secondary",\r | |
1034 | PCIBlankEntry\r | |
1035 | },\r | |
1036 | {\r | |
1037 | 0x0a,\r | |
1038 | L"PI-primary, PI-secondary",\r | |
1039 | PCIBlankEntry\r | |
1040 | },\r | |
1041 | {\r | |
1042 | 0x0b,\r | |
1043 | L"OM/PI-primary, PI-secondary",\r | |
1044 | PCIBlankEntry\r | |
1045 | },\r | |
1046 | {\r | |
1047 | 0x0c,\r | |
1048 | L"OM-secondary",\r | |
1049 | PCIBlankEntry\r | |
1050 | },\r | |
1051 | {\r | |
1052 | 0x0d,\r | |
1053 | L"OM-primary, OM/PI-secondary",\r | |
1054 | PCIBlankEntry\r | |
1055 | },\r | |
1056 | {\r | |
1057 | 0x0e,\r | |
1058 | L"PI-primary, OM/PI-secondary",\r | |
1059 | PCIBlankEntry\r | |
1060 | },\r | |
1061 | {\r | |
1062 | 0x0f,\r | |
1063 | L"OM/PI-primary, OM/PI-secondary",\r | |
1064 | PCIBlankEntry\r | |
1065 | },\r | |
1066 | {\r | |
1067 | 0x80,\r | |
1068 | L"Master",\r | |
1069 | PCIBlankEntry\r | |
1070 | },\r | |
1071 | {\r | |
1072 | 0x81,\r | |
1073 | L"Master, OM-primary",\r | |
1074 | PCIBlankEntry\r | |
1075 | },\r | |
1076 | {\r | |
1077 | 0x82,\r | |
1078 | L"Master, PI-primary",\r | |
1079 | PCIBlankEntry\r | |
1080 | },\r | |
1081 | {\r | |
1082 | 0x83,\r | |
1083 | L"Master, OM/PI-primary",\r | |
1084 | PCIBlankEntry\r | |
1085 | },\r | |
1086 | {\r | |
1087 | 0x84,\r | |
1088 | L"Master, OM-secondary",\r | |
1089 | PCIBlankEntry\r | |
1090 | },\r | |
1091 | {\r | |
1092 | 0x85,\r | |
1093 | L"Master, OM-primary, OM-secondary",\r | |
1094 | PCIBlankEntry\r | |
1095 | },\r | |
1096 | {\r | |
1097 | 0x86,\r | |
1098 | L"Master, PI-primary, OM-secondary",\r | |
1099 | PCIBlankEntry\r | |
1100 | },\r | |
1101 | {\r | |
1102 | 0x87,\r | |
1103 | L"Master, OM/PI-primary, OM-secondary",\r | |
1104 | PCIBlankEntry\r | |
1105 | },\r | |
1106 | {\r | |
1107 | 0x88,\r | |
1108 | L"Master, OM-secondary",\r | |
1109 | PCIBlankEntry\r | |
1110 | },\r | |
1111 | {\r | |
1112 | 0x89,\r | |
1113 | L"Master, OM-primary, PI-secondary",\r | |
1114 | PCIBlankEntry\r | |
1115 | },\r | |
1116 | {\r | |
1117 | 0x8a,\r | |
1118 | L"Master, PI-primary, PI-secondary",\r | |
1119 | PCIBlankEntry\r | |
1120 | },\r | |
1121 | {\r | |
1122 | 0x8b,\r | |
1123 | L"Master, OM/PI-primary, PI-secondary",\r | |
1124 | PCIBlankEntry\r | |
1125 | },\r | |
1126 | {\r | |
1127 | 0x8c,\r | |
1128 | L"Master, OM-secondary",\r | |
1129 | PCIBlankEntry\r | |
1130 | },\r | |
1131 | {\r | |
1132 | 0x8d,\r | |
1133 | L"Master, OM-primary, OM/PI-secondary",\r | |
1134 | PCIBlankEntry\r | |
1135 | },\r | |
1136 | {\r | |
1137 | 0x8e,\r | |
1138 | L"Master, PI-primary, OM/PI-secondary",\r | |
1139 | PCIBlankEntry\r | |
1140 | },\r | |
1141 | {\r | |
1142 | 0x8f,\r | |
1143 | L"Master, OM/PI-primary, OM/PI-secondary",\r | |
1144 | PCIBlankEntry\r | |
1145 | },\r | |
1146 | {\r | |
1147 | 0x00,\r | |
1148 | NULL,\r | |
1149 | /* null string ends the list */NULL\r | |
1150 | }\r | |
1151 | };\r | |
1152 | \r | |
f056e4c1 JC |
1153 | PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r |
1154 | {\r | |
1155 | 0x20,\r | |
1156 | L"Single stepping",\r | |
1157 | PCIBlankEntry\r | |
1158 | },\r | |
1159 | {\r | |
1160 | 0x30,\r | |
1161 | L"Continuous operation",\r | |
1162 | PCIBlankEntry\r | |
1163 | },\r | |
1164 | {\r | |
1165 | 0x00,\r | |
1166 | NULL,\r | |
1167 | /* null string ends the list */NULL\r | |
1168 | }\r | |
1169 | };\r | |
1170 | \r | |
1171 | PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r | |
1172 | {\r | |
1173 | 0x00,\r | |
1174 | L"",\r | |
1175 | PCIBlankEntry\r | |
1176 | },\r | |
1177 | {\r | |
1178 | 0x01,\r | |
1179 | L"AHCI",\r | |
1180 | PCIBlankEntry\r | |
1181 | },\r | |
1182 | {\r | |
1183 | 0x02,\r | |
1184 | L"Serial Storage Bus",\r | |
1185 | PCIBlankEntry\r | |
1186 | },\r | |
1187 | {\r | |
1188 | 0x00,\r | |
1189 | NULL,\r | |
1190 | /* null string ends the list */NULL\r | |
1191 | }\r | |
1192 | };\r | |
1193 | \r | |
1194 | PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r | |
1195 | {\r | |
1196 | 0x00,\r | |
1197 | L"",\r | |
1198 | PCIBlankEntry\r | |
1199 | },\r | |
1200 | {\r | |
1201 | 0x01,\r | |
1202 | L"Obsolete",\r | |
1203 | PCIBlankEntry\r | |
1204 | },\r | |
1205 | {\r | |
1206 | 0x00,\r | |
1207 | NULL,\r | |
1208 | /* null string ends the list */NULL\r | |
1209 | }\r | |
1210 | };\r | |
1211 | \r | |
1212 | PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r | |
1213 | {\r | |
1214 | 0x00,\r | |
1215 | L"",\r | |
1216 | PCIBlankEntry\r | |
1217 | },\r | |
1218 | {\r | |
1219 | 0x01,\r | |
1220 | L"NVMHCI",\r | |
1221 | PCIBlankEntry\r | |
1222 | },\r | |
1223 | {\r | |
1224 | 0x02,\r | |
1225 | L"NVM Express",\r | |
1226 | PCIBlankEntry\r | |
1227 | },\r | |
1228 | {\r | |
1229 | 0x00,\r | |
1230 | NULL,\r | |
1231 | /* null string ends the list */NULL\r | |
1232 | }\r | |
1233 | };\r | |
1234 | \r | |
1235 | PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r | |
1236 | {\r | |
1237 | 0x00,\r | |
1238 | L"",\r | |
1239 | PCIBlankEntry\r | |
1240 | },\r | |
1241 | {\r | |
1242 | 0x01,\r | |
1243 | L"UFSHCI",\r | |
1244 | PCIBlankEntry\r | |
1245 | },\r | |
1246 | {\r | |
1247 | 0x00,\r | |
1248 | NULL,\r | |
1249 | /* null string ends the list */NULL\r | |
1250 | }\r | |
1251 | };\r | |
1252 | \r | |
5d73d92f | 1253 | PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r |
1254 | {\r | |
1255 | 0x00,\r | |
1256 | L"VGA compatible",\r | |
1257 | PCIBlankEntry\r | |
1258 | },\r | |
1259 | {\r | |
1260 | 0x01,\r | |
1261 | L"8514 compatible",\r | |
1262 | PCIBlankEntry\r | |
1263 | },\r | |
1264 | {\r | |
1265 | 0x00,\r | |
1266 | NULL,\r | |
1267 | /* null string ends the list */NULL\r | |
1268 | }\r | |
1269 | };\r | |
1270 | \r | |
1271 | PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r | |
1272 | {\r | |
1273 | 0x00,\r | |
1274 | L"",\r | |
1275 | PCIBlankEntry\r | |
1276 | },\r | |
1277 | {\r | |
1278 | 0x01,\r | |
1279 | L"Subtractive decode",\r | |
1280 | PCIBlankEntry\r | |
1281 | },\r | |
1282 | {\r | |
1283 | 0x00,\r | |
1284 | NULL,\r | |
1285 | /* null string ends the list */NULL\r | |
1286 | }\r | |
1287 | };\r | |
1288 | \r | |
f056e4c1 JC |
1289 | PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r |
1290 | {\r | |
1291 | 0x40,\r | |
1292 | L"Primary PCI bus side facing the system host processor",\r | |
1293 | PCIBlankEntry\r | |
1294 | },\r | |
1295 | {\r | |
1296 | 0x80,\r | |
1297 | L"Secondary PCI bus side facing the system host processor",\r | |
1298 | PCIBlankEntry\r | |
1299 | },\r | |
1300 | {\r | |
1301 | 0x00,\r | |
1302 | NULL,\r | |
1303 | /* null string ends the list */NULL\r | |
1304 | }\r | |
1305 | };\r | |
1306 | \r | |
1307 | PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r | |
1308 | {\r | |
1309 | 0x00,\r | |
1310 | L"Custom",\r | |
1311 | PCIBlankEntry\r | |
1312 | },\r | |
1313 | {\r | |
1314 | 0x01,\r | |
1315 | L"ASI-SIG Defined Portal",\r | |
1316 | PCIBlankEntry\r | |
1317 | },\r | |
1318 | {\r | |
1319 | 0x00,\r | |
1320 | NULL,\r | |
1321 | /* null string ends the list */NULL\r | |
1322 | }\r | |
1323 | };\r | |
1324 | \r | |
5d73d92f | 1325 | PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r |
1326 | {\r | |
1327 | 0x00,\r | |
1328 | L"Generic XT-compatible",\r | |
1329 | PCIBlankEntry\r | |
1330 | },\r | |
1331 | {\r | |
1332 | 0x01,\r | |
1333 | L"16450-compatible",\r | |
1334 | PCIBlankEntry\r | |
1335 | },\r | |
1336 | {\r | |
1337 | 0x02,\r | |
1338 | L"16550-compatible",\r | |
1339 | PCIBlankEntry\r | |
1340 | },\r | |
1341 | {\r | |
1342 | 0x03,\r | |
1343 | L"16650-compatible",\r | |
1344 | PCIBlankEntry\r | |
1345 | },\r | |
1346 | {\r | |
1347 | 0x04,\r | |
1348 | L"16750-compatible",\r | |
1349 | PCIBlankEntry\r | |
1350 | },\r | |
1351 | {\r | |
1352 | 0x05,\r | |
1353 | L"16850-compatible",\r | |
1354 | PCIBlankEntry\r | |
1355 | },\r | |
1356 | {\r | |
1357 | 0x06,\r | |
1358 | L"16950-compatible",\r | |
1359 | PCIBlankEntry\r | |
1360 | },\r | |
1361 | {\r | |
1362 | 0x00,\r | |
1363 | NULL,\r | |
1364 | /* null string ends the list */NULL\r | |
1365 | }\r | |
1366 | };\r | |
1367 | \r | |
1368 | PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r | |
1369 | {\r | |
1370 | 0x00,\r | |
1371 | L"",\r | |
1372 | PCIBlankEntry\r | |
1373 | },\r | |
1374 | {\r | |
1375 | 0x01,\r | |
1376 | L"Bi-directional",\r | |
1377 | PCIBlankEntry\r | |
1378 | },\r | |
1379 | {\r | |
1380 | 0x02,\r | |
1381 | L"ECP 1.X-compliant",\r | |
1382 | PCIBlankEntry\r | |
1383 | },\r | |
1384 | {\r | |
1385 | 0x03,\r | |
1386 | L"IEEE 1284",\r | |
1387 | PCIBlankEntry\r | |
1388 | },\r | |
1389 | {\r | |
1390 | 0xfe,\r | |
1391 | L"IEEE 1284 target (not a controller)",\r | |
1392 | PCIBlankEntry\r | |
1393 | },\r | |
1394 | {\r | |
1395 | 0x00,\r | |
1396 | NULL,\r | |
1397 | /* null string ends the list */NULL\r | |
1398 | }\r | |
1399 | };\r | |
1400 | \r | |
1401 | PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r | |
1402 | {\r | |
1403 | 0x00,\r | |
1404 | L"Generic",\r | |
1405 | PCIBlankEntry\r | |
1406 | },\r | |
1407 | {\r | |
1408 | 0x01,\r | |
1409 | L"Hayes-compatible 16450",\r | |
1410 | PCIBlankEntry\r | |
1411 | },\r | |
1412 | {\r | |
1413 | 0x02,\r | |
1414 | L"Hayes-compatible 16550",\r | |
1415 | PCIBlankEntry\r | |
1416 | },\r | |
1417 | {\r | |
1418 | 0x03,\r | |
1419 | L"Hayes-compatible 16650",\r | |
1420 | PCIBlankEntry\r | |
1421 | },\r | |
1422 | {\r | |
1423 | 0x04,\r | |
1424 | L"Hayes-compatible 16750",\r | |
1425 | PCIBlankEntry\r | |
1426 | },\r | |
1427 | {\r | |
1428 | 0x00,\r | |
1429 | NULL,\r | |
1430 | /* null string ends the list */NULL\r | |
1431 | }\r | |
1432 | };\r | |
1433 | \r | |
1434 | PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r | |
1435 | {\r | |
1436 | 0x00,\r | |
1437 | L"Generic 8259",\r | |
1438 | PCIBlankEntry\r | |
1439 | },\r | |
1440 | {\r | |
1441 | 0x01,\r | |
1442 | L"ISA",\r | |
1443 | PCIBlankEntry\r | |
1444 | },\r | |
1445 | {\r | |
1446 | 0x02,\r | |
1447 | L"EISA",\r | |
1448 | PCIBlankEntry\r | |
1449 | },\r | |
1450 | {\r | |
1451 | 0x10,\r | |
1452 | L"IO APIC",\r | |
1453 | PCIBlankEntry\r | |
1454 | },\r | |
1455 | {\r | |
1456 | 0x20,\r | |
1457 | L"IO(x) APIC interrupt controller",\r | |
1458 | PCIBlankEntry\r | |
1459 | },\r | |
1460 | {\r | |
1461 | 0x00,\r | |
1462 | NULL,\r | |
1463 | /* null string ends the list */NULL\r | |
1464 | }\r | |
1465 | };\r | |
1466 | \r | |
1467 | PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r | |
1468 | {\r | |
1469 | 0x00,\r | |
1470 | L"Generic 8237",\r | |
1471 | PCIBlankEntry\r | |
1472 | },\r | |
1473 | {\r | |
1474 | 0x01,\r | |
1475 | L"ISA",\r | |
1476 | PCIBlankEntry\r | |
1477 | },\r | |
1478 | {\r | |
1479 | 0x02,\r | |
1480 | L"EISA",\r | |
1481 | PCIBlankEntry\r | |
1482 | },\r | |
1483 | {\r | |
1484 | 0x00,\r | |
1485 | NULL,\r | |
1486 | /* null string ends the list */NULL\r | |
1487 | }\r | |
1488 | };\r | |
1489 | \r | |
1490 | PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r | |
1491 | {\r | |
1492 | 0x00,\r | |
1493 | L"Generic 8254",\r | |
1494 | PCIBlankEntry\r | |
1495 | },\r | |
1496 | {\r | |
1497 | 0x01,\r | |
1498 | L"ISA",\r | |
1499 | PCIBlankEntry\r | |
1500 | },\r | |
1501 | {\r | |
1502 | 0x02,\r | |
1503 | L"EISA",\r | |
1504 | PCIBlankEntry\r | |
1505 | },\r | |
1506 | {\r | |
1507 | 0x00,\r | |
1508 | NULL,\r | |
1509 | /* null string ends the list */NULL\r | |
1510 | }\r | |
1511 | };\r | |
1512 | \r | |
1513 | PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r | |
1514 | {\r | |
1515 | 0x00,\r | |
1516 | L"Generic",\r | |
1517 | PCIBlankEntry\r | |
1518 | },\r | |
1519 | {\r | |
1520 | 0x01,\r | |
1521 | L"ISA",\r | |
1522 | PCIBlankEntry\r | |
1523 | },\r | |
1524 | {\r | |
1525 | 0x02,\r | |
1526 | L"EISA",\r | |
1527 | PCIBlankEntry\r | |
1528 | },\r | |
1529 | {\r | |
1530 | 0x00,\r | |
1531 | NULL,\r | |
1532 | /* null string ends the list */NULL\r | |
1533 | }\r | |
1534 | };\r | |
1535 | \r | |
1536 | PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r | |
1537 | {\r | |
1538 | 0x00,\r | |
1539 | L"Generic",\r | |
1540 | PCIBlankEntry\r | |
1541 | },\r | |
1542 | {\r | |
1543 | 0x10,\r | |
1544 | L"",\r | |
1545 | PCIBlankEntry\r | |
1546 | },\r | |
1547 | {\r | |
1548 | 0x00,\r | |
1549 | NULL,\r | |
1550 | /* null string ends the list */NULL\r | |
1551 | }\r | |
1552 | };\r | |
1553 | \r | |
1554 | PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r | |
1555 | {\r | |
1556 | 0x00,\r | |
f056e4c1 JC |
1557 | L"",\r |
1558 | PCIBlankEntry\r | |
1559 | },\r | |
1560 | {\r | |
1561 | 0x10,\r | |
1562 | L"Using 1394 OpenHCI spec",\r | |
1563 | PCIBlankEntry\r | |
1564 | },\r | |
1565 | {\r | |
1566 | 0x00,\r | |
1567 | NULL,\r | |
1568 | /* null string ends the list */NULL\r | |
1569 | }\r | |
1570 | };\r | |
1571 | \r | |
1572 | PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r | |
1573 | {\r | |
1574 | 0x00,\r | |
1575 | L"UHCI",\r | |
5d73d92f | 1576 | PCIBlankEntry\r |
1577 | },\r | |
1578 | {\r | |
1579 | 0x10,\r | |
f056e4c1 JC |
1580 | L"OHCI",\r |
1581 | PCIBlankEntry\r | |
1582 | },\r | |
1583 | {\r | |
1584 | 0x20,\r | |
1585 | L"EHCI",\r | |
1586 | PCIBlankEntry\r | |
1587 | },\r | |
1588 | {\r | |
1589 | 0x30,\r | |
1590 | L"xHCI",\r | |
5d73d92f | 1591 | PCIBlankEntry\r |
1592 | },\r | |
1593 | {\r | |
1594 | 0x80,\r | |
1595 | L"No specific programming interface",\r | |
1596 | PCIBlankEntry\r | |
1597 | },\r | |
1598 | {\r | |
1599 | 0xfe,\r | |
1600 | L"(Not Host Controller)",\r | |
1601 | PCIBlankEntry\r | |
1602 | },\r | |
1603 | {\r | |
1604 | 0x00,\r | |
1605 | NULL,\r | |
1606 | /* null string ends the list */NULL\r | |
1607 | }\r | |
1608 | };\r | |
1609 | \r | |
f056e4c1 | 1610 | PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r |
5d73d92f | 1611 | {\r |
1612 | 0x00,\r | |
f056e4c1 JC |
1613 | L"SMIC",\r |
1614 | PCIBlankEntry\r | |
1615 | },\r | |
1616 | {\r | |
1617 | 0x01,\r | |
1618 | L"Keyboard Controller Style",\r | |
1619 | PCIBlankEntry\r | |
1620 | },\r | |
1621 | {\r | |
1622 | 0x02,\r | |
1623 | L"Block Transfer",\r | |
1624 | PCIBlankEntry\r | |
1625 | },\r | |
1626 | {\r | |
1627 | 0x00,\r | |
1628 | NULL,\r | |
1629 | /* null string ends the list */NULL\r | |
1630 | }\r | |
1631 | };\r | |
1632 | \r | |
1633 | PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r | |
1634 | {\r | |
1635 | 0x00,\r | |
1636 | L"Consumer IR controller",\r | |
5d73d92f | 1637 | PCIBlankEntry\r |
1638 | },\r | |
1639 | {\r | |
1640 | 0x10,\r | |
f056e4c1 | 1641 | L"UWB Radio controller",\r |
5d73d92f | 1642 | PCIBlankEntry\r |
1643 | },\r | |
1644 | {\r | |
1645 | 0x00,\r | |
1646 | NULL,\r | |
1647 | /* null string ends the list */NULL\r | |
1648 | }\r | |
1649 | };\r | |
1650 | \r | |
1651 | PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r | |
1652 | {\r | |
1653 | 0x00,\r | |
1654 | L"Message FIFO at offset 40h",\r | |
1655 | PCIBlankEntry\r | |
1656 | },\r | |
1657 | {\r | |
1658 | 0x01,\r | |
1659 | L"",\r | |
1660 | PCIBlankEntry\r | |
1661 | },\r | |
1662 | {\r | |
1663 | 0x00,\r | |
1664 | NULL,\r | |
1665 | /* null string ends the list */NULL\r | |
1666 | }\r | |
1667 | };\r | |
1668 | \r | |
5d73d92f | 1669 | \r |
a1d4bfcc | 1670 | /**\r |
5d73d92f | 1671 | Generates printable Unicode strings that represent PCI device class,\r |
1672 | subclass and programmed I/F based on a value passed to the function.\r | |
1673 | \r | |
a1d4bfcc | 1674 | @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r |
5d73d92f | 1675 | PCI device. The encodings are:\r |
1676 | bits 23:16 - Base Class Code\r | |
1677 | bits 15:8 - Sub-Class Code\r | |
1678 | bits 7:0 - Programming Interface\r | |
4ff7e37b | 1679 | @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r |
5d73d92f | 1680 | printable class strings corresponding to ClassCode. The\r |
1681 | caller must not modify the strings that are pointed by\r | |
1682 | the fields in ClassStrings.\r | |
5d73d92f | 1683 | **/\r |
a1d4bfcc | 1684 | VOID\r |
1685 | PciGetClassStrings (\r | |
1686 | IN UINT32 ClassCode,\r | |
1687 | IN OUT PCI_CLASS_STRINGS *ClassStrings\r | |
1688 | )\r | |
5d73d92f | 1689 | {\r |
1690 | INTN Index;\r | |
1691 | UINT8 Code;\r | |
1692 | PCI_CLASS_ENTRY *CurrentClass;\r | |
1693 | \r | |
1694 | //\r | |
1695 | // Assume no strings found\r | |
1696 | //\r | |
1697 | ClassStrings->BaseClass = L"UNDEFINED";\r | |
1698 | ClassStrings->SubClass = L"UNDEFINED";\r | |
1699 | ClassStrings->PIFClass = L"UNDEFINED";\r | |
1700 | \r | |
1701 | CurrentClass = gClassStringList;\r | |
1702 | Code = (UINT8) (ClassCode >> 16);\r | |
1703 | Index = 0;\r | |
1704 | \r | |
1705 | //\r | |
1706 | // Go through all entries of the base class, until the entry with a matching\r | |
1707 | // base class code is found. If reaches an entry with a null description\r | |
1708 | // text, the last entry is met, which means no text for the base class was\r | |
1709 | // found, so no more action is needed.\r | |
1710 | //\r | |
1711 | while (Code != CurrentClass[Index].Code) {\r | |
1712 | if (NULL == CurrentClass[Index].DescText) {\r | |
1713 | return ;\r | |
1714 | }\r | |
1715 | \r | |
1716 | Index++;\r | |
1717 | }\r | |
1718 | //\r | |
1719 | // A base class was found. Assign description, and check if this class has\r | |
1720 | // sub-class defined. If sub-class defined, no more action is needed,\r | |
1721 | // otherwise, continue to find description for the sub-class code.\r | |
1722 | //\r | |
1723 | ClassStrings->BaseClass = CurrentClass[Index].DescText;\r | |
1724 | if (NULL == CurrentClass[Index].LowerLevelClass) {\r | |
1725 | return ;\r | |
1726 | }\r | |
1727 | //\r | |
1728 | // find Subclass entry\r | |
1729 | //\r | |
1730 | CurrentClass = CurrentClass[Index].LowerLevelClass;\r | |
1731 | Code = (UINT8) (ClassCode >> 8);\r | |
1732 | Index = 0;\r | |
1733 | \r | |
1734 | //\r | |
1735 | // Go through all entries of the sub-class, until the entry with a matching\r | |
1736 | // sub-class code is found. If reaches an entry with a null description\r | |
1737 | // text, the last entry is met, which means no text for the sub-class was\r | |
1738 | // found, so no more action is needed.\r | |
1739 | //\r | |
1740 | while (Code != CurrentClass[Index].Code) {\r | |
1741 | if (NULL == CurrentClass[Index].DescText) {\r | |
1742 | return ;\r | |
1743 | }\r | |
1744 | \r | |
1745 | Index++;\r | |
1746 | }\r | |
1747 | //\r | |
1748 | // A class was found for the sub-class code. Assign description, and check if\r | |
1749 | // this sub-class has programming interface defined. If no, no more action is\r | |
1750 | // needed, otherwise, continue to find description for the programming\r | |
1751 | // interface.\r | |
1752 | //\r | |
1753 | ClassStrings->SubClass = CurrentClass[Index].DescText;\r | |
1754 | if (NULL == CurrentClass[Index].LowerLevelClass) {\r | |
1755 | return ;\r | |
1756 | }\r | |
1757 | //\r | |
1758 | // Find programming interface entry\r | |
1759 | //\r | |
1760 | CurrentClass = CurrentClass[Index].LowerLevelClass;\r | |
1761 | Code = (UINT8) ClassCode;\r | |
1762 | Index = 0;\r | |
1763 | \r | |
1764 | //\r | |
1765 | // Go through all entries of the I/F entries, until the entry with a\r | |
1766 | // matching I/F code is found. If reaches an entry with a null description\r | |
1767 | // text, the last entry is met, which means no text was found, so no more\r | |
1768 | // action is needed.\r | |
1769 | //\r | |
1770 | while (Code != CurrentClass[Index].Code) {\r | |
1771 | if (NULL == CurrentClass[Index].DescText) {\r | |
1772 | return ;\r | |
1773 | }\r | |
1774 | \r | |
1775 | Index++;\r | |
1776 | }\r | |
1777 | //\r | |
1778 | // A class was found for the I/F code. Assign description, done!\r | |
1779 | //\r | |
1780 | ClassStrings->PIFClass = CurrentClass[Index].DescText;\r | |
1781 | return ;\r | |
1782 | }\r | |
1783 | \r | |
a1d4bfcc | 1784 | /**\r |
1785 | Print strings that represent PCI device class, subclass and programmed I/F.\r | |
1786 | \r | |
1787 | @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r | |
e8a57ade | 1788 | configuration space.\r |
a1d4bfcc | 1789 | @param[in] IncludePIF If the printed string should include the programming I/F part\r |
1790 | **/\r | |
5d73d92f | 1791 | VOID\r |
1792 | PciPrintClassCode (\r | |
1793 | IN UINT8 *ClassCodePtr,\r | |
1794 | IN BOOLEAN IncludePIF\r | |
1795 | )\r | |
5d73d92f | 1796 | {\r |
1797 | UINT32 ClassCode;\r | |
1798 | PCI_CLASS_STRINGS ClassStrings;\r | |
5d73d92f | 1799 | \r |
1800 | ClassCode = 0;\r | |
e8a57ade JC |
1801 | ClassCode |= (UINT32)ClassCodePtr[0];\r |
1802 | ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r | |
1803 | ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r | |
5d73d92f | 1804 | \r |
1805 | //\r | |
1806 | // Get name from class code\r | |
1807 | //\r | |
1808 | PciGetClassStrings (ClassCode, &ClassStrings);\r | |
1809 | \r | |
1810 | if (IncludePIF) {\r | |
1811 | //\r | |
c37e0f16 | 1812 | // Print base class, sub class, and programming inferface name\r |
5d73d92f | 1813 | //\r |
c37e0f16 | 1814 | ShellPrintEx (-1, -1, L"%s - %s - %s",\r |
5d73d92f | 1815 | ClassStrings.BaseClass,\r |
1816 | ClassStrings.SubClass,\r | |
1817 | ClassStrings.PIFClass\r | |
1818 | );\r | |
1819 | \r | |
1820 | } else {\r | |
1821 | //\r | |
c37e0f16 | 1822 | // Only print base class and sub class name\r |
5d73d92f | 1823 | //\r |
c37e0f16 | 1824 | ShellPrintEx (-1, -1, L"%s - %s",\r |
5d73d92f | 1825 | ClassStrings.BaseClass,\r |
1826 | ClassStrings.SubClass\r | |
c37e0f16 | 1827 | );\r |
5d73d92f | 1828 | }\r |
1829 | }\r | |
1830 | \r | |
a1d4bfcc | 1831 | /**\r |
1832 | This function finds out the protocol which is in charge of the given\r | |
1833 | segment, and its bus range covers the current bus number. It lookes\r | |
1834 | each instances of RootBridgeIoProtocol handle, until the one meets the\r | |
1835 | criteria is found.\r | |
1836 | \r | |
1837 | @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
1838 | @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
1839 | @param[in] Segment Segment number of device we are dealing with.\r | |
1840 | @param[in] Bus Bus number of device we are dealing with.\r | |
1841 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
1842 | \r | |
1843 | @retval EFI_SUCCESS The command completed successfully.\r | |
1844 | @retval EFI_INVALID_PARAMETER Invalid parameter.\r | |
5d73d92f | 1845 | \r |
a1d4bfcc | 1846 | **/\r |
5d73d92f | 1847 | EFI_STATUS\r |
1848 | PciFindProtocolInterface (\r | |
1849 | IN EFI_HANDLE *HandleBuf,\r | |
1850 | IN UINTN HandleCount,\r | |
1851 | IN UINT16 Segment,\r | |
1852 | IN UINT16 Bus,\r | |
1853 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r | |
1854 | );\r | |
1855 | \r | |
a1d4bfcc | 1856 | /**\r |
1857 | This function gets the protocol interface from the given handle, and\r | |
1858 | obtains its address space descriptors.\r | |
1859 | \r | |
1860 | @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r | |
1861 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
1862 | @param[out] Descriptors Points to the address space descriptors.\r | |
1863 | \r | |
1864 | @retval EFI_SUCCESS The command completed successfully\r | |
1865 | **/\r | |
5d73d92f | 1866 | EFI_STATUS\r |
1867 | PciGetProtocolAndResource (\r | |
1868 | IN EFI_HANDLE Handle,\r | |
1869 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r | |
1870 | OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r | |
1871 | );\r | |
1872 | \r | |
a1d4bfcc | 1873 | /**\r |
1874 | This function get the next bus range of given address space descriptors.\r | |
1875 | It also moves the pointer backward a node, to get prepared to be called\r | |
1876 | again.\r | |
1877 | \r | |
4ff7e37b ED |
1878 | @param[in, out] Descriptors Points to current position of a serial of address space\r |
1879 | descriptors.\r | |
1880 | @param[out] MinBus The lower range of bus number.\r | |
1881 | @param[out] MaxBus The upper range of bus number.\r | |
1882 | @param[out] IsEnd Meet end of the serial of descriptors.\r | |
a1d4bfcc | 1883 | \r |
1884 | @retval EFI_SUCCESS The command completed successfully.\r | |
1885 | **/\r | |
5d73d92f | 1886 | EFI_STATUS\r |
1887 | PciGetNextBusRange (\r | |
1888 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r | |
1889 | OUT UINT16 *MinBus,\r | |
1890 | OUT UINT16 *MaxBus,\r | |
1891 | OUT BOOLEAN *IsEnd\r | |
1892 | );\r | |
1893 | \r | |
a1d4bfcc | 1894 | /**\r |
1895 | Explain the data in PCI configuration space. The part which is common for\r | |
1896 | PCI device and bridge is interpreted in this function. It calls other\r | |
1897 | functions to interpret data unique for device or bridge.\r | |
1898 | \r | |
1899 | @param[in] ConfigSpace Data in PCI configuration space.\r | |
1900 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1901 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
a1d4bfcc | 1902 | **/\r |
33cc487c RN |
1903 | VOID\r |
1904 | PciExplainPci (\r | |
5d73d92f | 1905 | IN PCI_CONFIG_SPACE *ConfigSpace,\r |
1906 | IN UINT64 Address,\r | |
33cc487c | 1907 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r |
5d73d92f | 1908 | );\r |
1909 | \r | |
a1d4bfcc | 1910 | /**\r |
1911 | Explain the device specific part of data in PCI configuration space.\r | |
1912 | \r | |
1913 | @param[in] Device Data in PCI configuration space.\r | |
1914 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1915 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1916 | \r | |
1917 | @retval EFI_SUCCESS The command completed successfully.\r | |
1918 | **/\r | |
5d73d92f | 1919 | EFI_STATUS\r |
1920 | PciExplainDeviceData (\r | |
0c84a69f | 1921 | IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r |
5d73d92f | 1922 | IN UINT64 Address,\r |
1923 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
1924 | );\r | |
1925 | \r | |
a1d4bfcc | 1926 | /**\r |
1927 | Explain the bridge specific part of data in PCI configuration space.\r | |
1928 | \r | |
1929 | @param[in] Bridge Bridge specific data region in PCI configuration space.\r | |
1930 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1931 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1932 | \r | |
1933 | @retval EFI_SUCCESS The command completed successfully.\r | |
1934 | **/\r | |
5d73d92f | 1935 | EFI_STATUS\r |
1936 | PciExplainBridgeData (\r | |
0c84a69f | 1937 | IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r |
a1d4bfcc | 1938 | IN UINT64 Address,\r |
1939 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 1940 | );\r |
1941 | \r | |
a1d4bfcc | 1942 | /**\r |
1943 | Explain the Base Address Register(Bar) in PCI configuration space.\r | |
1944 | \r | |
4ff7e37b ED |
1945 | @param[in] Bar Points to the Base Address Register intended to interpret.\r |
1946 | @param[in] Command Points to the register Command.\r | |
1947 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1948 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1949 | @param[in, out] Index The Index.\r | |
a1d4bfcc | 1950 | \r |
1951 | @retval EFI_SUCCESS The command completed successfully.\r | |
1952 | **/\r | |
5d73d92f | 1953 | EFI_STATUS\r |
1954 | PciExplainBar (\r | |
1955 | IN UINT32 *Bar,\r | |
1956 | IN UINT16 *Command,\r | |
1957 | IN UINT64 Address,\r | |
1958 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
1959 | IN OUT UINTN *Index\r | |
1960 | );\r | |
1961 | \r | |
a1d4bfcc | 1962 | /**\r |
1963 | Explain the cardbus specific part of data in PCI configuration space.\r | |
1964 | \r | |
1965 | @param[in] CardBus CardBus specific region of PCI configuration space.\r | |
1966 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1967 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1968 | \r | |
1969 | @retval EFI_SUCCESS The command completed successfully.\r | |
1970 | **/\r | |
5d73d92f | 1971 | EFI_STATUS\r |
1972 | PciExplainCardBusData (\r | |
0c84a69f | 1973 | IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r |
5d73d92f | 1974 | IN UINT64 Address,\r |
1975 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
1976 | );\r | |
1977 | \r | |
a1d4bfcc | 1978 | /**\r |
1979 | Explain each meaningful bit of register Status. The definition of Status is\r | |
1980 | slightly different depending on the PCI header type.\r | |
1981 | \r | |
1982 | @param[in] Status Points to the content of register Status.\r | |
1983 | @param[in] MainStatus Indicates if this register is main status(not secondary\r | |
1984 | status).\r | |
1985 | @param[in] HeaderType Header type of this PCI device.\r | |
1986 | \r | |
1987 | @retval EFI_SUCCESS The command completed successfully.\r | |
1988 | **/\r | |
5d73d92f | 1989 | EFI_STATUS\r |
1990 | PciExplainStatus (\r | |
1991 | IN UINT16 *Status,\r | |
1992 | IN BOOLEAN MainStatus,\r | |
1993 | IN PCI_HEADER_TYPE HeaderType\r | |
1994 | );\r | |
1995 | \r | |
a1d4bfcc | 1996 | /**\r |
1997 | Explain each meaningful bit of register Command.\r | |
1998 | \r | |
1999 | @param[in] Command Points to the content of register Command.\r | |
2000 | \r | |
2001 | @retval EFI_SUCCESS The command completed successfully.\r | |
2002 | **/\r | |
5d73d92f | 2003 | EFI_STATUS\r |
2004 | PciExplainCommand (\r | |
2005 | IN UINT16 *Command\r | |
2006 | );\r | |
2007 | \r | |
a1d4bfcc | 2008 | /**\r |
2009 | Explain each meaningful bit of register Bridge Control.\r | |
2010 | \r | |
2011 | @param[in] BridgeControl Points to the content of register Bridge Control.\r | |
2012 | @param[in] HeaderType The headertype.\r | |
2013 | \r | |
2014 | @retval EFI_SUCCESS The command completed successfully.\r | |
2015 | **/\r | |
5d73d92f | 2016 | EFI_STATUS\r |
2017 | PciExplainBridgeControl (\r | |
2018 | IN UINT16 *BridgeControl,\r | |
2019 | IN PCI_HEADER_TYPE HeaderType\r | |
2020 | );\r | |
2021 | \r | |
a1d4bfcc | 2022 | /**\r |
33cc487c | 2023 | Locate capability register block per capability ID.\r |
a1d4bfcc | 2024 | \r |
33cc487c RN |
2025 | @param[in] ConfigSpace Data in PCI configuration space.\r |
2026 | @param[in] CapabilityId The capability ID.\r | |
a1d4bfcc | 2027 | \r |
33cc487c | 2028 | @return The offset of the register block per capability ID.\r |
a1d4bfcc | 2029 | **/\r |
33cc487c RN |
2030 | UINT8\r |
2031 | LocatePciCapability (\r | |
2032 | IN PCI_CONFIG_SPACE *ConfigSpace,\r | |
2033 | IN UINT8 CapabilityId\r | |
5d73d92f | 2034 | );\r |
2035 | \r | |
a1d4bfcc | 2036 | /**\r |
2037 | Display Pcie device structure.\r | |
2038 | \r | |
33cc487c RN |
2039 | @param[in] PciExpressCap PCI Express capability buffer.\r |
2040 | @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r | |
2041 | @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r | |
a1d4bfcc | 2042 | **/\r |
33cc487c | 2043 | VOID\r |
5d73d92f | 2044 | PciExplainPciExpress (\r |
33cc487c RN |
2045 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r |
2046 | IN UINT8 *ExtendedConfigSpace,\r | |
2047 | IN CONST UINT16 ExtendedCapability\r | |
5d73d92f | 2048 | );\r |
2049 | \r | |
a1d4bfcc | 2050 | /**\r |
2051 | Print out information of the capability information.\r | |
2052 | \r | |
2053 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2054 | \r | |
2055 | @retval EFI_SUCCESS The operation was successful.\r | |
2056 | **/\r | |
5d73d92f | 2057 | EFI_STATUS\r |
2058 | ExplainPcieCapReg (\r | |
0c84a69f | 2059 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2060 | );\r |
2061 | \r | |
2062 | /**\r | |
2063 | Print out information of the device capability information.\r | |
2064 | \r | |
2065 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2066 | \r |
a1d4bfcc | 2067 | @retval EFI_SUCCESS The operation was successful.\r |
2068 | **/\r | |
5d73d92f | 2069 | EFI_STATUS\r |
2070 | ExplainPcieDeviceCap (\r | |
0c84a69f | 2071 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2072 | );\r |
2073 | \r | |
2074 | /**\r | |
2075 | Print out information of the device control information.\r | |
5d73d92f | 2076 | \r |
a1d4bfcc | 2077 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2078 | \r | |
2079 | @retval EFI_SUCCESS The operation was successful.\r | |
2080 | **/\r | |
5d73d92f | 2081 | EFI_STATUS\r |
2082 | ExplainPcieDeviceControl (\r | |
0c84a69f | 2083 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2084 | );\r |
5d73d92f | 2085 | \r |
a1d4bfcc | 2086 | /**\r |
2087 | Print out information of the device status information.\r | |
2088 | \r | |
2089 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2090 | \r | |
2091 | @retval EFI_SUCCESS The operation was successful.\r | |
2092 | **/\r | |
5d73d92f | 2093 | EFI_STATUS\r |
2094 | ExplainPcieDeviceStatus (\r | |
0c84a69f | 2095 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2096 | );\r |
2097 | \r | |
2098 | /**\r | |
2099 | Print out information of the device link information.\r | |
2100 | \r | |
2101 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2102 | \r |
a1d4bfcc | 2103 | @retval EFI_SUCCESS The operation was successful.\r |
2104 | **/\r | |
5d73d92f | 2105 | EFI_STATUS\r |
2106 | ExplainPcieLinkCap (\r | |
0c84a69f | 2107 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2108 | );\r |
2109 | \r | |
2110 | /**\r | |
2111 | Print out information of the device link control information.\r | |
5d73d92f | 2112 | \r |
a1d4bfcc | 2113 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2114 | \r | |
2115 | @retval EFI_SUCCESS The operation was successful.\r | |
2116 | **/\r | |
5d73d92f | 2117 | EFI_STATUS\r |
2118 | ExplainPcieLinkControl (\r | |
0c84a69f | 2119 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2120 | );\r |
5d73d92f | 2121 | \r |
a1d4bfcc | 2122 | /**\r |
2123 | Print out information of the device link status information.\r | |
2124 | \r | |
2125 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2126 | \r | |
2127 | @retval EFI_SUCCESS The operation was successful.\r | |
2128 | **/\r | |
5d73d92f | 2129 | EFI_STATUS\r |
2130 | ExplainPcieLinkStatus (\r | |
0c84a69f | 2131 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2132 | );\r |
2133 | \r | |
2134 | /**\r | |
2135 | Print out information of the device slot information.\r | |
2136 | \r | |
2137 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2138 | \r |
a1d4bfcc | 2139 | @retval EFI_SUCCESS The operation was successful.\r |
2140 | **/\r | |
5d73d92f | 2141 | EFI_STATUS\r |
2142 | ExplainPcieSlotCap (\r | |
0c84a69f | 2143 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2144 | );\r |
2145 | \r | |
2146 | /**\r | |
2147 | Print out information of the device slot control information.\r | |
5d73d92f | 2148 | \r |
a1d4bfcc | 2149 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2150 | \r | |
2151 | @retval EFI_SUCCESS The operation was successful.\r | |
2152 | **/\r | |
5d73d92f | 2153 | EFI_STATUS\r |
2154 | ExplainPcieSlotControl (\r | |
0c84a69f | 2155 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2156 | );\r |
5d73d92f | 2157 | \r |
a1d4bfcc | 2158 | /**\r |
2159 | Print out information of the device slot status information.\r | |
2160 | \r | |
2161 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2162 | \r | |
2163 | @retval EFI_SUCCESS The operation was successful.\r | |
2164 | **/\r | |
5d73d92f | 2165 | EFI_STATUS\r |
2166 | ExplainPcieSlotStatus (\r | |
0c84a69f | 2167 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2168 | );\r |
2169 | \r | |
2170 | /**\r | |
2171 | Print out information of the device root information.\r | |
2172 | \r | |
2173 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2174 | \r |
a1d4bfcc | 2175 | @retval EFI_SUCCESS The operation was successful.\r |
2176 | **/\r | |
5d73d92f | 2177 | EFI_STATUS\r |
2178 | ExplainPcieRootControl (\r | |
0c84a69f | 2179 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2180 | );\r |
2181 | \r | |
2182 | /**\r | |
2183 | Print out information of the device root capability information.\r | |
5d73d92f | 2184 | \r |
a1d4bfcc | 2185 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2186 | \r | |
2187 | @retval EFI_SUCCESS The operation was successful.\r | |
2188 | **/\r | |
5d73d92f | 2189 | EFI_STATUS\r |
2190 | ExplainPcieRootCap (\r | |
0c84a69f | 2191 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2192 | );\r |
5d73d92f | 2193 | \r |
a1d4bfcc | 2194 | /**\r |
2195 | Print out information of the device root status information.\r | |
2196 | \r | |
2197 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2198 | \r | |
2199 | @retval EFI_SUCCESS The operation was successful.\r | |
2200 | **/\r | |
5d73d92f | 2201 | EFI_STATUS\r |
2202 | ExplainPcieRootStatus (\r | |
0c84a69f | 2203 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2204 | );\r |
5d73d92f | 2205 | \r |
0c84a69f | 2206 | typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCI_CAPABILITY_PCIEXP *PciExpressCap);\r |
5d73d92f | 2207 | \r |
2208 | typedef enum {\r | |
2209 | FieldWidthUINT8,\r | |
2210 | FieldWidthUINT16,\r | |
2211 | FieldWidthUINT32\r | |
2212 | } PCIE_CAPREG_FIELD_WIDTH;\r | |
2213 | \r | |
2214 | typedef enum {\r | |
2215 | PcieExplainTypeCommon,\r | |
2216 | PcieExplainTypeDevice,\r | |
2217 | PcieExplainTypeLink,\r | |
2218 | PcieExplainTypeSlot,\r | |
2219 | PcieExplainTypeRoot,\r | |
2220 | PcieExplainTypeMax\r | |
2221 | } PCIE_EXPLAIN_TYPE;\r | |
2222 | \r | |
2223 | typedef struct\r | |
2224 | {\r | |
2225 | UINT16 Token;\r | |
2226 | UINTN Offset;\r | |
2227 | PCIE_CAPREG_FIELD_WIDTH Width;\r | |
2228 | PCIE_EXPLAIN_FUNCTION Func;\r | |
2229 | PCIE_EXPLAIN_TYPE Type;\r | |
2230 | } PCIE_EXPLAIN_STRUCT;\r | |
2231 | \r | |
2232 | PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r | |
2233 | {\r | |
2234 | STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r | |
2235 | 0x00,\r | |
2236 | FieldWidthUINT8,\r | |
2237 | NULL,\r | |
2238 | PcieExplainTypeCommon\r | |
2239 | },\r | |
2240 | {\r | |
2241 | STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r | |
2242 | 0x01,\r | |
2243 | FieldWidthUINT8,\r | |
2244 | NULL,\r | |
2245 | PcieExplainTypeCommon\r | |
2246 | },\r | |
2247 | {\r | |
2248 | STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r | |
2249 | 0x02,\r | |
2250 | FieldWidthUINT16,\r | |
2251 | ExplainPcieCapReg,\r | |
2252 | PcieExplainTypeCommon\r | |
2253 | },\r | |
2254 | {\r | |
2255 | STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r | |
2256 | 0x04,\r | |
2257 | FieldWidthUINT32,\r | |
2258 | ExplainPcieDeviceCap,\r | |
2259 | PcieExplainTypeDevice\r | |
2260 | },\r | |
2261 | {\r | |
2262 | STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r | |
2263 | 0x08,\r | |
2264 | FieldWidthUINT16,\r | |
2265 | ExplainPcieDeviceControl,\r | |
2266 | PcieExplainTypeDevice\r | |
2267 | },\r | |
2268 | {\r | |
2269 | STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r | |
2270 | 0x0a,\r | |
2271 | FieldWidthUINT16,\r | |
2272 | ExplainPcieDeviceStatus,\r | |
2273 | PcieExplainTypeDevice\r | |
2274 | },\r | |
2275 | {\r | |
2276 | STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r | |
2277 | 0x0c,\r | |
2278 | FieldWidthUINT32,\r | |
2279 | ExplainPcieLinkCap,\r | |
2280 | PcieExplainTypeLink\r | |
2281 | },\r | |
2282 | {\r | |
2283 | STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r | |
2284 | 0x10,\r | |
2285 | FieldWidthUINT16,\r | |
2286 | ExplainPcieLinkControl,\r | |
2287 | PcieExplainTypeLink\r | |
2288 | },\r | |
2289 | {\r | |
2290 | STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r | |
2291 | 0x12,\r | |
2292 | FieldWidthUINT16,\r | |
2293 | ExplainPcieLinkStatus,\r | |
2294 | PcieExplainTypeLink\r | |
2295 | },\r | |
2296 | {\r | |
2297 | STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r | |
2298 | 0x14,\r | |
2299 | FieldWidthUINT32,\r | |
2300 | ExplainPcieSlotCap,\r | |
2301 | PcieExplainTypeSlot\r | |
2302 | },\r | |
2303 | {\r | |
2304 | STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r | |
2305 | 0x18,\r | |
2306 | FieldWidthUINT16,\r | |
2307 | ExplainPcieSlotControl,\r | |
2308 | PcieExplainTypeSlot\r | |
2309 | },\r | |
2310 | {\r | |
2311 | STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r | |
2312 | 0x1a,\r | |
2313 | FieldWidthUINT16,\r | |
2314 | ExplainPcieSlotStatus,\r | |
2315 | PcieExplainTypeSlot\r | |
2316 | },\r | |
2317 | {\r | |
2318 | STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r | |
2319 | 0x1c,\r | |
2320 | FieldWidthUINT16,\r | |
2321 | ExplainPcieRootControl,\r | |
2322 | PcieExplainTypeRoot\r | |
2323 | },\r | |
2324 | {\r | |
2325 | STRING_TOKEN (STR_PCIEX_RSVDP),\r | |
2326 | 0x1e,\r | |
2327 | FieldWidthUINT16,\r | |
2328 | ExplainPcieRootCap,\r | |
2329 | PcieExplainTypeRoot\r | |
2330 | },\r | |
2331 | {\r | |
2332 | STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r | |
2333 | 0x20,\r | |
2334 | FieldWidthUINT32,\r | |
2335 | ExplainPcieRootStatus,\r | |
2336 | PcieExplainTypeRoot\r | |
2337 | },\r | |
2338 | {\r | |
2339 | 0,\r | |
2340 | 0,\r | |
2341 | (PCIE_CAPREG_FIELD_WIDTH)0,\r | |
2342 | NULL,\r | |
2343 | PcieExplainTypeMax\r | |
2344 | }\r | |
2345 | };\r | |
2346 | \r | |
2347 | //\r | |
2348 | // Global Variables\r | |
2349 | //\r | |
2350 | PCI_CONFIG_SPACE *mConfigSpace = NULL;\r | |
2351 | STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r | |
2352 | {L"-s", TypeValue},\r | |
2353 | {L"-i", TypeFlag},\r | |
c831a2c3 | 2354 | {L"-ec", TypeValue},\r |
5d73d92f | 2355 | {NULL, TypeMax}\r |
2356 | };\r | |
2357 | \r | |
2358 | CHAR16 *DevicePortTypeTable[] = {\r | |
2359 | L"PCI Express Endpoint",\r | |
2360 | L"Legacy PCI Express Endpoint",\r | |
2361 | L"Unknown Type",\r | |
2362 | L"Unknonw Type",\r | |
2363 | L"Root Port of PCI Express Root Complex",\r | |
2364 | L"Upstream Port of PCI Express Switch",\r | |
2365 | L"Downstream Port of PCI Express Switch",\r | |
2366 | L"PCI Express to PCI/PCI-X Bridge",\r | |
2367 | L"PCI/PCI-X to PCI Express Bridge",\r | |
2368 | L"Root Complex Integrated Endpoint",\r | |
2369 | L"Root Complex Event Collector"\r | |
2370 | };\r | |
2371 | \r | |
2372 | CHAR16 *L0sLatencyStrTable[] = {\r | |
2373 | L"Less than 64ns",\r | |
2374 | L"64ns to less than 128ns",\r | |
2375 | L"128ns to less than 256ns",\r | |
2376 | L"256ns to less than 512ns",\r | |
2377 | L"512ns to less than 1us",\r | |
2378 | L"1us to less than 2us",\r | |
2379 | L"2us-4us",\r | |
2380 | L"More than 4us"\r | |
2381 | };\r | |
2382 | \r | |
2383 | CHAR16 *L1LatencyStrTable[] = {\r | |
2384 | L"Less than 1us",\r | |
2385 | L"1us to less than 2us",\r | |
2386 | L"2us to less than 4us",\r | |
2387 | L"4us to less than 8us",\r | |
2388 | L"8us to less than 16us",\r | |
2389 | L"16us to less than 32us",\r | |
2390 | L"32us-64us",\r | |
2391 | L"More than 64us"\r | |
2392 | };\r | |
2393 | \r | |
2394 | CHAR16 *ASPMCtrlStrTable[] = {\r | |
2395 | L"Disabled",\r | |
2396 | L"L0s Entry Enabled",\r | |
2397 | L"L1 Entry Enabled",\r | |
2398 | L"L0s and L1 Entry Enabled"\r | |
2399 | };\r | |
2400 | \r | |
2401 | CHAR16 *SlotPwrLmtScaleTable[] = {\r | |
2402 | L"1.0x",\r | |
2403 | L"0.1x",\r | |
2404 | L"0.01x",\r | |
2405 | L"0.001x"\r | |
2406 | };\r | |
2407 | \r | |
2408 | CHAR16 *IndicatorTable[] = {\r | |
2409 | L"Reserved",\r | |
2410 | L"On",\r | |
2411 | L"Blink",\r | |
2412 | L"Off"\r | |
2413 | };\r | |
2414 | \r | |
2415 | \r | |
a1d4bfcc | 2416 | /**\r |
2417 | Function for 'pci' command.\r | |
2418 | \r | |
2419 | @param[in] ImageHandle Handle to the Image (NULL if Internal).\r | |
2420 | @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r | |
2421 | **/\r | |
5d73d92f | 2422 | SHELL_STATUS\r |
2423 | EFIAPI\r | |
2424 | ShellCommandRunPci (\r | |
2425 | IN EFI_HANDLE ImageHandle,\r | |
2426 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
2427 | )\r | |
2428 | {\r | |
2429 | UINT16 Segment;\r | |
2430 | UINT16 Bus;\r | |
2431 | UINT16 Device;\r | |
2432 | UINT16 Func;\r | |
2433 | UINT64 Address;\r | |
2434 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r | |
2435 | EFI_STATUS Status;\r | |
0c84a69f | 2436 | PCI_DEVICE_INDEPENDENT_REGION PciHeader;\r |
5d73d92f | 2437 | PCI_CONFIG_SPACE ConfigSpace;\r |
2438 | UINTN ScreenCount;\r | |
2439 | UINTN TempColumn;\r | |
2440 | UINTN ScreenSize;\r | |
2441 | BOOLEAN ExplainData;\r | |
2442 | UINTN Index;\r | |
2443 | UINTN SizeOfHeader;\r | |
2444 | BOOLEAN PrintTitle;\r | |
2445 | UINTN HandleBufSize;\r | |
2446 | EFI_HANDLE *HandleBuf;\r | |
2447 | UINTN HandleCount;\r | |
2448 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r | |
2449 | UINT16 MinBus;\r | |
2450 | UINT16 MaxBus;\r | |
2451 | BOOLEAN IsEnd;\r | |
2452 | LIST_ENTRY *Package;\r | |
2453 | CHAR16 *ProblemParam;\r | |
2454 | SHELL_STATUS ShellStatus;\r | |
5d73d92f | 2455 | CONST CHAR16 *Temp;\r |
6855763e | 2456 | UINT64 RetVal;\r |
33cc487c RN |
2457 | UINT16 ExtendedCapability;\r |
2458 | UINT8 PcieCapabilityPtr;\r | |
2459 | UINT8 *ExtendedConfigSpace;\r | |
2460 | UINTN ExtendedConfigSize;\r | |
5d73d92f | 2461 | \r |
2462 | ShellStatus = SHELL_SUCCESS;\r | |
2463 | Status = EFI_SUCCESS;\r | |
2464 | Address = 0;\r | |
5d73d92f | 2465 | IoDev = NULL;\r |
2466 | HandleBuf = NULL;\r | |
2467 | Package = NULL;\r | |
2468 | \r | |
2469 | //\r | |
2470 | // initialize the shell lib (we must be in non-auto-init...)\r | |
2471 | //\r | |
2472 | Status = ShellInitialize();\r | |
2473 | ASSERT_EFI_ERROR(Status);\r | |
2474 | \r | |
2475 | Status = CommandInit();\r | |
2476 | ASSERT_EFI_ERROR(Status);\r | |
2477 | \r | |
2478 | //\r | |
2479 | // parse the command line\r | |
2480 | //\r | |
2481 | Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r | |
2482 | if (EFI_ERROR(Status)) {\r | |
2483 | if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r | |
ba0014b9 | 2484 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam);\r |
5d73d92f | 2485 | FreePool(ProblemParam);\r |
2486 | ShellStatus = SHELL_INVALID_PARAMETER;\r | |
2487 | } else {\r | |
2488 | ASSERT(FALSE);\r | |
2489 | }\r | |
2490 | } else {\r | |
2491 | \r | |
3737ac2b | 2492 | if (ShellCommandLineGetCount(Package) == 2) {\r |
ba0014b9 | 2493 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci");\r |
3737ac2b | 2494 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2495 | goto Done;\r | |
2496 | }\r | |
5d73d92f | 2497 | \r |
3737ac2b | 2498 | if (ShellCommandLineGetCount(Package) > 4) {\r |
ba0014b9 | 2499 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci");\r |
3737ac2b | 2500 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2501 | goto Done;\r | |
2502 | }\r | |
c831a2c3 | 2503 | if (ShellCommandLineGetFlag(Package, L"-ec") && ShellCommandLineGetValue(Package, L"-ec") == NULL) {\r |
ba0014b9 | 2504 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-ec");\r |
c831a2c3 RN |
2505 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2506 | goto Done;\r | |
2507 | }\r | |
3737ac2b | 2508 | if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r |
ba0014b9 | 2509 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s");\r |
3737ac2b | 2510 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2511 | goto Done;\r | |
2512 | }\r | |
5d73d92f | 2513 | //\r |
2514 | // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r | |
2515 | // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r | |
2516 | // space for handles and call it again.\r | |
2517 | //\r | |
2518 | HandleBufSize = sizeof (EFI_HANDLE);\r | |
3737ac2b | 2519 | HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r |
5d73d92f | 2520 | if (HandleBuf == NULL) {\r |
ba0014b9 | 2521 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2522 | ShellStatus = SHELL_OUT_OF_RESOURCES;\r |
2523 | goto Done;\r | |
2524 | }\r | |
2525 | \r | |
2526 | Status = gBS->LocateHandle (\r | |
2527 | ByProtocol,\r | |
2528 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2529 | NULL,\r | |
2530 | &HandleBufSize,\r | |
2531 | HandleBuf\r | |
2532 | );\r | |
2533 | \r | |
2534 | if (Status == EFI_BUFFER_TOO_SMALL) {\r | |
2535 | HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r | |
2536 | if (HandleBuf == NULL) {\r | |
ba0014b9 | 2537 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2538 | ShellStatus = SHELL_OUT_OF_RESOURCES;\r |
2539 | goto Done;\r | |
2540 | }\r | |
2541 | \r | |
2542 | Status = gBS->LocateHandle (\r | |
2543 | ByProtocol,\r | |
2544 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2545 | NULL,\r | |
2546 | &HandleBufSize,\r | |
2547 | HandleBuf\r | |
2548 | );\r | |
2549 | }\r | |
2550 | \r | |
2551 | if (EFI_ERROR (Status)) {\r | |
ba0014b9 | 2552 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2553 | ShellStatus = SHELL_NOT_FOUND;\r |
2554 | goto Done;\r | |
2555 | }\r | |
2556 | \r | |
2557 | HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r | |
2558 | //\r | |
2559 | // Argument Count == 1(no other argument): enumerate all pci functions\r | |
2560 | //\r | |
3737ac2b | 2561 | if (ShellCommandLineGetCount(Package) == 1) {\r |
5d73d92f | 2562 | gST->ConOut->QueryMode (\r |
2563 | gST->ConOut,\r | |
2564 | gST->ConOut->Mode->Mode,\r | |
2565 | &TempColumn,\r | |
2566 | &ScreenSize\r | |
2567 | );\r | |
2568 | \r | |
2569 | ScreenCount = 0;\r | |
2570 | ScreenSize -= 4;\r | |
2571 | if ((ScreenSize & 1) == 1) {\r | |
2572 | ScreenSize -= 1;\r | |
2573 | }\r | |
2574 | \r | |
2575 | PrintTitle = TRUE;\r | |
2576 | \r | |
2577 | //\r | |
2578 | // For each handle, which decides a segment and a bus number range,\r | |
2579 | // enumerate all devices on it.\r | |
2580 | //\r | |
2581 | for (Index = 0; Index < HandleCount; Index++) {\r | |
2582 | Status = PciGetProtocolAndResource (\r | |
2583 | HandleBuf[Index],\r | |
2584 | &IoDev,\r | |
2585 | &Descriptors\r | |
2586 | );\r | |
2587 | if (EFI_ERROR (Status)) {\r | |
ba0014b9 | 2588 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2589 | ShellStatus = SHELL_NOT_FOUND;\r |
2590 | goto Done;\r | |
2591 | }\r | |
2592 | //\r | |
2593 | // No document say it's impossible for a RootBridgeIo protocol handle\r | |
2594 | // to have more than one address space descriptors, so find out every\r | |
2595 | // bus range and for each of them do device enumeration.\r | |
2596 | //\r | |
2597 | while (TRUE) {\r | |
2598 | Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r | |
2599 | \r | |
2600 | if (EFI_ERROR (Status)) {\r | |
ba0014b9 | 2601 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2602 | ShellStatus = SHELL_NOT_FOUND;\r |
2603 | goto Done;\r | |
2604 | }\r | |
2605 | \r | |
2606 | if (IsEnd) {\r | |
2607 | break;\r | |
2608 | }\r | |
2609 | \r | |
2610 | for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r | |
2611 | //\r | |
2612 | // For each devices, enumerate all functions it contains\r | |
2613 | //\r | |
2614 | for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r | |
2615 | //\r | |
2616 | // For each function, read its configuration space and print summary\r | |
2617 | //\r | |
2618 | for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r | |
2619 | if (ShellGetExecutionBreakFlag ()) {\r | |
2620 | ShellStatus = SHELL_ABORTED;\r | |
2621 | goto Done;\r | |
2622 | }\r | |
0c84a69f | 2623 | Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r |
5d73d92f | 2624 | IoDev->Pci.Read (\r |
2625 | IoDev,\r | |
2626 | EfiPciWidthUint16,\r | |
2627 | Address,\r | |
2628 | 1,\r | |
2629 | &PciHeader.VendorId\r | |
2630 | );\r | |
2631 | \r | |
2632 | //\r | |
2633 | // If VendorId = 0xffff, there does not exist a device at this\r | |
2634 | // location. For each device, if there is any function on it,\r | |
2635 | // there must be 1 function at Function 0. So if Func = 0, there\r | |
2636 | // will be no more functions in the same device, so we can break\r | |
2637 | // loop to deal with the next device.\r | |
2638 | //\r | |
2639 | if (PciHeader.VendorId == 0xffff && Func == 0) {\r | |
2640 | break;\r | |
2641 | }\r | |
2642 | \r | |
2643 | if (PciHeader.VendorId != 0xffff) {\r | |
2644 | \r | |
2645 | if (PrintTitle) {\r | |
2646 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r | |
2647 | PrintTitle = FALSE;\r | |
2648 | }\r | |
2649 | \r | |
2650 | IoDev->Pci.Read (\r | |
2651 | IoDev,\r | |
2652 | EfiPciWidthUint32,\r | |
2653 | Address,\r | |
2654 | sizeof (PciHeader) / sizeof (UINT32),\r | |
2655 | &PciHeader\r | |
2656 | );\r | |
2657 | \r | |
2658 | ShellPrintHiiEx(\r | |
2659 | -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r | |
2660 | IoDev->SegmentNumber,\r | |
2661 | Bus,\r | |
2662 | Device,\r | |
2663 | Func\r | |
2664 | );\r | |
2665 | \r | |
2666 | PciPrintClassCode (PciHeader.ClassCode, FALSE);\r | |
2667 | ShellPrintHiiEx(\r | |
2668 | -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r | |
2669 | PciHeader.VendorId,\r | |
2670 | PciHeader.DeviceId,\r | |
2671 | PciHeader.ClassCode[0]\r | |
2672 | );\r | |
2673 | \r | |
2674 | ScreenCount += 2;\r | |
2675 | if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r | |
2676 | //\r | |
2677 | // If ScreenSize == 0 we have the console redirected so don't\r | |
2678 | // block updates\r | |
2679 | //\r | |
2680 | ScreenCount = 0;\r | |
2681 | }\r | |
2682 | //\r | |
2683 | // If this is not a multi-function device, we can leave the loop\r | |
2684 | // to deal with the next device.\r | |
2685 | //\r | |
2686 | if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r | |
2687 | break;\r | |
2688 | }\r | |
2689 | }\r | |
2690 | }\r | |
2691 | }\r | |
2692 | }\r | |
2693 | //\r | |
2694 | // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r | |
2695 | // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r | |
2696 | // devices on all bus, we can leave loop.\r | |
2697 | //\r | |
2698 | if (Descriptors == NULL) {\r | |
2699 | break;\r | |
2700 | }\r | |
2701 | }\r | |
2702 | }\r | |
2703 | \r | |
2704 | Status = EFI_SUCCESS;\r | |
2705 | goto Done;\r | |
2706 | }\r | |
2707 | \r | |
5d73d92f | 2708 | ExplainData = FALSE;\r |
2709 | Segment = 0;\r | |
2710 | Bus = 0;\r | |
2711 | Device = 0;\r | |
2712 | Func = 0;\r | |
33cc487c | 2713 | ExtendedCapability = 0xFFFF;\r |
5d73d92f | 2714 | if (ShellCommandLineGetFlag(Package, L"-i")) {\r |
2715 | ExplainData = TRUE;\r | |
2716 | }\r | |
2717 | \r | |
2718 | Temp = ShellCommandLineGetValue(Package, L"-s");\r | |
2719 | if (Temp != NULL) {\r | |
6855763e CP |
2720 | //\r |
2721 | // Input converted to hexadecimal number.\r | |
2722 | //\r | |
2723 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2724 | Segment = (UINT16) RetVal;\r | |
2725 | } else {\r | |
ba0014b9 | 2726 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
6855763e CP |
2727 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2728 | goto Done;\r | |
2729 | }\r | |
5d73d92f | 2730 | }\r |
2731 | \r | |
2732 | //\r | |
2733 | // The first Argument(except "-i") is assumed to be Bus number, second\r | |
2734 | // to be Device number, and third to be Func number.\r | |
2735 | //\r | |
2736 | Temp = ShellCommandLineGetRawValue(Package, 1);\r | |
2737 | if (Temp != NULL) {\r | |
6855763e CP |
2738 | //\r |
2739 | // Input converted to hexadecimal number.\r | |
2740 | //\r | |
2741 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2742 | Bus = (UINT16) RetVal;\r | |
2743 | } else {\r | |
ba0014b9 | 2744 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
6855763e CP |
2745 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2746 | goto Done;\r | |
2747 | }\r | |
2748 | \r | |
0c84a69f | 2749 | if (Bus > PCI_MAX_BUS) {\r |
ba0014b9 | 2750 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r |
5d73d92f | 2751 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2752 | goto Done;\r | |
2753 | }\r | |
2754 | }\r | |
2755 | Temp = ShellCommandLineGetRawValue(Package, 2);\r | |
2756 | if (Temp != NULL) {\r | |
6855763e CP |
2757 | //\r |
2758 | // Input converted to hexadecimal number.\r | |
2759 | //\r | |
2760 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2761 | Device = (UINT16) RetVal;\r | |
2762 | } else {\r | |
ba0014b9 | 2763 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
6855763e CP |
2764 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2765 | goto Done;\r | |
2766 | }\r | |
2767 | \r | |
0c84a69f | 2768 | if (Device > PCI_MAX_DEVICE){\r |
ba0014b9 | 2769 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r |
5d73d92f | 2770 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2771 | goto Done;\r | |
2772 | }\r | |
2773 | }\r | |
2774 | \r | |
2775 | Temp = ShellCommandLineGetRawValue(Package, 3);\r | |
2776 | if (Temp != NULL) {\r | |
6855763e CP |
2777 | //\r |
2778 | // Input converted to hexadecimal number.\r | |
2779 | //\r | |
2780 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
2781 | Func = (UINT16) RetVal;\r | |
2782 | } else {\r | |
ba0014b9 | 2783 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
6855763e CP |
2784 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2785 | goto Done;\r | |
2786 | }\r | |
2787 | \r | |
0c84a69f | 2788 | if (Func > PCI_MAX_FUNC){\r |
ba0014b9 | 2789 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r |
5d73d92f | 2790 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2791 | goto Done;\r | |
2792 | }\r | |
2793 | }\r | |
2794 | \r | |
31d7be01 RN |
2795 | Temp = ShellCommandLineGetValue (Package, L"-ec");\r |
2796 | if (Temp != NULL) {\r | |
2797 | //\r | |
2798 | // Input converted to hexadecimal number.\r | |
2799 | //\r | |
2800 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
33cc487c | 2801 | ExtendedCapability = (UINT16) RetVal;\r |
31d7be01 | 2802 | } else {\r |
ba0014b9 | 2803 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
31d7be01 RN |
2804 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2805 | goto Done;\r | |
2806 | }\r | |
2807 | }\r | |
2808 | \r | |
5d73d92f | 2809 | //\r |
2810 | // Find the protocol interface who's in charge of current segment, and its\r | |
2811 | // bus range covers the current bus\r | |
2812 | //\r | |
2813 | Status = PciFindProtocolInterface (\r | |
2814 | HandleBuf,\r | |
2815 | HandleCount,\r | |
2816 | Segment,\r | |
2817 | Bus,\r | |
2818 | &IoDev\r | |
2819 | );\r | |
2820 | \r | |
2821 | if (EFI_ERROR (Status)) {\r | |
2822 | ShellPrintHiiEx(\r | |
ba0014b9 | 2823 | -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci",\r |
5d73d92f | 2824 | Segment,\r |
2825 | Bus\r | |
2826 | );\r | |
2827 | ShellStatus = SHELL_NOT_FOUND;\r | |
2828 | goto Done;\r | |
2829 | }\r | |
2830 | \r | |
0c84a69f | 2831 | Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r |
5d73d92f | 2832 | Status = IoDev->Pci.Read (\r |
2833 | IoDev,\r | |
2834 | EfiPciWidthUint8,\r | |
2835 | Address,\r | |
2836 | sizeof (ConfigSpace),\r | |
2837 | &ConfigSpace\r | |
2838 | );\r | |
2839 | \r | |
2840 | if (EFI_ERROR (Status)) {\r | |
ba0014b9 | 2841 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2842 | ShellStatus = SHELL_ACCESS_DENIED;\r |
2843 | goto Done;\r | |
2844 | }\r | |
2845 | \r | |
2846 | mConfigSpace = &ConfigSpace;\r | |
2847 | ShellPrintHiiEx(\r | |
2848 | -1,\r | |
2849 | -1,\r | |
2850 | NULL,\r | |
2851 | STRING_TOKEN (STR_PCI_INFO),\r | |
2852 | gShellDebug1HiiHandle,\r | |
2853 | Segment,\r | |
2854 | Bus,\r | |
2855 | Device,\r | |
2856 | Func,\r | |
2857 | Segment,\r | |
2858 | Bus,\r | |
2859 | Device,\r | |
2860 | Func\r | |
2861 | );\r | |
2862 | \r | |
2863 | //\r | |
2864 | // Dump standard header of configuration space\r | |
2865 | //\r | |
2866 | SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r | |
2867 | \r | |
a1d4bfcc | 2868 | DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r |
5d73d92f | 2869 | ShellPrintEx(-1,-1, L"\r\n");\r |
2870 | \r | |
2871 | //\r | |
2872 | // Dump device dependent Part of configuration space\r | |
2873 | //\r | |
a1d4bfcc | 2874 | DumpHex (\r |
5d73d92f | 2875 | 2,\r |
2876 | SizeOfHeader,\r | |
2877 | sizeof (ConfigSpace) - SizeOfHeader,\r | |
2878 | ConfigSpace.Data\r | |
2879 | );\r | |
2880 | \r | |
33cc487c | 2881 | ExtendedConfigSpace = NULL;\r |
f1894fa2 | 2882 | ExtendedConfigSize = 0;\r |
33cc487c RN |
2883 | PcieCapabilityPtr = LocatePciCapability (&ConfigSpace, EFI_PCI_CAPABILITY_ID_PCIEXP);\r |
2884 | if (PcieCapabilityPtr != 0) {\r | |
2885 | ExtendedConfigSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r | |
2886 | ExtendedConfigSpace = AllocatePool (ExtendedConfigSize);\r | |
2887 | if (ExtendedConfigSpace != NULL) {\r | |
2888 | Status = IoDev->Pci.Read (\r | |
2889 | IoDev,\r | |
2890 | EfiPciWidthUint32,\r | |
2891 | EFI_PCI_ADDRESS (Bus, Device, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET),\r | |
2892 | ExtendedConfigSize / sizeof (UINT32),\r | |
2893 | ExtendedConfigSpace\r | |
2894 | );\r | |
2895 | if (EFI_ERROR (Status)) {\r | |
2896 | SHELL_FREE_NON_NULL (ExtendedConfigSpace);\r | |
2897 | }\r | |
2898 | }\r | |
2899 | }\r | |
2900 | \r | |
2901 | if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r | |
2902 | //\r | |
2903 | // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r | |
2904 | //\r | |
2905 | ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r | |
2906 | \r | |
2907 | DumpHex (\r | |
2908 | 2,\r | |
2909 | EFI_PCIE_CAPABILITY_BASE_OFFSET,\r | |
2910 | ExtendedConfigSize,\r | |
2911 | ExtendedConfigSpace\r | |
2912 | );\r | |
2913 | }\r | |
2914 | \r | |
5d73d92f | 2915 | //\r |
2916 | // If "-i" appears in command line, interpret data in configuration space\r | |
2917 | //\r | |
2918 | if (ExplainData) {\r | |
33cc487c | 2919 | PciExplainPci (&ConfigSpace, Address, IoDev);\r |
f1894fa2 | 2920 | if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r |
33cc487c RN |
2921 | PciExplainPciExpress (\r |
2922 | (PCI_CAPABILITY_PCIEXP *) ((UINT8 *) &ConfigSpace + PcieCapabilityPtr),\r | |
2923 | ExtendedConfigSpace,\r | |
2924 | ExtendedCapability\r | |
2925 | );\r | |
2926 | }\r | |
5d73d92f | 2927 | }\r |
2928 | }\r | |
2929 | Done:\r | |
2930 | if (HandleBuf != NULL) {\r | |
2931 | FreePool (HandleBuf);\r | |
2932 | }\r | |
2933 | if (Package != NULL) {\r | |
2934 | ShellCommandLineFreeVarList (Package);\r | |
2935 | }\r | |
2936 | mConfigSpace = NULL;\r | |
2937 | return ShellStatus;\r | |
2938 | }\r | |
2939 | \r | |
a1d4bfcc | 2940 | /**\r |
5d73d92f | 2941 | This function finds out the protocol which is in charge of the given\r |
2942 | segment, and its bus range covers the current bus number. It lookes\r | |
2943 | each instances of RootBridgeIoProtocol handle, until the one meets the\r | |
2944 | criteria is found.\r | |
2945 | \r | |
a1d4bfcc | 2946 | @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r |
2947 | @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
2948 | @param[in] Segment Segment number of device we are dealing with.\r | |
2949 | @param[in] Bus Bus number of device we are dealing with.\r | |
2950 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
5d73d92f | 2951 | \r |
a1d4bfcc | 2952 | @retval EFI_SUCCESS The command completed successfully.\r |
2953 | @retval EFI_INVALID_PARAMETER Invalid parameter.\r | |
5d73d92f | 2954 | \r |
2955 | **/\r | |
a1d4bfcc | 2956 | EFI_STATUS\r |
2957 | PciFindProtocolInterface (\r | |
2958 | IN EFI_HANDLE *HandleBuf,\r | |
2959 | IN UINTN HandleCount,\r | |
2960 | IN UINT16 Segment,\r | |
2961 | IN UINT16 Bus,\r | |
2962 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r | |
2963 | )\r | |
5d73d92f | 2964 | {\r |
2965 | UINTN Index;\r | |
2966 | EFI_STATUS Status;\r | |
5d73d92f | 2967 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r |
2968 | UINT16 MinBus;\r | |
2969 | UINT16 MaxBus;\r | |
2970 | BOOLEAN IsEnd;\r | |
2971 | \r | |
5d73d92f | 2972 | //\r |
2973 | // Go through all handles, until the one meets the criteria is found\r | |
2974 | //\r | |
2975 | for (Index = 0; Index < HandleCount; Index++) {\r | |
2976 | Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r | |
2977 | if (EFI_ERROR (Status)) {\r | |
2978 | return Status;\r | |
2979 | }\r | |
2980 | //\r | |
2981 | // When Descriptors == NULL, the Configuration() is not implemented,\r | |
2982 | // so we only check the Segment number\r | |
2983 | //\r | |
2984 | if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r | |
2985 | return EFI_SUCCESS;\r | |
2986 | }\r | |
2987 | \r | |
2988 | if ((*IoDev)->SegmentNumber != Segment) {\r | |
2989 | continue;\r | |
2990 | }\r | |
2991 | \r | |
2992 | while (TRUE) {\r | |
2993 | Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r | |
2994 | if (EFI_ERROR (Status)) {\r | |
2995 | return Status;\r | |
2996 | }\r | |
2997 | \r | |
2998 | if (IsEnd) {\r | |
2999 | break;\r | |
3000 | }\r | |
3001 | \r | |
3002 | if (MinBus <= Bus && MaxBus >= Bus) {\r | |
2c46dd23 | 3003 | return EFI_SUCCESS;\r |
5d73d92f | 3004 | }\r |
3005 | }\r | |
3006 | }\r | |
3007 | \r | |
2c46dd23 | 3008 | return EFI_NOT_FOUND;\r |
5d73d92f | 3009 | }\r |
3010 | \r | |
a1d4bfcc | 3011 | /**\r |
3012 | This function gets the protocol interface from the given handle, and\r | |
3013 | obtains its address space descriptors.\r | |
3014 | \r | |
3015 | @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r | |
3016 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
3017 | @param[out] Descriptors Points to the address space descriptors.\r | |
3018 | \r | |
3019 | @retval EFI_SUCCESS The command completed successfully\r | |
3020 | **/\r | |
5d73d92f | 3021 | EFI_STATUS\r |
3022 | PciGetProtocolAndResource (\r | |
3023 | IN EFI_HANDLE Handle,\r | |
3024 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r | |
3025 | OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r | |
3026 | )\r | |
5d73d92f | 3027 | {\r |
3028 | EFI_STATUS Status;\r | |
3029 | \r | |
3030 | //\r | |
3031 | // Get inferface from protocol\r | |
3032 | //\r | |
3033 | Status = gBS->HandleProtocol (\r | |
3034 | Handle,\r | |
3035 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
3036 | (VOID**)IoDev\r | |
3037 | );\r | |
3038 | \r | |
3039 | if (EFI_ERROR (Status)) {\r | |
3040 | return Status;\r | |
3041 | }\r | |
3042 | //\r | |
3043 | // Call Configuration() to get address space descriptors\r | |
3044 | //\r | |
3045 | Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r | |
3046 | if (Status == EFI_UNSUPPORTED) {\r | |
3047 | *Descriptors = NULL;\r | |
3048 | return EFI_SUCCESS;\r | |
3049 | \r | |
3050 | } else {\r | |
3051 | return Status;\r | |
3052 | }\r | |
3053 | }\r | |
3054 | \r | |
a1d4bfcc | 3055 | /**\r |
3056 | This function get the next bus range of given address space descriptors.\r | |
3057 | It also moves the pointer backward a node, to get prepared to be called\r | |
3058 | again.\r | |
3059 | \r | |
4ff7e37b ED |
3060 | @param[in, out] Descriptors Points to current position of a serial of address space\r |
3061 | descriptors.\r | |
3062 | @param[out] MinBus The lower range of bus number.\r | |
3063 | @param[out] MaxBus The upper range of bus number.\r | |
3064 | @param[out] IsEnd Meet end of the serial of descriptors.\r | |
a1d4bfcc | 3065 | \r |
3066 | @retval EFI_SUCCESS The command completed successfully.\r | |
3067 | **/\r | |
5d73d92f | 3068 | EFI_STATUS\r |
3069 | PciGetNextBusRange (\r | |
3070 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r | |
3071 | OUT UINT16 *MinBus,\r | |
3072 | OUT UINT16 *MaxBus,\r | |
3073 | OUT BOOLEAN *IsEnd\r | |
3074 | )\r | |
5d73d92f | 3075 | {\r |
3076 | *IsEnd = FALSE;\r | |
3077 | \r | |
3078 | //\r | |
3079 | // When *Descriptors is NULL, Configuration() is not implemented, so assume\r | |
3080 | // range is 0~PCI_MAX_BUS\r | |
3081 | //\r | |
3082 | if ((*Descriptors) == NULL) {\r | |
3083 | *MinBus = 0;\r | |
3084 | *MaxBus = PCI_MAX_BUS;\r | |
3085 | return EFI_SUCCESS;\r | |
3086 | }\r | |
3087 | //\r | |
3088 | // *Descriptors points to one or more address space descriptors, which\r | |
3089 | // ends with a end tagged descriptor. Examine each of the descriptors,\r | |
3090 | // if a bus typed one is found and its bus range covers bus, this handle\r | |
3091 | // is the handle we are looking for.\r | |
3092 | //\r | |
5d73d92f | 3093 | \r |
3094 | while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r | |
3095 | if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r | |
3096 | *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r | |
3097 | *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r | |
3098 | (*Descriptors)++;\r | |
3737ac2b | 3099 | return (EFI_SUCCESS);\r |
5d73d92f | 3100 | }\r |
3101 | \r | |
3102 | (*Descriptors)++;\r | |
3103 | }\r | |
3104 | \r | |
3737ac2b | 3105 | if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r |
3106 | *IsEnd = TRUE;\r | |
3107 | }\r | |
3108 | \r | |
5d73d92f | 3109 | return EFI_SUCCESS;\r |
3110 | }\r | |
3111 | \r | |
a1d4bfcc | 3112 | /**\r |
5d73d92f | 3113 | Explain the data in PCI configuration space. The part which is common for\r |
3114 | PCI device and bridge is interpreted in this function. It calls other\r | |
3115 | functions to interpret data unique for device or bridge.\r | |
3116 | \r | |
a1d4bfcc | 3117 | @param[in] ConfigSpace Data in PCI configuration space.\r |
3118 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3119 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
5d73d92f | 3120 | **/\r |
33cc487c RN |
3121 | VOID\r |
3122 | PciExplainPci (\r | |
a1d4bfcc | 3123 | IN PCI_CONFIG_SPACE *ConfigSpace,\r |
3124 | IN UINT64 Address,\r | |
33cc487c | 3125 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r |
a1d4bfcc | 3126 | )\r |
5d73d92f | 3127 | {\r |
0c84a69f RN |
3128 | PCI_DEVICE_INDEPENDENT_REGION *Common;\r |
3129 | PCI_HEADER_TYPE HeaderType;\r | |
5d73d92f | 3130 | \r |
3131 | Common = &(ConfigSpace->Common);\r | |
3132 | \r | |
c37e0f16 | 3133 | ShellPrintEx (-1, -1, L"\r\n");\r |
5d73d92f | 3134 | \r |
3135 | //\r | |
3136 | // Print Vendor Id and Device Id\r | |
3137 | //\r | |
3138 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r | |
3139 | INDEX_OF (&(Common->VendorId)),\r | |
3140 | Common->VendorId,\r | |
3141 | INDEX_OF (&(Common->DeviceId)),\r | |
3142 | Common->DeviceId\r | |
3143 | );\r | |
3144 | \r | |
3145 | //\r | |
3146 | // Print register Command\r | |
3147 | //\r | |
3148 | PciExplainCommand (&(Common->Command));\r | |
3149 | \r | |
3150 | //\r | |
3151 | // Print register Status\r | |
3152 | //\r | |
3153 | PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r | |
3154 | \r | |
3155 | //\r | |
3156 | // Print register Revision ID\r | |
3157 | //\r | |
14b5e3fd | 3158 | ShellPrintEx(-1, -1, L"\r\n");\r |
5d73d92f | 3159 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r |
0c84a69f RN |
3160 | INDEX_OF (&(Common->RevisionID)),\r |
3161 | Common->RevisionID\r | |
5d73d92f | 3162 | );\r |
3163 | \r | |
3164 | //\r | |
3165 | // Print register BIST\r | |
3166 | //\r | |
0c84a69f RN |
3167 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));\r |
3168 | if ((Common->BIST & BIT7) != 0) {\r | |
3169 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);\r | |
5d73d92f | 3170 | } else {\r |
3171 | ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r | |
3172 | }\r | |
3173 | //\r | |
3174 | // Print register Cache Line Size\r | |
3175 | //\r | |
3176 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3177 | STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r | |
3178 | gShellDebug1HiiHandle,\r | |
3179 | INDEX_OF (&(Common->CacheLineSize)),\r | |
3180 | Common->CacheLineSize\r | |
3181 | );\r | |
3182 | \r | |
3183 | //\r | |
3184 | // Print register Latency Timer\r | |
3185 | //\r | |
3186 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3187 | STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r | |
3188 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3189 | INDEX_OF (&(Common->LatencyTimer)),\r |
3190 | Common->LatencyTimer\r | |
5d73d92f | 3191 | );\r |
3192 | \r | |
3193 | //\r | |
3194 | // Print register Header Type\r | |
3195 | //\r | |
3196 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3197 | STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r | |
3198 | gShellDebug1HiiHandle,\r | |
3199 | INDEX_OF (&(Common->HeaderType)),\r | |
3200 | Common->HeaderType\r | |
3201 | );\r | |
3202 | \r | |
0c84a69f | 3203 | if ((Common->HeaderType & BIT7) != 0) {\r |
5d73d92f | 3204 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r |
3205 | \r | |
3206 | } else {\r | |
3207 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r | |
3208 | }\r | |
3209 | \r | |
3210 | HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r | |
3211 | switch (HeaderType) {\r | |
3212 | case PciDevice:\r | |
3213 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r | |
3214 | break;\r | |
3215 | \r | |
3216 | case PciP2pBridge:\r | |
3217 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r | |
3218 | break;\r | |
3219 | \r | |
3220 | case PciCardBusBridge:\r | |
3221 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r | |
3222 | break;\r | |
3223 | \r | |
3224 | default:\r | |
3225 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r | |
3226 | HeaderType = PciUndefined;\r | |
3227 | }\r | |
3228 | \r | |
3229 | //\r | |
3230 | // Print register Class Code\r | |
3231 | //\r | |
3232 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r | |
3233 | PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r | |
c37e0f16 | 3234 | ShellPrintEx (-1, -1, L"\r\n");\r |
5d73d92f | 3235 | }\r |
3236 | \r | |
a1d4bfcc | 3237 | /**\r |
3238 | Explain the device specific part of data in PCI configuration space.\r | |
3239 | \r | |
3240 | @param[in] Device Data in PCI configuration space.\r | |
3241 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3242 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3243 | \r | |
3244 | @retval EFI_SUCCESS The command completed successfully.\r | |
3245 | **/\r | |
5d73d92f | 3246 | EFI_STATUS\r |
3247 | PciExplainDeviceData (\r | |
0c84a69f | 3248 | IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r |
5d73d92f | 3249 | IN UINT64 Address,\r |
3250 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
3251 | )\r | |
5d73d92f | 3252 | {\r |
3253 | UINTN Index;\r | |
3254 | BOOLEAN BarExist;\r | |
3255 | EFI_STATUS Status;\r | |
3256 | UINTN BarCount;\r | |
3257 | \r | |
3258 | //\r | |
3259 | // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r | |
3260 | // exist. If these no Bar for this function, print "none", otherwise\r | |
3261 | // list detail information about this Bar.\r | |
3262 | //\r | |
3263 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r | |
3264 | \r | |
3265 | BarExist = FALSE;\r | |
3266 | BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r | |
3267 | for (Index = 0; Index < BarCount; Index++) {\r | |
3268 | if (Device->Bar[Index] == 0) {\r | |
3269 | continue;\r | |
3270 | }\r | |
3271 | \r | |
3272 | if (!BarExist) {\r | |
3273 | BarExist = TRUE;\r | |
3274 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3275 | ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r |
5d73d92f | 3276 | }\r |
3277 | \r | |
3278 | Status = PciExplainBar (\r | |
3279 | &(Device->Bar[Index]),\r | |
3280 | &(mConfigSpace->Common.Command),\r | |
3281 | Address,\r | |
3282 | IoDev,\r | |
3283 | &Index\r | |
3284 | );\r | |
3285 | \r | |
3286 | if (EFI_ERROR (Status)) {\r | |
3287 | break;\r | |
3288 | }\r | |
3289 | }\r | |
3290 | \r | |
3291 | if (!BarExist) {\r | |
3292 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r | |
3293 | \r | |
3294 | } else {\r | |
c37e0f16 | 3295 | ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r |
5d73d92f | 3296 | }\r |
3297 | \r | |
3298 | //\r | |
3299 | // Print register Expansion ROM Base Address\r | |
3300 | //\r | |
0c84a69f RN |
3301 | if ((Device->ExpansionRomBar & BIT0) == 0) {\r |
3302 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ExpansionRomBar)));\r | |
5d73d92f | 3303 | \r |
3304 | } else {\r | |
3305 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3306 | STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r | |
3307 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3308 | INDEX_OF (&(Device->ExpansionRomBar)),\r |
3309 | Device->ExpansionRomBar\r | |
5d73d92f | 3310 | );\r |
3311 | }\r | |
3312 | //\r | |
3313 | // Print register Cardbus CIS ptr\r | |
3314 | //\r | |
3315 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3316 | STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r | |
3317 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3318 | INDEX_OF (&(Device->CISPtr)),\r |
3319 | Device->CISPtr\r | |
5d73d92f | 3320 | );\r |
3321 | \r | |
3322 | //\r | |
3323 | // Print register Sub-vendor ID and subsystem ID\r | |
3324 | //\r | |
3325 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3326 | STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r | |
3327 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3328 | INDEX_OF (&(Device->SubsystemVendorID)),\r |
3329 | Device->SubsystemVendorID\r | |
5d73d92f | 3330 | );\r |
3331 | \r | |
3332 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3333 | STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r | |
3334 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3335 | INDEX_OF (&(Device->SubsystemID)),\r |
3336 | Device->SubsystemID\r | |
5d73d92f | 3337 | );\r |
3338 | \r | |
3339 | //\r | |
3340 | // Print register Capabilities Ptr\r | |
3341 | //\r | |
3342 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3343 | STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r | |
3344 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3345 | INDEX_OF (&(Device->CapabilityPtr)),\r |
3346 | Device->CapabilityPtr\r | |
5d73d92f | 3347 | );\r |
3348 | \r | |
3349 | //\r | |
3350 | // Print register Interrupt Line and interrupt pin\r | |
3351 | //\r | |
3352 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3353 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r | |
3354 | gShellDebug1HiiHandle,\r | |
3355 | INDEX_OF (&(Device->InterruptLine)),\r | |
3356 | Device->InterruptLine\r | |
3357 | );\r | |
3358 | \r | |
3359 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3360 | STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r | |
3361 | gShellDebug1HiiHandle,\r | |
3362 | INDEX_OF (&(Device->InterruptPin)),\r | |
3363 | Device->InterruptPin\r | |
3364 | );\r | |
3365 | \r | |
3366 | //\r | |
3367 | // Print register Min_Gnt and Max_Lat\r | |
3368 | //\r | |
3369 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3370 | STRING_TOKEN (STR_PCI2_MIN_GNT),\r | |
3371 | gShellDebug1HiiHandle,\r | |
3372 | INDEX_OF (&(Device->MinGnt)),\r | |
3373 | Device->MinGnt\r | |
3374 | );\r | |
3375 | \r | |
3376 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3377 | STRING_TOKEN (STR_PCI2_MAX_LAT),\r | |
3378 | gShellDebug1HiiHandle,\r | |
3379 | INDEX_OF (&(Device->MaxLat)),\r | |
3380 | Device->MaxLat\r | |
3381 | );\r | |
3382 | \r | |
3383 | return EFI_SUCCESS;\r | |
3384 | }\r | |
3385 | \r | |
a1d4bfcc | 3386 | /**\r |
3387 | Explain the bridge specific part of data in PCI configuration space.\r | |
3388 | \r | |
3389 | @param[in] Bridge Bridge specific data region in PCI configuration space.\r | |
3390 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3391 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3392 | \r | |
3393 | @retval EFI_SUCCESS The command completed successfully.\r | |
3394 | **/\r | |
5d73d92f | 3395 | EFI_STATUS\r |
3396 | PciExplainBridgeData (\r | |
0c84a69f | 3397 | IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r |
5d73d92f | 3398 | IN UINT64 Address,\r |
3399 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
3400 | )\r | |
5d73d92f | 3401 | {\r |
3402 | UINTN Index;\r | |
3403 | BOOLEAN BarExist;\r | |
3404 | UINTN BarCount;\r | |
3405 | UINT32 IoAddress32;\r | |
3406 | EFI_STATUS Status;\r | |
3407 | \r | |
3408 | //\r | |
3409 | // Print Base Address Registers. When Bar = 0, this Bar does not\r | |
3410 | // exist. If these no Bar for this function, print "none", otherwise\r | |
3411 | // list detail information about this Bar.\r | |
3412 | //\r | |
3413 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r | |
3414 | \r | |
3415 | BarExist = FALSE;\r | |
3416 | BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r | |
3417 | \r | |
3418 | for (Index = 0; Index < BarCount; Index++) {\r | |
3419 | if (Bridge->Bar[Index] == 0) {\r | |
3420 | continue;\r | |
3421 | }\r | |
3422 | \r | |
3423 | if (!BarExist) {\r | |
3424 | BarExist = TRUE;\r | |
3425 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3426 | ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r |
5d73d92f | 3427 | }\r |
3428 | \r | |
3429 | Status = PciExplainBar (\r | |
3430 | &(Bridge->Bar[Index]),\r | |
3431 | &(mConfigSpace->Common.Command),\r | |
3432 | Address,\r | |
3433 | IoDev,\r | |
3434 | &Index\r | |
3435 | );\r | |
3436 | \r | |
3437 | if (EFI_ERROR (Status)) {\r | |
3438 | break;\r | |
3439 | }\r | |
3440 | }\r | |
3441 | \r | |
3442 | if (!BarExist) {\r | |
3443 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r | |
3444 | } else {\r | |
c37e0f16 | 3445 | ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r |
5d73d92f | 3446 | }\r |
3447 | \r | |
3448 | //\r | |
3449 | // Expansion register ROM Base Address\r | |
3450 | //\r | |
0c84a69f RN |
3451 | if ((Bridge->ExpansionRomBAR & BIT0) == 0) {\r |
3452 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ExpansionRomBAR)));\r | |
5d73d92f | 3453 | \r |
3454 | } else {\r | |
3455 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3456 | STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r | |
3457 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3458 | INDEX_OF (&(Bridge->ExpansionRomBAR)),\r |
3459 | Bridge->ExpansionRomBAR\r | |
5d73d92f | 3460 | );\r |
3461 | }\r | |
3462 | //\r | |
3463 | // Print Bus Numbers(Primary, Secondary, and Subordinate\r | |
3464 | //\r | |
3465 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3466 | STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r | |
3467 | gShellDebug1HiiHandle,\r | |
3468 | INDEX_OF (&(Bridge->PrimaryBus)),\r | |
3469 | INDEX_OF (&(Bridge->SecondaryBus)),\r | |
3470 | INDEX_OF (&(Bridge->SubordinateBus))\r | |
3471 | );\r | |
3472 | \r | |
c37e0f16 | 3473 | ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r |
5d73d92f | 3474 | \r |
3475 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r | |
3476 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r | |
3477 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r | |
3478 | \r | |
3479 | //\r | |
3480 | // Print register Secondary Latency Timer\r | |
3481 | //\r | |
3482 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3483 | STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r | |
3484 | gShellDebug1HiiHandle,\r | |
3485 | INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r | |
3486 | Bridge->SecondaryLatencyTimer\r | |
3487 | );\r | |
3488 | \r | |
3489 | //\r | |
3490 | // Print register Secondary Status\r | |
3491 | //\r | |
3492 | PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r | |
3493 | \r | |
3494 | //\r | |
3495 | // Print I/O and memory ranges this bridge forwards. There are 3 resource\r | |
3496 | // types: I/O, memory, and pre-fetchable memory. For each resource type,\r | |
3497 | // base and limit address are listed.\r | |
3498 | //\r | |
3499 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3500 | ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r |
5d73d92f | 3501 | \r |
3502 | //\r | |
3503 | // IO Base & Limit\r | |
3504 | //\r | |
0c84a69f | 3505 | IoAddress32 = (Bridge->IoBaseUpper16 << 16 | Bridge->IoBase << 8);\r |
5d73d92f | 3506 | IoAddress32 &= 0xfffff000;\r |
3507 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3508 | STRING_TOKEN (STR_PCI2_TWO_VARS),\r | |
3509 | gShellDebug1HiiHandle,\r | |
3510 | INDEX_OF (&(Bridge->IoBase)),\r | |
3511 | IoAddress32\r | |
3512 | );\r | |
3513 | \r | |
0c84a69f | 3514 | IoAddress32 = (Bridge->IoLimitUpper16 << 16 | Bridge->IoLimit << 8);\r |
5d73d92f | 3515 | IoAddress32 |= 0x00000fff;\r |
3516 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r | |
3517 | \r | |
3518 | //\r | |
3519 | // Memory Base & Limit\r | |
3520 | //\r | |
3521 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3522 | STRING_TOKEN (STR_PCI2_MEMORY),\r | |
3523 | gShellDebug1HiiHandle,\r | |
3524 | INDEX_OF (&(Bridge->MemoryBase)),\r | |
3525 | (Bridge->MemoryBase << 16) & 0xfff00000\r | |
3526 | );\r | |
3527 | \r | |
3528 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3529 | STRING_TOKEN (STR_PCI2_ONE_VAR),\r | |
3530 | gShellDebug1HiiHandle,\r | |
3531 | (Bridge->MemoryLimit << 16) | 0x000fffff\r | |
3532 | );\r | |
3533 | \r | |
3534 | //\r | |
3535 | // Pre-fetch-able Memory Base & Limit\r | |
3536 | //\r | |
3537 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3538 | STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r | |
3539 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3540 | INDEX_OF (&(Bridge->PrefetchableMemoryBase)),\r |
3541 | Bridge->PrefetchableBaseUpper32,\r | |
3542 | (Bridge->PrefetchableMemoryBase << 16) & 0xfff00000\r | |
5d73d92f | 3543 | );\r |
3544 | \r | |
3545 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3546 | STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r | |
3547 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3548 | Bridge->PrefetchableLimitUpper32,\r |
3549 | (Bridge->PrefetchableMemoryLimit << 16) | 0x000fffff\r | |
5d73d92f | 3550 | );\r |
3551 | \r | |
3552 | //\r | |
3553 | // Print register Capabilities Pointer\r | |
3554 | //\r | |
3555 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3556 | STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r | |
3557 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3558 | INDEX_OF (&(Bridge->CapabilityPtr)),\r |
3559 | Bridge->CapabilityPtr\r | |
5d73d92f | 3560 | );\r |
3561 | \r | |
3562 | //\r | |
3563 | // Print register Bridge Control\r | |
3564 | //\r | |
3565 | PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r | |
3566 | \r | |
3567 | //\r | |
3568 | // Print register Interrupt Line & PIN\r | |
3569 | //\r | |
3570 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3571 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r | |
3572 | gShellDebug1HiiHandle,\r | |
3573 | INDEX_OF (&(Bridge->InterruptLine)),\r | |
3574 | Bridge->InterruptLine\r | |
3575 | );\r | |
3576 | \r | |
3577 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3578 | STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r | |
3579 | gShellDebug1HiiHandle,\r | |
3580 | INDEX_OF (&(Bridge->InterruptPin)),\r | |
3581 | Bridge->InterruptPin\r | |
3582 | );\r | |
3583 | \r | |
3584 | return EFI_SUCCESS;\r | |
3585 | }\r | |
3586 | \r | |
a1d4bfcc | 3587 | /**\r |
3588 | Explain the Base Address Register(Bar) in PCI configuration space.\r | |
3589 | \r | |
4ff7e37b ED |
3590 | @param[in] Bar Points to the Base Address Register intended to interpret.\r |
3591 | @param[in] Command Points to the register Command.\r | |
3592 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3593 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3594 | @param[in, out] Index The Index.\r | |
a1d4bfcc | 3595 | \r |
3596 | @retval EFI_SUCCESS The command completed successfully.\r | |
3597 | **/\r | |
5d73d92f | 3598 | EFI_STATUS\r |
3599 | PciExplainBar (\r | |
3600 | IN UINT32 *Bar,\r | |
3601 | IN UINT16 *Command,\r | |
3602 | IN UINT64 Address,\r | |
3603 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
3604 | IN OUT UINTN *Index\r | |
3605 | )\r | |
5d73d92f | 3606 | {\r |
3607 | UINT16 OldCommand;\r | |
3608 | UINT16 NewCommand;\r | |
3609 | UINT64 Bar64;\r | |
3610 | UINT32 OldBar32;\r | |
3611 | UINT32 NewBar32;\r | |
3612 | UINT64 OldBar64;\r | |
3613 | UINT64 NewBar64;\r | |
3614 | BOOLEAN IsMem;\r | |
3615 | BOOLEAN IsBar32;\r | |
3616 | UINT64 RegAddress;\r | |
3617 | \r | |
3618 | IsBar32 = TRUE;\r | |
3619 | Bar64 = 0;\r | |
3620 | NewBar32 = 0;\r | |
3621 | NewBar64 = 0;\r | |
3622 | \r | |
3623 | //\r | |
3624 | // According the bar type, list detail about this bar, for example: 32 or\r | |
3625 | // 64 bits; pre-fetchable or not.\r | |
3626 | //\r | |
0c84a69f | 3627 | if ((*Bar & BIT0) == 0) {\r |
5d73d92f | 3628 | //\r |
3629 | // This bar is of memory type\r | |
3630 | //\r | |
3631 | IsMem = TRUE;\r | |
3632 | \r | |
0c84a69f | 3633 | if ((*Bar & BIT1) == 0 && (*Bar & BIT2) == 0) {\r |
5d73d92f | 3634 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r |
3635 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r | |
3636 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r | |
3637 | \r | |
0c84a69f | 3638 | } else if ((*Bar & BIT1) == 0 && (*Bar & BIT2) != 0) {\r |
5d73d92f | 3639 | Bar64 = 0x0;\r |
3640 | CopyMem (&Bar64, Bar, sizeof (UINT64));\r | |
46cb4043 | 3641 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r |
2b578de0 | 3642 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r |
5d73d92f | 3643 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r |
3644 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r | |
3645 | IsBar32 = FALSE;\r | |
3646 | *Index += 1;\r | |
3647 | \r | |
3648 | } else {\r | |
3649 | //\r | |
3650 | // Reserved\r | |
3651 | //\r | |
3652 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r | |
3653 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r | |
3654 | }\r | |
3655 | \r | |
0c84a69f | 3656 | if ((*Bar & BIT3) == 0) {\r |
5d73d92f | 3657 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r |
3658 | \r | |
3659 | } else {\r | |
3660 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r | |
3661 | }\r | |
3662 | \r | |
3663 | } else {\r | |
3664 | //\r | |
3665 | // This bar is of io type\r | |
3666 | //\r | |
3667 | IsMem = FALSE;\r | |
3668 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r | |
c37e0f16 | 3669 | ShellPrintEx (-1, -1, L"I/O ");\r |
5d73d92f | 3670 | }\r |
3671 | \r | |
3672 | //\r | |
3673 | // Get BAR length(or the amount of resource this bar demands for). To get\r | |
3674 | // Bar length, first we should temporarily disable I/O and memory access\r | |
3675 | // of this function(by set bits in the register Command), then write all\r | |
3676 | // "1"s to this bar. The bar value read back is the amount of resource\r | |
3677 | // this bar demands for.\r | |
3678 | //\r | |
3679 | //\r | |
3680 | // Disable io & mem access\r | |
3681 | //\r | |
3682 | OldCommand = *Command;\r | |
3683 | NewCommand = (UINT16) (OldCommand & 0xfffc);\r | |
3684 | RegAddress = Address | INDEX_OF (Command);\r | |
3685 | IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r | |
3686 | \r | |
3687 | RegAddress = Address | INDEX_OF (Bar);\r | |
3688 | \r | |
3689 | //\r | |
3690 | // Read after write the BAR to get the size\r | |
3691 | //\r | |
3692 | if (IsBar32) {\r | |
3693 | OldBar32 = *Bar;\r | |
3694 | NewBar32 = 0xffffffff;\r | |
3695 | \r | |
3696 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r | |
3697 | IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r | |
3698 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r | |
3699 | \r | |
3700 | if (IsMem) {\r | |
3701 | NewBar32 = NewBar32 & 0xfffffff0;\r | |
3702 | NewBar32 = (~NewBar32) + 1;\r | |
3703 | \r | |
3704 | } else {\r | |
3705 | NewBar32 = NewBar32 & 0xfffffffc;\r | |
3706 | NewBar32 = (~NewBar32) + 1;\r | |
3707 | NewBar32 = NewBar32 & 0x0000ffff;\r | |
3708 | }\r | |
3709 | } else {\r | |
3710 | \r | |
3711 | OldBar64 = 0x0;\r | |
3712 | CopyMem (&OldBar64, Bar, sizeof (UINT64));\r | |
2b578de0 | 3713 | NewBar64 = 0xffffffffffffffffULL;\r |
5d73d92f | 3714 | \r |
3715 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r | |
3716 | IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r | |
3717 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r | |
3718 | \r | |
3719 | if (IsMem) {\r | |
2b578de0 | 3720 | NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r |
5d73d92f | 3721 | NewBar64 = (~NewBar64) + 1;\r |
3722 | \r | |
3723 | } else {\r | |
2b578de0 | 3724 | NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r |
5d73d92f | 3725 | NewBar64 = (~NewBar64) + 1;\r |
3726 | NewBar64 = NewBar64 & 0x000000000000ffff;\r | |
3727 | }\r | |
3728 | }\r | |
3729 | //\r | |
3730 | // Enable io & mem access\r | |
3731 | //\r | |
3732 | RegAddress = Address | INDEX_OF (Command);\r | |
3733 | IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r | |
3734 | \r | |
3735 | if (IsMem) {\r | |
3736 | if (IsBar32) {\r | |
3737 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r | |
3738 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r | |
3739 | \r | |
3740 | } else {\r | |
46cb4043 | 3741 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r |
5d73d92f | 3742 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r |
c37e0f16 | 3743 | ShellPrintEx (-1, -1, L" ");\r |
5d73d92f | 3744 | ShellPrintHiiEx(-1, -1, NULL,\r |
3745 | STRING_TOKEN (STR_PCI2_RSHIFT),\r | |
3746 | gShellDebug1HiiHandle,\r | |
46cb4043 | 3747 | (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r |
5d73d92f | 3748 | );\r |
2b578de0 | 3749 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r |
5d73d92f | 3750 | \r |
3751 | }\r | |
3752 | } else {\r | |
3753 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r | |
3754 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r | |
3755 | }\r | |
3756 | \r | |
3757 | return EFI_SUCCESS;\r | |
3758 | }\r | |
3759 | \r | |
a1d4bfcc | 3760 | /**\r |
3761 | Explain the cardbus specific part of data in PCI configuration space.\r | |
3762 | \r | |
3763 | @param[in] CardBus CardBus specific region of PCI configuration space.\r | |
3764 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3765 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3766 | \r | |
3767 | @retval EFI_SUCCESS The command completed successfully.\r | |
3768 | **/\r | |
5d73d92f | 3769 | EFI_STATUS\r |
3770 | PciExplainCardBusData (\r | |
0c84a69f | 3771 | IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r |
5d73d92f | 3772 | IN UINT64 Address,\r |
3773 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
3774 | )\r | |
5d73d92f | 3775 | {\r |
3776 | BOOLEAN Io32Bit;\r | |
3777 | PCI_CARDBUS_DATA *CardBusData;\r | |
3778 | \r | |
3779 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3780 | STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r | |
3781 | gShellDebug1HiiHandle,\r | |
3782 | INDEX_OF (&(CardBus->CardBusSocketReg)),\r | |
3783 | CardBus->CardBusSocketReg\r | |
3784 | );\r | |
3785 | \r | |
3786 | //\r | |
3787 | // Print Secondary Status\r | |
3788 | //\r | |
3789 | PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r | |
3790 | \r | |
3791 | //\r | |
3792 | // Print Bus Numbers(Primary bus number, CardBus bus number, and\r | |
3793 | // Subordinate bus number\r | |
3794 | //\r | |
3795 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3796 | STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r | |
3797 | gShellDebug1HiiHandle,\r | |
3798 | INDEX_OF (&(CardBus->PciBusNumber)),\r | |
3799 | INDEX_OF (&(CardBus->CardBusBusNumber)),\r | |
3800 | INDEX_OF (&(CardBus->SubordinateBusNumber))\r | |
3801 | );\r | |
3802 | \r | |
c37e0f16 | 3803 | ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r |
5d73d92f | 3804 | \r |
3805 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r | |
3806 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r | |
3807 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r | |
3808 | \r | |
3809 | //\r | |
3810 | // Print CardBus Latency Timer\r | |
3811 | //\r | |
3812 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3813 | STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r | |
3814 | gShellDebug1HiiHandle,\r | |
3815 | INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r | |
3816 | CardBus->CardBusLatencyTimer\r | |
3817 | );\r | |
3818 | \r | |
3819 | //\r | |
3820 | // Print Memory/Io ranges this cardbus bridge forwards\r | |
3821 | //\r | |
3822 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r | |
c37e0f16 | 3823 | ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r |
5d73d92f | 3824 | \r |
3825 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3826 | STRING_TOKEN (STR_PCI2_MEM_3),\r | |
3827 | gShellDebug1HiiHandle,\r | |
3828 | INDEX_OF (&(CardBus->MemoryBase0)),\r | |
0c84a69f | 3829 | CardBus->BridgeControl & BIT8 ? L" Prefetchable" : L"Non-Prefetchable",\r |
5d73d92f | 3830 | CardBus->MemoryBase0 & 0xfffff000,\r |
3831 | CardBus->MemoryLimit0 | 0x00000fff\r | |
3832 | );\r | |
3833 | \r | |
3834 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3835 | STRING_TOKEN (STR_PCI2_MEM_3),\r | |
3836 | gShellDebug1HiiHandle,\r | |
3837 | INDEX_OF (&(CardBus->MemoryBase1)),\r | |
0c84a69f | 3838 | CardBus->BridgeControl & BIT9 ? L" Prefetchable" : L"Non-Prefetchable",\r |
5d73d92f | 3839 | CardBus->MemoryBase1 & 0xfffff000,\r |
3840 | CardBus->MemoryLimit1 | 0x00000fff\r | |
3841 | );\r | |
3842 | \r | |
0c84a69f | 3843 | Io32Bit = (BOOLEAN) (CardBus->IoBase0 & BIT0);\r |
5d73d92f | 3844 | ShellPrintHiiEx(-1, -1, NULL,\r |
3845 | STRING_TOKEN (STR_PCI2_IO_2),\r | |
3846 | gShellDebug1HiiHandle,\r | |
3847 | INDEX_OF (&(CardBus->IoBase0)),\r | |
3848 | Io32Bit ? L" 32 bit" : L" 16 bit",\r | |
3849 | CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r | |
d8f8021c | 3850 | (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r |
5d73d92f | 3851 | );\r |
3852 | \r | |
0c84a69f | 3853 | Io32Bit = (BOOLEAN) (CardBus->IoBase1 & BIT0);\r |
5d73d92f | 3854 | ShellPrintHiiEx(-1, -1, NULL,\r |
3855 | STRING_TOKEN (STR_PCI2_IO_2),\r | |
3856 | gShellDebug1HiiHandle,\r | |
3857 | INDEX_OF (&(CardBus->IoBase1)),\r | |
3858 | Io32Bit ? L" 32 bit" : L" 16 bit",\r | |
3859 | CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r | |
d8f8021c | 3860 | (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r |
5d73d92f | 3861 | );\r |
3862 | \r | |
3863 | //\r | |
3864 | // Print register Interrupt Line & PIN\r | |
3865 | //\r | |
3866 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3867 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r | |
3868 | gShellDebug1HiiHandle,\r | |
3869 | INDEX_OF (&(CardBus->InterruptLine)),\r | |
3870 | CardBus->InterruptLine,\r | |
3871 | INDEX_OF (&(CardBus->InterruptPin)),\r | |
3872 | CardBus->InterruptPin\r | |
3873 | );\r | |
3874 | \r | |
3875 | //\r | |
3876 | // Print register Bridge Control\r | |
3877 | //\r | |
3878 | PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r | |
3879 | \r | |
3880 | //\r | |
3881 | // Print some registers in data region of PCI configuration space for cardbus\r | |
3882 | // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r | |
3883 | // Address.\r | |
3884 | //\r | |
0c84a69f | 3885 | CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_CONTROL_REGISTER));\r |
5d73d92f | 3886 | \r |
3887 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3888 | STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r | |
3889 | gShellDebug1HiiHandle,\r | |
3890 | INDEX_OF (&(CardBusData->SubVendorId)),\r | |
3891 | CardBusData->SubVendorId,\r | |
3892 | INDEX_OF (&(CardBusData->SubSystemId)),\r | |
3893 | CardBusData->SubSystemId\r | |
3894 | );\r | |
3895 | \r | |
3896 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3897 | STRING_TOKEN (STR_PCI2_OPTIONAL),\r | |
3898 | gShellDebug1HiiHandle,\r | |
3899 | INDEX_OF (&(CardBusData->LegacyBase)),\r | |
3900 | CardBusData->LegacyBase\r | |
3901 | );\r | |
3902 | \r | |
3903 | return EFI_SUCCESS;\r | |
3904 | }\r | |
3905 | \r | |
a1d4bfcc | 3906 | /**\r |
3907 | Explain each meaningful bit of register Status. The definition of Status is\r | |
3908 | slightly different depending on the PCI header type.\r | |
3909 | \r | |
3910 | @param[in] Status Points to the content of register Status.\r | |
3911 | @param[in] MainStatus Indicates if this register is main status(not secondary\r | |
3912 | status).\r | |
3913 | @param[in] HeaderType Header type of this PCI device.\r | |
3914 | \r | |
3915 | @retval EFI_SUCCESS The command completed successfully.\r | |
3916 | **/\r | |
5d73d92f | 3917 | EFI_STATUS\r |
3918 | PciExplainStatus (\r | |
3919 | IN UINT16 *Status,\r | |
3920 | IN BOOLEAN MainStatus,\r | |
3921 | IN PCI_HEADER_TYPE HeaderType\r | |
3922 | )\r | |
5d73d92f | 3923 | {\r |
3924 | if (MainStatus) {\r | |
3925 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r | |
3926 | \r | |
3927 | } else {\r | |
3928 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r | |
3929 | }\r | |
3930 | \r | |
0c84a69f | 3931 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & BIT4) != 0);\r |
5d73d92f | 3932 | \r |
3933 | //\r | |
3934 | // Bit 5 is meaningless for CardBus Bridge\r | |
3935 | //\r | |
3936 | if (HeaderType == PciCardBusBridge) {\r | |
0c84a69f | 3937 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r |
5d73d92f | 3938 | \r |
3939 | } else {\r | |
0c84a69f | 3940 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r |
5d73d92f | 3941 | }\r |
3942 | \r | |
0c84a69f | 3943 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & BIT7) != 0);\r |
5d73d92f | 3944 | \r |
0c84a69f | 3945 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & BIT8) != 0);\r |
5d73d92f | 3946 | //\r |
3947 | // Bit 9 and bit 10 together decides the DEVSEL timing\r | |
3948 | //\r | |
3949 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r | |
0c84a69f | 3950 | if ((*Status & BIT9) == 0 && (*Status & BIT10) == 0) {\r |
5d73d92f | 3951 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r |
3952 | \r | |
0c84a69f | 3953 | } else if ((*Status & BIT9) != 0 && (*Status & BIT10) == 0) {\r |
5d73d92f | 3954 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r |
3955 | \r | |
0c84a69f | 3956 | } else if ((*Status & BIT9) == 0 && (*Status & BIT10) != 0) {\r |
5d73d92f | 3957 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r |
3958 | \r | |
3959 | } else {\r | |
3960 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r | |
3961 | }\r | |
3962 | \r | |
3963 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3964 | STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r | |
3965 | gShellDebug1HiiHandle,\r | |
0c84a69f | 3966 | (*Status & BIT11) != 0\r |
5d73d92f | 3967 | );\r |
3968 | \r | |
3969 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3970 | STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r | |
3971 | gShellDebug1HiiHandle,\r | |
0c84a69f | 3972 | (*Status & BIT12) != 0\r |
5d73d92f | 3973 | );\r |
3974 | \r | |
3975 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3976 | STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r | |
3977 | gShellDebug1HiiHandle,\r | |
0c84a69f | 3978 | (*Status & BIT13) != 0\r |
5d73d92f | 3979 | );\r |
3980 | \r | |
3981 | if (MainStatus) {\r | |
3982 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3983 | STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r | |
3984 | gShellDebug1HiiHandle,\r | |
0c84a69f | 3985 | (*Status & BIT14) != 0\r |
5d73d92f | 3986 | );\r |
3987 | \r | |
3988 | } else {\r | |
3989 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3990 | STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r | |
3991 | gShellDebug1HiiHandle,\r | |
0c84a69f | 3992 | (*Status & BIT14) != 0\r |
5d73d92f | 3993 | );\r |
3994 | }\r | |
3995 | \r | |
3996 | ShellPrintHiiEx(-1, -1, NULL,\r | |
3997 | STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r | |
3998 | gShellDebug1HiiHandle,\r | |
0c84a69f | 3999 | (*Status & BIT15) != 0\r |
5d73d92f | 4000 | );\r |
4001 | \r | |
4002 | return EFI_SUCCESS;\r | |
4003 | }\r | |
4004 | \r | |
a1d4bfcc | 4005 | /**\r |
5d73d92f | 4006 | Explain each meaningful bit of register Command.\r |
4007 | \r | |
a1d4bfcc | 4008 | @param[in] Command Points to the content of register Command.\r |
5d73d92f | 4009 | \r |
a1d4bfcc | 4010 | @retval EFI_SUCCESS The command completed successfully.\r |
5d73d92f | 4011 | **/\r |
a1d4bfcc | 4012 | EFI_STATUS\r |
4013 | PciExplainCommand (\r | |
4014 | IN UINT16 *Command\r | |
4015 | )\r | |
5d73d92f | 4016 | {\r |
4017 | //\r | |
4018 | // Print the binary value of register Command\r | |
4019 | //\r | |
4020 | ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r | |
4021 | \r | |
4022 | //\r | |
4023 | // Explain register Command bit by bit\r | |
4024 | //\r | |
4025 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4026 | STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r | |
4027 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4028 | (*Command & BIT0) != 0\r |
5d73d92f | 4029 | );\r |
4030 | \r | |
4031 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4032 | STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r | |
4033 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4034 | (*Command & BIT1) != 0\r |
5d73d92f | 4035 | );\r |
4036 | \r | |
4037 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4038 | STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r | |
4039 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4040 | (*Command & BIT2) != 0\r |
5d73d92f | 4041 | );\r |
4042 | \r | |
4043 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4044 | STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r | |
4045 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4046 | (*Command & BIT3) != 0\r |
5d73d92f | 4047 | );\r |
4048 | \r | |
4049 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4050 | STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r | |
4051 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4052 | (*Command & BIT4) != 0\r |
5d73d92f | 4053 | );\r |
4054 | \r | |
4055 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4056 | STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r | |
4057 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4058 | (*Command & BIT5) != 0\r |
5d73d92f | 4059 | );\r |
4060 | \r | |
4061 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4062 | STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r | |
4063 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4064 | (*Command & BIT6) != 0\r |
5d73d92f | 4065 | );\r |
4066 | \r | |
4067 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4068 | STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r | |
4069 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4070 | (*Command & BIT7) != 0\r |
5d73d92f | 4071 | );\r |
4072 | \r | |
4073 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4074 | STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r | |
4075 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4076 | (*Command & BIT8) != 0\r |
5d73d92f | 4077 | );\r |
4078 | \r | |
4079 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4080 | STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r | |
4081 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4082 | (*Command & BIT9) != 0\r |
5d73d92f | 4083 | );\r |
4084 | \r | |
4085 | return EFI_SUCCESS;\r | |
4086 | }\r | |
4087 | \r | |
a1d4bfcc | 4088 | /**\r |
4089 | Explain each meaningful bit of register Bridge Control.\r | |
4090 | \r | |
4091 | @param[in] BridgeControl Points to the content of register Bridge Control.\r | |
4092 | @param[in] HeaderType The headertype.\r | |
4093 | \r | |
4094 | @retval EFI_SUCCESS The command completed successfully.\r | |
4095 | **/\r | |
5d73d92f | 4096 | EFI_STATUS\r |
4097 | PciExplainBridgeControl (\r | |
4098 | IN UINT16 *BridgeControl,\r | |
4099 | IN PCI_HEADER_TYPE HeaderType\r | |
4100 | )\r | |
5d73d92f | 4101 | {\r |
4102 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4103 | STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r | |
4104 | gShellDebug1HiiHandle,\r | |
4105 | INDEX_OF (BridgeControl),\r | |
4106 | *BridgeControl\r | |
4107 | );\r | |
4108 | \r | |
4109 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4110 | STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r | |
4111 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4112 | (*BridgeControl & BIT0) != 0\r |
5d73d92f | 4113 | );\r |
4114 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4115 | STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r | |
4116 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4117 | (*BridgeControl & BIT1) != 0\r |
5d73d92f | 4118 | );\r |
4119 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4120 | STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r | |
4121 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4122 | (*BridgeControl & BIT2) != 0\r |
5d73d92f | 4123 | );\r |
4124 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4125 | STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r | |
4126 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4127 | (*BridgeControl & BIT3) != 0\r |
5d73d92f | 4128 | );\r |
4129 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4130 | STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r | |
4131 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4132 | (*BridgeControl & BIT5) != 0\r |
5d73d92f | 4133 | );\r |
4134 | \r | |
4135 | //\r | |
4136 | // Register Bridge Control has some slight differences between P2P bridge\r | |
4137 | // and Cardbus bridge from bit 6 to bit 11.\r | |
4138 | //\r | |
4139 | if (HeaderType == PciP2pBridge) {\r | |
4140 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4141 | STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r | |
4142 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4143 | (*BridgeControl & BIT6) != 0\r |
5d73d92f | 4144 | );\r |
4145 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4146 | STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r | |
4147 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4148 | (*BridgeControl & BIT7) != 0\r |
5d73d92f | 4149 | );\r |
4150 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4151 | STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r | |
4152 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4153 | (*BridgeControl & BIT8)!=0 ? L"2^10" : L"2^15"\r |
5d73d92f | 4154 | );\r |
4155 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4156 | STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r | |
4157 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4158 | (*BridgeControl & BIT9)!=0 ? L"2^10" : L"2^15"\r |
5d73d92f | 4159 | );\r |
4160 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4161 | STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r | |
4162 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4163 | (*BridgeControl & BIT10) != 0\r |
5d73d92f | 4164 | );\r |
4165 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4166 | STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r | |
4167 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4168 | (*BridgeControl & BIT11) != 0\r |
5d73d92f | 4169 | );\r |
4170 | \r | |
4171 | } else {\r | |
4172 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4173 | STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r | |
4174 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4175 | (*BridgeControl & BIT6) != 0\r |
5d73d92f | 4176 | );\r |
4177 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4178 | STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r | |
4179 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4180 | (*BridgeControl & BIT7) != 0\r |
5d73d92f | 4181 | );\r |
4182 | ShellPrintHiiEx(-1, -1, NULL,\r | |
4183 | STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r | |
4184 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4185 | (*BridgeControl & BIT10) != 0\r |
5d73d92f | 4186 | );\r |
4187 | }\r | |
4188 | \r | |
4189 | return EFI_SUCCESS;\r | |
4190 | }\r | |
4191 | \r | |
a1d4bfcc | 4192 | /**\r |
33cc487c | 4193 | Locate capability register block per capability ID.\r |
a1d4bfcc | 4194 | \r |
33cc487c RN |
4195 | @param[in] ConfigSpace Data in PCI configuration space.\r |
4196 | @param[in] CapabilityId The capability ID.\r | |
a1d4bfcc | 4197 | \r |
33cc487c RN |
4198 | @return The offset of the register block per capability ID,\r |
4199 | or 0 if the register block cannot be found.\r | |
a1d4bfcc | 4200 | **/\r |
33cc487c RN |
4201 | UINT8\r |
4202 | LocatePciCapability (\r | |
4203 | IN PCI_CONFIG_SPACE *ConfigSpace,\r | |
4204 | IN UINT8 CapabilityId\r | |
5d73d92f | 4205 | )\r |
4206 | {\r | |
33cc487c RN |
4207 | UINT8 CapabilityPtr;\r |
4208 | EFI_PCI_CAPABILITY_HDR *CapabilityEntry;\r | |
5d73d92f | 4209 | \r |
4210 | //\r | |
33cc487c | 4211 | // To check the cpability of this device supports\r |
5d73d92f | 4212 | //\r |
33cc487c RN |
4213 | if ((ConfigSpace->Common.Status & EFI_PCI_STATUS_CAPABILITY) == 0) {\r |
4214 | return 0;\r | |
4215 | }\r | |
5d73d92f | 4216 | \r |
33cc487c RN |
4217 | switch ((PCI_HEADER_TYPE)(ConfigSpace->Common.HeaderType & 0x7f)) {\r |
4218 | case PciDevice:\r | |
4219 | CapabilityPtr = ConfigSpace->NonCommon.Device.CapabilityPtr;\r | |
4220 | break;\r | |
4221 | case PciP2pBridge:\r | |
4222 | CapabilityPtr = ConfigSpace->NonCommon.Bridge.CapabilityPtr;\r | |
4223 | break;\r | |
4224 | case PciCardBusBridge:\r | |
4225 | CapabilityPtr = ConfigSpace->NonCommon.CardBus.Cap_Ptr;\r | |
4226 | break;\r | |
4227 | default:\r | |
4228 | return 0;\r | |
4229 | }\r | |
5d73d92f | 4230 | \r |
33cc487c RN |
4231 | while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r |
4232 | CapabilityEntry = (EFI_PCI_CAPABILITY_HDR *) ((UINT8 *) ConfigSpace + CapabilityPtr);\r | |
4233 | if (CapabilityEntry->CapabilityID == CapabilityId) {\r | |
4234 | return CapabilityPtr;\r | |
5d73d92f | 4235 | }\r |
33cc487c | 4236 | \r |
5d73d92f | 4237 | //\r |
33cc487c RN |
4238 | // Certain PCI device may incorrectly have capability pointing to itself,\r |
4239 | // break to avoid dead loop.\r | |
5d73d92f | 4240 | //\r |
33cc487c RN |
4241 | if (CapabilityPtr == CapabilityEntry->NextItemPtr) {\r |
4242 | break;\r | |
4243 | }\r | |
4244 | \r | |
4245 | CapabilityPtr = CapabilityEntry->NextItemPtr;\r | |
5d73d92f | 4246 | }\r |
4247 | \r | |
33cc487c | 4248 | return 0;\r |
5d73d92f | 4249 | }\r |
4250 | \r | |
a1d4bfcc | 4251 | /**\r |
4252 | Print out information of the capability information.\r | |
4253 | \r | |
4254 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4255 | \r | |
4256 | @retval EFI_SUCCESS The operation was successful.\r | |
4257 | **/\r | |
5d73d92f | 4258 | EFI_STATUS\r |
4259 | ExplainPcieCapReg (\r | |
0c84a69f | 4260 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4261 | )\r |
5d73d92f | 4262 | {\r |
5d73d92f | 4263 | CHAR16 *DevicePortType;\r |
4264 | \r | |
c37e0f16 CP |
4265 | ShellPrintEx (-1, -1,\r |
4266 | L" Capability Version(3:0): %E0x%04x%N\r\n",\r | |
0c84a69f | 4267 | PciExpressCap->Capability.Bits.Version\r |
5d73d92f | 4268 | );\r |
0c84a69f RN |
4269 | if (PciExpressCap->Capability.Bits.DevicePortType < ARRAY_SIZE (DevicePortTypeTable)) {\r |
4270 | DevicePortType = DevicePortTypeTable[PciExpressCap->Capability.Bits.DevicePortType];\r | |
5d73d92f | 4271 | } else {\r |
4272 | DevicePortType = L"Unknown Type";\r | |
4273 | }\r | |
c37e0f16 CP |
4274 | ShellPrintEx (-1, -1,\r |
4275 | L" Device/PortType(7:4): %E%s%N\r\n",\r | |
5d73d92f | 4276 | DevicePortType\r |
4277 | );\r | |
4278 | //\r | |
4279 | // 'Slot Implemented' is only valid for:\r | |
4280 | // a) Root Port of PCI Express Root Complex, or\r | |
4281 | // b) Downstream Port of PCI Express Switch\r | |
4282 | //\r | |
0c84a69f RN |
4283 | if (PciExpressCap->Capability.Bits.DevicePortType== PCIE_DEVICE_PORT_TYPE_ROOT_PORT ||\r |
4284 | PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT) {\r | |
c37e0f16 CP |
4285 | ShellPrintEx (-1, -1,\r |
4286 | L" Slot Implemented(8): %E%d%N\r\n",\r | |
0c84a69f | 4287 | PciExpressCap->Capability.Bits.SlotImplemented\r |
5d73d92f | 4288 | );\r |
4289 | }\r | |
c37e0f16 CP |
4290 | ShellPrintEx (-1, -1,\r |
4291 | L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r | |
0c84a69f | 4292 | PciExpressCap->Capability.Bits.InterruptMessageNumber\r |
5d73d92f | 4293 | );\r |
4294 | return EFI_SUCCESS;\r | |
4295 | }\r | |
4296 | \r | |
a1d4bfcc | 4297 | /**\r |
4298 | Print out information of the device capability information.\r | |
4299 | \r | |
4300 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4301 | \r | |
4302 | @retval EFI_SUCCESS The operation was successful.\r | |
4303 | **/\r | |
5d73d92f | 4304 | EFI_STATUS\r |
4305 | ExplainPcieDeviceCap (\r | |
0c84a69f | 4306 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4307 | )\r |
5d73d92f | 4308 | {\r |
5d73d92f | 4309 | UINT8 DevicePortType;\r |
4310 | UINT8 L0sLatency;\r | |
4311 | UINT8 L1Latency;\r | |
4312 | \r | |
0c84a69f | 4313 | DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r |
c37e0f16 | 4314 | ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r |
0c84a69f RN |
4315 | if (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize < 6) {\r |
4316 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize + 7));\r | |
5d73d92f | 4317 | } else {\r |
c37e0f16 | 4318 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4319 | }\r |
c37e0f16 CP |
4320 | ShellPrintEx (-1, -1,\r |
4321 | L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r | |
0c84a69f | 4322 | PciExpressCap->DeviceCapability.Bits.PhantomFunctions\r |
5d73d92f | 4323 | );\r |
c37e0f16 CP |
4324 | ShellPrintEx (-1, -1,\r |
4325 | L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r | |
0c84a69f | 4326 | PciExpressCap->DeviceCapability.Bits.ExtendedTagField ? 8 : 5\r |
5d73d92f | 4327 | );\r |
4328 | //\r | |
4329 | // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r | |
4330 | //\r | |
4331 | if (IS_PCIE_ENDPOINT (DevicePortType)) {\r | |
0c84a69f RN |
4332 | L0sLatency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL0sAcceptableLatency;\r |
4333 | L1Latency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL1AcceptableLatency;\r | |
c37e0f16 | 4334 | ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r |
5d73d92f | 4335 | if (L0sLatency < 4) {\r |
c37e0f16 | 4336 | ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r |
5d73d92f | 4337 | } else {\r |
4338 | if (L0sLatency < 7) {\r | |
c37e0f16 | 4339 | ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r |
5d73d92f | 4340 | } else {\r |
c37e0f16 | 4341 | ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r |
5d73d92f | 4342 | }\r |
4343 | }\r | |
c37e0f16 | 4344 | ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r |
5d73d92f | 4345 | if (L1Latency < 7) {\r |
c37e0f16 | 4346 | ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r |
5d73d92f | 4347 | } else {\r |
c37e0f16 | 4348 | ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r |
5d73d92f | 4349 | }\r |
4350 | }\r | |
c37e0f16 CP |
4351 | ShellPrintEx (-1, -1,\r |
4352 | L" Role-based Error Reporting(15): %E%d%N\r\n",\r | |
0c84a69f | 4353 | PciExpressCap->DeviceCapability.Bits.RoleBasedErrorReporting\r |
5d73d92f | 4354 | );\r |
4355 | //\r | |
4356 | // Only valid for Upstream Port:\r | |
4357 | // a) Captured Slot Power Limit Value\r | |
4358 | // b) Captured Slot Power Scale\r | |
4359 | //\r | |
0c84a69f | 4360 | if (DevicePortType == PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) {\r |
c37e0f16 CP |
4361 | ShellPrintEx (-1, -1,\r |
4362 | L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r | |
0c84a69f | 4363 | PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitValue\r |
5d73d92f | 4364 | );\r |
c37e0f16 CP |
4365 | ShellPrintEx (-1, -1,\r |
4366 | L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r | |
0c84a69f | 4367 | SlotPwrLmtScaleTable[PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitScale]\r |
5d73d92f | 4368 | );\r |
4369 | }\r | |
4370 | //\r | |
4371 | // Function Level Reset Capability is only valid for Endpoint\r | |
4372 | //\r | |
4373 | if (IS_PCIE_ENDPOINT (DevicePortType)) {\r | |
c37e0f16 CP |
4374 | ShellPrintEx (-1, -1,\r |
4375 | L" Function Level Reset Capability(28): %E%d%N\r\n",\r | |
0c84a69f | 4376 | PciExpressCap->DeviceCapability.Bits.FunctionLevelReset\r |
5d73d92f | 4377 | );\r |
4378 | }\r | |
4379 | return EFI_SUCCESS;\r | |
4380 | }\r | |
4381 | \r | |
a1d4bfcc | 4382 | /**\r |
4383 | Print out information of the device control information.\r | |
4384 | \r | |
4385 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4386 | \r | |
4387 | @retval EFI_SUCCESS The operation was successful.\r | |
4388 | **/\r | |
5d73d92f | 4389 | EFI_STATUS\r |
4390 | ExplainPcieDeviceControl (\r | |
0c84a69f | 4391 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4392 | )\r |
5d73d92f | 4393 | {\r |
c37e0f16 CP |
4394 | ShellPrintEx (-1, -1,\r |
4395 | L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r | |
0c84a69f RN |
4396 | PciExpressCap->DeviceControl.Bits.CorrectableError\r |
4397 | );\r | |
c37e0f16 CP |
4398 | ShellPrintEx (-1, -1,\r |
4399 | L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r | |
0c84a69f | 4400 | PciExpressCap->DeviceControl.Bits.NonFatalError\r |
5d73d92f | 4401 | );\r |
c37e0f16 CP |
4402 | ShellPrintEx (-1, -1,\r |
4403 | L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r | |
0c84a69f | 4404 | PciExpressCap->DeviceControl.Bits.FatalError\r |
5d73d92f | 4405 | );\r |
c37e0f16 CP |
4406 | ShellPrintEx (-1, -1,\r |
4407 | L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r | |
0c84a69f | 4408 | PciExpressCap->DeviceControl.Bits.UnsupportedRequest\r |
5d73d92f | 4409 | );\r |
c37e0f16 CP |
4410 | ShellPrintEx (-1, -1,\r |
4411 | L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r | |
0c84a69f | 4412 | PciExpressCap->DeviceControl.Bits.RelaxedOrdering\r |
5d73d92f | 4413 | );\r |
c37e0f16 | 4414 | ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r |
0c84a69f RN |
4415 | if (PciExpressCap->DeviceControl.Bits.MaxPayloadSize < 6) {\r |
4416 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxPayloadSize + 7));\r | |
5d73d92f | 4417 | } else {\r |
c37e0f16 | 4418 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4419 | }\r |
c37e0f16 CP |
4420 | ShellPrintEx (-1, -1,\r |
4421 | L" Extended Tag Field Enable(8): %E%d%N\r\n",\r | |
0c84a69f | 4422 | PciExpressCap->DeviceControl.Bits.ExtendedTagField\r |
5d73d92f | 4423 | );\r |
c37e0f16 CP |
4424 | ShellPrintEx (-1, -1,\r |
4425 | L" Phantom Functions Enable(9): %E%d%N\r\n",\r | |
0c84a69f | 4426 | PciExpressCap->DeviceControl.Bits.PhantomFunctions\r |
5d73d92f | 4427 | );\r |
c37e0f16 CP |
4428 | ShellPrintEx (-1, -1,\r |
4429 | L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r | |
0c84a69f | 4430 | PciExpressCap->DeviceControl.Bits.AuxPower\r |
5d73d92f | 4431 | );\r |
c37e0f16 CP |
4432 | ShellPrintEx (-1, -1,\r |
4433 | L" Enable No Snoop(11): %E%d%N\r\n",\r | |
0c84a69f | 4434 | PciExpressCap->DeviceControl.Bits.NoSnoop\r |
5d73d92f | 4435 | );\r |
c37e0f16 | 4436 | ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r |
0c84a69f RN |
4437 | if (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize < 6) {\r |
4438 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize + 7));\r | |
5d73d92f | 4439 | } else {\r |
c37e0f16 | 4440 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4441 | }\r |
4442 | //\r | |
4443 | // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r | |
4444 | //\r | |
0c84a69f | 4445 | if (PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE) {\r |
c37e0f16 CP |
4446 | ShellPrintEx (-1, -1,\r |
4447 | L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r | |
0c84a69f | 4448 | PciExpressCap->DeviceControl.Bits.BridgeConfigurationRetryOrFunctionLevelReset\r |
5d73d92f | 4449 | );\r |
4450 | }\r | |
4451 | return EFI_SUCCESS;\r | |
4452 | }\r | |
4453 | \r | |
a1d4bfcc | 4454 | /**\r |
4455 | Print out information of the device status information.\r | |
4456 | \r | |
4457 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4458 | \r | |
4459 | @retval EFI_SUCCESS The operation was successful.\r | |
4460 | **/\r | |
5d73d92f | 4461 | EFI_STATUS\r |
4462 | ExplainPcieDeviceStatus (\r | |
0c84a69f | 4463 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4464 | )\r |
5d73d92f | 4465 | {\r |
c37e0f16 CP |
4466 | ShellPrintEx (-1, -1,\r |
4467 | L" Correctable Error Detected(0): %E%d%N\r\n",\r | |
0c84a69f | 4468 | PciExpressCap->DeviceStatus.Bits.CorrectableError\r |
5d73d92f | 4469 | );\r |
c37e0f16 CP |
4470 | ShellPrintEx (-1, -1,\r |
4471 | L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r | |
0c84a69f | 4472 | PciExpressCap->DeviceStatus.Bits.NonFatalError\r |
5d73d92f | 4473 | );\r |
c37e0f16 CP |
4474 | ShellPrintEx (-1, -1,\r |
4475 | L" Fatal Error Detected(2): %E%d%N\r\n",\r | |
0c84a69f | 4476 | PciExpressCap->DeviceStatus.Bits.FatalError\r |
5d73d92f | 4477 | );\r |
c37e0f16 CP |
4478 | ShellPrintEx (-1, -1,\r |
4479 | L" Unsupported Request Detected(3): %E%d%N\r\n",\r | |
0c84a69f | 4480 | PciExpressCap->DeviceStatus.Bits.UnsupportedRequest\r |
5d73d92f | 4481 | );\r |
c37e0f16 CP |
4482 | ShellPrintEx (-1, -1,\r |
4483 | L" AUX Power Detected(4): %E%d%N\r\n",\r | |
0c84a69f | 4484 | PciExpressCap->DeviceStatus.Bits.AuxPower\r |
5d73d92f | 4485 | );\r |
c37e0f16 CP |
4486 | ShellPrintEx (-1, -1,\r |
4487 | L" Transactions Pending(5): %E%d%N\r\n",\r | |
0c84a69f | 4488 | PciExpressCap->DeviceStatus.Bits.TransactionsPending\r |
5d73d92f | 4489 | );\r |
4490 | return EFI_SUCCESS;\r | |
4491 | }\r | |
4492 | \r | |
a1d4bfcc | 4493 | /**\r |
4494 | Print out information of the device link information.\r | |
4495 | \r | |
4496 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4497 | \r | |
4498 | @retval EFI_SUCCESS The operation was successful.\r | |
4499 | **/\r | |
5d73d92f | 4500 | EFI_STATUS\r |
4501 | ExplainPcieLinkCap (\r | |
0c84a69f | 4502 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4503 | )\r |
5d73d92f | 4504 | {\r |
541ddf44 | 4505 | CHAR16 *MaxLinkSpeed;\r |
a1d4bfcc | 4506 | CHAR16 *AspmValue;\r |
5d73d92f | 4507 | \r |
0c84a69f | 4508 | switch (PciExpressCap->LinkCapability.Bits.MaxLinkSpeed) {\r |
5d73d92f | 4509 | case 1:\r |
541ddf44 | 4510 | MaxLinkSpeed = L"2.5 GT/s";\r |
5d73d92f | 4511 | break;\r |
4512 | case 2:\r | |
541ddf44 CP |
4513 | MaxLinkSpeed = L"5.0 GT/s";\r |
4514 | break;\r | |
4515 | case 3:\r | |
4516 | MaxLinkSpeed = L"8.0 GT/s";\r | |
5d73d92f | 4517 | break;\r |
adb59b63 ZG |
4518 | case 4:\r |
4519 | MaxLinkSpeed = L"16.0 GT/s";\r | |
4520 | break;\r | |
4521 | case 5:\r | |
4522 | MaxLinkSpeed = L"32.0 GT/s";\r | |
4523 | break;\r | |
5d73d92f | 4524 | default:\r |
adb59b63 | 4525 | MaxLinkSpeed = L"Reserved";\r |
5d73d92f | 4526 | break;\r |
4527 | }\r | |
c37e0f16 | 4528 | ShellPrintEx (-1, -1,\r |
541ddf44 CP |
4529 | L" Maximum Link Speed(3:0): %E%s%N\r\n",\r |
4530 | MaxLinkSpeed\r | |
5d73d92f | 4531 | );\r |
c37e0f16 CP |
4532 | ShellPrintEx (-1, -1,\r |
4533 | L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r | |
0c84a69f | 4534 | PciExpressCap->LinkCapability.Bits.MaxLinkWidth\r |
5d73d92f | 4535 | );\r |
0c84a69f | 4536 | switch (PciExpressCap->LinkCapability.Bits.Aspm) {\r |
541ddf44 CP |
4537 | case 0:\r |
4538 | AspmValue = L"Not";\r | |
4539 | break;\r | |
5d73d92f | 4540 | case 1:\r |
541ddf44 CP |
4541 | AspmValue = L"L0s";\r |
4542 | break;\r | |
4543 | case 2:\r | |
4544 | AspmValue = L"L1";\r | |
5d73d92f | 4545 | break;\r |
4546 | case 3:\r | |
a1d4bfcc | 4547 | AspmValue = L"L0s and L1";\r |
5d73d92f | 4548 | break;\r |
4549 | default:\r | |
a1d4bfcc | 4550 | AspmValue = L"Reserved";\r |
5d73d92f | 4551 | break;\r |
4552 | }\r | |
c37e0f16 CP |
4553 | ShellPrintEx (-1, -1,\r |
4554 | L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r | |
a1d4bfcc | 4555 | AspmValue\r |
5d73d92f | 4556 | );\r |
c37e0f16 CP |
4557 | ShellPrintEx (-1, -1,\r |
4558 | L" L0s Exit Latency(14:12): %E%s%N\r\n",\r | |
0c84a69f | 4559 | L0sLatencyStrTable[PciExpressCap->LinkCapability.Bits.L0sExitLatency]\r |
5d73d92f | 4560 | );\r |
c37e0f16 CP |
4561 | ShellPrintEx (-1, -1,\r |
4562 | L" L1 Exit Latency(17:15): %E%s%N\r\n",\r | |
0c84a69f | 4563 | L1LatencyStrTable[PciExpressCap->LinkCapability.Bits.L1ExitLatency]\r |
5d73d92f | 4564 | );\r |
c37e0f16 CP |
4565 | ShellPrintEx (-1, -1,\r |
4566 | L" Clock Power Management(18): %E%d%N\r\n",\r | |
0c84a69f | 4567 | PciExpressCap->LinkCapability.Bits.ClockPowerManagement\r |
5d73d92f | 4568 | );\r |
c37e0f16 CP |
4569 | ShellPrintEx (-1, -1,\r |
4570 | L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r | |
0c84a69f | 4571 | PciExpressCap->LinkCapability.Bits.SurpriseDownError\r |
5d73d92f | 4572 | );\r |
c37e0f16 CP |
4573 | ShellPrintEx (-1, -1,\r |
4574 | L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r | |
0c84a69f | 4575 | PciExpressCap->LinkCapability.Bits.DataLinkLayerLinkActive\r |
5d73d92f | 4576 | );\r |
c37e0f16 CP |
4577 | ShellPrintEx (-1, -1,\r |
4578 | L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r | |
0c84a69f | 4579 | PciExpressCap->LinkCapability.Bits.LinkBandwidthNotification\r |
5d73d92f | 4580 | );\r |
c37e0f16 CP |
4581 | ShellPrintEx (-1, -1,\r |
4582 | L" Port Number(31:24): %E0x%02x%N\r\n",\r | |
0c84a69f | 4583 | PciExpressCap->LinkCapability.Bits.PortNumber\r |
5d73d92f | 4584 | );\r |
4585 | return EFI_SUCCESS;\r | |
4586 | }\r | |
4587 | \r | |
a1d4bfcc | 4588 | /**\r |
4589 | Print out information of the device link control information.\r | |
4590 | \r | |
4591 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4592 | \r | |
4593 | @retval EFI_SUCCESS The operation was successful.\r | |
4594 | **/\r | |
5d73d92f | 4595 | EFI_STATUS\r |
4596 | ExplainPcieLinkControl (\r | |
0c84a69f | 4597 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4598 | )\r |
5d73d92f | 4599 | {\r |
5d73d92f | 4600 | UINT8 DevicePortType;\r |
4601 | \r | |
0c84a69f | 4602 | DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r |
c37e0f16 CP |
4603 | ShellPrintEx (-1, -1,\r |
4604 | L" Active State Power Management Control(1:0): %E%s%N\r\n",\r | |
0c84a69f | 4605 | ASPMCtrlStrTable[PciExpressCap->LinkControl.Bits.AspmControl]\r |
5d73d92f | 4606 | );\r |
4607 | //\r | |
4608 | // RCB is not applicable to switches\r | |
4609 | //\r | |
4610 | if (!IS_PCIE_SWITCH(DevicePortType)) {\r | |
c37e0f16 CP |
4611 | ShellPrintEx (-1, -1,\r |
4612 | L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r | |
0c84a69f | 4613 | 1 << (PciExpressCap->LinkControl.Bits.ReadCompletionBoundary + 6)\r |
5d73d92f | 4614 | );\r |
4615 | }\r | |
4616 | //\r | |
4617 | // Link Disable is reserved on\r | |
4618 | // a) Endpoints\r | |
4619 | // b) PCI Express to PCI/PCI-X bridges\r | |
4620 | // c) Upstream Ports of Switches\r | |
4621 | //\r | |
4622 | if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r | |
0c84a69f RN |
4623 | DevicePortType != PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT &&\r |
4624 | DevicePortType != PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE) {\r | |
c37e0f16 CP |
4625 | ShellPrintEx (-1, -1,\r |
4626 | L" Link Disable(4): %E%d%N\r\n",\r | |
0c84a69f | 4627 | PciExpressCap->LinkControl.Bits.LinkDisable\r |
5d73d92f | 4628 | );\r |
4629 | }\r | |
c37e0f16 CP |
4630 | ShellPrintEx (-1, -1,\r |
4631 | L" Common Clock Configuration(6): %E%d%N\r\n",\r | |
0c84a69f | 4632 | PciExpressCap->LinkControl.Bits.CommonClockConfiguration\r |
5d73d92f | 4633 | );\r |
c37e0f16 CP |
4634 | ShellPrintEx (-1, -1,\r |
4635 | L" Extended Synch(7): %E%d%N\r\n",\r | |
0c84a69f | 4636 | PciExpressCap->LinkControl.Bits.ExtendedSynch\r |
5d73d92f | 4637 | );\r |
c37e0f16 CP |
4638 | ShellPrintEx (-1, -1,\r |
4639 | L" Enable Clock Power Management(8): %E%d%N\r\n",\r | |
0c84a69f | 4640 | PciExpressCap->LinkControl.Bits.ClockPowerManagement\r |
5d73d92f | 4641 | );\r |
c37e0f16 CP |
4642 | ShellPrintEx (-1, -1,\r |
4643 | L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r | |
0c84a69f | 4644 | PciExpressCap->LinkControl.Bits.HardwareAutonomousWidthDisable\r |
5d73d92f | 4645 | );\r |
c37e0f16 CP |
4646 | ShellPrintEx (-1, -1,\r |
4647 | L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r | |
0c84a69f | 4648 | PciExpressCap->LinkControl.Bits.LinkBandwidthManagementInterrupt\r |
5d73d92f | 4649 | );\r |
c37e0f16 CP |
4650 | ShellPrintEx (-1, -1,\r |
4651 | L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r | |
0c84a69f | 4652 | PciExpressCap->LinkControl.Bits.LinkAutonomousBandwidthInterrupt\r |
5d73d92f | 4653 | );\r |
4654 | return EFI_SUCCESS;\r | |
4655 | }\r | |
4656 | \r | |
a1d4bfcc | 4657 | /**\r |
4658 | Print out information of the device link status information.\r | |
4659 | \r | |
4660 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4661 | \r | |
4662 | @retval EFI_SUCCESS The operation was successful.\r | |
4663 | **/\r | |
5d73d92f | 4664 | EFI_STATUS\r |
4665 | ExplainPcieLinkStatus (\r | |
0c84a69f | 4666 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4667 | )\r |
5d73d92f | 4668 | {\r |
541ddf44 | 4669 | CHAR16 *CurLinkSpeed;\r |
5d73d92f | 4670 | \r |
0c84a69f | 4671 | switch (PciExpressCap->LinkStatus.Bits.CurrentLinkSpeed) {\r |
5d73d92f | 4672 | case 1:\r |
541ddf44 | 4673 | CurLinkSpeed = L"2.5 GT/s";\r |
5d73d92f | 4674 | break;\r |
4675 | case 2:\r | |
541ddf44 CP |
4676 | CurLinkSpeed = L"5.0 GT/s";\r |
4677 | break;\r | |
4678 | case 3:\r | |
4679 | CurLinkSpeed = L"8.0 GT/s";\r | |
5d73d92f | 4680 | break;\r |
adb59b63 ZG |
4681 | case 4:\r |
4682 | CurLinkSpeed = L"16.0 GT/s";\r | |
4683 | break;\r | |
4684 | case 5:\r | |
4685 | CurLinkSpeed = L"32.0 GT/s";\r | |
4686 | break;\r | |
5d73d92f | 4687 | default:\r |
541ddf44 | 4688 | CurLinkSpeed = L"Reserved";\r |
5d73d92f | 4689 | break;\r |
4690 | }\r | |
c37e0f16 CP |
4691 | ShellPrintEx (-1, -1,\r |
4692 | L" Current Link Speed(3:0): %E%s%N\r\n",\r | |
541ddf44 | 4693 | CurLinkSpeed\r |
5d73d92f | 4694 | );\r |
c37e0f16 CP |
4695 | ShellPrintEx (-1, -1,\r |
4696 | L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r | |
0c84a69f | 4697 | PciExpressCap->LinkStatus.Bits.NegotiatedLinkWidth\r |
5d73d92f | 4698 | );\r |
c37e0f16 CP |
4699 | ShellPrintEx (-1, -1,\r |
4700 | L" Link Training(11): %E%d%N\r\n",\r | |
0c84a69f | 4701 | PciExpressCap->LinkStatus.Bits.LinkTraining\r |
5d73d92f | 4702 | );\r |
c37e0f16 CP |
4703 | ShellPrintEx (-1, -1,\r |
4704 | L" Slot Clock Configuration(12): %E%d%N\r\n",\r | |
0c84a69f | 4705 | PciExpressCap->LinkStatus.Bits.SlotClockConfiguration\r |
5d73d92f | 4706 | );\r |
c37e0f16 CP |
4707 | ShellPrintEx (-1, -1,\r |
4708 | L" Data Link Layer Link Active(13): %E%d%N\r\n",\r | |
0c84a69f | 4709 | PciExpressCap->LinkStatus.Bits.DataLinkLayerLinkActive\r |
5d73d92f | 4710 | );\r |
c37e0f16 CP |
4711 | ShellPrintEx (-1, -1,\r |
4712 | L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r | |
0c84a69f | 4713 | PciExpressCap->LinkStatus.Bits.LinkBandwidthManagement\r |
5d73d92f | 4714 | );\r |
c37e0f16 CP |
4715 | ShellPrintEx (-1, -1,\r |
4716 | L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r | |
0c84a69f | 4717 | PciExpressCap->LinkStatus.Bits.LinkAutonomousBandwidth\r |
5d73d92f | 4718 | );\r |
4719 | return EFI_SUCCESS;\r | |
4720 | }\r | |
4721 | \r | |
a1d4bfcc | 4722 | /**\r |
4723 | Print out information of the device slot information.\r | |
4724 | \r | |
4725 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4726 | \r | |
4727 | @retval EFI_SUCCESS The operation was successful.\r | |
4728 | **/\r | |
5d73d92f | 4729 | EFI_STATUS\r |
4730 | ExplainPcieSlotCap (\r | |
0c84a69f | 4731 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4732 | )\r |
5d73d92f | 4733 | {\r |
c37e0f16 CP |
4734 | ShellPrintEx (-1, -1,\r |
4735 | L" Attention Button Present(0): %E%d%N\r\n",\r | |
0c84a69f | 4736 | PciExpressCap->SlotCapability.Bits.AttentionButton\r |
5d73d92f | 4737 | );\r |
c37e0f16 CP |
4738 | ShellPrintEx (-1, -1,\r |
4739 | L" Power Controller Present(1): %E%d%N\r\n",\r | |
0c84a69f | 4740 | PciExpressCap->SlotCapability.Bits.PowerController\r |
5d73d92f | 4741 | );\r |
c37e0f16 CP |
4742 | ShellPrintEx (-1, -1,\r |
4743 | L" MRL Sensor Present(2): %E%d%N\r\n",\r | |
0c84a69f | 4744 | PciExpressCap->SlotCapability.Bits.MrlSensor\r |
5d73d92f | 4745 | );\r |
c37e0f16 CP |
4746 | ShellPrintEx (-1, -1,\r |
4747 | L" Attention Indicator Present(3): %E%d%N\r\n",\r | |
0c84a69f | 4748 | PciExpressCap->SlotCapability.Bits.AttentionIndicator\r |
5d73d92f | 4749 | );\r |
c37e0f16 CP |
4750 | ShellPrintEx (-1, -1,\r |
4751 | L" Power Indicator Present(4): %E%d%N\r\n",\r | |
0c84a69f | 4752 | PciExpressCap->SlotCapability.Bits.PowerIndicator\r |
5d73d92f | 4753 | );\r |
c37e0f16 CP |
4754 | ShellPrintEx (-1, -1,\r |
4755 | L" Hot-Plug Surprise(5): %E%d%N\r\n",\r | |
0c84a69f | 4756 | PciExpressCap->SlotCapability.Bits.HotPlugSurprise\r |
5d73d92f | 4757 | );\r |
c37e0f16 CP |
4758 | ShellPrintEx (-1, -1,\r |
4759 | L" Hot-Plug Capable(6): %E%d%N\r\n",\r | |
0c84a69f | 4760 | PciExpressCap->SlotCapability.Bits.HotPlugCapable\r |
5d73d92f | 4761 | );\r |
c37e0f16 CP |
4762 | ShellPrintEx (-1, -1,\r |
4763 | L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r | |
0c84a69f | 4764 | PciExpressCap->SlotCapability.Bits.SlotPowerLimitValue\r |
5d73d92f | 4765 | );\r |
c37e0f16 CP |
4766 | ShellPrintEx (-1, -1,\r |
4767 | L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r | |
0c84a69f | 4768 | SlotPwrLmtScaleTable[PciExpressCap->SlotCapability.Bits.SlotPowerLimitScale]\r |
5d73d92f | 4769 | );\r |
c37e0f16 CP |
4770 | ShellPrintEx (-1, -1,\r |
4771 | L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r | |
0c84a69f | 4772 | PciExpressCap->SlotCapability.Bits.ElectromechanicalInterlock\r |
5d73d92f | 4773 | );\r |
c37e0f16 CP |
4774 | ShellPrintEx (-1, -1,\r |
4775 | L" No Command Completed Support(18): %E%d%N\r\n",\r | |
0c84a69f | 4776 | PciExpressCap->SlotCapability.Bits.NoCommandCompleted\r |
5d73d92f | 4777 | );\r |
c37e0f16 CP |
4778 | ShellPrintEx (-1, -1,\r |
4779 | L" Physical Slot Number(31:19): %E%d%N\r\n",\r | |
0c84a69f | 4780 | PciExpressCap->SlotCapability.Bits.PhysicalSlotNumber\r |
5d73d92f | 4781 | );\r |
4782 | \r | |
4783 | return EFI_SUCCESS;\r | |
4784 | }\r | |
4785 | \r | |
a1d4bfcc | 4786 | /**\r |
4787 | Print out information of the device slot control information.\r | |
4788 | \r | |
4789 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4790 | \r | |
4791 | @retval EFI_SUCCESS The operation was successful.\r | |
4792 | **/\r | |
5d73d92f | 4793 | EFI_STATUS\r |
4794 | ExplainPcieSlotControl (\r | |
0c84a69f | 4795 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4796 | )\r |
5d73d92f | 4797 | {\r |
c37e0f16 CP |
4798 | ShellPrintEx (-1, -1,\r |
4799 | L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r | |
0c84a69f | 4800 | PciExpressCap->SlotControl.Bits.AttentionButtonPressed\r |
5d73d92f | 4801 | );\r |
c37e0f16 CP |
4802 | ShellPrintEx (-1, -1,\r |
4803 | L" Power Fault Detected Enable(1): %E%d%N\r\n",\r | |
0c84a69f | 4804 | PciExpressCap->SlotControl.Bits.PowerFaultDetected\r |
5d73d92f | 4805 | );\r |
c37e0f16 CP |
4806 | ShellPrintEx (-1, -1,\r |
4807 | L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r | |
0c84a69f | 4808 | PciExpressCap->SlotControl.Bits.MrlSensorChanged\r |
5d73d92f | 4809 | );\r |
c37e0f16 CP |
4810 | ShellPrintEx (-1, -1,\r |
4811 | L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r | |
0c84a69f | 4812 | PciExpressCap->SlotControl.Bits.PresenceDetectChanged\r |
5d73d92f | 4813 | );\r |
c37e0f16 CP |
4814 | ShellPrintEx (-1, -1,\r |
4815 | L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r | |
0c84a69f | 4816 | PciExpressCap->SlotControl.Bits.CommandCompletedInterrupt\r |
5d73d92f | 4817 | );\r |
c37e0f16 CP |
4818 | ShellPrintEx (-1, -1,\r |
4819 | L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r | |
0c84a69f | 4820 | PciExpressCap->SlotControl.Bits.HotPlugInterrupt\r |
5d73d92f | 4821 | );\r |
c37e0f16 CP |
4822 | ShellPrintEx (-1, -1,\r |
4823 | L" Attention Indicator Control(7:6): %E%s%N\r\n",\r | |
0c84a69f RN |
4824 | IndicatorTable[\r |
4825 | PciExpressCap->SlotControl.Bits.AttentionIndicator]\r | |
5d73d92f | 4826 | );\r |
c37e0f16 CP |
4827 | ShellPrintEx (-1, -1,\r |
4828 | L" Power Indicator Control(9:8): %E%s%N\r\n",\r | |
0c84a69f | 4829 | IndicatorTable[PciExpressCap->SlotControl.Bits.PowerIndicator]\r |
5d73d92f | 4830 | );\r |
c37e0f16 | 4831 | ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r |
0c84a69f RN |
4832 | if (\r |
4833 | PciExpressCap->SlotControl.Bits.PowerController) {\r | |
c37e0f16 | 4834 | ShellPrintEx (-1, -1, L"Off%N\r\n");\r |
5d73d92f | 4835 | } else {\r |
c37e0f16 | 4836 | ShellPrintEx (-1, -1, L"On%N\r\n");\r |
5d73d92f | 4837 | }\r |
c37e0f16 CP |
4838 | ShellPrintEx (-1, -1,\r |
4839 | L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r | |
0c84a69f | 4840 | PciExpressCap->SlotControl.Bits.ElectromechanicalInterlock\r |
5d73d92f | 4841 | );\r |
c37e0f16 CP |
4842 | ShellPrintEx (-1, -1,\r |
4843 | L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r | |
0c84a69f | 4844 | PciExpressCap->SlotControl.Bits.DataLinkLayerStateChanged\r |
5d73d92f | 4845 | );\r |
4846 | return EFI_SUCCESS;\r | |
4847 | }\r | |
4848 | \r | |
a1d4bfcc | 4849 | /**\r |
4850 | Print out information of the device slot status information.\r | |
4851 | \r | |
4852 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4853 | \r | |
4854 | @retval EFI_SUCCESS The operation was successful.\r | |
4855 | **/\r | |
5d73d92f | 4856 | EFI_STATUS\r |
4857 | ExplainPcieSlotStatus (\r | |
0c84a69f | 4858 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4859 | )\r |
5d73d92f | 4860 | {\r |
c37e0f16 CP |
4861 | ShellPrintEx (-1, -1,\r |
4862 | L" Attention Button Pressed(0): %E%d%N\r\n",\r | |
0c84a69f | 4863 | PciExpressCap->SlotStatus.Bits.AttentionButtonPressed\r |
5d73d92f | 4864 | );\r |
c37e0f16 CP |
4865 | ShellPrintEx (-1, -1,\r |
4866 | L" Power Fault Detected(1): %E%d%N\r\n",\r | |
0c84a69f | 4867 | PciExpressCap->SlotStatus.Bits.PowerFaultDetected\r |
5d73d92f | 4868 | );\r |
c37e0f16 CP |
4869 | ShellPrintEx (-1, -1,\r |
4870 | L" MRL Sensor Changed(2): %E%d%N\r\n",\r | |
0c84a69f | 4871 | PciExpressCap->SlotStatus.Bits.MrlSensorChanged\r |
5d73d92f | 4872 | );\r |
c37e0f16 CP |
4873 | ShellPrintEx (-1, -1,\r |
4874 | L" Presence Detect Changed(3): %E%d%N\r\n",\r | |
0c84a69f | 4875 | PciExpressCap->SlotStatus.Bits.PresenceDetectChanged\r |
5d73d92f | 4876 | );\r |
c37e0f16 CP |
4877 | ShellPrintEx (-1, -1,\r |
4878 | L" Command Completed(4): %E%d%N\r\n",\r | |
0c84a69f | 4879 | PciExpressCap->SlotStatus.Bits.CommandCompleted\r |
5d73d92f | 4880 | );\r |
c37e0f16 | 4881 | ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r |
0c84a69f RN |
4882 | if (\r |
4883 | PciExpressCap->SlotStatus.Bits.MrlSensor) {\r | |
c37e0f16 | 4884 | ShellPrintEx (-1, -1, L" Opened%N\r\n");\r |
5d73d92f | 4885 | } else {\r |
c37e0f16 | 4886 | ShellPrintEx (-1, -1, L" Closed%N\r\n");\r |
5d73d92f | 4887 | }\r |
c37e0f16 | 4888 | ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r |
0c84a69f RN |
4889 | if (\r |
4890 | PciExpressCap->SlotStatus.Bits.PresenceDetect) {\r | |
c37e0f16 | 4891 | ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r |
5d73d92f | 4892 | } else {\r |
c37e0f16 | 4893 | ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r |
5d73d92f | 4894 | }\r |
c37e0f16 | 4895 | ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r |
0c84a69f RN |
4896 | if (\r |
4897 | PciExpressCap->SlotStatus.Bits.ElectromechanicalInterlock) {\r | |
c37e0f16 | 4898 | ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r |
5d73d92f | 4899 | } else {\r |
c37e0f16 | 4900 | ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r |
5d73d92f | 4901 | }\r |
c37e0f16 CP |
4902 | ShellPrintEx (-1, -1,\r |
4903 | L" Data Link Layer State Changed(8): %E%d%N\r\n",\r | |
0c84a69f | 4904 | PciExpressCap->SlotStatus.Bits.DataLinkLayerStateChanged\r |
5d73d92f | 4905 | );\r |
4906 | return EFI_SUCCESS;\r | |
4907 | }\r | |
4908 | \r | |
a1d4bfcc | 4909 | /**\r |
4910 | Print out information of the device root information.\r | |
4911 | \r | |
4912 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4913 | \r | |
4914 | @retval EFI_SUCCESS The operation was successful.\r | |
4915 | **/\r | |
5d73d92f | 4916 | EFI_STATUS\r |
4917 | ExplainPcieRootControl (\r | |
0c84a69f | 4918 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4919 | )\r |
5d73d92f | 4920 | {\r |
c37e0f16 CP |
4921 | ShellPrintEx (-1, -1,\r |
4922 | L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r | |
0c84a69f | 4923 | PciExpressCap->RootControl.Bits.SystemErrorOnCorrectableError\r |
5d73d92f | 4924 | );\r |
c37e0f16 CP |
4925 | ShellPrintEx (-1, -1,\r |
4926 | L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r | |
0c84a69f | 4927 | PciExpressCap->RootControl.Bits.SystemErrorOnNonFatalError\r |
5d73d92f | 4928 | );\r |
c37e0f16 CP |
4929 | ShellPrintEx (-1, -1,\r |
4930 | L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r | |
0c84a69f | 4931 | PciExpressCap->RootControl.Bits.SystemErrorOnFatalError\r |
5d73d92f | 4932 | );\r |
c37e0f16 CP |
4933 | ShellPrintEx (-1, -1,\r |
4934 | L" PME Interrupt Enable(3): %E%d%N\r\n",\r | |
0c84a69f | 4935 | PciExpressCap->RootControl.Bits.PmeInterrupt\r |
5d73d92f | 4936 | );\r |
c37e0f16 CP |
4937 | ShellPrintEx (-1, -1,\r |
4938 | L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r | |
0c84a69f | 4939 | PciExpressCap->RootControl.Bits.CrsSoftwareVisibility\r |
5d73d92f | 4940 | );\r |
4941 | \r | |
4942 | return EFI_SUCCESS;\r | |
4943 | }\r | |
4944 | \r | |
a1d4bfcc | 4945 | /**\r |
4946 | Print out information of the device root capability information.\r | |
4947 | \r | |
4948 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4949 | \r | |
4950 | @retval EFI_SUCCESS The operation was successful.\r | |
4951 | **/\r | |
5d73d92f | 4952 | EFI_STATUS\r |
4953 | ExplainPcieRootCap (\r | |
0c84a69f | 4954 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4955 | )\r |
5d73d92f | 4956 | {\r |
c37e0f16 CP |
4957 | ShellPrintEx (-1, -1,\r |
4958 | L" CRS Software Visibility(0): %E%d%N\r\n",\r | |
0c84a69f | 4959 | PciExpressCap->RootCapability.Bits.CrsSoftwareVisibility\r |
5d73d92f | 4960 | );\r |
4961 | \r | |
4962 | return EFI_SUCCESS;\r | |
4963 | }\r | |
4964 | \r | |
a1d4bfcc | 4965 | /**\r |
4966 | Print out information of the device root status information.\r | |
4967 | \r | |
4968 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4969 | \r | |
4970 | @retval EFI_SUCCESS The operation was successful.\r | |
4971 | **/\r | |
5d73d92f | 4972 | EFI_STATUS\r |
4973 | ExplainPcieRootStatus (\r | |
0c84a69f | 4974 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4975 | )\r |
5d73d92f | 4976 | {\r |
c37e0f16 CP |
4977 | ShellPrintEx (-1, -1,\r |
4978 | L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r | |
0c84a69f | 4979 | PciExpressCap->RootStatus.Bits.PmeRequesterId\r |
5d73d92f | 4980 | );\r |
c37e0f16 CP |
4981 | ShellPrintEx (-1, -1,\r |
4982 | L" PME Status(16): %E%d%N\r\n",\r | |
0c84a69f | 4983 | PciExpressCap->RootStatus.Bits.PmeStatus\r |
5d73d92f | 4984 | );\r |
c37e0f16 CP |
4985 | ShellPrintEx (-1, -1,\r |
4986 | L" PME Pending(17): %E%d%N\r\n",\r | |
0c84a69f | 4987 | PciExpressCap->RootStatus.Bits.PmePending\r |
5d73d92f | 4988 | );\r |
4989 | return EFI_SUCCESS;\r | |
4990 | }\r | |
4991 | \r | |
705bffb5 JC |
4992 | /**\r |
4993 | Function to interpret and print out the link control structure\r | |
4994 | \r | |
4995 | @param[in] HeaderAddress The Address of this capability header.\r | |
4996 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
4997 | **/\r | |
4998 | EFI_STATUS\r | |
705bffb5 JC |
4999 | PrintInterpretedExtendedCompatibilityLinkControl (\r |
5000 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5001 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5002 | )\r | |
5003 | {\r | |
5004 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r | |
5005 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r | |
5006 | \r | |
5007 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5008 | -1, -1, NULL,\r |
5009 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL),\r | |
5010 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5011 | Header->RootComplexLinkCapabilities,\r |
5012 | Header->RootComplexLinkControl,\r | |
5013 | Header->RootComplexLinkStatus\r | |
ba0014b9 | 5014 | );\r |
705bffb5 JC |
5015 | DumpHex (\r |
5016 | 4,\r | |
5017 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5018 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r | |
5019 | (VOID *) (HeaderAddress)\r | |
5020 | );\r | |
5021 | return (EFI_SUCCESS);\r | |
5022 | }\r | |
5023 | \r | |
5024 | /**\r | |
5025 | Function to interpret and print out the power budgeting structure\r | |
5026 | \r | |
5027 | @param[in] HeaderAddress The Address of this capability header.\r | |
5028 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5029 | **/\r | |
5030 | EFI_STATUS\r | |
705bffb5 JC |
5031 | PrintInterpretedExtendedCompatibilityPowerBudgeting (\r |
5032 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5033 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5034 | )\r | |
5035 | {\r | |
5036 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r | |
5037 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r | |
5038 | \r | |
5039 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5040 | -1, -1, NULL,\r |
5041 | STRING_TOKEN (STR_PCI_EXT_CAP_POWER),\r | |
5042 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5043 | Header->DataSelect,\r |
5044 | Header->Data,\r | |
5045 | Header->PowerBudgetCapability\r | |
ba0014b9 | 5046 | );\r |
705bffb5 JC |
5047 | DumpHex (\r |
5048 | 4,\r | |
5049 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5050 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r | |
5051 | (VOID *) (HeaderAddress)\r | |
5052 | );\r | |
5053 | return (EFI_SUCCESS);\r | |
5054 | }\r | |
5055 | \r | |
5056 | /**\r | |
5057 | Function to interpret and print out the ACS structure\r | |
5058 | \r | |
5059 | @param[in] HeaderAddress The Address of this capability header.\r | |
5060 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5061 | **/\r | |
5062 | EFI_STATUS\r | |
705bffb5 JC |
5063 | PrintInterpretedExtendedCompatibilityAcs (\r |
5064 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5065 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5066 | )\r | |
5067 | {\r | |
5068 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r | |
5069 | UINT16 VectorSize;\r | |
5070 | UINT16 LoopCounter;\r | |
5071 | \r | |
5072 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r | |
5073 | VectorSize = 0;\r | |
5074 | \r | |
5075 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5076 | -1, -1, NULL,\r |
5077 | STRING_TOKEN (STR_PCI_EXT_CAP_ACS),\r | |
5078 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5079 | Header->AcsCapability,\r |
5080 | Header->AcsControl\r | |
ba0014b9 | 5081 | );\r |
705bffb5 JC |
5082 | if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r |
5083 | VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r | |
5084 | if (VectorSize == 0) {\r | |
5085 | VectorSize = 256;\r | |
5086 | }\r | |
5087 | for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r | |
5088 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5089 | -1, -1, NULL,\r |
5090 | STRING_TOKEN (STR_PCI_EXT_CAP_ACS2),\r | |
5091 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5092 | LoopCounter + 1,\r |
5093 | Header->EgressControlVectorArray[LoopCounter]\r | |
ba0014b9 | 5094 | );\r |
705bffb5 JC |
5095 | }\r |
5096 | }\r | |
5097 | DumpHex (\r | |
5098 | 4,\r | |
5099 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5100 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r | |
5101 | (VOID *) (HeaderAddress)\r | |
5102 | );\r | |
5103 | return (EFI_SUCCESS);\r | |
5104 | }\r | |
5105 | \r | |
5106 | /**\r | |
5107 | Function to interpret and print out the latency tolerance reporting structure\r | |
5108 | \r | |
5109 | @param[in] HeaderAddress The Address of this capability header.\r | |
5110 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5111 | **/\r | |
5112 | EFI_STATUS\r | |
705bffb5 JC |
5113 | PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r |
5114 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5115 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5116 | )\r | |
5117 | {\r | |
5118 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r | |
5119 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r | |
5120 | \r | |
5121 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5122 | -1, -1, NULL,\r |
5123 | STRING_TOKEN (STR_PCI_EXT_CAP_LAT),\r | |
5124 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5125 | Header->MaxSnoopLatency,\r |
5126 | Header->MaxNoSnoopLatency\r | |
ba0014b9 | 5127 | );\r |
705bffb5 JC |
5128 | DumpHex (\r |
5129 | 4,\r | |
5130 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5131 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r | |
5132 | (VOID *) (HeaderAddress)\r | |
5133 | );\r | |
5134 | return (EFI_SUCCESS);\r | |
5135 | }\r | |
5136 | \r | |
5137 | /**\r | |
5138 | Function to interpret and print out the serial number structure\r | |
5139 | \r | |
5140 | @param[in] HeaderAddress The Address of this capability header.\r | |
5141 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5142 | **/\r | |
5143 | EFI_STATUS\r | |
705bffb5 JC |
5144 | PrintInterpretedExtendedCompatibilitySerialNumber (\r |
5145 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5146 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5147 | )\r | |
5148 | {\r | |
5149 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r | |
5150 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r | |
5151 | \r | |
5152 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5153 | -1, -1, NULL,\r |
5154 | STRING_TOKEN (STR_PCI_EXT_CAP_SN),\r | |
5155 | gShellDebug1HiiHandle,\r | |
705bffb5 | 5156 | Header->SerialNumber\r |
ba0014b9 | 5157 | );\r |
705bffb5 JC |
5158 | DumpHex (\r |
5159 | 4,\r | |
5160 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5161 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r | |
5162 | (VOID *) (HeaderAddress)\r | |
5163 | );\r | |
5164 | return (EFI_SUCCESS);\r | |
5165 | }\r | |
5166 | \r | |
5167 | /**\r | |
5168 | Function to interpret and print out the RCRB structure\r | |
5169 | \r | |
5170 | @param[in] HeaderAddress The Address of this capability header.\r | |
5171 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5172 | **/\r | |
5173 | EFI_STATUS\r | |
705bffb5 JC |
5174 | PrintInterpretedExtendedCompatibilityRcrb (\r |
5175 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5176 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5177 | )\r | |
5178 | {\r | |
5179 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r | |
5180 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r | |
5181 | \r | |
5182 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5183 | -1, -1, NULL,\r |
5184 | STRING_TOKEN (STR_PCI_EXT_CAP_RCRB),\r | |
5185 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5186 | Header->VendorId,\r |
5187 | Header->DeviceId,\r | |
5188 | Header->RcrbCapabilities,\r | |
5189 | Header->RcrbControl\r | |
ba0014b9 | 5190 | );\r |
705bffb5 JC |
5191 | DumpHex (\r |
5192 | 4,\r | |
5193 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5194 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r | |
5195 | (VOID *) (HeaderAddress)\r | |
5196 | );\r | |
5197 | return (EFI_SUCCESS);\r | |
5198 | }\r | |
5199 | \r | |
5200 | /**\r | |
5201 | Function to interpret and print out the vendor specific structure\r | |
5202 | \r | |
5203 | @param[in] HeaderAddress The Address of this capability header.\r | |
5204 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5205 | **/\r | |
5206 | EFI_STATUS\r | |
705bffb5 JC |
5207 | PrintInterpretedExtendedCompatibilityVendorSpecific (\r |
5208 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5209 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5210 | )\r | |
5211 | {\r | |
5212 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r | |
5213 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r | |
5214 | \r | |
5215 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5216 | -1, -1, NULL,\r |
5217 | STRING_TOKEN (STR_PCI_EXT_CAP_VEN),\r | |
5218 | gShellDebug1HiiHandle,\r | |
705bffb5 | 5219 | Header->VendorSpecificHeader\r |
ba0014b9 | 5220 | );\r |
705bffb5 JC |
5221 | DumpHex (\r |
5222 | 4,\r | |
5223 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5224 | PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r | |
5225 | (VOID *) (HeaderAddress)\r | |
5226 | );\r | |
5227 | return (EFI_SUCCESS);\r | |
5228 | }\r | |
5229 | \r | |
5230 | /**\r | |
5231 | Function to interpret and print out the Event Collector Endpoint Association structure\r | |
5232 | \r | |
5233 | @param[in] HeaderAddress The Address of this capability header.\r | |
5234 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5235 | **/\r | |
5236 | EFI_STATUS\r | |
705bffb5 JC |
5237 | PrintInterpretedExtendedCompatibilityECEA (\r |
5238 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5239 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5240 | )\r | |
5241 | {\r | |
5242 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r | |
5243 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r | |
5244 | \r | |
5245 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5246 | -1, -1, NULL,\r |
5247 | STRING_TOKEN (STR_PCI_EXT_CAP_ECEA),\r | |
5248 | gShellDebug1HiiHandle,\r | |
705bffb5 | 5249 | Header->AssociationBitmap\r |
ba0014b9 | 5250 | );\r |
705bffb5 JC |
5251 | DumpHex (\r |
5252 | 4,\r | |
5253 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5254 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r | |
5255 | (VOID *) (HeaderAddress)\r | |
5256 | );\r | |
5257 | return (EFI_SUCCESS);\r | |
5258 | }\r | |
5259 | \r | |
5260 | /**\r | |
5261 | Function to interpret and print out the ARI structure\r | |
5262 | \r | |
5263 | @param[in] HeaderAddress The Address of this capability header.\r | |
5264 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5265 | **/\r | |
5266 | EFI_STATUS\r | |
705bffb5 JC |
5267 | PrintInterpretedExtendedCompatibilityAri (\r |
5268 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5269 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5270 | )\r | |
5271 | {\r | |
5272 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r | |
5273 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r | |
5274 | \r | |
5275 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5276 | -1, -1, NULL,\r |
5277 | STRING_TOKEN (STR_PCI_EXT_CAP_ARI),\r | |
5278 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5279 | Header->AriCapability,\r |
5280 | Header->AriControl\r | |
ba0014b9 | 5281 | );\r |
705bffb5 JC |
5282 | DumpHex (\r |
5283 | 4,\r | |
5284 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5285 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r | |
5286 | (VOID *) (HeaderAddress)\r | |
5287 | );\r | |
5288 | return (EFI_SUCCESS);\r | |
5289 | }\r | |
5290 | \r | |
5291 | /**\r | |
5292 | Function to interpret and print out the DPA structure\r | |
5293 | \r | |
5294 | @param[in] HeaderAddress The Address of this capability header.\r | |
5295 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5296 | **/\r | |
5297 | EFI_STATUS\r | |
705bffb5 JC |
5298 | PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r |
5299 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5300 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5301 | )\r | |
5302 | {\r | |
5303 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r | |
5304 | UINT8 LinkCount;\r | |
5305 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r | |
5306 | \r | |
5307 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5308 | -1, -1, NULL,\r |
5309 | STRING_TOKEN (STR_PCI_EXT_CAP_DPA),\r | |
5310 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5311 | Header->DpaCapability,\r |
5312 | Header->DpaLatencyIndicator,\r | |
5313 | Header->DpaStatus,\r | |
5314 | Header->DpaControl\r | |
ba0014b9 | 5315 | );\r |
705bffb5 JC |
5316 | for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r |
5317 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5318 | -1, -1, NULL,\r |
5319 | STRING_TOKEN (STR_PCI_EXT_CAP_DPA2),\r | |
5320 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5321 | LinkCount+1,\r |
5322 | Header->DpaPowerAllocationArray[LinkCount]\r | |
5323 | );\r | |
5324 | }\r | |
5325 | DumpHex (\r | |
5326 | 4,\r | |
5327 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5328 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r | |
5329 | (VOID *) (HeaderAddress)\r | |
5330 | );\r | |
5331 | return (EFI_SUCCESS);\r | |
5332 | }\r | |
5333 | \r | |
5334 | /**\r | |
5335 | Function to interpret and print out the link declaration structure\r | |
5336 | \r | |
5337 | @param[in] HeaderAddress The Address of this capability header.\r | |
5338 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5339 | **/\r | |
5340 | EFI_STATUS\r | |
705bffb5 JC |
5341 | PrintInterpretedExtendedCompatibilityLinkDeclaration (\r |
5342 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5343 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5344 | )\r | |
5345 | {\r | |
5346 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r | |
5347 | UINT8 LinkCount;\r | |
5348 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r | |
5349 | \r | |
5350 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5351 | -1, -1, NULL,\r |
5352 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR),\r | |
5353 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5354 | Header->ElementSelfDescription\r |
5355 | );\r | |
5356 | \r | |
5357 | for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r | |
5358 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5359 | -1, -1, NULL,\r |
5360 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2),\r | |
5361 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5362 | LinkCount+1,\r |
5363 | Header->LinkEntry[LinkCount]\r | |
5364 | );\r | |
5365 | }\r | |
5366 | DumpHex (\r | |
5367 | 4,\r | |
5368 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5369 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r | |
5370 | (VOID *) (HeaderAddress)\r | |
5371 | );\r | |
5372 | return (EFI_SUCCESS);\r | |
5373 | }\r | |
5374 | \r | |
5375 | /**\r | |
5376 | Function to interpret and print out the Advanced Error Reporting structure\r | |
5377 | \r | |
5378 | @param[in] HeaderAddress The Address of this capability header.\r | |
5379 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5380 | **/\r | |
5381 | EFI_STATUS\r | |
705bffb5 JC |
5382 | PrintInterpretedExtendedCompatibilityAer (\r |
5383 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5384 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5385 | )\r | |
5386 | {\r | |
5387 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r | |
5388 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r | |
5389 | \r | |
5390 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5391 | -1, -1, NULL,\r |
5392 | STRING_TOKEN (STR_PCI_EXT_CAP_AER),\r | |
5393 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5394 | Header->UncorrectableErrorStatus,\r |
5395 | Header->UncorrectableErrorMask,\r | |
5396 | Header->UncorrectableErrorSeverity,\r | |
5397 | Header->CorrectableErrorStatus,\r | |
5398 | Header->CorrectableErrorMask,\r | |
5399 | Header->AdvancedErrorCapabilitiesAndControl,\r | |
231ad7d8 QS |
5400 | Header->HeaderLog[0],\r |
5401 | Header->HeaderLog[1],\r | |
5402 | Header->HeaderLog[2],\r | |
5403 | Header->HeaderLog[3],\r | |
705bffb5 JC |
5404 | Header->RootErrorCommand,\r |
5405 | Header->RootErrorStatus,\r | |
5406 | Header->ErrorSourceIdentification,\r | |
5407 | Header->CorrectableErrorSourceIdentification,\r | |
5408 | Header->TlpPrefixLog[0],\r | |
5409 | Header->TlpPrefixLog[1],\r | |
5410 | Header->TlpPrefixLog[2],\r | |
5411 | Header->TlpPrefixLog[3]\r | |
5412 | );\r | |
5413 | DumpHex (\r | |
5414 | 4,\r | |
5415 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5416 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r | |
5417 | (VOID *) (HeaderAddress)\r | |
5418 | );\r | |
5419 | return (EFI_SUCCESS);\r | |
5420 | }\r | |
5421 | \r | |
9f7f0697 JC |
5422 | /**\r |
5423 | Function to interpret and print out the multicast structure\r | |
5424 | \r | |
5425 | @param[in] HeaderAddress The Address of this capability header.\r | |
5426 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5427 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5428 | **/\r | |
5429 | EFI_STATUS\r | |
9f7f0697 JC |
5430 | PrintInterpretedExtendedCompatibilityMulticast (\r |
5431 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5432 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r | |
0c84a69f | 5433 | IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r |
9f7f0697 JC |
5434 | )\r |
5435 | {\r | |
5436 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r | |
5437 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r | |
5438 | \r | |
5439 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5440 | -1, -1, NULL,\r |
5441 | STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST),\r | |
5442 | gShellDebug1HiiHandle,\r | |
9f7f0697 JC |
5443 | Header->MultiCastCapability,\r |
5444 | Header->MulticastControl,\r | |
5445 | Header->McBaseAddress,\r | |
5446 | Header->McReceiveAddress,\r | |
5447 | Header->McBlockAll,\r | |
5448 | Header->McBlockUntranslated,\r | |
5449 | Header->McOverlayBar\r | |
5450 | );\r | |
5451 | \r | |
5452 | DumpHex (\r | |
5453 | 4,\r | |
5454 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5455 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r | |
5456 | (VOID *) (HeaderAddress)\r | |
5457 | );\r | |
5458 | \r | |
5459 | return (EFI_SUCCESS);\r | |
5460 | }\r | |
5461 | \r | |
5462 | /**\r | |
5463 | Function to interpret and print out the virtual channel and multi virtual channel structure\r | |
5464 | \r | |
5465 | @param[in] HeaderAddress The Address of this capability header.\r | |
5466 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5467 | **/\r | |
5468 | EFI_STATUS\r | |
9f7f0697 JC |
5469 | PrintInterpretedExtendedCompatibilityVirtualChannel (\r |
5470 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5471 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5472 | )\r | |
5473 | {\r | |
5474 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r | |
5475 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r | |
5476 | UINT32 ItemCount;\r | |
5477 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r | |
5478 | \r | |
5479 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5480 | -1, -1, NULL,\r |
5481 | STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE),\r | |
5482 | gShellDebug1HiiHandle,\r | |
9f7f0697 JC |
5483 | Header->ExtendedVcCount,\r |
5484 | Header->PortVcCapability1,\r | |
5485 | Header->PortVcCapability2,\r | |
5486 | Header->VcArbTableOffset,\r | |
5487 | Header->PortVcControl,\r | |
5488 | Header->PortVcStatus\r | |
5489 | );\r | |
5490 | for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r | |
5491 | CapabilityItem = &Header->Capability[ItemCount];\r | |
5492 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5493 | -1, -1, NULL,\r |
5494 | STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM),\r | |
5495 | gShellDebug1HiiHandle,\r | |
9f7f0697 JC |
5496 | ItemCount+1,\r |
5497 | CapabilityItem->VcResourceCapability,\r | |
5498 | CapabilityItem->PortArbTableOffset,\r | |
5499 | CapabilityItem->VcResourceControl,\r | |
5500 | CapabilityItem->VcResourceStatus\r | |
5501 | );\r | |
5502 | }\r | |
5503 | \r | |
5504 | DumpHex (\r | |
5505 | 4,\r | |
5506 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
26ca6f7e RN |
5507 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY)\r |
5508 | + Header->ExtendedVcCount * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC),\r | |
9f7f0697 JC |
5509 | (VOID *) (HeaderAddress)\r |
5510 | );\r | |
5511 | \r | |
5512 | return (EFI_SUCCESS);\r | |
5513 | }\r | |
5514 | \r | |
5515 | /**\r | |
5516 | Function to interpret and print out the resizeable bar structure\r | |
5517 | \r | |
5518 | @param[in] HeaderAddress The Address of this capability header.\r | |
5519 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5520 | **/\r | |
5521 | EFI_STATUS\r | |
9f7f0697 JC |
5522 | PrintInterpretedExtendedCompatibilityResizeableBar (\r |
5523 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5524 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5525 | )\r | |
5526 | {\r | |
5527 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r | |
5528 | UINT32 ItemCount;\r | |
5529 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r | |
5530 | \r | |
5531 | for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r | |
5532 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5533 | -1, -1, NULL,\r |
5534 | STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR),\r | |
5535 | gShellDebug1HiiHandle,\r | |
9f7f0697 JC |
5536 | ItemCount+1,\r |
5537 | Header->Capability[ItemCount].ResizableBarCapability,\r | |
5538 | Header->Capability[ItemCount].ResizableBarControl\r | |
5539 | );\r | |
5540 | }\r | |
5541 | \r | |
5542 | DumpHex (\r | |
5543 | 4,\r | |
5544 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5545 | (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r | |
5546 | (VOID *) (HeaderAddress)\r | |
5547 | );\r | |
5548 | \r | |
5549 | return (EFI_SUCCESS);\r | |
5550 | }\r | |
5551 | \r | |
5552 | /**\r | |
5553 | Function to interpret and print out the TPH structure\r | |
5554 | \r | |
5555 | @param[in] HeaderAddress The Address of this capability header.\r | |
5556 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5557 | **/\r | |
5558 | EFI_STATUS\r | |
9f7f0697 JC |
5559 | PrintInterpretedExtendedCompatibilityTph (\r |
5560 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5561 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
5562 | )\r | |
5563 | {\r | |
5564 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r | |
5565 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r | |
5566 | \r | |
5567 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5568 | -1, -1, NULL,\r |
5569 | STRING_TOKEN (STR_PCI_EXT_CAP_TPH),\r | |
5570 | gShellDebug1HiiHandle,\r | |
9f7f0697 JC |
5571 | Header->TphRequesterCapability,\r |
5572 | Header->TphRequesterControl\r | |
5573 | );\r | |
5574 | DumpHex (\r | |
5575 | 8,\r | |
5576 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r | |
5577 | GET_TPH_TABLE_SIZE(Header),\r | |
5578 | (VOID *)Header->TphStTable\r | |
5579 | );\r | |
5580 | \r | |
5581 | DumpHex (\r | |
5582 | 4,\r | |
5583 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
5584 | sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r | |
5585 | (VOID *) (HeaderAddress)\r | |
5586 | );\r | |
5587 | \r | |
5588 | return (EFI_SUCCESS);\r | |
5589 | }\r | |
5590 | \r | |
5591 | /**\r | |
5592 | Function to interpret and print out the secondary PCIe capability structure\r | |
5593 | \r | |
5594 | @param[in] HeaderAddress The Address of this capability header.\r | |
5595 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5596 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5597 | **/\r | |
5598 | EFI_STATUS\r | |
9f7f0697 JC |
5599 | PrintInterpretedExtendedCompatibilitySecondary (\r |
5600 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
5601 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r | |
0c84a69f | 5602 | IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
9f7f0697 JC |
5603 | )\r |
5604 | {\r | |
5605 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r | |
5606 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r | |
5607 | \r | |
5608 | ShellPrintHiiEx(\r | |
ba0014b9 LG |
5609 | -1, -1, NULL,\r |
5610 | STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY),\r | |
5611 | gShellDebug1HiiHandle,\r | |
0c84a69f | 5612 | Header->LinkControl3.Uint32,\r |
9f7f0697 JC |
5613 | Header->LaneErrorStatus\r |
5614 | );\r | |
5615 | DumpHex (\r | |
5616 | 8,\r | |
5617 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r | |
0c84a69f | 5618 | PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r |
9f7f0697 JC |
5619 | (VOID *)Header->EqualizationControl\r |
5620 | );\r | |
5621 | \r | |
5622 | DumpHex (\r | |
5623 | 4,\r | |
5624 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r | |
0c84a69f RN |
5625 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE) - sizeof (Header->EqualizationControl)\r |
5626 | + PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r | |
9f7f0697 JC |
5627 | (VOID *) (HeaderAddress)\r |
5628 | );\r | |
5629 | \r | |
5630 | return (EFI_SUCCESS);\r | |
5631 | }\r | |
5632 | \r | |
705bffb5 JC |
5633 | /**\r |
5634 | Display Pcie extended capability details\r | |
5635 | \r | |
5636 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5637 | @param[in] HeaderAddress The address of this capability header.\r | |
5638 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5639 | **/\r | |
5640 | EFI_STATUS\r | |
705bffb5 | 5641 | PrintPciExtendedCapabilityDetails(\r |
ba0014b9 | 5642 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r |
705bffb5 | 5643 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
0c84a69f | 5644 | IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r |
705bffb5 JC |
5645 | )\r |
5646 | {\r | |
5647 | switch (HeaderAddress->CapabilityId){\r | |
5648 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r | |
5649 | return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5650 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r |
5651 | return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5652 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r |
5653 | return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5654 | case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r |
5655 | return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5656 | case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r |
5657 | return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5658 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r |
5659 | return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5660 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r |
5661 | return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5662 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r |
5663 | return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5664 | case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r |
5665 | return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5666 | case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r |
5667 | return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5668 | case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r |
5669 | return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5670 | case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r |
5671 | return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r | |
705bffb5 JC |
5672 | case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r |
5673 | case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r | |
9f7f0697 | 5674 | return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r |
ba0014b9 | 5675 | case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID:\r |
9f7f0697 JC |
5676 | //\r |
5677 | // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r | |
5678 | //\r | |
5679 | return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r | |
705bffb5 | 5680 | case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r |
9f7f0697 | 5681 | return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 5682 | case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r |
9f7f0697 | 5683 | return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 5684 | case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r |
9f7f0697 | 5685 | return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r |
705bffb5 JC |
5686 | default:\r |
5687 | ShellPrintEx (-1, -1,\r | |
5688 | L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r | |
5689 | HeaderAddress->CapabilityId\r | |
5690 | );\r | |
5691 | return EFI_SUCCESS;\r | |
705bffb5 JC |
5692 | };\r |
5693 | \r | |
5694 | }\r | |
5695 | \r | |
a1d4bfcc | 5696 | /**\r |
5697 | Display Pcie device structure.\r | |
5698 | \r | |
33cc487c RN |
5699 | @param[in] PciExpressCap PCI Express capability buffer.\r |
5700 | @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r | |
5701 | @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r | |
a1d4bfcc | 5702 | **/\r |
33cc487c | 5703 | VOID\r |
5d73d92f | 5704 | PciExplainPciExpress (\r |
33cc487c RN |
5705 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r |
5706 | IN UINT8 *ExtendedConfigSpace,\r | |
5707 | IN CONST UINT16 ExtendedCapability\r | |
5d73d92f | 5708 | )\r |
5709 | {\r | |
0c84a69f RN |
5710 | UINT8 DevicePortType;\r |
5711 | UINTN Index;\r | |
5712 | UINT8 *RegAddr;\r | |
5713 | UINTN RegValue;\r | |
5714 | PCI_EXP_EXT_HDR *ExtHdr;\r | |
5d73d92f | 5715 | \r |
33cc487c | 5716 | DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r |
5d73d92f | 5717 | \r |
c37e0f16 | 5718 | ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r |
5d73d92f | 5719 | \r |
5720 | for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r | |
5721 | if (ShellGetExecutionBreakFlag()) {\r | |
33cc487c | 5722 | return;\r |
5d73d92f | 5723 | }\r |
33cc487c | 5724 | RegAddr = (UINT8 *) PciExpressCap + PcieExplainList[Index].Offset;\r |
5d73d92f | 5725 | switch (PcieExplainList[Index].Width) {\r |
5726 | case FieldWidthUINT8:\r | |
5727 | RegValue = *(UINT8 *) RegAddr;\r | |
5728 | break;\r | |
5729 | case FieldWidthUINT16:\r | |
5730 | RegValue = *(UINT16 *) RegAddr;\r | |
5731 | break;\r | |
5732 | case FieldWidthUINT32:\r | |
5733 | RegValue = *(UINT32 *) RegAddr;\r | |
5734 | break;\r | |
5735 | default:\r | |
5736 | RegValue = 0;\r | |
5737 | break;\r | |
5738 | }\r | |
5739 | ShellPrintHiiEx(-1, -1, NULL,\r | |
5740 | PcieExplainList[Index].Token,\r | |
5741 | gShellDebug1HiiHandle,\r | |
5742 | PcieExplainList[Index].Offset,\r | |
5743 | RegValue\r | |
5744 | );\r | |
5745 | if (PcieExplainList[Index].Func == NULL) {\r | |
5746 | continue;\r | |
5747 | }\r | |
5748 | switch (PcieExplainList[Index].Type) {\r | |
5749 | case PcieExplainTypeLink:\r | |
5750 | //\r | |
5751 | // Link registers should not be used by\r | |
5752 | // a) Root Complex Integrated Endpoint\r | |
5753 | // b) Root Complex Event Collector\r | |
5754 | //\r | |
0c84a69f RN |
5755 | if (DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT ||\r |
5756 | DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r | |
5d73d92f | 5757 | continue;\r |
5758 | }\r | |
5759 | break;\r | |
5760 | case PcieExplainTypeSlot:\r | |
5761 | //\r | |
5762 | // Slot registers are only valid for\r | |
5763 | // a) Root Port of PCI Express Root Complex\r | |
5764 | // b) Downstream Port of PCI Express Switch\r | |
5765 | // and when SlotImplemented bit is set in PCIE cap register.\r | |
5766 | //\r | |
0c84a69f RN |
5767 | if ((DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT &&\r |
5768 | DevicePortType != PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT) ||\r | |
33cc487c | 5769 | !PciExpressCap->Capability.Bits.SlotImplemented) {\r |
5d73d92f | 5770 | continue;\r |
5771 | }\r | |
5772 | break;\r | |
5773 | case PcieExplainTypeRoot:\r | |
5774 | //\r | |
5775 | // Root registers are only valid for\r | |
5776 | // Root Port of PCI Express Root Complex\r | |
5777 | //\r | |
0c84a69f | 5778 | if (DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT) {\r |
5d73d92f | 5779 | continue;\r |
5780 | }\r | |
5781 | break;\r | |
5782 | default:\r | |
5783 | break;\r | |
5784 | }\r | |
33cc487c | 5785 | PcieExplainList[Index].Func (PciExpressCap);\r |
5d73d92f | 5786 | }\r |
5787 | \r | |
33cc487c | 5788 | ExtHdr = (PCI_EXP_EXT_HDR*)ExtendedConfigSpace;\r |
c831a2c3 | 5789 | while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r |
705bffb5 | 5790 | //\r |
c831a2c3 | 5791 | // Process this item\r |
705bffb5 | 5792 | //\r |
33cc487c | 5793 | if (ExtendedCapability == 0xFFFF || ExtendedCapability == ExtHdr->CapabilityId) {\r |
705bffb5 | 5794 | //\r |
c831a2c3 | 5795 | // Print this item\r |
705bffb5 | 5796 | //\r |
33cc487c | 5797 | PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExtendedConfigSpace, ExtHdr, PciExpressCap);\r |
c831a2c3 | 5798 | }\r |
5d73d92f | 5799 | \r |
c831a2c3 RN |
5800 | //\r |
5801 | // Advance to the next item if it exists\r | |
5802 | //\r | |
5803 | if (ExtHdr->NextCapabilityOffset != 0) {\r | |
33cc487c | 5804 | ExtHdr = (PCI_EXP_EXT_HDR*)(ExtendedConfigSpace + ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);\r |
c831a2c3 RN |
5805 | } else {\r |
5806 | break;\r | |
705bffb5 | 5807 | }\r |
d8f8021c | 5808 | }\r |
5d73d92f | 5809 | }\r |