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529a5a86 MK |
1 | /** @file\r |
2 | Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r | |
3 | \r | |
3eb69b08 | 4 | Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>\r |
241f9149 LD |
5 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r |
6 | \r | |
0acd8697 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
529a5a86 MK |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | #ifndef _CPU_PISMMCPUDXESMM_H_\r | |
12 | #define _CPU_PISMMCPUDXESMM_H_\r | |
13 | \r | |
14 | #include <PiSmm.h>\r | |
15 | \r | |
16 | #include <Protocol/MpService.h>\r | |
17 | #include <Protocol/SmmConfiguration.h>\r | |
18 | #include <Protocol/SmmCpu.h>\r | |
19 | #include <Protocol/SmmAccess2.h>\r | |
529a5a86 MK |
20 | #include <Protocol/SmmReadyToLock.h>\r |
21 | #include <Protocol/SmmCpuService.h>\r | |
827330cc | 22 | #include <Protocol/SmmMemoryAttribute.h>\r |
529a5a86 MK |
23 | \r |
24 | #include <Guid/AcpiS3Context.h>\r | |
8a2e1a9d | 25 | #include <Guid/MemoryAttributesTable.h>\r |
717fb604 | 26 | #include <Guid/PiSmmMemoryAttributesTable.h>\r |
529a5a86 MK |
27 | \r |
28 | #include <Library/BaseLib.h>\r | |
29 | #include <Library/IoLib.h>\r | |
30 | #include <Library/TimerLib.h>\r | |
529a5a86 MK |
31 | #include <Library/SynchronizationLib.h>\r |
32 | #include <Library/DebugLib.h>\r | |
33 | #include <Library/BaseMemoryLib.h>\r | |
34 | #include <Library/PcdLib.h>\r | |
529a5a86 MK |
35 | #include <Library/MtrrLib.h>\r |
36 | #include <Library/SmmCpuPlatformHookLib.h>\r | |
37 | #include <Library/SmmServicesTableLib.h>\r | |
38 | #include <Library/MemoryAllocationLib.h>\r | |
39 | #include <Library/UefiBootServicesTableLib.h>\r | |
40 | #include <Library/UefiRuntimeServicesTableLib.h>\r | |
41 | #include <Library/DebugAgentLib.h>\r | |
8a2e1a9d | 42 | #include <Library/UefiLib.h>\r |
529a5a86 MK |
43 | #include <Library/HobLib.h>\r |
44 | #include <Library/LocalApicLib.h>\r | |
45 | #include <Library/UefiCpuLib.h>\r | |
46 | #include <Library/CpuExceptionHandlerLib.h>\r | |
47 | #include <Library/ReportStatusCodeLib.h>\r | |
48 | #include <Library/SmmCpuFeaturesLib.h>\r | |
49 | #include <Library/PeCoffGetEntryPointLib.h>\r | |
93324390 | 50 | #include <Library/RegisterCpuFeaturesLib.h>\r |
529a5a86 MK |
51 | \r |
52 | #include <AcpiCpuData.h>\r | |
53 | #include <CpuHotPlugData.h>\r | |
54 | \r | |
55 | #include <Register/Cpuid.h>\r | |
f85d3ce2 | 56 | #include <Register/Msr.h>\r |
529a5a86 MK |
57 | \r |
58 | #include "CpuService.h"\r | |
59 | #include "SmmProfile.h"\r | |
60 | \r | |
3eb69b08 JY |
61 | //\r |
62 | // CET definition\r | |
63 | //\r | |
64 | #define CPUID_CET_SS BIT7\r | |
65 | #define CPUID_CET_IBT BIT20\r | |
66 | \r | |
67 | #define CR4_CET_ENABLE BIT23\r | |
68 | \r | |
69 | #define MSR_IA32_S_CET 0x6A2\r | |
70 | #define MSR_IA32_PL0_SSP 0x6A4\r | |
71 | #define MSR_IA32_INTERRUPT_SSP_TABLE_ADDR 0x6A8\r | |
72 | \r | |
73 | typedef union {\r | |
74 | struct {\r | |
75 | // enable shadow stacks\r | |
76 | UINT32 SH_STK_ENP:1;\r | |
77 | // enable the WRSS{D,Q}W instructions.\r | |
78 | UINT32 WR_SHSTK_EN:1;\r | |
79 | // enable tracking of indirect call/jmp targets to be ENDBRANCH instruction.\r | |
80 | UINT32 ENDBR_EN:1;\r | |
81 | // enable legacy compatibility treatment for indirect call/jmp tracking.\r | |
82 | UINT32 LEG_IW_EN:1;\r | |
83 | // enable use of no-track prefix on indirect call/jmp.\r | |
84 | UINT32 NO_TRACK_EN:1;\r | |
85 | // disable suppression of CET indirect branch tracking on legacy compatibility.\r | |
86 | UINT32 SUPPRESS_DIS:1;\r | |
87 | UINT32 RSVD:4;\r | |
88 | // indirect branch tracking is suppressed.\r | |
89 | // This bit can be written to 1 only if TRACKER is written as IDLE.\r | |
90 | UINT32 SUPPRESS:1;\r | |
91 | // Value of the endbranch state machine\r | |
92 | // Values: IDLE (0), WAIT_FOR_ENDBRANCH(1).\r | |
93 | UINT32 TRACKER:1;\r | |
94 | // linear address of a bitmap in memory indicating valid\r | |
95 | // pages as target of CALL/JMP_indirect that do not land on ENDBRANCH when CET is enabled\r | |
96 | // and not suppressed. Valid when ENDBR_EN is 1. Must be machine canonical when written on\r | |
97 | // parts that support 64 bit mode. On parts that do not support 64 bit mode, the bits 63:32 are\r | |
98 | // reserved and must be 0. This value is extended by 12 bits at the low end to form the base address\r | |
99 | // (this automatically aligns the address on a 4-Kbyte boundary).\r | |
100 | UINT32 EB_LEG_BITMAP_BASE_low:12;\r | |
101 | UINT32 EB_LEG_BITMAP_BASE_high:32;\r | |
102 | } Bits;\r | |
103 | UINT64 Uint64;\r | |
104 | } MSR_IA32_CET;\r | |
105 | \r | |
529a5a86 MK |
106 | //\r |
107 | // MSRs required for configuration of SMM Code Access Check\r | |
108 | //\r | |
109 | #define EFI_MSR_SMM_MCA_CAP 0x17D\r | |
110 | #define SMM_CODE_ACCESS_CHK_BIT BIT58\r | |
111 | \r | |
112 | #define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r | |
113 | #define SMM_CODE_CHK_EN_BIT BIT2\r | |
114 | \r | |
115 | ///\r | |
116 | /// Page Table Entry\r | |
117 | ///\r | |
118 | #define IA32_PG_P BIT0\r | |
119 | #define IA32_PG_RW BIT1\r | |
881520ea | 120 | #define IA32_PG_U BIT2\r |
529a5a86 MK |
121 | #define IA32_PG_WT BIT3\r |
122 | #define IA32_PG_CD BIT4\r | |
123 | #define IA32_PG_A BIT5\r | |
881520ea | 124 | #define IA32_PG_D BIT6\r |
529a5a86 MK |
125 | #define IA32_PG_PS BIT7\r |
126 | #define IA32_PG_PAT_2M BIT12\r | |
127 | #define IA32_PG_PAT_4K IA32_PG_PS\r | |
128 | #define IA32_PG_PMNT BIT62\r | |
129 | #define IA32_PG_NX BIT63\r | |
130 | \r | |
717fb604 | 131 | #define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r |
881520ea JY |
132 | //\r |
133 | // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r | |
134 | // X64 PAE PDPTE does not have such restriction\r | |
135 | //\r | |
136 | #define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r | |
137 | \r | |
717fb604 JY |
138 | #define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r |
139 | \r | |
140 | #define PAGING_4K_MASK 0xFFF\r | |
141 | #define PAGING_2M_MASK 0x1FFFFF\r | |
142 | #define PAGING_1G_MASK 0x3FFFFFFF\r | |
143 | \r | |
144 | #define PAGING_PAE_INDEX_MASK 0x1FF\r | |
145 | \r | |
146 | #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r | |
147 | #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r | |
148 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r | |
149 | \r | |
7ed6f781 JF |
150 | #define SMRR_MAX_ADDRESS BASE_4GB\r |
151 | \r | |
717fb604 JY |
152 | typedef enum {\r |
153 | PageNone,\r | |
154 | Page4K,\r | |
155 | Page2M,\r | |
156 | Page1G,\r | |
157 | } PAGE_ATTRIBUTE;\r | |
158 | \r | |
159 | typedef struct {\r | |
160 | PAGE_ATTRIBUTE Attribute;\r | |
161 | UINT64 Length;\r | |
162 | UINT64 AddressMask;\r | |
163 | } PAGE_ATTRIBUTE_TABLE;\r | |
164 | \r | |
529a5a86 MK |
165 | //\r |
166 | // Size of Task-State Segment defined in IA32 Manual\r | |
167 | //\r | |
168 | #define TSS_SIZE 104\r | |
3eb69b08 | 169 | #define EXCEPTION_TSS_SIZE (TSS_SIZE + 4) // Add 4 bytes SSP\r |
529a5a86 MK |
170 | #define TSS_X64_IST1_OFFSET 36\r |
171 | #define TSS_IA32_CR3_OFFSET 28\r | |
172 | #define TSS_IA32_ESP_OFFSET 56\r | |
3eb69b08 | 173 | #define TSS_IA32_SSP_OFFSET 104\r |
529a5a86 | 174 | \r |
717fb604 JY |
175 | #define CR0_WP BIT16\r |
176 | \r | |
529a5a86 MK |
177 | //\r |
178 | // Code select value\r | |
179 | //\r | |
180 | #define PROTECT_MODE_CODE_SEGMENT 0x08\r | |
181 | #define LONG_MODE_CODE_SEGMENT 0x38\r | |
182 | \r | |
183 | //\r | |
184 | // The size 0x20 must be bigger than\r | |
185 | // the size of template code of SmmInit. Currently,\r | |
186 | // the size of SmmInit requires the 0x16 Bytes buffer\r | |
187 | // at least.\r | |
188 | //\r | |
189 | #define BACK_BUF_SIZE 0x20\r | |
190 | \r | |
191 | #define EXCEPTION_VECTOR_NUMBER 0x20\r | |
192 | \r | |
193 | #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r | |
194 | \r | |
195 | typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r | |
196 | #define ARRIVAL_EXCEPTION_BLOCKED 0x1\r | |
197 | #define ARRIVAL_EXCEPTION_DELAYED 0x2\r | |
198 | #define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r | |
199 | \r | |
200 | //\r | |
201 | // Private structure for the SMM CPU module that is stored in DXE Runtime memory\r | |
202 | // Contains the SMM Configuration Protocols that is produced.\r | |
203 | // Contains a mix of DXE and SMM contents. All the fields must be used properly.\r | |
204 | //\r | |
205 | #define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r | |
206 | \r | |
207 | typedef struct {\r | |
208 | UINTN Signature;\r | |
209 | \r | |
210 | EFI_HANDLE SmmCpuHandle;\r | |
211 | \r | |
212 | EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r | |
213 | SMM_CPU_OPERATION *Operation;\r | |
214 | UINTN *CpuSaveStateSize;\r | |
215 | VOID **CpuSaveState;\r | |
216 | \r | |
217 | EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r | |
218 | EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r | |
219 | EFI_SMM_ENTRY_POINT SmmCoreEntry;\r | |
220 | \r | |
221 | EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r | |
222 | } SMM_CPU_PRIVATE_DATA;\r | |
223 | \r | |
224 | extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r | |
225 | extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r | |
226 | extern UINTN mMaxNumberOfCpus;\r | |
227 | extern UINTN mNumberOfCpus;\r | |
529a5a86 MK |
228 | extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r |
229 | \r | |
230 | ///\r | |
231 | /// The mode of the CPU at the time an SMI occurs\r | |
232 | ///\r | |
233 | extern UINT8 mSmmSaveStateRegisterLma;\r | |
234 | \r | |
529a5a86 MK |
235 | //\r |
236 | // SMM CPU Protocol function prototypes.\r | |
237 | //\r | |
238 | \r | |
239 | /**\r | |
240 | Read information from the CPU save state.\r | |
241 | \r | |
242 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
243 | @param Width The number of bytes to read from the CPU save state.\r | |
244 | @param Register Specifies the CPU register to read form the save state.\r | |
245 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
246 | @param Buffer Upon return, this holds the CPU register value read from the save state.\r | |
247 | \r | |
248 | @retval EFI_SUCCESS The register was read from Save State\r | |
249 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
250 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
251 | \r | |
252 | **/\r | |
253 | EFI_STATUS\r | |
254 | EFIAPI\r | |
255 | SmmReadSaveState (\r | |
256 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
257 | IN UINTN Width,\r | |
258 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
259 | IN UINTN CpuIndex,\r | |
260 | OUT VOID *Buffer\r | |
261 | );\r | |
262 | \r | |
263 | /**\r | |
264 | Write data to the CPU save state.\r | |
265 | \r | |
266 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
267 | @param Width The number of bytes to read from the CPU save state.\r | |
268 | @param Register Specifies the CPU register to write to the save state.\r | |
269 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
270 | @param Buffer Upon entry, this holds the new CPU register value.\r | |
271 | \r | |
272 | @retval EFI_SUCCESS The register was written from Save State\r | |
273 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
274 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r | |
275 | \r | |
276 | **/\r | |
277 | EFI_STATUS\r | |
278 | EFIAPI\r | |
279 | SmmWriteSaveState (\r | |
280 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
281 | IN UINTN Width,\r | |
282 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
283 | IN UINTN CpuIndex,\r | |
284 | IN CONST VOID *Buffer\r | |
285 | );\r | |
286 | \r | |
287 | /**\r | |
288 | Read a CPU Save State register on the target processor.\r | |
289 | \r | |
290 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
291 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
292 | \r | |
293 | This function supports reading a CPU Save State register in SMBase relocation handler.\r | |
294 | \r | |
295 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
296 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
297 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
298 | @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r | |
299 | \r | |
300 | @retval EFI_SUCCESS The register was read from Save State.\r | |
301 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
302 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
303 | \r | |
304 | **/\r | |
305 | EFI_STATUS\r | |
306 | EFIAPI\r | |
307 | ReadSaveStateRegister (\r | |
308 | IN UINTN CpuIndex,\r | |
309 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
310 | IN UINTN Width,\r | |
311 | OUT VOID *Buffer\r | |
312 | );\r | |
313 | \r | |
314 | /**\r | |
315 | Write value to a CPU Save State register on the target processor.\r | |
316 | \r | |
317 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
318 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
319 | \r | |
320 | This function supports writing a CPU Save State register in SMBase relocation handler.\r | |
321 | \r | |
322 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
323 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
324 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
325 | @param[in] Buffer Upon entry, this holds the new CPU register value.\r | |
326 | \r | |
327 | @retval EFI_SUCCESS The register was written to Save State.\r | |
328 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
329 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r | |
330 | \r | |
331 | **/\r | |
332 | EFI_STATUS\r | |
333 | EFIAPI\r | |
334 | WriteSaveStateRegister (\r | |
335 | IN UINTN CpuIndex,\r | |
336 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
337 | IN UINTN Width,\r | |
338 | IN CONST VOID *Buffer\r | |
339 | );\r | |
340 | \r | |
529a5a86 MK |
341 | extern CONST UINT8 gcSmmInitTemplate[];\r |
342 | extern CONST UINT16 gcSmmInitSize;\r | |
f0053e83 LE |
343 | X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0;\r |
344 | extern UINT32 mSmmCr0;\r | |
6b0841c1 | 345 | X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;\r |
351b49c1 LE |
346 | extern UINT32 mSmmCr4;\r |
347 | X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;\r | |
5830d2c3 | 348 | X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack;\r |
3eb69b08 JY |
349 | X86_ASSEMBLY_PATCH_LABEL mPatchCetSupported;\r |
350 | extern BOOLEAN mCetSupported;\r | |
529a5a86 MK |
351 | \r |
352 | /**\r | |
353 | Semaphore operation for all processor relocate SMMBase.\r | |
354 | **/\r | |
355 | VOID\r | |
356 | EFIAPI\r | |
357 | SmmRelocationSemaphoreComplete (\r | |
358 | VOID\r | |
359 | );\r | |
360 | \r | |
361 | ///\r | |
362 | /// The type of SMM CPU Information\r | |
363 | ///\r | |
364 | typedef struct {\r | |
ed3d5ecb | 365 | SPIN_LOCK *Busy;\r |
529a5a86 MK |
366 | volatile EFI_AP_PROCEDURE Procedure;\r |
367 | volatile VOID *Parameter;\r | |
ed3d5ecb JF |
368 | volatile UINT32 *Run;\r |
369 | volatile BOOLEAN *Present;\r | |
529a5a86 MK |
370 | } SMM_CPU_DATA_BLOCK;\r |
371 | \r | |
372 | typedef enum {\r | |
373 | SmmCpuSyncModeTradition,\r | |
374 | SmmCpuSyncModeRelaxedAp,\r | |
375 | SmmCpuSyncModeMax\r | |
376 | } SMM_CPU_SYNC_MODE;\r | |
377 | \r | |
378 | typedef struct {\r | |
379 | //\r | |
380 | // Pointer to an array. The array should be located immediately after this structure\r | |
381 | // so that UC cache-ability can be set together.\r | |
382 | //\r | |
383 | SMM_CPU_DATA_BLOCK *CpuData;\r | |
fe3a75bc | 384 | volatile UINT32 *Counter;\r |
529a5a86 | 385 | volatile UINT32 BspIndex;\r |
fe3a75bc JF |
386 | volatile BOOLEAN *InsideSmm;\r |
387 | volatile BOOLEAN *AllCpusInSync;\r | |
529a5a86 MK |
388 | volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r |
389 | volatile BOOLEAN SwitchBsp;\r | |
390 | volatile BOOLEAN *CandidateBsp;\r | |
391 | } SMM_DISPATCHER_MP_SYNC_DATA;\r | |
392 | \r | |
529a5a86 MK |
393 | #define SMM_PSD_OFFSET 0xfb00\r |
394 | \r | |
1d648531 JF |
395 | ///\r |
396 | /// All global semaphores' pointer\r | |
397 | ///\r | |
398 | typedef struct {\r | |
399 | volatile UINT32 *Counter;\r | |
400 | volatile BOOLEAN *InsideSmm;\r | |
401 | volatile BOOLEAN *AllCpusInSync;\r | |
402 | SPIN_LOCK *PFLock;\r | |
403 | SPIN_LOCK *CodeAccessCheckLock;\r | |
404 | } SMM_CPU_SEMAPHORE_GLOBAL;\r | |
405 | \r | |
4e920581 JF |
406 | ///\r |
407 | /// All semaphores for each processor\r | |
408 | ///\r | |
409 | typedef struct {\r | |
410 | SPIN_LOCK *Busy;\r | |
411 | volatile UINT32 *Run;\r | |
412 | volatile BOOLEAN *Present;\r | |
413 | } SMM_CPU_SEMAPHORE_CPU;\r | |
414 | \r | |
1d648531 JF |
415 | ///\r |
416 | /// All semaphores' information\r | |
417 | ///\r | |
418 | typedef struct {\r | |
419 | SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r | |
4e920581 | 420 | SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r |
1d648531 JF |
421 | } SMM_CPU_SEMAPHORES;\r |
422 | \r | |
529a5a86 | 423 | extern IA32_DESCRIPTOR gcSmiGdtr;\r |
717fb604 JY |
424 | extern EFI_PHYSICAL_ADDRESS mGdtBuffer;\r |
425 | extern UINTN mGdtBufferSize;\r | |
529a5a86 MK |
426 | extern IA32_DESCRIPTOR gcSmiIdtr;\r |
427 | extern VOID *gcSmiIdtrPtr;\r | |
529a5a86 | 428 | extern UINT64 gPhyMask;\r |
529a5a86 | 429 | extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r |
529a5a86 MK |
430 | extern UINTN mSmmStackArrayBase;\r |
431 | extern UINTN mSmmStackArrayEnd;\r | |
432 | extern UINTN mSmmStackSize;\r | |
433 | extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r | |
434 | extern IA32_DESCRIPTOR gcSmiInitGdtr;\r | |
dc99315b JF |
435 | extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r |
436 | extern UINTN mSemaphoreSize;\r | |
fe3a75bc JF |
437 | extern SPIN_LOCK *mPFLock;\r |
438 | extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r | |
7ed6f781 JF |
439 | extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;\r |
440 | extern UINTN mSmmCpuSmramRangeCount;\r | |
714c2603 | 441 | extern UINT8 mPhysicalAddressBits;\r |
529a5a86 | 442 | \r |
241f9149 LD |
443 | //\r |
444 | // Copy of the PcdPteMemoryEncryptionAddressOrMask\r | |
445 | //\r | |
446 | extern UINT64 mAddressEncMask;\r | |
447 | \r | |
529a5a86 MK |
448 | /**\r |
449 | Create 4G PageTable in SMRAM.\r | |
450 | \r | |
717fb604 | 451 | @param[in] Is32BitPageTable Whether the page table is 32-bit PAE\r |
529a5a86 MK |
452 | @return PageTable Address\r |
453 | \r | |
454 | **/\r | |
455 | UINT32\r | |
456 | Gen4GPageTable (\r | |
881520ea | 457 | IN BOOLEAN Is32BitPageTable\r |
529a5a86 MK |
458 | );\r |
459 | \r | |
460 | \r | |
461 | /**\r | |
462 | Initialize global data for MP synchronization.\r | |
463 | \r | |
3eb69b08 JY |
464 | @param Stacks Base address of SMI stack buffer for all processors.\r |
465 | @param StackSize Stack size for each processor in SMM.\r | |
466 | @param ShadowStackSize Shadow Stack size for each processor in SMM.\r | |
529a5a86 MK |
467 | \r |
468 | **/\r | |
469 | UINT32\r | |
470 | InitializeMpServiceData (\r | |
471 | IN VOID *Stacks,\r | |
3eb69b08 JY |
472 | IN UINTN StackSize,\r |
473 | IN UINTN ShadowStackSize\r | |
529a5a86 MK |
474 | );\r |
475 | \r | |
476 | /**\r | |
477 | Initialize Timer for SMM AP Sync.\r | |
478 | \r | |
479 | **/\r | |
480 | VOID\r | |
481 | InitializeSmmTimer (\r | |
482 | VOID\r | |
483 | );\r | |
484 | \r | |
485 | /**\r | |
486 | Start Timer for SMM AP Sync.\r | |
487 | \r | |
488 | **/\r | |
489 | UINT64\r | |
490 | EFIAPI\r | |
491 | StartSyncTimer (\r | |
492 | VOID\r | |
493 | );\r | |
494 | \r | |
495 | /**\r | |
496 | Check if the SMM AP Sync timer is timeout.\r | |
497 | \r | |
498 | @param Timer The start timer from the begin.\r | |
499 | \r | |
500 | **/\r | |
501 | BOOLEAN\r | |
502 | EFIAPI\r | |
503 | IsSyncTimerTimeout (\r | |
504 | IN UINT64 Timer\r | |
505 | );\r | |
506 | \r | |
507 | /**\r | |
508 | Initialize IDT for SMM Stack Guard.\r | |
509 | \r | |
510 | **/\r | |
511 | VOID\r | |
512 | EFIAPI\r | |
513 | InitializeIDTSmmStackGuard (\r | |
514 | VOID\r | |
515 | );\r | |
516 | \r | |
fe5f1949 JY |
517 | /**\r |
518 | Initialize Gdt for all processors.\r | |
717fb604 | 519 | \r |
fe5f1949 JY |
520 | @param[in] Cr3 CR3 value.\r |
521 | @param[out] GdtStepSize The step size for GDT table.\r | |
522 | \r | |
523 | @return GdtBase for processor 0.\r | |
524 | GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r | |
525 | **/\r | |
526 | VOID *\r | |
527 | InitGdt (\r | |
528 | IN UINTN Cr3,\r | |
529 | OUT UINTN *GdtStepSize\r | |
530 | );\r | |
531 | \r | |
529a5a86 MK |
532 | /**\r |
533 | \r | |
534 | Register the SMM Foundation entry point.\r | |
535 | \r | |
536 | @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r | |
537 | @param SmmEntryPoint SMM Foundation EntryPoint\r | |
538 | \r | |
539 | @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r | |
540 | \r | |
541 | **/\r | |
542 | EFI_STATUS\r | |
543 | EFIAPI\r | |
544 | RegisterSmmEntry (\r | |
545 | IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r | |
546 | IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r | |
547 | );\r | |
548 | \r | |
549 | /**\r | |
550 | Create PageTable for SMM use.\r | |
551 | \r | |
552 | @return PageTable Address\r | |
553 | \r | |
554 | **/\r | |
555 | UINT32\r | |
556 | SmmInitPageTable (\r | |
557 | VOID\r | |
558 | );\r | |
559 | \r | |
560 | /**\r | |
561 | Schedule a procedure to run on the specified CPU.\r | |
562 | \r | |
563 | @param Procedure The address of the procedure to run\r | |
564 | @param CpuIndex Target CPU number\r | |
565 | @param ProcArguments The parameter to pass to the procedure\r | |
566 | \r | |
567 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
568 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
569 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
570 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
571 | @retval EFI_SUCCESS - The procedure has been successfully scheduled\r | |
572 | \r | |
573 | **/\r | |
574 | EFI_STATUS\r | |
575 | EFIAPI\r | |
576 | SmmStartupThisAp (\r | |
577 | IN EFI_AP_PROCEDURE Procedure,\r | |
578 | IN UINTN CpuIndex,\r | |
579 | IN OUT VOID *ProcArguments OPTIONAL\r | |
580 | );\r | |
581 | \r | |
582 | /**\r | |
583 | Schedule a procedure to run on the specified CPU in a blocking fashion.\r | |
584 | \r | |
585 | @param Procedure The address of the procedure to run\r | |
586 | @param CpuIndex Target CPU Index\r | |
587 | @param ProcArguments The parameter to pass to the procedure\r | |
588 | \r | |
589 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
590 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
591 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
592 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
593 | @retval EFI_SUCCESS The procedure has been successfully scheduled\r | |
594 | \r | |
595 | **/\r | |
596 | EFI_STATUS\r | |
597 | EFIAPI\r | |
598 | SmmBlockingStartupThisAp (\r | |
599 | IN EFI_AP_PROCEDURE Procedure,\r | |
600 | IN UINTN CpuIndex,\r | |
601 | IN OUT VOID *ProcArguments OPTIONAL\r | |
602 | );\r | |
603 | \r | |
e4435f71 JY |
604 | /**\r |
605 | This function sets the attributes for the memory region specified by BaseAddress and\r | |
606 | Length from their current attributes to the attributes specified by Attributes.\r | |
607 | \r | |
608 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
609 | @param[in] Length The size in bytes of the memory region.\r | |
610 | @param[in] Attributes The bit mask of attributes to set for the memory region.\r | |
611 | \r | |
612 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
613 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
614 | BaseAddress and Length cannot be modified.\r | |
615 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
616 | Attributes specified an illegal combination of attributes that\r | |
617 | cannot be set together.\r | |
618 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
619 | the memory resource range.\r | |
620 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
621 | resource range specified by BaseAddress and Length.\r | |
622 | The bit mask of attributes is not support for the memory resource\r | |
623 | range specified by BaseAddress and Length.\r | |
624 | \r | |
625 | **/\r | |
626 | EFI_STATUS\r | |
627 | EFIAPI\r | |
628 | SmmSetMemoryAttributes (\r | |
629 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
630 | IN UINT64 Length,\r | |
631 | IN UINT64 Attributes\r | |
632 | );\r | |
633 | \r | |
634 | /**\r | |
635 | This function clears the attributes for the memory region specified by BaseAddress and\r | |
636 | Length from their current attributes to the attributes specified by Attributes.\r | |
637 | \r | |
638 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
639 | @param[in] Length The size in bytes of the memory region.\r | |
640 | @param[in] Attributes The bit mask of attributes to clear for the memory region.\r | |
641 | \r | |
642 | @retval EFI_SUCCESS The attributes were cleared for the memory region.\r | |
643 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
644 | BaseAddress and Length cannot be modified.\r | |
645 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
646 | Attributes specified an illegal combination of attributes that\r | |
647 | cannot be set together.\r | |
648 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
649 | the memory resource range.\r | |
650 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
651 | resource range specified by BaseAddress and Length.\r | |
652 | The bit mask of attributes is not support for the memory resource\r | |
653 | range specified by BaseAddress and Length.\r | |
654 | \r | |
655 | **/\r | |
656 | EFI_STATUS\r | |
657 | EFIAPI\r | |
658 | SmmClearMemoryAttributes (\r | |
659 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
660 | IN UINT64 Length,\r | |
661 | IN UINT64 Attributes\r | |
662 | );\r | |
663 | \r | |
529a5a86 MK |
664 | /**\r |
665 | Initialize MP synchronization data.\r | |
666 | \r | |
667 | **/\r | |
668 | VOID\r | |
669 | EFIAPI\r | |
670 | InitializeMpSyncData (\r | |
671 | VOID\r | |
672 | );\r | |
673 | \r | |
674 | /**\r | |
675 | \r | |
676 | Find out SMRAM information including SMRR base and SMRR size.\r | |
677 | \r | |
678 | @param SmrrBase SMRR base\r | |
679 | @param SmrrSize SMRR size\r | |
680 | \r | |
681 | **/\r | |
682 | VOID\r | |
683 | FindSmramInfo (\r | |
684 | OUT UINT32 *SmrrBase,\r | |
685 | OUT UINT32 *SmrrSize\r | |
686 | );\r | |
687 | \r | |
688 | /**\r | |
0bdc9e75 | 689 | Relocate SmmBases for each processor.\r |
529a5a86 | 690 | \r |
0bdc9e75 | 691 | Execute on first boot and all S3 resumes\r |
529a5a86 MK |
692 | \r |
693 | **/\r | |
694 | VOID\r | |
0bdc9e75 SZ |
695 | EFIAPI\r |
696 | SmmRelocateBases (\r | |
529a5a86 MK |
697 | VOID\r |
698 | );\r | |
699 | \r | |
700 | /**\r | |
701 | Page Fault handler for SMM use.\r | |
702 | \r | |
703 | @param InterruptType Defines the type of interrupt or exception that\r | |
704 | occurred on the processor.This parameter is processor architecture specific.\r | |
705 | @param SystemContext A pointer to the processor context when\r | |
706 | the interrupt occurred on the processor.\r | |
707 | **/\r | |
708 | VOID\r | |
709 | EFIAPI\r | |
710 | SmiPFHandler (\r | |
b8caae19 JF |
711 | IN EFI_EXCEPTION_TYPE InterruptType,\r |
712 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
529a5a86 MK |
713 | );\r |
714 | \r | |
715 | /**\r | |
716 | Perform the remaining tasks.\r | |
717 | \r | |
718 | **/\r | |
719 | VOID\r | |
720 | PerformRemainingTasks (\r | |
721 | VOID\r | |
722 | );\r | |
723 | \r | |
9f419739 JY |
724 | /**\r |
725 | Perform the pre tasks.\r | |
726 | \r | |
727 | **/\r | |
728 | VOID\r | |
729 | PerformPreTasks (\r | |
730 | VOID\r | |
731 | );\r | |
732 | \r | |
529a5a86 MK |
733 | /**\r |
734 | Initialize MSR spin lock by MSR index.\r | |
735 | \r | |
736 | @param MsrIndex MSR index value.\r | |
737 | \r | |
738 | **/\r | |
739 | VOID\r | |
740 | InitMsrSpinLockByIndex (\r | |
741 | IN UINT32 MsrIndex\r | |
742 | );\r | |
743 | \r | |
744 | /**\r | |
745 | Hook return address of SMM Save State so that semaphore code\r | |
746 | can be executed immediately after AP exits SMM to indicate to\r | |
747 | the BSP that an AP has exited SMM after SMBASE relocation.\r | |
748 | \r | |
749 | @param[in] CpuIndex The processor index.\r | |
750 | @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r | |
751 | immediately after AP exits SMM.\r | |
752 | \r | |
753 | **/\r | |
754 | VOID\r | |
755 | SemaphoreHook (\r | |
756 | IN UINTN CpuIndex,\r | |
757 | IN volatile BOOLEAN *RebasedFlag\r | |
758 | );\r | |
759 | \r | |
760 | /**\r | |
761 | Configure SMM Code Access Check feature for all processors.\r | |
762 | SMM Feature Control MSR will be locked after configuration.\r | |
763 | **/\r | |
764 | VOID\r | |
765 | ConfigSmmCodeAccessCheck (\r | |
766 | VOID\r | |
767 | );\r | |
768 | \r | |
769 | /**\r | |
770 | Hook the code executed immediately after an RSM instruction on the currently\r | |
771 | executing CPU. The mode of code executed immediately after RSM must be\r | |
772 | detected, and the appropriate hook must be selected. Always clear the auto\r | |
773 | HALT restart flag if it is set.\r | |
774 | \r | |
775 | @param[in] CpuIndex The processor index for the currently\r | |
776 | executing CPU.\r | |
777 | @param[in] CpuState Pointer to SMRAM Save State Map for the\r | |
778 | currently executing CPU.\r | |
779 | @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r | |
780 | 32-bit mode from 64-bit SMM.\r | |
781 | @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r | |
782 | same mode as SMM.\r | |
783 | \r | |
784 | @retval The value of the original instruction pointer before it was hooked.\r | |
785 | \r | |
786 | **/\r | |
787 | UINT64\r | |
788 | EFIAPI\r | |
789 | HookReturnFromSmm (\r | |
790 | IN UINTN CpuIndex,\r | |
791 | SMRAM_SAVE_STATE_MAP *CpuState,\r | |
792 | UINT64 NewInstructionPointer32,\r | |
793 | UINT64 NewInstructionPointer\r | |
794 | );\r | |
795 | \r | |
796 | /**\r | |
797 | Get the size of the SMI Handler in bytes.\r | |
798 | \r | |
799 | @retval The size, in bytes, of the SMI Handler.\r | |
800 | \r | |
801 | **/\r | |
802 | UINTN\r | |
803 | EFIAPI\r | |
804 | GetSmiHandlerSize (\r | |
805 | VOID\r | |
806 | );\r | |
807 | \r | |
808 | /**\r | |
809 | Install the SMI handler for the CPU specified by CpuIndex. This function\r | |
810 | is called by the CPU that was elected as monarch during System Management\r | |
811 | Mode initialization.\r | |
812 | \r | |
813 | @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r | |
814 | The value must be between 0 and the NumberOfCpus field\r | |
815 | in the System Management System Table (SMST).\r | |
816 | @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r | |
817 | @param[in] SmiStack The stack to use when an SMI is processed by the\r | |
818 | the CPU specified by CpuIndex.\r | |
819 | @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r | |
820 | processed by the CPU specified by CpuIndex.\r | |
821 | @param[in] GdtBase The base address of the GDT to use when an SMI is\r | |
822 | processed by the CPU specified by CpuIndex.\r | |
823 | @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r | |
824 | processed by the CPU specified by CpuIndex.\r | |
825 | @param[in] IdtBase The base address of the IDT to use when an SMI is\r | |
826 | processed by the CPU specified by CpuIndex.\r | |
827 | @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r | |
828 | processed by the CPU specified by CpuIndex.\r | |
829 | @param[in] Cr3 The base address of the page tables to use when an SMI\r | |
830 | is processed by the CPU specified by CpuIndex.\r | |
831 | **/\r | |
832 | VOID\r | |
833 | EFIAPI\r | |
834 | InstallSmiHandler (\r | |
835 | IN UINTN CpuIndex,\r | |
836 | IN UINT32 SmBase,\r | |
837 | IN VOID *SmiStack,\r | |
838 | IN UINTN StackSize,\r | |
839 | IN UINTN GdtBase,\r | |
840 | IN UINTN GdtSize,\r | |
841 | IN UINTN IdtBase,\r | |
842 | IN UINTN IdtSize,\r | |
843 | IN UINT32 Cr3\r | |
844 | );\r | |
845 | \r | |
846 | /**\r | |
847 | Search module name by input IP address and output it.\r | |
848 | \r | |
849 | @param CallerIpAddress Caller instruction pointer.\r | |
850 | \r | |
851 | **/\r | |
852 | VOID\r | |
853 | DumpModuleInfoByIp (\r | |
854 | IN UINTN CallerIpAddress\r | |
855 | );\r | |
21c17193 | 856 | \r |
717fb604 JY |
857 | /**\r |
858 | This function sets memory attribute according to MemoryAttributesTable.\r | |
859 | **/\r | |
860 | VOID\r | |
861 | SetMemMapAttributes (\r | |
862 | VOID\r | |
863 | );\r | |
864 | \r | |
d2fc7711 JY |
865 | /**\r |
866 | This function sets UEFI memory attribute according to UEFI memory map.\r | |
867 | **/\r | |
868 | VOID\r | |
869 | SetUefiMemMapAttributes (\r | |
870 | VOID\r | |
871 | );\r | |
872 | \r | |
873 | /**\r | |
874 | Return if the Address is forbidden as SMM communication buffer.\r | |
875 | \r | |
876 | @param[in] Address the address to be checked\r | |
877 | \r | |
878 | @return TRUE The address is forbidden as SMM communication buffer.\r | |
879 | @return FALSE The address is allowed as SMM communication buffer.\r | |
880 | **/\r | |
881 | BOOLEAN\r | |
882 | IsSmmCommBufferForbiddenAddress (\r | |
883 | IN UINT64 Address\r | |
884 | );\r | |
885 | \r | |
886 | /**\r | |
887 | This function caches the UEFI memory map information.\r | |
888 | **/\r | |
889 | VOID\r | |
890 | GetUefiMemoryMap (\r | |
891 | VOID\r | |
892 | );\r | |
893 | \r | |
717fb604 JY |
894 | /**\r |
895 | This function sets memory attribute for page table.\r | |
896 | **/\r | |
897 | VOID\r | |
898 | SetPageTableAttributes (\r | |
899 | VOID\r | |
900 | );\r | |
901 | \r | |
902 | /**\r | |
903 | Return page table base.\r | |
904 | \r | |
905 | @return page table base.\r | |
906 | **/\r | |
907 | UINTN\r | |
908 | GetPageTableBase (\r | |
909 | VOID\r | |
910 | );\r | |
911 | \r | |
912 | /**\r | |
913 | This function sets the attributes for the memory region specified by BaseAddress and\r | |
914 | Length from their current attributes to the attributes specified by Attributes.\r | |
915 | \r | |
916 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
917 | @param[in] Length The size in bytes of the memory region.\r | |
918 | @param[in] Attributes The bit mask of attributes to set for the memory region.\r | |
919 | @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r | |
920 | \r | |
921 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
922 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
923 | BaseAddress and Length cannot be modified.\r | |
924 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
925 | Attributes specified an illegal combination of attributes that\r | |
926 | cannot be set together.\r | |
927 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
928 | the memory resource range.\r | |
929 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
930 | resource range specified by BaseAddress and Length.\r | |
931 | The bit mask of attributes is not support for the memory resource\r | |
932 | range specified by BaseAddress and Length.\r | |
933 | \r | |
934 | **/\r | |
935 | EFI_STATUS\r | |
936 | EFIAPI\r | |
937 | SmmSetMemoryAttributesEx (\r | |
938 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
939 | IN UINT64 Length,\r | |
940 | IN UINT64 Attributes,\r | |
941 | OUT BOOLEAN *IsSplitted OPTIONAL\r | |
942 | );\r | |
943 | \r | |
944 | /**\r | |
945 | This function clears the attributes for the memory region specified by BaseAddress and\r | |
946 | Length from their current attributes to the attributes specified by Attributes.\r | |
947 | \r | |
948 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
949 | @param[in] Length The size in bytes of the memory region.\r | |
950 | @param[in] Attributes The bit mask of attributes to clear for the memory region.\r | |
951 | @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r | |
952 | \r | |
953 | @retval EFI_SUCCESS The attributes were cleared for the memory region.\r | |
954 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
955 | BaseAddress and Length cannot be modified.\r | |
956 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
957 | Attributes specified an illegal combination of attributes that\r | |
958 | cannot be set together.\r | |
959 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
960 | the memory resource range.\r | |
961 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
962 | resource range specified by BaseAddress and Length.\r | |
963 | The bit mask of attributes is not support for the memory resource\r | |
964 | range specified by BaseAddress and Length.\r | |
965 | \r | |
966 | **/\r | |
967 | EFI_STATUS\r | |
968 | EFIAPI\r | |
969 | SmmClearMemoryAttributesEx (\r | |
970 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
971 | IN UINT64 Length,\r | |
972 | IN UINT64 Attributes,\r | |
973 | OUT BOOLEAN *IsSplitted OPTIONAL\r | |
974 | );\r | |
975 | \r | |
21c17193 JY |
976 | /**\r |
977 | This API provides a way to allocate memory for page table.\r | |
978 | \r | |
979 | This API can be called more once to allocate memory for page tables.\r | |
980 | \r | |
981 | Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r | |
982 | allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r | |
983 | is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r | |
984 | returned.\r | |
985 | \r | |
986 | @param Pages The number of 4 KB pages to allocate.\r | |
987 | \r | |
988 | @return A pointer to the allocated buffer or NULL if allocation fails.\r | |
989 | \r | |
990 | **/\r | |
991 | VOID *\r | |
992 | AllocatePageTableMemory (\r | |
993 | IN UINTN Pages\r | |
994 | );\r | |
995 | \r | |
717fb604 JY |
996 | /**\r |
997 | Allocate pages for code.\r | |
998 | \r | |
999 | @param[in] Pages Number of pages to be allocated.\r | |
1000 | \r | |
1001 | @return Allocated memory.\r | |
1002 | **/\r | |
1003 | VOID *\r | |
1004 | AllocateCodePages (\r | |
1005 | IN UINTN Pages\r | |
1006 | );\r | |
1007 | \r | |
1008 | /**\r | |
1009 | Allocate aligned pages for code.\r | |
1010 | \r | |
1011 | @param[in] Pages Number of pages to be allocated.\r | |
1012 | @param[in] Alignment The requested alignment of the allocation.\r | |
1013 | Must be a power of two.\r | |
1014 | If Alignment is zero, then byte alignment is used.\r | |
1015 | \r | |
1016 | @return Allocated memory.\r | |
1017 | **/\r | |
1018 | VOID *\r | |
1019 | AllocateAlignedCodePages (\r | |
1020 | IN UINTN Pages,\r | |
1021 | IN UINTN Alignment\r | |
1022 | );\r | |
1023 | \r | |
0bdc9e75 SZ |
1024 | \r |
1025 | //\r | |
1026 | // S3 related global variable and function prototype.\r | |
1027 | //\r | |
1028 | \r | |
1029 | extern BOOLEAN mSmmS3Flag;\r | |
1030 | \r | |
1031 | /**\r | |
1032 | Initialize SMM S3 resume state structure used during S3 Resume.\r | |
1033 | \r | |
1034 | @param[in] Cr3 The base address of the page tables to use in SMM.\r | |
1035 | \r | |
1036 | **/\r | |
1037 | VOID\r | |
1038 | InitSmmS3ResumeState (\r | |
1039 | IN UINT32 Cr3\r | |
1040 | );\r | |
1041 | \r | |
1042 | /**\r | |
1043 | Get ACPI CPU data.\r | |
1044 | \r | |
1045 | **/\r | |
1046 | VOID\r | |
1047 | GetAcpiCpuData (\r | |
1048 | VOID\r | |
1049 | );\r | |
1050 | \r | |
1051 | /**\r | |
1052 | Restore SMM Configuration in S3 boot path.\r | |
1053 | \r | |
1054 | **/\r | |
1055 | VOID\r | |
1056 | RestoreSmmConfigurationInS3 (\r | |
1057 | VOID\r | |
1058 | );\r | |
1059 | \r | |
b10d5ddc SZ |
1060 | /**\r |
1061 | Get ACPI S3 enable flag.\r | |
1062 | \r | |
1063 | **/\r | |
1064 | VOID\r | |
1065 | GetAcpiS3EnableFlag (\r | |
1066 | VOID\r | |
1067 | );\r | |
1068 | \r | |
4a0f88dd JF |
1069 | /**\r |
1070 | Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r | |
1071 | \r | |
672b80c8 MK |
1072 | @param[in] ApHltLoopCode The address of the safe hlt-loop function.\r |
1073 | @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r | |
1074 | @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.\r | |
4a0f88dd JF |
1075 | \r |
1076 | **/\r | |
1077 | VOID\r | |
1078 | TransferApToSafeState (\r | |
672b80c8 MK |
1079 | IN UINTN ApHltLoopCode,\r |
1080 | IN UINTN TopOfStack,\r | |
1081 | IN UINTN NumberToFinishAddress\r | |
4a0f88dd JF |
1082 | );\r |
1083 | \r | |
3eb69b08 JY |
1084 | /**\r |
1085 | Set ShadowStack memory.\r | |
1086 | \r | |
1087 | @param[in] Cr3 The page table base address.\r | |
1088 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
1089 | @param[in] Length The size in bytes of the memory region.\r | |
1090 | \r | |
1091 | @retval EFI_SUCCESS The shadow stack memory is set.\r | |
1092 | **/\r | |
1093 | EFI_STATUS\r | |
1094 | SetShadowStack (\r | |
1095 | IN UINTN Cr3,\r | |
1096 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
1097 | IN UINT64 Length\r | |
1098 | );\r | |
1099 | \r | |
1100 | /**\r | |
1101 | Set not present memory.\r | |
1102 | \r | |
1103 | @param[in] Cr3 The page table base address.\r | |
1104 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
1105 | @param[in] Length The size in bytes of the memory region.\r | |
1106 | \r | |
1107 | @retval EFI_SUCCESS The not present memory is set.\r | |
1108 | **/\r | |
1109 | EFI_STATUS\r | |
1110 | SetNotPresentPage (\r | |
1111 | IN UINTN Cr3,\r | |
1112 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
1113 | IN UINT64 Length\r | |
1114 | );\r | |
1115 | \r | |
1116 | /**\r | |
1117 | Initialize the shadow stack related data structure.\r | |
1118 | \r | |
1119 | @param CpuIndex The index of CPU.\r | |
1120 | @param ShadowStack The bottom of the shadow stack for this CPU.\r | |
1121 | **/\r | |
1122 | VOID\r | |
1123 | InitShadowStack (\r | |
1124 | IN UINTN CpuIndex,\r | |
1125 | IN VOID *ShadowStack\r | |
1126 | );\r | |
1127 | \r | |
827330cc JW |
1128 | /**\r |
1129 | This function set given attributes of the memory region specified by\r | |
1130 | BaseAddress and Length.\r | |
1131 | \r | |
1132 | @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.\r | |
1133 | @param BaseAddress The physical address that is the start address of\r | |
1134 | a memory region.\r | |
1135 | @param Length The size in bytes of the memory region.\r | |
1136 | @param Attributes The bit mask of attributes to set for the memory\r | |
1137 | region.\r | |
1138 | \r | |
1139 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
1140 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
1141 | Attributes specified an illegal combination of\r | |
1142 | attributes that cannot be set together.\r | |
1143 | @retval EFI_UNSUPPORTED The processor does not support one or more\r | |
1144 | bytes of the memory resource range specified\r | |
1145 | by BaseAddress and Length.\r | |
aae02dcc | 1146 | The bit mask of attributes is not supported for\r |
827330cc JW |
1147 | the memory resource range specified by\r |
1148 | BaseAddress and Length.\r | |
1149 | \r | |
1150 | **/\r | |
1151 | EFI_STATUS\r | |
1152 | EFIAPI\r | |
1153 | EdkiiSmmSetMemoryAttributes (\r | |
1154 | IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r | |
1155 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
1156 | IN UINT64 Length,\r | |
1157 | IN UINT64 Attributes\r | |
1158 | );\r | |
1159 | \r | |
1160 | /**\r | |
1161 | This function clears given attributes of the memory region specified by\r | |
1162 | BaseAddress and Length.\r | |
1163 | \r | |
1164 | @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.\r | |
1165 | @param BaseAddress The physical address that is the start address of\r | |
1166 | a memory region.\r | |
1167 | @param Length The size in bytes of the memory region.\r | |
aae02dcc | 1168 | @param Attributes The bit mask of attributes to clear for the memory\r |
827330cc JW |
1169 | region.\r |
1170 | \r | |
aae02dcc | 1171 | @retval EFI_SUCCESS The attributes were cleared for the memory region.\r |
827330cc JW |
1172 | @retval EFI_INVALID_PARAMETER Length is zero.\r |
1173 | Attributes specified an illegal combination of\r | |
aae02dcc | 1174 | attributes that cannot be cleared together.\r |
827330cc JW |
1175 | @retval EFI_UNSUPPORTED The processor does not support one or more\r |
1176 | bytes of the memory resource range specified\r | |
1177 | by BaseAddress and Length.\r | |
aae02dcc | 1178 | The bit mask of attributes is not supported for\r |
827330cc JW |
1179 | the memory resource range specified by\r |
1180 | BaseAddress and Length.\r | |
1181 | \r | |
1182 | **/\r | |
1183 | EFI_STATUS\r | |
1184 | EFIAPI\r | |
1185 | EdkiiSmmClearMemoryAttributes (\r | |
1186 | IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r | |
1187 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
1188 | IN UINT64 Length,\r | |
1189 | IN UINT64 Attributes\r | |
1190 | );\r | |
1191 | \r | |
1192 | /**\r | |
aae02dcc | 1193 | This function retrieves the attributes of the memory region specified by\r |
827330cc JW |
1194 | BaseAddress and Length. If different attributes are got from different part\r |
1195 | of the memory region, EFI_NO_MAPPING will be returned.\r | |
1196 | \r | |
1197 | @param This The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.\r | |
1198 | @param BaseAddress The physical address that is the start address of\r | |
1199 | a memory region.\r | |
1200 | @param Length The size in bytes of the memory region.\r | |
1201 | @param Attributes Pointer to attributes returned.\r | |
1202 | \r | |
1203 | @retval EFI_SUCCESS The attributes got for the memory region.\r | |
1204 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
1205 | Attributes is NULL.\r | |
1206 | @retval EFI_NO_MAPPING Attributes are not consistent cross the memory\r | |
1207 | region.\r | |
1208 | @retval EFI_UNSUPPORTED The processor does not support one or more\r | |
1209 | bytes of the memory resource range specified\r | |
1210 | by BaseAddress and Length.\r | |
827330cc JW |
1211 | \r |
1212 | **/\r | |
1213 | EFI_STATUS\r | |
1214 | EFIAPI\r | |
1215 | EdkiiSmmGetMemoryAttributes (\r | |
1216 | IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r | |
1217 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
1218 | IN UINT64 Length,\r | |
1219 | IN UINT64 *Attributes\r | |
1220 | );\r | |
1221 | \r | |
e21e355e LG |
1222 | /**\r |
1223 | This function fixes up the address of the global variable or function\r | |
1224 | referred in SmmInit assembly files to be the absoute address.\r | |
1225 | **/\r | |
1226 | VOID\r | |
1227 | EFIAPI\r | |
1228 | PiSmmCpuSmmInitFixupAddress (\r | |
1229 | );\r | |
1230 | \r | |
1231 | /**\r | |
1232 | This function fixes up the address of the global variable or function\r | |
1233 | referred in SmiEntry assembly files to be the absoute address.\r | |
1234 | **/\r | |
1235 | VOID\r | |
1236 | EFIAPI\r | |
1237 | PiSmmCpuSmiEntryFixupAddress (\r | |
1238 | );\r | |
1239 | \r | |
37f9fea5 VN |
1240 | /**\r |
1241 | This function reads CR2 register when on-demand paging is enabled\r | |
1242 | for 64 bit and no action for 32 bit.\r | |
1243 | \r | |
1244 | @param[out] *Cr2 Pointer to variable to hold CR2 register value.\r | |
1245 | **/\r | |
1246 | VOID\r | |
1247 | SaveCr2 (\r | |
1248 | OUT UINTN *Cr2\r | |
1249 | );\r | |
1250 | \r | |
1251 | /**\r | |
1252 | This function writes into CR2 register when on-demand paging is enabled\r | |
1253 | for 64 bit and no action for 32 bit.\r | |
1254 | \r | |
1255 | @param[in] Cr2 Value to write into CR2 register.\r | |
1256 | **/\r | |
1257 | VOID\r | |
1258 | RestoreCr2 (\r | |
1259 | IN UINTN Cr2\r | |
1260 | );\r | |
1261 | \r | |
529a5a86 | 1262 | #endif\r |