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529a5a86 MK |
1 | /** @file\r |
2 | Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r | |
3 | \r | |
f85d3ce2 | 4 | Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r |
529a5a86 MK |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _CPU_PISMMCPUDXESMM_H_\r | |
16 | #define _CPU_PISMMCPUDXESMM_H_\r | |
17 | \r | |
18 | #include <PiSmm.h>\r | |
19 | \r | |
20 | #include <Protocol/MpService.h>\r | |
21 | #include <Protocol/SmmConfiguration.h>\r | |
22 | #include <Protocol/SmmCpu.h>\r | |
23 | #include <Protocol/SmmAccess2.h>\r | |
529a5a86 MK |
24 | #include <Protocol/SmmReadyToLock.h>\r |
25 | #include <Protocol/SmmCpuService.h>\r | |
26 | \r | |
27 | #include <Guid/AcpiS3Context.h>\r | |
717fb604 | 28 | #include <Guid/PiSmmMemoryAttributesTable.h>\r |
529a5a86 MK |
29 | \r |
30 | #include <Library/BaseLib.h>\r | |
31 | #include <Library/IoLib.h>\r | |
32 | #include <Library/TimerLib.h>\r | |
529a5a86 MK |
33 | #include <Library/SynchronizationLib.h>\r |
34 | #include <Library/DebugLib.h>\r | |
35 | #include <Library/BaseMemoryLib.h>\r | |
36 | #include <Library/PcdLib.h>\r | |
37 | #include <Library/CacheMaintenanceLib.h>\r | |
38 | #include <Library/MtrrLib.h>\r | |
39 | #include <Library/SmmCpuPlatformHookLib.h>\r | |
40 | #include <Library/SmmServicesTableLib.h>\r | |
41 | #include <Library/MemoryAllocationLib.h>\r | |
42 | #include <Library/UefiBootServicesTableLib.h>\r | |
43 | #include <Library/UefiRuntimeServicesTableLib.h>\r | |
44 | #include <Library/DebugAgentLib.h>\r | |
45 | #include <Library/HobLib.h>\r | |
46 | #include <Library/LocalApicLib.h>\r | |
47 | #include <Library/UefiCpuLib.h>\r | |
48 | #include <Library/CpuExceptionHandlerLib.h>\r | |
49 | #include <Library/ReportStatusCodeLib.h>\r | |
50 | #include <Library/SmmCpuFeaturesLib.h>\r | |
51 | #include <Library/PeCoffGetEntryPointLib.h>\r | |
52 | \r | |
53 | #include <AcpiCpuData.h>\r | |
54 | #include <CpuHotPlugData.h>\r | |
55 | \r | |
56 | #include <Register/Cpuid.h>\r | |
f85d3ce2 | 57 | #include <Register/Msr.h>\r |
529a5a86 MK |
58 | \r |
59 | #include "CpuService.h"\r | |
60 | #include "SmmProfile.h"\r | |
61 | \r | |
62 | //\r | |
63 | // MSRs required for configuration of SMM Code Access Check\r | |
64 | //\r | |
65 | #define EFI_MSR_SMM_MCA_CAP 0x17D\r | |
66 | #define SMM_CODE_ACCESS_CHK_BIT BIT58\r | |
67 | \r | |
68 | #define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r | |
69 | #define SMM_CODE_CHK_EN_BIT BIT2\r | |
70 | \r | |
71 | ///\r | |
72 | /// Page Table Entry\r | |
73 | ///\r | |
74 | #define IA32_PG_P BIT0\r | |
75 | #define IA32_PG_RW BIT1\r | |
881520ea | 76 | #define IA32_PG_U BIT2\r |
529a5a86 MK |
77 | #define IA32_PG_WT BIT3\r |
78 | #define IA32_PG_CD BIT4\r | |
79 | #define IA32_PG_A BIT5\r | |
881520ea | 80 | #define IA32_PG_D BIT6\r |
529a5a86 MK |
81 | #define IA32_PG_PS BIT7\r |
82 | #define IA32_PG_PAT_2M BIT12\r | |
83 | #define IA32_PG_PAT_4K IA32_PG_PS\r | |
84 | #define IA32_PG_PMNT BIT62\r | |
85 | #define IA32_PG_NX BIT63\r | |
86 | \r | |
717fb604 | 87 | #define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r |
881520ea JY |
88 | //\r |
89 | // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r | |
90 | // X64 PAE PDPTE does not have such restriction\r | |
91 | //\r | |
92 | #define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r | |
93 | \r | |
717fb604 JY |
94 | #define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r |
95 | \r | |
96 | #define PAGING_4K_MASK 0xFFF\r | |
97 | #define PAGING_2M_MASK 0x1FFFFF\r | |
98 | #define PAGING_1G_MASK 0x3FFFFFFF\r | |
99 | \r | |
100 | #define PAGING_PAE_INDEX_MASK 0x1FF\r | |
101 | \r | |
102 | #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r | |
103 | #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r | |
104 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r | |
105 | \r | |
106 | typedef enum {\r | |
107 | PageNone,\r | |
108 | Page4K,\r | |
109 | Page2M,\r | |
110 | Page1G,\r | |
111 | } PAGE_ATTRIBUTE;\r | |
112 | \r | |
113 | typedef struct {\r | |
114 | PAGE_ATTRIBUTE Attribute;\r | |
115 | UINT64 Length;\r | |
116 | UINT64 AddressMask;\r | |
117 | } PAGE_ATTRIBUTE_TABLE;\r | |
118 | \r | |
529a5a86 MK |
119 | //\r |
120 | // Size of Task-State Segment defined in IA32 Manual\r | |
121 | //\r | |
122 | #define TSS_SIZE 104\r | |
123 | #define TSS_X64_IST1_OFFSET 36\r | |
124 | #define TSS_IA32_CR3_OFFSET 28\r | |
125 | #define TSS_IA32_ESP_OFFSET 56\r | |
126 | \r | |
717fb604 JY |
127 | #define CR0_WP BIT16\r |
128 | \r | |
529a5a86 MK |
129 | //\r |
130 | // Code select value\r | |
131 | //\r | |
132 | #define PROTECT_MODE_CODE_SEGMENT 0x08\r | |
133 | #define LONG_MODE_CODE_SEGMENT 0x38\r | |
134 | \r | |
135 | //\r | |
136 | // The size 0x20 must be bigger than\r | |
137 | // the size of template code of SmmInit. Currently,\r | |
138 | // the size of SmmInit requires the 0x16 Bytes buffer\r | |
139 | // at least.\r | |
140 | //\r | |
141 | #define BACK_BUF_SIZE 0x20\r | |
142 | \r | |
143 | #define EXCEPTION_VECTOR_NUMBER 0x20\r | |
144 | \r | |
145 | #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r | |
146 | \r | |
147 | typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r | |
148 | #define ARRIVAL_EXCEPTION_BLOCKED 0x1\r | |
149 | #define ARRIVAL_EXCEPTION_DELAYED 0x2\r | |
150 | #define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r | |
151 | \r | |
152 | //\r | |
153 | // Private structure for the SMM CPU module that is stored in DXE Runtime memory\r | |
154 | // Contains the SMM Configuration Protocols that is produced.\r | |
155 | // Contains a mix of DXE and SMM contents. All the fields must be used properly.\r | |
156 | //\r | |
157 | #define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r | |
158 | \r | |
159 | typedef struct {\r | |
160 | UINTN Signature;\r | |
161 | \r | |
162 | EFI_HANDLE SmmCpuHandle;\r | |
163 | \r | |
164 | EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r | |
165 | SMM_CPU_OPERATION *Operation;\r | |
166 | UINTN *CpuSaveStateSize;\r | |
167 | VOID **CpuSaveState;\r | |
168 | \r | |
169 | EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r | |
170 | EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r | |
171 | EFI_SMM_ENTRY_POINT SmmCoreEntry;\r | |
172 | \r | |
173 | EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r | |
174 | } SMM_CPU_PRIVATE_DATA;\r | |
175 | \r | |
176 | extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r | |
177 | extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r | |
178 | extern UINTN mMaxNumberOfCpus;\r | |
179 | extern UINTN mNumberOfCpus;\r | |
529a5a86 MK |
180 | extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r |
181 | \r | |
182 | ///\r | |
183 | /// The mode of the CPU at the time an SMI occurs\r | |
184 | ///\r | |
185 | extern UINT8 mSmmSaveStateRegisterLma;\r | |
186 | \r | |
187 | \r | |
188 | //\r | |
189 | // SMM CPU Protocol function prototypes.\r | |
190 | //\r | |
191 | \r | |
192 | /**\r | |
193 | Read information from the CPU save state.\r | |
194 | \r | |
195 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
196 | @param Width The number of bytes to read from the CPU save state.\r | |
197 | @param Register Specifies the CPU register to read form the save state.\r | |
198 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
199 | @param Buffer Upon return, this holds the CPU register value read from the save state.\r | |
200 | \r | |
201 | @retval EFI_SUCCESS The register was read from Save State\r | |
202 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
203 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
204 | \r | |
205 | **/\r | |
206 | EFI_STATUS\r | |
207 | EFIAPI\r | |
208 | SmmReadSaveState (\r | |
209 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
210 | IN UINTN Width,\r | |
211 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
212 | IN UINTN CpuIndex,\r | |
213 | OUT VOID *Buffer\r | |
214 | );\r | |
215 | \r | |
216 | /**\r | |
217 | Write data to the CPU save state.\r | |
218 | \r | |
219 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
220 | @param Width The number of bytes to read from the CPU save state.\r | |
221 | @param Register Specifies the CPU register to write to the save state.\r | |
222 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
223 | @param Buffer Upon entry, this holds the new CPU register value.\r | |
224 | \r | |
225 | @retval EFI_SUCCESS The register was written from Save State\r | |
226 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
227 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r | |
228 | \r | |
229 | **/\r | |
230 | EFI_STATUS\r | |
231 | EFIAPI\r | |
232 | SmmWriteSaveState (\r | |
233 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
234 | IN UINTN Width,\r | |
235 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
236 | IN UINTN CpuIndex,\r | |
237 | IN CONST VOID *Buffer\r | |
238 | );\r | |
239 | \r | |
240 | /**\r | |
241 | Read a CPU Save State register on the target processor.\r | |
242 | \r | |
243 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
244 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
245 | \r | |
246 | This function supports reading a CPU Save State register in SMBase relocation handler.\r | |
247 | \r | |
248 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
249 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
250 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
251 | @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r | |
252 | \r | |
253 | @retval EFI_SUCCESS The register was read from Save State.\r | |
254 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
255 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
256 | \r | |
257 | **/\r | |
258 | EFI_STATUS\r | |
259 | EFIAPI\r | |
260 | ReadSaveStateRegister (\r | |
261 | IN UINTN CpuIndex,\r | |
262 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
263 | IN UINTN Width,\r | |
264 | OUT VOID *Buffer\r | |
265 | );\r | |
266 | \r | |
267 | /**\r | |
268 | Write value to a CPU Save State register on the target processor.\r | |
269 | \r | |
270 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
271 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
272 | \r | |
273 | This function supports writing a CPU Save State register in SMBase relocation handler.\r | |
274 | \r | |
275 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
276 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
277 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
278 | @param[in] Buffer Upon entry, this holds the new CPU register value.\r | |
279 | \r | |
280 | @retval EFI_SUCCESS The register was written to Save State.\r | |
281 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
282 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r | |
283 | \r | |
284 | **/\r | |
285 | EFI_STATUS\r | |
286 | EFIAPI\r | |
287 | WriteSaveStateRegister (\r | |
288 | IN UINTN CpuIndex,\r | |
289 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
290 | IN UINTN Width,\r | |
291 | IN CONST VOID *Buffer\r | |
292 | );\r | |
293 | \r | |
294 | //\r | |
295 | //\r | |
296 | //\r | |
297 | typedef struct {\r | |
298 | UINT32 Offset;\r | |
299 | UINT16 Segment;\r | |
300 | UINT16 Reserved;\r | |
301 | } IA32_FAR_ADDRESS;\r | |
302 | \r | |
303 | extern IA32_FAR_ADDRESS gSmmJmpAddr;\r | |
304 | \r | |
305 | extern CONST UINT8 gcSmmInitTemplate[];\r | |
306 | extern CONST UINT16 gcSmmInitSize;\r | |
307 | extern UINT32 gSmmCr0;\r | |
308 | extern UINT32 gSmmCr3;\r | |
309 | extern UINT32 gSmmCr4;\r | |
310 | extern UINTN gSmmInitStack;\r | |
311 | \r | |
312 | /**\r | |
313 | Semaphore operation for all processor relocate SMMBase.\r | |
314 | **/\r | |
315 | VOID\r | |
316 | EFIAPI\r | |
317 | SmmRelocationSemaphoreComplete (\r | |
318 | VOID\r | |
319 | );\r | |
320 | \r | |
321 | ///\r | |
322 | /// The type of SMM CPU Information\r | |
323 | ///\r | |
324 | typedef struct {\r | |
ed3d5ecb | 325 | SPIN_LOCK *Busy;\r |
529a5a86 MK |
326 | volatile EFI_AP_PROCEDURE Procedure;\r |
327 | volatile VOID *Parameter;\r | |
ed3d5ecb JF |
328 | volatile UINT32 *Run;\r |
329 | volatile BOOLEAN *Present;\r | |
529a5a86 MK |
330 | } SMM_CPU_DATA_BLOCK;\r |
331 | \r | |
332 | typedef enum {\r | |
333 | SmmCpuSyncModeTradition,\r | |
334 | SmmCpuSyncModeRelaxedAp,\r | |
335 | SmmCpuSyncModeMax\r | |
336 | } SMM_CPU_SYNC_MODE;\r | |
337 | \r | |
338 | typedef struct {\r | |
339 | //\r | |
340 | // Pointer to an array. The array should be located immediately after this structure\r | |
341 | // so that UC cache-ability can be set together.\r | |
342 | //\r | |
343 | SMM_CPU_DATA_BLOCK *CpuData;\r | |
fe3a75bc | 344 | volatile UINT32 *Counter;\r |
529a5a86 | 345 | volatile UINT32 BspIndex;\r |
fe3a75bc JF |
346 | volatile BOOLEAN *InsideSmm;\r |
347 | volatile BOOLEAN *AllCpusInSync;\r | |
529a5a86 MK |
348 | volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r |
349 | volatile BOOLEAN SwitchBsp;\r | |
350 | volatile BOOLEAN *CandidateBsp;\r | |
351 | } SMM_DISPATCHER_MP_SYNC_DATA;\r | |
352 | \r | |
695e62d1 JF |
353 | #define MSR_SPIN_LOCK_INIT_NUM 15\r |
354 | \r | |
529a5a86 | 355 | typedef struct {\r |
dc99315b | 356 | SPIN_LOCK *SpinLock;\r |
529a5a86 MK |
357 | UINT32 MsrIndex;\r |
358 | } MP_MSR_LOCK;\r | |
359 | \r | |
360 | #define SMM_PSD_OFFSET 0xfb00\r | |
361 | \r | |
1d648531 JF |
362 | ///\r |
363 | /// All global semaphores' pointer\r | |
364 | ///\r | |
365 | typedef struct {\r | |
366 | volatile UINT32 *Counter;\r | |
367 | volatile BOOLEAN *InsideSmm;\r | |
368 | volatile BOOLEAN *AllCpusInSync;\r | |
369 | SPIN_LOCK *PFLock;\r | |
370 | SPIN_LOCK *CodeAccessCheckLock;\r | |
6c4c15fa | 371 | SPIN_LOCK *MemoryMappedLock;\r |
1d648531 JF |
372 | } SMM_CPU_SEMAPHORE_GLOBAL;\r |
373 | \r | |
4e920581 JF |
374 | ///\r |
375 | /// All semaphores for each processor\r | |
376 | ///\r | |
377 | typedef struct {\r | |
378 | SPIN_LOCK *Busy;\r | |
379 | volatile UINT32 *Run;\r | |
380 | volatile BOOLEAN *Present;\r | |
381 | } SMM_CPU_SEMAPHORE_CPU;\r | |
382 | \r | |
695e62d1 JF |
383 | ///\r |
384 | /// All MSRs semaphores' pointer and counter\r | |
385 | ///\r | |
386 | typedef struct {\r | |
387 | SPIN_LOCK *Msr;\r | |
388 | UINTN AvailableCounter;\r | |
389 | } SMM_CPU_SEMAPHORE_MSR;\r | |
4e920581 | 390 | \r |
1d648531 JF |
391 | ///\r |
392 | /// All semaphores' information\r | |
393 | ///\r | |
394 | typedef struct {\r | |
395 | SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r | |
4e920581 | 396 | SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r |
695e62d1 | 397 | SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;\r |
1d648531 JF |
398 | } SMM_CPU_SEMAPHORES;\r |
399 | \r | |
529a5a86 | 400 | extern IA32_DESCRIPTOR gcSmiGdtr;\r |
717fb604 JY |
401 | extern EFI_PHYSICAL_ADDRESS mGdtBuffer;\r |
402 | extern UINTN mGdtBufferSize;\r | |
529a5a86 MK |
403 | extern IA32_DESCRIPTOR gcSmiIdtr;\r |
404 | extern VOID *gcSmiIdtrPtr;\r | |
529a5a86 | 405 | extern UINT64 gPhyMask;\r |
529a5a86 | 406 | extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r |
529a5a86 MK |
407 | extern UINTN mSmmStackArrayBase;\r |
408 | extern UINTN mSmmStackArrayEnd;\r | |
409 | extern UINTN mSmmStackSize;\r | |
410 | extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r | |
411 | extern IA32_DESCRIPTOR gcSmiInitGdtr;\r | |
dc99315b JF |
412 | extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r |
413 | extern UINTN mSemaphoreSize;\r | |
fe3a75bc JF |
414 | extern SPIN_LOCK *mPFLock;\r |
415 | extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r | |
6c4c15fa | 416 | extern SPIN_LOCK *mMemoryMappedLock;\r |
529a5a86 MK |
417 | \r |
418 | /**\r | |
419 | Create 4G PageTable in SMRAM.\r | |
420 | \r | |
717fb604 | 421 | @param[in] Is32BitPageTable Whether the page table is 32-bit PAE\r |
529a5a86 MK |
422 | @return PageTable Address\r |
423 | \r | |
424 | **/\r | |
425 | UINT32\r | |
426 | Gen4GPageTable (\r | |
881520ea | 427 | IN BOOLEAN Is32BitPageTable\r |
529a5a86 MK |
428 | );\r |
429 | \r | |
430 | \r | |
431 | /**\r | |
432 | Initialize global data for MP synchronization.\r | |
433 | \r | |
434 | @param Stacks Base address of SMI stack buffer for all processors.\r | |
435 | @param StackSize Stack size for each processor in SMM.\r | |
436 | \r | |
437 | **/\r | |
438 | UINT32\r | |
439 | InitializeMpServiceData (\r | |
440 | IN VOID *Stacks,\r | |
441 | IN UINTN StackSize\r | |
442 | );\r | |
443 | \r | |
444 | /**\r | |
445 | Initialize Timer for SMM AP Sync.\r | |
446 | \r | |
447 | **/\r | |
448 | VOID\r | |
449 | InitializeSmmTimer (\r | |
450 | VOID\r | |
451 | );\r | |
452 | \r | |
453 | /**\r | |
454 | Start Timer for SMM AP Sync.\r | |
455 | \r | |
456 | **/\r | |
457 | UINT64\r | |
458 | EFIAPI\r | |
459 | StartSyncTimer (\r | |
460 | VOID\r | |
461 | );\r | |
462 | \r | |
463 | /**\r | |
464 | Check if the SMM AP Sync timer is timeout.\r | |
465 | \r | |
466 | @param Timer The start timer from the begin.\r | |
467 | \r | |
468 | **/\r | |
469 | BOOLEAN\r | |
470 | EFIAPI\r | |
471 | IsSyncTimerTimeout (\r | |
472 | IN UINT64 Timer\r | |
473 | );\r | |
474 | \r | |
475 | /**\r | |
476 | Initialize IDT for SMM Stack Guard.\r | |
477 | \r | |
478 | **/\r | |
479 | VOID\r | |
480 | EFIAPI\r | |
481 | InitializeIDTSmmStackGuard (\r | |
482 | VOID\r | |
483 | );\r | |
484 | \r | |
fe5f1949 JY |
485 | /**\r |
486 | Initialize Gdt for all processors.\r | |
717fb604 | 487 | \r |
fe5f1949 JY |
488 | @param[in] Cr3 CR3 value.\r |
489 | @param[out] GdtStepSize The step size for GDT table.\r | |
490 | \r | |
491 | @return GdtBase for processor 0.\r | |
492 | GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r | |
493 | **/\r | |
494 | VOID *\r | |
495 | InitGdt (\r | |
496 | IN UINTN Cr3,\r | |
497 | OUT UINTN *GdtStepSize\r | |
498 | );\r | |
499 | \r | |
529a5a86 MK |
500 | /**\r |
501 | \r | |
502 | Register the SMM Foundation entry point.\r | |
503 | \r | |
504 | @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r | |
505 | @param SmmEntryPoint SMM Foundation EntryPoint\r | |
506 | \r | |
507 | @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r | |
508 | \r | |
509 | **/\r | |
510 | EFI_STATUS\r | |
511 | EFIAPI\r | |
512 | RegisterSmmEntry (\r | |
513 | IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r | |
514 | IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r | |
515 | );\r | |
516 | \r | |
517 | /**\r | |
518 | Create PageTable for SMM use.\r | |
519 | \r | |
520 | @return PageTable Address\r | |
521 | \r | |
522 | **/\r | |
523 | UINT32\r | |
524 | SmmInitPageTable (\r | |
525 | VOID\r | |
526 | );\r | |
527 | \r | |
528 | /**\r | |
529 | Schedule a procedure to run on the specified CPU.\r | |
530 | \r | |
531 | @param Procedure The address of the procedure to run\r | |
532 | @param CpuIndex Target CPU number\r | |
533 | @param ProcArguments The parameter to pass to the procedure\r | |
534 | \r | |
535 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
536 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
537 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
538 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
539 | @retval EFI_SUCCESS - The procedure has been successfully scheduled\r | |
540 | \r | |
541 | **/\r | |
542 | EFI_STATUS\r | |
543 | EFIAPI\r | |
544 | SmmStartupThisAp (\r | |
545 | IN EFI_AP_PROCEDURE Procedure,\r | |
546 | IN UINTN CpuIndex,\r | |
547 | IN OUT VOID *ProcArguments OPTIONAL\r | |
548 | );\r | |
549 | \r | |
550 | /**\r | |
551 | Schedule a procedure to run on the specified CPU in a blocking fashion.\r | |
552 | \r | |
553 | @param Procedure The address of the procedure to run\r | |
554 | @param CpuIndex Target CPU Index\r | |
555 | @param ProcArguments The parameter to pass to the procedure\r | |
556 | \r | |
557 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
558 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
559 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
560 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
561 | @retval EFI_SUCCESS The procedure has been successfully scheduled\r | |
562 | \r | |
563 | **/\r | |
564 | EFI_STATUS\r | |
565 | EFIAPI\r | |
566 | SmmBlockingStartupThisAp (\r | |
567 | IN EFI_AP_PROCEDURE Procedure,\r | |
568 | IN UINTN CpuIndex,\r | |
569 | IN OUT VOID *ProcArguments OPTIONAL\r | |
570 | );\r | |
571 | \r | |
572 | /**\r | |
573 | Initialize MP synchronization data.\r | |
574 | \r | |
575 | **/\r | |
576 | VOID\r | |
577 | EFIAPI\r | |
578 | InitializeMpSyncData (\r | |
579 | VOID\r | |
580 | );\r | |
581 | \r | |
582 | /**\r | |
583 | \r | |
584 | Find out SMRAM information including SMRR base and SMRR size.\r | |
585 | \r | |
586 | @param SmrrBase SMRR base\r | |
587 | @param SmrrSize SMRR size\r | |
588 | \r | |
589 | **/\r | |
590 | VOID\r | |
591 | FindSmramInfo (\r | |
592 | OUT UINT32 *SmrrBase,\r | |
593 | OUT UINT32 *SmrrSize\r | |
594 | );\r | |
595 | \r | |
596 | /**\r | |
0bdc9e75 | 597 | Relocate SmmBases for each processor.\r |
529a5a86 | 598 | \r |
0bdc9e75 | 599 | Execute on first boot and all S3 resumes\r |
529a5a86 MK |
600 | \r |
601 | **/\r | |
602 | VOID\r | |
0bdc9e75 SZ |
603 | EFIAPI\r |
604 | SmmRelocateBases (\r | |
529a5a86 MK |
605 | VOID\r |
606 | );\r | |
607 | \r | |
608 | /**\r | |
609 | Page Fault handler for SMM use.\r | |
610 | \r | |
611 | @param InterruptType Defines the type of interrupt or exception that\r | |
612 | occurred on the processor.This parameter is processor architecture specific.\r | |
613 | @param SystemContext A pointer to the processor context when\r | |
614 | the interrupt occurred on the processor.\r | |
615 | **/\r | |
616 | VOID\r | |
617 | EFIAPI\r | |
618 | SmiPFHandler (\r | |
619 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
620 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
621 | );\r | |
622 | \r | |
623 | /**\r | |
624 | Perform the remaining tasks.\r | |
625 | \r | |
626 | **/\r | |
627 | VOID\r | |
628 | PerformRemainingTasks (\r | |
629 | VOID\r | |
630 | );\r | |
631 | \r | |
9f419739 JY |
632 | /**\r |
633 | Perform the pre tasks.\r | |
634 | \r | |
635 | **/\r | |
636 | VOID\r | |
637 | PerformPreTasks (\r | |
638 | VOID\r | |
639 | );\r | |
640 | \r | |
529a5a86 MK |
641 | /**\r |
642 | Initialize MSR spin lock by MSR index.\r | |
643 | \r | |
644 | @param MsrIndex MSR index value.\r | |
645 | \r | |
646 | **/\r | |
647 | VOID\r | |
648 | InitMsrSpinLockByIndex (\r | |
649 | IN UINT32 MsrIndex\r | |
650 | );\r | |
651 | \r | |
652 | /**\r | |
653 | Hook return address of SMM Save State so that semaphore code\r | |
654 | can be executed immediately after AP exits SMM to indicate to\r | |
655 | the BSP that an AP has exited SMM after SMBASE relocation.\r | |
656 | \r | |
657 | @param[in] CpuIndex The processor index.\r | |
658 | @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r | |
659 | immediately after AP exits SMM.\r | |
660 | \r | |
661 | **/\r | |
662 | VOID\r | |
663 | SemaphoreHook (\r | |
664 | IN UINTN CpuIndex,\r | |
665 | IN volatile BOOLEAN *RebasedFlag\r | |
666 | );\r | |
667 | \r | |
668 | /**\r | |
669 | Configure SMM Code Access Check feature for all processors.\r | |
670 | SMM Feature Control MSR will be locked after configuration.\r | |
671 | **/\r | |
672 | VOID\r | |
673 | ConfigSmmCodeAccessCheck (\r | |
674 | VOID\r | |
675 | );\r | |
676 | \r | |
677 | /**\r | |
678 | Hook the code executed immediately after an RSM instruction on the currently\r | |
679 | executing CPU. The mode of code executed immediately after RSM must be\r | |
680 | detected, and the appropriate hook must be selected. Always clear the auto\r | |
681 | HALT restart flag if it is set.\r | |
682 | \r | |
683 | @param[in] CpuIndex The processor index for the currently\r | |
684 | executing CPU.\r | |
685 | @param[in] CpuState Pointer to SMRAM Save State Map for the\r | |
686 | currently executing CPU.\r | |
687 | @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r | |
688 | 32-bit mode from 64-bit SMM.\r | |
689 | @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r | |
690 | same mode as SMM.\r | |
691 | \r | |
692 | @retval The value of the original instruction pointer before it was hooked.\r | |
693 | \r | |
694 | **/\r | |
695 | UINT64\r | |
696 | EFIAPI\r | |
697 | HookReturnFromSmm (\r | |
698 | IN UINTN CpuIndex,\r | |
699 | SMRAM_SAVE_STATE_MAP *CpuState,\r | |
700 | UINT64 NewInstructionPointer32,\r | |
701 | UINT64 NewInstructionPointer\r | |
702 | );\r | |
703 | \r | |
704 | /**\r | |
705 | Get the size of the SMI Handler in bytes.\r | |
706 | \r | |
707 | @retval The size, in bytes, of the SMI Handler.\r | |
708 | \r | |
709 | **/\r | |
710 | UINTN\r | |
711 | EFIAPI\r | |
712 | GetSmiHandlerSize (\r | |
713 | VOID\r | |
714 | );\r | |
715 | \r | |
716 | /**\r | |
717 | Install the SMI handler for the CPU specified by CpuIndex. This function\r | |
718 | is called by the CPU that was elected as monarch during System Management\r | |
719 | Mode initialization.\r | |
720 | \r | |
721 | @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r | |
722 | The value must be between 0 and the NumberOfCpus field\r | |
723 | in the System Management System Table (SMST).\r | |
724 | @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r | |
725 | @param[in] SmiStack The stack to use when an SMI is processed by the\r | |
726 | the CPU specified by CpuIndex.\r | |
727 | @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r | |
728 | processed by the CPU specified by CpuIndex.\r | |
729 | @param[in] GdtBase The base address of the GDT to use when an SMI is\r | |
730 | processed by the CPU specified by CpuIndex.\r | |
731 | @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r | |
732 | processed by the CPU specified by CpuIndex.\r | |
733 | @param[in] IdtBase The base address of the IDT to use when an SMI is\r | |
734 | processed by the CPU specified by CpuIndex.\r | |
735 | @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r | |
736 | processed by the CPU specified by CpuIndex.\r | |
737 | @param[in] Cr3 The base address of the page tables to use when an SMI\r | |
738 | is processed by the CPU specified by CpuIndex.\r | |
739 | **/\r | |
740 | VOID\r | |
741 | EFIAPI\r | |
742 | InstallSmiHandler (\r | |
743 | IN UINTN CpuIndex,\r | |
744 | IN UINT32 SmBase,\r | |
745 | IN VOID *SmiStack,\r | |
746 | IN UINTN StackSize,\r | |
747 | IN UINTN GdtBase,\r | |
748 | IN UINTN GdtSize,\r | |
749 | IN UINTN IdtBase,\r | |
750 | IN UINTN IdtSize,\r | |
751 | IN UINT32 Cr3\r | |
752 | );\r | |
753 | \r | |
754 | /**\r | |
755 | Search module name by input IP address and output it.\r | |
756 | \r | |
757 | @param CallerIpAddress Caller instruction pointer.\r | |
758 | \r | |
759 | **/\r | |
760 | VOID\r | |
761 | DumpModuleInfoByIp (\r | |
762 | IN UINTN CallerIpAddress\r | |
763 | );\r | |
21c17193 | 764 | \r |
717fb604 JY |
765 | /**\r |
766 | This function sets memory attribute according to MemoryAttributesTable.\r | |
767 | **/\r | |
768 | VOID\r | |
769 | SetMemMapAttributes (\r | |
770 | VOID\r | |
771 | );\r | |
772 | \r | |
773 | /**\r | |
774 | This function sets memory attribute for page table.\r | |
775 | **/\r | |
776 | VOID\r | |
777 | SetPageTableAttributes (\r | |
778 | VOID\r | |
779 | );\r | |
780 | \r | |
781 | /**\r | |
782 | Return page table base.\r | |
783 | \r | |
784 | @return page table base.\r | |
785 | **/\r | |
786 | UINTN\r | |
787 | GetPageTableBase (\r | |
788 | VOID\r | |
789 | );\r | |
790 | \r | |
791 | /**\r | |
792 | This function sets the attributes for the memory region specified by BaseAddress and\r | |
793 | Length from their current attributes to the attributes specified by Attributes.\r | |
794 | \r | |
795 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
796 | @param[in] Length The size in bytes of the memory region.\r | |
797 | @param[in] Attributes The bit mask of attributes to set for the memory region.\r | |
798 | @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r | |
799 | \r | |
800 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
801 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
802 | BaseAddress and Length cannot be modified.\r | |
803 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
804 | Attributes specified an illegal combination of attributes that\r | |
805 | cannot be set together.\r | |
806 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
807 | the memory resource range.\r | |
808 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
809 | resource range specified by BaseAddress and Length.\r | |
810 | The bit mask of attributes is not support for the memory resource\r | |
811 | range specified by BaseAddress and Length.\r | |
812 | \r | |
813 | **/\r | |
814 | EFI_STATUS\r | |
815 | EFIAPI\r | |
816 | SmmSetMemoryAttributesEx (\r | |
817 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
818 | IN UINT64 Length,\r | |
819 | IN UINT64 Attributes,\r | |
820 | OUT BOOLEAN *IsSplitted OPTIONAL\r | |
821 | );\r | |
822 | \r | |
823 | /**\r | |
824 | This function clears the attributes for the memory region specified by BaseAddress and\r | |
825 | Length from their current attributes to the attributes specified by Attributes.\r | |
826 | \r | |
827 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
828 | @param[in] Length The size in bytes of the memory region.\r | |
829 | @param[in] Attributes The bit mask of attributes to clear for the memory region.\r | |
830 | @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r | |
831 | \r | |
832 | @retval EFI_SUCCESS The attributes were cleared for the memory region.\r | |
833 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
834 | BaseAddress and Length cannot be modified.\r | |
835 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
836 | Attributes specified an illegal combination of attributes that\r | |
837 | cannot be set together.\r | |
838 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
839 | the memory resource range.\r | |
840 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
841 | resource range specified by BaseAddress and Length.\r | |
842 | The bit mask of attributes is not support for the memory resource\r | |
843 | range specified by BaseAddress and Length.\r | |
844 | \r | |
845 | **/\r | |
846 | EFI_STATUS\r | |
847 | EFIAPI\r | |
848 | SmmClearMemoryAttributesEx (\r | |
849 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
850 | IN UINT64 Length,\r | |
851 | IN UINT64 Attributes,\r | |
852 | OUT BOOLEAN *IsSplitted OPTIONAL\r | |
853 | );\r | |
854 | \r | |
21c17193 JY |
855 | /**\r |
856 | This API provides a way to allocate memory for page table.\r | |
857 | \r | |
858 | This API can be called more once to allocate memory for page tables.\r | |
859 | \r | |
860 | Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r | |
861 | allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r | |
862 | is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r | |
863 | returned.\r | |
864 | \r | |
865 | @param Pages The number of 4 KB pages to allocate.\r | |
866 | \r | |
867 | @return A pointer to the allocated buffer or NULL if allocation fails.\r | |
868 | \r | |
869 | **/\r | |
870 | VOID *\r | |
871 | AllocatePageTableMemory (\r | |
872 | IN UINTN Pages\r | |
873 | );\r | |
874 | \r | |
717fb604 JY |
875 | /**\r |
876 | Allocate pages for code.\r | |
877 | \r | |
878 | @param[in] Pages Number of pages to be allocated.\r | |
879 | \r | |
880 | @return Allocated memory.\r | |
881 | **/\r | |
882 | VOID *\r | |
883 | AllocateCodePages (\r | |
884 | IN UINTN Pages\r | |
885 | );\r | |
886 | \r | |
887 | /**\r | |
888 | Allocate aligned pages for code.\r | |
889 | \r | |
890 | @param[in] Pages Number of pages to be allocated.\r | |
891 | @param[in] Alignment The requested alignment of the allocation.\r | |
892 | Must be a power of two.\r | |
893 | If Alignment is zero, then byte alignment is used.\r | |
894 | \r | |
895 | @return Allocated memory.\r | |
896 | **/\r | |
897 | VOID *\r | |
898 | AllocateAlignedCodePages (\r | |
899 | IN UINTN Pages,\r | |
900 | IN UINTN Alignment\r | |
901 | );\r | |
902 | \r | |
0bdc9e75 SZ |
903 | \r |
904 | //\r | |
905 | // S3 related global variable and function prototype.\r | |
906 | //\r | |
907 | \r | |
908 | extern BOOLEAN mSmmS3Flag;\r | |
909 | \r | |
910 | /**\r | |
911 | Initialize SMM S3 resume state structure used during S3 Resume.\r | |
912 | \r | |
913 | @param[in] Cr3 The base address of the page tables to use in SMM.\r | |
914 | \r | |
915 | **/\r | |
916 | VOID\r | |
917 | InitSmmS3ResumeState (\r | |
918 | IN UINT32 Cr3\r | |
919 | );\r | |
920 | \r | |
921 | /**\r | |
922 | Get ACPI CPU data.\r | |
923 | \r | |
924 | **/\r | |
925 | VOID\r | |
926 | GetAcpiCpuData (\r | |
927 | VOID\r | |
928 | );\r | |
929 | \r | |
930 | /**\r | |
931 | Restore SMM Configuration in S3 boot path.\r | |
932 | \r | |
933 | **/\r | |
934 | VOID\r | |
935 | RestoreSmmConfigurationInS3 (\r | |
936 | VOID\r | |
937 | );\r | |
938 | \r | |
b10d5ddc SZ |
939 | /**\r |
940 | Get ACPI S3 enable flag.\r | |
941 | \r | |
942 | **/\r | |
943 | VOID\r | |
944 | GetAcpiS3EnableFlag (\r | |
945 | VOID\r | |
946 | );\r | |
947 | \r | |
4a0f88dd JF |
948 | /**\r |
949 | Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r | |
950 | \r | |
672b80c8 MK |
951 | @param[in] ApHltLoopCode The address of the safe hlt-loop function.\r |
952 | @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r | |
953 | @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.\r | |
4a0f88dd JF |
954 | \r |
955 | **/\r | |
956 | VOID\r | |
957 | TransferApToSafeState (\r | |
672b80c8 MK |
958 | IN UINTN ApHltLoopCode,\r |
959 | IN UINTN TopOfStack,\r | |
960 | IN UINTN NumberToFinishAddress\r | |
4a0f88dd JF |
961 | );\r |
962 | \r | |
529a5a86 | 963 | #endif\r |