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529a5a86 MK |
1 | /** @file\r |
2 | Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r | |
3 | \r | |
f85d3ce2 | 4 | Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r |
241f9149 LD |
5 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r |
6 | \r | |
529a5a86 MK |
7 | This program and the accompanying materials\r |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #ifndef _CPU_PISMMCPUDXESMM_H_\r | |
18 | #define _CPU_PISMMCPUDXESMM_H_\r | |
19 | \r | |
20 | #include <PiSmm.h>\r | |
21 | \r | |
22 | #include <Protocol/MpService.h>\r | |
23 | #include <Protocol/SmmConfiguration.h>\r | |
24 | #include <Protocol/SmmCpu.h>\r | |
25 | #include <Protocol/SmmAccess2.h>\r | |
529a5a86 MK |
26 | #include <Protocol/SmmReadyToLock.h>\r |
27 | #include <Protocol/SmmCpuService.h>\r | |
28 | \r | |
29 | #include <Guid/AcpiS3Context.h>\r | |
717fb604 | 30 | #include <Guid/PiSmmMemoryAttributesTable.h>\r |
529a5a86 MK |
31 | \r |
32 | #include <Library/BaseLib.h>\r | |
33 | #include <Library/IoLib.h>\r | |
34 | #include <Library/TimerLib.h>\r | |
529a5a86 MK |
35 | #include <Library/SynchronizationLib.h>\r |
36 | #include <Library/DebugLib.h>\r | |
37 | #include <Library/BaseMemoryLib.h>\r | |
38 | #include <Library/PcdLib.h>\r | |
39 | #include <Library/CacheMaintenanceLib.h>\r | |
40 | #include <Library/MtrrLib.h>\r | |
41 | #include <Library/SmmCpuPlatformHookLib.h>\r | |
42 | #include <Library/SmmServicesTableLib.h>\r | |
43 | #include <Library/MemoryAllocationLib.h>\r | |
44 | #include <Library/UefiBootServicesTableLib.h>\r | |
45 | #include <Library/UefiRuntimeServicesTableLib.h>\r | |
46 | #include <Library/DebugAgentLib.h>\r | |
47 | #include <Library/HobLib.h>\r | |
48 | #include <Library/LocalApicLib.h>\r | |
49 | #include <Library/UefiCpuLib.h>\r | |
50 | #include <Library/CpuExceptionHandlerLib.h>\r | |
51 | #include <Library/ReportStatusCodeLib.h>\r | |
52 | #include <Library/SmmCpuFeaturesLib.h>\r | |
53 | #include <Library/PeCoffGetEntryPointLib.h>\r | |
54 | \r | |
55 | #include <AcpiCpuData.h>\r | |
56 | #include <CpuHotPlugData.h>\r | |
57 | \r | |
58 | #include <Register/Cpuid.h>\r | |
f85d3ce2 | 59 | #include <Register/Msr.h>\r |
529a5a86 MK |
60 | \r |
61 | #include "CpuService.h"\r | |
62 | #include "SmmProfile.h"\r | |
63 | \r | |
64 | //\r | |
65 | // MSRs required for configuration of SMM Code Access Check\r | |
66 | //\r | |
67 | #define EFI_MSR_SMM_MCA_CAP 0x17D\r | |
68 | #define SMM_CODE_ACCESS_CHK_BIT BIT58\r | |
69 | \r | |
70 | #define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r | |
71 | #define SMM_CODE_CHK_EN_BIT BIT2\r | |
72 | \r | |
73 | ///\r | |
74 | /// Page Table Entry\r | |
75 | ///\r | |
76 | #define IA32_PG_P BIT0\r | |
77 | #define IA32_PG_RW BIT1\r | |
881520ea | 78 | #define IA32_PG_U BIT2\r |
529a5a86 MK |
79 | #define IA32_PG_WT BIT3\r |
80 | #define IA32_PG_CD BIT4\r | |
81 | #define IA32_PG_A BIT5\r | |
881520ea | 82 | #define IA32_PG_D BIT6\r |
529a5a86 MK |
83 | #define IA32_PG_PS BIT7\r |
84 | #define IA32_PG_PAT_2M BIT12\r | |
85 | #define IA32_PG_PAT_4K IA32_PG_PS\r | |
86 | #define IA32_PG_PMNT BIT62\r | |
87 | #define IA32_PG_NX BIT63\r | |
88 | \r | |
717fb604 | 89 | #define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r |
881520ea JY |
90 | //\r |
91 | // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r | |
92 | // X64 PAE PDPTE does not have such restriction\r | |
93 | //\r | |
94 | #define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r | |
95 | \r | |
717fb604 JY |
96 | #define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r |
97 | \r | |
98 | #define PAGING_4K_MASK 0xFFF\r | |
99 | #define PAGING_2M_MASK 0x1FFFFF\r | |
100 | #define PAGING_1G_MASK 0x3FFFFFFF\r | |
101 | \r | |
102 | #define PAGING_PAE_INDEX_MASK 0x1FF\r | |
103 | \r | |
104 | #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r | |
105 | #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r | |
106 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r | |
107 | \r | |
108 | typedef enum {\r | |
109 | PageNone,\r | |
110 | Page4K,\r | |
111 | Page2M,\r | |
112 | Page1G,\r | |
113 | } PAGE_ATTRIBUTE;\r | |
114 | \r | |
115 | typedef struct {\r | |
116 | PAGE_ATTRIBUTE Attribute;\r | |
117 | UINT64 Length;\r | |
118 | UINT64 AddressMask;\r | |
119 | } PAGE_ATTRIBUTE_TABLE;\r | |
120 | \r | |
529a5a86 MK |
121 | //\r |
122 | // Size of Task-State Segment defined in IA32 Manual\r | |
123 | //\r | |
124 | #define TSS_SIZE 104\r | |
125 | #define TSS_X64_IST1_OFFSET 36\r | |
126 | #define TSS_IA32_CR3_OFFSET 28\r | |
127 | #define TSS_IA32_ESP_OFFSET 56\r | |
128 | \r | |
717fb604 JY |
129 | #define CR0_WP BIT16\r |
130 | \r | |
529a5a86 MK |
131 | //\r |
132 | // Code select value\r | |
133 | //\r | |
134 | #define PROTECT_MODE_CODE_SEGMENT 0x08\r | |
135 | #define LONG_MODE_CODE_SEGMENT 0x38\r | |
136 | \r | |
137 | //\r | |
138 | // The size 0x20 must be bigger than\r | |
139 | // the size of template code of SmmInit. Currently,\r | |
140 | // the size of SmmInit requires the 0x16 Bytes buffer\r | |
141 | // at least.\r | |
142 | //\r | |
143 | #define BACK_BUF_SIZE 0x20\r | |
144 | \r | |
145 | #define EXCEPTION_VECTOR_NUMBER 0x20\r | |
146 | \r | |
147 | #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r | |
148 | \r | |
149 | typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r | |
150 | #define ARRIVAL_EXCEPTION_BLOCKED 0x1\r | |
151 | #define ARRIVAL_EXCEPTION_DELAYED 0x2\r | |
152 | #define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r | |
153 | \r | |
154 | //\r | |
155 | // Private structure for the SMM CPU module that is stored in DXE Runtime memory\r | |
156 | // Contains the SMM Configuration Protocols that is produced.\r | |
157 | // Contains a mix of DXE and SMM contents. All the fields must be used properly.\r | |
158 | //\r | |
159 | #define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r | |
160 | \r | |
161 | typedef struct {\r | |
162 | UINTN Signature;\r | |
163 | \r | |
164 | EFI_HANDLE SmmCpuHandle;\r | |
165 | \r | |
166 | EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r | |
167 | SMM_CPU_OPERATION *Operation;\r | |
168 | UINTN *CpuSaveStateSize;\r | |
169 | VOID **CpuSaveState;\r | |
170 | \r | |
171 | EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r | |
172 | EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r | |
173 | EFI_SMM_ENTRY_POINT SmmCoreEntry;\r | |
174 | \r | |
175 | EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r | |
176 | } SMM_CPU_PRIVATE_DATA;\r | |
177 | \r | |
178 | extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r | |
179 | extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r | |
180 | extern UINTN mMaxNumberOfCpus;\r | |
181 | extern UINTN mNumberOfCpus;\r | |
529a5a86 MK |
182 | extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r |
183 | \r | |
184 | ///\r | |
185 | /// The mode of the CPU at the time an SMI occurs\r | |
186 | ///\r | |
187 | extern UINT8 mSmmSaveStateRegisterLma;\r | |
188 | \r | |
529a5a86 MK |
189 | //\r |
190 | // SMM CPU Protocol function prototypes.\r | |
191 | //\r | |
192 | \r | |
193 | /**\r | |
194 | Read information from the CPU save state.\r | |
195 | \r | |
196 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
197 | @param Width The number of bytes to read from the CPU save state.\r | |
198 | @param Register Specifies the CPU register to read form the save state.\r | |
199 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
200 | @param Buffer Upon return, this holds the CPU register value read from the save state.\r | |
201 | \r | |
202 | @retval EFI_SUCCESS The register was read from Save State\r | |
203 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
204 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
205 | \r | |
206 | **/\r | |
207 | EFI_STATUS\r | |
208 | EFIAPI\r | |
209 | SmmReadSaveState (\r | |
210 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
211 | IN UINTN Width,\r | |
212 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
213 | IN UINTN CpuIndex,\r | |
214 | OUT VOID *Buffer\r | |
215 | );\r | |
216 | \r | |
217 | /**\r | |
218 | Write data to the CPU save state.\r | |
219 | \r | |
220 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
221 | @param Width The number of bytes to read from the CPU save state.\r | |
222 | @param Register Specifies the CPU register to write to the save state.\r | |
223 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
224 | @param Buffer Upon entry, this holds the new CPU register value.\r | |
225 | \r | |
226 | @retval EFI_SUCCESS The register was written from Save State\r | |
227 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
228 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r | |
229 | \r | |
230 | **/\r | |
231 | EFI_STATUS\r | |
232 | EFIAPI\r | |
233 | SmmWriteSaveState (\r | |
234 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
235 | IN UINTN Width,\r | |
236 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
237 | IN UINTN CpuIndex,\r | |
238 | IN CONST VOID *Buffer\r | |
239 | );\r | |
240 | \r | |
241 | /**\r | |
242 | Read a CPU Save State register on the target processor.\r | |
243 | \r | |
244 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
245 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
246 | \r | |
247 | This function supports reading a CPU Save State register in SMBase relocation handler.\r | |
248 | \r | |
249 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
250 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
251 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
252 | @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r | |
253 | \r | |
254 | @retval EFI_SUCCESS The register was read from Save State.\r | |
255 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
256 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
257 | \r | |
258 | **/\r | |
259 | EFI_STATUS\r | |
260 | EFIAPI\r | |
261 | ReadSaveStateRegister (\r | |
262 | IN UINTN CpuIndex,\r | |
263 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
264 | IN UINTN Width,\r | |
265 | OUT VOID *Buffer\r | |
266 | );\r | |
267 | \r | |
268 | /**\r | |
269 | Write value to a CPU Save State register on the target processor.\r | |
270 | \r | |
271 | This function abstracts the differences that whether the CPU Save State register is in the\r | |
272 | IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
273 | \r | |
274 | This function supports writing a CPU Save State register in SMBase relocation handler.\r | |
275 | \r | |
276 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
277 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r | |
278 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
279 | @param[in] Buffer Upon entry, this holds the new CPU register value.\r | |
280 | \r | |
281 | @retval EFI_SUCCESS The register was written to Save State.\r | |
282 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
283 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r | |
284 | \r | |
285 | **/\r | |
286 | EFI_STATUS\r | |
287 | EFIAPI\r | |
288 | WriteSaveStateRegister (\r | |
289 | IN UINTN CpuIndex,\r | |
290 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
291 | IN UINTN Width,\r | |
292 | IN CONST VOID *Buffer\r | |
293 | );\r | |
294 | \r | |
295 | //\r | |
296 | //\r | |
297 | //\r | |
298 | typedef struct {\r | |
299 | UINT32 Offset;\r | |
300 | UINT16 Segment;\r | |
301 | UINT16 Reserved;\r | |
302 | } IA32_FAR_ADDRESS;\r | |
303 | \r | |
304 | extern IA32_FAR_ADDRESS gSmmJmpAddr;\r | |
305 | \r | |
306 | extern CONST UINT8 gcSmmInitTemplate[];\r | |
307 | extern CONST UINT16 gcSmmInitSize;\r | |
308 | extern UINT32 gSmmCr0;\r | |
309 | extern UINT32 gSmmCr3;\r | |
310 | extern UINT32 gSmmCr4;\r | |
311 | extern UINTN gSmmInitStack;\r | |
312 | \r | |
313 | /**\r | |
314 | Semaphore operation for all processor relocate SMMBase.\r | |
315 | **/\r | |
316 | VOID\r | |
317 | EFIAPI\r | |
318 | SmmRelocationSemaphoreComplete (\r | |
319 | VOID\r | |
320 | );\r | |
321 | \r | |
322 | ///\r | |
323 | /// The type of SMM CPU Information\r | |
324 | ///\r | |
325 | typedef struct {\r | |
ed3d5ecb | 326 | SPIN_LOCK *Busy;\r |
529a5a86 MK |
327 | volatile EFI_AP_PROCEDURE Procedure;\r |
328 | volatile VOID *Parameter;\r | |
ed3d5ecb JF |
329 | volatile UINT32 *Run;\r |
330 | volatile BOOLEAN *Present;\r | |
529a5a86 MK |
331 | } SMM_CPU_DATA_BLOCK;\r |
332 | \r | |
333 | typedef enum {\r | |
334 | SmmCpuSyncModeTradition,\r | |
335 | SmmCpuSyncModeRelaxedAp,\r | |
336 | SmmCpuSyncModeMax\r | |
337 | } SMM_CPU_SYNC_MODE;\r | |
338 | \r | |
339 | typedef struct {\r | |
340 | //\r | |
341 | // Pointer to an array. The array should be located immediately after this structure\r | |
342 | // so that UC cache-ability can be set together.\r | |
343 | //\r | |
344 | SMM_CPU_DATA_BLOCK *CpuData;\r | |
fe3a75bc | 345 | volatile UINT32 *Counter;\r |
529a5a86 | 346 | volatile UINT32 BspIndex;\r |
fe3a75bc JF |
347 | volatile BOOLEAN *InsideSmm;\r |
348 | volatile BOOLEAN *AllCpusInSync;\r | |
529a5a86 MK |
349 | volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r |
350 | volatile BOOLEAN SwitchBsp;\r | |
351 | volatile BOOLEAN *CandidateBsp;\r | |
352 | } SMM_DISPATCHER_MP_SYNC_DATA;\r | |
353 | \r | |
695e62d1 JF |
354 | #define MSR_SPIN_LOCK_INIT_NUM 15\r |
355 | \r | |
529a5a86 | 356 | typedef struct {\r |
dc99315b | 357 | SPIN_LOCK *SpinLock;\r |
529a5a86 MK |
358 | UINT32 MsrIndex;\r |
359 | } MP_MSR_LOCK;\r | |
360 | \r | |
361 | #define SMM_PSD_OFFSET 0xfb00\r | |
362 | \r | |
1d648531 JF |
363 | ///\r |
364 | /// All global semaphores' pointer\r | |
365 | ///\r | |
366 | typedef struct {\r | |
367 | volatile UINT32 *Counter;\r | |
368 | volatile BOOLEAN *InsideSmm;\r | |
369 | volatile BOOLEAN *AllCpusInSync;\r | |
370 | SPIN_LOCK *PFLock;\r | |
371 | SPIN_LOCK *CodeAccessCheckLock;\r | |
6c4c15fa | 372 | SPIN_LOCK *MemoryMappedLock;\r |
1d648531 JF |
373 | } SMM_CPU_SEMAPHORE_GLOBAL;\r |
374 | \r | |
4e920581 JF |
375 | ///\r |
376 | /// All semaphores for each processor\r | |
377 | ///\r | |
378 | typedef struct {\r | |
379 | SPIN_LOCK *Busy;\r | |
380 | volatile UINT32 *Run;\r | |
381 | volatile BOOLEAN *Present;\r | |
382 | } SMM_CPU_SEMAPHORE_CPU;\r | |
383 | \r | |
695e62d1 JF |
384 | ///\r |
385 | /// All MSRs semaphores' pointer and counter\r | |
386 | ///\r | |
387 | typedef struct {\r | |
388 | SPIN_LOCK *Msr;\r | |
389 | UINTN AvailableCounter;\r | |
390 | } SMM_CPU_SEMAPHORE_MSR;\r | |
4e920581 | 391 | \r |
1d648531 JF |
392 | ///\r |
393 | /// All semaphores' information\r | |
394 | ///\r | |
395 | typedef struct {\r | |
396 | SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r | |
4e920581 | 397 | SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r |
695e62d1 | 398 | SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;\r |
1d648531 JF |
399 | } SMM_CPU_SEMAPHORES;\r |
400 | \r | |
529a5a86 | 401 | extern IA32_DESCRIPTOR gcSmiGdtr;\r |
717fb604 JY |
402 | extern EFI_PHYSICAL_ADDRESS mGdtBuffer;\r |
403 | extern UINTN mGdtBufferSize;\r | |
529a5a86 MK |
404 | extern IA32_DESCRIPTOR gcSmiIdtr;\r |
405 | extern VOID *gcSmiIdtrPtr;\r | |
529a5a86 | 406 | extern UINT64 gPhyMask;\r |
529a5a86 | 407 | extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r |
529a5a86 MK |
408 | extern UINTN mSmmStackArrayBase;\r |
409 | extern UINTN mSmmStackArrayEnd;\r | |
410 | extern UINTN mSmmStackSize;\r | |
411 | extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r | |
412 | extern IA32_DESCRIPTOR gcSmiInitGdtr;\r | |
dc99315b JF |
413 | extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r |
414 | extern UINTN mSemaphoreSize;\r | |
fe3a75bc JF |
415 | extern SPIN_LOCK *mPFLock;\r |
416 | extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r | |
6c4c15fa | 417 | extern SPIN_LOCK *mMemoryMappedLock;\r |
529a5a86 | 418 | \r |
241f9149 LD |
419 | //\r |
420 | // Copy of the PcdPteMemoryEncryptionAddressOrMask\r | |
421 | //\r | |
422 | extern UINT64 mAddressEncMask;\r | |
423 | \r | |
529a5a86 MK |
424 | /**\r |
425 | Create 4G PageTable in SMRAM.\r | |
426 | \r | |
717fb604 | 427 | @param[in] Is32BitPageTable Whether the page table is 32-bit PAE\r |
529a5a86 MK |
428 | @return PageTable Address\r |
429 | \r | |
430 | **/\r | |
431 | UINT32\r | |
432 | Gen4GPageTable (\r | |
881520ea | 433 | IN BOOLEAN Is32BitPageTable\r |
529a5a86 MK |
434 | );\r |
435 | \r | |
436 | \r | |
437 | /**\r | |
438 | Initialize global data for MP synchronization.\r | |
439 | \r | |
440 | @param Stacks Base address of SMI stack buffer for all processors.\r | |
441 | @param StackSize Stack size for each processor in SMM.\r | |
442 | \r | |
443 | **/\r | |
444 | UINT32\r | |
445 | InitializeMpServiceData (\r | |
446 | IN VOID *Stacks,\r | |
447 | IN UINTN StackSize\r | |
448 | );\r | |
449 | \r | |
450 | /**\r | |
451 | Initialize Timer for SMM AP Sync.\r | |
452 | \r | |
453 | **/\r | |
454 | VOID\r | |
455 | InitializeSmmTimer (\r | |
456 | VOID\r | |
457 | );\r | |
458 | \r | |
459 | /**\r | |
460 | Start Timer for SMM AP Sync.\r | |
461 | \r | |
462 | **/\r | |
463 | UINT64\r | |
464 | EFIAPI\r | |
465 | StartSyncTimer (\r | |
466 | VOID\r | |
467 | );\r | |
468 | \r | |
469 | /**\r | |
470 | Check if the SMM AP Sync timer is timeout.\r | |
471 | \r | |
472 | @param Timer The start timer from the begin.\r | |
473 | \r | |
474 | **/\r | |
475 | BOOLEAN\r | |
476 | EFIAPI\r | |
477 | IsSyncTimerTimeout (\r | |
478 | IN UINT64 Timer\r | |
479 | );\r | |
480 | \r | |
481 | /**\r | |
482 | Initialize IDT for SMM Stack Guard.\r | |
483 | \r | |
484 | **/\r | |
485 | VOID\r | |
486 | EFIAPI\r | |
487 | InitializeIDTSmmStackGuard (\r | |
488 | VOID\r | |
489 | );\r | |
490 | \r | |
fe5f1949 JY |
491 | /**\r |
492 | Initialize Gdt for all processors.\r | |
717fb604 | 493 | \r |
fe5f1949 JY |
494 | @param[in] Cr3 CR3 value.\r |
495 | @param[out] GdtStepSize The step size for GDT table.\r | |
496 | \r | |
497 | @return GdtBase for processor 0.\r | |
498 | GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r | |
499 | **/\r | |
500 | VOID *\r | |
501 | InitGdt (\r | |
502 | IN UINTN Cr3,\r | |
503 | OUT UINTN *GdtStepSize\r | |
504 | );\r | |
505 | \r | |
e4435f71 JY |
506 | /**\r |
507 | This function sets GDT/IDT buffer to be RO and XP.\r | |
508 | **/\r | |
509 | VOID\r | |
510 | PatchGdtIdtMap (\r | |
511 | VOID\r | |
512 | );\r | |
513 | \r | |
529a5a86 MK |
514 | /**\r |
515 | \r | |
516 | Register the SMM Foundation entry point.\r | |
517 | \r | |
518 | @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance\r | |
519 | @param SmmEntryPoint SMM Foundation EntryPoint\r | |
520 | \r | |
521 | @retval EFI_SUCCESS Successfully to register SMM foundation entry point\r | |
522 | \r | |
523 | **/\r | |
524 | EFI_STATUS\r | |
525 | EFIAPI\r | |
526 | RegisterSmmEntry (\r | |
527 | IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,\r | |
528 | IN EFI_SMM_ENTRY_POINT SmmEntryPoint\r | |
529 | );\r | |
530 | \r | |
531 | /**\r | |
532 | Create PageTable for SMM use.\r | |
533 | \r | |
534 | @return PageTable Address\r | |
535 | \r | |
536 | **/\r | |
537 | UINT32\r | |
538 | SmmInitPageTable (\r | |
539 | VOID\r | |
540 | );\r | |
541 | \r | |
542 | /**\r | |
543 | Schedule a procedure to run on the specified CPU.\r | |
544 | \r | |
545 | @param Procedure The address of the procedure to run\r | |
546 | @param CpuIndex Target CPU number\r | |
547 | @param ProcArguments The parameter to pass to the procedure\r | |
548 | \r | |
549 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
550 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
551 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
552 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
553 | @retval EFI_SUCCESS - The procedure has been successfully scheduled\r | |
554 | \r | |
555 | **/\r | |
556 | EFI_STATUS\r | |
557 | EFIAPI\r | |
558 | SmmStartupThisAp (\r | |
559 | IN EFI_AP_PROCEDURE Procedure,\r | |
560 | IN UINTN CpuIndex,\r | |
561 | IN OUT VOID *ProcArguments OPTIONAL\r | |
562 | );\r | |
563 | \r | |
564 | /**\r | |
565 | Schedule a procedure to run on the specified CPU in a blocking fashion.\r | |
566 | \r | |
567 | @param Procedure The address of the procedure to run\r | |
568 | @param CpuIndex Target CPU Index\r | |
569 | @param ProcArguments The parameter to pass to the procedure\r | |
570 | \r | |
571 | @retval EFI_INVALID_PARAMETER CpuNumber not valid\r | |
572 | @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP\r | |
573 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM\r | |
574 | @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy\r | |
575 | @retval EFI_SUCCESS The procedure has been successfully scheduled\r | |
576 | \r | |
577 | **/\r | |
578 | EFI_STATUS\r | |
579 | EFIAPI\r | |
580 | SmmBlockingStartupThisAp (\r | |
581 | IN EFI_AP_PROCEDURE Procedure,\r | |
582 | IN UINTN CpuIndex,\r | |
583 | IN OUT VOID *ProcArguments OPTIONAL\r | |
584 | );\r | |
585 | \r | |
e4435f71 JY |
586 | /**\r |
587 | This function sets the attributes for the memory region specified by BaseAddress and\r | |
588 | Length from their current attributes to the attributes specified by Attributes.\r | |
589 | \r | |
590 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
591 | @param[in] Length The size in bytes of the memory region.\r | |
592 | @param[in] Attributes The bit mask of attributes to set for the memory region.\r | |
593 | \r | |
594 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
595 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
596 | BaseAddress and Length cannot be modified.\r | |
597 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
598 | Attributes specified an illegal combination of attributes that\r | |
599 | cannot be set together.\r | |
600 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
601 | the memory resource range.\r | |
602 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
603 | resource range specified by BaseAddress and Length.\r | |
604 | The bit mask of attributes is not support for the memory resource\r | |
605 | range specified by BaseAddress and Length.\r | |
606 | \r | |
607 | **/\r | |
608 | EFI_STATUS\r | |
609 | EFIAPI\r | |
610 | SmmSetMemoryAttributes (\r | |
611 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
612 | IN UINT64 Length,\r | |
613 | IN UINT64 Attributes\r | |
614 | );\r | |
615 | \r | |
616 | /**\r | |
617 | This function clears the attributes for the memory region specified by BaseAddress and\r | |
618 | Length from their current attributes to the attributes specified by Attributes.\r | |
619 | \r | |
620 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
621 | @param[in] Length The size in bytes of the memory region.\r | |
622 | @param[in] Attributes The bit mask of attributes to clear for the memory region.\r | |
623 | \r | |
624 | @retval EFI_SUCCESS The attributes were cleared for the memory region.\r | |
625 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
626 | BaseAddress and Length cannot be modified.\r | |
627 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
628 | Attributes specified an illegal combination of attributes that\r | |
629 | cannot be set together.\r | |
630 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
631 | the memory resource range.\r | |
632 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
633 | resource range specified by BaseAddress and Length.\r | |
634 | The bit mask of attributes is not support for the memory resource\r | |
635 | range specified by BaseAddress and Length.\r | |
636 | \r | |
637 | **/\r | |
638 | EFI_STATUS\r | |
639 | EFIAPI\r | |
640 | SmmClearMemoryAttributes (\r | |
641 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
642 | IN UINT64 Length,\r | |
643 | IN UINT64 Attributes\r | |
644 | );\r | |
645 | \r | |
529a5a86 MK |
646 | /**\r |
647 | Initialize MP synchronization data.\r | |
648 | \r | |
649 | **/\r | |
650 | VOID\r | |
651 | EFIAPI\r | |
652 | InitializeMpSyncData (\r | |
653 | VOID\r | |
654 | );\r | |
655 | \r | |
656 | /**\r | |
657 | \r | |
658 | Find out SMRAM information including SMRR base and SMRR size.\r | |
659 | \r | |
660 | @param SmrrBase SMRR base\r | |
661 | @param SmrrSize SMRR size\r | |
662 | \r | |
663 | **/\r | |
664 | VOID\r | |
665 | FindSmramInfo (\r | |
666 | OUT UINT32 *SmrrBase,\r | |
667 | OUT UINT32 *SmrrSize\r | |
668 | );\r | |
669 | \r | |
670 | /**\r | |
0bdc9e75 | 671 | Relocate SmmBases for each processor.\r |
529a5a86 | 672 | \r |
0bdc9e75 | 673 | Execute on first boot and all S3 resumes\r |
529a5a86 MK |
674 | \r |
675 | **/\r | |
676 | VOID\r | |
0bdc9e75 SZ |
677 | EFIAPI\r |
678 | SmmRelocateBases (\r | |
529a5a86 MK |
679 | VOID\r |
680 | );\r | |
681 | \r | |
682 | /**\r | |
683 | Page Fault handler for SMM use.\r | |
684 | \r | |
685 | @param InterruptType Defines the type of interrupt or exception that\r | |
686 | occurred on the processor.This parameter is processor architecture specific.\r | |
687 | @param SystemContext A pointer to the processor context when\r | |
688 | the interrupt occurred on the processor.\r | |
689 | **/\r | |
690 | VOID\r | |
691 | EFIAPI\r | |
692 | SmiPFHandler (\r | |
693 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
694 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
695 | );\r | |
696 | \r | |
697 | /**\r | |
698 | Perform the remaining tasks.\r | |
699 | \r | |
700 | **/\r | |
701 | VOID\r | |
702 | PerformRemainingTasks (\r | |
703 | VOID\r | |
704 | );\r | |
705 | \r | |
9f419739 JY |
706 | /**\r |
707 | Perform the pre tasks.\r | |
708 | \r | |
709 | **/\r | |
710 | VOID\r | |
711 | PerformPreTasks (\r | |
712 | VOID\r | |
713 | );\r | |
714 | \r | |
529a5a86 MK |
715 | /**\r |
716 | Initialize MSR spin lock by MSR index.\r | |
717 | \r | |
718 | @param MsrIndex MSR index value.\r | |
719 | \r | |
720 | **/\r | |
721 | VOID\r | |
722 | InitMsrSpinLockByIndex (\r | |
723 | IN UINT32 MsrIndex\r | |
724 | );\r | |
725 | \r | |
726 | /**\r | |
727 | Hook return address of SMM Save State so that semaphore code\r | |
728 | can be executed immediately after AP exits SMM to indicate to\r | |
729 | the BSP that an AP has exited SMM after SMBASE relocation.\r | |
730 | \r | |
731 | @param[in] CpuIndex The processor index.\r | |
732 | @param[in] RebasedFlag A pointer to a flag that is set to TRUE\r | |
733 | immediately after AP exits SMM.\r | |
734 | \r | |
735 | **/\r | |
736 | VOID\r | |
737 | SemaphoreHook (\r | |
738 | IN UINTN CpuIndex,\r | |
739 | IN volatile BOOLEAN *RebasedFlag\r | |
740 | );\r | |
741 | \r | |
742 | /**\r | |
743 | Configure SMM Code Access Check feature for all processors.\r | |
744 | SMM Feature Control MSR will be locked after configuration.\r | |
745 | **/\r | |
746 | VOID\r | |
747 | ConfigSmmCodeAccessCheck (\r | |
748 | VOID\r | |
749 | );\r | |
750 | \r | |
751 | /**\r | |
752 | Hook the code executed immediately after an RSM instruction on the currently\r | |
753 | executing CPU. The mode of code executed immediately after RSM must be\r | |
754 | detected, and the appropriate hook must be selected. Always clear the auto\r | |
755 | HALT restart flag if it is set.\r | |
756 | \r | |
757 | @param[in] CpuIndex The processor index for the currently\r | |
758 | executing CPU.\r | |
759 | @param[in] CpuState Pointer to SMRAM Save State Map for the\r | |
760 | currently executing CPU.\r | |
761 | @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r | |
762 | 32-bit mode from 64-bit SMM.\r | |
763 | @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r | |
764 | same mode as SMM.\r | |
765 | \r | |
766 | @retval The value of the original instruction pointer before it was hooked.\r | |
767 | \r | |
768 | **/\r | |
769 | UINT64\r | |
770 | EFIAPI\r | |
771 | HookReturnFromSmm (\r | |
772 | IN UINTN CpuIndex,\r | |
773 | SMRAM_SAVE_STATE_MAP *CpuState,\r | |
774 | UINT64 NewInstructionPointer32,\r | |
775 | UINT64 NewInstructionPointer\r | |
776 | );\r | |
777 | \r | |
778 | /**\r | |
779 | Get the size of the SMI Handler in bytes.\r | |
780 | \r | |
781 | @retval The size, in bytes, of the SMI Handler.\r | |
782 | \r | |
783 | **/\r | |
784 | UINTN\r | |
785 | EFIAPI\r | |
786 | GetSmiHandlerSize (\r | |
787 | VOID\r | |
788 | );\r | |
789 | \r | |
790 | /**\r | |
791 | Install the SMI handler for the CPU specified by CpuIndex. This function\r | |
792 | is called by the CPU that was elected as monarch during System Management\r | |
793 | Mode initialization.\r | |
794 | \r | |
795 | @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r | |
796 | The value must be between 0 and the NumberOfCpus field\r | |
797 | in the System Management System Table (SMST).\r | |
798 | @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r | |
799 | @param[in] SmiStack The stack to use when an SMI is processed by the\r | |
800 | the CPU specified by CpuIndex.\r | |
801 | @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r | |
802 | processed by the CPU specified by CpuIndex.\r | |
803 | @param[in] GdtBase The base address of the GDT to use when an SMI is\r | |
804 | processed by the CPU specified by CpuIndex.\r | |
805 | @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r | |
806 | processed by the CPU specified by CpuIndex.\r | |
807 | @param[in] IdtBase The base address of the IDT to use when an SMI is\r | |
808 | processed by the CPU specified by CpuIndex.\r | |
809 | @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r | |
810 | processed by the CPU specified by CpuIndex.\r | |
811 | @param[in] Cr3 The base address of the page tables to use when an SMI\r | |
812 | is processed by the CPU specified by CpuIndex.\r | |
813 | **/\r | |
814 | VOID\r | |
815 | EFIAPI\r | |
816 | InstallSmiHandler (\r | |
817 | IN UINTN CpuIndex,\r | |
818 | IN UINT32 SmBase,\r | |
819 | IN VOID *SmiStack,\r | |
820 | IN UINTN StackSize,\r | |
821 | IN UINTN GdtBase,\r | |
822 | IN UINTN GdtSize,\r | |
823 | IN UINTN IdtBase,\r | |
824 | IN UINTN IdtSize,\r | |
825 | IN UINT32 Cr3\r | |
826 | );\r | |
827 | \r | |
828 | /**\r | |
829 | Search module name by input IP address and output it.\r | |
830 | \r | |
831 | @param CallerIpAddress Caller instruction pointer.\r | |
832 | \r | |
833 | **/\r | |
834 | VOID\r | |
835 | DumpModuleInfoByIp (\r | |
836 | IN UINTN CallerIpAddress\r | |
837 | );\r | |
21c17193 | 838 | \r |
717fb604 JY |
839 | /**\r |
840 | This function sets memory attribute according to MemoryAttributesTable.\r | |
841 | **/\r | |
842 | VOID\r | |
843 | SetMemMapAttributes (\r | |
844 | VOID\r | |
845 | );\r | |
846 | \r | |
d2fc7711 JY |
847 | /**\r |
848 | This function sets UEFI memory attribute according to UEFI memory map.\r | |
849 | **/\r | |
850 | VOID\r | |
851 | SetUefiMemMapAttributes (\r | |
852 | VOID\r | |
853 | );\r | |
854 | \r | |
855 | /**\r | |
856 | Return if the Address is forbidden as SMM communication buffer.\r | |
857 | \r | |
858 | @param[in] Address the address to be checked\r | |
859 | \r | |
860 | @return TRUE The address is forbidden as SMM communication buffer.\r | |
861 | @return FALSE The address is allowed as SMM communication buffer.\r | |
862 | **/\r | |
863 | BOOLEAN\r | |
864 | IsSmmCommBufferForbiddenAddress (\r | |
865 | IN UINT64 Address\r | |
866 | );\r | |
867 | \r | |
868 | /**\r | |
869 | This function caches the UEFI memory map information.\r | |
870 | **/\r | |
871 | VOID\r | |
872 | GetUefiMemoryMap (\r | |
873 | VOID\r | |
874 | );\r | |
875 | \r | |
717fb604 JY |
876 | /**\r |
877 | This function sets memory attribute for page table.\r | |
878 | **/\r | |
879 | VOID\r | |
880 | SetPageTableAttributes (\r | |
881 | VOID\r | |
882 | );\r | |
883 | \r | |
884 | /**\r | |
885 | Return page table base.\r | |
886 | \r | |
887 | @return page table base.\r | |
888 | **/\r | |
889 | UINTN\r | |
890 | GetPageTableBase (\r | |
891 | VOID\r | |
892 | );\r | |
893 | \r | |
894 | /**\r | |
895 | This function sets the attributes for the memory region specified by BaseAddress and\r | |
896 | Length from their current attributes to the attributes specified by Attributes.\r | |
897 | \r | |
898 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
899 | @param[in] Length The size in bytes of the memory region.\r | |
900 | @param[in] Attributes The bit mask of attributes to set for the memory region.\r | |
901 | @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r | |
902 | \r | |
903 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
904 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
905 | BaseAddress and Length cannot be modified.\r | |
906 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
907 | Attributes specified an illegal combination of attributes that\r | |
908 | cannot be set together.\r | |
909 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
910 | the memory resource range.\r | |
911 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
912 | resource range specified by BaseAddress and Length.\r | |
913 | The bit mask of attributes is not support for the memory resource\r | |
914 | range specified by BaseAddress and Length.\r | |
915 | \r | |
916 | **/\r | |
917 | EFI_STATUS\r | |
918 | EFIAPI\r | |
919 | SmmSetMemoryAttributesEx (\r | |
920 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
921 | IN UINT64 Length,\r | |
922 | IN UINT64 Attributes,\r | |
923 | OUT BOOLEAN *IsSplitted OPTIONAL\r | |
924 | );\r | |
925 | \r | |
926 | /**\r | |
927 | This function clears the attributes for the memory region specified by BaseAddress and\r | |
928 | Length from their current attributes to the attributes specified by Attributes.\r | |
929 | \r | |
930 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
931 | @param[in] Length The size in bytes of the memory region.\r | |
932 | @param[in] Attributes The bit mask of attributes to clear for the memory region.\r | |
933 | @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r | |
934 | \r | |
935 | @retval EFI_SUCCESS The attributes were cleared for the memory region.\r | |
936 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
937 | BaseAddress and Length cannot be modified.\r | |
938 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
939 | Attributes specified an illegal combination of attributes that\r | |
940 | cannot be set together.\r | |
941 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
942 | the memory resource range.\r | |
943 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
944 | resource range specified by BaseAddress and Length.\r | |
945 | The bit mask of attributes is not support for the memory resource\r | |
946 | range specified by BaseAddress and Length.\r | |
947 | \r | |
948 | **/\r | |
949 | EFI_STATUS\r | |
950 | EFIAPI\r | |
951 | SmmClearMemoryAttributesEx (\r | |
952 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
953 | IN UINT64 Length,\r | |
954 | IN UINT64 Attributes,\r | |
955 | OUT BOOLEAN *IsSplitted OPTIONAL\r | |
956 | );\r | |
957 | \r | |
21c17193 JY |
958 | /**\r |
959 | This API provides a way to allocate memory for page table.\r | |
960 | \r | |
961 | This API can be called more once to allocate memory for page tables.\r | |
962 | \r | |
963 | Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r | |
964 | allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r | |
965 | is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r | |
966 | returned.\r | |
967 | \r | |
968 | @param Pages The number of 4 KB pages to allocate.\r | |
969 | \r | |
970 | @return A pointer to the allocated buffer or NULL if allocation fails.\r | |
971 | \r | |
972 | **/\r | |
973 | VOID *\r | |
974 | AllocatePageTableMemory (\r | |
975 | IN UINTN Pages\r | |
976 | );\r | |
977 | \r | |
717fb604 JY |
978 | /**\r |
979 | Allocate pages for code.\r | |
980 | \r | |
981 | @param[in] Pages Number of pages to be allocated.\r | |
982 | \r | |
983 | @return Allocated memory.\r | |
984 | **/\r | |
985 | VOID *\r | |
986 | AllocateCodePages (\r | |
987 | IN UINTN Pages\r | |
988 | );\r | |
989 | \r | |
990 | /**\r | |
991 | Allocate aligned pages for code.\r | |
992 | \r | |
993 | @param[in] Pages Number of pages to be allocated.\r | |
994 | @param[in] Alignment The requested alignment of the allocation.\r | |
995 | Must be a power of two.\r | |
996 | If Alignment is zero, then byte alignment is used.\r | |
997 | \r | |
998 | @return Allocated memory.\r | |
999 | **/\r | |
1000 | VOID *\r | |
1001 | AllocateAlignedCodePages (\r | |
1002 | IN UINTN Pages,\r | |
1003 | IN UINTN Alignment\r | |
1004 | );\r | |
1005 | \r | |
0bdc9e75 SZ |
1006 | \r |
1007 | //\r | |
1008 | // S3 related global variable and function prototype.\r | |
1009 | //\r | |
1010 | \r | |
1011 | extern BOOLEAN mSmmS3Flag;\r | |
1012 | \r | |
1013 | /**\r | |
1014 | Initialize SMM S3 resume state structure used during S3 Resume.\r | |
1015 | \r | |
1016 | @param[in] Cr3 The base address of the page tables to use in SMM.\r | |
1017 | \r | |
1018 | **/\r | |
1019 | VOID\r | |
1020 | InitSmmS3ResumeState (\r | |
1021 | IN UINT32 Cr3\r | |
1022 | );\r | |
1023 | \r | |
1024 | /**\r | |
1025 | Get ACPI CPU data.\r | |
1026 | \r | |
1027 | **/\r | |
1028 | VOID\r | |
1029 | GetAcpiCpuData (\r | |
1030 | VOID\r | |
1031 | );\r | |
1032 | \r | |
1033 | /**\r | |
1034 | Restore SMM Configuration in S3 boot path.\r | |
1035 | \r | |
1036 | **/\r | |
1037 | VOID\r | |
1038 | RestoreSmmConfigurationInS3 (\r | |
1039 | VOID\r | |
1040 | );\r | |
1041 | \r | |
b10d5ddc SZ |
1042 | /**\r |
1043 | Get ACPI S3 enable flag.\r | |
1044 | \r | |
1045 | **/\r | |
1046 | VOID\r | |
1047 | GetAcpiS3EnableFlag (\r | |
1048 | VOID\r | |
1049 | );\r | |
1050 | \r | |
4a0f88dd JF |
1051 | /**\r |
1052 | Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r | |
1053 | \r | |
672b80c8 MK |
1054 | @param[in] ApHltLoopCode The address of the safe hlt-loop function.\r |
1055 | @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r | |
1056 | @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.\r | |
4a0f88dd JF |
1057 | \r |
1058 | **/\r | |
1059 | VOID\r | |
1060 | TransferApToSafeState (\r | |
672b80c8 MK |
1061 | IN UINTN ApHltLoopCode,\r |
1062 | IN UINTN TopOfStack,\r | |
1063 | IN UINTN NumberToFinishAddress\r | |
4a0f88dd JF |
1064 | );\r |
1065 | \r | |
529a5a86 | 1066 | #endif\r |