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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1353ebb4 | 33 | |
da285121 | 34 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 35 | static void __init ssb_select_mitigation(void); |
05516ad8 | 36 | static void __init l1tf_select_mitigation(void); |
da285121 | 37 | |
7011f443 JK |
38 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
39 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 40 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 41 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 42 | |
d0c3bedd KRW |
43 | /* |
44 | * The vendor and possibly platform specific bits which can be modified in | |
45 | * x86_spec_ctrl_base. | |
46 | */ | |
e5f984ed | 47 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 48 | |
c37b94dd KRW |
49 | /* |
50 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 51 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
52 | */ |
53 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 54 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 55 | |
6cd930f0 TG |
56 | /* Control conditional STIPB in switch_to() */ |
57 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); | |
58b2d4c8 TG |
58 | /* Control conditional IBPB in switch_mm() */ |
59 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
60 | /* Control unconditional IBPB in switch_mm() */ | |
61 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
6cd930f0 | 62 | |
1353ebb4 JF |
63 | void __init check_bugs(void) |
64 | { | |
65 | identify_boot_cpu(); | |
55a36b65 | 66 | |
483ec3c6 TG |
67 | /* |
68 | * identify_boot_cpu() initialized SMT support information, let the | |
69 | * core code know. | |
70 | */ | |
ade31b9e | 71 | cpu_smt_check_topology_early(); |
483ec3c6 | 72 | |
62a67e12 BP |
73 | if (!IS_ENABLED(CONFIG_SMP)) { |
74 | pr_info("CPU: "); | |
75 | print_cpu_info(&boot_cpu_data); | |
76 | } | |
77 | ||
296b454a KRW |
78 | /* |
79 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
80 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
81 | * init code as it is not enumerated and depends on the family. | |
296b454a | 82 | */ |
50f9b919 | 83 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
84 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
85 | ||
e5f984ed TG |
86 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
87 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
88 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
89 | ||
da285121 DW |
90 | /* Select the proper spectre mitigation before patching alternatives */ |
91 | spectre_v2_select_mitigation(); | |
92 | ||
e63490c8 KRW |
93 | /* |
94 | * Select proper mitigation for any exposure to the Speculative Store | |
95 | * Bypass vulnerability. | |
96 | */ | |
97 | ssb_select_mitigation(); | |
98 | ||
05516ad8 AK |
99 | l1tf_select_mitigation(); |
100 | ||
62a67e12 | 101 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
102 | /* |
103 | * Check whether we are able to run this kernel safely on SMP. | |
104 | * | |
105 | * - i386 is no longer supported. | |
106 | * - In order to run on anything without a TSC, we need to be | |
107 | * compiled for a i486. | |
108 | */ | |
109 | if (boot_cpu_data.x86 < 4) | |
110 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
111 | ||
bfe4bb15 MV |
112 | init_utsname()->machine[1] = |
113 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 114 | alternative_instructions(); |
304bceda | 115 | |
4d164092 | 116 | fpu__init_check_bugs(); |
62a67e12 BP |
117 | #else /* CONFIG_X86_64 */ |
118 | alternative_instructions(); | |
119 | ||
120 | /* | |
121 | * Make sure the first 2MB area is not mapped by huge pages | |
122 | * There are typically fixed size MTRRs in there and overlapping | |
123 | * MTRRs into large pages causes slow downs. | |
124 | * | |
125 | * Right now we don't do that with gbpages because there seems | |
126 | * very little benefit for that case. | |
127 | */ | |
128 | if (!direct_gbpages) | |
129 | set_memory_4k((unsigned long)__va(0), 1); | |
130 | #endif | |
1353ebb4 | 131 | } |
61dc0f55 | 132 | |
12376b62 BP |
133 | void |
134 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 135 | { |
e5f984ed | 136 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 137 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 138 | |
50f9b919 | 139 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 140 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
141 | /* |
142 | * Restrict guest_spec_ctrl to supported values. Clear the | |
143 | * modifiable bits in the host base value and or the | |
144 | * modifiable bits from the guest value. | |
145 | */ | |
146 | guestval = hostval & ~x86_spec_ctrl_mask; | |
147 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
148 | ||
12376b62 | 149 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
150 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
151 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 152 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 153 | |
e0b04783 TC |
154 | /* Conditional STIBP enabled? */ |
155 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
156 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
157 | ||
e5f984ed TG |
158 | if (hostval != guestval) { |
159 | msrval = setguest ? guestval : hostval; | |
160 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
161 | } |
162 | } | |
1238ed31 TG |
163 | |
164 | /* | |
165 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
166 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
167 | */ | |
168 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
169 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
170 | return; | |
171 | ||
172 | /* | |
173 | * If the host has SSBD mitigation enabled, force it in the host's | |
174 | * virtual MSR value. If its not permanently enabled, evaluate | |
175 | * current's TIF_SSBD thread flag. | |
176 | */ | |
177 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
178 | hostval = SPEC_CTRL_SSBD; | |
179 | else | |
180 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
181 | ||
182 | /* Sanitize the guest value */ | |
183 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
184 | ||
185 | if (hostval != guestval) { | |
186 | unsigned long tif; | |
187 | ||
188 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
189 | ssbd_spec_ctrl_to_tif(hostval); | |
190 | ||
8fce7184 | 191 | speculation_ctrl_update(tif); |
1238ed31 | 192 | } |
19fff03f | 193 | } |
12376b62 | 194 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 195 | |
8fe36c9d | 196 | static void x86_amd_ssb_disable(void) |
c37b94dd | 197 | { |
8fe36c9d | 198 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 199 | |
65e02bbd TL |
200 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
201 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
202 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
203 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
204 | } | |
205 | ||
aef0bebc TG |
206 | #undef pr_fmt |
207 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
208 | ||
209 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
210 | SPECTRE_V2_NONE; | |
211 | ||
6cd930f0 TG |
212 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
213 | SPECTRE_V2_USER_NONE; | |
214 | ||
d280282b | 215 | #ifdef RETPOLINE |
bb3c2578 TG |
216 | static bool spectre_v2_bad_module; |
217 | ||
d280282b AK |
218 | bool retpoline_module_ok(bool has_retpoline) |
219 | { | |
220 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
221 | return true; | |
222 | ||
c8b8e109 | 223 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
224 | spectre_v2_bad_module = true; |
225 | return false; | |
226 | } | |
bb3c2578 TG |
227 | |
228 | static inline const char *spectre_v2_module_string(void) | |
229 | { | |
230 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
231 | } | |
232 | #else | |
233 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 234 | #endif |
da285121 | 235 | |
da285121 DW |
236 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
237 | { | |
238 | int len = strlen(opt); | |
239 | ||
240 | return len == arglen && !strncmp(arg, opt, len); | |
241 | } | |
242 | ||
aef0bebc TG |
243 | /* The kernel command line selection for spectre v2 */ |
244 | enum spectre_v2_mitigation_cmd { | |
245 | SPECTRE_V2_CMD_NONE, | |
246 | SPECTRE_V2_CMD_AUTO, | |
247 | SPECTRE_V2_CMD_FORCE, | |
248 | SPECTRE_V2_CMD_RETPOLINE, | |
249 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
250 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
251 | }; | |
252 | ||
6cd930f0 TG |
253 | enum spectre_v2_user_cmd { |
254 | SPECTRE_V2_USER_CMD_NONE, | |
255 | SPECTRE_V2_USER_CMD_AUTO, | |
256 | SPECTRE_V2_USER_CMD_FORCE, | |
2cdf6a58 | 257 | SPECTRE_V2_USER_CMD_PRCTL, |
1c3cf627 | 258 | SPECTRE_V2_USER_CMD_SECCOMP, |
6cd930f0 TG |
259 | }; |
260 | ||
261 | static const char * const spectre_v2_user_strings[] = { | |
262 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", | |
263 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
2cdf6a58 | 264 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", |
1c3cf627 | 265 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", |
6cd930f0 TG |
266 | }; |
267 | ||
268 | static const struct { | |
269 | const char *option; | |
270 | enum spectre_v2_user_cmd cmd; | |
271 | bool secure; | |
272 | } v2_user_options[] __initdata = { | |
273 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, | |
274 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
275 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
2cdf6a58 | 276 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, |
1c3cf627 | 277 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, |
6cd930f0 TG |
278 | }; |
279 | ||
280 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
281 | { | |
282 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
283 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
284 | } | |
285 | ||
286 | static enum spectre_v2_user_cmd __init | |
287 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
288 | { | |
289 | char arg[20]; | |
290 | int ret, i; | |
291 | ||
292 | switch (v2_cmd) { | |
293 | case SPECTRE_V2_CMD_NONE: | |
294 | return SPECTRE_V2_USER_CMD_NONE; | |
295 | case SPECTRE_V2_CMD_FORCE: | |
296 | return SPECTRE_V2_USER_CMD_FORCE; | |
297 | default: | |
298 | break; | |
299 | } | |
300 | ||
301 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
302 | arg, sizeof(arg)); | |
303 | if (ret < 0) | |
304 | return SPECTRE_V2_USER_CMD_AUTO; | |
305 | ||
306 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
307 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
308 | spec_v2_user_print_cond(v2_user_options[i].option, | |
309 | v2_user_options[i].secure); | |
310 | return v2_user_options[i].cmd; | |
311 | } | |
312 | } | |
313 | ||
314 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
315 | return SPECTRE_V2_USER_CMD_AUTO; | |
316 | } | |
317 | ||
318 | static void __init | |
319 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
320 | { | |
321 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
322 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
323 | ||
324 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
325 | return; | |
326 | ||
327 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
328 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
329 | smt_possible = false; | |
330 | ||
331 | switch (spectre_v2_parse_user_cmdline(v2_cmd)) { | |
6cd930f0 TG |
332 | case SPECTRE_V2_USER_CMD_NONE: |
333 | goto set_mode; | |
334 | case SPECTRE_V2_USER_CMD_FORCE: | |
335 | mode = SPECTRE_V2_USER_STRICT; | |
336 | break; | |
2cdf6a58 TG |
337 | case SPECTRE_V2_USER_CMD_PRCTL: |
338 | mode = SPECTRE_V2_USER_PRCTL; | |
339 | break; | |
1c3cf627 TG |
340 | case SPECTRE_V2_USER_CMD_AUTO: |
341 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
342 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
343 | mode = SPECTRE_V2_USER_SECCOMP; | |
344 | else | |
345 | mode = SPECTRE_V2_USER_PRCTL; | |
346 | break; | |
6cd930f0 TG |
347 | } |
348 | ||
349 | /* Initialize Indirect Branch Prediction Barrier */ | |
350 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
351 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
58b2d4c8 TG |
352 | |
353 | switch (mode) { | |
354 | case SPECTRE_V2_USER_STRICT: | |
355 | static_branch_enable(&switch_mm_always_ibpb); | |
356 | break; | |
2cdf6a58 | 357 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 358 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 TG |
359 | static_branch_enable(&switch_mm_cond_ibpb); |
360 | break; | |
58b2d4c8 TG |
361 | default: |
362 | break; | |
363 | } | |
364 | ||
365 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
366 | mode == SPECTRE_V2_USER_STRICT ? "always-on" : "conditional"); | |
6cd930f0 TG |
367 | } |
368 | ||
369 | /* If enhanced IBRS is enabled no STIPB required */ | |
370 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
371 | return; | |
372 | ||
2cdf6a58 TG |
373 | /* |
374 | * If SMT is not possible or STIBP is not available clear the STIPB | |
375 | * mode. | |
376 | */ | |
377 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
378 | mode = SPECTRE_V2_USER_NONE; | |
6cd930f0 TG |
379 | set_mode: |
380 | spectre_v2_user = mode; | |
381 | /* Only print the STIBP mode when SMT possible */ | |
382 | if (smt_possible) | |
383 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
384 | } | |
385 | ||
0eb5928b | 386 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
387 | [SPECTRE_V2_NONE] = "Vulnerable", |
388 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
389 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
390 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
391 | }; | |
392 | ||
17c33e7c KA |
393 | static const struct { |
394 | const char *option; | |
395 | enum spectre_v2_mitigation_cmd cmd; | |
396 | bool secure; | |
5a76cb46 | 397 | } mitigation_options[] __initdata = { |
aef0bebc TG |
398 | { "off", SPECTRE_V2_CMD_NONE, false }, |
399 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
400 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
401 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
402 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
403 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
404 | }; |
405 | ||
10640103 | 406 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 407 | { |
10640103 | 408 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
409 | pr_info("%s selected on command line.\n", reason); |
410 | } | |
411 | ||
da285121 DW |
412 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
413 | { | |
aef0bebc | 414 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 415 | char arg[20]; |
17c33e7c | 416 | int ret, i; |
17c33e7c KA |
417 | |
418 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
419 | return SPECTRE_V2_CMD_NONE; | |
17c33e7c | 420 | |
4e8e955a TC |
421 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
422 | if (ret < 0) | |
423 | return SPECTRE_V2_CMD_AUTO; | |
424 | ||
425 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
426 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
427 | continue; | |
428 | cmd = mitigation_options[i].cmd; | |
429 | break; | |
430 | } | |
431 | ||
432 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
433 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
434 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
435 | } |
436 | ||
17c33e7c KA |
437 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
438 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
439 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
440 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 441 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 442 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
443 | } |
444 | ||
445 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
446 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
447 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
448 | return SPECTRE_V2_CMD_AUTO; | |
449 | } | |
450 | ||
10640103 TG |
451 | spec_v2_print_cond(mitigation_options[i].option, |
452 | mitigation_options[i].secure); | |
17c33e7c | 453 | return cmd; |
da285121 DW |
454 | } |
455 | ||
456 | static void __init spectre_v2_select_mitigation(void) | |
457 | { | |
458 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
459 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
460 | ||
461 | /* | |
462 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
463 | * then nothing to do. | |
464 | */ | |
465 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
466 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
467 | return; | |
468 | ||
469 | switch (cmd) { | |
470 | case SPECTRE_V2_CMD_NONE: | |
471 | return; | |
472 | ||
473 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 474 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
475 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
476 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
477 | /* Force it so VMEXIT will restore correctly */ | |
478 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
479 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
480 | goto specv2_set_mode; | |
481 | } | |
d0f293e0 DL |
482 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
483 | goto retpoline_auto; | |
484 | break; | |
da285121 DW |
485 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
486 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
487 | goto retpoline_amd; | |
488 | break; | |
489 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
490 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
491 | goto retpoline_generic; | |
492 | break; | |
493 | case SPECTRE_V2_CMD_RETPOLINE: | |
494 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
495 | goto retpoline_auto; | |
496 | break; | |
497 | } | |
713f1b95 | 498 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
499 | return; |
500 | ||
501 | retpoline_auto: | |
502 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
503 | retpoline_amd: | |
504 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 505 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
506 | goto retpoline_generic; |
507 | } | |
51dd01b5 | 508 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
509 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
510 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
511 | } else { | |
512 | retpoline_generic: | |
51dd01b5 | 513 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
514 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
515 | } | |
516 | ||
1044fde9 | 517 | specv2_set_mode: |
da285121 DW |
518 | spectre_v2_enabled = mode; |
519 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
520 | |
521 | /* | |
14623a43 JK |
522 | * If spectre v2 protection has been enabled, unconditionally fill |
523 | * RSB during a context switch; this protects against two independent | |
524 | * issues: | |
c995efd5 | 525 | * |
14623a43 JK |
526 | * - RSB underflow (and switch to BTB) on Skylake+ |
527 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 528 | */ |
14623a43 JK |
529 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
530 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 531 | |
390b99c3 DW |
532 | /* |
533 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
534 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
535 | * speculation around firmware calls only when Enhanced IBRS isn't | |
536 | * supported. | |
537 | * | |
538 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
539 | * the user might select retpoline on the kernel command line and if | |
540 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
541 | * enable IBRS around firmware calls. | |
390b99c3 | 542 | */ |
1044fde9 | 543 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
544 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
545 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
546 | } | |
7011f443 | 547 | |
6cd930f0 TG |
548 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
549 | spectre_v2_user_select_mitigation(cmd); | |
550 | ||
7011f443 JK |
551 | /* Enable STIBP if appropriate */ |
552 | arch_smt_update(); | |
da285121 DW |
553 | } |
554 | ||
984d266f | 555 | static void update_stibp_msr(void * __unused) |
aef0bebc | 556 | { |
984d266f | 557 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
aef0bebc TG |
558 | } |
559 | ||
984d266f TG |
560 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
561 | static void update_stibp_strict(void) | |
aef0bebc | 562 | { |
984d266f TG |
563 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
564 | ||
565 | if (sched_smt_active()) | |
566 | mask |= SPEC_CTRL_STIBP; | |
567 | ||
568 | if (mask == x86_spec_ctrl_base) | |
569 | return; | |
570 | ||
571 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
572 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
573 | x86_spec_ctrl_base = mask; | |
574 | on_each_cpu(update_stibp_msr, NULL, 1); | |
aef0bebc TG |
575 | } |
576 | ||
2cdf6a58 TG |
577 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
578 | static void update_indir_branch_cond(void) | |
579 | { | |
580 | if (sched_smt_active()) | |
581 | static_branch_enable(&switch_to_cond_stibp); | |
582 | else | |
583 | static_branch_disable(&switch_to_cond_stibp); | |
584 | } | |
585 | ||
aef0bebc TG |
586 | void arch_smt_update(void) |
587 | { | |
984d266f TG |
588 | /* Enhanced IBRS implies STIBP. No update required. */ |
589 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
aef0bebc TG |
590 | return; |
591 | ||
592 | mutex_lock(&spec_ctrl_mutex); | |
593 | ||
984d266f TG |
594 | switch (spectre_v2_user) { |
595 | case SPECTRE_V2_USER_NONE: | |
596 | break; | |
597 | case SPECTRE_V2_USER_STRICT: | |
598 | update_stibp_strict(); | |
599 | break; | |
ac40ad3b | 600 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 601 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 | 602 | update_indir_branch_cond(); |
ac40ad3b | 603 | break; |
aef0bebc | 604 | } |
984d266f | 605 | |
aef0bebc TG |
606 | mutex_unlock(&spec_ctrl_mutex); |
607 | } | |
608 | ||
e63490c8 KRW |
609 | #undef pr_fmt |
610 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
611 | ||
b5e6d77d | 612 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
613 | |
614 | /* The kernel command line selection */ | |
615 | enum ssb_mitigation_cmd { | |
616 | SPEC_STORE_BYPASS_CMD_NONE, | |
617 | SPEC_STORE_BYPASS_CMD_AUTO, | |
618 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 619 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 620 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
621 | }; |
622 | ||
0eb5928b | 623 | static const char * const ssb_strings[] = { |
e63490c8 | 624 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 625 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
626 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
627 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
628 | }; |
629 | ||
630 | static const struct { | |
631 | const char *option; | |
632 | enum ssb_mitigation_cmd cmd; | |
5a76cb46 | 633 | } ssb_mitigation_options[] __initdata = { |
c7416003 KC |
634 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
635 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
636 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
637 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
638 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
639 | }; |
640 | ||
641 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
642 | { | |
643 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
644 | char arg[20]; | |
645 | int ret, i; | |
646 | ||
647 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
648 | return SPEC_STORE_BYPASS_CMD_NONE; | |
649 | } else { | |
650 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
651 | arg, sizeof(arg)); | |
652 | if (ret < 0) | |
653 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
654 | ||
655 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
656 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
657 | continue; | |
658 | ||
659 | cmd = ssb_mitigation_options[i].cmd; | |
660 | break; | |
661 | } | |
662 | ||
663 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
664 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
665 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
666 | } | |
667 | } | |
668 | ||
669 | return cmd; | |
670 | } | |
671 | ||
dbe3009d | 672 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
673 | { |
674 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
675 | enum ssb_mitigation_cmd cmd; | |
676 | ||
8fe36c9d | 677 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
678 | return mode; |
679 | ||
680 | cmd = ssb_parse_cmdline(); | |
681 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
682 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
683 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
684 | return mode; | |
685 | ||
686 | switch (cmd) { | |
687 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
688 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
689 | /* | |
690 | * Choose prctl+seccomp as the default mode if seccomp is | |
691 | * enabled. | |
692 | */ | |
693 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
694 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
695 | else | |
696 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 697 | break; |
e63490c8 KRW |
698 | case SPEC_STORE_BYPASS_CMD_ON: |
699 | mode = SPEC_STORE_BYPASS_DISABLE; | |
700 | break; | |
574dcf89 TG |
701 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
702 | mode = SPEC_STORE_BYPASS_PRCTL; | |
703 | break; | |
e63490c8 KRW |
704 | case SPEC_STORE_BYPASS_CMD_NONE: |
705 | break; | |
706 | } | |
707 | ||
23b9eab9 KRW |
708 | /* |
709 | * We have three CPU feature flags that are in play here: | |
710 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 711 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
712 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
713 | */ | |
574dcf89 | 714 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 715 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 716 | /* |
3b881627 KRW |
717 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
718 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 719 | */ |
5005c716 TL |
720 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
721 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 722 | x86_amd_ssb_disable(); |
5005c716 | 723 | } else { |
8fe36c9d | 724 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 725 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 726 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
727 | } |
728 | } | |
729 | ||
e63490c8 KRW |
730 | return mode; |
731 | } | |
732 | ||
043d480e | 733 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
734 | { |
735 | ssb_mode = __ssb_select_mitigation(); | |
736 | ||
737 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
738 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
739 | } | |
740 | ||
da285121 | 741 | #undef pr_fmt |
c7416003 | 742 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 743 | |
801d6893 | 744 | static void task_update_spec_tif(struct task_struct *tsk) |
574dcf89 | 745 | { |
801d6893 TG |
746 | /* Force the update of the real TIF bits */ |
747 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
d4595948 TG |
748 | |
749 | /* | |
750 | * Immediately update the speculation control MSRs for the current | |
751 | * task, but for a non-current task delay setting the CPU | |
752 | * mitigation until it is scheduled next. | |
753 | * | |
754 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
755 | * always the current task. | |
756 | */ | |
801d6893 | 757 | if (tsk == current) |
d4595948 TG |
758 | speculation_ctrl_update_current(); |
759 | } | |
760 | ||
761 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
762 | { | |
c7416003 KC |
763 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
764 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
765 | return -ENXIO; |
766 | ||
733f4234 TG |
767 | switch (ctrl) { |
768 | case PR_SPEC_ENABLE: | |
769 | /* If speculation is force disabled, enable is not allowed */ | |
770 | if (task_spec_ssb_force_disable(task)) | |
771 | return -EPERM; | |
772 | task_clear_spec_ssb_disable(task); | |
801d6893 | 773 | task_update_spec_tif(task); |
733f4234 TG |
774 | break; |
775 | case PR_SPEC_DISABLE: | |
776 | task_set_spec_ssb_disable(task); | |
801d6893 | 777 | task_update_spec_tif(task); |
733f4234 TG |
778 | break; |
779 | case PR_SPEC_FORCE_DISABLE: | |
780 | task_set_spec_ssb_disable(task); | |
781 | task_set_spec_ssb_force_disable(task); | |
801d6893 | 782 | task_update_spec_tif(task); |
733f4234 TG |
783 | break; |
784 | default: | |
785 | return -ERANGE; | |
786 | } | |
574dcf89 TG |
787 | return 0; |
788 | } | |
789 | ||
ac40ad3b TG |
790 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
791 | { | |
792 | switch (ctrl) { | |
793 | case PR_SPEC_ENABLE: | |
794 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
795 | return 0; | |
796 | /* | |
797 | * Indirect branch speculation is always disabled in strict | |
798 | * mode. | |
799 | */ | |
800 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT) | |
801 | return -EPERM; | |
802 | task_clear_spec_ib_disable(task); | |
803 | task_update_spec_tif(task); | |
804 | break; | |
805 | case PR_SPEC_DISABLE: | |
806 | case PR_SPEC_FORCE_DISABLE: | |
807 | /* | |
808 | * Indirect branch speculation is always allowed when | |
809 | * mitigation is force disabled. | |
810 | */ | |
811 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
812 | return -EPERM; | |
813 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT) | |
814 | return 0; | |
815 | task_set_spec_ib_disable(task); | |
816 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
817 | task_set_spec_ib_force_disable(task); | |
818 | task_update_spec_tif(task); | |
819 | break; | |
820 | default: | |
821 | return -ERANGE; | |
822 | } | |
823 | return 0; | |
824 | } | |
825 | ||
5b38e244 TG |
826 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
827 | unsigned long ctrl) | |
828 | { | |
829 | switch (which) { | |
830 | case PR_SPEC_STORE_BYPASS: | |
831 | return ssb_prctl_set(task, ctrl); | |
ac40ad3b TG |
832 | case PR_SPEC_INDIRECT_BRANCH: |
833 | return ib_prctl_set(task, ctrl); | |
5b38e244 TG |
834 | default: |
835 | return -ENODEV; | |
836 | } | |
837 | } | |
838 | ||
839 | #ifdef CONFIG_SECCOMP | |
840 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
841 | { | |
c7416003 KC |
842 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
843 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
1c3cf627 TG |
844 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
845 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
846 | } |
847 | #endif | |
848 | ||
199bfed2 | 849 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
850 | { |
851 | switch (ssb_mode) { | |
852 | case SPEC_STORE_BYPASS_DISABLE: | |
853 | return PR_SPEC_DISABLE; | |
c7416003 | 854 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 855 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
856 | if (task_spec_ssb_force_disable(task)) |
857 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
858 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
859 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
860 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
861 | default: | |
862 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
863 | return PR_SPEC_ENABLE; | |
864 | return PR_SPEC_NOT_AFFECTED; | |
865 | } | |
866 | } | |
867 | ||
ac40ad3b TG |
868 | static int ib_prctl_get(struct task_struct *task) |
869 | { | |
870 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
871 | return PR_SPEC_NOT_AFFECTED; | |
872 | ||
873 | switch (spectre_v2_user) { | |
874 | case SPECTRE_V2_USER_NONE: | |
875 | return PR_SPEC_ENABLE; | |
876 | case SPECTRE_V2_USER_PRCTL: | |
1c3cf627 | 877 | case SPECTRE_V2_USER_SECCOMP: |
ac40ad3b TG |
878 | if (task_spec_ib_force_disable(task)) |
879 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
880 | if (task_spec_ib_disable(task)) | |
881 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
882 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
883 | case SPECTRE_V2_USER_STRICT: | |
884 | return PR_SPEC_DISABLE; | |
885 | default: | |
886 | return PR_SPEC_NOT_AFFECTED; | |
887 | } | |
888 | } | |
889 | ||
199bfed2 | 890 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
891 | { |
892 | switch (which) { | |
893 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 894 | return ssb_prctl_get(task); |
ac40ad3b TG |
895 | case PR_SPEC_INDIRECT_BRANCH: |
896 | return ib_prctl_get(task); | |
574dcf89 TG |
897 | default: |
898 | return -ENODEV; | |
899 | } | |
900 | } | |
901 | ||
23b9eab9 KRW |
902 | void x86_spec_ctrl_setup_ap(void) |
903 | { | |
50f9b919 | 904 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 905 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
906 | |
907 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 908 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
909 | } |
910 | ||
73ca9f47 KRW |
911 | #undef pr_fmt |
912 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 913 | |
24fcb53c JK |
914 | /* Default mitigation for L1TF-affected CPUs */ |
915 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 916 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
917 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
918 | ||
522c7bed | 919 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
920 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
921 | #endif | |
922 | ||
f1f016ed AK |
923 | /* |
924 | * These CPUs all support 44bits physical address space internally in the | |
925 | * cache but CPUID can report a smaller number of physical address bits. | |
926 | * | |
927 | * The L1TF mitigation uses the top most address bit for the inversion of | |
928 | * non present PTEs. When the installed memory reaches into the top most | |
929 | * address bit due to memory holes, which has been observed on machines | |
930 | * which report 36bits physical address bits and have 32G RAM installed, | |
931 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
932 | * This is a false positive because the mitigation is still possible due to | |
933 | * the fact that the cache uses 44bit internally. Use the cache bits | |
934 | * instead of the reported physical bits and adjust them on the affected | |
935 | * machines to 44bit if the reported bits are less than 44. | |
936 | */ | |
937 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
938 | { | |
939 | if (c->x86 != 6) | |
940 | return; | |
941 | ||
942 | switch (c->x86_model) { | |
943 | case INTEL_FAM6_NEHALEM: | |
944 | case INTEL_FAM6_WESTMERE: | |
945 | case INTEL_FAM6_SANDYBRIDGE: | |
946 | case INTEL_FAM6_IVYBRIDGE: | |
947 | case INTEL_FAM6_HASWELL_CORE: | |
948 | case INTEL_FAM6_HASWELL_ULT: | |
949 | case INTEL_FAM6_HASWELL_GT3E: | |
950 | case INTEL_FAM6_BROADWELL_CORE: | |
951 | case INTEL_FAM6_BROADWELL_GT3E: | |
952 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
953 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
954 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
955 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
956 | if (c->x86_cache_bits < 44) | |
957 | c->x86_cache_bits = 44; | |
958 | break; | |
959 | } | |
960 | } | |
961 | ||
73ca9f47 KRW |
962 | static void __init l1tf_select_mitigation(void) |
963 | { | |
964 | u64 half_pa; | |
965 | ||
966 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
967 | return; | |
968 | ||
f1f016ed AK |
969 | override_cache_bits(&boot_cpu_data); |
970 | ||
24fcb53c JK |
971 | switch (l1tf_mitigation) { |
972 | case L1TF_MITIGATION_OFF: | |
973 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
974 | case L1TF_MITIGATION_FLUSH: | |
975 | break; | |
976 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
977 | case L1TF_MITIGATION_FULL: | |
978 | cpu_smt_disable(false); | |
979 | break; | |
980 | case L1TF_MITIGATION_FULL_FORCE: | |
981 | cpu_smt_disable(true); | |
982 | break; | |
983 | } | |
984 | ||
73ca9f47 KRW |
985 | #if CONFIG_PGTABLE_LEVELS == 2 |
986 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
987 | return; | |
988 | #endif | |
989 | ||
73ca9f47 KRW |
990 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
991 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
992 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
993 | return; | |
994 | } | |
995 | ||
996 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
997 | } | |
24fcb53c JK |
998 | |
999 | static int __init l1tf_cmdline(char *str) | |
1000 | { | |
1001 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1002 | return 0; | |
1003 | ||
1004 | if (!str) | |
1005 | return -EINVAL; | |
1006 | ||
1007 | if (!strcmp(str, "off")) | |
1008 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1009 | else if (!strcmp(str, "flush,nowarn")) | |
1010 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1011 | else if (!strcmp(str, "flush")) | |
1012 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1013 | else if (!strcmp(str, "flush,nosmt")) | |
1014 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1015 | else if (!strcmp(str, "full")) | |
1016 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1017 | else if (!strcmp(str, "full,force")) | |
1018 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | early_param("l1tf", l1tf_cmdline); | |
1023 | ||
73ca9f47 KRW |
1024 | #undef pr_fmt |
1025 | ||
61dc0f55 | 1026 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 1027 | |
b9cfedcd TG |
1028 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1029 | ||
1030 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 1031 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
1032 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1033 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1034 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1035 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1036 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 1037 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
1038 | }; |
1039 | ||
1040 | static ssize_t l1tf_show_state(char *buf) | |
1041 | { | |
1042 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1043 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1044 | ||
3899f7b1 PB |
1045 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1046 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 1047 | sched_smt_active())) { |
3899f7b1 PB |
1048 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1049 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 1050 | } |
3899f7b1 PB |
1051 | |
1052 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1053 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 1054 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
1055 | } |
1056 | #else | |
1057 | static ssize_t l1tf_show_state(char *buf) | |
1058 | { | |
1059 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1060 | } | |
1061 | #endif | |
1062 | ||
2daa53e8 TC |
1063 | static char *stibp_state(void) |
1064 | { | |
4a8d91c8 TC |
1065 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1066 | return ""; | |
1067 | ||
6cd930f0 TG |
1068 | switch (spectre_v2_user) { |
1069 | case SPECTRE_V2_USER_NONE: | |
1070 | return ", STIBP: disabled"; | |
1071 | case SPECTRE_V2_USER_STRICT: | |
1072 | return ", STIBP: forced"; | |
ac40ad3b | 1073 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 1074 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 TG |
1075 | if (static_key_enabled(&switch_to_cond_stibp)) |
1076 | return ", STIBP: conditional"; | |
6cd930f0 TG |
1077 | } |
1078 | return ""; | |
2daa53e8 TC |
1079 | } |
1080 | ||
1081 | static char *ibpb_state(void) | |
1082 | { | |
58b2d4c8 | 1083 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
2cdf6a58 | 1084 | if (static_key_enabled(&switch_mm_always_ibpb)) |
58b2d4c8 | 1085 | return ", IBPB: always-on"; |
2cdf6a58 TG |
1086 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1087 | return ", IBPB: conditional"; | |
1088 | return ", IBPB: disabled"; | |
58b2d4c8 TG |
1089 | } |
1090 | return ""; | |
2daa53e8 TC |
1091 | } |
1092 | ||
ace051d5 | 1093 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 1094 | char *buf, unsigned int bug) |
61dc0f55 | 1095 | { |
d2b8fc2d | 1096 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1097 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
1098 | |
1099 | switch (bug) { | |
1100 | case X86_BUG_CPU_MELTDOWN: | |
1101 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1102 | return sprintf(buf, "Mitigation: PTI\n"); | |
1103 | ||
1104 | break; | |
1105 | ||
1106 | case X86_BUG_SPECTRE_V1: | |
1107 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
1108 | ||
1109 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 1110 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 1111 | ibpb_state(), |
d2b8fc2d | 1112 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 1113 | stibp_state(), |
5e2fafd5 | 1114 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
1115 | spectre_v2_module_string()); |
1116 | ||
e63490c8 KRW |
1117 | case X86_BUG_SPEC_STORE_BYPASS: |
1118 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1119 | ||
05516ad8 AK |
1120 | case X86_BUG_L1TF: |
1121 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 1122 | return l1tf_show_state(buf); |
05516ad8 | 1123 | break; |
d2b8fc2d KRW |
1124 | default: |
1125 | break; | |
1126 | } | |
1127 | ||
61dc0f55 TG |
1128 | return sprintf(buf, "Vulnerable\n"); |
1129 | } | |
1130 | ||
d2b8fc2d KRW |
1131 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1132 | { | |
1133 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1134 | } | |
1135 | ||
713f1b95 | 1136 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1137 | { |
d2b8fc2d | 1138 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1139 | } |
1140 | ||
713f1b95 | 1141 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1142 | { |
d2b8fc2d | 1143 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1144 | } |
d7de9182 KRW |
1145 | |
1146 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1147 | { | |
1148 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1149 | } | |
05516ad8 AK |
1150 | |
1151 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1152 | { | |
1153 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1154 | } | |
61dc0f55 | 1155 | #endif |