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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1353ebb4 | 33 | |
da285121 | 34 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 35 | static void __init ssb_select_mitigation(void); |
05516ad8 | 36 | static void __init l1tf_select_mitigation(void); |
da285121 | 37 | |
7011f443 JK |
38 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
39 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 40 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 41 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 42 | |
d0c3bedd KRW |
43 | /* |
44 | * The vendor and possibly platform specific bits which can be modified in | |
45 | * x86_spec_ctrl_base. | |
46 | */ | |
e5f984ed | 47 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 48 | |
c37b94dd KRW |
49 | /* |
50 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 51 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
52 | */ |
53 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 54 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 55 | |
8edb388f | 56 | /* Control conditional STIBP in switch_to() */ |
6cd930f0 | 57 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
58b2d4c8 TG |
58 | /* Control conditional IBPB in switch_mm() */ |
59 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
60 | /* Control unconditional IBPB in switch_mm() */ | |
61 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
6cd930f0 | 62 | |
1353ebb4 JF |
63 | void __init check_bugs(void) |
64 | { | |
65 | identify_boot_cpu(); | |
55a36b65 | 66 | |
483ec3c6 TG |
67 | /* |
68 | * identify_boot_cpu() initialized SMT support information, let the | |
69 | * core code know. | |
70 | */ | |
ade31b9e | 71 | cpu_smt_check_topology_early(); |
483ec3c6 | 72 | |
62a67e12 BP |
73 | if (!IS_ENABLED(CONFIG_SMP)) { |
74 | pr_info("CPU: "); | |
75 | print_cpu_info(&boot_cpu_data); | |
76 | } | |
77 | ||
296b454a KRW |
78 | /* |
79 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
80 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
81 | * init code as it is not enumerated and depends on the family. | |
296b454a | 82 | */ |
50f9b919 | 83 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
84 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
85 | ||
e5f984ed TG |
86 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
87 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
88 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
89 | ||
da285121 DW |
90 | /* Select the proper spectre mitigation before patching alternatives */ |
91 | spectre_v2_select_mitigation(); | |
92 | ||
e63490c8 KRW |
93 | /* |
94 | * Select proper mitigation for any exposure to the Speculative Store | |
95 | * Bypass vulnerability. | |
96 | */ | |
97 | ssb_select_mitigation(); | |
98 | ||
05516ad8 AK |
99 | l1tf_select_mitigation(); |
100 | ||
62a67e12 | 101 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
102 | /* |
103 | * Check whether we are able to run this kernel safely on SMP. | |
104 | * | |
105 | * - i386 is no longer supported. | |
106 | * - In order to run on anything without a TSC, we need to be | |
107 | * compiled for a i486. | |
108 | */ | |
109 | if (boot_cpu_data.x86 < 4) | |
110 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
111 | ||
bfe4bb15 MV |
112 | init_utsname()->machine[1] = |
113 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 114 | alternative_instructions(); |
304bceda | 115 | |
4d164092 | 116 | fpu__init_check_bugs(); |
62a67e12 BP |
117 | #else /* CONFIG_X86_64 */ |
118 | alternative_instructions(); | |
119 | ||
120 | /* | |
121 | * Make sure the first 2MB area is not mapped by huge pages | |
122 | * There are typically fixed size MTRRs in there and overlapping | |
123 | * MTRRs into large pages causes slow downs. | |
124 | * | |
125 | * Right now we don't do that with gbpages because there seems | |
126 | * very little benefit for that case. | |
127 | */ | |
128 | if (!direct_gbpages) | |
129 | set_memory_4k((unsigned long)__va(0), 1); | |
130 | #endif | |
1353ebb4 | 131 | } |
61dc0f55 | 132 | |
12376b62 BP |
133 | void |
134 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 135 | { |
e5f984ed | 136 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 137 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 138 | |
50f9b919 | 139 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 140 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
141 | /* |
142 | * Restrict guest_spec_ctrl to supported values. Clear the | |
143 | * modifiable bits in the host base value and or the | |
144 | * modifiable bits from the guest value. | |
145 | */ | |
146 | guestval = hostval & ~x86_spec_ctrl_mask; | |
147 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
148 | ||
12376b62 | 149 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
150 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
151 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 152 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 153 | |
e0b04783 TC |
154 | /* Conditional STIBP enabled? */ |
155 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
156 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
157 | ||
e5f984ed TG |
158 | if (hostval != guestval) { |
159 | msrval = setguest ? guestval : hostval; | |
160 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
161 | } |
162 | } | |
1238ed31 TG |
163 | |
164 | /* | |
165 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
166 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
167 | */ | |
168 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
169 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
170 | return; | |
171 | ||
172 | /* | |
173 | * If the host has SSBD mitigation enabled, force it in the host's | |
174 | * virtual MSR value. If its not permanently enabled, evaluate | |
175 | * current's TIF_SSBD thread flag. | |
176 | */ | |
177 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
178 | hostval = SPEC_CTRL_SSBD; | |
179 | else | |
180 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
181 | ||
182 | /* Sanitize the guest value */ | |
183 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
184 | ||
185 | if (hostval != guestval) { | |
186 | unsigned long tif; | |
187 | ||
188 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
189 | ssbd_spec_ctrl_to_tif(hostval); | |
190 | ||
8fce7184 | 191 | speculation_ctrl_update(tif); |
1238ed31 | 192 | } |
19fff03f | 193 | } |
12376b62 | 194 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 195 | |
8fe36c9d | 196 | static void x86_amd_ssb_disable(void) |
c37b94dd | 197 | { |
8fe36c9d | 198 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 199 | |
65e02bbd TL |
200 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
201 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
202 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
203 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
204 | } | |
205 | ||
aef0bebc TG |
206 | #undef pr_fmt |
207 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
208 | ||
209 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
210 | SPECTRE_V2_NONE; | |
211 | ||
6cd930f0 TG |
212 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
213 | SPECTRE_V2_USER_NONE; | |
214 | ||
e9a556ad | 215 | #ifdef CONFIG_RETPOLINE |
bb3c2578 TG |
216 | static bool spectre_v2_bad_module; |
217 | ||
d280282b AK |
218 | bool retpoline_module_ok(bool has_retpoline) |
219 | { | |
220 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
221 | return true; | |
222 | ||
c8b8e109 | 223 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
224 | spectre_v2_bad_module = true; |
225 | return false; | |
226 | } | |
bb3c2578 TG |
227 | |
228 | static inline const char *spectre_v2_module_string(void) | |
229 | { | |
230 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
231 | } | |
232 | #else | |
233 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 234 | #endif |
da285121 | 235 | |
da285121 DW |
236 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
237 | { | |
238 | int len = strlen(opt); | |
239 | ||
240 | return len == arglen && !strncmp(arg, opt, len); | |
241 | } | |
242 | ||
aef0bebc TG |
243 | /* The kernel command line selection for spectre v2 */ |
244 | enum spectre_v2_mitigation_cmd { | |
245 | SPECTRE_V2_CMD_NONE, | |
246 | SPECTRE_V2_CMD_AUTO, | |
247 | SPECTRE_V2_CMD_FORCE, | |
248 | SPECTRE_V2_CMD_RETPOLINE, | |
249 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
250 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
251 | }; | |
252 | ||
6cd930f0 TG |
253 | enum spectre_v2_user_cmd { |
254 | SPECTRE_V2_USER_CMD_NONE, | |
255 | SPECTRE_V2_USER_CMD_AUTO, | |
256 | SPECTRE_V2_USER_CMD_FORCE, | |
2cdf6a58 | 257 | SPECTRE_V2_USER_CMD_PRCTL, |
fd1b7023 | 258 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
1c3cf627 | 259 | SPECTRE_V2_USER_CMD_SECCOMP, |
fd1b7023 | 260 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
6cd930f0 TG |
261 | }; |
262 | ||
263 | static const char * const spectre_v2_user_strings[] = { | |
fbed8eca TL |
264 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", |
265 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
266 | [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", | |
267 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", | |
268 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", | |
6cd930f0 TG |
269 | }; |
270 | ||
271 | static const struct { | |
272 | const char *option; | |
273 | enum spectre_v2_user_cmd cmd; | |
274 | bool secure; | |
275 | } v2_user_options[] __initdata = { | |
fd1b7023 TG |
276 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
277 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
278 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
279 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
280 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
281 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
282 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
6cd930f0 TG |
283 | }; |
284 | ||
285 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
286 | { | |
287 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
288 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
289 | } | |
290 | ||
291 | static enum spectre_v2_user_cmd __init | |
292 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
293 | { | |
294 | char arg[20]; | |
295 | int ret, i; | |
296 | ||
297 | switch (v2_cmd) { | |
298 | case SPECTRE_V2_CMD_NONE: | |
299 | return SPECTRE_V2_USER_CMD_NONE; | |
300 | case SPECTRE_V2_CMD_FORCE: | |
301 | return SPECTRE_V2_USER_CMD_FORCE; | |
302 | default: | |
303 | break; | |
304 | } | |
305 | ||
306 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
307 | arg, sizeof(arg)); | |
308 | if (ret < 0) | |
309 | return SPECTRE_V2_USER_CMD_AUTO; | |
310 | ||
311 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
312 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
313 | spec_v2_user_print_cond(v2_user_options[i].option, | |
314 | v2_user_options[i].secure); | |
315 | return v2_user_options[i].cmd; | |
316 | } | |
317 | } | |
318 | ||
319 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
320 | return SPECTRE_V2_USER_CMD_AUTO; | |
321 | } | |
322 | ||
323 | static void __init | |
324 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
325 | { | |
326 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
327 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
fd1b7023 | 328 | enum spectre_v2_user_cmd cmd; |
6cd930f0 TG |
329 | |
330 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
331 | return; | |
332 | ||
333 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
334 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
335 | smt_possible = false; | |
336 | ||
fd1b7023 TG |
337 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
338 | switch (cmd) { | |
6cd930f0 TG |
339 | case SPECTRE_V2_USER_CMD_NONE: |
340 | goto set_mode; | |
341 | case SPECTRE_V2_USER_CMD_FORCE: | |
342 | mode = SPECTRE_V2_USER_STRICT; | |
343 | break; | |
2cdf6a58 | 344 | case SPECTRE_V2_USER_CMD_PRCTL: |
fd1b7023 | 345 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
2cdf6a58 TG |
346 | mode = SPECTRE_V2_USER_PRCTL; |
347 | break; | |
1c3cf627 TG |
348 | case SPECTRE_V2_USER_CMD_AUTO: |
349 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
fd1b7023 | 350 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
1c3cf627 TG |
351 | if (IS_ENABLED(CONFIG_SECCOMP)) |
352 | mode = SPECTRE_V2_USER_SECCOMP; | |
353 | else | |
354 | mode = SPECTRE_V2_USER_PRCTL; | |
355 | break; | |
6cd930f0 TG |
356 | } |
357 | ||
fbed8eca TL |
358 | /* |
359 | * At this point, an STIBP mode other than "off" has been set. | |
360 | * If STIBP support is not being forced, check if STIBP always-on | |
361 | * is preferred. | |
362 | */ | |
363 | if (mode != SPECTRE_V2_USER_STRICT && | |
364 | boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) | |
365 | mode = SPECTRE_V2_USER_STRICT_PREFERRED; | |
366 | ||
6cd930f0 TG |
367 | /* Initialize Indirect Branch Prediction Barrier */ |
368 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
369 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
58b2d4c8 | 370 | |
fd1b7023 TG |
371 | switch (cmd) { |
372 | case SPECTRE_V2_USER_CMD_FORCE: | |
373 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
374 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
58b2d4c8 TG |
375 | static_branch_enable(&switch_mm_always_ibpb); |
376 | break; | |
fd1b7023 TG |
377 | case SPECTRE_V2_USER_CMD_PRCTL: |
378 | case SPECTRE_V2_USER_CMD_AUTO: | |
379 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
2cdf6a58 TG |
380 | static_branch_enable(&switch_mm_cond_ibpb); |
381 | break; | |
58b2d4c8 TG |
382 | default: |
383 | break; | |
384 | } | |
385 | ||
386 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
fd1b7023 TG |
387 | static_key_enabled(&switch_mm_always_ibpb) ? |
388 | "always-on" : "conditional"); | |
6cd930f0 TG |
389 | } |
390 | ||
8edb388f | 391 | /* If enhanced IBRS is enabled no STIBP required */ |
6cd930f0 TG |
392 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
393 | return; | |
394 | ||
2cdf6a58 | 395 | /* |
8edb388f | 396 | * If SMT is not possible or STIBP is not available clear the STIBP |
2cdf6a58 TG |
397 | * mode. |
398 | */ | |
399 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
400 | mode = SPECTRE_V2_USER_NONE; | |
6cd930f0 TG |
401 | set_mode: |
402 | spectre_v2_user = mode; | |
403 | /* Only print the STIBP mode when SMT possible */ | |
404 | if (smt_possible) | |
405 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
406 | } | |
407 | ||
0eb5928b | 408 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
409 | [SPECTRE_V2_NONE] = "Vulnerable", |
410 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
411 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
412 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
413 | }; | |
414 | ||
17c33e7c KA |
415 | static const struct { |
416 | const char *option; | |
417 | enum spectre_v2_mitigation_cmd cmd; | |
418 | bool secure; | |
5a76cb46 | 419 | } mitigation_options[] __initdata = { |
aef0bebc TG |
420 | { "off", SPECTRE_V2_CMD_NONE, false }, |
421 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
422 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
423 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
424 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
425 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
426 | }; |
427 | ||
10640103 | 428 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 429 | { |
10640103 | 430 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
431 | pr_info("%s selected on command line.\n", reason); |
432 | } | |
433 | ||
da285121 DW |
434 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
435 | { | |
aef0bebc | 436 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 437 | char arg[20]; |
17c33e7c | 438 | int ret, i; |
17c33e7c KA |
439 | |
440 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
441 | return SPECTRE_V2_CMD_NONE; | |
17c33e7c | 442 | |
4e8e955a TC |
443 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
444 | if (ret < 0) | |
445 | return SPECTRE_V2_CMD_AUTO; | |
446 | ||
447 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
448 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
449 | continue; | |
450 | cmd = mitigation_options[i].cmd; | |
451 | break; | |
452 | } | |
453 | ||
454 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
455 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
456 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
457 | } |
458 | ||
17c33e7c KA |
459 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
460 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
461 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
462 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 463 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 464 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
465 | } |
466 | ||
467 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
468 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
469 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
470 | return SPECTRE_V2_CMD_AUTO; | |
471 | } | |
472 | ||
10640103 TG |
473 | spec_v2_print_cond(mitigation_options[i].option, |
474 | mitigation_options[i].secure); | |
17c33e7c | 475 | return cmd; |
da285121 DW |
476 | } |
477 | ||
478 | static void __init spectre_v2_select_mitigation(void) | |
479 | { | |
480 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
481 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
482 | ||
483 | /* | |
484 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
485 | * then nothing to do. | |
486 | */ | |
487 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
488 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
489 | return; | |
490 | ||
491 | switch (cmd) { | |
492 | case SPECTRE_V2_CMD_NONE: | |
493 | return; | |
494 | ||
495 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 496 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
497 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
498 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
499 | /* Force it so VMEXIT will restore correctly */ | |
500 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
501 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
502 | goto specv2_set_mode; | |
503 | } | |
d0f293e0 DL |
504 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
505 | goto retpoline_auto; | |
506 | break; | |
da285121 DW |
507 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
508 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
509 | goto retpoline_amd; | |
510 | break; | |
511 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
512 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
513 | goto retpoline_generic; | |
514 | break; | |
515 | case SPECTRE_V2_CMD_RETPOLINE: | |
516 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
517 | goto retpoline_auto; | |
518 | break; | |
519 | } | |
713f1b95 | 520 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
521 | return; |
522 | ||
523 | retpoline_auto: | |
524 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
525 | retpoline_amd: | |
526 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 527 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
528 | goto retpoline_generic; |
529 | } | |
51dd01b5 | 530 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
531 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
532 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
533 | } else { | |
534 | retpoline_generic: | |
51dd01b5 | 535 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
536 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
537 | } | |
538 | ||
1044fde9 | 539 | specv2_set_mode: |
da285121 DW |
540 | spectre_v2_enabled = mode; |
541 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
542 | |
543 | /* | |
14623a43 JK |
544 | * If spectre v2 protection has been enabled, unconditionally fill |
545 | * RSB during a context switch; this protects against two independent | |
546 | * issues: | |
c995efd5 | 547 | * |
14623a43 JK |
548 | * - RSB underflow (and switch to BTB) on Skylake+ |
549 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 550 | */ |
14623a43 JK |
551 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
552 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 553 | |
390b99c3 DW |
554 | /* |
555 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
556 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
557 | * speculation around firmware calls only when Enhanced IBRS isn't | |
558 | * supported. | |
559 | * | |
560 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
561 | * the user might select retpoline on the kernel command line and if | |
562 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
563 | * enable IBRS around firmware calls. | |
390b99c3 | 564 | */ |
1044fde9 | 565 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
566 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
567 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
568 | } | |
7011f443 | 569 | |
6cd930f0 TG |
570 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
571 | spectre_v2_user_select_mitigation(cmd); | |
572 | ||
7011f443 JK |
573 | /* Enable STIBP if appropriate */ |
574 | arch_smt_update(); | |
da285121 DW |
575 | } |
576 | ||
984d266f | 577 | static void update_stibp_msr(void * __unused) |
aef0bebc | 578 | { |
984d266f | 579 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
aef0bebc TG |
580 | } |
581 | ||
984d266f TG |
582 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
583 | static void update_stibp_strict(void) | |
aef0bebc | 584 | { |
984d266f TG |
585 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
586 | ||
587 | if (sched_smt_active()) | |
588 | mask |= SPEC_CTRL_STIBP; | |
589 | ||
590 | if (mask == x86_spec_ctrl_base) | |
591 | return; | |
592 | ||
593 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
594 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
595 | x86_spec_ctrl_base = mask; | |
596 | on_each_cpu(update_stibp_msr, NULL, 1); | |
aef0bebc TG |
597 | } |
598 | ||
2cdf6a58 TG |
599 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
600 | static void update_indir_branch_cond(void) | |
601 | { | |
602 | if (sched_smt_active()) | |
603 | static_branch_enable(&switch_to_cond_stibp); | |
604 | else | |
605 | static_branch_disable(&switch_to_cond_stibp); | |
606 | } | |
607 | ||
aef0bebc TG |
608 | void arch_smt_update(void) |
609 | { | |
984d266f TG |
610 | /* Enhanced IBRS implies STIBP. No update required. */ |
611 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
aef0bebc TG |
612 | return; |
613 | ||
614 | mutex_lock(&spec_ctrl_mutex); | |
615 | ||
984d266f TG |
616 | switch (spectre_v2_user) { |
617 | case SPECTRE_V2_USER_NONE: | |
618 | break; | |
619 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 620 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
984d266f TG |
621 | update_stibp_strict(); |
622 | break; | |
ac40ad3b | 623 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 624 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 | 625 | update_indir_branch_cond(); |
ac40ad3b | 626 | break; |
aef0bebc | 627 | } |
984d266f | 628 | |
aef0bebc TG |
629 | mutex_unlock(&spec_ctrl_mutex); |
630 | } | |
631 | ||
e63490c8 KRW |
632 | #undef pr_fmt |
633 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
634 | ||
b5e6d77d | 635 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
636 | |
637 | /* The kernel command line selection */ | |
638 | enum ssb_mitigation_cmd { | |
639 | SPEC_STORE_BYPASS_CMD_NONE, | |
640 | SPEC_STORE_BYPASS_CMD_AUTO, | |
641 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 642 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 643 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
644 | }; |
645 | ||
0eb5928b | 646 | static const char * const ssb_strings[] = { |
e63490c8 | 647 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 648 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
649 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
650 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
651 | }; |
652 | ||
653 | static const struct { | |
654 | const char *option; | |
655 | enum ssb_mitigation_cmd cmd; | |
5a76cb46 | 656 | } ssb_mitigation_options[] __initdata = { |
c7416003 KC |
657 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
658 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
659 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
660 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
661 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
662 | }; |
663 | ||
664 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
665 | { | |
666 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
667 | char arg[20]; | |
668 | int ret, i; | |
669 | ||
670 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
671 | return SPEC_STORE_BYPASS_CMD_NONE; | |
672 | } else { | |
673 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
674 | arg, sizeof(arg)); | |
675 | if (ret < 0) | |
676 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
677 | ||
678 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
679 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
680 | continue; | |
681 | ||
682 | cmd = ssb_mitigation_options[i].cmd; | |
683 | break; | |
684 | } | |
685 | ||
686 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
687 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
688 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
689 | } | |
690 | } | |
691 | ||
692 | return cmd; | |
693 | } | |
694 | ||
dbe3009d | 695 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
696 | { |
697 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
698 | enum ssb_mitigation_cmd cmd; | |
699 | ||
8fe36c9d | 700 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
701 | return mode; |
702 | ||
703 | cmd = ssb_parse_cmdline(); | |
704 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
705 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
706 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
707 | return mode; | |
708 | ||
709 | switch (cmd) { | |
710 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
711 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
712 | /* | |
713 | * Choose prctl+seccomp as the default mode if seccomp is | |
714 | * enabled. | |
715 | */ | |
716 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
717 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
718 | else | |
719 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 720 | break; |
e63490c8 KRW |
721 | case SPEC_STORE_BYPASS_CMD_ON: |
722 | mode = SPEC_STORE_BYPASS_DISABLE; | |
723 | break; | |
574dcf89 TG |
724 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
725 | mode = SPEC_STORE_BYPASS_PRCTL; | |
726 | break; | |
e63490c8 KRW |
727 | case SPEC_STORE_BYPASS_CMD_NONE: |
728 | break; | |
729 | } | |
730 | ||
23b9eab9 KRW |
731 | /* |
732 | * We have three CPU feature flags that are in play here: | |
733 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 734 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
735 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
736 | */ | |
574dcf89 | 737 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 738 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 739 | /* |
3b881627 KRW |
740 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
741 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 742 | */ |
5005c716 TL |
743 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
744 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 745 | x86_amd_ssb_disable(); |
5005c716 | 746 | } else { |
8fe36c9d | 747 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 748 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 749 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
750 | } |
751 | } | |
752 | ||
e63490c8 KRW |
753 | return mode; |
754 | } | |
755 | ||
043d480e | 756 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
757 | { |
758 | ssb_mode = __ssb_select_mitigation(); | |
759 | ||
760 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
761 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
762 | } | |
763 | ||
da285121 | 764 | #undef pr_fmt |
c7416003 | 765 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 766 | |
801d6893 | 767 | static void task_update_spec_tif(struct task_struct *tsk) |
574dcf89 | 768 | { |
801d6893 TG |
769 | /* Force the update of the real TIF bits */ |
770 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
d4595948 TG |
771 | |
772 | /* | |
773 | * Immediately update the speculation control MSRs for the current | |
774 | * task, but for a non-current task delay setting the CPU | |
775 | * mitigation until it is scheduled next. | |
776 | * | |
777 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
778 | * always the current task. | |
779 | */ | |
801d6893 | 780 | if (tsk == current) |
d4595948 TG |
781 | speculation_ctrl_update_current(); |
782 | } | |
783 | ||
784 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
785 | { | |
c7416003 KC |
786 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
787 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
788 | return -ENXIO; |
789 | ||
733f4234 TG |
790 | switch (ctrl) { |
791 | case PR_SPEC_ENABLE: | |
792 | /* If speculation is force disabled, enable is not allowed */ | |
793 | if (task_spec_ssb_force_disable(task)) | |
794 | return -EPERM; | |
795 | task_clear_spec_ssb_disable(task); | |
801d6893 | 796 | task_update_spec_tif(task); |
733f4234 TG |
797 | break; |
798 | case PR_SPEC_DISABLE: | |
799 | task_set_spec_ssb_disable(task); | |
801d6893 | 800 | task_update_spec_tif(task); |
733f4234 TG |
801 | break; |
802 | case PR_SPEC_FORCE_DISABLE: | |
803 | task_set_spec_ssb_disable(task); | |
804 | task_set_spec_ssb_force_disable(task); | |
801d6893 | 805 | task_update_spec_tif(task); |
733f4234 TG |
806 | break; |
807 | default: | |
808 | return -ERANGE; | |
809 | } | |
574dcf89 TG |
810 | return 0; |
811 | } | |
812 | ||
ac40ad3b TG |
813 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
814 | { | |
815 | switch (ctrl) { | |
816 | case PR_SPEC_ENABLE: | |
817 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
818 | return 0; | |
819 | /* | |
820 | * Indirect branch speculation is always disabled in strict | |
821 | * mode. | |
822 | */ | |
fbed8eca TL |
823 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
824 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
825 | return -EPERM; |
826 | task_clear_spec_ib_disable(task); | |
827 | task_update_spec_tif(task); | |
828 | break; | |
829 | case PR_SPEC_DISABLE: | |
830 | case PR_SPEC_FORCE_DISABLE: | |
831 | /* | |
832 | * Indirect branch speculation is always allowed when | |
833 | * mitigation is force disabled. | |
834 | */ | |
835 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
836 | return -EPERM; | |
fbed8eca TL |
837 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
838 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
839 | return 0; |
840 | task_set_spec_ib_disable(task); | |
841 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
842 | task_set_spec_ib_force_disable(task); | |
843 | task_update_spec_tif(task); | |
844 | break; | |
845 | default: | |
846 | return -ERANGE; | |
847 | } | |
848 | return 0; | |
849 | } | |
850 | ||
5b38e244 TG |
851 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
852 | unsigned long ctrl) | |
853 | { | |
854 | switch (which) { | |
855 | case PR_SPEC_STORE_BYPASS: | |
856 | return ssb_prctl_set(task, ctrl); | |
ac40ad3b TG |
857 | case PR_SPEC_INDIRECT_BRANCH: |
858 | return ib_prctl_set(task, ctrl); | |
5b38e244 TG |
859 | default: |
860 | return -ENODEV; | |
861 | } | |
862 | } | |
863 | ||
864 | #ifdef CONFIG_SECCOMP | |
865 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
866 | { | |
c7416003 KC |
867 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
868 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
1c3cf627 TG |
869 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
870 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
871 | } |
872 | #endif | |
873 | ||
199bfed2 | 874 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
875 | { |
876 | switch (ssb_mode) { | |
877 | case SPEC_STORE_BYPASS_DISABLE: | |
878 | return PR_SPEC_DISABLE; | |
c7416003 | 879 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 880 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
881 | if (task_spec_ssb_force_disable(task)) |
882 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
883 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
884 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
885 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
886 | default: | |
887 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
888 | return PR_SPEC_ENABLE; | |
889 | return PR_SPEC_NOT_AFFECTED; | |
890 | } | |
891 | } | |
892 | ||
ac40ad3b TG |
893 | static int ib_prctl_get(struct task_struct *task) |
894 | { | |
895 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
896 | return PR_SPEC_NOT_AFFECTED; | |
897 | ||
898 | switch (spectre_v2_user) { | |
899 | case SPECTRE_V2_USER_NONE: | |
900 | return PR_SPEC_ENABLE; | |
901 | case SPECTRE_V2_USER_PRCTL: | |
1c3cf627 | 902 | case SPECTRE_V2_USER_SECCOMP: |
ac40ad3b TG |
903 | if (task_spec_ib_force_disable(task)) |
904 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
905 | if (task_spec_ib_disable(task)) | |
906 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
907 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
908 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 909 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
ac40ad3b TG |
910 | return PR_SPEC_DISABLE; |
911 | default: | |
912 | return PR_SPEC_NOT_AFFECTED; | |
913 | } | |
914 | } | |
915 | ||
199bfed2 | 916 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
917 | { |
918 | switch (which) { | |
919 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 920 | return ssb_prctl_get(task); |
ac40ad3b TG |
921 | case PR_SPEC_INDIRECT_BRANCH: |
922 | return ib_prctl_get(task); | |
574dcf89 TG |
923 | default: |
924 | return -ENODEV; | |
925 | } | |
926 | } | |
927 | ||
23b9eab9 KRW |
928 | void x86_spec_ctrl_setup_ap(void) |
929 | { | |
50f9b919 | 930 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 931 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
932 | |
933 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 934 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
935 | } |
936 | ||
73ca9f47 KRW |
937 | #undef pr_fmt |
938 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 939 | |
24fcb53c JK |
940 | /* Default mitigation for L1TF-affected CPUs */ |
941 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 942 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
943 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
944 | ||
522c7bed | 945 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
946 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
947 | #endif | |
948 | ||
f1f016ed AK |
949 | /* |
950 | * These CPUs all support 44bits physical address space internally in the | |
951 | * cache but CPUID can report a smaller number of physical address bits. | |
952 | * | |
953 | * The L1TF mitigation uses the top most address bit for the inversion of | |
954 | * non present PTEs. When the installed memory reaches into the top most | |
955 | * address bit due to memory holes, which has been observed on machines | |
956 | * which report 36bits physical address bits and have 32G RAM installed, | |
957 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
958 | * This is a false positive because the mitigation is still possible due to | |
959 | * the fact that the cache uses 44bit internally. Use the cache bits | |
960 | * instead of the reported physical bits and adjust them on the affected | |
961 | * machines to 44bit if the reported bits are less than 44. | |
962 | */ | |
963 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
964 | { | |
965 | if (c->x86 != 6) | |
966 | return; | |
967 | ||
968 | switch (c->x86_model) { | |
969 | case INTEL_FAM6_NEHALEM: | |
970 | case INTEL_FAM6_WESTMERE: | |
971 | case INTEL_FAM6_SANDYBRIDGE: | |
972 | case INTEL_FAM6_IVYBRIDGE: | |
973 | case INTEL_FAM6_HASWELL_CORE: | |
974 | case INTEL_FAM6_HASWELL_ULT: | |
975 | case INTEL_FAM6_HASWELL_GT3E: | |
976 | case INTEL_FAM6_BROADWELL_CORE: | |
977 | case INTEL_FAM6_BROADWELL_GT3E: | |
978 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
979 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
980 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
981 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
982 | if (c->x86_cache_bits < 44) | |
983 | c->x86_cache_bits = 44; | |
984 | break; | |
985 | } | |
986 | } | |
987 | ||
73ca9f47 KRW |
988 | static void __init l1tf_select_mitigation(void) |
989 | { | |
990 | u64 half_pa; | |
991 | ||
992 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
993 | return; | |
994 | ||
f1f016ed AK |
995 | override_cache_bits(&boot_cpu_data); |
996 | ||
24fcb53c JK |
997 | switch (l1tf_mitigation) { |
998 | case L1TF_MITIGATION_OFF: | |
999 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
1000 | case L1TF_MITIGATION_FLUSH: | |
1001 | break; | |
1002 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
1003 | case L1TF_MITIGATION_FULL: | |
1004 | cpu_smt_disable(false); | |
1005 | break; | |
1006 | case L1TF_MITIGATION_FULL_FORCE: | |
1007 | cpu_smt_disable(true); | |
1008 | break; | |
1009 | } | |
1010 | ||
73ca9f47 KRW |
1011 | #if CONFIG_PGTABLE_LEVELS == 2 |
1012 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1013 | return; | |
1014 | #endif | |
1015 | ||
73ca9f47 KRW |
1016 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
1017 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
1018 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
1019 | return; | |
1020 | } | |
1021 | ||
1022 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1023 | } | |
24fcb53c JK |
1024 | |
1025 | static int __init l1tf_cmdline(char *str) | |
1026 | { | |
1027 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1028 | return 0; | |
1029 | ||
1030 | if (!str) | |
1031 | return -EINVAL; | |
1032 | ||
1033 | if (!strcmp(str, "off")) | |
1034 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1035 | else if (!strcmp(str, "flush,nowarn")) | |
1036 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1037 | else if (!strcmp(str, "flush")) | |
1038 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1039 | else if (!strcmp(str, "flush,nosmt")) | |
1040 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1041 | else if (!strcmp(str, "full")) | |
1042 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1043 | else if (!strcmp(str, "full,force")) | |
1044 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | early_param("l1tf", l1tf_cmdline); | |
1049 | ||
73ca9f47 KRW |
1050 | #undef pr_fmt |
1051 | ||
61dc0f55 | 1052 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 1053 | |
b9cfedcd TG |
1054 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1055 | ||
1056 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 1057 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
1058 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1059 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1060 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1061 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1062 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 1063 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
1064 | }; |
1065 | ||
1066 | static ssize_t l1tf_show_state(char *buf) | |
1067 | { | |
1068 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1069 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1070 | ||
3899f7b1 PB |
1071 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1072 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 1073 | sched_smt_active())) { |
3899f7b1 PB |
1074 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1075 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 1076 | } |
3899f7b1 PB |
1077 | |
1078 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1079 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 1080 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
1081 | } |
1082 | #else | |
1083 | static ssize_t l1tf_show_state(char *buf) | |
1084 | { | |
1085 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1086 | } | |
1087 | #endif | |
1088 | ||
2daa53e8 TC |
1089 | static char *stibp_state(void) |
1090 | { | |
4a8d91c8 TC |
1091 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1092 | return ""; | |
1093 | ||
6cd930f0 TG |
1094 | switch (spectre_v2_user) { |
1095 | case SPECTRE_V2_USER_NONE: | |
1096 | return ", STIBP: disabled"; | |
1097 | case SPECTRE_V2_USER_STRICT: | |
1098 | return ", STIBP: forced"; | |
fbed8eca TL |
1099 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
1100 | return ", STIBP: always-on"; | |
ac40ad3b | 1101 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 1102 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 TG |
1103 | if (static_key_enabled(&switch_to_cond_stibp)) |
1104 | return ", STIBP: conditional"; | |
6cd930f0 TG |
1105 | } |
1106 | return ""; | |
2daa53e8 TC |
1107 | } |
1108 | ||
1109 | static char *ibpb_state(void) | |
1110 | { | |
58b2d4c8 | 1111 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
2cdf6a58 | 1112 | if (static_key_enabled(&switch_mm_always_ibpb)) |
58b2d4c8 | 1113 | return ", IBPB: always-on"; |
2cdf6a58 TG |
1114 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1115 | return ", IBPB: conditional"; | |
1116 | return ", IBPB: disabled"; | |
58b2d4c8 TG |
1117 | } |
1118 | return ""; | |
2daa53e8 TC |
1119 | } |
1120 | ||
ace051d5 | 1121 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 1122 | char *buf, unsigned int bug) |
61dc0f55 | 1123 | { |
d2b8fc2d | 1124 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1125 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
1126 | |
1127 | switch (bug) { | |
1128 | case X86_BUG_CPU_MELTDOWN: | |
1129 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1130 | return sprintf(buf, "Mitigation: PTI\n"); | |
1131 | ||
1132 | break; | |
1133 | ||
1134 | case X86_BUG_SPECTRE_V1: | |
1135 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
1136 | ||
1137 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 1138 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 1139 | ibpb_state(), |
d2b8fc2d | 1140 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 1141 | stibp_state(), |
5e2fafd5 | 1142 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
1143 | spectre_v2_module_string()); |
1144 | ||
e63490c8 KRW |
1145 | case X86_BUG_SPEC_STORE_BYPASS: |
1146 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1147 | ||
05516ad8 AK |
1148 | case X86_BUG_L1TF: |
1149 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 1150 | return l1tf_show_state(buf); |
05516ad8 | 1151 | break; |
d2b8fc2d KRW |
1152 | default: |
1153 | break; | |
1154 | } | |
1155 | ||
61dc0f55 TG |
1156 | return sprintf(buf, "Vulnerable\n"); |
1157 | } | |
1158 | ||
d2b8fc2d KRW |
1159 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1160 | { | |
1161 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1162 | } | |
1163 | ||
713f1b95 | 1164 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1165 | { |
d2b8fc2d | 1166 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1167 | } |
1168 | ||
713f1b95 | 1169 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1170 | { |
d2b8fc2d | 1171 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1172 | } |
d7de9182 KRW |
1173 | |
1174 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1175 | { | |
1176 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1177 | } | |
05516ad8 AK |
1178 | |
1179 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1180 | { | |
1181 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1182 | } | |
61dc0f55 | 1183 | #endif |