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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1353ebb4 | 33 | |
da285121 | 34 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 35 | static void __init ssb_select_mitigation(void); |
05516ad8 | 36 | static void __init l1tf_select_mitigation(void); |
da285121 | 37 | |
7011f443 JK |
38 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
39 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 40 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 41 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 42 | |
d0c3bedd KRW |
43 | /* |
44 | * The vendor and possibly platform specific bits which can be modified in | |
45 | * x86_spec_ctrl_base. | |
46 | */ | |
e5f984ed | 47 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 48 | |
c37b94dd KRW |
49 | /* |
50 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 51 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
52 | */ |
53 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 54 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 55 | |
8edb388f | 56 | /* Control conditional STIBP in switch_to() */ |
6cd930f0 | 57 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
58b2d4c8 TG |
58 | /* Control conditional IBPB in switch_mm() */ |
59 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
60 | /* Control unconditional IBPB in switch_mm() */ | |
61 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
6cd930f0 | 62 | |
5ab15133 TG |
63 | /* Control MDS CPU buffer clear before returning to user space */ |
64 | DEFINE_STATIC_KEY_FALSE(mds_user_clear); | |
abf9852b | 65 | EXPORT_SYMBOL_GPL(mds_user_clear); |
5ab15133 | 66 | |
1353ebb4 JF |
67 | void __init check_bugs(void) |
68 | { | |
69 | identify_boot_cpu(); | |
55a36b65 | 70 | |
483ec3c6 TG |
71 | /* |
72 | * identify_boot_cpu() initialized SMT support information, let the | |
73 | * core code know. | |
74 | */ | |
ade31b9e | 75 | cpu_smt_check_topology_early(); |
483ec3c6 | 76 | |
62a67e12 BP |
77 | if (!IS_ENABLED(CONFIG_SMP)) { |
78 | pr_info("CPU: "); | |
79 | print_cpu_info(&boot_cpu_data); | |
80 | } | |
81 | ||
296b454a KRW |
82 | /* |
83 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
84 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
85 | * init code as it is not enumerated and depends on the family. | |
296b454a | 86 | */ |
50f9b919 | 87 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
88 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
89 | ||
e5f984ed TG |
90 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
91 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
92 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
93 | ||
da285121 DW |
94 | /* Select the proper spectre mitigation before patching alternatives */ |
95 | spectre_v2_select_mitigation(); | |
96 | ||
e63490c8 KRW |
97 | /* |
98 | * Select proper mitigation for any exposure to the Speculative Store | |
99 | * Bypass vulnerability. | |
100 | */ | |
101 | ssb_select_mitigation(); | |
102 | ||
05516ad8 AK |
103 | l1tf_select_mitigation(); |
104 | ||
62a67e12 | 105 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
106 | /* |
107 | * Check whether we are able to run this kernel safely on SMP. | |
108 | * | |
109 | * - i386 is no longer supported. | |
110 | * - In order to run on anything without a TSC, we need to be | |
111 | * compiled for a i486. | |
112 | */ | |
113 | if (boot_cpu_data.x86 < 4) | |
114 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
115 | ||
bfe4bb15 MV |
116 | init_utsname()->machine[1] = |
117 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 118 | alternative_instructions(); |
304bceda | 119 | |
4d164092 | 120 | fpu__init_check_bugs(); |
62a67e12 BP |
121 | #else /* CONFIG_X86_64 */ |
122 | alternative_instructions(); | |
123 | ||
124 | /* | |
125 | * Make sure the first 2MB area is not mapped by huge pages | |
126 | * There are typically fixed size MTRRs in there and overlapping | |
127 | * MTRRs into large pages causes slow downs. | |
128 | * | |
129 | * Right now we don't do that with gbpages because there seems | |
130 | * very little benefit for that case. | |
131 | */ | |
132 | if (!direct_gbpages) | |
133 | set_memory_4k((unsigned long)__va(0), 1); | |
134 | #endif | |
1353ebb4 | 135 | } |
61dc0f55 | 136 | |
12376b62 BP |
137 | void |
138 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 139 | { |
e5f984ed | 140 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 141 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 142 | |
50f9b919 | 143 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 144 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
145 | /* |
146 | * Restrict guest_spec_ctrl to supported values. Clear the | |
147 | * modifiable bits in the host base value and or the | |
148 | * modifiable bits from the guest value. | |
149 | */ | |
150 | guestval = hostval & ~x86_spec_ctrl_mask; | |
151 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
152 | ||
12376b62 | 153 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
154 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
155 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 156 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 157 | |
e0b04783 TC |
158 | /* Conditional STIBP enabled? */ |
159 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
160 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
161 | ||
e5f984ed TG |
162 | if (hostval != guestval) { |
163 | msrval = setguest ? guestval : hostval; | |
164 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
165 | } |
166 | } | |
1238ed31 TG |
167 | |
168 | /* | |
169 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
170 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
171 | */ | |
172 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
173 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
174 | return; | |
175 | ||
176 | /* | |
177 | * If the host has SSBD mitigation enabled, force it in the host's | |
178 | * virtual MSR value. If its not permanently enabled, evaluate | |
179 | * current's TIF_SSBD thread flag. | |
180 | */ | |
181 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
182 | hostval = SPEC_CTRL_SSBD; | |
183 | else | |
184 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
185 | ||
186 | /* Sanitize the guest value */ | |
187 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
188 | ||
189 | if (hostval != guestval) { | |
190 | unsigned long tif; | |
191 | ||
192 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
193 | ssbd_spec_ctrl_to_tif(hostval); | |
194 | ||
8fce7184 | 195 | speculation_ctrl_update(tif); |
1238ed31 | 196 | } |
19fff03f | 197 | } |
12376b62 | 198 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 199 | |
8fe36c9d | 200 | static void x86_amd_ssb_disable(void) |
c37b94dd | 201 | { |
8fe36c9d | 202 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 203 | |
65e02bbd TL |
204 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
205 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
206 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
207 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
208 | } | |
209 | ||
aef0bebc TG |
210 | #undef pr_fmt |
211 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
212 | ||
213 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
214 | SPECTRE_V2_NONE; | |
215 | ||
6cd930f0 TG |
216 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
217 | SPECTRE_V2_USER_NONE; | |
218 | ||
e9a556ad | 219 | #ifdef CONFIG_RETPOLINE |
bb3c2578 TG |
220 | static bool spectre_v2_bad_module; |
221 | ||
d280282b AK |
222 | bool retpoline_module_ok(bool has_retpoline) |
223 | { | |
224 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
225 | return true; | |
226 | ||
c8b8e109 | 227 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
228 | spectre_v2_bad_module = true; |
229 | return false; | |
230 | } | |
bb3c2578 TG |
231 | |
232 | static inline const char *spectre_v2_module_string(void) | |
233 | { | |
234 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
235 | } | |
236 | #else | |
237 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 238 | #endif |
da285121 | 239 | |
da285121 DW |
240 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
241 | { | |
242 | int len = strlen(opt); | |
243 | ||
244 | return len == arglen && !strncmp(arg, opt, len); | |
245 | } | |
246 | ||
aef0bebc TG |
247 | /* The kernel command line selection for spectre v2 */ |
248 | enum spectre_v2_mitigation_cmd { | |
249 | SPECTRE_V2_CMD_NONE, | |
250 | SPECTRE_V2_CMD_AUTO, | |
251 | SPECTRE_V2_CMD_FORCE, | |
252 | SPECTRE_V2_CMD_RETPOLINE, | |
253 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
254 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
255 | }; | |
256 | ||
6cd930f0 TG |
257 | enum spectre_v2_user_cmd { |
258 | SPECTRE_V2_USER_CMD_NONE, | |
259 | SPECTRE_V2_USER_CMD_AUTO, | |
260 | SPECTRE_V2_USER_CMD_FORCE, | |
2cdf6a58 | 261 | SPECTRE_V2_USER_CMD_PRCTL, |
fd1b7023 | 262 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
1c3cf627 | 263 | SPECTRE_V2_USER_CMD_SECCOMP, |
fd1b7023 | 264 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
6cd930f0 TG |
265 | }; |
266 | ||
267 | static const char * const spectre_v2_user_strings[] = { | |
fbed8eca TL |
268 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", |
269 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
270 | [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", | |
271 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", | |
272 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", | |
6cd930f0 TG |
273 | }; |
274 | ||
275 | static const struct { | |
276 | const char *option; | |
277 | enum spectre_v2_user_cmd cmd; | |
278 | bool secure; | |
279 | } v2_user_options[] __initdata = { | |
fd1b7023 TG |
280 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
281 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
282 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
283 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
284 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
285 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
286 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
6cd930f0 TG |
287 | }; |
288 | ||
289 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
290 | { | |
291 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
292 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
293 | } | |
294 | ||
295 | static enum spectre_v2_user_cmd __init | |
296 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
297 | { | |
298 | char arg[20]; | |
299 | int ret, i; | |
300 | ||
301 | switch (v2_cmd) { | |
302 | case SPECTRE_V2_CMD_NONE: | |
303 | return SPECTRE_V2_USER_CMD_NONE; | |
304 | case SPECTRE_V2_CMD_FORCE: | |
305 | return SPECTRE_V2_USER_CMD_FORCE; | |
306 | default: | |
307 | break; | |
308 | } | |
309 | ||
310 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
311 | arg, sizeof(arg)); | |
312 | if (ret < 0) | |
313 | return SPECTRE_V2_USER_CMD_AUTO; | |
314 | ||
315 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
316 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
317 | spec_v2_user_print_cond(v2_user_options[i].option, | |
318 | v2_user_options[i].secure); | |
319 | return v2_user_options[i].cmd; | |
320 | } | |
321 | } | |
322 | ||
323 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
324 | return SPECTRE_V2_USER_CMD_AUTO; | |
325 | } | |
326 | ||
327 | static void __init | |
328 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
329 | { | |
330 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
331 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
fd1b7023 | 332 | enum spectre_v2_user_cmd cmd; |
6cd930f0 TG |
333 | |
334 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
335 | return; | |
336 | ||
337 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
338 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
339 | smt_possible = false; | |
340 | ||
fd1b7023 TG |
341 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
342 | switch (cmd) { | |
6cd930f0 TG |
343 | case SPECTRE_V2_USER_CMD_NONE: |
344 | goto set_mode; | |
345 | case SPECTRE_V2_USER_CMD_FORCE: | |
346 | mode = SPECTRE_V2_USER_STRICT; | |
347 | break; | |
2cdf6a58 | 348 | case SPECTRE_V2_USER_CMD_PRCTL: |
fd1b7023 | 349 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
2cdf6a58 TG |
350 | mode = SPECTRE_V2_USER_PRCTL; |
351 | break; | |
1c3cf627 TG |
352 | case SPECTRE_V2_USER_CMD_AUTO: |
353 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
fd1b7023 | 354 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
1c3cf627 TG |
355 | if (IS_ENABLED(CONFIG_SECCOMP)) |
356 | mode = SPECTRE_V2_USER_SECCOMP; | |
357 | else | |
358 | mode = SPECTRE_V2_USER_PRCTL; | |
359 | break; | |
6cd930f0 TG |
360 | } |
361 | ||
fbed8eca TL |
362 | /* |
363 | * At this point, an STIBP mode other than "off" has been set. | |
364 | * If STIBP support is not being forced, check if STIBP always-on | |
365 | * is preferred. | |
366 | */ | |
367 | if (mode != SPECTRE_V2_USER_STRICT && | |
368 | boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) | |
369 | mode = SPECTRE_V2_USER_STRICT_PREFERRED; | |
370 | ||
6cd930f0 TG |
371 | /* Initialize Indirect Branch Prediction Barrier */ |
372 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
373 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
58b2d4c8 | 374 | |
fd1b7023 TG |
375 | switch (cmd) { |
376 | case SPECTRE_V2_USER_CMD_FORCE: | |
377 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
378 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
58b2d4c8 TG |
379 | static_branch_enable(&switch_mm_always_ibpb); |
380 | break; | |
fd1b7023 TG |
381 | case SPECTRE_V2_USER_CMD_PRCTL: |
382 | case SPECTRE_V2_USER_CMD_AUTO: | |
383 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
2cdf6a58 TG |
384 | static_branch_enable(&switch_mm_cond_ibpb); |
385 | break; | |
58b2d4c8 TG |
386 | default: |
387 | break; | |
388 | } | |
389 | ||
390 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
fd1b7023 TG |
391 | static_key_enabled(&switch_mm_always_ibpb) ? |
392 | "always-on" : "conditional"); | |
6cd930f0 TG |
393 | } |
394 | ||
8edb388f | 395 | /* If enhanced IBRS is enabled no STIBP required */ |
6cd930f0 TG |
396 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
397 | return; | |
398 | ||
2cdf6a58 | 399 | /* |
8edb388f | 400 | * If SMT is not possible or STIBP is not available clear the STIBP |
2cdf6a58 TG |
401 | * mode. |
402 | */ | |
403 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
404 | mode = SPECTRE_V2_USER_NONE; | |
6cd930f0 TG |
405 | set_mode: |
406 | spectre_v2_user = mode; | |
407 | /* Only print the STIBP mode when SMT possible */ | |
408 | if (smt_possible) | |
409 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
410 | } | |
411 | ||
0eb5928b | 412 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
413 | [SPECTRE_V2_NONE] = "Vulnerable", |
414 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
415 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
416 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
417 | }; | |
418 | ||
17c33e7c KA |
419 | static const struct { |
420 | const char *option; | |
421 | enum spectre_v2_mitigation_cmd cmd; | |
422 | bool secure; | |
5a76cb46 | 423 | } mitigation_options[] __initdata = { |
aef0bebc TG |
424 | { "off", SPECTRE_V2_CMD_NONE, false }, |
425 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
426 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
427 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
428 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
429 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
430 | }; |
431 | ||
10640103 | 432 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 433 | { |
10640103 | 434 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
435 | pr_info("%s selected on command line.\n", reason); |
436 | } | |
437 | ||
da285121 DW |
438 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
439 | { | |
aef0bebc | 440 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 441 | char arg[20]; |
17c33e7c | 442 | int ret, i; |
17c33e7c KA |
443 | |
444 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
445 | return SPECTRE_V2_CMD_NONE; | |
17c33e7c | 446 | |
4e8e955a TC |
447 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
448 | if (ret < 0) | |
449 | return SPECTRE_V2_CMD_AUTO; | |
450 | ||
451 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
452 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
453 | continue; | |
454 | cmd = mitigation_options[i].cmd; | |
455 | break; | |
456 | } | |
457 | ||
458 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
459 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
460 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
461 | } |
462 | ||
17c33e7c KA |
463 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
464 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
465 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
466 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 467 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 468 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
469 | } |
470 | ||
471 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
472 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
473 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
474 | return SPECTRE_V2_CMD_AUTO; | |
475 | } | |
476 | ||
10640103 TG |
477 | spec_v2_print_cond(mitigation_options[i].option, |
478 | mitigation_options[i].secure); | |
17c33e7c | 479 | return cmd; |
da285121 DW |
480 | } |
481 | ||
482 | static void __init spectre_v2_select_mitigation(void) | |
483 | { | |
484 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
485 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
486 | ||
487 | /* | |
488 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
489 | * then nothing to do. | |
490 | */ | |
491 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
492 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
493 | return; | |
494 | ||
495 | switch (cmd) { | |
496 | case SPECTRE_V2_CMD_NONE: | |
497 | return; | |
498 | ||
499 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 500 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
501 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
502 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
503 | /* Force it so VMEXIT will restore correctly */ | |
504 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
505 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
506 | goto specv2_set_mode; | |
507 | } | |
d0f293e0 DL |
508 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
509 | goto retpoline_auto; | |
510 | break; | |
da285121 DW |
511 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
512 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
513 | goto retpoline_amd; | |
514 | break; | |
515 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
516 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
517 | goto retpoline_generic; | |
518 | break; | |
519 | case SPECTRE_V2_CMD_RETPOLINE: | |
520 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
521 | goto retpoline_auto; | |
522 | break; | |
523 | } | |
713f1b95 | 524 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
525 | return; |
526 | ||
527 | retpoline_auto: | |
528 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
529 | retpoline_amd: | |
530 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 531 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
532 | goto retpoline_generic; |
533 | } | |
51dd01b5 | 534 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
535 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
536 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
537 | } else { | |
538 | retpoline_generic: | |
51dd01b5 | 539 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
540 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
541 | } | |
542 | ||
1044fde9 | 543 | specv2_set_mode: |
da285121 DW |
544 | spectre_v2_enabled = mode; |
545 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
546 | |
547 | /* | |
14623a43 JK |
548 | * If spectre v2 protection has been enabled, unconditionally fill |
549 | * RSB during a context switch; this protects against two independent | |
550 | * issues: | |
c995efd5 | 551 | * |
14623a43 JK |
552 | * - RSB underflow (and switch to BTB) on Skylake+ |
553 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 554 | */ |
14623a43 JK |
555 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
556 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 557 | |
390b99c3 DW |
558 | /* |
559 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
560 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
561 | * speculation around firmware calls only when Enhanced IBRS isn't | |
562 | * supported. | |
563 | * | |
564 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
565 | * the user might select retpoline on the kernel command line and if | |
566 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
567 | * enable IBRS around firmware calls. | |
390b99c3 | 568 | */ |
1044fde9 | 569 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
570 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
571 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
572 | } | |
7011f443 | 573 | |
6cd930f0 TG |
574 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
575 | spectre_v2_user_select_mitigation(cmd); | |
576 | ||
7011f443 JK |
577 | /* Enable STIBP if appropriate */ |
578 | arch_smt_update(); | |
da285121 DW |
579 | } |
580 | ||
984d266f | 581 | static void update_stibp_msr(void * __unused) |
aef0bebc | 582 | { |
984d266f | 583 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
aef0bebc TG |
584 | } |
585 | ||
984d266f TG |
586 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
587 | static void update_stibp_strict(void) | |
aef0bebc | 588 | { |
984d266f TG |
589 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
590 | ||
591 | if (sched_smt_active()) | |
592 | mask |= SPEC_CTRL_STIBP; | |
593 | ||
594 | if (mask == x86_spec_ctrl_base) | |
595 | return; | |
596 | ||
597 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
598 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
599 | x86_spec_ctrl_base = mask; | |
600 | on_each_cpu(update_stibp_msr, NULL, 1); | |
aef0bebc TG |
601 | } |
602 | ||
2cdf6a58 TG |
603 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
604 | static void update_indir_branch_cond(void) | |
605 | { | |
606 | if (sched_smt_active()) | |
607 | static_branch_enable(&switch_to_cond_stibp); | |
608 | else | |
609 | static_branch_disable(&switch_to_cond_stibp); | |
610 | } | |
611 | ||
aef0bebc TG |
612 | void arch_smt_update(void) |
613 | { | |
984d266f TG |
614 | /* Enhanced IBRS implies STIBP. No update required. */ |
615 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
aef0bebc TG |
616 | return; |
617 | ||
618 | mutex_lock(&spec_ctrl_mutex); | |
619 | ||
984d266f TG |
620 | switch (spectre_v2_user) { |
621 | case SPECTRE_V2_USER_NONE: | |
622 | break; | |
623 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 624 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
984d266f TG |
625 | update_stibp_strict(); |
626 | break; | |
ac40ad3b | 627 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 628 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 | 629 | update_indir_branch_cond(); |
ac40ad3b | 630 | break; |
aef0bebc | 631 | } |
984d266f | 632 | |
aef0bebc TG |
633 | mutex_unlock(&spec_ctrl_mutex); |
634 | } | |
635 | ||
e63490c8 KRW |
636 | #undef pr_fmt |
637 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
638 | ||
b5e6d77d | 639 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
640 | |
641 | /* The kernel command line selection */ | |
642 | enum ssb_mitigation_cmd { | |
643 | SPEC_STORE_BYPASS_CMD_NONE, | |
644 | SPEC_STORE_BYPASS_CMD_AUTO, | |
645 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 646 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 647 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
648 | }; |
649 | ||
0eb5928b | 650 | static const char * const ssb_strings[] = { |
e63490c8 | 651 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 652 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
653 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
654 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
655 | }; |
656 | ||
657 | static const struct { | |
658 | const char *option; | |
659 | enum ssb_mitigation_cmd cmd; | |
5a76cb46 | 660 | } ssb_mitigation_options[] __initdata = { |
c7416003 KC |
661 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
662 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
663 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
664 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
665 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
666 | }; |
667 | ||
668 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
669 | { | |
670 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
671 | char arg[20]; | |
672 | int ret, i; | |
673 | ||
674 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
675 | return SPEC_STORE_BYPASS_CMD_NONE; | |
676 | } else { | |
677 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
678 | arg, sizeof(arg)); | |
679 | if (ret < 0) | |
680 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
681 | ||
682 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
683 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
684 | continue; | |
685 | ||
686 | cmd = ssb_mitigation_options[i].cmd; | |
687 | break; | |
688 | } | |
689 | ||
690 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
691 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
692 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
693 | } | |
694 | } | |
695 | ||
696 | return cmd; | |
697 | } | |
698 | ||
dbe3009d | 699 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
700 | { |
701 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
702 | enum ssb_mitigation_cmd cmd; | |
703 | ||
8fe36c9d | 704 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
705 | return mode; |
706 | ||
707 | cmd = ssb_parse_cmdline(); | |
708 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
709 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
710 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
711 | return mode; | |
712 | ||
713 | switch (cmd) { | |
714 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
715 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
716 | /* | |
717 | * Choose prctl+seccomp as the default mode if seccomp is | |
718 | * enabled. | |
719 | */ | |
720 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
721 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
722 | else | |
723 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 724 | break; |
e63490c8 KRW |
725 | case SPEC_STORE_BYPASS_CMD_ON: |
726 | mode = SPEC_STORE_BYPASS_DISABLE; | |
727 | break; | |
574dcf89 TG |
728 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
729 | mode = SPEC_STORE_BYPASS_PRCTL; | |
730 | break; | |
e63490c8 KRW |
731 | case SPEC_STORE_BYPASS_CMD_NONE: |
732 | break; | |
733 | } | |
734 | ||
23b9eab9 KRW |
735 | /* |
736 | * We have three CPU feature flags that are in play here: | |
737 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 738 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
739 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
740 | */ | |
574dcf89 | 741 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 742 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 743 | /* |
3b881627 KRW |
744 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
745 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 746 | */ |
5005c716 TL |
747 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
748 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 749 | x86_amd_ssb_disable(); |
5005c716 | 750 | } else { |
8fe36c9d | 751 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 752 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 753 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
754 | } |
755 | } | |
756 | ||
e63490c8 KRW |
757 | return mode; |
758 | } | |
759 | ||
043d480e | 760 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
761 | { |
762 | ssb_mode = __ssb_select_mitigation(); | |
763 | ||
764 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
765 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
766 | } | |
767 | ||
da285121 | 768 | #undef pr_fmt |
c7416003 | 769 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 770 | |
801d6893 | 771 | static void task_update_spec_tif(struct task_struct *tsk) |
574dcf89 | 772 | { |
801d6893 TG |
773 | /* Force the update of the real TIF bits */ |
774 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
d4595948 TG |
775 | |
776 | /* | |
777 | * Immediately update the speculation control MSRs for the current | |
778 | * task, but for a non-current task delay setting the CPU | |
779 | * mitigation until it is scheduled next. | |
780 | * | |
781 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
782 | * always the current task. | |
783 | */ | |
801d6893 | 784 | if (tsk == current) |
d4595948 TG |
785 | speculation_ctrl_update_current(); |
786 | } | |
787 | ||
788 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
789 | { | |
c7416003 KC |
790 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
791 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
792 | return -ENXIO; |
793 | ||
733f4234 TG |
794 | switch (ctrl) { |
795 | case PR_SPEC_ENABLE: | |
796 | /* If speculation is force disabled, enable is not allowed */ | |
797 | if (task_spec_ssb_force_disable(task)) | |
798 | return -EPERM; | |
799 | task_clear_spec_ssb_disable(task); | |
801d6893 | 800 | task_update_spec_tif(task); |
733f4234 TG |
801 | break; |
802 | case PR_SPEC_DISABLE: | |
803 | task_set_spec_ssb_disable(task); | |
801d6893 | 804 | task_update_spec_tif(task); |
733f4234 TG |
805 | break; |
806 | case PR_SPEC_FORCE_DISABLE: | |
807 | task_set_spec_ssb_disable(task); | |
808 | task_set_spec_ssb_force_disable(task); | |
801d6893 | 809 | task_update_spec_tif(task); |
733f4234 TG |
810 | break; |
811 | default: | |
812 | return -ERANGE; | |
813 | } | |
574dcf89 TG |
814 | return 0; |
815 | } | |
816 | ||
ac40ad3b TG |
817 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
818 | { | |
819 | switch (ctrl) { | |
820 | case PR_SPEC_ENABLE: | |
821 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
822 | return 0; | |
823 | /* | |
824 | * Indirect branch speculation is always disabled in strict | |
825 | * mode. | |
826 | */ | |
fbed8eca TL |
827 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
828 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
829 | return -EPERM; |
830 | task_clear_spec_ib_disable(task); | |
831 | task_update_spec_tif(task); | |
832 | break; | |
833 | case PR_SPEC_DISABLE: | |
834 | case PR_SPEC_FORCE_DISABLE: | |
835 | /* | |
836 | * Indirect branch speculation is always allowed when | |
837 | * mitigation is force disabled. | |
838 | */ | |
839 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
840 | return -EPERM; | |
fbed8eca TL |
841 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
842 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
843 | return 0; |
844 | task_set_spec_ib_disable(task); | |
845 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
846 | task_set_spec_ib_force_disable(task); | |
847 | task_update_spec_tif(task); | |
848 | break; | |
849 | default: | |
850 | return -ERANGE; | |
851 | } | |
852 | return 0; | |
853 | } | |
854 | ||
5b38e244 TG |
855 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
856 | unsigned long ctrl) | |
857 | { | |
858 | switch (which) { | |
859 | case PR_SPEC_STORE_BYPASS: | |
860 | return ssb_prctl_set(task, ctrl); | |
ac40ad3b TG |
861 | case PR_SPEC_INDIRECT_BRANCH: |
862 | return ib_prctl_set(task, ctrl); | |
5b38e244 TG |
863 | default: |
864 | return -ENODEV; | |
865 | } | |
866 | } | |
867 | ||
868 | #ifdef CONFIG_SECCOMP | |
869 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
870 | { | |
c7416003 KC |
871 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
872 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
1c3cf627 TG |
873 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
874 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
875 | } |
876 | #endif | |
877 | ||
199bfed2 | 878 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
879 | { |
880 | switch (ssb_mode) { | |
881 | case SPEC_STORE_BYPASS_DISABLE: | |
882 | return PR_SPEC_DISABLE; | |
c7416003 | 883 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 884 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
885 | if (task_spec_ssb_force_disable(task)) |
886 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
887 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
888 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
889 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
890 | default: | |
891 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
892 | return PR_SPEC_ENABLE; | |
893 | return PR_SPEC_NOT_AFFECTED; | |
894 | } | |
895 | } | |
896 | ||
ac40ad3b TG |
897 | static int ib_prctl_get(struct task_struct *task) |
898 | { | |
899 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
900 | return PR_SPEC_NOT_AFFECTED; | |
901 | ||
902 | switch (spectre_v2_user) { | |
903 | case SPECTRE_V2_USER_NONE: | |
904 | return PR_SPEC_ENABLE; | |
905 | case SPECTRE_V2_USER_PRCTL: | |
1c3cf627 | 906 | case SPECTRE_V2_USER_SECCOMP: |
ac40ad3b TG |
907 | if (task_spec_ib_force_disable(task)) |
908 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
909 | if (task_spec_ib_disable(task)) | |
910 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
911 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
912 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 913 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
ac40ad3b TG |
914 | return PR_SPEC_DISABLE; |
915 | default: | |
916 | return PR_SPEC_NOT_AFFECTED; | |
917 | } | |
918 | } | |
919 | ||
199bfed2 | 920 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
921 | { |
922 | switch (which) { | |
923 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 924 | return ssb_prctl_get(task); |
ac40ad3b TG |
925 | case PR_SPEC_INDIRECT_BRANCH: |
926 | return ib_prctl_get(task); | |
574dcf89 TG |
927 | default: |
928 | return -ENODEV; | |
929 | } | |
930 | } | |
931 | ||
23b9eab9 KRW |
932 | void x86_spec_ctrl_setup_ap(void) |
933 | { | |
50f9b919 | 934 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 935 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
936 | |
937 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 938 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
939 | } |
940 | ||
73ca9f47 KRW |
941 | #undef pr_fmt |
942 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 943 | |
24fcb53c JK |
944 | /* Default mitigation for L1TF-affected CPUs */ |
945 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 946 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
947 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
948 | ||
522c7bed | 949 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
950 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
951 | #endif | |
952 | ||
f1f016ed AK |
953 | /* |
954 | * These CPUs all support 44bits physical address space internally in the | |
955 | * cache but CPUID can report a smaller number of physical address bits. | |
956 | * | |
957 | * The L1TF mitigation uses the top most address bit for the inversion of | |
958 | * non present PTEs. When the installed memory reaches into the top most | |
959 | * address bit due to memory holes, which has been observed on machines | |
960 | * which report 36bits physical address bits and have 32G RAM installed, | |
961 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
962 | * This is a false positive because the mitigation is still possible due to | |
963 | * the fact that the cache uses 44bit internally. Use the cache bits | |
964 | * instead of the reported physical bits and adjust them on the affected | |
965 | * machines to 44bit if the reported bits are less than 44. | |
966 | */ | |
967 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
968 | { | |
969 | if (c->x86 != 6) | |
970 | return; | |
971 | ||
972 | switch (c->x86_model) { | |
973 | case INTEL_FAM6_NEHALEM: | |
974 | case INTEL_FAM6_WESTMERE: | |
975 | case INTEL_FAM6_SANDYBRIDGE: | |
976 | case INTEL_FAM6_IVYBRIDGE: | |
977 | case INTEL_FAM6_HASWELL_CORE: | |
978 | case INTEL_FAM6_HASWELL_ULT: | |
979 | case INTEL_FAM6_HASWELL_GT3E: | |
980 | case INTEL_FAM6_BROADWELL_CORE: | |
981 | case INTEL_FAM6_BROADWELL_GT3E: | |
982 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
983 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
984 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
985 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
986 | if (c->x86_cache_bits < 44) | |
987 | c->x86_cache_bits = 44; | |
988 | break; | |
989 | } | |
990 | } | |
991 | ||
73ca9f47 KRW |
992 | static void __init l1tf_select_mitigation(void) |
993 | { | |
994 | u64 half_pa; | |
995 | ||
996 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
997 | return; | |
998 | ||
f1f016ed AK |
999 | override_cache_bits(&boot_cpu_data); |
1000 | ||
24fcb53c JK |
1001 | switch (l1tf_mitigation) { |
1002 | case L1TF_MITIGATION_OFF: | |
1003 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
1004 | case L1TF_MITIGATION_FLUSH: | |
1005 | break; | |
1006 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
1007 | case L1TF_MITIGATION_FULL: | |
1008 | cpu_smt_disable(false); | |
1009 | break; | |
1010 | case L1TF_MITIGATION_FULL_FORCE: | |
1011 | cpu_smt_disable(true); | |
1012 | break; | |
1013 | } | |
1014 | ||
73ca9f47 KRW |
1015 | #if CONFIG_PGTABLE_LEVELS == 2 |
1016 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1017 | return; | |
1018 | #endif | |
1019 | ||
73ca9f47 KRW |
1020 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
1021 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
1022 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
f80e341a VB |
1023 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
1024 | half_pa); | |
1025 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
1026 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n"); | |
73ca9f47 KRW |
1027 | return; |
1028 | } | |
1029 | ||
1030 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1031 | } | |
24fcb53c JK |
1032 | |
1033 | static int __init l1tf_cmdline(char *str) | |
1034 | { | |
1035 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1036 | return 0; | |
1037 | ||
1038 | if (!str) | |
1039 | return -EINVAL; | |
1040 | ||
1041 | if (!strcmp(str, "off")) | |
1042 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1043 | else if (!strcmp(str, "flush,nowarn")) | |
1044 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1045 | else if (!strcmp(str, "flush")) | |
1046 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1047 | else if (!strcmp(str, "flush,nosmt")) | |
1048 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1049 | else if (!strcmp(str, "full")) | |
1050 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1051 | else if (!strcmp(str, "full,force")) | |
1052 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | early_param("l1tf", l1tf_cmdline); | |
1057 | ||
73ca9f47 KRW |
1058 | #undef pr_fmt |
1059 | ||
61dc0f55 | 1060 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 1061 | |
b9cfedcd TG |
1062 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1063 | ||
1064 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 1065 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
1066 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1067 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1068 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1069 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1070 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 1071 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
1072 | }; |
1073 | ||
1074 | static ssize_t l1tf_show_state(char *buf) | |
1075 | { | |
1076 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1077 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1078 | ||
3899f7b1 PB |
1079 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1080 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 1081 | sched_smt_active())) { |
3899f7b1 PB |
1082 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1083 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 1084 | } |
3899f7b1 PB |
1085 | |
1086 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1087 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 1088 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
1089 | } |
1090 | #else | |
1091 | static ssize_t l1tf_show_state(char *buf) | |
1092 | { | |
1093 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1094 | } | |
1095 | #endif | |
1096 | ||
2daa53e8 TC |
1097 | static char *stibp_state(void) |
1098 | { | |
4a8d91c8 TC |
1099 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1100 | return ""; | |
1101 | ||
6cd930f0 TG |
1102 | switch (spectre_v2_user) { |
1103 | case SPECTRE_V2_USER_NONE: | |
1104 | return ", STIBP: disabled"; | |
1105 | case SPECTRE_V2_USER_STRICT: | |
1106 | return ", STIBP: forced"; | |
fbed8eca TL |
1107 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
1108 | return ", STIBP: always-on"; | |
ac40ad3b | 1109 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 1110 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 TG |
1111 | if (static_key_enabled(&switch_to_cond_stibp)) |
1112 | return ", STIBP: conditional"; | |
6cd930f0 TG |
1113 | } |
1114 | return ""; | |
2daa53e8 TC |
1115 | } |
1116 | ||
1117 | static char *ibpb_state(void) | |
1118 | { | |
58b2d4c8 | 1119 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
2cdf6a58 | 1120 | if (static_key_enabled(&switch_mm_always_ibpb)) |
58b2d4c8 | 1121 | return ", IBPB: always-on"; |
2cdf6a58 TG |
1122 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1123 | return ", IBPB: conditional"; | |
1124 | return ", IBPB: disabled"; | |
58b2d4c8 TG |
1125 | } |
1126 | return ""; | |
2daa53e8 TC |
1127 | } |
1128 | ||
ace051d5 | 1129 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 1130 | char *buf, unsigned int bug) |
61dc0f55 | 1131 | { |
d2b8fc2d | 1132 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1133 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
1134 | |
1135 | switch (bug) { | |
1136 | case X86_BUG_CPU_MELTDOWN: | |
1137 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1138 | return sprintf(buf, "Mitigation: PTI\n"); | |
1139 | ||
1140 | break; | |
1141 | ||
1142 | case X86_BUG_SPECTRE_V1: | |
1143 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
1144 | ||
1145 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 1146 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 1147 | ibpb_state(), |
d2b8fc2d | 1148 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 1149 | stibp_state(), |
5e2fafd5 | 1150 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
1151 | spectre_v2_module_string()); |
1152 | ||
e63490c8 KRW |
1153 | case X86_BUG_SPEC_STORE_BYPASS: |
1154 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1155 | ||
05516ad8 AK |
1156 | case X86_BUG_L1TF: |
1157 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 1158 | return l1tf_show_state(buf); |
05516ad8 | 1159 | break; |
d2b8fc2d KRW |
1160 | default: |
1161 | break; | |
1162 | } | |
1163 | ||
61dc0f55 TG |
1164 | return sprintf(buf, "Vulnerable\n"); |
1165 | } | |
1166 | ||
d2b8fc2d KRW |
1167 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1168 | { | |
1169 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1170 | } | |
1171 | ||
713f1b95 | 1172 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1173 | { |
d2b8fc2d | 1174 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1175 | } |
1176 | ||
713f1b95 | 1177 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1178 | { |
d2b8fc2d | 1179 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1180 | } |
d7de9182 KRW |
1181 | |
1182 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1183 | { | |
1184 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1185 | } | |
05516ad8 AK |
1186 | |
1187 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1188 | { | |
1189 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1190 | } | |
61dc0f55 | 1191 | #endif |