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KVM: MMU: Fix false flooding when a pte points to page table
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
6aa8b732 19#include "vmx.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
e495606d 29
6aa8b732 30#include <asm/io.h>
3b3be0d1 31#include <asm/desc.h>
6aa8b732 32
6aa8b732
AK		 33MODULE_AUTHOR("Qumranet");
34MODULE_LICENSE("GPL");
35
c7addb90
AK		 36static int bypass_guest_pf = 1;
37module_param(bypass_guest_pf, bool, 0);
38
2384d2b3
SY		 39static int enable_vpid = 1;
40module_param(enable_vpid, bool, 0);
41
4c9fc8ef
AK		 42static int flexpriority_enabled = 1;
43module_param(flexpriority_enabled, bool, 0);
44
1439442c 45static int enable_ept = 1;
d56f546d
SY		 46module_param(enable_ept, bool, 0);
47
a2fa3e9f
GH		 48struct vmcs {
49 u32 revision_id;
50 u32 abort;
51 char data[0];
52};
53
54struct vcpu_vmx {
fb3f0f51 55 struct kvm_vcpu vcpu;
a2fa3e9f 56 int launched;
29bd8a78 57 u8 fail;
1155f76a 58 u32 idt_vectoring_info;
a2fa3e9f
GH		 59 struct kvm_msr_entry *guest_msrs;
60 struct kvm_msr_entry *host_msrs;
61 int nmsrs;
62 int save_nmsrs;
63 int msr_offset_efer;
64#ifdef CONFIG_X86_64
65 int msr_offset_kernel_gs_base;
66#endif
67 struct vmcs *vmcs;
68 struct {
69 int loaded;
70 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 71 int gs_ldt_reload_needed;
72 int fs_reload_needed;
51c6cf66 73 int guest_efer_loaded;
d77c26fc 74 } host_state;
9c8cba37
AK		 75 struct {
76 struct {
77 bool pending;
78 u8 vector;
79 unsigned rip;
80 } irq;
81 } rmode;
2384d2b3 82 int vpid;
a2fa3e9f
GH		 83};
84
85static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
86{
fb3f0f51 87 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 88}
89
b7ebfb05 90static int init_rmode(struct kvm *kvm);
75880a01 91
6aa8b732
AK		 92static DEFINE_PER_CPU(struct vmcs *, vmxarea);
93static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
94
fdef3ad1
HQ		 95static struct page *vmx_io_bitmap_a;
96static struct page *vmx_io_bitmap_b;
25c5f225 97static struct page *vmx_msr_bitmap;
fdef3ad1 98
2384d2b3
SY		 99static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
100static DEFINE_SPINLOCK(vmx_vpid_lock);
101
1c3d14fe 102static struct vmcs_config {
6aa8b732
AK		 103 int size;
104 int order;
105 u32 revision_id;
1c3d14fe
YS		 106 u32 pin_based_exec_ctrl;
107 u32 cpu_based_exec_ctrl;
f78e0e2e 108 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 109 u32 vmexit_ctrl;
110 u32 vmentry_ctrl;
111} vmcs_config;
6aa8b732 112
d56f546d
SY		 113struct vmx_capability {
114 u32 ept;
115 u32 vpid;
116} vmx_capability;
117
6aa8b732
AK		 118#define VMX_SEGMENT_FIELD(seg) \
119 [VCPU_SREG_##seg] = { \
120 .selector = GUEST_##seg##_SELECTOR, \
121 .base = GUEST_##seg##_BASE, \
122 .limit = GUEST_##seg##_LIMIT, \
123 .ar_bytes = GUEST_##seg##_AR_BYTES, \
124 }
125
126static struct kvm_vmx_segment_field {
127 unsigned selector;
128 unsigned base;
129 unsigned limit;
130 unsigned ar_bytes;
131} kvm_vmx_segment_fields[] = {
132 VMX_SEGMENT_FIELD(CS),
133 VMX_SEGMENT_FIELD(DS),
134 VMX_SEGMENT_FIELD(ES),
135 VMX_SEGMENT_FIELD(FS),
136 VMX_SEGMENT_FIELD(GS),
137 VMX_SEGMENT_FIELD(SS),
138 VMX_SEGMENT_FIELD(TR),
139 VMX_SEGMENT_FIELD(LDTR),
140};
141
4d56c8a7
AK		 142/*
143 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
144 * away by decrementing the array size.
145 */
6aa8b732 146static const u32 vmx_msr_index[] = {
05b3e0c2 147#ifdef CONFIG_X86_64
6aa8b732
AK		 148 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
149#endif
150 MSR_EFER, MSR_K6_STAR,
151};
9d8f549d 152#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 153
a2fa3e9f
GH		 154static void load_msrs(struct kvm_msr_entry *e, int n)
155{
156 int i;
157
158 for (i = 0; i < n; ++i)
159 wrmsrl(e[i].index, e[i].data);
160}
161
162static void save_msrs(struct kvm_msr_entry *e, int n)
163{
164 int i;
165
166 for (i = 0; i < n; ++i)
167 rdmsrl(e[i].index, e[i].data);
168}
169
6aa8b732
AK		 170static inline int is_page_fault(u32 intr_info)
171{
172 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
173 INTR_INFO_VALID_MASK)) ==
174 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
175}
176
2ab455cc
AL		 177static inline int is_no_device(u32 intr_info)
178{
179 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
180 INTR_INFO_VALID_MASK)) ==
181 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
182}
183
7aa81cc0
AL		 184static inline int is_invalid_opcode(u32 intr_info)
185{
186 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
187 INTR_INFO_VALID_MASK)) ==
188 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
189}
190
6aa8b732
AK		 191static inline int is_external_interrupt(u32 intr_info)
192{
193 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
194 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
195}
196
25c5f225
SY		 197static inline int cpu_has_vmx_msr_bitmap(void)
198{
199 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
200}
201
6e5d865c
YS		 202static inline int cpu_has_vmx_tpr_shadow(void)
203{
204 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
205}
206
207static inline int vm_need_tpr_shadow(struct kvm *kvm)
208{
209 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
210}
211
f78e0e2e
SY		 212static inline int cpu_has_secondary_exec_ctrls(void)
213{
214 return (vmcs_config.cpu_based_exec_ctrl &
215 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
216}
217
774ead3a 218static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 219{
4c9fc8ef
AK		 220 return flexpriority_enabled
221 && (vmcs_config.cpu_based_2nd_exec_ctrl &
222 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
f78e0e2e
SY		 223}
224
d56f546d
SY		 225static inline int cpu_has_vmx_invept_individual_addr(void)
226{
227 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
228}
229
230static inline int cpu_has_vmx_invept_context(void)
231{
232 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
233}
234
235static inline int cpu_has_vmx_invept_global(void)
236{
237 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
238}
239
240static inline int cpu_has_vmx_ept(void)
241{
242 return (vmcs_config.cpu_based_2nd_exec_ctrl &
243 SECONDARY_EXEC_ENABLE_EPT);
244}
245
246static inline int vm_need_ept(void)
247{
248 return (cpu_has_vmx_ept() && enable_ept);
249}
250
f78e0e2e
SY		 251static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
252{
253 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
254 (irqchip_in_kernel(kvm)));
255}
256
2384d2b3
SY		 257static inline int cpu_has_vmx_vpid(void)
258{
259 return (vmcs_config.cpu_based_2nd_exec_ctrl &
260 SECONDARY_EXEC_ENABLE_VPID);
261}
262
8b9cf98c 263static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 264{
265 int i;
266
a2fa3e9f
GH		 267 for (i = 0; i < vmx->nmsrs; ++i)
268 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 269 return i;
270 return -1;
271}
272
2384d2b3
SY		 273static inline void __invvpid(int ext, u16 vpid, gva_t gva)
274{
275 struct {
276 u64 vpid : 16;
277 u64 rsvd : 48;
278 u64 gva;
279 } operand = { vpid, 0, gva };
280
281 asm volatile (ASM_VMX_INVVPID
282 /* CF==1 or ZF==1 --> rc = -1 */
283 "; ja 1f ; ud2 ; 1:"
284 : : "a"(&operand), "c"(ext) : "cc", "memory");
285}
286
1439442c
SY		 287static inline void __invept(int ext, u64 eptp, gpa_t gpa)
288{
289 struct {
290 u64 eptp, gpa;
291 } operand = {eptp, gpa};
292
293 asm volatile (ASM_VMX_INVEPT
294 /* CF==1 or ZF==1 --> rc = -1 */
295 "; ja 1f ; ud2 ; 1:\n"
296 : : "a" (&operand), "c" (ext) : "cc", "memory");
297}
298
8b9cf98c 299static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 300{
301 int i;
302
8b9cf98c 303 i = __find_msr_index(vmx, msr);
a75beee6 304 if (i >= 0)
a2fa3e9f 305 return &vmx->guest_msrs[i];
8b6d44c7 306 return NULL;
7725f0ba
AK		 307}
308
6aa8b732
AK		 309static void vmcs_clear(struct vmcs *vmcs)
310{
311 u64 phys_addr = __pa(vmcs);
312 u8 error;
313
314 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
315 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
316 : "cc", "memory");
317 if (error)
318 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
319 vmcs, phys_addr);
320}
321
322static void __vcpu_clear(void *arg)
323{
8b9cf98c 324 struct vcpu_vmx *vmx = arg;
d3b2c338 325 int cpu = raw_smp_processor_id();
6aa8b732 326
8b9cf98c 327 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 328 vmcs_clear(vmx->vmcs);
329 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 330 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 331 rdtscll(vmx->vcpu.arch.host_tsc);
6aa8b732
AK		 332}
333
8b9cf98c 334static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 335{
eae5ecb5
AK		 336 if (vmx->vcpu.cpu == -1)
337 return;
8691e5a8 338 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8b9cf98c 339 vmx->launched = 0;
8d0be2b3
AK		 340}
341
2384d2b3
SY		 342static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
343{
344 if (vmx->vpid == 0)
345 return;
346
347 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
348}
349
1439442c
SY		 350static inline void ept_sync_global(void)
351{
352 if (cpu_has_vmx_invept_global())
353 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
354}
355
356static inline void ept_sync_context(u64 eptp)
357{
358 if (vm_need_ept()) {
359 if (cpu_has_vmx_invept_context())
360 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
361 else
362 ept_sync_global();
363 }
364}
365
366static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
367{
368 if (vm_need_ept()) {
369 if (cpu_has_vmx_invept_individual_addr())
370 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
371 eptp, gpa);
372 else
373 ept_sync_context(eptp);
374 }
375}
376
6aa8b732
AK		 377static unsigned long vmcs_readl(unsigned long field)
378{
379 unsigned long value;
380
381 asm volatile (ASM_VMX_VMREAD_RDX_RAX
382 : "=a"(value) : "d"(field) : "cc");
383 return value;
384}
385
386static u16 vmcs_read16(unsigned long field)
387{
388 return vmcs_readl(field);
389}
390
391static u32 vmcs_read32(unsigned long field)
392{
393 return vmcs_readl(field);
394}
395
396static u64 vmcs_read64(unsigned long field)
397{
05b3e0c2 398#ifdef CONFIG_X86_64
6aa8b732
AK		 399 return vmcs_readl(field);
400#else
401 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
402#endif
403}
404
e52de1b8
AK		 405static noinline void vmwrite_error(unsigned long field, unsigned long value)
406{
407 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
408 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
409 dump_stack();
410}
411
6aa8b732
AK		 412static void vmcs_writel(unsigned long field, unsigned long value)
413{
414 u8 error;
415
416 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
d77c26fc 417 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 418 if (unlikely(error))
419 vmwrite_error(field, value);
6aa8b732
AK		 420}
421
422static void vmcs_write16(unsigned long field, u16 value)
423{
424 vmcs_writel(field, value);
425}
426
427static void vmcs_write32(unsigned long field, u32 value)
428{
429 vmcs_writel(field, value);
430}
431
432static void vmcs_write64(unsigned long field, u64 value)
433{
6aa8b732 434 vmcs_writel(field, value);
7682f2d0 435#ifndef CONFIG_X86_64
6aa8b732
AK		 436 asm volatile ("");
437 vmcs_writel(field+1, value >> 32);
438#endif
439}
440
2ab455cc
AL		 441static void vmcs_clear_bits(unsigned long field, u32 mask)
442{
443 vmcs_writel(field, vmcs_readl(field) & ~mask);
444}
445
446static void vmcs_set_bits(unsigned long field, u32 mask)
447{
448 vmcs_writel(field, vmcs_readl(field) | mask);
449}
450
abd3f2d6
AK		 451static void update_exception_bitmap(struct kvm_vcpu *vcpu)
452{
453 u32 eb;
454
7aa81cc0 455 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 456 if (!vcpu->fpu_active)
457 eb |= 1u << NM_VECTOR;
458 if (vcpu->guest_debug.enabled)
459 eb |= 1u << 1;
ad312c7c 460 if (vcpu->arch.rmode.active)
abd3f2d6 461 eb = ~0;
1439442c
SY		 462 if (vm_need_ept())
463 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 464 vmcs_write32(EXCEPTION_BITMAP, eb);
465}
466
33ed6329
AK		 467static void reload_tss(void)
468{
33ed6329
AK		 469 /*
470 * VT restores TR but not its size. Useless.
471 */
472 struct descriptor_table gdt;
a5f61300 473 struct desc_struct *descs;
33ed6329
AK		 474
475 get_gdt(&gdt);
476 descs = (void *)gdt.base;
477 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
478 load_TR_desc();
33ed6329
AK		 479}
480
8b9cf98c 481static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 482{
a2fa3e9f 483 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 484 u64 host_efer = vmx->host_msrs[efer_offset].data;
485 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
486 u64 ignore_bits;
487
488 if (efer_offset < 0)
489 return;
490 /*
491 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
492 * outside long mode
493 */
494 ignore_bits = EFER_NX | EFER_SCE;
495#ifdef CONFIG_X86_64
496 ignore_bits |= EFER_LMA | EFER_LME;
497 /* SCE is meaningful only in long mode on Intel */
498 if (guest_efer & EFER_LMA)
499 ignore_bits &= ~(u64)EFER_SCE;
500#endif
501 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
502 return;
2cc51560 503
51c6cf66
AK		 504 vmx->host_state.guest_efer_loaded = 1;
505 guest_efer &= ~ignore_bits;
506 guest_efer |= host_efer & ignore_bits;
507 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 508 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 509}
510
51c6cf66
AK		 511static void reload_host_efer(struct vcpu_vmx *vmx)
512{
513 if (vmx->host_state.guest_efer_loaded) {
514 vmx->host_state.guest_efer_loaded = 0;
515 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
516 }
517}
518
04d2cc77 519static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 520{
04d2cc77
AK		 521 struct vcpu_vmx *vmx = to_vmx(vcpu);
522
a2fa3e9f 523 if (vmx->host_state.loaded)
33ed6329
AK		 524 return;
525
a2fa3e9f 526 vmx->host_state.loaded = 1;
33ed6329
AK		 527 /*
528 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
529 * allow segment selectors with cpl > 0 or ti == 1.
530 */
a2fa3e9f 531 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 532 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 533 vmx->host_state.fs_sel = read_fs();
152d3f2f 534 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 535 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 536 vmx->host_state.fs_reload_needed = 0;
537 } else {
33ed6329 538 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 539 vmx->host_state.fs_reload_needed = 1;
33ed6329 540 }
a2fa3e9f
GH		 541 vmx->host_state.gs_sel = read_gs();
542 if (!(vmx->host_state.gs_sel & 7))
543 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 544 else {
545 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 546 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 547 }
548
549#ifdef CONFIG_X86_64
550 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
551 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
552#else
a2fa3e9f
GH		 553 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
554 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 555#endif
707c0874
AK		 556
557#ifdef CONFIG_X86_64
d77c26fc 558 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 559 save_msrs(vmx->host_msrs +
560 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 561
707c0874 562#endif
a2fa3e9f 563 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 564 load_transition_efer(vmx);
33ed6329
AK		 565}
566
a9b21b62 567static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 568{
15ad7146 569 unsigned long flags;
33ed6329 570
a2fa3e9f 571 if (!vmx->host_state.loaded)
33ed6329
AK		 572 return;
573
e1beb1d3 574 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 575 vmx->host_state.loaded = 0;
152d3f2f 576 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 577 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 578 if (vmx->host_state.gs_ldt_reload_needed) {
579 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 580 /*
581 * If we have to reload gs, we must take care to
582 * preserve our gs base.
583 */
15ad7146 584 local_irq_save(flags);
a2fa3e9f 585 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 586#ifdef CONFIG_X86_64
587 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
588#endif
15ad7146 589 local_irq_restore(flags);
33ed6329 590 }
152d3f2f 591 reload_tss();
a2fa3e9f
GH		 592 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
593 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 594 reload_host_efer(vmx);
33ed6329
AK		 595}
596
a9b21b62
AK		 597static void vmx_load_host_state(struct vcpu_vmx *vmx)
598{
599 preempt_disable();
600 __vmx_load_host_state(vmx);
601 preempt_enable();
602}
603
6aa8b732
AK		 604/*
605 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
606 * vcpu mutex is already taken.
607 */
15ad7146 608static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 609{
a2fa3e9f
GH		 610 struct vcpu_vmx *vmx = to_vmx(vcpu);
611 u64 phys_addr = __pa(vmx->vmcs);
019960ae 612 u64 tsc_this, delta, new_offset;
6aa8b732 613
a3d7f85f 614 if (vcpu->cpu != cpu) {
8b9cf98c 615 vcpu_clear(vmx);
2f599714 616 kvm_migrate_timers(vcpu);
2384d2b3 617 vpid_sync_vcpu_all(vmx);
a3d7f85f 618 }
6aa8b732 619
a2fa3e9f 620 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 621 u8 error;
622
a2fa3e9f 623 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 624 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
625 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
626 : "cc");
627 if (error)
628 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 629 vmx->vmcs, phys_addr);
6aa8b732
AK		 630 }
631
632 if (vcpu->cpu != cpu) {
633 struct descriptor_table dt;
634 unsigned long sysenter_esp;
635
636 vcpu->cpu = cpu;
637 /*
638 * Linux uses per-cpu TSS and GDT, so set these when switching
639 * processors.
640 */
641 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
642 get_gdt(&dt);
643 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
644
645 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
646 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 647
648 /*
649 * Make sure the time stamp counter is monotonous.
650 */
651 rdtscll(tsc_this);
019960ae
AK		 652 if (tsc_this < vcpu->arch.host_tsc) {
653 delta = vcpu->arch.host_tsc - tsc_this;
654 new_offset = vmcs_read64(TSC_OFFSET) + delta;
655 vmcs_write64(TSC_OFFSET, new_offset);
656 }
6aa8b732 657 }
6aa8b732
AK		 658}
659
660static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
661{
a9b21b62 662 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 663}
664
5fd86fcf
AK		 665static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
666{
667 if (vcpu->fpu_active)
668 return;
669 vcpu->fpu_active = 1;
707d92fa 670 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 671 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 672 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 673 update_exception_bitmap(vcpu);
674}
675
676static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
677{
678 if (!vcpu->fpu_active)
679 return;
680 vcpu->fpu_active = 0;
707d92fa 681 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 682 update_exception_bitmap(vcpu);
683}
684
774c47f1
AK		 685static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
686{
8b9cf98c 687 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 688}
689
6aa8b732
AK		 690static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
691{
692 return vmcs_readl(GUEST_RFLAGS);
693}
694
695static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
696{
ad312c7c 697 if (vcpu->arch.rmode.active)
053de044 698 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 699 vmcs_writel(GUEST_RFLAGS, rflags);
700}
701
702static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
703{
704 unsigned long rip;
705 u32 interruptibility;
706
707 rip = vmcs_readl(GUEST_RIP);
708 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
709 vmcs_writel(GUEST_RIP, rip);
710
711 /*
712 * We emulated an instruction, so temporary interrupt blocking
713 * should be removed, if set.
714 */
715 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
716 if (interruptibility & 3)
717 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
718 interruptibility & ~3);
ad312c7c 719 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 720}
721
298101da
AK		 722static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
723 bool has_error_code, u32 error_code)
724{
725 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
726 nr | INTR_TYPE_EXCEPTION
2e11384c 727 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
298101da
AK		 728 | INTR_INFO_VALID_MASK);
729 if (has_error_code)
730 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
731}
732
733static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
734{
735 struct vcpu_vmx *vmx = to_vmx(vcpu);
736
737 return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
738}
739
a75beee6
ED		 740/*
741 * Swap MSR entry in host/guest MSR entry array.
742 */
54e11fa1 743#ifdef CONFIG_X86_64
8b9cf98c 744static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 745{
a2fa3e9f
GH		 746 struct kvm_msr_entry tmp;
747
748 tmp = vmx->guest_msrs[to];
749 vmx->guest_msrs[to] = vmx->guest_msrs[from];
750 vmx->guest_msrs[from] = tmp;
751 tmp = vmx->host_msrs[to];
752 vmx->host_msrs[to] = vmx->host_msrs[from];
753 vmx->host_msrs[from] = tmp;
a75beee6 754}
54e11fa1 755#endif
a75beee6 756
e38aea3e
AK		 757/*
758 * Set up the vmcs to automatically save and restore system
759 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
760 * mode, as fiddling with msrs is very expensive.
761 */
8b9cf98c 762static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 763{
2cc51560 764 int save_nmsrs;
e38aea3e 765
33f9c505 766 vmx_load_host_state(vmx);
a75beee6
ED		 767 save_nmsrs = 0;
768#ifdef CONFIG_X86_64
8b9cf98c 769 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 770 int index;
771
8b9cf98c 772 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 773 if (index >= 0)
8b9cf98c
RR		 774 move_msr_up(vmx, index, save_nmsrs++);
775 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 776 if (index >= 0)
8b9cf98c
RR		 777 move_msr_up(vmx, index, save_nmsrs++);
778 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 779 if (index >= 0)
8b9cf98c
RR		 780 move_msr_up(vmx, index, save_nmsrs++);
781 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 782 if (index >= 0)
8b9cf98c 783 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 784 /*
785 * MSR_K6_STAR is only needed on long mode guests, and only
786 * if efer.sce is enabled.
787 */
8b9cf98c 788 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 789 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 790 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 791 }
792#endif
a2fa3e9f 793 vmx->save_nmsrs = save_nmsrs;
e38aea3e 794
4d56c8a7 795#ifdef CONFIG_X86_64
a2fa3e9f 796 vmx->msr_offset_kernel_gs_base =
8b9cf98c 797 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 798#endif
8b9cf98c 799 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 800}
801
6aa8b732
AK		 802/*
803 * reads and returns guest's timestamp counter "register"
804 * guest_tsc = host_tsc + tsc_offset -- 21.3
805 */
806static u64 guest_read_tsc(void)
807{
808 u64 host_tsc, tsc_offset;
809
810 rdtscll(host_tsc);
811 tsc_offset = vmcs_read64(TSC_OFFSET);
812 return host_tsc + tsc_offset;
813}
814
815/*
816 * writes 'guest_tsc' into guest's timestamp counter "register"
817 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
818 */
819static void guest_write_tsc(u64 guest_tsc)
820{
821 u64 host_tsc;
822
823 rdtscll(host_tsc);
824 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
825}
826
6aa8b732
AK		 827/*
828 * Reads an msr value (of 'msr_index') into 'pdata'.
829 * Returns 0 on success, non-0 otherwise.
830 * Assumes vcpu_load() was already called.
831 */
832static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
833{
834 u64 data;
a2fa3e9f 835 struct kvm_msr_entry *msr;
6aa8b732
AK		 836
837 if (!pdata) {
838 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
839 return -EINVAL;
840 }
841
842 switch (msr_index) {
05b3e0c2 843#ifdef CONFIG_X86_64
6aa8b732
AK		 844 case MSR_FS_BASE:
845 data = vmcs_readl(GUEST_FS_BASE);
846 break;
847 case MSR_GS_BASE:
848 data = vmcs_readl(GUEST_GS_BASE);
849 break;
850 case MSR_EFER:
3bab1f5d 851 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 852#endif
853 case MSR_IA32_TIME_STAMP_COUNTER:
854 data = guest_read_tsc();
855 break;
856 case MSR_IA32_SYSENTER_CS:
857 data = vmcs_read32(GUEST_SYSENTER_CS);
858 break;
859 case MSR_IA32_SYSENTER_EIP:
f5b42c33 860 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 861 break;
862 case MSR_IA32_SYSENTER_ESP:
f5b42c33 863 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 864 break;
6aa8b732 865 default:
8b9cf98c 866 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 867 if (msr) {
868 data = msr->data;
869 break;
6aa8b732 870 }
3bab1f5d 871 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 872 }
873
874 *pdata = data;
875 return 0;
876}
877
878/*
879 * Writes msr value into into the appropriate "register".
880 * Returns 0 on success, non-0 otherwise.
881 * Assumes vcpu_load() was already called.
882 */
883static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
884{
a2fa3e9f
GH		 885 struct vcpu_vmx *vmx = to_vmx(vcpu);
886 struct kvm_msr_entry *msr;
2cc51560
ED		 887 int ret = 0;
888
6aa8b732 889 switch (msr_index) {
05b3e0c2 890#ifdef CONFIG_X86_64
3bab1f5d 891 case MSR_EFER:
a9b21b62 892 vmx_load_host_state(vmx);
2cc51560 893 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 894 break;
6aa8b732
AK		 895 case MSR_FS_BASE:
896 vmcs_writel(GUEST_FS_BASE, data);
897 break;
898 case MSR_GS_BASE:
899 vmcs_writel(GUEST_GS_BASE, data);
900 break;
901#endif
902 case MSR_IA32_SYSENTER_CS:
903 vmcs_write32(GUEST_SYSENTER_CS, data);
904 break;
905 case MSR_IA32_SYSENTER_EIP:
f5b42c33 906 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 907 break;
908 case MSR_IA32_SYSENTER_ESP:
f5b42c33 909 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 910 break;
d27d4aca 911 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 912 guest_write_tsc(data);
913 break;
6aa8b732 914 default:
a9b21b62 915 vmx_load_host_state(vmx);
8b9cf98c 916 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 917 if (msr) {
918 msr->data = data;
919 break;
6aa8b732 920 }
2cc51560 921 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 922 }
923
2cc51560 924 return ret;
6aa8b732
AK		 925}
926
927/*
928 * Sync the rsp and rip registers into the vcpu structure. This allows
ad312c7c 929 * registers to be accessed by indexing vcpu->arch.regs.
6aa8b732
AK		 930 */
931static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
932{
ad312c7c
ZX		 933 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
934 vcpu->arch.rip = vmcs_readl(GUEST_RIP);
6aa8b732
AK		 935}
936
937/*
938 * Syncs rsp and rip back into the vmcs. Should be called after possible
939 * modification.
940 */
941static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
942{
ad312c7c
ZX		 943 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
944 vmcs_writel(GUEST_RIP, vcpu->arch.rip);
6aa8b732
AK		 945}
946
947static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
948{
949 unsigned long dr7 = 0x400;
6aa8b732
AK		 950 int old_singlestep;
951
6aa8b732
AK		 952 old_singlestep = vcpu->guest_debug.singlestep;
953
954 vcpu->guest_debug.enabled = dbg->enabled;
955 if (vcpu->guest_debug.enabled) {
956 int i;
957
958 dr7 |= 0x200; /* exact */
959 for (i = 0; i < 4; ++i) {
960 if (!dbg->breakpoints[i].enabled)
961 continue;
962 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
963 dr7 |= 2 << (i*2); /* global enable */
964 dr7 |= 0 << (i*4+16); /* execution breakpoint */
965 }
966
6aa8b732 967 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 968 } else
6aa8b732 969 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 970
971 if (old_singlestep && !vcpu->guest_debug.singlestep) {
972 unsigned long flags;
973
974 flags = vmcs_readl(GUEST_RFLAGS);
975 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
976 vmcs_writel(GUEST_RFLAGS, flags);
977 }
978
abd3f2d6 979 update_exception_bitmap(vcpu);
6aa8b732
AK		 980 vmcs_writel(GUEST_DR7, dr7);
981
982 return 0;
983}
984
2a8067f1
ED		 985static int vmx_get_irq(struct kvm_vcpu *vcpu)
986{
1155f76a 987 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a8067f1
ED		 988 u32 idtv_info_field;
989
1155f76a 990 idtv_info_field = vmx->idt_vectoring_info;
2a8067f1
ED		 991 if (idtv_info_field & INTR_INFO_VALID_MASK) {
992 if (is_external_interrupt(idtv_info_field))
993 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
994 else
d77c26fc 995 printk(KERN_DEBUG "pending exception: not handled yet\n");
2a8067f1
ED		 996 }
997 return -1;
998}
999
6aa8b732
AK		 1000static __init int cpu_has_kvm_support(void)
1001{
1002 unsigned long ecx = cpuid_ecx(1);
1003 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1004}
1005
1006static __init int vmx_disabled_by_bios(void)
1007{
1008 u64 msr;
1009
1010 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 1011 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1012 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1013 == MSR_IA32_FEATURE_CONTROL_LOCKED;
1014 /* locked but not enabled */
6aa8b732
AK		 1015}
1016
774c47f1 1017static void hardware_enable(void *garbage)
6aa8b732
AK		 1018{
1019 int cpu = raw_smp_processor_id();
1020 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1021 u64 old;
1022
1023 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 1024 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1025 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1026 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
1027 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1028 /* enable and lock */
62b3ffb8
YS		 1029 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1030 MSR_IA32_FEATURE_CONTROL_LOCKED |
1031 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1032 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 1033 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
1034 : "memory", "cc");
1035}
1036
1037static void hardware_disable(void *garbage)
1038{
1039 asm volatile (ASM_VMX_VMXOFF : : : "cc");
e693d71b 1040 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1041}
1042
1c3d14fe 1043static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1044 u32 msr, u32 *result)
1c3d14fe
YS		 1045{
1046 u32 vmx_msr_low, vmx_msr_high;
1047 u32 ctl = ctl_min | ctl_opt;
1048
1049 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1050
1051 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1052 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1053
1054 /* Ensure minimum (required) set of control bits are supported. */
1055 if (ctl_min & ~ctl)
002c7f7c 1056 return -EIO;
1c3d14fe
YS		 1057
1058 *result = ctl;
1059 return 0;
1060}
1061
002c7f7c 1062static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1063{
1064 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1065 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1066 u32 _pin_based_exec_control = 0;
1067 u32 _cpu_based_exec_control = 0;
f78e0e2e 1068 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1069 u32 _vmexit_control = 0;
1070 u32 _vmentry_control = 0;
1071
1072 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1073 opt = 0;
1074 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1075 &_pin_based_exec_control) < 0)
002c7f7c 1076 return -EIO;
1c3d14fe
YS		 1077
1078 min = CPU_BASED_HLT_EXITING |
1079#ifdef CONFIG_X86_64
1080 CPU_BASED_CR8_LOAD_EXITING |
1081 CPU_BASED_CR8_STORE_EXITING |
1082#endif
d56f546d
SY		 1083 CPU_BASED_CR3_LOAD_EXITING |
1084 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1085 CPU_BASED_USE_IO_BITMAPS |
1086 CPU_BASED_MOV_DR_EXITING |
1087 CPU_BASED_USE_TSC_OFFSETING;
f78e0e2e 1088 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1089 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1090 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1091 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1092 &_cpu_based_exec_control) < 0)
002c7f7c 1093 return -EIO;
6e5d865c
YS		 1094#ifdef CONFIG_X86_64
1095 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1096 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1097 ~CPU_BASED_CR8_STORE_EXITING;
1098#endif
f78e0e2e 1099 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1100 min2 = 0;
1101 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1102 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1103 SECONDARY_EXEC_ENABLE_VPID |
1104 SECONDARY_EXEC_ENABLE_EPT;
1105 if (adjust_vmx_controls(min2, opt2,
1106 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1107 &_cpu_based_2nd_exec_control) < 0)
1108 return -EIO;
1109 }
1110#ifndef CONFIG_X86_64
1111 if (!(_cpu_based_2nd_exec_control &
1112 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1113 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1114#endif
d56f546d
SY		 1115 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1116 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1117 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1118 CPU_BASED_CR3_STORE_EXITING);
1119 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1120 &_cpu_based_exec_control) < 0)
1121 return -EIO;
1122 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1123 vmx_capability.ept, vmx_capability.vpid);
1124 }
1c3d14fe
YS		 1125
1126 min = 0;
1127#ifdef CONFIG_X86_64
1128 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1129#endif
1130 opt = 0;
1131 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1132 &_vmexit_control) < 0)
002c7f7c 1133 return -EIO;
1c3d14fe
YS		 1134
1135 min = opt = 0;
1136 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1137 &_vmentry_control) < 0)
002c7f7c 1138 return -EIO;
6aa8b732 1139
c68876fd 1140 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1141
1142 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1143 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1144 return -EIO;
1c3d14fe
YS		 1145
1146#ifdef CONFIG_X86_64
1147 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1148 if (vmx_msr_high & (1u<<16))
002c7f7c 1149 return -EIO;
1c3d14fe
YS		 1150#endif
1151
1152 /* Require Write-Back (WB) memory type for VMCS accesses. */
1153 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1154 return -EIO;
1c3d14fe 1155
002c7f7c
YS		 1156 vmcs_conf->size = vmx_msr_high & 0x1fff;
1157 vmcs_conf->order = get_order(vmcs_config.size);
1158 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1159
002c7f7c
YS		 1160 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1161 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1162 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1163 vmcs_conf->vmexit_ctrl = _vmexit_control;
1164 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1165
1166 return 0;
c68876fd 1167}
6aa8b732
AK		 1168
1169static struct vmcs *alloc_vmcs_cpu(int cpu)
1170{
1171 int node = cpu_to_node(cpu);
1172 struct page *pages;
1173 struct vmcs *vmcs;
1174
1c3d14fe 1175 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1176 if (!pages)
1177 return NULL;
1178 vmcs = page_address(pages);
1c3d14fe
YS		 1179 memset(vmcs, 0, vmcs_config.size);
1180 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1181 return vmcs;
1182}
1183
1184static struct vmcs *alloc_vmcs(void)
1185{
d3b2c338 1186 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1187}
1188
1189static void free_vmcs(struct vmcs *vmcs)
1190{
1c3d14fe 1191 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1192}
1193
39959588 1194static void free_kvm_area(void)
6aa8b732
AK		 1195{
1196 int cpu;
1197
1198 for_each_online_cpu(cpu)
1199 free_vmcs(per_cpu(vmxarea, cpu));
1200}
1201
6aa8b732
AK		 1202static __init int alloc_kvm_area(void)
1203{
1204 int cpu;
1205
1206 for_each_online_cpu(cpu) {
1207 struct vmcs *vmcs;
1208
1209 vmcs = alloc_vmcs_cpu(cpu);
1210 if (!vmcs) {
1211 free_kvm_area();
1212 return -ENOMEM;
1213 }
1214
1215 per_cpu(vmxarea, cpu) = vmcs;
1216 }
1217 return 0;
1218}
1219
1220static __init int hardware_setup(void)
1221{
002c7f7c
YS		 1222 if (setup_vmcs_config(&vmcs_config) < 0)
1223 return -EIO;
50a37eb4
JR		 1224
1225 if (boot_cpu_has(X86_FEATURE_NX))
1226 kvm_enable_efer_bits(EFER_NX);
1227
6aa8b732
AK		 1228 return alloc_kvm_area();
1229}
1230
1231static __exit void hardware_unsetup(void)
1232{
1233 free_kvm_area();
1234}
1235
6aa8b732
AK		 1236static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1237{
1238 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1239
6af11b9e 1240 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1241 vmcs_write16(sf->selector, save->selector);
1242 vmcs_writel(sf->base, save->base);
1243 vmcs_write32(sf->limit, save->limit);
1244 vmcs_write32(sf->ar_bytes, save->ar);
1245 } else {
1246 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1247 << AR_DPL_SHIFT;
1248 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1249 }
1250}
1251
1252static void enter_pmode(struct kvm_vcpu *vcpu)
1253{
1254 unsigned long flags;
1255
ad312c7c 1256 vcpu->arch.rmode.active = 0;
6aa8b732 1257
ad312c7c
ZX		 1258 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1259 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1260 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1261
1262 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1263 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1264 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1265 vmcs_writel(GUEST_RFLAGS, flags);
1266
66aee91a
RR		 1267 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1268 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1269
1270 update_exception_bitmap(vcpu);
1271
ad312c7c
ZX		 1272 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1273 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1274 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1275 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1276
1277 vmcs_write16(GUEST_SS_SELECTOR, 0);
1278 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1279
1280 vmcs_write16(GUEST_CS_SELECTOR,
1281 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1282 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1283}
1284
d77c26fc 1285static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1286{
bfc6d222 1287 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1288 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1289 kvm->memslots[0].npages - 3;
1290 return base_gfn << PAGE_SHIFT;
1291 }
bfc6d222 1292 return kvm->arch.tss_addr;
6aa8b732
AK		 1293}
1294
1295static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1296{
1297 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1298
1299 save->selector = vmcs_read16(sf->selector);
1300 save->base = vmcs_readl(sf->base);
1301 save->limit = vmcs_read32(sf->limit);
1302 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1303 vmcs_write16(sf->selector, save->base >> 4);
1304 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1305 vmcs_write32(sf->limit, 0xffff);
1306 vmcs_write32(sf->ar_bytes, 0xf3);
1307}
1308
1309static void enter_rmode(struct kvm_vcpu *vcpu)
1310{
1311 unsigned long flags;
1312
ad312c7c 1313 vcpu->arch.rmode.active = 1;
6aa8b732 1314
ad312c7c 1315 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1316 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1317
ad312c7c 1318 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1319 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1320
ad312c7c 1321 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1322 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1323
1324 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1325 vcpu->arch.rmode.save_iopl
1326 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1327
053de044 1328 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1329
1330 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1331 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1332 update_exception_bitmap(vcpu);
1333
1334 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1335 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1336 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1337
1338 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1339 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1340 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1341 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1342 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1343
ad312c7c
ZX		 1344 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1345 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1346 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1347 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1348
8668a3c4 1349 kvm_mmu_reset_context(vcpu);
b7ebfb05 1350 init_rmode(vcpu->kvm);
6aa8b732
AK		 1351}
1352
05b3e0c2 1353#ifdef CONFIG_X86_64
6aa8b732
AK		 1354
1355static void enter_lmode(struct kvm_vcpu *vcpu)
1356{
1357 u32 guest_tr_ar;
1358
1359 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1360 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1361 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1362 __func__);
6aa8b732
AK		 1363 vmcs_write32(GUEST_TR_AR_BYTES,
1364 (guest_tr_ar & ~AR_TYPE_MASK)
1365 | AR_TYPE_BUSY_64_TSS);
1366 }
1367
ad312c7c 1368 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1369
8b9cf98c 1370 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1371 vmcs_write32(VM_ENTRY_CONTROLS,
1372 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1373 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1374}
1375
1376static void exit_lmode(struct kvm_vcpu *vcpu)
1377{
ad312c7c 1378 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1379
1380 vmcs_write32(VM_ENTRY_CONTROLS,
1381 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1382 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1383}
1384
1385#endif
1386
2384d2b3
SY		 1387static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1388{
1389 vpid_sync_vcpu_all(to_vmx(vcpu));
1390}
1391
25c4c276 1392static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1393{
ad312c7c
ZX		 1394 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1395 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1396}
1397
1439442c
SY		 1398static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1399{
1400 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1401 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1402 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1403 return;
1404 }
1405 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1406 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1407 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1408 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1409 }
1410}
1411
1412static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1413
1414static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1415 unsigned long cr0,
1416 struct kvm_vcpu *vcpu)
1417{
1418 if (!(cr0 & X86_CR0_PG)) {
1419 /* From paging/starting to nonpaging */
1420 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1421 vmcs_config.cpu_based_exec_ctrl |
1422 (CPU_BASED_CR3_LOAD_EXITING |
1423 CPU_BASED_CR3_STORE_EXITING));
1424 vcpu->arch.cr0 = cr0;
1425 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1426 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1427 *hw_cr0 &= ~X86_CR0_WP;
1428 } else if (!is_paging(vcpu)) {
1429 /* From nonpaging to paging */
1430 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1431 vmcs_config.cpu_based_exec_ctrl &
1432 ~(CPU_BASED_CR3_LOAD_EXITING |
1433 CPU_BASED_CR3_STORE_EXITING));
1434 vcpu->arch.cr0 = cr0;
1435 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1436 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1437 *hw_cr0 &= ~X86_CR0_WP;
1438 }
1439}
1440
1441static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1442 struct kvm_vcpu *vcpu)
1443{
1444 if (!is_paging(vcpu)) {
1445 *hw_cr4 &= ~X86_CR4_PAE;
1446 *hw_cr4 |= X86_CR4_PSE;
1447 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1448 *hw_cr4 &= ~X86_CR4_PAE;
1449}
1450
6aa8b732
AK		 1451static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1452{
1439442c
SY		 1453 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1454 KVM_VM_CR0_ALWAYS_ON;
1455
5fd86fcf
AK		 1456 vmx_fpu_deactivate(vcpu);
1457
ad312c7c 1458 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1459 enter_pmode(vcpu);
1460
ad312c7c 1461 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1462 enter_rmode(vcpu);
1463
05b3e0c2 1464#ifdef CONFIG_X86_64
ad312c7c 1465 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1466 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1467 enter_lmode(vcpu);
707d92fa 1468 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1469 exit_lmode(vcpu);
1470 }
1471#endif
1472
1439442c
SY		 1473 if (vm_need_ept())
1474 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1475
6aa8b732 1476 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1477 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1478 vcpu->arch.cr0 = cr0;
5fd86fcf 1479
707d92fa 1480 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1481 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1482}
1483
1439442c
SY		 1484static u64 construct_eptp(unsigned long root_hpa)
1485{
1486 u64 eptp;
1487
1488 /* TODO write the value reading from MSR */
1489 eptp = VMX_EPT_DEFAULT_MT |
1490 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1491 eptp |= (root_hpa & PAGE_MASK);
1492
1493 return eptp;
1494}
1495
6aa8b732
AK		 1496static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1497{
1439442c
SY		 1498 unsigned long guest_cr3;
1499 u64 eptp;
1500
1501 guest_cr3 = cr3;
1502 if (vm_need_ept()) {
1503 eptp = construct_eptp(cr3);
1504 vmcs_write64(EPT_POINTER, eptp);
1505 ept_sync_context(eptp);
1506 ept_load_pdptrs(vcpu);
1507 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1508 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1509 }
1510
2384d2b3 1511 vmx_flush_tlb(vcpu);
1439442c 1512 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1513 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1514 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1515}
1516
1517static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1518{
1439442c
SY		 1519 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1520 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1521
ad312c7c 1522 vcpu->arch.cr4 = cr4;
1439442c
SY		 1523 if (vm_need_ept())
1524 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1525
1526 vmcs_writel(CR4_READ_SHADOW, cr4);
1527 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1528}
1529
6aa8b732
AK		 1530static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1531{
8b9cf98c
RR		 1532 struct vcpu_vmx *vmx = to_vmx(vcpu);
1533 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1534
ad312c7c 1535 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1536 if (!msr)
1537 return;
6aa8b732
AK		 1538 if (efer & EFER_LMA) {
1539 vmcs_write32(VM_ENTRY_CONTROLS,
1540 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1541 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1542 msr->data = efer;
1543
1544 } else {
1545 vmcs_write32(VM_ENTRY_CONTROLS,
1546 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1547 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1548
1549 msr->data = efer & ~EFER_LME;
1550 }
8b9cf98c 1551 setup_msrs(vmx);
6aa8b732
AK		 1552}
1553
6aa8b732
AK		 1554static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1555{
1556 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1557
1558 return vmcs_readl(sf->base);
1559}
1560
1561static void vmx_get_segment(struct kvm_vcpu *vcpu,
1562 struct kvm_segment *var, int seg)
1563{
1564 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1565 u32 ar;
1566
1567 var->base = vmcs_readl(sf->base);
1568 var->limit = vmcs_read32(sf->limit);
1569 var->selector = vmcs_read16(sf->selector);
1570 ar = vmcs_read32(sf->ar_bytes);
1571 if (ar & AR_UNUSABLE_MASK)
1572 ar = 0;
1573 var->type = ar & 15;
1574 var->s = (ar >> 4) & 1;
1575 var->dpl = (ar >> 5) & 3;
1576 var->present = (ar >> 7) & 1;
1577 var->avl = (ar >> 12) & 1;
1578 var->l = (ar >> 13) & 1;
1579 var->db = (ar >> 14) & 1;
1580 var->g = (ar >> 15) & 1;
1581 var->unusable = (ar >> 16) & 1;
1582}
1583
2e4d2653
IE		 1584static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1585{
1586 struct kvm_segment kvm_seg;
1587
1588 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1589 return 0;
1590
1591 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1592 return 3;
1593
1594 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1595 return kvm_seg.selector & 3;
1596}
1597
653e3108 1598static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1599{
6aa8b732
AK		 1600 u32 ar;
1601
653e3108 1602 if (var->unusable)
6aa8b732
AK		 1603 ar = 1 << 16;
1604 else {
1605 ar = var->type & 15;
1606 ar |= (var->s & 1) << 4;
1607 ar |= (var->dpl & 3) << 5;
1608 ar |= (var->present & 1) << 7;
1609 ar |= (var->avl & 1) << 12;
1610 ar |= (var->l & 1) << 13;
1611 ar |= (var->db & 1) << 14;
1612 ar |= (var->g & 1) << 15;
1613 }
f7fbf1fd
UL		 1614 if (ar == 0) /* a 0 value means unusable */
1615 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1616
1617 return ar;
1618}
1619
1620static void vmx_set_segment(struct kvm_vcpu *vcpu,
1621 struct kvm_segment *var, int seg)
1622{
1623 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1624 u32 ar;
1625
ad312c7c
ZX		 1626 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1627 vcpu->arch.rmode.tr.selector = var->selector;
1628 vcpu->arch.rmode.tr.base = var->base;
1629 vcpu->arch.rmode.tr.limit = var->limit;
1630 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1631 return;
1632 }
1633 vmcs_writel(sf->base, var->base);
1634 vmcs_write32(sf->limit, var->limit);
1635 vmcs_write16(sf->selector, var->selector);
ad312c7c 1636 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1637 /*
1638 * Hack real-mode segments into vm86 compatibility.
1639 */
1640 if (var->base == 0xffff0000 && var->selector == 0xf000)
1641 vmcs_writel(sf->base, 0xf0000);
1642 ar = 0xf3;
1643 } else
1644 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1645 vmcs_write32(sf->ar_bytes, ar);
1646}
1647
6aa8b732
AK		 1648static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1649{
1650 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1651
1652 *db = (ar >> 14) & 1;
1653 *l = (ar >> 13) & 1;
1654}
1655
1656static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1657{
1658 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1659 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1660}
1661
1662static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1663{
1664 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1665 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1666}
1667
1668static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1669{
1670 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1671 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1672}
1673
1674static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1675{
1676 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1677 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1678}
1679
d77c26fc 1680static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1681{
6aa8b732 1682 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1683 u16 data = 0;
10589a46 1684 int ret = 0;
195aefde 1685 int r;
6aa8b732 1686
195aefde
IE		 1687 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1688 if (r < 0)
10589a46 1689 goto out;
195aefde
IE		 1690 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1691 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1692 if (r < 0)
10589a46 1693 goto out;
195aefde
IE		 1694 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1695 if (r < 0)
10589a46 1696 goto out;
195aefde
IE		 1697 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1698 if (r < 0)
10589a46 1699 goto out;
195aefde 1700 data = ~0;
10589a46
MT		 1701 r = kvm_write_guest_page(kvm, fn, &data,
1702 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1703 sizeof(u8));
195aefde 1704 if (r < 0)
10589a46
MT		 1705 goto out;
1706
1707 ret = 1;
1708out:
10589a46 1709 return ret;
6aa8b732
AK		 1710}
1711
b7ebfb05
SY		 1712static int init_rmode_identity_map(struct kvm *kvm)
1713{
1714 int i, r, ret;
1715 pfn_t identity_map_pfn;
1716 u32 tmp;
1717
1718 if (!vm_need_ept())
1719 return 1;
1720 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1721 printk(KERN_ERR "EPT: identity-mapping pagetable "
1722 "haven't been allocated!\n");
1723 return 0;
1724 }
1725 if (likely(kvm->arch.ept_identity_pagetable_done))
1726 return 1;
1727 ret = 0;
1728 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1729 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1730 if (r < 0)
1731 goto out;
1732 /* Set up identity-mapping pagetable for EPT in real mode */
1733 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1734 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1735 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1736 r = kvm_write_guest_page(kvm, identity_map_pfn,
1737 &tmp, i * sizeof(tmp), sizeof(tmp));
1738 if (r < 0)
1739 goto out;
1740 }
1741 kvm->arch.ept_identity_pagetable_done = true;
1742 ret = 1;
1743out:
1744 return ret;
1745}
1746
6aa8b732
AK		 1747static void seg_setup(int seg)
1748{
1749 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1750
1751 vmcs_write16(sf->selector, 0);
1752 vmcs_writel(sf->base, 0);
1753 vmcs_write32(sf->limit, 0xffff);
1754 vmcs_write32(sf->ar_bytes, 0x93);
1755}
1756
f78e0e2e
SY		 1757static int alloc_apic_access_page(struct kvm *kvm)
1758{
1759 struct kvm_userspace_memory_region kvm_userspace_mem;
1760 int r = 0;
1761
72dc67a6 1762 down_write(&kvm->slots_lock);
bfc6d222 1763 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 1764 goto out;
1765 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1766 kvm_userspace_mem.flags = 0;
1767 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1768 kvm_userspace_mem.memory_size = PAGE_SIZE;
1769 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1770 if (r)
1771 goto out;
72dc67a6
IE		 1772
1773 down_read(&current->mm->mmap_sem);
bfc6d222 1774 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
72dc67a6 1775 up_read(&current->mm->mmap_sem);
f78e0e2e 1776out:
72dc67a6 1777 up_write(&kvm->slots_lock);
f78e0e2e
SY		 1778 return r;
1779}
1780
b7ebfb05
SY		 1781static int alloc_identity_pagetable(struct kvm *kvm)
1782{
1783 struct kvm_userspace_memory_region kvm_userspace_mem;
1784 int r = 0;
1785
1786 down_write(&kvm->slots_lock);
1787 if (kvm->arch.ept_identity_pagetable)
1788 goto out;
1789 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1790 kvm_userspace_mem.flags = 0;
1791 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1792 kvm_userspace_mem.memory_size = PAGE_SIZE;
1793 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1794 if (r)
1795 goto out;
1796
1797 down_read(&current->mm->mmap_sem);
1798 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1799 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1800 up_read(&current->mm->mmap_sem);
1801out:
1802 up_write(&kvm->slots_lock);
1803 return r;
1804}
1805
2384d2b3
SY		 1806static void allocate_vpid(struct vcpu_vmx *vmx)
1807{
1808 int vpid;
1809
1810 vmx->vpid = 0;
1811 if (!enable_vpid || !cpu_has_vmx_vpid())
1812 return;
1813 spin_lock(&vmx_vpid_lock);
1814 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1815 if (vpid < VMX_NR_VPIDS) {
1816 vmx->vpid = vpid;
1817 __set_bit(vpid, vmx_vpid_bitmap);
1818 }
1819 spin_unlock(&vmx_vpid_lock);
1820}
1821
8b2cf73c 1822static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
25c5f225
SY		 1823{
1824 void *va;
1825
1826 if (!cpu_has_vmx_msr_bitmap())
1827 return;
1828
1829 /*
1830 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1831 * have the write-low and read-high bitmap offsets the wrong way round.
1832 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1833 */
1834 va = kmap(msr_bitmap);
1835 if (msr <= 0x1fff) {
1836 __clear_bit(msr, va + 0x000); /* read-low */
1837 __clear_bit(msr, va + 0x800); /* write-low */
1838 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1839 msr &= 0x1fff;
1840 __clear_bit(msr, va + 0x400); /* read-high */
1841 __clear_bit(msr, va + 0xc00); /* write-high */
1842 }
1843 kunmap(msr_bitmap);
1844}
1845
6aa8b732
AK		 1846/*
1847 * Sets up the vmcs for emulated real mode.
1848 */
8b9cf98c 1849static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1850{
1851 u32 host_sysenter_cs;
1852 u32 junk;
1853 unsigned long a;
1854 struct descriptor_table dt;
1855 int i;
cd2276a7 1856 unsigned long kvm_vmx_return;
6e5d865c 1857 u32 exec_control;
6aa8b732 1858
6aa8b732 1859 /* I/O */
fdef3ad1
HQ		 1860 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1861 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 1862
25c5f225
SY		 1863 if (cpu_has_vmx_msr_bitmap())
1864 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1865
6aa8b732
AK		 1866 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1867
6aa8b732 1868 /* Control */
1c3d14fe
YS		 1869 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1870 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1871
1872 exec_control = vmcs_config.cpu_based_exec_ctrl;
1873 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1874 exec_control &= ~CPU_BASED_TPR_SHADOW;
1875#ifdef CONFIG_X86_64
1876 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1877 CPU_BASED_CR8_LOAD_EXITING;
1878#endif
1879 }
d56f546d
SY		 1880 if (!vm_need_ept())
1881 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1882 CPU_BASED_CR3_LOAD_EXITING;
6e5d865c 1883 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1884
83ff3b9d
SY		 1885 if (cpu_has_secondary_exec_ctrls()) {
1886 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1887 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1888 exec_control &=
1889 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 1890 if (vmx->vpid == 0)
1891 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
d56f546d
SY		 1892 if (!vm_need_ept())
1893 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 1894 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1895 }
f78e0e2e 1896
c7addb90
AK		 1897 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1898 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 1899 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1900
1901 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1902 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1903 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1904
1905 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1906 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1907 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1908 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1909 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1910 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1911#ifdef CONFIG_X86_64
6aa8b732
AK		 1912 rdmsrl(MSR_FS_BASE, a);
1913 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1914 rdmsrl(MSR_GS_BASE, a);
1915 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1916#else
1917 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1918 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1919#endif
1920
1921 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1922
1923 get_idt(&dt);
1924 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1925
d77c26fc 1926 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 1927 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1928 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1929 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1930 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1931
1932 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1933 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1934 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1935 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1936 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1937 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1938
6aa8b732
AK		 1939 for (i = 0; i < NR_VMX_MSR; ++i) {
1940 u32 index = vmx_msr_index[i];
1941 u32 data_low, data_high;
1942 u64 data;
a2fa3e9f 1943 int j = vmx->nmsrs;
6aa8b732
AK		 1944
1945 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1946 continue;
432bd6cb
AK		 1947 if (wrmsr_safe(index, data_low, data_high) < 0)
1948 continue;
6aa8b732 1949 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1950 vmx->host_msrs[j].index = index;
1951 vmx->host_msrs[j].reserved = 0;
1952 vmx->host_msrs[j].data = data;
1953 vmx->guest_msrs[j] = vmx->host_msrs[j];
1954 ++vmx->nmsrs;
6aa8b732 1955 }
6aa8b732 1956
1c3d14fe 1957 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1958
1959 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1960 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1961
e00c8cf2
AK		 1962 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1963 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1964
f78e0e2e 1965
e00c8cf2
AK		 1966 return 0;
1967}
1968
b7ebfb05
SY		 1969static int init_rmode(struct kvm *kvm)
1970{
1971 if (!init_rmode_tss(kvm))
1972 return 0;
1973 if (!init_rmode_identity_map(kvm))
1974 return 0;
1975 return 1;
1976}
1977
e00c8cf2
AK		 1978static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1979{
1980 struct vcpu_vmx *vmx = to_vmx(vcpu);
1981 u64 msr;
1982 int ret;
1983
3200f405 1984 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 1985 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 1986 ret = -ENOMEM;
1987 goto out;
1988 }
1989
ad312c7c 1990 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 1991
ad312c7c 1992 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 1993 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 1994 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1995 if (vmx->vcpu.vcpu_id == 0)
1996 msr |= MSR_IA32_APICBASE_BSP;
1997 kvm_set_apic_base(&vmx->vcpu, msr);
1998
1999 fx_init(&vmx->vcpu);
2000
2001 /*
2002 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2003 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2004 */
2005 if (vmx->vcpu.vcpu_id == 0) {
2006 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2007 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2008 } else {
ad312c7c
ZX		 2009 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2010 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2
AK		 2011 }
2012 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2013 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2014
2015 seg_setup(VCPU_SREG_DS);
2016 seg_setup(VCPU_SREG_ES);
2017 seg_setup(VCPU_SREG_FS);
2018 seg_setup(VCPU_SREG_GS);
2019 seg_setup(VCPU_SREG_SS);
2020
2021 vmcs_write16(GUEST_TR_SELECTOR, 0);
2022 vmcs_writel(GUEST_TR_BASE, 0);
2023 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2024 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2025
2026 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2027 vmcs_writel(GUEST_LDTR_BASE, 0);
2028 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2029 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2030
2031 vmcs_write32(GUEST_SYSENTER_CS, 0);
2032 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2033 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2034
2035 vmcs_writel(GUEST_RFLAGS, 0x02);
2036 if (vmx->vcpu.vcpu_id == 0)
2037 vmcs_writel(GUEST_RIP, 0xfff0);
2038 else
2039 vmcs_writel(GUEST_RIP, 0);
2040 vmcs_writel(GUEST_RSP, 0);
2041
2042 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2043 vmcs_writel(GUEST_DR7, 0x400);
2044
2045 vmcs_writel(GUEST_GDTR_BASE, 0);
2046 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2047
2048 vmcs_writel(GUEST_IDTR_BASE, 0);
2049 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2050
2051 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2052 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2053 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2054
2055 guest_write_tsc(0);
2056
2057 /* Special registers */
2058 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2059
2060 setup_msrs(vmx);
2061
6aa8b732
AK		 2062 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2063
f78e0e2e
SY		 2064 if (cpu_has_vmx_tpr_shadow()) {
2065 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2066 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2067 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2068 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2069 vmcs_write32(TPR_THRESHOLD, 0);
2070 }
2071
2072 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2073 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2074 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2075
2384d2b3
SY		 2076 if (vmx->vpid != 0)
2077 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2078
ad312c7c
ZX		 2079 vmx->vcpu.arch.cr0 = 0x60000010;
2080 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2081 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2082 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2083 vmx_fpu_activate(&vmx->vcpu);
2084 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2085
2384d2b3
SY		 2086 vpid_sync_vcpu_all(vmx);
2087
3200f405 2088 ret = 0;
6aa8b732 2089
6aa8b732 2090out:
3200f405 2091 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2092 return ret;
2093}
2094
85f455f7
ED		 2095static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2096{
9c8cba37
AK		 2097 struct vcpu_vmx *vmx = to_vmx(vcpu);
2098
2714d1d3
FEL		 2099 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2100
ad312c7c 2101 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2102 vmx->rmode.irq.pending = true;
2103 vmx->rmode.irq.vector = irq;
2104 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
9c5623e3
AK		 2105 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2106 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2107 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
9c8cba37 2108 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2109 return;
2110 }
2111 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2112 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2113}
2114
6aa8b732
AK		 2115static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2116{
ad312c7c
ZX		 2117 int word_index = __ffs(vcpu->arch.irq_summary);
2118 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 2119 int irq = word_index * BITS_PER_LONG + bit_index;
2120
ad312c7c
ZX		 2121 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2122 if (!vcpu->arch.irq_pending[word_index])
2123 clear_bit(word_index, &vcpu->arch.irq_summary);
85f455f7 2124 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 2125}
2126
c1150d8c
DL		 2127
2128static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2129 struct kvm_run *kvm_run)
6aa8b732 2130{
c1150d8c
DL		 2131 u32 cpu_based_vm_exec_control;
2132
ad312c7c 2133 vcpu->arch.interrupt_window_open =
c1150d8c
DL		 2134 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2135 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2136
ad312c7c
ZX		 2137 if (vcpu->arch.interrupt_window_open &&
2138 vcpu->arch.irq_summary &&
c1150d8c 2139 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 2140 /*
c1150d8c 2141 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 2142 */
2143 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 2144
2145 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
ad312c7c
ZX		 2146 if (!vcpu->arch.interrupt_window_open &&
2147 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 2148 /*
2149 * Interrupts blocked. Wait for unblock.
2150 */
c1150d8c
DL		 2151 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2152 else
2153 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2154 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 2155}
2156
cbc94022
IE		 2157static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2158{
2159 int ret;
2160 struct kvm_userspace_memory_region tss_mem = {
2161 .slot = 8,
2162 .guest_phys_addr = addr,
2163 .memory_size = PAGE_SIZE * 3,
2164 .flags = 0,
2165 };
2166
2167 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2168 if (ret)
2169 return ret;
bfc6d222 2170 kvm->arch.tss_addr = addr;
cbc94022
IE		 2171 return 0;
2172}
2173
6aa8b732
AK		 2174static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2175{
2176 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2177
2178 set_debugreg(dbg->bp[0], 0);
2179 set_debugreg(dbg->bp[1], 1);
2180 set_debugreg(dbg->bp[2], 2);
2181 set_debugreg(dbg->bp[3], 3);
2182
2183 if (dbg->singlestep) {
2184 unsigned long flags;
2185
2186 flags = vmcs_readl(GUEST_RFLAGS);
2187 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2188 vmcs_writel(GUEST_RFLAGS, flags);
2189 }
2190}
2191
2192static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2193 int vec, u32 err_code)
2194{
ad312c7c 2195 if (!vcpu->arch.rmode.active)
6aa8b732
AK		 2196 return 0;
2197
b3f37707
NK		 2198 /*
2199 * Instruction with address size override prefix opcode 0x67
2200 * Cause the #SS fault with 0 error code in VM86 mode.
2201 */
2202 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2203 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 2204 return 1;
2205 return 0;
2206}
2207
2208static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2209{
1155f76a 2210 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2211 u32 intr_info, error_code;
2212 unsigned long cr2, rip;
2213 u32 vect_info;
2214 enum emulation_result er;
2215
1155f76a 2216 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2217 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2218
2219 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2220 !is_page_fault(intr_info))
6aa8b732 2221 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2222 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2223
85f455f7 2224 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 2225 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 2226 set_bit(irq, vcpu->arch.irq_pending);
2227 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 2228 }
2229
1b6269db
AK		 2230 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2231 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2232
2233 if (is_no_device(intr_info)) {
5fd86fcf 2234 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2235 return 1;
2236 }
2237
7aa81cc0 2238 if (is_invalid_opcode(intr_info)) {
571008da 2239 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2240 if (er != EMULATE_DONE)
7ee5d940 2241 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2242 return 1;
2243 }
2244
6aa8b732
AK		 2245 error_code = 0;
2246 rip = vmcs_readl(GUEST_RIP);
2e11384c 2247 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2248 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2249 if (is_page_fault(intr_info)) {
1439442c
SY		 2250 /* EPT won't cause page fault directly */
2251 if (vm_need_ept())
2252 BUG();
6aa8b732 2253 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2254 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2255 (u32)((u64)cr2 >> 32), handler);
3067714c 2256 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2257 }
2258
ad312c7c 2259 if (vcpu->arch.rmode.active &&
6aa8b732 2260 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2261 error_code)) {
ad312c7c
ZX		 2262 if (vcpu->arch.halt_request) {
2263 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2264 return kvm_emulate_halt(vcpu);
2265 }
6aa8b732 2266 return 1;
72d6e5a0 2267 }
6aa8b732 2268
d77c26fc
MD		 2269 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2270 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 2271 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2272 return 0;
2273 }
2274 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2275 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2276 kvm_run->ex.error_code = error_code;
2277 return 0;
2278}
2279
2280static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2281 struct kvm_run *kvm_run)
2282{
1165f5fe 2283 ++vcpu->stat.irq_exits;
2714d1d3 2284 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2285 return 1;
2286}
2287
988ad74f
AK		 2288static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2289{
2290 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2291 return 0;
2292}
6aa8b732 2293
6aa8b732
AK		 2294static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2295{
bfdaab09 2296 unsigned long exit_qualification;
039576c0
AK		 2297 int size, down, in, string, rep;
2298 unsigned port;
6aa8b732 2299
1165f5fe 2300 ++vcpu->stat.io_exits;
bfdaab09 2301 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2302 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2303
2304 if (string) {
3427318f
LV		 2305 if (emulate_instruction(vcpu,
2306 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2307 return 0;
2308 return 1;
2309 }
2310
2311 size = (exit_qualification & 7) + 1;
2312 in = (exit_qualification & 8) != 0;
039576c0 2313 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 2314 rep = (exit_qualification & 32) != 0;
2315 port = exit_qualification >> 16;
e70669ab 2316
3090dd73 2317 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2318}
2319
102d8325
IM		 2320static void
2321vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2322{
2323 /*
2324 * Patch in the VMCALL instruction:
2325 */
2326 hypercall[0] = 0x0f;
2327 hypercall[1] = 0x01;
2328 hypercall[2] = 0xc1;
102d8325
IM		 2329}
2330
6aa8b732
AK		 2331static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2332{
bfdaab09 2333 unsigned long exit_qualification;
6aa8b732
AK		 2334 int cr;
2335 int reg;
2336
bfdaab09 2337 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2338 cr = exit_qualification & 15;
2339 reg = (exit_qualification >> 8) & 15;
2340 switch ((exit_qualification >> 4) & 3) {
2341 case 0: /* mov to cr */
2714d1d3
FEL		 2342 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg],
2343 (u32)((u64)vcpu->arch.regs[reg] >> 32), handler);
6aa8b732
AK		 2344 switch (cr) {
2345 case 0:
2346 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2347 kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2348 skip_emulated_instruction(vcpu);
2349 return 1;
2350 case 3:
2351 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2352 kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2353 skip_emulated_instruction(vcpu);
2354 return 1;
2355 case 4:
2356 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2357 kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2358 skip_emulated_instruction(vcpu);
2359 return 1;
2360 case 8:
2361 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2362 kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
6aa8b732 2363 skip_emulated_instruction(vcpu);
e5314067
AK		 2364 if (irqchip_in_kernel(vcpu->kvm))
2365 return 1;
253abdee
YS		 2366 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2367 return 0;
6aa8b732
AK		 2368 };
2369 break;
25c4c276
AL		 2370 case 2: /* clts */
2371 vcpu_load_rsp_rip(vcpu);
5fd86fcf 2372 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2373 vcpu->arch.cr0 &= ~X86_CR0_TS;
2374 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2375 vmx_fpu_activate(vcpu);
2714d1d3 2376 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2377 skip_emulated_instruction(vcpu);
2378 return 1;
6aa8b732
AK		 2379 case 1: /*mov from cr*/
2380 switch (cr) {
2381 case 3:
2382 vcpu_load_rsp_rip(vcpu);
ad312c7c 2383 vcpu->arch.regs[reg] = vcpu->arch.cr3;
6aa8b732 2384 vcpu_put_rsp_rip(vcpu);
2714d1d3
FEL		 2385 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2386 (u32)vcpu->arch.regs[reg],
2387 (u32)((u64)vcpu->arch.regs[reg] >> 32),
2388 handler);
6aa8b732
AK		 2389 skip_emulated_instruction(vcpu);
2390 return 1;
2391 case 8:
6aa8b732 2392 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2393 vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
6aa8b732 2394 vcpu_put_rsp_rip(vcpu);
2714d1d3
FEL		 2395 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2396 (u32)vcpu->arch.regs[reg], handler);
6aa8b732
AK		 2397 skip_emulated_instruction(vcpu);
2398 return 1;
2399 }
2400 break;
2401 case 3: /* lmsw */
2d3ad1f4 2402 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2403
2404 skip_emulated_instruction(vcpu);
2405 return 1;
2406 default:
2407 break;
2408 }
2409 kvm_run->exit_reason = 0;
f0242478 2410 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2411 (int)(exit_qualification >> 4) & 3, cr);
2412 return 0;
2413}
2414
2415static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2416{
bfdaab09 2417 unsigned long exit_qualification;
6aa8b732
AK		 2418 unsigned long val;
2419 int dr, reg;
2420
2421 /*
2422 * FIXME: this code assumes the host is debugging the guest.
2423 * need to deal with guest debugging itself too.
2424 */
bfdaab09 2425 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2426 dr = exit_qualification & 7;
2427 reg = (exit_qualification >> 8) & 15;
2428 vcpu_load_rsp_rip(vcpu);
2429 if (exit_qualification & 16) {
2430 /* mov from dr */
2431 switch (dr) {
2432 case 6:
2433 val = 0xffff0ff0;
2434 break;
2435 case 7:
2436 val = 0x400;
2437 break;
2438 default:
2439 val = 0;
2440 }
ad312c7c 2441 vcpu->arch.regs[reg] = val;
2714d1d3 2442 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732
AK		 2443 } else {
2444 /* mov to dr */
2445 }
2446 vcpu_put_rsp_rip(vcpu);
2447 skip_emulated_instruction(vcpu);
2448 return 1;
2449}
2450
2451static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2452{
06465c5a
AK		 2453 kvm_emulate_cpuid(vcpu);
2454 return 1;
6aa8b732
AK		 2455}
2456
2457static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2458{
ad312c7c 2459 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2460 u64 data;
2461
2462 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2463 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2464 return 1;
2465 }
2466
2714d1d3
FEL		 2467 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2468 handler);
2469
6aa8b732 2470 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2471 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2472 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2473 skip_emulated_instruction(vcpu);
2474 return 1;
2475}
2476
2477static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2478{
ad312c7c
ZX		 2479 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2480 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2481 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2482
2714d1d3
FEL		 2483 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2484 handler);
2485
6aa8b732 2486 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2487 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2488 return 1;
2489 }
2490
2491 skip_emulated_instruction(vcpu);
2492 return 1;
2493}
2494
6e5d865c
YS		 2495static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2496 struct kvm_run *kvm_run)
2497{
2498 return 1;
2499}
2500
6aa8b732
AK		 2501static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2502 struct kvm_run *kvm_run)
2503{
85f455f7
ED		 2504 u32 cpu_based_vm_exec_control;
2505
2506 /* clear pending irq */
2507 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2508 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2509 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2510
2511 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2512
c1150d8c
DL		 2513 /*
2514 * If the user space waits to inject interrupts, exit as soon as
2515 * possible
2516 */
2517 if (kvm_run->request_interrupt_window &&
ad312c7c 2518 !vcpu->arch.irq_summary) {
c1150d8c 2519 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2520 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2521 return 0;
2522 }
6aa8b732
AK		 2523 return 1;
2524}
2525
2526static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2527{
2528 skip_emulated_instruction(vcpu);
d3bef15f 2529 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2530}
2531
c21415e8
IM		 2532static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2533{
510043da 2534 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2535 kvm_emulate_hypercall(vcpu);
2536 return 1;
c21415e8
IM		 2537}
2538
e5edaa01
ED		 2539static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2540{
2541 skip_emulated_instruction(vcpu);
2542 /* TODO: Add support for VT-d/pass-through device */
2543 return 1;
2544}
2545
f78e0e2e
SY		 2546static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2547{
2548 u64 exit_qualification;
2549 enum emulation_result er;
2550 unsigned long offset;
2551
2552 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2553 offset = exit_qualification & 0xffful;
2554
2555 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2556
2557 if (er != EMULATE_DONE) {
2558 printk(KERN_ERR
2559 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2560 offset);
2561 return -ENOTSUPP;
2562 }
2563 return 1;
2564}
2565
37817f29
IE		 2566static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2567{
2568 unsigned long exit_qualification;
2569 u16 tss_selector;
2570 int reason;
2571
2572 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2573
2574 reason = (u32)exit_qualification >> 30;
2575 tss_selector = exit_qualification;
2576
2577 return kvm_task_switch(vcpu, tss_selector, reason);
2578}
2579
1439442c
SY		 2580static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2581{
2582 u64 exit_qualification;
2583 enum emulation_result er;
2584 gpa_t gpa;
2585 unsigned long hva;
2586 int gla_validity;
2587 int r;
2588
2589 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2590
2591 if (exit_qualification & (1 << 6)) {
2592 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2593 return -ENOTSUPP;
2594 }
2595
2596 gla_validity = (exit_qualification >> 7) & 0x3;
2597 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2598 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2599 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2600 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2601 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2602 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2603 (long unsigned int)exit_qualification);
2604 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2605 kvm_run->hw.hardware_exit_reason = 0;
2606 return -ENOTSUPP;
2607 }
2608
2609 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2610 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2611 if (!kvm_is_error_hva(hva)) {
2612 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2613 if (r < 0) {
2614 printk(KERN_ERR "EPT: Not enough memory!\n");
2615 return -ENOMEM;
2616 }
2617 return 1;
2618 } else {
2619 /* must be MMIO */
2620 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2621
2622 if (er == EMULATE_FAIL) {
2623 printk(KERN_ERR
2624 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2625 er);
2626 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2627 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2628 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2629 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2630 (long unsigned int)exit_qualification);
2631 return -ENOTSUPP;
2632 } else if (er == EMULATE_DO_MMIO)
2633 return 0;
2634 }
2635 return 1;
2636}
2637
6aa8b732
AK		 2638/*
2639 * The exit handlers return 1 if the exit was handled fully and guest execution
2640 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2641 * to be done to userspace and return 0.
2642 */
2643static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2644 struct kvm_run *kvm_run) = {
2645 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2646 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2647 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2648 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2649 [EXIT_REASON_CR_ACCESS] = handle_cr,
2650 [EXIT_REASON_DR_ACCESS] = handle_dr,
2651 [EXIT_REASON_CPUID] = handle_cpuid,
2652 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2653 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2654 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2655 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2656 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 2657 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2658 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 2659 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 2660 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 2661 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 2662};
2663
2664static const int kvm_vmx_max_exit_handlers =
50a3485c 2665 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2666
2667/*
2668 * The guest has exited. See if we can fix it or if we need userspace
2669 * assistance.
2670 */
2671static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2672{
6aa8b732 2673 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 2674 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 2675 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 2676
2714d1d3
FEL		 2677 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP),
2678 (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit);
2679
1439442c
SY		 2680 /* Access CR3 don't cause VMExit in paging mode, so we need
2681 * to sync with guest real CR3. */
2682 if (vm_need_ept() && is_paging(vcpu)) {
2683 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2684 ept_load_pdptrs(vcpu);
2685 }
2686
29bd8a78
AK		 2687 if (unlikely(vmx->fail)) {
2688 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2689 kvm_run->fail_entry.hardware_entry_failure_reason
2690 = vmcs_read32(VM_INSTRUCTION_ERROR);
2691 return 0;
2692 }
6aa8b732 2693
d77c26fc 2694 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c
SY		 2695 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2696 exit_reason != EXIT_REASON_EPT_VIOLATION))
6aa8b732 2697 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
b8688d51 2698 "exit reason is 0x%x\n", __func__, exit_reason);
6aa8b732
AK		 2699 if (exit_reason < kvm_vmx_max_exit_handlers
2700 && kvm_vmx_exit_handlers[exit_reason])
2701 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2702 else {
2703 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2704 kvm_run->hw.hardware_exit_reason = exit_reason;
2705 }
2706 return 0;
2707}
2708
6e5d865c
YS		 2709static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2710{
2711 int max_irr, tpr;
2712
2713 if (!vm_need_tpr_shadow(vcpu->kvm))
2714 return;
2715
2716 if (!kvm_lapic_enabled(vcpu) ||
2717 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2718 vmcs_write32(TPR_THRESHOLD, 0);
2719 return;
2720 }
2721
2722 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2723 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2724}
2725
85f455f7
ED		 2726static void enable_irq_window(struct kvm_vcpu *vcpu)
2727{
2728 u32 cpu_based_vm_exec_control;
2729
2730 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2731 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2732 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2733}
2734
2735static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2736{
1155f76a 2737 struct vcpu_vmx *vmx = to_vmx(vcpu);
85f455f7
ED		 2738 u32 idtv_info_field, intr_info_field;
2739 int has_ext_irq, interrupt_window_open;
1b9778da 2740 int vector;
85f455f7 2741
6e5d865c
YS		 2742 update_tpr_threshold(vcpu);
2743
85f455f7
ED		 2744 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2745 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
1155f76a 2746 idtv_info_field = vmx->idt_vectoring_info;
85f455f7
ED		 2747 if (intr_info_field & INTR_INFO_VALID_MASK) {
2748 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2749 /* TODO: fault when IDT_Vectoring */
9584bf2c
RH		 2750 if (printk_ratelimit())
2751 printk(KERN_ERR "Fault when IDT_Vectoring\n");
85f455f7
ED		 2752 }
2753 if (has_ext_irq)
2754 enable_irq_window(vcpu);
2755 return;
2756 }
2757 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
9c8cba37
AK		 2758 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2759 == INTR_TYPE_EXT_INTR
ad312c7c 2760 && vcpu->arch.rmode.active) {
9c8cba37
AK		 2761 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2762
2763 vmx_inject_irq(vcpu, vect);
2764 if (unlikely(has_ext_irq))
2765 enable_irq_window(vcpu);
2766 return;
2767 }
2768
2714d1d3
FEL		 2769 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2770
85f455f7
ED		 2771 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2772 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2773 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2774
2e11384c 2775 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
85f455f7
ED		 2776 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2777 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2778 if (unlikely(has_ext_irq))
2779 enable_irq_window(vcpu);
2780 return;
2781 }
2782 if (!has_ext_irq)
2783 return;
2784 interrupt_window_open =
2785 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2786 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2787 if (interrupt_window_open) {
2788 vector = kvm_cpu_get_interrupt(vcpu);
2789 vmx_inject_irq(vcpu, vector);
2790 kvm_timer_intr_post(vcpu, vector);
2791 } else
85f455f7
ED		 2792 enable_irq_window(vcpu);
2793}
2794
9c8cba37
AK		 2795/*
2796 * Failure to inject an interrupt should give us the information
2797 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2798 * when fetching the interrupt redirection bitmap in the real-mode
2799 * tss, this doesn't happen. So we do it ourselves.
2800 */
2801static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2802{
2803 vmx->rmode.irq.pending = 0;
2804 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2805 return;
2806 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2807 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2808 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2809 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2810 return;
2811 }
2812 vmx->idt_vectoring_info =
2813 VECTORING_INFO_VALID_MASK
2814 | INTR_TYPE_EXT_INTR
2815 | vmx->rmode.irq.vector;
2816}
2817
04d2cc77 2818static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2819{
a2fa3e9f 2820 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2821 u32 intr_info;
e6adf283
AK		 2822
2823 /*
2824 * Loading guest fpu may have cleared host cr0.ts
2825 */
2826 vmcs_writel(HOST_CR0, read_cr0());
2827
d77c26fc 2828 asm(
6aa8b732 2829 /* Store host registers */
05b3e0c2 2830#ifdef CONFIG_X86_64
c2036300 2831 "push %%rdx; push %%rbp;"
6aa8b732 2832 "push %%rcx \n\t"
6aa8b732 2833#else
ff593e5a
LV		 2834 "push %%edx; push %%ebp;"
2835 "push %%ecx \n\t"
6aa8b732 2836#endif
c2036300 2837 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
6aa8b732 2838 /* Check if vmlaunch of vmresume is needed */
e08aa78a 2839 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 2840 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2841#ifdef CONFIG_X86_64
e08aa78a 2842 "mov %c[cr2](%0), %%rax \n\t"
6aa8b732 2843 "mov %%rax, %%cr2 \n\t"
e08aa78a
AK		 2844 "mov %c[rax](%0), %%rax \n\t"
2845 "mov %c[rbx](%0), %%rbx \n\t"
2846 "mov %c[rdx](%0), %%rdx \n\t"
2847 "mov %c[rsi](%0), %%rsi \n\t"
2848 "mov %c[rdi](%0), %%rdi \n\t"
2849 "mov %c[rbp](%0), %%rbp \n\t"
2850 "mov %c[r8](%0), %%r8 \n\t"
2851 "mov %c[r9](%0), %%r9 \n\t"
2852 "mov %c[r10](%0), %%r10 \n\t"
2853 "mov %c[r11](%0), %%r11 \n\t"
2854 "mov %c[r12](%0), %%r12 \n\t"
2855 "mov %c[r13](%0), %%r13 \n\t"
2856 "mov %c[r14](%0), %%r14 \n\t"
2857 "mov %c[r15](%0), %%r15 \n\t"
2858 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
6aa8b732 2859#else
e08aa78a 2860 "mov %c[cr2](%0), %%eax \n\t"
6aa8b732 2861 "mov %%eax, %%cr2 \n\t"
e08aa78a
AK		 2862 "mov %c[rax](%0), %%eax \n\t"
2863 "mov %c[rbx](%0), %%ebx \n\t"
2864 "mov %c[rdx](%0), %%edx \n\t"
2865 "mov %c[rsi](%0), %%esi \n\t"
2866 "mov %c[rdi](%0), %%edi \n\t"
2867 "mov %c[rbp](%0), %%ebp \n\t"
2868 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
6aa8b732
AK		 2869#endif
2870 /* Enter guest mode */
cd2276a7 2871 "jne .Llaunched \n\t"
6aa8b732 2872 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2873 "jmp .Lkvm_vmx_return \n\t"
2874 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2875 ".Lkvm_vmx_return: "
6aa8b732 2876 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2877#ifdef CONFIG_X86_64
e08aa78a
AK		 2878 "xchg %0, (%%rsp) \n\t"
2879 "mov %%rax, %c[rax](%0) \n\t"
2880 "mov %%rbx, %c[rbx](%0) \n\t"
2881 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2882 "mov %%rdx, %c[rdx](%0) \n\t"
2883 "mov %%rsi, %c[rsi](%0) \n\t"
2884 "mov %%rdi, %c[rdi](%0) \n\t"
2885 "mov %%rbp, %c[rbp](%0) \n\t"
2886 "mov %%r8, %c[r8](%0) \n\t"
2887 "mov %%r9, %c[r9](%0) \n\t"
2888 "mov %%r10, %c[r10](%0) \n\t"
2889 "mov %%r11, %c[r11](%0) \n\t"
2890 "mov %%r12, %c[r12](%0) \n\t"
2891 "mov %%r13, %c[r13](%0) \n\t"
2892 "mov %%r14, %c[r14](%0) \n\t"
2893 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 2894 "mov %%cr2, %%rax \n\t"
e08aa78a 2895 "mov %%rax, %c[cr2](%0) \n\t"
6aa8b732 2896
e08aa78a 2897 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
6aa8b732 2898#else
e08aa78a
AK		 2899 "xchg %0, (%%esp) \n\t"
2900 "mov %%eax, %c[rax](%0) \n\t"
2901 "mov %%ebx, %c[rbx](%0) \n\t"
2902 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2903 "mov %%edx, %c[rdx](%0) \n\t"
2904 "mov %%esi, %c[rsi](%0) \n\t"
2905 "mov %%edi, %c[rdi](%0) \n\t"
2906 "mov %%ebp, %c[rbp](%0) \n\t"
6aa8b732 2907 "mov %%cr2, %%eax \n\t"
e08aa78a 2908 "mov %%eax, %c[cr2](%0) \n\t"
6aa8b732 2909
e08aa78a 2910 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
6aa8b732 2911#endif
e08aa78a
AK		 2912 "setbe %c[fail](%0) \n\t"
2913 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2914 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2915 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
ad312c7c
ZX		 2916 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2917 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2918 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2919 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2920 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2921 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2922 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 2923#ifdef CONFIG_X86_64
ad312c7c
ZX		 2924 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2925 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2926 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2927 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2928 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2929 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2930 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2931 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 2932#endif
ad312c7c 2933 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300
LV		 2934 : "cc", "memory"
2935#ifdef CONFIG_X86_64
2936 , "rbx", "rdi", "rsi"
2937 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
ff593e5a
LV		 2938#else
2939 , "ebx", "edi", "rsi"
c2036300
LV		 2940#endif
2941 );
6aa8b732 2942
1155f76a 2943 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 2944 if (vmx->rmode.irq.pending)
2945 fixup_rmode_irq(vmx);
1155f76a 2946
ad312c7c 2947 vcpu->arch.interrupt_window_open =
d77c26fc 2948 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2949
d77c26fc 2950 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2951 vmx->launched = 1;
1b6269db
AK		 2952
2953 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2954
2955 /* We need to handle NMIs before interrupts are enabled */
2714d1d3
FEL		 2956 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
2957 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 2958 asm("int $2");
2714d1d3 2959 }
6aa8b732
AK		 2960}
2961
6aa8b732
AK		 2962static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2963{
a2fa3e9f
GH		 2964 struct vcpu_vmx *vmx = to_vmx(vcpu);
2965
2966 if (vmx->vmcs) {
15c8b6c1 2967 on_each_cpu(__vcpu_clear, vmx, 1);
a2fa3e9f
GH		 2968 free_vmcs(vmx->vmcs);
2969 vmx->vmcs = NULL;
6aa8b732
AK		 2970 }
2971}
2972
2973static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2974{
fb3f0f51
RR		 2975 struct vcpu_vmx *vmx = to_vmx(vcpu);
2976
2384d2b3
SY		 2977 spin_lock(&vmx_vpid_lock);
2978 if (vmx->vpid != 0)
2979 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2980 spin_unlock(&vmx_vpid_lock);
6aa8b732 2981 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2982 kfree(vmx->host_msrs);
2983 kfree(vmx->guest_msrs);
2984 kvm_vcpu_uninit(vcpu);
a4770347 2985 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2986}
2987
fb3f0f51 2988static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2989{
fb3f0f51 2990 int err;
c16f862d 2991 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2992 int cpu;
6aa8b732 2993
a2fa3e9f 2994 if (!vmx)
fb3f0f51
RR		 2995 return ERR_PTR(-ENOMEM);
2996
2384d2b3 2997 allocate_vpid(vmx);
1439442c
SY		 2998 if (id == 0 && vm_need_ept()) {
2999 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3000 VMX_EPT_WRITABLE_MASK |
3001 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3002 kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK,
3003 VMX_EPT_FAKE_DIRTY_MASK, 0ull,
3004 VMX_EPT_EXECUTABLE_MASK);
3005 kvm_enable_tdp();
3006 }
2384d2b3 3007
fb3f0f51
RR		 3008 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3009 if (err)
3010 goto free_vcpu;
965b58a5 3011
a2fa3e9f 3012 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3013 if (!vmx->guest_msrs) {
3014 err = -ENOMEM;
3015 goto uninit_vcpu;
3016 }
965b58a5 3017
a2fa3e9f
GH		 3018 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3019 if (!vmx->host_msrs)
fb3f0f51 3020 goto free_guest_msrs;
965b58a5 3021
a2fa3e9f
GH		 3022 vmx->vmcs = alloc_vmcs();
3023 if (!vmx->vmcs)
fb3f0f51 3024 goto free_msrs;
a2fa3e9f
GH		 3025
3026 vmcs_clear(vmx->vmcs);
3027
15ad7146
AK		 3028 cpu = get_cpu();
3029 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3030 err = vmx_vcpu_setup(vmx);
fb3f0f51 3031 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3032 put_cpu();
fb3f0f51
RR		 3033 if (err)
3034 goto free_vmcs;
5e4a0b3c
MT		 3035 if (vm_need_virtualize_apic_accesses(kvm))
3036 if (alloc_apic_access_page(kvm) != 0)
3037 goto free_vmcs;
fb3f0f51 3038
b7ebfb05
SY		 3039 if (vm_need_ept())
3040 if (alloc_identity_pagetable(kvm) != 0)
3041 goto free_vmcs;
3042
fb3f0f51
RR		 3043 return &vmx->vcpu;
3044
3045free_vmcs:
3046 free_vmcs(vmx->vmcs);
3047free_msrs:
3048 kfree(vmx->host_msrs);
3049free_guest_msrs:
3050 kfree(vmx->guest_msrs);
3051uninit_vcpu:
3052 kvm_vcpu_uninit(&vmx->vcpu);
3053free_vcpu:
a4770347 3054 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3055 return ERR_PTR(err);
6aa8b732
AK		 3056}
3057
002c7f7c
YS		 3058static void __init vmx_check_processor_compat(void *rtn)
3059{
3060 struct vmcs_config vmcs_conf;
3061
3062 *(int *)rtn = 0;
3063 if (setup_vmcs_config(&vmcs_conf) < 0)
3064 *(int *)rtn = -EIO;
3065 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3066 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3067 smp_processor_id());
3068 *(int *)rtn = -EIO;
3069 }
3070}
3071
67253af5
SY		 3072static int get_ept_level(void)
3073{
3074 return VMX_EPT_DEFAULT_GAW + 1;
3075}
3076
cbdd1bea 3077static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3078 .cpu_has_kvm_support = cpu_has_kvm_support,
3079 .disabled_by_bios = vmx_disabled_by_bios,
3080 .hardware_setup = hardware_setup,
3081 .hardware_unsetup = hardware_unsetup,
002c7f7c 3082 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3083 .hardware_enable = hardware_enable,
3084 .hardware_disable = hardware_disable,
774ead3a 3085 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 3086
3087 .vcpu_create = vmx_create_vcpu,
3088 .vcpu_free = vmx_free_vcpu,
04d2cc77 3089 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3090
04d2cc77 3091 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3092 .vcpu_load = vmx_vcpu_load,
3093 .vcpu_put = vmx_vcpu_put,
774c47f1 3094 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 3095
3096 .set_guest_debug = set_guest_debug,
04d2cc77 3097 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 3098 .get_msr = vmx_get_msr,
3099 .set_msr = vmx_set_msr,
3100 .get_segment_base = vmx_get_segment_base,
3101 .get_segment = vmx_get_segment,
3102 .set_segment = vmx_set_segment,
2e4d2653 3103 .get_cpl = vmx_get_cpl,
6aa8b732 3104 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3105 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3106 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3107 .set_cr3 = vmx_set_cr3,
3108 .set_cr4 = vmx_set_cr4,
6aa8b732 3109 .set_efer = vmx_set_efer,
6aa8b732
AK		 3110 .get_idt = vmx_get_idt,
3111 .set_idt = vmx_set_idt,
3112 .get_gdt = vmx_get_gdt,
3113 .set_gdt = vmx_set_gdt,
3114 .cache_regs = vcpu_load_rsp_rip,
3115 .decache_regs = vcpu_put_rsp_rip,
3116 .get_rflags = vmx_get_rflags,
3117 .set_rflags = vmx_set_rflags,
3118
3119 .tlb_flush = vmx_flush_tlb,
6aa8b732 3120
6aa8b732 3121 .run = vmx_vcpu_run,
04d2cc77 3122 .handle_exit = kvm_handle_exit,
6aa8b732 3123 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3124 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 3125 .get_irq = vmx_get_irq,
3126 .set_irq = vmx_inject_irq,
298101da
AK		 3127 .queue_exception = vmx_queue_exception,
3128 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 3129 .inject_pending_irq = vmx_intr_assist,
3130 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 3131
3132 .set_tss_addr = vmx_set_tss_addr,
67253af5 3133 .get_tdp_level = get_ept_level,
6aa8b732
AK		 3134};
3135
3136static int __init vmx_init(void)
3137{
25c5f225 3138 void *va;
fdef3ad1
HQ		 3139 int r;
3140
3141 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3142 if (!vmx_io_bitmap_a)
3143 return -ENOMEM;
3144
3145 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3146 if (!vmx_io_bitmap_b) {
3147 r = -ENOMEM;
3148 goto out;
3149 }
3150
25c5f225
SY		 3151 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3152 if (!vmx_msr_bitmap) {
3153 r = -ENOMEM;
3154 goto out1;
3155 }
3156
fdef3ad1
HQ		 3157 /*
3158 * Allow direct access to the PC debug port (it is often used for I/O
3159 * delays, but the vmexits simply slow things down).
3160 */
25c5f225
SY		 3161 va = kmap(vmx_io_bitmap_a);
3162 memset(va, 0xff, PAGE_SIZE);
3163 clear_bit(0x80, va);
cd0536d7 3164 kunmap(vmx_io_bitmap_a);
fdef3ad1 3165
25c5f225
SY		 3166 va = kmap(vmx_io_bitmap_b);
3167 memset(va, 0xff, PAGE_SIZE);
cd0536d7 3168 kunmap(vmx_io_bitmap_b);
fdef3ad1 3169
25c5f225
SY		 3170 va = kmap(vmx_msr_bitmap);
3171 memset(va, 0xff, PAGE_SIZE);
3172 kunmap(vmx_msr_bitmap);
3173
2384d2b3
SY		 3174 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3175
cb498ea2 3176 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3177 if (r)
25c5f225
SY		 3178 goto out2;
3179
3180 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3181 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3182 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3183 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3184 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
fdef3ad1 3185
1439442c
SY		 3186 if (cpu_has_vmx_ept())
3187 bypass_guest_pf = 0;
3188
c7addb90
AK		 3189 if (bypass_guest_pf)
3190 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3191
1439442c
SY		 3192 ept_sync_global();
3193
fdef3ad1
HQ		 3194 return 0;
3195
25c5f225
SY		 3196out2:
3197 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3198out1:
3199 __free_page(vmx_io_bitmap_b);
3200out:
3201 __free_page(vmx_io_bitmap_a);
3202 return r;
6aa8b732
AK		 3203}
3204
3205static void __exit vmx_exit(void)
3206{
25c5f225 3207 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3208 __free_page(vmx_io_bitmap_b);
3209 __free_page(vmx_io_bitmap_a);
3210
cb498ea2 3211 kvm_exit();
6aa8b732
AK		 3212}
3213
3214module_init(vmx_init)
3215module_exit(vmx_exit)
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