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x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentry
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM		 110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
9ed96e87
MT		 113unsigned int min_timer_period_us = 500;
114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT		 116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW		 138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK		 141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY		 151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
f0ace387 187 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 195 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 197 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 200 { NULL }
201};
202
2acf923e
DC		 203u64 __read_mostly host_xcr0;
204
b6785def 205static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 206
af585b92
GN		 207static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208{
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212}
213
18863bdd
AK		 214static void kvm_on_user_return(struct user_return_notifier *urn)
215{
216 unsigned slot;
18863bdd
AK		 217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 219 struct kvm_shared_msr_values *values;
1650b4eb
IA		 220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
18863bdd 232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
18863bdd
AK		 237 }
238 }
18863bdd
AK		 239}
240
2bf78fa7 241static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 242{
18863bdd 243 u64 value;
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 246
2bf78fa7
SY		 247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256}
257
258void kvm_define_shared_msr(unsigned slot, u32 msr)
259{
0123be42 260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 261 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 264}
265EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267static void kvm_shared_msr_cpu_online(void)
268{
269 unsigned i;
18863bdd
AK		 270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 272 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 273}
274
8b3c3104 275int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 276{
013f6a5d
MT		 277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 279 int err;
18863bdd 280
2bf78fa7 281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 282 return 0;
2bf78fa7 283 smsr->values[slot].curr = value;
8b3c3104
AH		 284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
18863bdd
AK		 288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
8b3c3104 293 return 0;
18863bdd
AK		 294}
295EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
13a34e06 297static void drop_user_return_notifiers(void)
3548bab5 298{
013f6a5d
MT		 299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304}
305
6866b83e
CO		 306u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307{
8a5a87d9 308 return vcpu->arch.apic_base;
6866b83e
CO		 309}
310EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
58cb628d
JK		 312int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313{
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 320
d3802286
JM		 321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
58cb628d 323 if (!msr_info->host_initiated &&
d3802286 324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
6866b83e
CO		 332}
333EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
2605fc21 335asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 336{
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339}
340EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
3fd28fce
ED		 342#define EXCPT_BENIGN 0
343#define EXCPT_CONTRIBUTORY 1
344#define EXCPT_PF 2
345
346static int exception_class(int vector)
347{
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361}
362
d6e8c854
NA		 363#define EXCPT_FAULT 0
364#define EXCPT_TRAP 1
365#define EXCPT_ABORT 2
366#define EXCPT_INTERRUPT 3
367
368static int exception_type(int vector)
369{
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386}
387
3fd28fce 388static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
3fd28fce
ED		 391{
392 u32 prev_nr;
393 int class1, class2;
394
3842d135
AK		 395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
664f8e26 397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 398 queue:
3ffb2468
NA		 399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
664f8e26
WL		 401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
3fd28fce
ED		 416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
a8eeb04a 426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
3fd28fce 438 vcpu->arch.exception.pending = true;
664f8e26 439 vcpu->arch.exception.injected = false;
3fd28fce
ED		 440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448}
449
298101da
AK		 450void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451{
ce7ddec4 452 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 453}
454EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
ce7ddec4
JR		 456void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457{
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459}
460EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
6affcbed 462int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 463{
db8fcefa
AP		 464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
6affcbed
KH		 467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
db8fcefa
AP		 470}
471EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 472
6389ee94 473void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 474{
475 ++vcpu->stat.pf_guest;
adfe20fb
WL		 476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
6389ee94 482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 483}
27d6c865 484EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 485
ef54bcfe 486static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 487{
6389ee94
AK		 488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 490 else
6389ee94 491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 492
493 return fault->nested_page_fault;
d4f8cf66
JR		 494}
495
3419ffc8
SY		 496void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497{
7460fb4a
AK		 498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 500}
501EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
298101da
AK		 503void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504{
ce7ddec4 505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 506}
507EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
ce7ddec4
JR		 509void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510{
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512}
513EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
0a79b009
AK		 515/*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 520{
0a79b009
AK		 521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
298101da 525}
0a79b009 526EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 527
16f8a6f9
NA		 528bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529{
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535}
536EXPORT_SYMBOL_GPL(kvm_require_dr);
537
ec92fe44
JR		 538/*
539 * This function will be used to read from the physical memory of the currently
54bf36aa 540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 541 * can read from guest physical or from the guest's guest physical memory.
542 */
543int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546{
54987b7a 547 struct x86_exception exception;
ec92fe44
JR		 548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
54987b7a 552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
54bf36aa 558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 559}
560EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
69b0049a 562static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 563 void *data, int offset, int len, u32 access)
564{
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567}
568
a03490ed
CO		 569/*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
ff03a073 572int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 573{
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
ff03a073 578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 579
ff03a073
JR		 580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 588 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
ff03a073 597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 602out:
a03490ed
CO		 603
604 return ret;
605}
cc4b6871 606EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 607
9ed38ffa 608bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 609{
ff03a073 610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 611 bool changed = true;
3d06b8bf
JR		 612 int offset;
613 gfn_t gfn;
d835dfec
AK		 614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
6de4f3ad
AK		 619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
a512177e
PB		 623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 627 if (r < 0)
628 goto out;
ff03a073 629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 630out:
d835dfec
AK		 631
632 return changed;
633}
9ed38ffa 634EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 635
49a9b07e 636int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 637{
aad82703 638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 640
f9a48e6a
AK		 641 cr0 |= X86_CR0_ET;
642
ab344828 643#ifdef CONFIG_X86_64
0f12244f
GN		 644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
ab344828
GN		 646#endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 649
0f12244f
GN		 650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
a03490ed 652
0f12244f
GN		 653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
a03490ed
CO		 655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657#ifdef CONFIG_X86_64
f6801dff 658 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 659 int cs_db, cs_l;
660
0f12244f
GN		 661 if (!is_pae(vcpu))
662 return 1;
a03490ed 663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 664 if (cs_l)
665 return 1;
a03490ed
CO		 666 } else
667#endif
ff03a073 668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 669 kvm_read_cr3(vcpu)))
0f12244f 670 return 1;
a03490ed
CO		 671 }
672
ad756a16
MJ		 673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
a03490ed 676 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 677
d170c419 678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 679 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 680 kvm_async_pf_hash_reset(vcpu);
681 }
e5f3f027 682
aad82703
SY		 683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
b18d5431 685
879ae188
LE		 686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
0f12244f
GN		 691 return 0;
692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 694
2d3ad1f4 695void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 696{
49a9b07e 697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 700
42bdf991
MT		 701static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702{
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
706 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
707 vcpu->guest_xcr0_loaded = 1;
708 }
709}
710
711static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
712{
713 if (vcpu->guest_xcr0_loaded) {
714 if (vcpu->arch.xcr0 != host_xcr0)
715 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
716 vcpu->guest_xcr0_loaded = 0;
717 }
718}
719
69b0049a 720static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 721{
56c103ec
LJ		 722 u64 xcr0 = xcr;
723 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 724 u64 valid_bits;
2acf923e
DC		 725
726 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
727 if (index != XCR_XFEATURE_ENABLED_MASK)
728 return 1;
d91cab78 729 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 730 return 1;
d91cab78 731 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 732 return 1;
46c34cb0
PB		 733
734 /*
735 * Do not allow the guest to set bits that we do not support
736 * saving. However, xcr0 bit 0 is always set, even if the
737 * emulated CPU does not support XSAVE (see fx_init).
738 */
d91cab78 739 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 740 if (xcr0 & ~valid_bits)
2acf923e 741 return 1;
46c34cb0 742
d91cab78
DH		 743 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
744 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 745 return 1;
746
d91cab78
DH		 747 if (xcr0 & XFEATURE_MASK_AVX512) {
748 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 749 return 1;
d91cab78 750 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 751 return 1;
752 }
2acf923e 753 vcpu->arch.xcr0 = xcr0;
56c103ec 754
d91cab78 755 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 756 kvm_update_cpuid(vcpu);
2acf923e
DC		 757 return 0;
758}
759
760int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
761{
764bcbc5
Z		 762 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
763 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 764 kvm_inject_gp(vcpu, 0);
765 return 1;
766 }
767 return 0;
768}
769EXPORT_SYMBOL_GPL(kvm_set_xcr);
770
a83b29c6 771int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 772{
fc78f519 773 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 774 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 775 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 776
0f12244f
GN		 777 if (cr4 & CR4_RESERVED_BITS)
778 return 1;
a03490ed 779
d6321d49 780 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 781 return 1;
782
d6321d49 783 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 784 return 1;
785
d6321d49 786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 787 return 1;
788
d6321d49 789 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 790 return 1;
791
d6321d49 792 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 793 return 1;
794
fd8cb433 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 796 return 1;
797
df9b1e03
PB		 798 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
799 return 1;
800
a03490ed 801 if (is_long_mode(vcpu)) {
0f12244f
GN		 802 if (!(cr4 & X86_CR4_PAE))
803 return 1;
a2edf57f
AK		 804 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
805 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 806 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
807 kvm_read_cr3(vcpu)))
0f12244f
GN		 808 return 1;
809
ad756a16 810 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 811 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 812 return 1;
813
814 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
815 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
816 return 1;
817 }
818
5e1746d6 819 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 820 return 1;
a03490ed 821
ad756a16
MJ		 822 if (((cr4 ^ old_cr4) & pdptr_bits) ||
823 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 824 kvm_mmu_reset_context(vcpu);
0f12244f 825
b9baba86 826 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 827 kvm_update_cpuid(vcpu);
2acf923e 828
0f12244f
GN		 829 return 0;
830}
2d3ad1f4 831EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 832
2390218b 833int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 834{
ac146235 835#ifdef CONFIG_X86_64
9d88fca7 836 cr3 &= ~CR3_PCID_INVD;
ac146235 837#endif
9d88fca7 838
9f8fe504 839 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 840 kvm_mmu_sync_roots(vcpu);
77c3913b 841 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 842 return 0;
d835dfec
AK		 843 }
844
d1cd3ce9
YZ		 845 if (is_long_mode(vcpu) &&
846 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
847 return 1;
848 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 849 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 850 return 1;
a03490ed 851
0f12244f 852 vcpu->arch.cr3 = cr3;
aff48baa 853 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 854 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 855 return 0;
856}
2d3ad1f4 857EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 858
eea1cff9 859int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 860{
0f12244f
GN		 861 if (cr8 & CR8_RESERVED_BITS)
862 return 1;
35754c98 863 if (lapic_in_kernel(vcpu))
a03490ed
CO		 864 kvm_lapic_set_tpr(vcpu, cr8);
865 else
ad312c7c 866 vcpu->arch.cr8 = cr8;
0f12244f
GN		 867 return 0;
868}
2d3ad1f4 869EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 870
2d3ad1f4 871unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 872{
35754c98 873 if (lapic_in_kernel(vcpu))
a03490ed
CO		 874 return kvm_lapic_get_cr8(vcpu);
875 else
ad312c7c 876 return vcpu->arch.cr8;
a03490ed 877}
2d3ad1f4 878EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 879
ae561ede
NA		 880static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
881{
882 int i;
883
884 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
885 for (i = 0; i < KVM_NR_DB_REGS; i++)
886 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
887 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
888 }
889}
890
73aaf249
JK		 891static void kvm_update_dr6(struct kvm_vcpu *vcpu)
892{
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
895}
896
c8639010
JK		 897static void kvm_update_dr7(struct kvm_vcpu *vcpu)
898{
899 unsigned long dr7;
900
901 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
902 dr7 = vcpu->arch.guest_debug_dr7;
903 else
904 dr7 = vcpu->arch.dr7;
905 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 906 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
907 if (dr7 & DR7_BP_EN_MASK)
908 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 909}
910
6f43ed01
NA		 911static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
912{
913 u64 fixed = DR6_FIXED_1;
914
d6321d49 915 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 916 fixed |= DR6_RTM;
917 return fixed;
918}
919
338dbc97 920static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 921{
922 switch (dr) {
923 case 0 ... 3:
924 vcpu->arch.db[dr] = val;
925 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
926 vcpu->arch.eff_db[dr] = val;
927 break;
928 case 4:
020df079
GN		 929 /* fall through */
930 case 6:
338dbc97
GN		 931 if (val & 0xffffffff00000000ULL)
932 return -1; /* #GP */
6f43ed01 933 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 934 kvm_update_dr6(vcpu);
020df079
GN		 935 break;
936 case 5:
020df079
GN		 937 /* fall through */
938 default: /* 7 */
338dbc97
GN		 939 if (val & 0xffffffff00000000ULL)
940 return -1; /* #GP */
020df079 941 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 942 kvm_update_dr7(vcpu);
020df079
GN		 943 break;
944 }
945
946 return 0;
947}
338dbc97
GN		 948
949int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
950{
16f8a6f9 951 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 952 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 953 return 1;
954 }
955 return 0;
338dbc97 956}
020df079
GN		 957EXPORT_SYMBOL_GPL(kvm_set_dr);
958
16f8a6f9 959int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 960{
961 switch (dr) {
962 case 0 ... 3:
963 *val = vcpu->arch.db[dr];
964 break;
965 case 4:
020df079
GN		 966 /* fall through */
967 case 6:
73aaf249
JK		 968 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
969 *val = vcpu->arch.dr6;
970 else
971 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 972 break;
973 case 5:
020df079
GN		 974 /* fall through */
975 default: /* 7 */
976 *val = vcpu->arch.dr7;
977 break;
978 }
338dbc97
GN		 979 return 0;
980}
020df079
GN		 981EXPORT_SYMBOL_GPL(kvm_get_dr);
982
022cd0e8
AK		 983bool kvm_rdpmc(struct kvm_vcpu *vcpu)
984{
985 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
986 u64 data;
987 int err;
988
c6702c9d 989 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 990 if (err)
991 return err;
992 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
993 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
994 return err;
995}
996EXPORT_SYMBOL_GPL(kvm_rdpmc);
997
043405e1
CO		 998/*
999 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1000 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1001 *
1002 * This list is modified at module load time to reflect the
e3267cbb 1003 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1004 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1005 * may depend on host virtualization features rather than host cpu features.
043405e1 1006 */
e3267cbb 1007
043405e1
CO		 1008static u32 msrs_to_save[] = {
1009 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1010 MSR_STAR,
043405e1
CO		 1011#ifdef CONFIG_X86_64
1012 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1013#endif
b3897a49 1014 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1015 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
74469996 1016 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1017};
1018
1019static unsigned num_msrs_to_save;
1020
62ef68bb
PB		 1021static u32 emulated_msrs[] = {
1022 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1023 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1024 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1025 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1026 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1027 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1028 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1029 HV_X64_MSR_RESET,
11c4b1ca 1030 HV_X64_MSR_VP_INDEX,
9eec50b8 1031 HV_X64_MSR_VP_RUNTIME,
5c919412 1032 HV_X64_MSR_SCONTROL,
1f4b34f8 1033 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1034 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1035 MSR_KVM_PV_EOI_EN,
1036
ba904635 1037 MSR_IA32_TSC_ADJUST,
a3e06bbe 1038 MSR_IA32_TSCDEADLINE,
043405e1 1039 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1040 MSR_IA32_MCG_STATUS,
1041 MSR_IA32_MCG_CTL,
c45dcc71 1042 MSR_IA32_MCG_EXT_CTL,
64d60670 1043 MSR_IA32_SMBASE,
db2336a8
KH		 1044 MSR_PLATFORM_INFO,
1045 MSR_MISC_FEATURES_ENABLES,
4d5c8a07 1046 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1047};
1048
62ef68bb
PB		 1049static unsigned num_emulated_msrs;
1050
384bb783 1051bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1052{
b69e8cae 1053 if (efer & efer_reserved_bits)
384bb783 1054 return false;
15c4a640 1055
1b4d56b8 1056 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1057 return false;
1b2fd70c 1058
1b4d56b8 1059 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1060 return false;
d8017474 1061
384bb783
JK		 1062 return true;
1063}
1064EXPORT_SYMBOL_GPL(kvm_valid_efer);
1065
1066static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1067{
1068 u64 old_efer = vcpu->arch.efer;
1069
1070 if (!kvm_valid_efer(vcpu, efer))
1071 return 1;
1072
1073 if (is_paging(vcpu)
1074 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1075 return 1;
1076
15c4a640 1077 efer &= ~EFER_LMA;
f6801dff 1078 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1079
a3d204e2
SY		 1080 kvm_x86_ops->set_efer(vcpu, efer);
1081
aad82703
SY		 1082 /* Update reserved bits */
1083 if ((efer ^ old_efer) & EFER_NX)
1084 kvm_mmu_reset_context(vcpu);
1085
b69e8cae 1086 return 0;
15c4a640
CO		 1087}
1088
f2b4b7dd
JR		 1089void kvm_enable_efer_bits(u64 mask)
1090{
1091 efer_reserved_bits &= ~mask;
1092}
1093EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1094
15c4a640
CO		 1095/*
1096 * Writes msr value into into the appropriate "register".
1097 * Returns 0 on success, non-0 otherwise.
1098 * Assumes vcpu_load() was already called.
1099 */
8fe8ab46 1100int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1101{
854e8bb1
NA		 1102 switch (msr->index) {
1103 case MSR_FS_BASE:
1104 case MSR_GS_BASE:
1105 case MSR_KERNEL_GS_BASE:
1106 case MSR_CSTAR:
1107 case MSR_LSTAR:
fd8cb433 1108 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1109 return 1;
1110 break;
1111 case MSR_IA32_SYSENTER_EIP:
1112 case MSR_IA32_SYSENTER_ESP:
1113 /*
1114 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1115 * non-canonical address is written on Intel but not on
1116 * AMD (which ignores the top 32-bits, because it does
1117 * not implement 64-bit SYSENTER).
1118 *
1119 * 64-bit code should hence be able to write a non-canonical
1120 * value on AMD. Making the address canonical ensures that
1121 * vmentry does not fail on Intel after writing a non-canonical
1122 * value, and that something deterministic happens if the guest
1123 * invokes 64-bit SYSENTER.
1124 */
fd8cb433 1125 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1126 }
8fe8ab46 1127 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1128}
854e8bb1 1129EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1130
313a3dc7
CO		 1131/*
1132 * Adapt set_msr() to msr_io()'s calling convention
1133 */
609e36d3
PB		 1134static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1135{
1136 struct msr_data msr;
1137 int r;
1138
1139 msr.index = index;
1140 msr.host_initiated = true;
1141 r = kvm_get_msr(vcpu, &msr);
1142 if (r)
1143 return r;
1144
1145 *data = msr.data;
1146 return 0;
1147}
1148
313a3dc7
CO		 1149static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1150{
8fe8ab46
WA		 1151 struct msr_data msr;
1152
1153 msr.data = *data;
1154 msr.index = index;
1155 msr.host_initiated = true;
1156 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1157}
1158
16e8d74d
MT		 1159#ifdef CONFIG_X86_64
1160struct pvclock_gtod_data {
1161 seqcount_t seq;
1162
1163 struct { /* extract of a clocksource struct */
1164 int vclock_mode;
a5a1d1c2
TG		 1165 u64 cycle_last;
1166 u64 mask;
16e8d74d
MT		 1167 u32 mult;
1168 u32 shift;
1169 } clock;
1170
cbcf2dd3
TG		 1171 u64 boot_ns;
1172 u64 nsec_base;
55dd00a7 1173 u64 wall_time_sec;
16e8d74d
MT		 1174};
1175
1176static struct pvclock_gtod_data pvclock_gtod_data;
1177
1178static void update_pvclock_gtod(struct timekeeper *tk)
1179{
1180 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1181 u64 boot_ns;
1182
876e7881 1183 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1184
1185 write_seqcount_begin(&vdata->seq);
1186
1187 /* copy pvclock gtod data */
876e7881
PZ		 1188 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1189 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1190 vdata->clock.mask = tk->tkr_mono.mask;
1191 vdata->clock.mult = tk->tkr_mono.mult;
1192 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1193
cbcf2dd3 1194 vdata->boot_ns = boot_ns;
876e7881 1195 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1196
55dd00a7
MT		 1197 vdata->wall_time_sec = tk->xtime_sec;
1198
16e8d74d
MT		 1199 write_seqcount_end(&vdata->seq);
1200}
1201#endif
1202
bab5bb39
NK		 1203void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1204{
1205 /*
1206 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1207 * vcpu_enter_guest. This function is only called from
1208 * the physical CPU that is running vcpu.
1209 */
1210 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1211}
16e8d74d 1212
18068523
GOC		 1213static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1214{
9ed3c444
AK		 1215 int version;
1216 int r;
50d0a0f9 1217 struct pvclock_wall_clock wc;
87aeb54f 1218 struct timespec64 boot;
18068523
GOC		 1219
1220 if (!wall_clock)
1221 return;
1222
9ed3c444
AK		 1223 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1224 if (r)
1225 return;
1226
1227 if (version & 1)
1228 ++version; /* first time write, random junk */
1229
1230 ++version;
18068523 1231
1dab1345
NK		 1232 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1233 return;
18068523 1234
50d0a0f9
GH		 1235 /*
1236 * The guest calculates current wall clock time by adding
34c238a1 1237 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1238 * wall clock specified here. guest system time equals host
1239 * system time for us, thus we must fill in host boot time here.
1240 */
87aeb54f 1241 getboottime64(&boot);
50d0a0f9 1242
4b648665 1243 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1244 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1245 boot = timespec64_sub(boot, ts);
4b648665 1246 }
87aeb54f 1247 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1248 wc.nsec = boot.tv_nsec;
1249 wc.version = version;
18068523
GOC		 1250
1251 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1252
1253 version++;
1254 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1255}
1256
50d0a0f9
GH		 1257static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1258{
b51012de
PB		 1259 do_shl32_div32(dividend, divisor);
1260 return dividend;
50d0a0f9
GH		 1261}
1262
3ae13faa 1263static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1264 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1265{
5f4e3f88 1266 uint64_t scaled64;
50d0a0f9
GH		 1267 int32_t shift = 0;
1268 uint64_t tps64;
1269 uint32_t tps32;
1270
3ae13faa
PB		 1271 tps64 = base_hz;
1272 scaled64 = scaled_hz;
50933623 1273 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1274 tps64 >>= 1;
1275 shift--;
1276 }
1277
1278 tps32 = (uint32_t)tps64;
50933623
JK		 1279 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1280 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1281 scaled64 >>= 1;
1282 else
1283 tps32 <<= 1;
50d0a0f9
GH		 1284 shift++;
1285 }
1286
5f4e3f88
ZA		 1287 *pshift = shift;
1288 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1289
3ae13faa
PB		 1290 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1291 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1292}
1293
d828199e 1294#ifdef CONFIG_X86_64
16e8d74d 1295static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1296#endif
16e8d74d 1297
c8076604 1298static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1299static unsigned long max_tsc_khz;
c8076604 1300
cc578287 1301static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1302{
cc578287
ZA		 1303 u64 v = (u64)khz * (1000000 + ppm);
1304 do_div(v, 1000000);
1305 return v;
1e993611
JR		 1306}
1307
381d585c
HZ		 1308static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1309{
1310 u64 ratio;
1311
1312 /* Guest TSC same frequency as host TSC? */
1313 if (!scale) {
1314 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1315 return 0;
1316 }
1317
1318 /* TSC scaling supported? */
1319 if (!kvm_has_tsc_control) {
1320 if (user_tsc_khz > tsc_khz) {
1321 vcpu->arch.tsc_catchup = 1;
1322 vcpu->arch.tsc_always_catchup = 1;
1323 return 0;
1324 } else {
1325 WARN(1, "user requested TSC rate below hardware speed\n");
1326 return -1;
1327 }
1328 }
1329
1330 /* TSC scaling required - calculate ratio */
1331 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1332 user_tsc_khz, tsc_khz);
1333
1334 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1335 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1336 user_tsc_khz);
1337 return -1;
1338 }
1339
1340 vcpu->arch.tsc_scaling_ratio = ratio;
1341 return 0;
1342}
1343
4941b8cb 1344static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1345{
cc578287
ZA		 1346 u32 thresh_lo, thresh_hi;
1347 int use_scaling = 0;
217fc9cf 1348
03ba32ca 1349 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1350 if (user_tsc_khz == 0) {
ad721883
HZ		 1351 /* set tsc_scaling_ratio to a safe value */
1352 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1353 return -1;
ad721883 1354 }
03ba32ca 1355
c285545f 1356 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1357 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1358 &vcpu->arch.virtual_tsc_shift,
1359 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1360 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1361
1362 /*
1363 * Compute the variation in TSC rate which is acceptable
1364 * within the range of tolerance and decide if the
1365 * rate being applied is within that bounds of the hardware
1366 * rate. If so, no scaling or compensation need be done.
1367 */
1368 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1369 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1370 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1371 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1372 use_scaling = 1;
1373 }
4941b8cb 1374 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1375}
1376
1377static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1378{
e26101b1 1379 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1380 vcpu->arch.virtual_tsc_mult,
1381 vcpu->arch.virtual_tsc_shift);
e26101b1 1382 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1383 return tsc;
1384}
1385
69b0049a 1386static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1387{
1388#ifdef CONFIG_X86_64
1389 bool vcpus_matched;
b48aa97e
MT		 1390 struct kvm_arch *ka = &vcpu->kvm->arch;
1391 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1392
1393 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1394 atomic_read(&vcpu->kvm->online_vcpus));
1395
7f187922
MT		 1396 /*
1397 * Once the masterclock is enabled, always perform request in
1398 * order to update it.
1399 *
1400 * In order to enable masterclock, the host clocksource must be TSC
1401 * and the vcpus need to have matched TSCs. When that happens,
1402 * perform request to enable masterclock.
1403 */
1404 if (ka->use_master_clock ||
1405 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1406 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1407
1408 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1409 atomic_read(&vcpu->kvm->online_vcpus),
1410 ka->use_master_clock, gtod->clock.vclock_mode);
1411#endif
1412}
1413
ba904635
WA		 1414static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1415{
3e3f5026 1416 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1417 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1418}
1419
35181e86
HZ		 1420/*
1421 * Multiply tsc by a fixed point number represented by ratio.
1422 *
1423 * The most significant 64-N bits (mult) of ratio represent the
1424 * integral part of the fixed point number; the remaining N bits
1425 * (frac) represent the fractional part, ie. ratio represents a fixed
1426 * point number (mult + frac * 2^(-N)).
1427 *
1428 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1429 */
1430static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1431{
1432 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1433}
1434
1435u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1436{
1437 u64 _tsc = tsc;
1438 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1439
1440 if (ratio != kvm_default_tsc_scaling_ratio)
1441 _tsc = __scale_tsc(ratio, tsc);
1442
1443 return _tsc;
1444}
1445EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1446
07c1419a
HZ		 1447static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1448{
1449 u64 tsc;
1450
1451 tsc = kvm_scale_tsc(vcpu, rdtsc());
1452
1453 return target_tsc - tsc;
1454}
1455
4ba76538
HZ		 1456u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1457{
ea26e4ec 1458 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1459}
1460EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1461
a545ab6a
LC		 1462static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1463{
1464 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1465 vcpu->arch.tsc_offset = offset;
1466}
1467
8fe8ab46 1468void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1469{
1470 struct kvm *kvm = vcpu->kvm;
f38e098f 1471 u64 offset, ns, elapsed;
99e3e30a 1472 unsigned long flags;
b48aa97e 1473 bool matched;
0d3da0d2 1474 bool already_matched;
8fe8ab46 1475 u64 data = msr->data;
c5e8ec8e 1476 bool synchronizing = false;
99e3e30a 1477
038f8c11 1478 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1479 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1480 ns = ktime_get_boot_ns();
f38e098f 1481 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1482
03ba32ca 1483 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1484 if (data == 0 && msr->host_initiated) {
1485 /*
1486 * detection of vcpu initialization -- need to sync
1487 * with other vCPUs. This particularly helps to keep
1488 * kvm_clock stable after CPU hotplug
1489 */
1490 synchronizing = true;
1491 } else {
1492 u64 tsc_exp = kvm->arch.last_tsc_write +
1493 nsec_to_cycles(vcpu, elapsed);
1494 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1495 /*
1496 * Special case: TSC write with a small delta (1 second)
1497 * of virtual cycle time against real time is
1498 * interpreted as an attempt to synchronize the CPU.
1499 */
1500 synchronizing = data < tsc_exp + tsc_hz &&
1501 data + tsc_hz > tsc_exp;
1502 }
c5e8ec8e 1503 }
f38e098f
ZA		 1504
1505 /*
5d3cb0f6
ZA		 1506 * For a reliable TSC, we can match TSC offsets, and for an unstable
1507 * TSC, we add elapsed time in this computation. We could let the
1508 * compensation code attempt to catch up if we fall behind, but
1509 * it's better to try to match offsets from the beginning.
1510 */
c5e8ec8e 1511 if (synchronizing &&
5d3cb0f6 1512 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1513 if (!check_tsc_unstable()) {
e26101b1 1514 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1515 pr_debug("kvm: matched tsc offset for %llu\n", data);
1516 } else {
857e4099 1517 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1518 data += delta;
07c1419a 1519 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1520 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1521 }
b48aa97e 1522 matched = true;
0d3da0d2 1523 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1524 } else {
1525 /*
1526 * We split periods of matched TSC writes into generations.
1527 * For each generation, we track the original measured
1528 * nanosecond time, offset, and write, so if TSCs are in
1529 * sync, we can match exact offset, and if not, we can match
4a969980 1530 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1531 *
1532 * These values are tracked in kvm->arch.cur_xxx variables.
1533 */
1534 kvm->arch.cur_tsc_generation++;
1535 kvm->arch.cur_tsc_nsec = ns;
1536 kvm->arch.cur_tsc_write = data;
1537 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1538 matched = false;
0d3da0d2 1539 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1540 kvm->arch.cur_tsc_generation, data);
f38e098f 1541 }
e26101b1
ZA		 1542
1543 /*
1544 * We also track th most recent recorded KHZ, write and time to
1545 * allow the matching interval to be extended at each write.
1546 */
f38e098f
ZA		 1547 kvm->arch.last_tsc_nsec = ns;
1548 kvm->arch.last_tsc_write = data;
5d3cb0f6 1549 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1550
b183aa58 1551 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1552
1553 /* Keep track of which generation this VCPU has synchronized to */
1554 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1555 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1556 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1557
d6321d49 1558 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1559 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1560
a545ab6a 1561 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1562 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1563
1564 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1565 if (!matched) {
b48aa97e 1566 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1567 } else if (!already_matched) {
1568 kvm->arch.nr_vcpus_matched_tsc++;
1569 }
b48aa97e
MT		 1570
1571 kvm_track_tsc_matching(vcpu);
1572 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1573}
e26101b1 1574
99e3e30a
ZA		 1575EXPORT_SYMBOL_GPL(kvm_write_tsc);
1576
58ea6767
HZ		 1577static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1578 s64 adjustment)
1579{
ea26e4ec 1580 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1581}
1582
1583static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1584{
1585 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1586 WARN_ON(adjustment < 0);
1587 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1588 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1589}
1590
d828199e
MT		 1591#ifdef CONFIG_X86_64
1592
a5a1d1c2 1593static u64 read_tsc(void)
d828199e 1594{
a5a1d1c2 1595 u64 ret = (u64)rdtsc_ordered();
03b9730b 1596 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1597
1598 if (likely(ret >= last))
1599 return ret;
1600
1601 /*
1602 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1603 * predictable (it's just a function of time and the likely is
d828199e
MT		 1604 * very likely) and there's a data dependence, so force GCC
1605 * to generate a branch instead. I don't barrier() because
1606 * we don't actually need a barrier, and if this function
1607 * ever gets inlined it will generate worse code.
1608 */
1609 asm volatile ("");
1610 return last;
1611}
1612
a5a1d1c2 1613static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1614{
1615 long v;
1616 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1617
1618 *cycle_now = read_tsc();
1619
1620 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1621 return v * gtod->clock.mult;
1622}
1623
a5a1d1c2 1624static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1625{
cbcf2dd3 1626 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1627 unsigned long seq;
d828199e 1628 int mode;
cbcf2dd3 1629 u64 ns;
d828199e 1630
d828199e
MT		 1631 do {
1632 seq = read_seqcount_begin(&gtod->seq);
1633 mode = gtod->clock.vclock_mode;
cbcf2dd3 1634 ns = gtod->nsec_base;
d828199e
MT		 1635 ns += vgettsc(cycle_now);
1636 ns >>= gtod->clock.shift;
cbcf2dd3 1637 ns += gtod->boot_ns;
d828199e 1638 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1639 *t = ns;
d828199e
MT		 1640
1641 return mode;
1642}
1643
55dd00a7
MT		 1644static int do_realtime(struct timespec *ts, u64 *cycle_now)
1645{
1646 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1647 unsigned long seq;
1648 int mode;
1649 u64 ns;
1650
1651 do {
1652 seq = read_seqcount_begin(&gtod->seq);
1653 mode = gtod->clock.vclock_mode;
1654 ts->tv_sec = gtod->wall_time_sec;
1655 ns = gtod->nsec_base;
1656 ns += vgettsc(cycle_now);
1657 ns >>= gtod->clock.shift;
1658 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1659
1660 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1661 ts->tv_nsec = ns;
1662
1663 return mode;
1664}
1665
d828199e 1666/* returns true if host is using tsc clocksource */
a5a1d1c2 1667static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1668{
d828199e
MT		 1669 /* checked again under seqlock below */
1670 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1671 return false;
1672
cbcf2dd3 1673 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1674}
55dd00a7
MT		 1675
1676/* returns true if host is using tsc clocksource */
1677static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1678 u64 *cycle_now)
1679{
1680 /* checked again under seqlock below */
1681 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1682 return false;
1683
1684 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1685}
d828199e
MT		 1686#endif
1687
1688/*
1689 *
b48aa97e
MT		 1690 * Assuming a stable TSC across physical CPUS, and a stable TSC
1691 * across virtual CPUs, the following condition is possible.
1692 * Each numbered line represents an event visible to both
d828199e
MT		 1693 * CPUs at the next numbered event.
1694 *
1695 * "timespecX" represents host monotonic time. "tscX" represents
1696 * RDTSC value.
1697 *
1698 * VCPU0 on CPU0 | VCPU1 on CPU1
1699 *
1700 * 1. read timespec0,tsc0
1701 * 2. | timespec1 = timespec0 + N
1702 * | tsc1 = tsc0 + M
1703 * 3. transition to guest | transition to guest
1704 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1705 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1706 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1707 *
1708 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1709 *
1710 * - ret0 < ret1
1711 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1712 * ...
1713 * - 0 < N - M => M < N
1714 *
1715 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1716 * always the case (the difference between two distinct xtime instances
1717 * might be smaller then the difference between corresponding TSC reads,
1718 * when updating guest vcpus pvclock areas).
1719 *
1720 * To avoid that problem, do not allow visibility of distinct
1721 * system_timestamp/tsc_timestamp values simultaneously: use a master
1722 * copy of host monotonic time values. Update that master copy
1723 * in lockstep.
1724 *
b48aa97e 1725 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1726 *
1727 */
1728
1729static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1730{
1731#ifdef CONFIG_X86_64
1732 struct kvm_arch *ka = &kvm->arch;
1733 int vclock_mode;
b48aa97e
MT		 1734 bool host_tsc_clocksource, vcpus_matched;
1735
1736 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1737 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1738
1739 /*
1740 * If the host uses TSC clock, then passthrough TSC as stable
1741 * to the guest.
1742 */
b48aa97e 1743 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1744 &ka->master_kernel_ns,
1745 &ka->master_cycle_now);
1746
16a96021 1747 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1748 && !ka->backwards_tsc_observed
54750f2c 1749 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1750
d828199e
MT		 1751 if (ka->use_master_clock)
1752 atomic_set(&kvm_guest_has_master_clock, 1);
1753
1754 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1755 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1756 vcpus_matched);
d828199e
MT		 1757#endif
1758}
1759
2860c4b1
PB		 1760void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1761{
1762 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1763}
1764
2e762ff7
MT		 1765static void kvm_gen_update_masterclock(struct kvm *kvm)
1766{
1767#ifdef CONFIG_X86_64
1768 int i;
1769 struct kvm_vcpu *vcpu;
1770 struct kvm_arch *ka = &kvm->arch;
1771
1772 spin_lock(&ka->pvclock_gtod_sync_lock);
1773 kvm_make_mclock_inprogress_request(kvm);
1774 /* no guest entries from this point */
1775 pvclock_update_vm_gtod_copy(kvm);
1776
1777 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1778 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1779
1780 /* guest entries allowed */
1781 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1782 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1783
1784 spin_unlock(&ka->pvclock_gtod_sync_lock);
1785#endif
1786}
1787
e891a32e 1788u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1789{
108b249c 1790 struct kvm_arch *ka = &kvm->arch;
8b953440 1791 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1792 u64 ret;
108b249c 1793
8b953440
PB		 1794 spin_lock(&ka->pvclock_gtod_sync_lock);
1795 if (!ka->use_master_clock) {
1796 spin_unlock(&ka->pvclock_gtod_sync_lock);
1797 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1798 }
1799
8b953440
PB		 1800 hv_clock.tsc_timestamp = ka->master_cycle_now;
1801 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1802 spin_unlock(&ka->pvclock_gtod_sync_lock);
1803
e2c2206a
WL		 1804 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1805 get_cpu();
1806
e70b57a6
WL		 1807 if (__this_cpu_read(cpu_tsc_khz)) {
1808 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1809 &hv_clock.tsc_shift,
1810 &hv_clock.tsc_to_system_mul);
1811 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1812 } else
1813 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1814
1815 put_cpu();
1816
1817 return ret;
108b249c
PB		 1818}
1819
0d6dd2ff
PB		 1820static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1821{
1822 struct kvm_vcpu_arch *vcpu = &v->arch;
1823 struct pvclock_vcpu_time_info guest_hv_clock;
1824
4e335d9e 1825 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1826 &guest_hv_clock, sizeof(guest_hv_clock))))
1827 return;
1828
1829 /* This VCPU is paused, but it's legal for a guest to read another
1830 * VCPU's kvmclock, so we really have to follow the specification where
1831 * it says that version is odd if data is being modified, and even after
1832 * it is consistent.
1833 *
1834 * Version field updates must be kept separate. This is because
1835 * kvm_write_guest_cached might use a "rep movs" instruction, and
1836 * writes within a string instruction are weakly ordered. So there
1837 * are three writes overall.
1838 *
1839 * As a small optimization, only write the version field in the first
1840 * and third write. The vcpu->pv_time cache is still valid, because the
1841 * version field is the first in the struct.
1842 */
1843 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1844
51c4b8bb
LA		 1845 if (guest_hv_clock.version & 1)
1846 ++guest_hv_clock.version; /* first time write, random junk */
1847
0d6dd2ff 1848 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1849 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1850 &vcpu->hv_clock,
1851 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1852
1853 smp_wmb();
1854
1855 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1856 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1857
1858 if (vcpu->pvclock_set_guest_stopped_request) {
1859 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1860 vcpu->pvclock_set_guest_stopped_request = false;
1861 }
1862
1863 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1864
4e335d9e
PB		 1865 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1866 &vcpu->hv_clock,
1867 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1868
1869 smp_wmb();
1870
1871 vcpu->hv_clock.version++;
4e335d9e
PB		 1872 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1873 &vcpu->hv_clock,
1874 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1875}
1876
34c238a1 1877static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1878{
78db6a50 1879 unsigned long flags, tgt_tsc_khz;
18068523 1880 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1881 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1882 s64 kernel_ns;
d828199e 1883 u64 tsc_timestamp, host_tsc;
51d59c6b 1884 u8 pvclock_flags;
d828199e
MT		 1885 bool use_master_clock;
1886
1887 kernel_ns = 0;
1888 host_tsc = 0;
18068523 1889
d828199e
MT		 1890 /*
1891 * If the host uses TSC clock, then passthrough TSC as stable
1892 * to the guest.
1893 */
1894 spin_lock(&ka->pvclock_gtod_sync_lock);
1895 use_master_clock = ka->use_master_clock;
1896 if (use_master_clock) {
1897 host_tsc = ka->master_cycle_now;
1898 kernel_ns = ka->master_kernel_ns;
1899 }
1900 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1901
1902 /* Keep irq disabled to prevent changes to the clock */
1903 local_irq_save(flags);
78db6a50
PB		 1904 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1905 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1906 local_irq_restore(flags);
1907 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1908 return 1;
1909 }
d828199e 1910 if (!use_master_clock) {
4ea1636b 1911 host_tsc = rdtsc();
108b249c 1912 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1913 }
1914
4ba76538 1915 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1916
c285545f
ZA		 1917 /*
1918 * We may have to catch up the TSC to match elapsed wall clock
1919 * time for two reasons, even if kvmclock is used.
1920 * 1) CPU could have been running below the maximum TSC rate
1921 * 2) Broken TSC compensation resets the base at each VCPU
1922 * entry to avoid unknown leaps of TSC even when running
1923 * again on the same CPU. This may cause apparent elapsed
1924 * time to disappear, and the guest to stand still or run
1925 * very slowly.
1926 */
1927 if (vcpu->tsc_catchup) {
1928 u64 tsc = compute_guest_tsc(v, kernel_ns);
1929 if (tsc > tsc_timestamp) {
f1e2b260 1930 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1931 tsc_timestamp = tsc;
1932 }
50d0a0f9
GH		 1933 }
1934
18068523
GOC		 1935 local_irq_restore(flags);
1936
0d6dd2ff 1937 /* With all the info we got, fill in the values */
18068523 1938
78db6a50
PB		 1939 if (kvm_has_tsc_control)
1940 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1941
1942 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1943 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1944 &vcpu->hv_clock.tsc_shift,
1945 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1946 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1947 }
1948
1d5f066e 1949 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1950 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1951 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1952
d828199e 1953 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1954 pvclock_flags = 0;
d828199e
MT		 1955 if (use_master_clock)
1956 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1957
78c0337a
MT		 1958 vcpu->hv_clock.flags = pvclock_flags;
1959
095cf55d
PB		 1960 if (vcpu->pv_time_enabled)
1961 kvm_setup_pvclock_page(v);
1962 if (v == kvm_get_vcpu(v->kvm, 0))
1963 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1964 return 0;
c8076604
GH		 1965}
1966
0061d53d
MT		 1967/*
1968 * kvmclock updates which are isolated to a given vcpu, such as
1969 * vcpu->cpu migration, should not allow system_timestamp from
1970 * the rest of the vcpus to remain static. Otherwise ntp frequency
1971 * correction applies to one vcpu's system_timestamp but not
1972 * the others.
1973 *
1974 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1975 * We need to rate-limit these requests though, as they can
1976 * considerably slow guests that have a large number of vcpus.
1977 * The time for a remote vcpu to update its kvmclock is bound
1978 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1979 */
1980
7e44e449
AJ		 1981#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1982
1983static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1984{
1985 int i;
7e44e449
AJ		 1986 struct delayed_work *dwork = to_delayed_work(work);
1987 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1988 kvmclock_update_work);
1989 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1990 struct kvm_vcpu *vcpu;
1991
1992 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1993 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1994 kvm_vcpu_kick(vcpu);
1995 }
1996}
1997
7e44e449
AJ		 1998static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1999{
2000 struct kvm *kvm = v->kvm;
2001
105b21bb 2002 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2003 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2004 KVMCLOCK_UPDATE_DELAY);
2005}
2006
332967a3
AJ		 2007#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2008
2009static void kvmclock_sync_fn(struct work_struct *work)
2010{
2011 struct delayed_work *dwork = to_delayed_work(work);
2012 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2013 kvmclock_sync_work);
2014 struct kvm *kvm = container_of(ka, struct kvm, arch);
2015
630994b3
MT		 2016 if (!kvmclock_periodic_sync)
2017 return;
2018
332967a3
AJ		 2019 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2020 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2021 KVMCLOCK_SYNC_PERIOD);
2022}
2023
9ffd986c 2024static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2025{
890ca9ae
HY		 2026 u64 mcg_cap = vcpu->arch.mcg_cap;
2027 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2028 u32 msr = msr_info->index;
2029 u64 data = msr_info->data;
890ca9ae 2030
15c4a640 2031 switch (msr) {
15c4a640 2032 case MSR_IA32_MCG_STATUS:
890ca9ae 2033 vcpu->arch.mcg_status = data;
15c4a640 2034 break;
c7ac679c 2035 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2036 if (!(mcg_cap & MCG_CTL_P))
2037 return 1;
2038 if (data != 0 && data != ~(u64)0)
2039 return -1;
2040 vcpu->arch.mcg_ctl = data;
2041 break;
2042 default:
2043 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2044 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2045 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2046 /* only 0 or all 1s can be written to IA32_MCi_CTL
2047 * some Linux kernels though clear bit 10 in bank 4 to
2048 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2049 * this to avoid an uncatched #GP in the guest
2050 */
890ca9ae 2051 if ((offset & 0x3) == 0 &&
114be429 2052 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2053 return -1;
9ffd986c
WL		 2054 if (!msr_info->host_initiated &&
2055 (offset & 0x3) == 1 && data != 0)
2056 return -1;
890ca9ae
HY		 2057 vcpu->arch.mce_banks[offset] = data;
2058 break;
2059 }
2060 return 1;
2061 }
2062 return 0;
2063}
2064
ffde22ac
ES		 2065static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2066{
2067 struct kvm *kvm = vcpu->kvm;
2068 int lm = is_long_mode(vcpu);
2069 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2070 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2071 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2072 : kvm->arch.xen_hvm_config.blob_size_32;
2073 u32 page_num = data & ~PAGE_MASK;
2074 u64 page_addr = data & PAGE_MASK;
2075 u8 *page;
2076 int r;
2077
2078 r = -E2BIG;
2079 if (page_num >= blob_size)
2080 goto out;
2081 r = -ENOMEM;
ff5c2c03
SL		 2082 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2083 if (IS_ERR(page)) {
2084 r = PTR_ERR(page);
ffde22ac 2085 goto out;
ff5c2c03 2086 }
54bf36aa 2087 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2088 goto out_free;
2089 r = 0;
2090out_free:
2091 kfree(page);
2092out:
2093 return r;
2094}
2095
344d9588
GN		 2096static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2097{
2098 gpa_t gpa = data & ~0x3f;
2099
52a5c155
WL		 2100 /* Bits 3:5 are reserved, Should be zero */
2101 if (data & 0x38)
344d9588
GN		 2102 return 1;
2103
2104 vcpu->arch.apf.msr_val = data;
2105
2106 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2107 kvm_clear_async_pf_completion_queue(vcpu);
2108 kvm_async_pf_hash_reset(vcpu);
2109 return 0;
2110 }
2111
4e335d9e 2112 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2113 sizeof(u32)))
344d9588
GN		 2114 return 1;
2115
6adba527 2116 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2117 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2118 kvm_async_pf_wakeup_all(vcpu);
2119 return 0;
2120}
2121
12f9a48f
GC		 2122static void kvmclock_reset(struct kvm_vcpu *vcpu)
2123{
0b79459b 2124 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2125}
2126
c9aaa895
GC		 2127static void record_steal_time(struct kvm_vcpu *vcpu)
2128{
2129 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2130 return;
2131
4e335d9e 2132 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2133 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2134 return;
2135
0b9f6c46
PX		 2136 vcpu->arch.st.steal.preempted = 0;
2137
35f3fae1
WL		 2138 if (vcpu->arch.st.steal.version & 1)
2139 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2140
2141 vcpu->arch.st.steal.version += 1;
2142
4e335d9e 2143 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2144 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2145
2146 smp_wmb();
2147
c54cdf14
LC		 2148 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2149 vcpu->arch.st.last_steal;
2150 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2151
4e335d9e 2152 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2153 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2154
2155 smp_wmb();
2156
2157 vcpu->arch.st.steal.version += 1;
c9aaa895 2158
4e335d9e 2159 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2160 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2161}
2162
8fe8ab46 2163int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2164{
5753785f 2165 bool pr = false;
8fe8ab46
WA		 2166 u32 msr = msr_info->index;
2167 u64 data = msr_info->data;
5753785f 2168
15c4a640 2169 switch (msr) {
2e32b719
BP		 2170 case MSR_AMD64_NB_CFG:
2171 case MSR_IA32_UCODE_REV:
2172 case MSR_IA32_UCODE_WRITE:
2173 case MSR_VM_HSAVE_PA:
2174 case MSR_AMD64_PATCH_LOADER:
2175 case MSR_AMD64_BU_CFG2:
405a353a 2176 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2177 break;
2178
15c4a640 2179 case MSR_EFER:
b69e8cae 2180 return set_efer(vcpu, data);
8f1589d9
AP		 2181 case MSR_K7_HWCR:
2182 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2183 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2184 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2185 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2186 if (data != 0) {
a737f256
CD		 2187 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2188 data);
8f1589d9
AP		 2189 return 1;
2190 }
15c4a640 2191 break;
f7c6d140
AP		 2192 case MSR_FAM10H_MMIO_CONF_BASE:
2193 if (data != 0) {
a737f256
CD		 2194 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2195 "0x%llx\n", data);
f7c6d140
AP		 2196 return 1;
2197 }
15c4a640 2198 break;
b5e2fec0
AG		 2199 case MSR_IA32_DEBUGCTLMSR:
2200 if (!data) {
2201 /* We support the non-activated case already */
2202 break;
2203 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2204 /* Values other than LBR and BTF are vendor-specific,
2205 thus reserved and should throw a #GP */
2206 return 1;
2207 }
a737f256
CD		 2208 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2209 __func__, data);
b5e2fec0 2210 break;
9ba075a6 2211 case 0x200 ... 0x2ff:
ff53604b 2212 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2213 case MSR_IA32_APICBASE:
58cb628d 2214 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2215 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2216 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2217 case MSR_IA32_TSCDEADLINE:
2218 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2219 break;
ba904635 2220 case MSR_IA32_TSC_ADJUST:
d6321d49 2221 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2222 if (!msr_info->host_initiated) {
d913b904 2223 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2224 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2225 }
2226 vcpu->arch.ia32_tsc_adjust_msr = data;
2227 }
2228 break;
15c4a640 2229 case MSR_IA32_MISC_ENABLE:
ad312c7c 2230 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2231 break;
64d60670
PB		 2232 case MSR_IA32_SMBASE:
2233 if (!msr_info->host_initiated)
2234 return 1;
2235 vcpu->arch.smbase = data;
2236 break;
11c6bffa 2237 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2238 case MSR_KVM_WALL_CLOCK:
2239 vcpu->kvm->arch.wall_clock = data;
2240 kvm_write_wall_clock(vcpu->kvm, data);
2241 break;
11c6bffa 2242 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2243 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2244 struct kvm_arch *ka = &vcpu->kvm->arch;
2245
12f9a48f 2246 kvmclock_reset(vcpu);
18068523 2247
54750f2c
MT		 2248 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2249 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2250
2251 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2252 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2253
2254 ka->boot_vcpu_runs_old_kvmclock = tmp;
2255 }
2256
18068523 2257 vcpu->arch.time = data;
0061d53d 2258 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2259
2260 /* we verify if the enable bit is set... */
2261 if (!(data & 1))
2262 break;
2263
4e335d9e 2264 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2265 &vcpu->arch.pv_time, data & ~1ULL,
2266 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2267 vcpu->arch.pv_time_enabled = false;
2268 else
2269 vcpu->arch.pv_time_enabled = true;
32cad84f 2270
18068523
GOC		 2271 break;
2272 }
344d9588
GN		 2273 case MSR_KVM_ASYNC_PF_EN:
2274 if (kvm_pv_enable_async_pf(vcpu, data))
2275 return 1;
2276 break;
c9aaa895
GC		 2277 case MSR_KVM_STEAL_TIME:
2278
2279 if (unlikely(!sched_info_on()))
2280 return 1;
2281
2282 if (data & KVM_STEAL_RESERVED_MASK)
2283 return 1;
2284
4e335d9e 2285 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2286 data & KVM_STEAL_VALID_BITS,
2287 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2288 return 1;
2289
2290 vcpu->arch.st.msr_val = data;
2291
2292 if (!(data & KVM_MSR_ENABLED))
2293 break;
2294
c9aaa895
GC		 2295 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2296
2297 break;
ae7a2a3f
MT		 2298 case MSR_KVM_PV_EOI_EN:
2299 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2300 return 1;
2301 break;
c9aaa895 2302
890ca9ae
HY		 2303 case MSR_IA32_MCG_CTL:
2304 case MSR_IA32_MCG_STATUS:
81760dcc 2305 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2306 return set_msr_mce(vcpu, msr_info);
71db6023 2307
6912ac32
WH		 2308 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2309 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2310 pr = true; /* fall through */
2311 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2312 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2313 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2314 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2315
2316 if (pr || data != 0)
a737f256
CD		 2317 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2318 "0x%x data 0x%llx\n", msr, data);
5753785f 2319 break;
84e0cefa
JS		 2320 case MSR_K7_CLK_CTL:
2321 /*
2322 * Ignore all writes to this no longer documented MSR.
2323 * Writes are only relevant for old K7 processors,
2324 * all pre-dating SVM, but a recommended workaround from
4a969980 2325 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2326 * affected processor models on the command line, hence
2327 * the need to ignore the workaround.
2328 */
2329 break;
55cd8e5a 2330 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2331 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2332 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2333 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2334 return kvm_hv_set_msr_common(vcpu, msr, data,
2335 msr_info->host_initiated);
91c9c3ed 2336 case MSR_IA32_BBL_CR_CTL3:
2337 /* Drop writes to this legacy MSR -- see rdmsr
2338 * counterpart for further detail.
2339 */
fab0aa3b
EM		 2340 if (report_ignored_msrs)
2341 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2342 msr, data);
91c9c3ed 2343 break;
2b036c6b 2344 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2345 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2346 return 1;
2347 vcpu->arch.osvw.length = data;
2348 break;
2349 case MSR_AMD64_OSVW_STATUS:
d6321d49 2350 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2351 return 1;
2352 vcpu->arch.osvw.status = data;
2353 break;
db2336a8
KH		 2354 case MSR_PLATFORM_INFO:
2355 if (!msr_info->host_initiated ||
2356 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2357 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2358 cpuid_fault_enabled(vcpu)))
2359 return 1;
2360 vcpu->arch.msr_platform_info = data;
2361 break;
2362 case MSR_MISC_FEATURES_ENABLES:
2363 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2364 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2365 !supports_cpuid_fault(vcpu)))
2366 return 1;
2367 vcpu->arch.msr_misc_features_enables = data;
2368 break;
15c4a640 2369 default:
ffde22ac
ES		 2370 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2371 return xen_hvm_config(vcpu, data);
c6702c9d 2372 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2373 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2374 if (!ignore_msrs) {
ae0f5499 2375 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2376 msr, data);
ed85c068
AP		 2377 return 1;
2378 } else {
fab0aa3b
EM		 2379 if (report_ignored_msrs)
2380 vcpu_unimpl(vcpu,
2381 "ignored wrmsr: 0x%x data 0x%llx\n",
2382 msr, data);
ed85c068
AP		 2383 break;
2384 }
15c4a640
CO		 2385 }
2386 return 0;
2387}
2388EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2389
2390
2391/*
2392 * Reads an msr value (of 'msr_index') into 'pdata'.
2393 * Returns 0 on success, non-0 otherwise.
2394 * Assumes vcpu_load() was already called.
2395 */
609e36d3 2396int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2397{
609e36d3 2398 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2399}
ff651cb6 2400EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2401
890ca9ae 2402static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2403{
2404 u64 data;
890ca9ae
HY		 2405 u64 mcg_cap = vcpu->arch.mcg_cap;
2406 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2407
2408 switch (msr) {
15c4a640
CO		 2409 case MSR_IA32_P5_MC_ADDR:
2410 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2411 data = 0;
2412 break;
15c4a640 2413 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2414 data = vcpu->arch.mcg_cap;
2415 break;
c7ac679c 2416 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2417 if (!(mcg_cap & MCG_CTL_P))
2418 return 1;
2419 data = vcpu->arch.mcg_ctl;
2420 break;
2421 case MSR_IA32_MCG_STATUS:
2422 data = vcpu->arch.mcg_status;
2423 break;
2424 default:
2425 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2426 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2427 u32 offset = msr - MSR_IA32_MC0_CTL;
2428 data = vcpu->arch.mce_banks[offset];
2429 break;
2430 }
2431 return 1;
2432 }
2433 *pdata = data;
2434 return 0;
2435}
2436
609e36d3 2437int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2438{
609e36d3 2439 switch (msr_info->index) {
890ca9ae 2440 case MSR_IA32_PLATFORM_ID:
15c4a640 2441 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2442 case MSR_IA32_DEBUGCTLMSR:
2443 case MSR_IA32_LASTBRANCHFROMIP:
2444 case MSR_IA32_LASTBRANCHTOIP:
2445 case MSR_IA32_LASTINTFROMIP:
2446 case MSR_IA32_LASTINTTOIP:
60af2ecd 2447 case MSR_K8_SYSCFG:
3afb1121
PB		 2448 case MSR_K8_TSEG_ADDR:
2449 case MSR_K8_TSEG_MASK:
60af2ecd 2450 case MSR_K7_HWCR:
61a6bd67 2451 case MSR_VM_HSAVE_PA:
1fdbd48c 2452 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2453 case MSR_AMD64_NB_CFG:
f7c6d140 2454 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2455 case MSR_AMD64_BU_CFG2:
0c2df2a1 2456 case MSR_IA32_PERF_CTL:
405a353a 2457 case MSR_AMD64_DC_CFG:
609e36d3 2458 msr_info->data = 0;
15c4a640 2459 break;
6912ac32
WH		 2460 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2461 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2462 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2463 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2464 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2465 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2466 msr_info->data = 0;
5753785f 2467 break;
742bc670 2468 case MSR_IA32_UCODE_REV:
609e36d3 2469 msr_info->data = 0x100000000ULL;
742bc670 2470 break;
9ba075a6 2471 case MSR_MTRRcap:
9ba075a6 2472 case 0x200 ... 0x2ff:
ff53604b 2473 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2474 case 0xcd: /* fsb frequency */
609e36d3 2475 msr_info->data = 3;
15c4a640 2476 break;
7b914098
JS		 2477 /*
2478 * MSR_EBC_FREQUENCY_ID
2479 * Conservative value valid for even the basic CPU models.
2480 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2481 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2482 * and 266MHz for model 3, or 4. Set Core Clock
2483 * Frequency to System Bus Frequency Ratio to 1 (bits
2484 * 31:24) even though these are only valid for CPU
2485 * models > 2, however guests may end up dividing or
2486 * multiplying by zero otherwise.
2487 */
2488 case MSR_EBC_FREQUENCY_ID:
609e36d3 2489 msr_info->data = 1 << 24;
7b914098 2490 break;
15c4a640 2491 case MSR_IA32_APICBASE:
609e36d3 2492 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2493 break;
0105d1a5 2494 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2495 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2496 break;
a3e06bbe 2497 case MSR_IA32_TSCDEADLINE:
609e36d3 2498 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2499 break;
ba904635 2500 case MSR_IA32_TSC_ADJUST:
609e36d3 2501 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2502 break;
15c4a640 2503 case MSR_IA32_MISC_ENABLE:
609e36d3 2504 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2505 break;
64d60670
PB		 2506 case MSR_IA32_SMBASE:
2507 if (!msr_info->host_initiated)
2508 return 1;
2509 msr_info->data = vcpu->arch.smbase;
15c4a640 2510 break;
847f0ad8
AG		 2511 case MSR_IA32_PERF_STATUS:
2512 /* TSC increment by tick */
609e36d3 2513 msr_info->data = 1000ULL;
847f0ad8 2514 /* CPU multiplier */
b0996ae4 2515 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2516 break;
15c4a640 2517 case MSR_EFER:
609e36d3 2518 msr_info->data = vcpu->arch.efer;
15c4a640 2519 break;
18068523 2520 case MSR_KVM_WALL_CLOCK:
11c6bffa 2521 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2522 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2523 break;
2524 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2525 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2526 msr_info->data = vcpu->arch.time;
18068523 2527 break;
344d9588 2528 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2529 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2530 break;
c9aaa895 2531 case MSR_KVM_STEAL_TIME:
609e36d3 2532 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2533 break;
1d92128f 2534 case MSR_KVM_PV_EOI_EN:
609e36d3 2535 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2536 break;
890ca9ae
HY		 2537 case MSR_IA32_P5_MC_ADDR:
2538 case MSR_IA32_P5_MC_TYPE:
2539 case MSR_IA32_MCG_CAP:
2540 case MSR_IA32_MCG_CTL:
2541 case MSR_IA32_MCG_STATUS:
81760dcc 2542 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2543 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2544 case MSR_K7_CLK_CTL:
2545 /*
2546 * Provide expected ramp-up count for K7. All other
2547 * are set to zero, indicating minimum divisors for
2548 * every field.
2549 *
2550 * This prevents guest kernels on AMD host with CPU
2551 * type 6, model 8 and higher from exploding due to
2552 * the rdmsr failing.
2553 */
609e36d3 2554 msr_info->data = 0x20000000;
84e0cefa 2555 break;
55cd8e5a 2556 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2557 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2558 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2559 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2560 return kvm_hv_get_msr_common(vcpu,
2561 msr_info->index, &msr_info->data);
55cd8e5a 2562 break;
91c9c3ed 2563 case MSR_IA32_BBL_CR_CTL3:
2564 /* This legacy MSR exists but isn't fully documented in current
2565 * silicon. It is however accessed by winxp in very narrow
2566 * scenarios where it sets bit #19, itself documented as
2567 * a "reserved" bit. Best effort attempt to source coherent
2568 * read data here should the balance of the register be
2569 * interpreted by the guest:
2570 *
2571 * L2 cache control register 3: 64GB range, 256KB size,
2572 * enabled, latency 0x1, configured
2573 */
609e36d3 2574 msr_info->data = 0xbe702111;
91c9c3ed 2575 break;
2b036c6b 2576 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2577 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2578 return 1;
609e36d3 2579 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2580 break;
2581 case MSR_AMD64_OSVW_STATUS:
d6321d49 2582 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2583 return 1;
609e36d3 2584 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2585 break;
db2336a8
KH		 2586 case MSR_PLATFORM_INFO:
2587 msr_info->data = vcpu->arch.msr_platform_info;
2588 break;
2589 case MSR_MISC_FEATURES_ENABLES:
2590 msr_info->data = vcpu->arch.msr_misc_features_enables;
2591 break;
15c4a640 2592 default:
c6702c9d 2593 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2594 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2595 if (!ignore_msrs) {
ae0f5499
BD		 2596 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2597 msr_info->index);
ed85c068
AP		 2598 return 1;
2599 } else {
fab0aa3b
EM		 2600 if (report_ignored_msrs)
2601 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2602 msr_info->index);
609e36d3 2603 msr_info->data = 0;
ed85c068
AP		 2604 }
2605 break;
15c4a640 2606 }
15c4a640
CO		 2607 return 0;
2608}
2609EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2610
313a3dc7
CO		 2611/*
2612 * Read or write a bunch of msrs. All parameters are kernel addresses.
2613 *
2614 * @return number of msrs set successfully.
2615 */
2616static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2617 struct kvm_msr_entry *entries,
2618 int (*do_msr)(struct kvm_vcpu *vcpu,
2619 unsigned index, u64 *data))
2620{
f656ce01 2621 int i, idx;
313a3dc7 2622
f656ce01 2623 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2624 for (i = 0; i < msrs->nmsrs; ++i)
2625 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2626 break;
f656ce01 2627 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2628
313a3dc7
CO		 2629 return i;
2630}
2631
2632/*
2633 * Read or write a bunch of msrs. Parameters are user addresses.
2634 *
2635 * @return number of msrs set successfully.
2636 */
2637static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2638 int (*do_msr)(struct kvm_vcpu *vcpu,
2639 unsigned index, u64 *data),
2640 int writeback)
2641{
2642 struct kvm_msrs msrs;
2643 struct kvm_msr_entry *entries;
2644 int r, n;
2645 unsigned size;
2646
2647 r = -EFAULT;
2648 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2649 goto out;
2650
2651 r = -E2BIG;
2652 if (msrs.nmsrs >= MAX_IO_MSRS)
2653 goto out;
2654
313a3dc7 2655 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2656 entries = memdup_user(user_msrs->entries, size);
2657 if (IS_ERR(entries)) {
2658 r = PTR_ERR(entries);
313a3dc7 2659 goto out;
ff5c2c03 2660 }
313a3dc7
CO		 2661
2662 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2663 if (r < 0)
2664 goto out_free;
2665
2666 r = -EFAULT;
2667 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2668 goto out_free;
2669
2670 r = n;
2671
2672out_free:
7a73c028 2673 kfree(entries);
313a3dc7
CO		 2674out:
2675 return r;
2676}
2677
784aa3d7 2678int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2679{
2680 int r;
2681
2682 switch (ext) {
2683 case KVM_CAP_IRQCHIP:
2684 case KVM_CAP_HLT:
2685 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2686 case KVM_CAP_SET_TSS_ADDR:
07716717 2687 case KVM_CAP_EXT_CPUID:
9c15bb1d 2688 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2689 case KVM_CAP_CLOCKSOURCE:
7837699f 2690 case KVM_CAP_PIT:
a28e4f5a 2691 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2692 case KVM_CAP_MP_STATE:
ed848624 2693 case KVM_CAP_SYNC_MMU:
a355c85c 2694 case KVM_CAP_USER_NMI:
52d939a0 2695 case KVM_CAP_REINJECT_CONTROL:
4925663a 2696 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2697 case KVM_CAP_IOEVENTFD:
f848a5a8 2698 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2699 case KVM_CAP_PIT2:
e9f42757 2700 case KVM_CAP_PIT_STATE2:
b927a3ce 2701 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2702 case KVM_CAP_XEN_HVM:
3cfc3092 2703 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2704 case KVM_CAP_HYPERV:
10388a07 2705 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2706 case KVM_CAP_HYPERV_SPIN:
5c919412 2707 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2708 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2709 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2710 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2711 case KVM_CAP_DEBUGREGS:
d2be1651 2712 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2713 case KVM_CAP_XSAVE:
344d9588 2714 case KVM_CAP_ASYNC_PF:
92a1f12d 2715 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2716 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2717 case KVM_CAP_READONLY_MEM:
5f66b620 2718 case KVM_CAP_HYPERV_TIME:
100943c5 2719 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2720 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2721 case KVM_CAP_ENABLE_CAP_VM:
2722 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2723 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2724 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2725 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2726 r = 1;
2727 break;
e3fd9a93
PB		 2728 case KVM_CAP_ADJUST_CLOCK:
2729 r = KVM_CLOCK_TSC_STABLE;
2730 break;
668fffa3
MT		 2731 case KVM_CAP_X86_GUEST_MWAIT:
2732 r = kvm_mwait_in_guest();
2733 break;
6d396b55
PB		 2734 case KVM_CAP_X86_SMM:
2735 /* SMBASE is usually relocated above 1M on modern chipsets,
2736 * and SMM handlers might indeed rely on 4G segment limits,
2737 * so do not report SMM to be available if real mode is
2738 * emulated via vm86 mode. Still, do not go to great lengths
2739 * to avoid userspace's usage of the feature, because it is a
2740 * fringe case that is not enabled except via specific settings
2741 * of the module parameters.
2742 */
4d5c8a07 2743 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2744 break;
774ead3a
AK		 2745 case KVM_CAP_VAPIC:
2746 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2747 break;
f725230a 2748 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2749 r = KVM_SOFT_MAX_VCPUS;
2750 break;
2751 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2752 r = KVM_MAX_VCPUS;
2753 break;
a988b910 2754 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2755 r = KVM_USER_MEM_SLOTS;
a988b910 2756 break;
a68a6a72
MT		 2757 case KVM_CAP_PV_MMU: /* obsolete */
2758 r = 0;
2f333bcb 2759 break;
890ca9ae
HY		 2760 case KVM_CAP_MCE:
2761 r = KVM_MAX_MCE_BANKS;
2762 break;
2d5b5a66 2763 case KVM_CAP_XCRS:
d366bf7e 2764 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2765 break;
92a1f12d
JR		 2766 case KVM_CAP_TSC_CONTROL:
2767 r = kvm_has_tsc_control;
2768 break;
37131313
RK		 2769 case KVM_CAP_X2APIC_API:
2770 r = KVM_X2APIC_API_VALID_FLAGS;
2771 break;
018d00d2
ZX		 2772 default:
2773 r = 0;
2774 break;
2775 }
2776 return r;
2777
2778}
2779
043405e1
CO		 2780long kvm_arch_dev_ioctl(struct file *filp,
2781 unsigned int ioctl, unsigned long arg)
2782{
2783 void __user *argp = (void __user *)arg;
2784 long r;
2785
2786 switch (ioctl) {
2787 case KVM_GET_MSR_INDEX_LIST: {
2788 struct kvm_msr_list __user *user_msr_list = argp;
2789 struct kvm_msr_list msr_list;
2790 unsigned n;
2791
2792 r = -EFAULT;
2793 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2794 goto out;
2795 n = msr_list.nmsrs;
62ef68bb 2796 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2797 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2798 goto out;
2799 r = -E2BIG;
e125e7b6 2800 if (n < msr_list.nmsrs)
043405e1
CO		 2801 goto out;
2802 r = -EFAULT;
2803 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2804 num_msrs_to_save * sizeof(u32)))
2805 goto out;
e125e7b6 2806 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2807 &emulated_msrs,
62ef68bb 2808 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2809 goto out;
2810 r = 0;
2811 break;
2812 }
9c15bb1d
BP		 2813 case KVM_GET_SUPPORTED_CPUID:
2814 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2815 struct kvm_cpuid2 __user *cpuid_arg = argp;
2816 struct kvm_cpuid2 cpuid;
2817
2818 r = -EFAULT;
2819 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2820 goto out;
9c15bb1d
BP		 2821
2822 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2823 ioctl);
674eea0f
AK		 2824 if (r)
2825 goto out;
2826
2827 r = -EFAULT;
2828 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2829 goto out;
2830 r = 0;
2831 break;
2832 }
890ca9ae 2833 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2834 r = -EFAULT;
c45dcc71
AR		 2835 if (copy_to_user(argp, &kvm_mce_cap_supported,
2836 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2837 goto out;
2838 r = 0;
2839 break;
2840 }
043405e1
CO		 2841 default:
2842 r = -EINVAL;
2843 }
2844out:
2845 return r;
2846}
2847
f5f48ee1
SY		 2848static void wbinvd_ipi(void *garbage)
2849{
2850 wbinvd();
2851}
2852
2853static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2854{
e0f0bbc5 2855 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2856}
2857
313a3dc7
CO		 2858void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2859{
f5f48ee1
SY		 2860 /* Address WBINVD may be executed by guest */
2861 if (need_emulate_wbinvd(vcpu)) {
2862 if (kvm_x86_ops->has_wbinvd_exit())
2863 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2864 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2865 smp_call_function_single(vcpu->cpu,
2866 wbinvd_ipi, NULL, 1);
2867 }
2868
313a3dc7 2869 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2870
0dd6a6ed
ZA		 2871 /* Apply any externally detected TSC adjustments (due to suspend) */
2872 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2873 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2874 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2875 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2876 }
8f6055cb 2877
48434c20 2878 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2879 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2880 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2881 if (tsc_delta < 0)
2882 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2883
c285545f 2884 if (check_tsc_unstable()) {
07c1419a 2885 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2886 vcpu->arch.last_guest_tsc);
a545ab6a 2887 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2888 vcpu->arch.tsc_catchup = 1;
c285545f 2889 }
a749e247
PB		 2890
2891 if (kvm_lapic_hv_timer_in_use(vcpu))
2892 kvm_lapic_restart_hv_timer(vcpu);
2893
d98d07ca
MT		 2894 /*
2895 * On a host with synchronized TSC, there is no need to update
2896 * kvmclock on vcpu->cpu migration
2897 */
2898 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2899 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2900 if (vcpu->cpu != cpu)
1bd2009e 2901 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2902 vcpu->cpu = cpu;
6b7d7e76 2903 }
c9aaa895 2904
c9aaa895 2905 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2906}
2907
0b9f6c46
PX		 2908static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2909{
2910 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2911 return;
2912
2913 vcpu->arch.st.steal.preempted = 1;
2914
4e335d9e 2915 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2916 &vcpu->arch.st.steal.preempted,
2917 offsetof(struct kvm_steal_time, preempted),
2918 sizeof(vcpu->arch.st.steal.preempted));
2919}
2920
313a3dc7
CO		 2921void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2922{
cc0d907c 2923 int idx;
de63ad4c
LM		 2924
2925 if (vcpu->preempted)
2926 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2927
931f261b
AA		 2928 /*
2929 * Disable page faults because we're in atomic context here.
2930 * kvm_write_guest_offset_cached() would call might_fault()
2931 * that relies on pagefault_disable() to tell if there's a
2932 * bug. NOTE: the write to guest memory may not go through if
2933 * during postcopy live migration or if there's heavy guest
2934 * paging.
2935 */
2936 pagefault_disable();
cc0d907c
AA		 2937 /*
2938 * kvm_memslots() will be called by
2939 * kvm_write_guest_offset_cached() so take the srcu lock.
2940 */
2941 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2942 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2943 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2944 pagefault_enable();
02daab21 2945 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 2946 vcpu->arch.last_host_tsc = rdtsc();
7046f30e
WL		 2947 /*
2948 * If userspace has set any breakpoints or watchpoints, dr6 is restored
2949 * on every vmexit, but if not, we might have a stale dr6 from the
2950 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
2951 */
2952 set_debugreg(0, 6);
313a3dc7
CO		 2953}
2954
313a3dc7
CO		 2955static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2956 struct kvm_lapic_state *s)
2957{
76dfafd5 2958 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2959 kvm_x86_ops->sync_pir_to_irr(vcpu);
2960
a92e2543 2961 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2962}
2963
2964static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2965 struct kvm_lapic_state *s)
2966{
a92e2543
RK		 2967 int r;
2968
2969 r = kvm_apic_set_state(vcpu, s);
2970 if (r)
2971 return r;
cb142eb7 2972 update_cr8_intercept(vcpu);
313a3dc7
CO		 2973
2974 return 0;
2975}
2976
127a457a
MG		 2977static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2978{
2979 return (!lapic_in_kernel(vcpu) ||
2980 kvm_apic_accept_pic_intr(vcpu));
2981}
2982
782d422b
MG		 2983/*
2984 * if userspace requested an interrupt window, check that the
2985 * interrupt window is open.
2986 *
2987 * No need to exit to userspace if we already have an interrupt queued.
2988 */
2989static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2990{
2991 return kvm_arch_interrupt_allowed(vcpu) &&
2992 !kvm_cpu_has_interrupt(vcpu) &&
2993 !kvm_event_needs_reinjection(vcpu) &&
2994 kvm_cpu_accept_dm_intr(vcpu);
2995}
2996
f77bc6a4
ZX		 2997static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2998 struct kvm_interrupt *irq)
2999{
02cdb50f 3000 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3001 return -EINVAL;
1c1a9ce9
SR		 3002
3003 if (!irqchip_in_kernel(vcpu->kvm)) {
3004 kvm_queue_interrupt(vcpu, irq->irq, false);
3005 kvm_make_request(KVM_REQ_EVENT, vcpu);
3006 return 0;
3007 }
3008
3009 /*
3010 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3011 * fail for in-kernel 8259.
3012 */
3013 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3014 return -ENXIO;
f77bc6a4 3015
1c1a9ce9
SR		 3016 if (vcpu->arch.pending_external_vector != -1)
3017 return -EEXIST;
f77bc6a4 3018
1c1a9ce9 3019 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3020 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3021 return 0;
3022}
3023
c4abb7c9
JK		 3024static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3025{
c4abb7c9 3026 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3027
3028 return 0;
3029}
3030
f077825a
PB		 3031static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3032{
64d60670
PB		 3033 kvm_make_request(KVM_REQ_SMI, vcpu);
3034
f077825a
PB		 3035 return 0;
3036}
3037
b209749f
AK		 3038static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3039 struct kvm_tpr_access_ctl *tac)
3040{
3041 if (tac->flags)
3042 return -EINVAL;
3043 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3044 return 0;
3045}
3046
890ca9ae
HY		 3047static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3048 u64 mcg_cap)
3049{
3050 int r;
3051 unsigned bank_num = mcg_cap & 0xff, bank;
3052
3053 r = -EINVAL;
a9e38c3e 3054 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3055 goto out;
c45dcc71 3056 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3057 goto out;
3058 r = 0;
3059 vcpu->arch.mcg_cap = mcg_cap;
3060 /* Init IA32_MCG_CTL to all 1s */
3061 if (mcg_cap & MCG_CTL_P)
3062 vcpu->arch.mcg_ctl = ~(u64)0;
3063 /* Init IA32_MCi_CTL to all 1s */
3064 for (bank = 0; bank < bank_num; bank++)
3065 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3066
3067 if (kvm_x86_ops->setup_mce)
3068 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3069out:
3070 return r;
3071}
3072
3073static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3074 struct kvm_x86_mce *mce)
3075{
3076 u64 mcg_cap = vcpu->arch.mcg_cap;
3077 unsigned bank_num = mcg_cap & 0xff;
3078 u64 *banks = vcpu->arch.mce_banks;
3079
3080 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3081 return -EINVAL;
3082 /*
3083 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3084 * reporting is disabled
3085 */
3086 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3087 vcpu->arch.mcg_ctl != ~(u64)0)
3088 return 0;
3089 banks += 4 * mce->bank;
3090 /*
3091 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3092 * reporting is disabled for the bank
3093 */
3094 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3095 return 0;
3096 if (mce->status & MCI_STATUS_UC) {
3097 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3098 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3099 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3100 return 0;
3101 }
3102 if (banks[1] & MCI_STATUS_VAL)
3103 mce->status |= MCI_STATUS_OVER;
3104 banks[2] = mce->addr;
3105 banks[3] = mce->misc;
3106 vcpu->arch.mcg_status = mce->mcg_status;
3107 banks[1] = mce->status;
3108 kvm_queue_exception(vcpu, MC_VECTOR);
3109 } else if (!(banks[1] & MCI_STATUS_VAL)
3110 || !(banks[1] & MCI_STATUS_UC)) {
3111 if (banks[1] & MCI_STATUS_VAL)
3112 mce->status |= MCI_STATUS_OVER;
3113 banks[2] = mce->addr;
3114 banks[3] = mce->misc;
3115 banks[1] = mce->status;
3116 } else
3117 banks[1] |= MCI_STATUS_OVER;
3118 return 0;
3119}
3120
3cfc3092
JK		 3121static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3122 struct kvm_vcpu_events *events)
3123{
7460fb4a 3124 process_nmi(vcpu);
664f8e26
WL		 3125 /*
3126 * FIXME: pass injected and pending separately. This is only
3127 * needed for nested virtualization, whose state cannot be
3128 * migrated yet. For now we can combine them.
3129 */
03b82a30 3130 events->exception.injected =
664f8e26
WL		 3131 (vcpu->arch.exception.pending ||
3132 vcpu->arch.exception.injected) &&
03b82a30 3133 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3134 events->exception.nr = vcpu->arch.exception.nr;
3135 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3136 events->exception.pad = 0;
3cfc3092
JK		 3137 events->exception.error_code = vcpu->arch.exception.error_code;
3138
03b82a30
JK		 3139 events->interrupt.injected =
3140 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3141 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3142 events->interrupt.soft = 0;
37ccdcbe 3143 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3144
3145 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3146 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3147 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3148 events->nmi.pad = 0;
3cfc3092 3149
66450a21 3150 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3151
f077825a
PB		 3152 events->smi.smm = is_smm(vcpu);
3153 events->smi.pending = vcpu->arch.smi_pending;
3154 events->smi.smm_inside_nmi =
3155 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3156 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3157
dab4b911 3158 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3159 | KVM_VCPUEVENT_VALID_SHADOW
3160 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3161 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3162}
3163
6ef4e07e
XG		 3164static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3165
3cfc3092
JK		 3166static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3167 struct kvm_vcpu_events *events)
3168{
dab4b911 3169 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3170 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3171 | KVM_VCPUEVENT_VALID_SHADOW
3172 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3173 return -EINVAL;
3174
78e546c8 3175 if (events->exception.injected &&
28d06353
JM		 3176 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3177 is_guest_mode(vcpu)))
78e546c8
PB		 3178 return -EINVAL;
3179
28bf2888
DH		 3180 /* INITs are latched while in SMM */
3181 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3182 (events->smi.smm || events->smi.pending) &&
3183 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3184 return -EINVAL;
3185
7460fb4a 3186 process_nmi(vcpu);
664f8e26 3187 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3188 vcpu->arch.exception.pending = events->exception.injected;
3189 vcpu->arch.exception.nr = events->exception.nr;
3190 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3191 vcpu->arch.exception.error_code = events->exception.error_code;
3192
3193 vcpu->arch.interrupt.pending = events->interrupt.injected;
3194 vcpu->arch.interrupt.nr = events->interrupt.nr;
3195 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3196 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3197 kvm_x86_ops->set_interrupt_shadow(vcpu,
3198 events->interrupt.shadow);
3cfc3092
JK		 3199
3200 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3201 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3202 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3203 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3204
66450a21 3205 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3206 lapic_in_kernel(vcpu))
66450a21 3207 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3208
f077825a 3209 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3210 u32 hflags = vcpu->arch.hflags;
f077825a 3211 if (events->smi.smm)
6ef4e07e 3212 hflags |= HF_SMM_MASK;
f077825a 3213 else
6ef4e07e
XG		 3214 hflags &= ~HF_SMM_MASK;
3215 kvm_set_hflags(vcpu, hflags);
3216
f077825a 3217 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3218
3219 if (events->smi.smm) {
3220 if (events->smi.smm_inside_nmi)
3221 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3222 else
f4ef1910
WL		 3223 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3224 if (lapic_in_kernel(vcpu)) {
3225 if (events->smi.latched_init)
3226 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3227 else
3228 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3229 }
f077825a
PB		 3230 }
3231 }
3232
3842d135
AK		 3233 kvm_make_request(KVM_REQ_EVENT, vcpu);
3234
3cfc3092
JK		 3235 return 0;
3236}
3237
a1efbe77
JK		 3238static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3239 struct kvm_debugregs *dbgregs)
3240{
73aaf249
JK		 3241 unsigned long val;
3242
a1efbe77 3243 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3244 kvm_get_dr(vcpu, 6, &val);
73aaf249 3245 dbgregs->dr6 = val;
a1efbe77
JK		 3246 dbgregs->dr7 = vcpu->arch.dr7;
3247 dbgregs->flags = 0;
97e69aa6 3248 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3249}
3250
3251static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3252 struct kvm_debugregs *dbgregs)
3253{
3254 if (dbgregs->flags)
3255 return -EINVAL;
3256
d14bdb55
PB		 3257 if (dbgregs->dr6 & ~0xffffffffull)
3258 return -EINVAL;
3259 if (dbgregs->dr7 & ~0xffffffffull)
3260 return -EINVAL;
3261
a1efbe77 3262 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3263 kvm_update_dr0123(vcpu);
a1efbe77 3264 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3265 kvm_update_dr6(vcpu);
a1efbe77 3266 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3267 kvm_update_dr7(vcpu);
a1efbe77 3268
a1efbe77
JK		 3269 return 0;
3270}
3271
df1daba7
PB		 3272#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3273
3274static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3275{
c47ada30 3276 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3277 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3278 u64 valid;
3279
3280 /*
3281 * Copy legacy XSAVE area, to avoid complications with CPUID
3282 * leaves 0 and 1 in the loop below.
3283 */
3284 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3285
3286 /* Set XSTATE_BV */
00c87e9a 3287 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3288 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3289
3290 /*
3291 * Copy each region from the possibly compacted offset to the
3292 * non-compacted offset.
3293 */
d91cab78 3294 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3295 while (valid) {
3296 u64 feature = valid & -valid;
3297 int index = fls64(feature) - 1;
3298 void *src = get_xsave_addr(xsave, feature);
3299
3300 if (src) {
3301 u32 size, offset, ecx, edx;
3302 cpuid_count(XSTATE_CPUID, index,
3303 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3304 if (feature == XFEATURE_MASK_PKRU)
3305 memcpy(dest + offset, &vcpu->arch.pkru,
3306 sizeof(vcpu->arch.pkru));
3307 else
3308 memcpy(dest + offset, src, size);
3309
df1daba7
PB		 3310 }
3311
3312 valid -= feature;
3313 }
3314}
3315
3316static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3317{
c47ada30 3318 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3319 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3320 u64 valid;
3321
3322 /*
3323 * Copy legacy XSAVE area, to avoid complications with CPUID
3324 * leaves 0 and 1 in the loop below.
3325 */
3326 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3327
3328 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3329 xsave->header.xfeatures = xstate_bv;
782511b0 3330 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3331 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3332
3333 /*
3334 * Copy each region from the non-compacted offset to the
3335 * possibly compacted offset.
3336 */
d91cab78 3337 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3338 while (valid) {
3339 u64 feature = valid & -valid;
3340 int index = fls64(feature) - 1;
3341 void *dest = get_xsave_addr(xsave, feature);
3342
3343 if (dest) {
3344 u32 size, offset, ecx, edx;
3345 cpuid_count(XSTATE_CPUID, index,
3346 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3347 if (feature == XFEATURE_MASK_PKRU)
3348 memcpy(&vcpu->arch.pkru, src + offset,
3349 sizeof(vcpu->arch.pkru));
3350 else
3351 memcpy(dest, src + offset, size);
ee4100da 3352 }
df1daba7
PB		 3353
3354 valid -= feature;
3355 }
3356}
3357
2d5b5a66
SY		 3358static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3359 struct kvm_xsave *guest_xsave)
3360{
d366bf7e 3361 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3362 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3363 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3364 } else {
2d5b5a66 3365 memcpy(guest_xsave->region,
7366ed77 3366 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3367 sizeof(struct fxregs_state));
2d5b5a66 3368 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3369 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3370 }
3371}
3372
a575813b
WL		 3373#define XSAVE_MXCSR_OFFSET 24
3374
2d5b5a66
SY		 3375static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3376 struct kvm_xsave *guest_xsave)
3377{
3378 u64 xstate_bv =
3379 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3380 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3381
d366bf7e 3382 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3383 /*
3384 * Here we allow setting states that are not present in
3385 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3386 * with old userspace.
3387 */
a575813b
WL		 3388 if (xstate_bv & ~kvm_supported_xcr0() ||
3389 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3390 return -EINVAL;
df1daba7 3391 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3392 } else {
a575813b
WL		 3393 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3394 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3395 return -EINVAL;
7366ed77 3396 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3397 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3398 }
3399 return 0;
3400}
3401
3402static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3403 struct kvm_xcrs *guest_xcrs)
3404{
d366bf7e 3405 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3406 guest_xcrs->nr_xcrs = 0;
3407 return;
3408 }
3409
3410 guest_xcrs->nr_xcrs = 1;
3411 guest_xcrs->flags = 0;
3412 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3413 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3414}
3415
3416static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3417 struct kvm_xcrs *guest_xcrs)
3418{
3419 int i, r = 0;
3420
d366bf7e 3421 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3422 return -EINVAL;
3423
3424 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3425 return -EINVAL;
3426
3427 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3428 /* Only support XCR0 currently */
c67a04cb 3429 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3430 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3431 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3432 break;
3433 }
3434 if (r)
3435 r = -EINVAL;
3436 return r;
3437}
3438
1c0b28c2
EM		 3439/*
3440 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3441 * stopped by the hypervisor. This function will be called from the host only.
3442 * EINVAL is returned when the host attempts to set the flag for a guest that
3443 * does not support pv clocks.
3444 */
3445static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3446{
0b79459b 3447 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3448 return -EINVAL;
51d59c6b 3449 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3450 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3451 return 0;
3452}
3453
5c919412
AS		 3454static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3455 struct kvm_enable_cap *cap)
3456{
3457 if (cap->flags)
3458 return -EINVAL;
3459
3460 switch (cap->cap) {
efc479e6
RK		 3461 case KVM_CAP_HYPERV_SYNIC2:
3462 if (cap->args[0])
3463 return -EINVAL;
5c919412 3464 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3465 if (!irqchip_in_kernel(vcpu->kvm))
3466 return -EINVAL;
efc479e6
RK		 3467 return kvm_hv_activate_synic(vcpu, cap->cap ==
3468 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3469 default:
3470 return -EINVAL;
3471 }
3472}
3473
313a3dc7
CO		 3474long kvm_arch_vcpu_ioctl(struct file *filp,
3475 unsigned int ioctl, unsigned long arg)
3476{
3477 struct kvm_vcpu *vcpu = filp->private_data;
3478 void __user *argp = (void __user *)arg;
3479 int r;
d1ac91d8
AK		 3480 union {
3481 struct kvm_lapic_state *lapic;
3482 struct kvm_xsave *xsave;
3483 struct kvm_xcrs *xcrs;
3484 void *buffer;
3485 } u;
3486
3487 u.buffer = NULL;
313a3dc7
CO		 3488 switch (ioctl) {
3489 case KVM_GET_LAPIC: {
2204ae3c 3490 r = -EINVAL;
bce87cce 3491 if (!lapic_in_kernel(vcpu))
2204ae3c 3492 goto out;
d1ac91d8 3493 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3494
b772ff36 3495 r = -ENOMEM;
d1ac91d8 3496 if (!u.lapic)
b772ff36 3497 goto out;
d1ac91d8 3498 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3499 if (r)
3500 goto out;
3501 r = -EFAULT;
d1ac91d8 3502 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3503 goto out;
3504 r = 0;
3505 break;
3506 }
3507 case KVM_SET_LAPIC: {
2204ae3c 3508 r = -EINVAL;
bce87cce 3509 if (!lapic_in_kernel(vcpu))
2204ae3c 3510 goto out;
ff5c2c03 3511 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3512 if (IS_ERR(u.lapic))
3513 return PTR_ERR(u.lapic);
ff5c2c03 3514
d1ac91d8 3515 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3516 break;
3517 }
f77bc6a4
ZX		 3518 case KVM_INTERRUPT: {
3519 struct kvm_interrupt irq;
3520
3521 r = -EFAULT;
3522 if (copy_from_user(&irq, argp, sizeof irq))
3523 goto out;
3524 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3525 break;
3526 }
c4abb7c9
JK		 3527 case KVM_NMI: {
3528 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3529 break;
3530 }
f077825a
PB		 3531 case KVM_SMI: {
3532 r = kvm_vcpu_ioctl_smi(vcpu);
3533 break;
3534 }
313a3dc7
CO		 3535 case KVM_SET_CPUID: {
3536 struct kvm_cpuid __user *cpuid_arg = argp;
3537 struct kvm_cpuid cpuid;
3538
3539 r = -EFAULT;
3540 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3541 goto out;
3542 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3543 break;
3544 }
07716717
DK		 3545 case KVM_SET_CPUID2: {
3546 struct kvm_cpuid2 __user *cpuid_arg = argp;
3547 struct kvm_cpuid2 cpuid;
3548
3549 r = -EFAULT;
3550 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3551 goto out;
3552 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3553 cpuid_arg->entries);
07716717
DK		 3554 break;
3555 }
3556 case KVM_GET_CPUID2: {
3557 struct kvm_cpuid2 __user *cpuid_arg = argp;
3558 struct kvm_cpuid2 cpuid;
3559
3560 r = -EFAULT;
3561 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3562 goto out;
3563 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3564 cpuid_arg->entries);
07716717
DK		 3565 if (r)
3566 goto out;
3567 r = -EFAULT;
3568 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3569 goto out;
3570 r = 0;
3571 break;
3572 }
313a3dc7 3573 case KVM_GET_MSRS:
609e36d3 3574 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3575 break;
3576 case KVM_SET_MSRS:
3577 r = msr_io(vcpu, argp, do_set_msr, 0);
3578 break;
b209749f
AK		 3579 case KVM_TPR_ACCESS_REPORTING: {
3580 struct kvm_tpr_access_ctl tac;
3581
3582 r = -EFAULT;
3583 if (copy_from_user(&tac, argp, sizeof tac))
3584 goto out;
3585 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3586 if (r)
3587 goto out;
3588 r = -EFAULT;
3589 if (copy_to_user(argp, &tac, sizeof tac))
3590 goto out;
3591 r = 0;
3592 break;
3593 };
b93463aa
AK		 3594 case KVM_SET_VAPIC_ADDR: {
3595 struct kvm_vapic_addr va;
7301d6ab 3596 int idx;
b93463aa
AK		 3597
3598 r = -EINVAL;
35754c98 3599 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3600 goto out;
3601 r = -EFAULT;
3602 if (copy_from_user(&va, argp, sizeof va))
3603 goto out;
7301d6ab 3604 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3605 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3606 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3607 break;
3608 }
890ca9ae
HY		 3609 case KVM_X86_SETUP_MCE: {
3610 u64 mcg_cap;
3611
3612 r = -EFAULT;
3613 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3614 goto out;
3615 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3616 break;
3617 }
3618 case KVM_X86_SET_MCE: {
3619 struct kvm_x86_mce mce;
3620
3621 r = -EFAULT;
3622 if (copy_from_user(&mce, argp, sizeof mce))
3623 goto out;
3624 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3625 break;
3626 }
3cfc3092
JK		 3627 case KVM_GET_VCPU_EVENTS: {
3628 struct kvm_vcpu_events events;
3629
3630 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3631
3632 r = -EFAULT;
3633 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3634 break;
3635 r = 0;
3636 break;
3637 }
3638 case KVM_SET_VCPU_EVENTS: {
3639 struct kvm_vcpu_events events;
3640
3641 r = -EFAULT;
3642 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3643 break;
3644
3645 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3646 break;
3647 }
a1efbe77
JK		 3648 case KVM_GET_DEBUGREGS: {
3649 struct kvm_debugregs dbgregs;
3650
3651 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3652
3653 r = -EFAULT;
3654 if (copy_to_user(argp, &dbgregs,
3655 sizeof(struct kvm_debugregs)))
3656 break;
3657 r = 0;
3658 break;
3659 }
3660 case KVM_SET_DEBUGREGS: {
3661 struct kvm_debugregs dbgregs;
3662
3663 r = -EFAULT;
3664 if (copy_from_user(&dbgregs, argp,
3665 sizeof(struct kvm_debugregs)))
3666 break;
3667
3668 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3669 break;
3670 }
2d5b5a66 3671 case KVM_GET_XSAVE: {
d1ac91d8 3672 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3673 r = -ENOMEM;
d1ac91d8 3674 if (!u.xsave)
2d5b5a66
SY		 3675 break;
3676
d1ac91d8 3677 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3678
3679 r = -EFAULT;
d1ac91d8 3680 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3681 break;
3682 r = 0;
3683 break;
3684 }
3685 case KVM_SET_XSAVE: {
ff5c2c03 3686 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3687 if (IS_ERR(u.xsave))
3688 return PTR_ERR(u.xsave);
2d5b5a66 3689
d1ac91d8 3690 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3691 break;
3692 }
3693 case KVM_GET_XCRS: {
d1ac91d8 3694 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3695 r = -ENOMEM;
d1ac91d8 3696 if (!u.xcrs)
2d5b5a66
SY		 3697 break;
3698
d1ac91d8 3699 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3700
3701 r = -EFAULT;
d1ac91d8 3702 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3703 sizeof(struct kvm_xcrs)))
3704 break;
3705 r = 0;
3706 break;
3707 }
3708 case KVM_SET_XCRS: {
ff5c2c03 3709 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3710 if (IS_ERR(u.xcrs))
3711 return PTR_ERR(u.xcrs);
2d5b5a66 3712
d1ac91d8 3713 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3714 break;
3715 }
92a1f12d
JR		 3716 case KVM_SET_TSC_KHZ: {
3717 u32 user_tsc_khz;
3718
3719 r = -EINVAL;
92a1f12d
JR		 3720 user_tsc_khz = (u32)arg;
3721
3722 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3723 goto out;
3724
cc578287
ZA		 3725 if (user_tsc_khz == 0)
3726 user_tsc_khz = tsc_khz;
3727
381d585c
HZ		 3728 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3729 r = 0;
92a1f12d 3730
92a1f12d
JR		 3731 goto out;
3732 }
3733 case KVM_GET_TSC_KHZ: {
cc578287 3734 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3735 goto out;
3736 }
1c0b28c2
EM		 3737 case KVM_KVMCLOCK_CTRL: {
3738 r = kvm_set_guest_paused(vcpu);
3739 goto out;
3740 }
5c919412
AS		 3741 case KVM_ENABLE_CAP: {
3742 struct kvm_enable_cap cap;
3743
3744 r = -EFAULT;
3745 if (copy_from_user(&cap, argp, sizeof(cap)))
3746 goto out;
3747 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3748 break;
3749 }
313a3dc7
CO		 3750 default:
3751 r = -EINVAL;
3752 }
3753out:
d1ac91d8 3754 kfree(u.buffer);
313a3dc7
CO		 3755 return r;
3756}
3757
5b1c1493
CO		 3758int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3759{
3760 return VM_FAULT_SIGBUS;
3761}
3762
1fe779f8
CO		 3763static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3764{
3765 int ret;
3766
3767 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3768 return -EINVAL;
1fe779f8
CO		 3769 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3770 return ret;
3771}
3772
b927a3ce
SY		 3773static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3774 u64 ident_addr)
3775{
3776 kvm->arch.ept_identity_map_addr = ident_addr;
3777 return 0;
3778}
3779
1fe779f8
CO		 3780static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3781 u32 kvm_nr_mmu_pages)
3782{
3783 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3784 return -EINVAL;
3785
79fac95e 3786 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3787
3788 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3789 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3790
79fac95e 3791 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3792 return 0;
3793}
3794
3795static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3796{
39de71ec 3797 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3798}
3799
1fe779f8
CO		 3800static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3801{
90bca052 3802 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3803 int r;
3804
3805 r = 0;
3806 switch (chip->chip_id) {
3807 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3808 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3809 sizeof(struct kvm_pic_state));
3810 break;
3811 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3812 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3813 sizeof(struct kvm_pic_state));
3814 break;
3815 case KVM_IRQCHIP_IOAPIC:
33392b49 3816 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3817 break;
3818 default:
3819 r = -EINVAL;
3820 break;
3821 }
3822 return r;
3823}
3824
3825static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3826{
90bca052 3827 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3828 int r;
3829
3830 r = 0;
3831 switch (chip->chip_id) {
3832 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3833 spin_lock(&pic->lock);
3834 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3835 sizeof(struct kvm_pic_state));
90bca052 3836 spin_unlock(&pic->lock);
1fe779f8
CO		 3837 break;
3838 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3839 spin_lock(&pic->lock);
3840 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3841 sizeof(struct kvm_pic_state));
90bca052 3842 spin_unlock(&pic->lock);
1fe779f8
CO		 3843 break;
3844 case KVM_IRQCHIP_IOAPIC:
33392b49 3845 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3846 break;
3847 default:
3848 r = -EINVAL;
3849 break;
3850 }
90bca052 3851 kvm_pic_update_irq(pic);
1fe779f8
CO		 3852 return r;
3853}
3854
e0f63cb9
SY		 3855static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3856{
34f3941c
RK		 3857 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3858
3859 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3860
3861 mutex_lock(&kps->lock);
3862 memcpy(ps, &kps->channels, sizeof(*ps));
3863 mutex_unlock(&kps->lock);
2da29bcc 3864 return 0;
e0f63cb9
SY		 3865}
3866
3867static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3868{
0185604c 3869 int i;
09edea72
RK		 3870 struct kvm_pit *pit = kvm->arch.vpit;
3871
3872 mutex_lock(&pit->pit_state.lock);
34f3941c 3873 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3874 for (i = 0; i < 3; i++)
09edea72
RK		 3875 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3876 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3877 return 0;
e9f42757
BK		 3878}
3879
3880static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3881{
e9f42757
BK		 3882 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3883 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3884 sizeof(ps->channels));
3885 ps->flags = kvm->arch.vpit->pit_state.flags;
3886 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3887 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3888 return 0;
e9f42757
BK		 3889}
3890
3891static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3892{
2da29bcc 3893 int start = 0;
0185604c 3894 int i;
e9f42757 3895 u32 prev_legacy, cur_legacy;
09edea72
RK		 3896 struct kvm_pit *pit = kvm->arch.vpit;
3897
3898 mutex_lock(&pit->pit_state.lock);
3899 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3900 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3901 if (!prev_legacy && cur_legacy)
3902 start = 1;
09edea72
RK		 3903 memcpy(&pit->pit_state.channels, &ps->channels,
3904 sizeof(pit->pit_state.channels));
3905 pit->pit_state.flags = ps->flags;
0185604c 3906 for (i = 0; i < 3; i++)
09edea72 3907 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3908 start && i == 0);
09edea72 3909 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3910 return 0;
e0f63cb9
SY		 3911}
3912
52d939a0
MT		 3913static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3914 struct kvm_reinject_control *control)
3915{
71474e2f
RK		 3916 struct kvm_pit *pit = kvm->arch.vpit;
3917
3918 if (!pit)
52d939a0 3919 return -ENXIO;
b39c90b6 3920
71474e2f
RK		 3921 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3922 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3923 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3924 */
3925 mutex_lock(&pit->pit_state.lock);
3926 kvm_pit_set_reinject(pit, control->pit_reinject);
3927 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3928
52d939a0
MT		 3929 return 0;
3930}
3931
95d4c16c 3932/**
60c34612
TY		 3933 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3934 * @kvm: kvm instance
3935 * @log: slot id and address to which we copy the log
95d4c16c 3936 *
e108ff2f
PB		 3937 * Steps 1-4 below provide general overview of dirty page logging. See
3938 * kvm_get_dirty_log_protect() function description for additional details.
3939 *
3940 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3941 * always flush the TLB (step 4) even if previous step failed and the dirty
3942 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3943 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3944 * writes will be marked dirty for next log read.
95d4c16c 3945 *
60c34612
TY		 3946 * 1. Take a snapshot of the bit and clear it if needed.
3947 * 2. Write protect the corresponding page.
e108ff2f
PB		 3948 * 3. Copy the snapshot to the userspace.
3949 * 4. Flush TLB's if needed.
5bb064dc 3950 */
60c34612 3951int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3952{
60c34612 3953 bool is_dirty = false;
e108ff2f 3954 int r;
5bb064dc 3955
79fac95e 3956 mutex_lock(&kvm->slots_lock);
5bb064dc 3957
88178fd4
KH		 3958 /*
3959 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3960 */
3961 if (kvm_x86_ops->flush_log_dirty)
3962 kvm_x86_ops->flush_log_dirty(kvm);
3963
e108ff2f 3964 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3965
3966 /*
3967 * All the TLBs can be flushed out of mmu lock, see the comments in
3968 * kvm_mmu_slot_remove_write_access().
3969 */
e108ff2f 3970 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3971 if (is_dirty)
3972 kvm_flush_remote_tlbs(kvm);
3973
79fac95e 3974 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3975 return r;
3976}
3977
aa2fbe6d
YZ		 3978int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3979 bool line_status)
23d43cf9
CD		 3980{
3981 if (!irqchip_in_kernel(kvm))
3982 return -ENXIO;
3983
3984 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3985 irq_event->irq, irq_event->level,
3986 line_status);
23d43cf9
CD		 3987 return 0;
3988}
3989
90de4a18
NA		 3990static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3991 struct kvm_enable_cap *cap)
3992{
3993 int r;
3994
3995 if (cap->flags)
3996 return -EINVAL;
3997
3998 switch (cap->cap) {
3999 case KVM_CAP_DISABLE_QUIRKS:
4000 kvm->arch.disabled_quirks = cap->args[0];
4001 r = 0;
4002 break;
49df6397
SR		 4003 case KVM_CAP_SPLIT_IRQCHIP: {
4004 mutex_lock(&kvm->lock);
b053b2ae
SR		 4005 r = -EINVAL;
4006 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4007 goto split_irqchip_unlock;
49df6397
SR		 4008 r = -EEXIST;
4009 if (irqchip_in_kernel(kvm))
4010 goto split_irqchip_unlock;
557abc40 4011 if (kvm->created_vcpus)
49df6397
SR		 4012 goto split_irqchip_unlock;
4013 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4014 if (r)
49df6397
SR		 4015 goto split_irqchip_unlock;
4016 /* Pairs with irqchip_in_kernel. */
4017 smp_wmb();
49776faf 4018 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4019 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4020 r = 0;
4021split_irqchip_unlock:
4022 mutex_unlock(&kvm->lock);
4023 break;
4024 }
37131313
RK		 4025 case KVM_CAP_X2APIC_API:
4026 r = -EINVAL;
4027 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4028 break;
4029
4030 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4031 kvm->arch.x2apic_format = true;
c519265f
RK		 4032 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4033 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4034
4035 r = 0;
4036 break;
90de4a18
NA		 4037 default:
4038 r = -EINVAL;
4039 break;
4040 }
4041 return r;
4042}
4043
1fe779f8
CO		 4044long kvm_arch_vm_ioctl(struct file *filp,
4045 unsigned int ioctl, unsigned long arg)
4046{
4047 struct kvm *kvm = filp->private_data;
4048 void __user *argp = (void __user *)arg;
367e1319 4049 int r = -ENOTTY;
f0d66275
DH		 4050 /*
4051 * This union makes it completely explicit to gcc-3.x
4052 * that these two variables' stack usage should be
4053 * combined, not added together.
4054 */
4055 union {
4056 struct kvm_pit_state ps;
e9f42757 4057 struct kvm_pit_state2 ps2;
c5ff41ce 4058 struct kvm_pit_config pit_config;
f0d66275 4059 } u;
1fe779f8
CO		 4060
4061 switch (ioctl) {
4062 case KVM_SET_TSS_ADDR:
4063 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4064 break;
b927a3ce
SY		 4065 case KVM_SET_IDENTITY_MAP_ADDR: {
4066 u64 ident_addr;
4067
1af1ac91
DH		 4068 mutex_lock(&kvm->lock);
4069 r = -EINVAL;
4070 if (kvm->created_vcpus)
4071 goto set_identity_unlock;
b927a3ce
SY		 4072 r = -EFAULT;
4073 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4074 goto set_identity_unlock;
b927a3ce 4075 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4076set_identity_unlock:
4077 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4078 break;
4079 }
1fe779f8
CO		 4080 case KVM_SET_NR_MMU_PAGES:
4081 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4082 break;
4083 case KVM_GET_NR_MMU_PAGES:
4084 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4085 break;
3ddea128 4086 case KVM_CREATE_IRQCHIP: {
3ddea128 4087 mutex_lock(&kvm->lock);
09941366 4088
3ddea128 4089 r = -EEXIST;
35e6eaa3 4090 if (irqchip_in_kernel(kvm))
3ddea128 4091 goto create_irqchip_unlock;
09941366 4092
3e515705 4093 r = -EINVAL;
557abc40 4094 if (kvm->created_vcpus)
3e515705 4095 goto create_irqchip_unlock;
09941366
RK		 4096
4097 r = kvm_pic_init(kvm);
4098 if (r)
3ddea128 4099 goto create_irqchip_unlock;
09941366
RK		 4100
4101 r = kvm_ioapic_init(kvm);
4102 if (r) {
09941366 4103 kvm_pic_destroy(kvm);
3ddea128 4104 goto create_irqchip_unlock;
09941366
RK		 4105 }
4106
399ec807
AK		 4107 r = kvm_setup_default_irq_routing(kvm);
4108 if (r) {
72bb2fcd 4109 kvm_ioapic_destroy(kvm);
09941366 4110 kvm_pic_destroy(kvm);
71ba994c 4111 goto create_irqchip_unlock;
399ec807 4112 }
49776faf 4113 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4114 smp_wmb();
49776faf 4115 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4116 create_irqchip_unlock:
4117 mutex_unlock(&kvm->lock);
1fe779f8 4118 break;
3ddea128 4119 }
7837699f 4120 case KVM_CREATE_PIT:
c5ff41ce
JK		 4121 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4122 goto create_pit;
4123 case KVM_CREATE_PIT2:
4124 r = -EFAULT;
4125 if (copy_from_user(&u.pit_config, argp,
4126 sizeof(struct kvm_pit_config)))
4127 goto out;
4128 create_pit:
250715a6 4129 mutex_lock(&kvm->lock);
269e05e4
AK		 4130 r = -EEXIST;
4131 if (kvm->arch.vpit)
4132 goto create_pit_unlock;
7837699f 4133 r = -ENOMEM;
c5ff41ce 4134 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4135 if (kvm->arch.vpit)
4136 r = 0;
269e05e4 4137 create_pit_unlock:
250715a6 4138 mutex_unlock(&kvm->lock);
7837699f 4139 break;
1fe779f8
CO		 4140 case KVM_GET_IRQCHIP: {
4141 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4142 struct kvm_irqchip *chip;
1fe779f8 4143
ff5c2c03
SL		 4144 chip = memdup_user(argp, sizeof(*chip));
4145 if (IS_ERR(chip)) {
4146 r = PTR_ERR(chip);
1fe779f8 4147 goto out;
ff5c2c03
SL		 4148 }
4149
1fe779f8 4150 r = -ENXIO;
826da321 4151 if (!irqchip_kernel(kvm))
f0d66275
DH		 4152 goto get_irqchip_out;
4153 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4154 if (r)
f0d66275 4155 goto get_irqchip_out;
1fe779f8 4156 r = -EFAULT;
f0d66275
DH		 4157 if (copy_to_user(argp, chip, sizeof *chip))
4158 goto get_irqchip_out;
1fe779f8 4159 r = 0;
f0d66275
DH		 4160 get_irqchip_out:
4161 kfree(chip);
1fe779f8
CO		 4162 break;
4163 }
4164 case KVM_SET_IRQCHIP: {
4165 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4166 struct kvm_irqchip *chip;
1fe779f8 4167
ff5c2c03
SL		 4168 chip = memdup_user(argp, sizeof(*chip));
4169 if (IS_ERR(chip)) {
4170 r = PTR_ERR(chip);
1fe779f8 4171 goto out;
ff5c2c03
SL		 4172 }
4173
1fe779f8 4174 r = -ENXIO;
826da321 4175 if (!irqchip_kernel(kvm))
f0d66275
DH		 4176 goto set_irqchip_out;
4177 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4178 if (r)
f0d66275 4179 goto set_irqchip_out;
1fe779f8 4180 r = 0;
f0d66275
DH		 4181 set_irqchip_out:
4182 kfree(chip);
1fe779f8
CO		 4183 break;
4184 }
e0f63cb9 4185 case KVM_GET_PIT: {
e0f63cb9 4186 r = -EFAULT;
f0d66275 4187 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4188 goto out;
4189 r = -ENXIO;
4190 if (!kvm->arch.vpit)
4191 goto out;
f0d66275 4192 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4193 if (r)
4194 goto out;
4195 r = -EFAULT;
f0d66275 4196 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4197 goto out;
4198 r = 0;
4199 break;
4200 }
4201 case KVM_SET_PIT: {
e0f63cb9 4202 r = -EFAULT;
f0d66275 4203 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4204 goto out;
4205 r = -ENXIO;
4206 if (!kvm->arch.vpit)
4207 goto out;
f0d66275 4208 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4209 break;
4210 }
e9f42757
BK		 4211 case KVM_GET_PIT2: {
4212 r = -ENXIO;
4213 if (!kvm->arch.vpit)
4214 goto out;
4215 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4216 if (r)
4217 goto out;
4218 r = -EFAULT;
4219 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4220 goto out;
4221 r = 0;
4222 break;
4223 }
4224 case KVM_SET_PIT2: {
4225 r = -EFAULT;
4226 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4227 goto out;
4228 r = -ENXIO;
4229 if (!kvm->arch.vpit)
4230 goto out;
4231 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4232 break;
4233 }
52d939a0
MT		 4234 case KVM_REINJECT_CONTROL: {
4235 struct kvm_reinject_control control;
4236 r = -EFAULT;
4237 if (copy_from_user(&control, argp, sizeof(control)))
4238 goto out;
4239 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4240 break;
4241 }
d71ba788
PB		 4242 case KVM_SET_BOOT_CPU_ID:
4243 r = 0;
4244 mutex_lock(&kvm->lock);
557abc40 4245 if (kvm->created_vcpus)
d71ba788
PB		 4246 r = -EBUSY;
4247 else
4248 kvm->arch.bsp_vcpu_id = arg;
4249 mutex_unlock(&kvm->lock);
4250 break;
ffde22ac 4251 case KVM_XEN_HVM_CONFIG: {
df92b316 4252 struct kvm_xen_hvm_config xhc;
ffde22ac 4253 r = -EFAULT;
df92b316 4254 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4255 goto out;
4256 r = -EINVAL;
df92b316 4257 if (xhc.flags)
ffde22ac 4258 goto out;
df92b316 4259 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4260 r = 0;
4261 break;
4262 }
afbcf7ab 4263 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4264 struct kvm_clock_data user_ns;
4265 u64 now_ns;
afbcf7ab
GC		 4266
4267 r = -EFAULT;
4268 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4269 goto out;
4270
4271 r = -EINVAL;
4272 if (user_ns.flags)
4273 goto out;
4274
4275 r = 0;
0bc48bea
RK		 4276 /*
4277 * TODO: userspace has to take care of races with VCPU_RUN, so
4278 * kvm_gen_update_masterclock() can be cut down to locked
4279 * pvclock_update_vm_gtod_copy().
4280 */
4281 kvm_gen_update_masterclock(kvm);
e891a32e 4282 now_ns = get_kvmclock_ns(kvm);
108b249c 4283 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4284 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4285 break;
4286 }
4287 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4288 struct kvm_clock_data user_ns;
4289 u64 now_ns;
4290
e891a32e 4291 now_ns = get_kvmclock_ns(kvm);
108b249c 4292 user_ns.clock = now_ns;
e3fd9a93 4293 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4294 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4295
4296 r = -EFAULT;
4297 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4298 goto out;
4299 r = 0;
4300 break;
4301 }
90de4a18
NA		 4302 case KVM_ENABLE_CAP: {
4303 struct kvm_enable_cap cap;
afbcf7ab 4304
90de4a18
NA		 4305 r = -EFAULT;
4306 if (copy_from_user(&cap, argp, sizeof(cap)))
4307 goto out;
4308 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4309 break;
4310 }
1fe779f8 4311 default:
ad6260da 4312 r = -ENOTTY;
1fe779f8
CO		 4313 }
4314out:
4315 return r;
4316}
4317
a16b043c 4318static void kvm_init_msr_list(void)
043405e1
CO		 4319{
4320 u32 dummy[2];
4321 unsigned i, j;
4322
62ef68bb 4323 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4324 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4325 continue;
93c4adc7
PB		 4326
4327 /*
4328 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4329 * to the guests in some cases.
93c4adc7
PB		 4330 */
4331 switch (msrs_to_save[i]) {
4332 case MSR_IA32_BNDCFGS:
4333 if (!kvm_x86_ops->mpx_supported())
4334 continue;
4335 break;
9dbe6cf9
PB		 4336 case MSR_TSC_AUX:
4337 if (!kvm_x86_ops->rdtscp_supported())
4338 continue;
4339 break;
93c4adc7
PB		 4340 default:
4341 break;
4342 }
4343
043405e1
CO		 4344 if (j < i)
4345 msrs_to_save[j] = msrs_to_save[i];
4346 j++;
4347 }
4348 num_msrs_to_save = j;
62ef68bb
PB		 4349
4350 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4d5c8a07
TL		 4351 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4352 continue;
62ef68bb
PB		 4353
4354 if (j < i)
4355 emulated_msrs[j] = emulated_msrs[i];
4356 j++;
4357 }
4358 num_emulated_msrs = j;
043405e1
CO		 4359}
4360
bda9020e
MT		 4361static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4362 const void *v)
bbd9b64e 4363{
70252a10
AK		 4364 int handled = 0;
4365 int n;
4366
4367 do {
4368 n = min(len, 8);
bce87cce 4369 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4370 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4371 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4372 break;
4373 handled += n;
4374 addr += n;
4375 len -= n;
4376 v += n;
4377 } while (len);
bbd9b64e 4378
70252a10 4379 return handled;
bbd9b64e
CO		 4380}
4381
bda9020e 4382static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4383{
70252a10
AK		 4384 int handled = 0;
4385 int n;
4386
4387 do {
4388 n = min(len, 8);
bce87cce 4389 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4390 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4391 addr, n, v))
4392 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4393 break;
e39d200f 4394 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4395 handled += n;
4396 addr += n;
4397 len -= n;
4398 v += n;
4399 } while (len);
bbd9b64e 4400
70252a10 4401 return handled;
bbd9b64e
CO		 4402}
4403
2dafc6c2
GN		 4404static void kvm_set_segment(struct kvm_vcpu *vcpu,
4405 struct kvm_segment *var, int seg)
4406{
4407 kvm_x86_ops->set_segment(vcpu, var, seg);
4408}
4409
4410void kvm_get_segment(struct kvm_vcpu *vcpu,
4411 struct kvm_segment *var, int seg)
4412{
4413 kvm_x86_ops->get_segment(vcpu, var, seg);
4414}
4415
54987b7a
PB		 4416gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4417 struct x86_exception *exception)
02f59dc9
JR		 4418{
4419 gpa_t t_gpa;
02f59dc9
JR		 4420
4421 BUG_ON(!mmu_is_nested(vcpu));
4422
4423 /* NPT walks are always user-walks */
4424 access |= PFERR_USER_MASK;
54987b7a 4425 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4426
4427 return t_gpa;
4428}
4429
ab9ae313
AK		 4430gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4431 struct x86_exception *exception)
1871c602
GN		 4432{
4433 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4434 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4435}
4436
ab9ae313
AK		 4437 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4438 struct x86_exception *exception)
1871c602
GN		 4439{
4440 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4441 access |= PFERR_FETCH_MASK;
ab9ae313 4442 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4443}
4444
ab9ae313
AK		 4445gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4446 struct x86_exception *exception)
1871c602
GN		 4447{
4448 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4449 access |= PFERR_WRITE_MASK;
ab9ae313 4450 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4451}
4452
4453/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4454gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4455 struct x86_exception *exception)
1871c602 4456{
ab9ae313 4457 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4458}
4459
4460static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4461 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4462 struct x86_exception *exception)
bbd9b64e
CO		 4463{
4464 void *data = val;
10589a46 4465 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4466
4467 while (bytes) {
14dfe855 4468 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4469 exception);
bbd9b64e 4470 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4471 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4472 int ret;
4473
bcc55cba 4474 if (gpa == UNMAPPED_GVA)
ab9ae313 4475 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4476 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4477 offset, toread);
10589a46 4478 if (ret < 0) {
c3cd7ffa 4479 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4480 goto out;
4481 }
bbd9b64e 4482
77c2002e
IE		 4483 bytes -= toread;
4484 data += toread;
4485 addr += toread;
bbd9b64e 4486 }
10589a46 4487out:
10589a46 4488 return r;
bbd9b64e 4489}
77c2002e 4490
1871c602 4491/* used for instruction fetching */
0f65dd70
AK		 4492static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4493 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4494 struct x86_exception *exception)
1871c602 4495{
0f65dd70 4496 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4497 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4498 unsigned offset;
4499 int ret;
0f65dd70 4500
44583cba
PB		 4501 /* Inline kvm_read_guest_virt_helper for speed. */
4502 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4503 exception);
4504 if (unlikely(gpa == UNMAPPED_GVA))
4505 return X86EMUL_PROPAGATE_FAULT;
4506
4507 offset = addr & (PAGE_SIZE-1);
4508 if (WARN_ON(offset + bytes > PAGE_SIZE))
4509 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4510 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4511 offset, bytes);
44583cba
PB		 4512 if (unlikely(ret < 0))
4513 return X86EMUL_IO_NEEDED;
4514
4515 return X86EMUL_CONTINUE;
1871c602
GN		 4516}
4517
064aea77 4518int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4519 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4520 struct x86_exception *exception)
1871c602 4521{
0f65dd70 4522 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4523 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4524
1871c602 4525 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4526 exception);
1871c602 4527}
064aea77 4528EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4529
0f65dd70
AK		 4530static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4531 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4532 struct x86_exception *exception)
1871c602 4533{
0f65dd70 4534 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4535 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4536}
4537
7a036a6f
RK		 4538static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4539 unsigned long addr, void *val, unsigned int bytes)
4540{
4541 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4542 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4543
4544 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4545}
4546
6a4d7550 4547int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4548 gva_t addr, void *val,
2dafc6c2 4549 unsigned int bytes,
bcc55cba 4550 struct x86_exception *exception)
77c2002e 4551{
0f65dd70 4552 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4553 void *data = val;
4554 int r = X86EMUL_CONTINUE;
4555
f0ace387
PB		 4556 /* kvm_write_guest_virt_system can pull in tons of pages. */
4557 vcpu->arch.l1tf_flush_l1d = true;
4558
77c2002e 4559 while (bytes) {
14dfe855
JR		 4560 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4561 PFERR_WRITE_MASK,
ab9ae313 4562 exception);
77c2002e
IE		 4563 unsigned offset = addr & (PAGE_SIZE-1);
4564 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4565 int ret;
4566
bcc55cba 4567 if (gpa == UNMAPPED_GVA)
ab9ae313 4568 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4569 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4570 if (ret < 0) {
c3cd7ffa 4571 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4572 goto out;
4573 }
4574
4575 bytes -= towrite;
4576 data += towrite;
4577 addr += towrite;
4578 }
4579out:
4580 return r;
4581}
6a4d7550 4582EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4583
0f89b207
TL		 4584static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4585 gpa_t gpa, bool write)
4586{
4587 /* For APIC access vmexit */
4588 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4589 return 1;
4590
4591 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4592 trace_vcpu_match_mmio(gva, gpa, write, true);
4593 return 1;
4594 }
4595
4596 return 0;
4597}
4598
af7cc7d1
XG		 4599static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4600 gpa_t *gpa, struct x86_exception *exception,
4601 bool write)
4602{
97d64b78
AK		 4603 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4604 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4605
be94f6b7
HH		 4606 /*
4607 * currently PKRU is only applied to ept enabled guest so
4608 * there is no pkey in EPT page table for L1 guest or EPT
4609 * shadow page table for L2 guest.
4610 */
97d64b78 4611 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4612 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4613 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4614 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4615 (gva & (PAGE_SIZE - 1));
4f022648 4616 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4617 return 1;
4618 }
4619
af7cc7d1
XG		 4620 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4621
4622 if (*gpa == UNMAPPED_GVA)
4623 return -1;
4624
0f89b207 4625 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4626}
4627
3200f405 4628int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4629 const void *val, int bytes)
bbd9b64e
CO		 4630{
4631 int ret;
4632
54bf36aa 4633 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4634 if (ret < 0)
bbd9b64e 4635 return 0;
0eb05bf2 4636 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4637 return 1;
4638}
4639
77d197b2
XG		 4640struct read_write_emulator_ops {
4641 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4642 int bytes);
4643 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4644 void *val, int bytes);
4645 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4646 int bytes, void *val);
4647 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4648 void *val, int bytes);
4649 bool write;
4650};
4651
4652static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4653{
4654 if (vcpu->mmio_read_completed) {
77d197b2 4655 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4656 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4657 vcpu->mmio_read_completed = 0;
4658 return 1;
4659 }
4660
4661 return 0;
4662}
4663
4664static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4665 void *val, int bytes)
4666{
54bf36aa 4667 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4668}
4669
4670static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4671 void *val, int bytes)
4672{
4673 return emulator_write_phys(vcpu, gpa, val, bytes);
4674}
4675
4676static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4677{
e39d200f 4678 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4679 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4680}
4681
4682static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4683 void *val, int bytes)
4684{
e39d200f 4685 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4686 return X86EMUL_IO_NEEDED;
4687}
4688
4689static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4690 void *val, int bytes)
4691{
f78146b0
AK		 4692 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4693
87da7e66 4694 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4695 return X86EMUL_CONTINUE;
4696}
4697
0fbe9b0b 4698static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4699 .read_write_prepare = read_prepare,
4700 .read_write_emulate = read_emulate,
4701 .read_write_mmio = vcpu_mmio_read,
4702 .read_write_exit_mmio = read_exit_mmio,
4703};
4704
0fbe9b0b 4705static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4706 .read_write_emulate = write_emulate,
4707 .read_write_mmio = write_mmio,
4708 .read_write_exit_mmio = write_exit_mmio,
4709 .write = true,
4710};
4711
22388a3c
XG		 4712static int emulator_read_write_onepage(unsigned long addr, void *val,
4713 unsigned int bytes,
4714 struct x86_exception *exception,
4715 struct kvm_vcpu *vcpu,
0fbe9b0b 4716 const struct read_write_emulator_ops *ops)
bbd9b64e 4717{
af7cc7d1
XG		 4718 gpa_t gpa;
4719 int handled, ret;
22388a3c 4720 bool write = ops->write;
f78146b0 4721 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4722 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4723
4724 /*
4725 * If the exit was due to a NPF we may already have a GPA.
4726 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4727 * Note, this cannot be used on string operations since string
4728 * operation using rep will only have the initial GPA from the NPF
4729 * occurred.
4730 */
4731 if (vcpu->arch.gpa_available &&
4732 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4733 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4734 gpa = vcpu->arch.gpa_val;
4735 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4736 } else {
4737 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4738 if (ret < 0)
4739 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4740 }
10589a46 4741
618232e2 4742 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4743 return X86EMUL_CONTINUE;
4744
bbd9b64e
CO		 4745 /*
4746 * Is this MMIO handled locally?
4747 */
22388a3c 4748 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4749 if (handled == bytes)
bbd9b64e 4750 return X86EMUL_CONTINUE;
bbd9b64e 4751
70252a10
AK		 4752 gpa += handled;
4753 bytes -= handled;
4754 val += handled;
4755
87da7e66
XG		 4756 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4757 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4758 frag->gpa = gpa;
4759 frag->data = val;
4760 frag->len = bytes;
f78146b0 4761 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4762}
4763
52eb5a6d
XL		 4764static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4765 unsigned long addr,
22388a3c
XG		 4766 void *val, unsigned int bytes,
4767 struct x86_exception *exception,
0fbe9b0b 4768 const struct read_write_emulator_ops *ops)
bbd9b64e 4769{
0f65dd70 4770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4771 gpa_t gpa;
4772 int rc;
4773
4774 if (ops->read_write_prepare &&
4775 ops->read_write_prepare(vcpu, val, bytes))
4776 return X86EMUL_CONTINUE;
4777
4778 vcpu->mmio_nr_fragments = 0;
0f65dd70 4779
bbd9b64e
CO		 4780 /* Crossing a page boundary? */
4781 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4782 int now;
bbd9b64e
CO		 4783
4784 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4785 rc = emulator_read_write_onepage(addr, val, now, exception,
4786 vcpu, ops);
4787
bbd9b64e
CO		 4788 if (rc != X86EMUL_CONTINUE)
4789 return rc;
4790 addr += now;
bac15531
NA		 4791 if (ctxt->mode != X86EMUL_MODE_PROT64)
4792 addr = (u32)addr;
bbd9b64e
CO		 4793 val += now;
4794 bytes -= now;
4795 }
22388a3c 4796
f78146b0
AK		 4797 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4798 vcpu, ops);
4799 if (rc != X86EMUL_CONTINUE)
4800 return rc;
4801
4802 if (!vcpu->mmio_nr_fragments)
4803 return rc;
4804
4805 gpa = vcpu->mmio_fragments[0].gpa;
4806
4807 vcpu->mmio_needed = 1;
4808 vcpu->mmio_cur_fragment = 0;
4809
87da7e66 4810 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4811 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4812 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4813 vcpu->run->mmio.phys_addr = gpa;
4814
4815 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4816}
4817
4818static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4819 unsigned long addr,
4820 void *val,
4821 unsigned int bytes,
4822 struct x86_exception *exception)
4823{
4824 return emulator_read_write(ctxt, addr, val, bytes,
4825 exception, &read_emultor);
4826}
4827
52eb5a6d 4828static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4829 unsigned long addr,
4830 const void *val,
4831 unsigned int bytes,
4832 struct x86_exception *exception)
4833{
4834 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4835 exception, &write_emultor);
bbd9b64e 4836}
bbd9b64e 4837
daea3e73
AK		 4838#define CMPXCHG_TYPE(t, ptr, old, new) \
4839 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4840
4841#ifdef CONFIG_X86_64
4842# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4843#else
4844# define CMPXCHG64(ptr, old, new) \
9749a6c0 4845 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4846#endif
4847
0f65dd70
AK		 4848static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4849 unsigned long addr,
bbd9b64e
CO		 4850 const void *old,
4851 const void *new,
4852 unsigned int bytes,
0f65dd70 4853 struct x86_exception *exception)
bbd9b64e 4854{
0f65dd70 4855 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4856 gpa_t gpa;
4857 struct page *page;
4858 char *kaddr;
4859 bool exchanged;
2bacc55c 4860
daea3e73
AK		 4861 /* guests cmpxchg8b have to be emulated atomically */
4862 if (bytes > 8 || (bytes & (bytes - 1)))
4863 goto emul_write;
10589a46 4864
daea3e73 4865 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4866
daea3e73
AK		 4867 if (gpa == UNMAPPED_GVA ||
4868 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4869 goto emul_write;
2bacc55c 4870
daea3e73
AK		 4871 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4872 goto emul_write;
72dc67a6 4873
54bf36aa 4874 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4875 if (is_error_page(page))
c19b8bd6 4876 goto emul_write;
72dc67a6 4877
8fd75e12 4878 kaddr = kmap_atomic(page);
daea3e73
AK		 4879 kaddr += offset_in_page(gpa);
4880 switch (bytes) {
4881 case 1:
4882 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4883 break;
4884 case 2:
4885 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4886 break;
4887 case 4:
4888 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4889 break;
4890 case 8:
4891 exchanged = CMPXCHG64(kaddr, old, new);
4892 break;
4893 default:
4894 BUG();
2bacc55c 4895 }
8fd75e12 4896 kunmap_atomic(kaddr);
daea3e73
AK		 4897 kvm_release_page_dirty(page);
4898
4899 if (!exchanged)
4900 return X86EMUL_CMPXCHG_FAILED;
4901
54bf36aa 4902 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4903 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4904
4905 return X86EMUL_CONTINUE;
4a5f48f6 4906
3200f405 4907emul_write:
daea3e73 4908 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4909
0f65dd70 4910 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4911}
4912
cf8f70bf
GN		 4913static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4914{
cbfc6c91 4915 int r = 0, i;
cf8f70bf 4916
cbfc6c91
WL		 4917 for (i = 0; i < vcpu->arch.pio.count; i++) {
4918 if (vcpu->arch.pio.in)
4919 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4920 vcpu->arch.pio.size, pd);
4921 else
4922 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4923 vcpu->arch.pio.port, vcpu->arch.pio.size,
4924 pd);
4925 if (r)
4926 break;
4927 pd += vcpu->arch.pio.size;
4928 }
cf8f70bf
GN		 4929 return r;
4930}
4931
6f6fbe98
XG		 4932static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4933 unsigned short port, void *val,
4934 unsigned int count, bool in)
cf8f70bf 4935{
cf8f70bf 4936 vcpu->arch.pio.port = port;
6f6fbe98 4937 vcpu->arch.pio.in = in;
7972995b 4938 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4939 vcpu->arch.pio.size = size;
4940
4941 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4942 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4943 return 1;
4944 }
4945
4946 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4947 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4948 vcpu->run->io.size = size;
4949 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4950 vcpu->run->io.count = count;
4951 vcpu->run->io.port = port;
4952
4953 return 0;
4954}
4955
6f6fbe98
XG		 4956static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4957 int size, unsigned short port, void *val,
4958 unsigned int count)
cf8f70bf 4959{
ca1d4a9e 4960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4961 int ret;
ca1d4a9e 4962
6f6fbe98
XG		 4963 if (vcpu->arch.pio.count)
4964 goto data_avail;
cf8f70bf 4965
cbfc6c91
WL		 4966 memset(vcpu->arch.pio_data, 0, size * count);
4967
6f6fbe98
XG		 4968 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4969 if (ret) {
4970data_avail:
4971 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4972 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4973 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4974 return 1;
4975 }
4976
cf8f70bf
GN		 4977 return 0;
4978}
4979
6f6fbe98
XG		 4980static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4981 int size, unsigned short port,
4982 const void *val, unsigned int count)
4983{
4984 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4985
4986 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4987 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4988 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4989}
4990
bbd9b64e
CO		 4991static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4992{
4993 return kvm_x86_ops->get_segment_base(vcpu, seg);
4994}
4995
3cb16fe7 4996static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4997{
3cb16fe7 4998 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4999}
5000
ae6a2375 5001static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5002{
5003 if (!need_emulate_wbinvd(vcpu))
5004 return X86EMUL_CONTINUE;
5005
5006 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5007 int cpu = get_cpu();
5008
5009 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5010 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5011 wbinvd_ipi, NULL, 1);
2eec7343 5012 put_cpu();
f5f48ee1 5013 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5014 } else
5015 wbinvd();
f5f48ee1
SY		 5016 return X86EMUL_CONTINUE;
5017}
5cb56059
JS		 5018
5019int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5020{
6affcbed
KH		 5021 kvm_emulate_wbinvd_noskip(vcpu);
5022 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5023}
f5f48ee1
SY		 5024EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5025
5cb56059
JS		 5026
5027
bcaf5cc5
AK		 5028static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5029{
5cb56059 5030 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5031}
5032
52eb5a6d
XL		 5033static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5034 unsigned long *dest)
bbd9b64e 5035{
16f8a6f9 5036 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5037}
5038
52eb5a6d
XL		 5039static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5040 unsigned long value)
bbd9b64e 5041{
338dbc97 5042
717746e3 5043 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5044}
5045
52a46617 5046static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5047{
52a46617 5048 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5049}
5050
717746e3 5051static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5052{
717746e3 5053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5054 unsigned long value;
5055
5056 switch (cr) {
5057 case 0:
5058 value = kvm_read_cr0(vcpu);
5059 break;
5060 case 2:
5061 value = vcpu->arch.cr2;
5062 break;
5063 case 3:
9f8fe504 5064 value = kvm_read_cr3(vcpu);
52a46617
GN		 5065 break;
5066 case 4:
5067 value = kvm_read_cr4(vcpu);
5068 break;
5069 case 8:
5070 value = kvm_get_cr8(vcpu);
5071 break;
5072 default:
a737f256 5073 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5074 return 0;
5075 }
5076
5077 return value;
5078}
5079
717746e3 5080static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5081{
717746e3 5082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5083 int res = 0;
5084
52a46617
GN		 5085 switch (cr) {
5086 case 0:
49a9b07e 5087 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5088 break;
5089 case 2:
5090 vcpu->arch.cr2 = val;
5091 break;
5092 case 3:
2390218b 5093 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5094 break;
5095 case 4:
a83b29c6 5096 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5097 break;
5098 case 8:
eea1cff9 5099 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5100 break;
5101 default:
a737f256 5102 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5103 res = -1;
52a46617 5104 }
0f12244f
GN		 5105
5106 return res;
52a46617
GN		 5107}
5108
717746e3 5109static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5110{
717746e3 5111 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5112}
5113
4bff1e86 5114static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5115{
4bff1e86 5116 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5117}
5118
4bff1e86 5119static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5120{
4bff1e86 5121 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5122}
5123
1ac9d0cf
AK		 5124static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5125{
5126 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5127}
5128
5129static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5130{
5131 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5132}
5133
4bff1e86
AK		 5134static unsigned long emulator_get_cached_segment_base(
5135 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5136{
4bff1e86 5137 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5138}
5139
1aa36616
AK		 5140static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5141 struct desc_struct *desc, u32 *base3,
5142 int seg)
2dafc6c2
GN		 5143{
5144 struct kvm_segment var;
5145
4bff1e86 5146 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5147 *selector = var.selector;
2dafc6c2 5148
378a8b09
GN		 5149 if (var.unusable) {
5150 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5151 if (base3)
5152 *base3 = 0;
2dafc6c2 5153 return false;
378a8b09 5154 }
2dafc6c2
GN		 5155
5156 if (var.g)
5157 var.limit >>= 12;
5158 set_desc_limit(desc, var.limit);
5159 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5160#ifdef CONFIG_X86_64
5161 if (base3)
5162 *base3 = var.base >> 32;
5163#endif
2dafc6c2
GN		 5164 desc->type = var.type;
5165 desc->s = var.s;
5166 desc->dpl = var.dpl;
5167 desc->p = var.present;
5168 desc->avl = var.avl;
5169 desc->l = var.l;
5170 desc->d = var.db;
5171 desc->g = var.g;
5172
5173 return true;
5174}
5175
1aa36616
AK		 5176static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5177 struct desc_struct *desc, u32 base3,
5178 int seg)
2dafc6c2 5179{
4bff1e86 5180 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5181 struct kvm_segment var;
5182
1aa36616 5183 var.selector = selector;
2dafc6c2 5184 var.base = get_desc_base(desc);
5601d05b
GN		 5185#ifdef CONFIG_X86_64
5186 var.base |= ((u64)base3) << 32;
5187#endif
2dafc6c2
GN		 5188 var.limit = get_desc_limit(desc);
5189 if (desc->g)
5190 var.limit = (var.limit << 12) | 0xfff;
5191 var.type = desc->type;
2dafc6c2
GN		 5192 var.dpl = desc->dpl;
5193 var.db = desc->d;
5194 var.s = desc->s;
5195 var.l = desc->l;
5196 var.g = desc->g;
5197 var.avl = desc->avl;
5198 var.present = desc->p;
5199 var.unusable = !var.present;
5200 var.padding = 0;
5201
5202 kvm_set_segment(vcpu, &var, seg);
5203 return;
5204}
5205
717746e3
AK		 5206static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5207 u32 msr_index, u64 *pdata)
5208{
609e36d3
PB		 5209 struct msr_data msr;
5210 int r;
5211
5212 msr.index = msr_index;
5213 msr.host_initiated = false;
5214 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5215 if (r)
5216 return r;
5217
5218 *pdata = msr.data;
5219 return 0;
717746e3
AK		 5220}
5221
5222static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5223 u32 msr_index, u64 data)
5224{
8fe8ab46
WA		 5225 struct msr_data msr;
5226
5227 msr.data = data;
5228 msr.index = msr_index;
5229 msr.host_initiated = false;
5230 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5231}
5232
64d60670
PB		 5233static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5234{
5235 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5236
5237 return vcpu->arch.smbase;
5238}
5239
5240static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5241{
5242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5243
5244 vcpu->arch.smbase = smbase;
5245}
5246
67f4d428
NA		 5247static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5248 u32 pmc)
5249{
c6702c9d 5250 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5251}
5252
222d21aa
AK		 5253static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5254 u32 pmc, u64 *pdata)
5255{
c6702c9d 5256 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5257}
5258
6c3287f7
AK		 5259static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5260{
5261 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5262}
5263
2953538e 5264static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5265 struct x86_instruction_info *info,
c4f035c6
AK		 5266 enum x86_intercept_stage stage)
5267{
2953538e 5268 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5269}
5270
e911eb3b
YZ		 5271static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5272 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5273{
e911eb3b 5274 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5275}
5276
dd856efa
AK		 5277static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5278{
5279 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5280}
5281
5282static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5283{
5284 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5285}
5286
801806d9
NA		 5287static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5288{
5289 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5290}
5291
6ed071f0
LP		 5292static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5293{
5294 return emul_to_vcpu(ctxt)->arch.hflags;
5295}
5296
5297static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5298{
5299 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5300}
5301
0234bf88
LP		 5302static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5303{
5304 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5305}
5306
0225fb50 5307static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5308 .read_gpr = emulator_read_gpr,
5309 .write_gpr = emulator_write_gpr,
1871c602 5310 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5311 .write_std = kvm_write_guest_virt_system,
7a036a6f 5312 .read_phys = kvm_read_guest_phys_system,
1871c602 5313 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5314 .read_emulated = emulator_read_emulated,
5315 .write_emulated = emulator_write_emulated,
5316 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5317 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5318 .pio_in_emulated = emulator_pio_in_emulated,
5319 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5320 .get_segment = emulator_get_segment,
5321 .set_segment = emulator_set_segment,
5951c442 5322 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5323 .get_gdt = emulator_get_gdt,
160ce1f1 5324 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5325 .set_gdt = emulator_set_gdt,
5326 .set_idt = emulator_set_idt,
52a46617
GN		 5327 .get_cr = emulator_get_cr,
5328 .set_cr = emulator_set_cr,
9c537244 5329 .cpl = emulator_get_cpl,
35aa5375
GN		 5330 .get_dr = emulator_get_dr,
5331 .set_dr = emulator_set_dr,
64d60670
PB		 5332 .get_smbase = emulator_get_smbase,
5333 .set_smbase = emulator_set_smbase,
717746e3
AK		 5334 .set_msr = emulator_set_msr,
5335 .get_msr = emulator_get_msr,
67f4d428 5336 .check_pmc = emulator_check_pmc,
222d21aa 5337 .read_pmc = emulator_read_pmc,
6c3287f7 5338 .halt = emulator_halt,
bcaf5cc5 5339 .wbinvd = emulator_wbinvd,
d6aa1000 5340 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5341 .intercept = emulator_intercept,
bdb42f5a 5342 .get_cpuid = emulator_get_cpuid,
801806d9 5343 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5344 .get_hflags = emulator_get_hflags,
5345 .set_hflags = emulator_set_hflags,
0234bf88 5346 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5347};
5348
95cb2295
GN		 5349static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5350{
37ccdcbe 5351 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5352 /*
5353 * an sti; sti; sequence only disable interrupts for the first
5354 * instruction. So, if the last instruction, be it emulated or
5355 * not, left the system with the INT_STI flag enabled, it
5356 * means that the last instruction is an sti. We should not
5357 * leave the flag on in this case. The same goes for mov ss
5358 */
37ccdcbe
PB		 5359 if (int_shadow & mask)
5360 mask = 0;
6addfc42 5361 if (unlikely(int_shadow || mask)) {
95cb2295 5362 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5363 if (!mask)
5364 kvm_make_request(KVM_REQ_EVENT, vcpu);
5365 }
95cb2295
GN		 5366}
5367
ef54bcfe 5368static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5369{
5370 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5371 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5372 return kvm_propagate_fault(vcpu, &ctxt->exception);
5373
5374 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5375 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5376 ctxt->exception.error_code);
54b8486f 5377 else
da9cb575 5378 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5379 return false;
54b8486f
GN		 5380}
5381
8ec4722d
MG		 5382static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5383{
adf52235 5384 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5385 int cs_db, cs_l;
5386
8ec4722d
MG		 5387 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5388
adf52235 5389 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5390 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5391
adf52235
TY		 5392 ctxt->eip = kvm_rip_read(vcpu);
5393 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5394 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5395 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5396 cs_db ? X86EMUL_MODE_PROT32 :
5397 X86EMUL_MODE_PROT16;
a584539b 5398 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5399 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5400 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5401
dd856efa 5402 init_decode_cache(ctxt);
7ae441ea 5403 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5404}
5405
71f9833b 5406int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5407{
9d74191a 5408 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5409 int ret;
5410
5411 init_emulate_ctxt(vcpu);
5412
9dac77fa
AK		 5413 ctxt->op_bytes = 2;
5414 ctxt->ad_bytes = 2;
5415 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5416 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5417
5418 if (ret != X86EMUL_CONTINUE)
5419 return EMULATE_FAIL;
5420
9dac77fa 5421 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5422 kvm_rip_write(vcpu, ctxt->eip);
5423 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5424
5425 if (irq == NMI_VECTOR)
7460fb4a 5426 vcpu->arch.nmi_pending = 0;
63995653
MG		 5427 else
5428 vcpu->arch.interrupt.pending = false;
5429
5430 return EMULATE_DONE;
5431}
5432EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5433
6d77dbfc
GN		 5434static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5435{
fc3a9157
JR		 5436 int r = EMULATE_DONE;
5437
6d77dbfc
GN		 5438 ++vcpu->stat.insn_emulation_fail;
5439 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5440 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5441 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5442 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5443 vcpu->run->internal.ndata = 0;
1f4dcb3b 5444 r = EMULATE_USER_EXIT;
fc3a9157 5445 }
6d77dbfc 5446 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5447
5448 return r;
6d77dbfc
GN		 5449}
5450
93c05d3e 5451static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5452 bool write_fault_to_shadow_pgtable,
5453 int emulation_type)
a6f177ef 5454{
95b3cf69 5455 gpa_t gpa = cr2;
ba049e93 5456 kvm_pfn_t pfn;
a6f177ef 5457
991eebf9
GN		 5458 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5459 return false;
5460
95b3cf69
XG		 5461 if (!vcpu->arch.mmu.direct_map) {
5462 /*
5463 * Write permission should be allowed since only
5464 * write access need to be emulated.
5465 */
5466 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5467
95b3cf69
XG		 5468 /*
5469 * If the mapping is invalid in guest, let cpu retry
5470 * it to generate fault.
5471 */
5472 if (gpa == UNMAPPED_GVA)
5473 return true;
5474 }
a6f177ef 5475
8e3d9d06
XG		 5476 /*
5477 * Do not retry the unhandleable instruction if it faults on the
5478 * readonly host memory, otherwise it will goto a infinite loop:
5479 * retry instruction -> write #PF -> emulation fail -> retry
5480 * instruction -> ...
5481 */
5482 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5483
5484 /*
5485 * If the instruction failed on the error pfn, it can not be fixed,
5486 * report the error to userspace.
5487 */
5488 if (is_error_noslot_pfn(pfn))
5489 return false;
5490
5491 kvm_release_pfn_clean(pfn);
5492
5493 /* The instructions are well-emulated on direct mmu. */
5494 if (vcpu->arch.mmu.direct_map) {
5495 unsigned int indirect_shadow_pages;
5496
5497 spin_lock(&vcpu->kvm->mmu_lock);
5498 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5499 spin_unlock(&vcpu->kvm->mmu_lock);
5500
5501 if (indirect_shadow_pages)
5502 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5503
a6f177ef 5504 return true;
8e3d9d06 5505 }
a6f177ef 5506
95b3cf69
XG		 5507 /*
5508 * if emulation was due to access to shadowed page table
5509 * and it failed try to unshadow page and re-enter the
5510 * guest to let CPU execute the instruction.
5511 */
5512 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5513
5514 /*
5515 * If the access faults on its page table, it can not
5516 * be fixed by unprotecting shadow page and it should
5517 * be reported to userspace.
5518 */
5519 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5520}
5521
1cb3f3ae
XG		 5522static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5523 unsigned long cr2, int emulation_type)
5524{
5525 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5526 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5527
5528 last_retry_eip = vcpu->arch.last_retry_eip;
5529 last_retry_addr = vcpu->arch.last_retry_addr;
5530
5531 /*
5532 * If the emulation is caused by #PF and it is non-page_table
5533 * writing instruction, it means the VM-EXIT is caused by shadow
5534 * page protected, we can zap the shadow page and retry this
5535 * instruction directly.
5536 *
5537 * Note: if the guest uses a non-page-table modifying instruction
5538 * on the PDE that points to the instruction, then we will unmap
5539 * the instruction and go to an infinite loop. So, we cache the
5540 * last retried eip and the last fault address, if we meet the eip
5541 * and the address again, we can break out of the potential infinite
5542 * loop.
5543 */
5544 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5545
5546 if (!(emulation_type & EMULTYPE_RETRY))
5547 return false;
5548
5549 if (x86_page_table_writing_insn(ctxt))
5550 return false;
5551
5552 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5553 return false;
5554
5555 vcpu->arch.last_retry_eip = ctxt->eip;
5556 vcpu->arch.last_retry_addr = cr2;
5557
5558 if (!vcpu->arch.mmu.direct_map)
5559 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5560
22368028 5561 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5562
5563 return true;
5564}
5565
716d51ab
GN		 5566static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5567static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5568
64d60670 5569static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5570{
64d60670 5571 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5572 /* This is a good place to trace that we are exiting SMM. */
5573 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5574
c43203ca
PB		 5575 /* Process a latched INIT or SMI, if any. */
5576 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5577 }
699023e2
PB		 5578
5579 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5580}
5581
5582static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5583{
5584 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5585
a584539b 5586 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5587
5588 if (changed & HF_SMM_MASK)
5589 kvm_smm_changed(vcpu);
a584539b
PB		 5590}
5591
4a1e10d5
PB		 5592static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5593 unsigned long *db)
5594{
5595 u32 dr6 = 0;
5596 int i;
5597 u32 enable, rwlen;
5598
5599 enable = dr7;
5600 rwlen = dr7 >> 16;
5601 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5602 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5603 dr6 |= (1 << i);
5604 return dr6;
5605}
5606
c8401dda 5607static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5608{
5609 struct kvm_run *kvm_run = vcpu->run;
5610
c8401dda
PB		 5611 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5612 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5613 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5614 kvm_run->debug.arch.exception = DB_VECTOR;
5615 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5616 *r = EMULATE_USER_EXIT;
5617 } else {
5618 /*
5619 * "Certain debug exceptions may clear bit 0-3. The
5620 * remaining contents of the DR6 register are never
5621 * cleared by the processor".
5622 */
5623 vcpu->arch.dr6 &= ~15;
5624 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5625 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5626 }
5627}
5628
6affcbed
KH		 5629int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5630{
5631 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5632 int r = EMULATE_DONE;
5633
5634 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5635
5636 /*
5637 * rflags is the old, "raw" value of the flags. The new value has
5638 * not been saved yet.
5639 *
5640 * This is correct even for TF set by the guest, because "the
5641 * processor will not generate this exception after the instruction
5642 * that sets the TF flag".
5643 */
5644 if (unlikely(rflags & X86_EFLAGS_TF))
5645 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5646 return r == EMULATE_DONE;
5647}
5648EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5649
4a1e10d5
PB		 5650static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5651{
4a1e10d5
PB		 5652 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5653 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5654 struct kvm_run *kvm_run = vcpu->run;
5655 unsigned long eip = kvm_get_linear_rip(vcpu);
5656 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5657 vcpu->arch.guest_debug_dr7,
5658 vcpu->arch.eff_db);
5659
5660 if (dr6 != 0) {
6f43ed01 5661 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5662 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5663 kvm_run->debug.arch.exception = DB_VECTOR;
5664 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5665 *r = EMULATE_USER_EXIT;
5666 return true;
5667 }
5668 }
5669
4161a569
NA		 5670 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5671 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5672 unsigned long eip = kvm_get_linear_rip(vcpu);
5673 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5674 vcpu->arch.dr7,
5675 vcpu->arch.db);
5676
5677 if (dr6 != 0) {
5678 vcpu->arch.dr6 &= ~15;
6f43ed01 5679 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5680 kvm_queue_exception(vcpu, DB_VECTOR);
5681 *r = EMULATE_DONE;
5682 return true;
5683 }
5684 }
5685
5686 return false;
5687}
5688
51d8b661
AP		 5689int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5690 unsigned long cr2,
dc25e89e
AP		 5691 int emulation_type,
5692 void *insn,
5693 int insn_len)
bbd9b64e 5694{
95cb2295 5695 int r;
9d74191a 5696 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5697 bool writeback = true;
93c05d3e 5698 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5699
f0ace387
PB		 5700 vcpu->arch.l1tf_flush_l1d = true;
5701
93c05d3e
XG		 5702 /*
5703 * Clear write_fault_to_shadow_pgtable here to ensure it is
5704 * never reused.
5705 */
5706 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5707 kvm_clear_exception_queue(vcpu);
8d7d8102 5708
571008da 5709 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5710 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5711
5712 /*
5713 * We will reenter on the same instruction since
5714 * we do not set complete_userspace_io. This does not
5715 * handle watchpoints yet, those would be handled in
5716 * the emulate_ops.
5717 */
60165b0a
VK		 5718 if (!(emulation_type & EMULTYPE_SKIP) &&
5719 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5720 return r;
5721
9d74191a
TY		 5722 ctxt->interruptibility = 0;
5723 ctxt->have_exception = false;
e0ad0b47 5724 ctxt->exception.vector = -1;
9d74191a 5725 ctxt->perm_ok = false;
bbd9b64e 5726
b51e974f 5727 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5728
9d74191a 5729 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5730
e46479f8 5731 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5732 ++vcpu->stat.insn_emulation;
1d2887e2 5733 if (r != EMULATION_OK) {
4005996e
AK		 5734 if (emulation_type & EMULTYPE_TRAP_UD)
5735 return EMULATE_FAIL;
991eebf9
GN		 5736 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5737 emulation_type))
bbd9b64e 5738 return EMULATE_DONE;
6ea6e843
PB		 5739 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5740 return EMULATE_DONE;
6d77dbfc
GN		 5741 if (emulation_type & EMULTYPE_SKIP)
5742 return EMULATE_FAIL;
5743 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5744 }
5745 }
5746
ba8afb6b 5747 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5748 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5749 if (ctxt->eflags & X86_EFLAGS_RF)
5750 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5751 return EMULATE_DONE;
5752 }
5753
1cb3f3ae
XG		 5754 if (retry_instruction(ctxt, cr2, emulation_type))
5755 return EMULATE_DONE;
5756
7ae441ea 5757 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5758 changes registers values during IO operation */
7ae441ea
GN		 5759 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5760 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5761 emulator_invalidate_register_cache(ctxt);
7ae441ea 5762 }
4d2179e1 5763
5cd21917 5764restart:
0f89b207
TL		 5765 /* Save the faulting GPA (cr2) in the address field */
5766 ctxt->exception.address = cr2;
5767
9d74191a 5768 r = x86_emulate_insn(ctxt);
bbd9b64e 5769
775fde86
JR		 5770 if (r == EMULATION_INTERCEPTED)
5771 return EMULATE_DONE;
5772
d2ddd1c4 5773 if (r == EMULATION_FAILED) {
991eebf9
GN		 5774 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5775 emulation_type))
c3cd7ffa
GN		 5776 return EMULATE_DONE;
5777
6d77dbfc 5778 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5779 }
5780
9d74191a 5781 if (ctxt->have_exception) {
d2ddd1c4 5782 r = EMULATE_DONE;
ef54bcfe
PB		 5783 if (inject_emulated_exception(vcpu))
5784 return r;
d2ddd1c4 5785 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5786 if (!vcpu->arch.pio.in) {
5787 /* FIXME: return into emulator if single-stepping. */
3457e419 5788 vcpu->arch.pio.count = 0;
0912c977 5789 } else {
7ae441ea 5790 writeback = false;
716d51ab
GN		 5791 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5792 }
ac0a48c3 5793 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5794 } else if (vcpu->mmio_needed) {
5795 if (!vcpu->mmio_is_write)
5796 writeback = false;
ac0a48c3 5797 r = EMULATE_USER_EXIT;
716d51ab 5798 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5799 } else if (r == EMULATION_RESTART)
5cd21917 5800 goto restart;
d2ddd1c4
GN		 5801 else
5802 r = EMULATE_DONE;
f850e2e6 5803
7ae441ea 5804 if (writeback) {
6addfc42 5805 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5806 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5807 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5808 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5809 if (r == EMULATE_DONE &&
5810 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5811 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5812 if (!ctxt->have_exception ||
5813 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5814 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5815
5816 /*
5817 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5818 * do nothing, and it will be requested again as soon as
5819 * the shadow expires. But we still need to check here,
5820 * because POPF has no interrupt shadow.
5821 */
5822 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5823 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5824 } else
5825 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5826
5827 return r;
de7d789a 5828}
51d8b661 5829EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5830
cf8f70bf 5831int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5832{
cf8f70bf 5833 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5834 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5835 size, port, &val, 1);
cf8f70bf 5836 /* do not return to emulator after return from userspace */
7972995b 5837 vcpu->arch.pio.count = 0;
de7d789a
CO		 5838 return ret;
5839}
cf8f70bf 5840EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5841
8370c3d0
TL		 5842static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5843{
5844 unsigned long val;
5845
5846 /* We should only ever be called with arch.pio.count equal to 1 */
5847 BUG_ON(vcpu->arch.pio.count != 1);
5848
5849 /* For size less than 4 we merge, else we zero extend */
5850 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5851 : 0;
5852
5853 /*
5854 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5855 * the copy and tracing
5856 */
5857 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5858 vcpu->arch.pio.port, &val, 1);
5859 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5860
5861 return 1;
5862}
5863
5864int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5865{
5866 unsigned long val;
5867 int ret;
5868
5869 /* For size less than 4 we merge, else we zero extend */
5870 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5871
5872 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5873 &val, 1);
5874 if (ret) {
5875 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5876 return ret;
5877 }
5878
5879 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5880
5881 return 0;
5882}
5883EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5884
251a5fd6 5885static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5886{
0a3aee0d 5887 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5888 return 0;
8cfdc000
ZA		 5889}
5890
5891static void tsc_khz_changed(void *data)
c8076604 5892{
8cfdc000
ZA		 5893 struct cpufreq_freqs *freq = data;
5894 unsigned long khz = 0;
5895
5896 if (data)
5897 khz = freq->new;
5898 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5899 khz = cpufreq_quick_get(raw_smp_processor_id());
5900 if (!khz)
5901 khz = tsc_khz;
0a3aee0d 5902 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5903}
5904
c8076604
GH		 5905static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5906 void *data)
5907{
5908 struct cpufreq_freqs *freq = data;
5909 struct kvm *kvm;
5910 struct kvm_vcpu *vcpu;
5911 int i, send_ipi = 0;
5912
8cfdc000
ZA		 5913 /*
5914 * We allow guests to temporarily run on slowing clocks,
5915 * provided we notify them after, or to run on accelerating
5916 * clocks, provided we notify them before. Thus time never
5917 * goes backwards.
5918 *
5919 * However, we have a problem. We can't atomically update
5920 * the frequency of a given CPU from this function; it is
5921 * merely a notifier, which can be called from any CPU.
5922 * Changing the TSC frequency at arbitrary points in time
5923 * requires a recomputation of local variables related to
5924 * the TSC for each VCPU. We must flag these local variables
5925 * to be updated and be sure the update takes place with the
5926 * new frequency before any guests proceed.
5927 *
5928 * Unfortunately, the combination of hotplug CPU and frequency
5929 * change creates an intractable locking scenario; the order
5930 * of when these callouts happen is undefined with respect to
5931 * CPU hotplug, and they can race with each other. As such,
5932 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5933 * undefined; you can actually have a CPU frequency change take
5934 * place in between the computation of X and the setting of the
5935 * variable. To protect against this problem, all updates of
5936 * the per_cpu tsc_khz variable are done in an interrupt
5937 * protected IPI, and all callers wishing to update the value
5938 * must wait for a synchronous IPI to complete (which is trivial
5939 * if the caller is on the CPU already). This establishes the
5940 * necessary total order on variable updates.
5941 *
5942 * Note that because a guest time update may take place
5943 * anytime after the setting of the VCPU's request bit, the
5944 * correct TSC value must be set before the request. However,
5945 * to ensure the update actually makes it to any guest which
5946 * starts running in hardware virtualization between the set
5947 * and the acquisition of the spinlock, we must also ping the
5948 * CPU after setting the request bit.
5949 *
5950 */
5951
c8076604
GH		 5952 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5953 return 0;
5954 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5955 return 0;
8cfdc000
ZA		 5956
5957 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5958
2f303b74 5959 spin_lock(&kvm_lock);
c8076604 5960 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5961 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5962 if (vcpu->cpu != freq->cpu)
5963 continue;
c285545f 5964 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5965 if (vcpu->cpu != smp_processor_id())
8cfdc000 5966 send_ipi = 1;
c8076604
GH		 5967 }
5968 }
2f303b74 5969 spin_unlock(&kvm_lock);
c8076604
GH		 5970
5971 if (freq->old < freq->new && send_ipi) {
5972 /*
5973 * We upscale the frequency. Must make the guest
5974 * doesn't see old kvmclock values while running with
5975 * the new frequency, otherwise we risk the guest sees
5976 * time go backwards.
5977 *
5978 * In case we update the frequency for another cpu
5979 * (which might be in guest context) send an interrupt
5980 * to kick the cpu out of guest context. Next time
5981 * guest context is entered kvmclock will be updated,
5982 * so the guest will not see stale values.
5983 */
8cfdc000 5984 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5985 }
5986 return 0;
5987}
5988
5989static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5990 .notifier_call = kvmclock_cpufreq_notifier
5991};
5992
251a5fd6 5993static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5994{
251a5fd6
SAS		 5995 tsc_khz_changed(NULL);
5996 return 0;
8cfdc000
ZA		 5997}
5998
b820cc0c
ZA		 5999static void kvm_timer_init(void)
6000{
c285545f 6001 max_tsc_khz = tsc_khz;
460dd42e 6002
b820cc0c 6003 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6004#ifdef CONFIG_CPU_FREQ
6005 struct cpufreq_policy policy;
758f588d
BP		 6006 int cpu;
6007
c285545f 6008 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6009 cpu = get_cpu();
6010 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6011 if (policy.cpuinfo.max_freq)
6012 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6013 put_cpu();
c285545f 6014#endif
b820cc0c
ZA		 6015 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6016 CPUFREQ_TRANSITION_NOTIFIER);
6017 }
c285545f 6018 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6019
73c1b41e 6020 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6021 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6022}
6023
ff9d07a0
ZY		 6024static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6025
f5132b01 6026int kvm_is_in_guest(void)
ff9d07a0 6027{
086c9855 6028 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6029}
6030
6031static int kvm_is_user_mode(void)
6032{
6033 int user_mode = 3;
dcf46b94 6034
086c9855
AS		 6035 if (__this_cpu_read(current_vcpu))
6036 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6037
ff9d07a0
ZY		 6038 return user_mode != 0;
6039}
6040
6041static unsigned long kvm_get_guest_ip(void)
6042{
6043 unsigned long ip = 0;
dcf46b94 6044
086c9855
AS		 6045 if (__this_cpu_read(current_vcpu))
6046 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6047
ff9d07a0
ZY		 6048 return ip;
6049}
6050
6051static struct perf_guest_info_callbacks kvm_guest_cbs = {
6052 .is_in_guest = kvm_is_in_guest,
6053 .is_user_mode = kvm_is_user_mode,
6054 .get_guest_ip = kvm_get_guest_ip,
6055};
6056
6057void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6058{
086c9855 6059 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6060}
6061EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6062
6063void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6064{
086c9855 6065 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6066}
6067EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6068
ce88decf
XG		 6069static void kvm_set_mmio_spte_mask(void)
6070{
6071 u64 mask;
6072 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6073
6074 /*
6075 * Set the reserved bits and the present bit of an paging-structure
6076 * entry to generate page fault with PFER.RSV = 1.
6077 */
885032b9 6078 /* Mask the reserved physical address bits. */
d1431483 6079 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6080
885032b9 6081 /* Set the present bit. */
ce88decf
XG		 6082 mask |= 1ull;
6083
6084#ifdef CONFIG_X86_64
6085 /*
6086 * If reserved bit is not supported, clear the present bit to disable
6087 * mmio page fault.
6088 */
6089 if (maxphyaddr == 52)
6090 mask &= ~1ull;
6091#endif
6092
dcdca5fe 6093 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6094}
6095
16e8d74d
MT		 6096#ifdef CONFIG_X86_64
6097static void pvclock_gtod_update_fn(struct work_struct *work)
6098{
d828199e
MT		 6099 struct kvm *kvm;
6100
6101 struct kvm_vcpu *vcpu;
6102 int i;
6103
2f303b74 6104 spin_lock(&kvm_lock);
d828199e
MT		 6105 list_for_each_entry(kvm, &vm_list, vm_list)
6106 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6107 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6108 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6109 spin_unlock(&kvm_lock);
16e8d74d
MT		 6110}
6111
6112static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6113
6114/*
6115 * Notification about pvclock gtod data update.
6116 */
6117static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6118 void *priv)
6119{
6120 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6121 struct timekeeper *tk = priv;
6122
6123 update_pvclock_gtod(tk);
6124
6125 /* disable master clock if host does not trust, or does not
6126 * use, TSC clocksource
6127 */
6128 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6129 atomic_read(&kvm_guest_has_master_clock) != 0)
6130 queue_work(system_long_wq, &pvclock_gtod_work);
6131
6132 return 0;
6133}
6134
6135static struct notifier_block pvclock_gtod_notifier = {
6136 .notifier_call = pvclock_gtod_notify,
6137};
6138#endif
6139
f8c16bba 6140int kvm_arch_init(void *opaque)
043405e1 6141{
b820cc0c 6142 int r;
6b61edf7 6143 struct kvm_x86_ops *ops = opaque;
f8c16bba 6144
f8c16bba
ZX		 6145 if (kvm_x86_ops) {
6146 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6147 r = -EEXIST;
6148 goto out;
f8c16bba
ZX		 6149 }
6150
6151 if (!ops->cpu_has_kvm_support()) {
6152 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6153 r = -EOPNOTSUPP;
6154 goto out;
f8c16bba
ZX		 6155 }
6156 if (ops->disabled_by_bios()) {
1cdfde02 6157 printk(KERN_WARNING "kvm: disabled by bios\n");
56c6d28a
ZX		 6158 r = -EOPNOTSUPP;
6159 goto out;
f8c16bba
ZX		 6160 }
6161
013f6a5d
MT		 6162 r = -ENOMEM;
6163 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6164 if (!shared_msrs) {
6165 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6166 goto out;
6167 }
6168
97db56ce
AK		 6169 r = kvm_mmu_module_init();
6170 if (r)
013f6a5d 6171 goto out_free_percpu;
97db56ce 6172
ce88decf 6173 kvm_set_mmio_spte_mask();
97db56ce 6174
f8c16bba 6175 kvm_x86_ops = ops;
920c8377 6176
7b52345e 6177 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6178 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6179 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6180 kvm_timer_init();
c8076604 6181
ff9d07a0
ZY		 6182 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6183
d366bf7e 6184 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6185 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6186
c5cc421b 6187 kvm_lapic_init();
16e8d74d
MT		 6188#ifdef CONFIG_X86_64
6189 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6190#endif
6191
f8c16bba 6192 return 0;
56c6d28a 6193
013f6a5d
MT		 6194out_free_percpu:
6195 free_percpu(shared_msrs);
56c6d28a 6196out:
56c6d28a 6197 return r;
043405e1 6198}
8776e519 6199
f8c16bba
ZX		 6200void kvm_arch_exit(void)
6201{
cef84c30 6202 kvm_lapic_exit();
ff9d07a0
ZY		 6203 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6204
888d256e
JK		 6205 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6206 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6207 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6208 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6209#ifdef CONFIG_X86_64
6210 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6211#endif
f8c16bba 6212 kvm_x86_ops = NULL;
56c6d28a 6213 kvm_mmu_module_exit();
013f6a5d 6214 free_percpu(shared_msrs);
56c6d28a 6215}
f8c16bba 6216
5cb56059 6217int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6218{
6219 ++vcpu->stat.halt_exits;
35754c98 6220 if (lapic_in_kernel(vcpu)) {
a4535290 6221 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6222 return 1;
6223 } else {
6224 vcpu->run->exit_reason = KVM_EXIT_HLT;
6225 return 0;
6226 }
6227}
5cb56059
JS		 6228EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6229
6230int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6231{
6affcbed
KH		 6232 int ret = kvm_skip_emulated_instruction(vcpu);
6233 /*
6234 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6235 * KVM_EXIT_DEBUG here.
6236 */
6237 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6238}
8776e519
HB		 6239EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6240
8ef81a9a 6241#ifdef CONFIG_X86_64
55dd00a7
MT		 6242static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6243 unsigned long clock_type)
6244{
6245 struct kvm_clock_pairing clock_pairing;
6246 struct timespec ts;
80fbd89c 6247 u64 cycle;
55dd00a7
MT		 6248 int ret;
6249
6250 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6251 return -KVM_EOPNOTSUPP;
6252
6253 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6254 return -KVM_EOPNOTSUPP;
6255
6256 clock_pairing.sec = ts.tv_sec;
6257 clock_pairing.nsec = ts.tv_nsec;
6258 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6259 clock_pairing.flags = 0;
6260
6261 ret = 0;
6262 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6263 sizeof(struct kvm_clock_pairing)))
6264 ret = -KVM_EFAULT;
6265
6266 return ret;
6267}
8ef81a9a 6268#endif
55dd00a7 6269
6aef266c
SV		 6270/*
6271 * kvm_pv_kick_cpu_op: Kick a vcpu.
6272 *
6273 * @apicid - apicid of vcpu to be kicked.
6274 */
6275static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6276{
24d2166b 6277 struct kvm_lapic_irq lapic_irq;
6aef266c 6278
24d2166b
R		 6279 lapic_irq.shorthand = 0;
6280 lapic_irq.dest_mode = 0;
ebd28fcb 6281 lapic_irq.level = 0;
24d2166b 6282 lapic_irq.dest_id = apicid;
93bbf0b8 6283 lapic_irq.msi_redir_hint = false;
6aef266c 6284
24d2166b 6285 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6286 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6287}
6288
d62caabb
AS		 6289void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6290{
6291 vcpu->arch.apicv_active = false;
6292 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6293}
6294
8776e519
HB		 6295int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6296{
6297 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6298 int op_64_bit, r;
8776e519 6299
6affcbed 6300 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6301
55cd8e5a
GN		 6302 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6303 return kvm_hv_hypercall(vcpu);
6304
5fdbf976
MT		 6305 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6306 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6307 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6308 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6309 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6310
229456fc 6311 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6312
a449c7aa
NA		 6313 op_64_bit = is_64_bit_mode(vcpu);
6314 if (!op_64_bit) {
8776e519
HB		 6315 nr &= 0xFFFFFFFF;
6316 a0 &= 0xFFFFFFFF;
6317 a1 &= 0xFFFFFFFF;
6318 a2 &= 0xFFFFFFFF;
6319 a3 &= 0xFFFFFFFF;
6320 }
6321
07708c4a
JK		 6322 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6323 ret = -KVM_EPERM;
6324 goto out;
6325 }
6326
8776e519 6327 switch (nr) {
b93463aa
AK		 6328 case KVM_HC_VAPIC_POLL_IRQ:
6329 ret = 0;
6330 break;
6aef266c
SV		 6331 case KVM_HC_KICK_CPU:
6332 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6333 ret = 0;
6334 break;
8ef81a9a 6335#ifdef CONFIG_X86_64
55dd00a7
MT		 6336 case KVM_HC_CLOCK_PAIRING:
6337 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6338 break;
8ef81a9a 6339#endif
8776e519
HB		 6340 default:
6341 ret = -KVM_ENOSYS;
6342 break;
6343 }
07708c4a 6344out:
a449c7aa
NA		 6345 if (!op_64_bit)
6346 ret = (u32)ret;
5fdbf976 6347 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6348 ++vcpu->stat.hypercalls;
2f333bcb 6349 return r;
8776e519
HB		 6350}
6351EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6352
b6785def 6353static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6354{
d6aa1000 6355 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6356 char instruction[3];
5fdbf976 6357 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6358
8776e519 6359 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6360
ce2e852e
DV		 6361 return emulator_write_emulated(ctxt, rip, instruction, 3,
6362 &ctxt->exception);
8776e519
HB		 6363}
6364
851ba692 6365static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6366{
782d422b
MG		 6367 return vcpu->run->request_interrupt_window &&
6368 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6369}
6370
851ba692 6371static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6372{
851ba692
AK		 6373 struct kvm_run *kvm_run = vcpu->run;
6374
91586a3b 6375 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6376 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6377 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6378 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6379 kvm_run->ready_for_interrupt_injection =
6380 pic_in_kernel(vcpu->kvm) ||
782d422b 6381 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6382}
6383
95ba8273
GN		 6384static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6385{
6386 int max_irr, tpr;
6387
6388 if (!kvm_x86_ops->update_cr8_intercept)
6389 return;
6390
bce87cce 6391 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6392 return;
6393
d62caabb
AS		 6394 if (vcpu->arch.apicv_active)
6395 return;
6396
8db3baa2
GN		 6397 if (!vcpu->arch.apic->vapic_addr)
6398 max_irr = kvm_lapic_find_highest_irr(vcpu);
6399 else
6400 max_irr = -1;
95ba8273
GN		 6401
6402 if (max_irr != -1)
6403 max_irr >>= 4;
6404
6405 tpr = kvm_lapic_get_cr8(vcpu);
6406
6407 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6408}
6409
b6b8a145 6410static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6411{
b6b8a145
JK		 6412 int r;
6413
95ba8273 6414 /* try to reinject previous events if any */
664f8e26
WL		 6415 if (vcpu->arch.exception.injected) {
6416 kvm_x86_ops->queue_exception(vcpu);
6417 return 0;
6418 }
6419
6420 /*
6421 * Exceptions must be injected immediately, or the exception
6422 * frame will have the address of the NMI or interrupt handler.
6423 */
6424 if (!vcpu->arch.exception.pending) {
6425 if (vcpu->arch.nmi_injected) {
6426 kvm_x86_ops->set_nmi(vcpu);
6427 return 0;
6428 }
6429
6430 if (vcpu->arch.interrupt.pending) {
6431 kvm_x86_ops->set_irq(vcpu);
6432 return 0;
6433 }
6434 }
6435
6436 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6437 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6438 if (r != 0)
6439 return r;
6440 }
6441
6442 /* try to inject new event if pending */
b59bb7bd 6443 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6444 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6445 vcpu->arch.exception.has_error_code,
6446 vcpu->arch.exception.error_code);
d6e8c854 6447
664f8e26
WL		 6448 vcpu->arch.exception.pending = false;
6449 vcpu->arch.exception.injected = true;
6450
d6e8c854
NA		 6451 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6452 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6453 X86_EFLAGS_RF);
6454
6bdf0662
NA		 6455 if (vcpu->arch.exception.nr == DB_VECTOR &&
6456 (vcpu->arch.dr7 & DR7_GD)) {
6457 vcpu->arch.dr7 &= ~DR7_GD;
6458 kvm_update_dr7(vcpu);
6459 }
6460
cfcd20e5 6461 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6462 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6463 vcpu->arch.smi_pending = false;
ee2cd4b7 6464 enter_smm(vcpu);
c43203ca 6465 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6466 --vcpu->arch.nmi_pending;
6467 vcpu->arch.nmi_injected = true;
6468 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6469 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6470 /*
6471 * Because interrupts can be injected asynchronously, we are
6472 * calling check_nested_events again here to avoid a race condition.
6473 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6474 * proposal and current concerns. Perhaps we should be setting
6475 * KVM_REQ_EVENT only on certain events and not unconditionally?
6476 */
6477 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6478 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6479 if (r != 0)
6480 return r;
6481 }
95ba8273 6482 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6483 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6484 false);
6485 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6486 }
6487 }
ee2cd4b7 6488
b6b8a145 6489 return 0;
95ba8273
GN		 6490}
6491
7460fb4a
AK		 6492static void process_nmi(struct kvm_vcpu *vcpu)
6493{
6494 unsigned limit = 2;
6495
6496 /*
6497 * x86 is limited to one NMI running, and one NMI pending after it.
6498 * If an NMI is already in progress, limit further NMIs to just one.
6499 * Otherwise, allow two (and we'll inject the first one immediately).
6500 */
6501 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6502 limit = 1;
6503
6504 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6505 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6506 kvm_make_request(KVM_REQ_EVENT, vcpu);
6507}
6508
ee2cd4b7 6509static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6510{
6511 u32 flags = 0;
6512 flags |= seg->g << 23;
6513 flags |= seg->db << 22;
6514 flags |= seg->l << 21;
6515 flags |= seg->avl << 20;
6516 flags |= seg->present << 15;
6517 flags |= seg->dpl << 13;
6518 flags |= seg->s << 12;
6519 flags |= seg->type << 8;
6520 return flags;
6521}
6522
ee2cd4b7 6523static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6524{
6525 struct kvm_segment seg;
6526 int offset;
6527
6528 kvm_get_segment(vcpu, &seg, n);
6529 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6530
6531 if (n < 3)
6532 offset = 0x7f84 + n * 12;
6533 else
6534 offset = 0x7f2c + (n - 3) * 12;
6535
6536 put_smstate(u32, buf, offset + 8, seg.base);
6537 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6538 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6539}
6540
efbb288a 6541#ifdef CONFIG_X86_64
ee2cd4b7 6542static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6543{
6544 struct kvm_segment seg;
6545 int offset;
6546 u16 flags;
6547
6548 kvm_get_segment(vcpu, &seg, n);
6549 offset = 0x7e00 + n * 16;
6550
ee2cd4b7 6551 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6552 put_smstate(u16, buf, offset, seg.selector);
6553 put_smstate(u16, buf, offset + 2, flags);
6554 put_smstate(u32, buf, offset + 4, seg.limit);
6555 put_smstate(u64, buf, offset + 8, seg.base);
6556}
efbb288a 6557#endif
660a5d51 6558
ee2cd4b7 6559static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6560{
6561 struct desc_ptr dt;
6562 struct kvm_segment seg;
6563 unsigned long val;
6564 int i;
6565
6566 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6567 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6568 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6569 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6570
6571 for (i = 0; i < 8; i++)
6572 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6573
6574 kvm_get_dr(vcpu, 6, &val);
6575 put_smstate(u32, buf, 0x7fcc, (u32)val);
6576 kvm_get_dr(vcpu, 7, &val);
6577 put_smstate(u32, buf, 0x7fc8, (u32)val);
6578
6579 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6580 put_smstate(u32, buf, 0x7fc4, seg.selector);
6581 put_smstate(u32, buf, 0x7f64, seg.base);
6582 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6583 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6584
6585 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6586 put_smstate(u32, buf, 0x7fc0, seg.selector);
6587 put_smstate(u32, buf, 0x7f80, seg.base);
6588 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6589 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6590
6591 kvm_x86_ops->get_gdt(vcpu, &dt);
6592 put_smstate(u32, buf, 0x7f74, dt.address);
6593 put_smstate(u32, buf, 0x7f70, dt.size);
6594
6595 kvm_x86_ops->get_idt(vcpu, &dt);
6596 put_smstate(u32, buf, 0x7f58, dt.address);
6597 put_smstate(u32, buf, 0x7f54, dt.size);
6598
6599 for (i = 0; i < 6; i++)
ee2cd4b7 6600 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6601
6602 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6603
6604 /* revision id */
6605 put_smstate(u32, buf, 0x7efc, 0x00020000);
6606 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6607}
6608
ee2cd4b7 6609static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6610{
6611#ifdef CONFIG_X86_64
6612 struct desc_ptr dt;
6613 struct kvm_segment seg;
6614 unsigned long val;
6615 int i;
6616
6617 for (i = 0; i < 16; i++)
6618 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6619
6620 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6621 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6622
6623 kvm_get_dr(vcpu, 6, &val);
6624 put_smstate(u64, buf, 0x7f68, val);
6625 kvm_get_dr(vcpu, 7, &val);
6626 put_smstate(u64, buf, 0x7f60, val);
6627
6628 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6629 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6630 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6631
6632 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6633
6634 /* revision id */
6635 put_smstate(u32, buf, 0x7efc, 0x00020064);
6636
6637 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6638
6639 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6640 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6641 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6642 put_smstate(u32, buf, 0x7e94, seg.limit);
6643 put_smstate(u64, buf, 0x7e98, seg.base);
6644
6645 kvm_x86_ops->get_idt(vcpu, &dt);
6646 put_smstate(u32, buf, 0x7e84, dt.size);
6647 put_smstate(u64, buf, 0x7e88, dt.address);
6648
6649 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6650 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6651 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6652 put_smstate(u32, buf, 0x7e74, seg.limit);
6653 put_smstate(u64, buf, 0x7e78, seg.base);
6654
6655 kvm_x86_ops->get_gdt(vcpu, &dt);
6656 put_smstate(u32, buf, 0x7e64, dt.size);
6657 put_smstate(u64, buf, 0x7e68, dt.address);
6658
6659 for (i = 0; i < 6; i++)
ee2cd4b7 6660 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6661#else
6662 WARN_ON_ONCE(1);
6663#endif
6664}
6665
ee2cd4b7 6666static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6667{
660a5d51 6668 struct kvm_segment cs, ds;
18c3626e 6669 struct desc_ptr dt;
660a5d51
PB		 6670 char buf[512];
6671 u32 cr0;
6672
660a5d51 6673 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6674 memset(buf, 0, 512);
d6321d49 6675 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6676 enter_smm_save_state_64(vcpu, buf);
660a5d51 6677 else
ee2cd4b7 6678 enter_smm_save_state_32(vcpu, buf);
660a5d51 6679
0234bf88
LP		 6680 /*
6681 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6682 * vCPU state (e.g. leave guest mode) after we've saved the state into
6683 * the SMM state-save area.
6684 */
6685 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6686
6687 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6688 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6689
6690 if (kvm_x86_ops->get_nmi_mask(vcpu))
6691 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6692 else
6693 kvm_x86_ops->set_nmi_mask(vcpu, true);
6694
6695 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6696 kvm_rip_write(vcpu, 0x8000);
6697
6698 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6699 kvm_x86_ops->set_cr0(vcpu, cr0);
6700 vcpu->arch.cr0 = cr0;
6701
6702 kvm_x86_ops->set_cr4(vcpu, 0);
6703
18c3626e
PB		 6704 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6705 dt.address = dt.size = 0;
6706 kvm_x86_ops->set_idt(vcpu, &dt);
6707
660a5d51
PB		 6708 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6709
6710 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6711 cs.base = vcpu->arch.smbase;
6712
6713 ds.selector = 0;
6714 ds.base = 0;
6715
6716 cs.limit = ds.limit = 0xffffffff;
6717 cs.type = ds.type = 0x3;
6718 cs.dpl = ds.dpl = 0;
6719 cs.db = ds.db = 0;
6720 cs.s = ds.s = 1;
6721 cs.l = ds.l = 0;
6722 cs.g = ds.g = 1;
6723 cs.avl = ds.avl = 0;
6724 cs.present = ds.present = 1;
6725 cs.unusable = ds.unusable = 0;
6726 cs.padding = ds.padding = 0;
6727
6728 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6729 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6730 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6731 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6732 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6733 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6734
d6321d49 6735 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6736 kvm_x86_ops->set_efer(vcpu, 0);
6737
6738 kvm_update_cpuid(vcpu);
6739 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6740}
6741
ee2cd4b7 6742static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6743{
6744 vcpu->arch.smi_pending = true;
6745 kvm_make_request(KVM_REQ_EVENT, vcpu);
6746}
6747
2860c4b1
PB		 6748void kvm_make_scan_ioapic_request(struct kvm *kvm)
6749{
6750 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6751}
6752
3d81bc7e 6753static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6754{
5c919412
AS		 6755 u64 eoi_exit_bitmap[4];
6756
3d81bc7e
YZ		 6757 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6758 return;
c7c9c56c 6759
6308630b 6760 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6761
b053b2ae 6762 if (irqchip_split(vcpu->kvm))
6308630b 6763 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6764 else {
76dfafd5 6765 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6766 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6767 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6768 }
5c919412
AS		 6769 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6770 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6771 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6772}
6773
a70656b6
RK		 6774static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6775{
6776 ++vcpu->stat.tlb_flush;
6777 kvm_x86_ops->tlb_flush(vcpu);
6778}
6779
b1394e74
RK		 6780void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6781 unsigned long start, unsigned long end)
6782{
6783 unsigned long apic_address;
6784
6785 /*
6786 * The physical address of apic access page is stored in the VMCS.
6787 * Update it when it becomes invalid.
6788 */
6789 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6790 if (start <= apic_address && apic_address < end)
6791 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6792}
6793
4256f43f
TC		 6794void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6795{
c24ae0dc
TC		 6796 struct page *page = NULL;
6797
35754c98 6798 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6799 return;
6800
4256f43f
TC		 6801 if (!kvm_x86_ops->set_apic_access_page_addr)
6802 return;
6803
c24ae0dc 6804 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6805 if (is_error_page(page))
6806 return;
c24ae0dc
TC		 6807 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6808
6809 /*
6810 * Do not pin apic access page in memory, the MMU notifier
6811 * will call us again if it is migrated or swapped out.
6812 */
6813 put_page(page);
4256f43f
TC		 6814}
6815EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6816
9357d939 6817/*
362c698f 6818 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6819 * exiting to the userspace. Otherwise, the value will be returned to the
6820 * userspace.
6821 */
851ba692 6822static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6823{
6824 int r;
62a193ed
MG		 6825 bool req_int_win =
6826 dm_request_for_irq_injection(vcpu) &&
6827 kvm_cpu_accept_dm_intr(vcpu);
6828
730dca42 6829 bool req_immediate_exit = false;
b6c7a5dc 6830
2fa6e1e1 6831 if (kvm_request_pending(vcpu)) {
a8eeb04a 6832 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6833 kvm_mmu_unload(vcpu);
a8eeb04a 6834 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6835 __kvm_migrate_timers(vcpu);
d828199e
MT		 6836 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6837 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6838 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6839 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6840 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6841 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6842 if (unlikely(r))
6843 goto out;
6844 }
a8eeb04a 6845 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6846 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6847 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6848 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6849 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6850 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6851 r = 0;
6852 goto out;
6853 }
a8eeb04a 6854 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6855 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6856 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6857 r = 0;
6858 goto out;
6859 }
af585b92
GN		 6860 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6861 /* Page is swapped out. Do synthetic halt */
6862 vcpu->arch.apf.halted = true;
6863 r = 1;
6864 goto out;
6865 }
c9aaa895
GC		 6866 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6867 record_steal_time(vcpu);
64d60670
PB		 6868 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6869 process_smi(vcpu);
7460fb4a
AK		 6870 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6871 process_nmi(vcpu);
f5132b01 6872 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6873 kvm_pmu_handle_event(vcpu);
f5132b01 6874 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6875 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6876 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6877 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6878 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6879 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6880 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6881 vcpu->run->eoi.vector =
6882 vcpu->arch.pending_ioapic_eoi;
6883 r = 0;
6884 goto out;
6885 }
6886 }
3d81bc7e
YZ		 6887 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6888 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6889 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6890 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6891 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6892 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6893 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6894 r = 0;
6895 goto out;
6896 }
e516cebb
AS		 6897 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6898 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6899 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6900 r = 0;
6901 goto out;
6902 }
db397571
AS		 6903 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6904 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6905 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6906 r = 0;
6907 goto out;
6908 }
f3b138c5
AS		 6909
6910 /*
6911 * KVM_REQ_HV_STIMER has to be processed after
6912 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6913 * depend on the guest clock being up-to-date
6914 */
1f4b34f8
AS		 6915 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6916 kvm_hv_process_stimers(vcpu);
2f52d58c 6917 }
b93463aa 6918
b463a6f7 6919 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6920 ++vcpu->stat.req_event;
66450a21
JK		 6921 kvm_apic_accept_events(vcpu);
6922 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6923 r = 1;
6924 goto out;
6925 }
6926
b6b8a145
JK		 6927 if (inject_pending_event(vcpu, req_int_win) != 0)
6928 req_immediate_exit = true;
321c5658 6929 else {
cc3d967f 6930 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6931 *
cc3d967f
LP		 6932 * SMIs have three cases:
6933 * 1) They can be nested, and then there is nothing to
6934 * do here because RSM will cause a vmexit anyway.
6935 * 2) There is an ISA-specific reason why SMI cannot be
6936 * injected, and the moment when this changes can be
6937 * intercepted.
6938 * 3) Or the SMI can be pending because
6939 * inject_pending_event has completed the injection
6940 * of an IRQ or NMI from the previous vmexit, and
6941 * then we request an immediate exit to inject the
6942 * SMI.
c43203ca
PB		 6943 */
6944 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6945 if (!kvm_x86_ops->enable_smi_window(vcpu))
6946 req_immediate_exit = true;
321c5658
YS		 6947 if (vcpu->arch.nmi_pending)
6948 kvm_x86_ops->enable_nmi_window(vcpu);
6949 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6950 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6951 WARN_ON(vcpu->arch.exception.pending);
321c5658 6952 }
b463a6f7
AK		 6953
6954 if (kvm_lapic_enabled(vcpu)) {
6955 update_cr8_intercept(vcpu);
6956 kvm_lapic_sync_to_vapic(vcpu);
6957 }
6958 }
6959
d8368af8
AK		 6960 r = kvm_mmu_reload(vcpu);
6961 if (unlikely(r)) {
d905c069 6962 goto cancel_injection;
d8368af8
AK		 6963 }
6964
b6c7a5dc
HB		 6965 preempt_disable();
6966
6967 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 6968
6969 /*
6970 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6971 * IPI are then delayed after guest entry, which ensures that they
6972 * result in virtual interrupt delivery.
6973 */
6974 local_irq_disable();
6b7e2d09
XG		 6975 vcpu->mode = IN_GUEST_MODE;
6976
01b71917
MT		 6977 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6978
0f127d12 6979 /*
b95234c8 6980 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6981 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6982 *
6983 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6984 * pairs with the memory barrier implicit in pi_test_and_set_on
6985 * (see vmx_deliver_posted_interrupt).
6986 *
6987 * 3) This also orders the write to mode from any reads to the page
6988 * tables done while the VCPU is running. Please see the comment
6989 * in kvm_flush_remote_tlbs.
6b7e2d09 6990 */
01b71917 6991 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6992
b95234c8
PB		 6993 /*
6994 * This handles the case where a posted interrupt was
6995 * notified with kvm_vcpu_kick.
6996 */
6997 if (kvm_lapic_enabled(vcpu)) {
6998 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6999 kvm_x86_ops->sync_pir_to_irr(vcpu);
7000 }
32f88400 7001
2fa6e1e1 7002 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7003 || need_resched() || signal_pending(current)) {
6b7e2d09 7004 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7005 smp_wmb();
6c142801
AK		 7006 local_irq_enable();
7007 preempt_enable();
01b71917 7008 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7009 r = 1;
d905c069 7010 goto cancel_injection;
6c142801
AK		 7011 }
7012
fc5b7f3b
DM		 7013 kvm_load_guest_xcr0(vcpu);
7014
c43203ca
PB		 7015 if (req_immediate_exit) {
7016 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7017 smp_send_reschedule(vcpu->cpu);
c43203ca 7018 }
d6185f20 7019
8b89fe1f
PB		 7020 trace_kvm_entry(vcpu->vcpu_id);
7021 wait_lapic_expire(vcpu);
6edaa530 7022 guest_enter_irqoff();
b6c7a5dc 7023
42dbaa5a 7024 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7025 set_debugreg(0, 7);
7026 set_debugreg(vcpu->arch.eff_db[0], 0);
7027 set_debugreg(vcpu->arch.eff_db[1], 1);
7028 set_debugreg(vcpu->arch.eff_db[2], 2);
7029 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7030 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7031 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7032 }
b6c7a5dc 7033
851ba692 7034 kvm_x86_ops->run(vcpu);
b6c7a5dc 7035
c77fb5fe
PB		 7036 /*
7037 * Do this here before restoring debug registers on the host. And
7038 * since we do this before handling the vmexit, a DR access vmexit
7039 * can (a) read the correct value of the debug registers, (b) set
7040 * KVM_DEBUGREG_WONT_EXIT again.
7041 */
7042 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7043 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7044 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7045 kvm_update_dr0123(vcpu);
7046 kvm_update_dr6(vcpu);
7047 kvm_update_dr7(vcpu);
7048 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7049 }
7050
24f1e32c
FW		 7051 /*
7052 * If the guest has used debug registers, at least dr7
7053 * will be disabled while returning to the host.
7054 * If we don't have active breakpoints in the host, we don't
7055 * care about the messed up debug address registers. But if
7056 * we have some of them active, restore the old state.
7057 */
59d8eb53 7058 if (hw_breakpoint_active())
24f1e32c 7059 hw_breakpoint_restore();
42dbaa5a 7060
4ba76538 7061 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7062
6b7e2d09 7063 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7064 smp_wmb();
a547c6db 7065
fc5b7f3b
DM		 7066 kvm_put_guest_xcr0(vcpu);
7067
a547c6db 7068 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7069
7070 ++vcpu->stat.exits;
7071
f2485b3e 7072 guest_exit_irqoff();
b6c7a5dc 7073
f2485b3e 7074 local_irq_enable();
b6c7a5dc
HB		 7075 preempt_enable();
7076
f656ce01 7077 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7078
b6c7a5dc
HB		 7079 /*
7080 * Profile KVM exit RIPs:
7081 */
7082 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7083 unsigned long rip = kvm_rip_read(vcpu);
7084 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7085 }
7086
cc578287
ZA		 7087 if (unlikely(vcpu->arch.tsc_always_catchup))
7088 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7089
5cfb1d5a
MT		 7090 if (vcpu->arch.apic_attention)
7091 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7092
618232e2 7093 vcpu->arch.gpa_available = false;
851ba692 7094 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7095 return r;
7096
7097cancel_injection:
7098 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7099 if (unlikely(vcpu->arch.apic_attention))
7100 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7101out:
7102 return r;
7103}
b6c7a5dc 7104
362c698f
PB		 7105static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7106{
bf9f6ac8
FW		 7107 if (!kvm_arch_vcpu_runnable(vcpu) &&
7108 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7109 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7110 kvm_vcpu_block(vcpu);
7111 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7112
7113 if (kvm_x86_ops->post_block)
7114 kvm_x86_ops->post_block(vcpu);
7115
9c8fd1ba
PB		 7116 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7117 return 1;
7118 }
362c698f
PB		 7119
7120 kvm_apic_accept_events(vcpu);
7121 switch(vcpu->arch.mp_state) {
7122 case KVM_MP_STATE_HALTED:
7123 vcpu->arch.pv.pv_unhalted = false;
7124 vcpu->arch.mp_state =
7125 KVM_MP_STATE_RUNNABLE;
7126 case KVM_MP_STATE_RUNNABLE:
7127 vcpu->arch.apf.halted = false;
7128 break;
7129 case KVM_MP_STATE_INIT_RECEIVED:
7130 break;
7131 default:
7132 return -EINTR;
7133 break;
7134 }
7135 return 1;
7136}
09cec754 7137
5d9bc648
PB		 7138static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7139{
0ad3bed6
PB		 7140 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7141 kvm_x86_ops->check_nested_events(vcpu, false);
7142
5d9bc648
PB		 7143 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7144 !vcpu->arch.apf.halted);
7145}
7146
362c698f 7147static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7148{
7149 int r;
f656ce01 7150 struct kvm *kvm = vcpu->kvm;
d7690175 7151
f656ce01 7152 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
f0ace387 7153 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7154
362c698f 7155 for (;;) {
58f800d5 7156 if (kvm_vcpu_running(vcpu)) {
851ba692 7157 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7158 } else {
362c698f 7159 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7160 }
7161
09cec754
GN		 7162 if (r <= 0)
7163 break;
7164
72875d8a 7165 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7166 if (kvm_cpu_has_pending_timer(vcpu))
7167 kvm_inject_pending_timer_irqs(vcpu);
7168
782d422b
MG		 7169 if (dm_request_for_irq_injection(vcpu) &&
7170 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7171 r = 0;
7172 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7173 ++vcpu->stat.request_irq_exits;
362c698f 7174 break;
09cec754 7175 }
af585b92
GN		 7176
7177 kvm_check_async_pf_completion(vcpu);
7178
09cec754
GN		 7179 if (signal_pending(current)) {
7180 r = -EINTR;
851ba692 7181 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7182 ++vcpu->stat.signal_exits;
362c698f 7183 break;
09cec754
GN		 7184 }
7185 if (need_resched()) {
f656ce01 7186 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7187 cond_resched();
f656ce01 7188 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7189 }
b6c7a5dc
HB		 7190 }
7191
f656ce01 7192 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7193
7194 return r;
7195}
7196
716d51ab
GN		 7197static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7198{
7199 int r;
7200 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7201 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7202 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7203 if (r != EMULATE_DONE)
7204 return 0;
7205 return 1;
7206}
7207
7208static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7209{
7210 BUG_ON(!vcpu->arch.pio.count);
7211
7212 return complete_emulated_io(vcpu);
7213}
7214
f78146b0
AK		 7215/*
7216 * Implements the following, as a state machine:
7217 *
7218 * read:
7219 * for each fragment
87da7e66
XG		 7220 * for each mmio piece in the fragment
7221 * write gpa, len
7222 * exit
7223 * copy data
f78146b0
AK		 7224 * execute insn
7225 *
7226 * write:
7227 * for each fragment
87da7e66
XG		 7228 * for each mmio piece in the fragment
7229 * write gpa, len
7230 * copy data
7231 * exit
f78146b0 7232 */
716d51ab 7233static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7234{
7235 struct kvm_run *run = vcpu->run;
f78146b0 7236 struct kvm_mmio_fragment *frag;
87da7e66 7237 unsigned len;
5287f194 7238
716d51ab 7239 BUG_ON(!vcpu->mmio_needed);
5287f194 7240
716d51ab 7241 /* Complete previous fragment */
87da7e66
XG		 7242 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7243 len = min(8u, frag->len);
716d51ab 7244 if (!vcpu->mmio_is_write)
87da7e66
XG		 7245 memcpy(frag->data, run->mmio.data, len);
7246
7247 if (frag->len <= 8) {
7248 /* Switch to the next fragment. */
7249 frag++;
7250 vcpu->mmio_cur_fragment++;
7251 } else {
7252 /* Go forward to the next mmio piece. */
7253 frag->data += len;
7254 frag->gpa += len;
7255 frag->len -= len;
7256 }
7257
a08d3b3b 7258 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7259 vcpu->mmio_needed = 0;
0912c977
PB		 7260
7261 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7262 if (vcpu->mmio_is_write)
716d51ab
GN		 7263 return 1;
7264 vcpu->mmio_read_completed = 1;
7265 return complete_emulated_io(vcpu);
7266 }
87da7e66 7267
716d51ab
GN		 7268 run->exit_reason = KVM_EXIT_MMIO;
7269 run->mmio.phys_addr = frag->gpa;
7270 if (vcpu->mmio_is_write)
87da7e66
XG		 7271 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7272 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7273 run->mmio.is_write = vcpu->mmio_is_write;
7274 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7275 return 0;
5287f194
AK		 7276}
7277
716d51ab 7278
b6c7a5dc
HB		 7279int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7280{
7281 int r;
b6c7a5dc 7282
20b7035c 7283 kvm_sigset_activate(vcpu);
ac9f6dc0 7284
5663d8f9
PX		 7285 kvm_load_guest_fpu(vcpu);
7286
a4535290 7287 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7288 if (kvm_run->immediate_exit) {
7289 r = -EINTR;
7290 goto out;
7291 }
b6c7a5dc 7292 kvm_vcpu_block(vcpu);
66450a21 7293 kvm_apic_accept_events(vcpu);
72875d8a 7294 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7295 r = -EAGAIN;
a0595000
JS		 7296 if (signal_pending(current)) {
7297 r = -EINTR;
7298 vcpu->run->exit_reason = KVM_EXIT_INTR;
7299 ++vcpu->stat.signal_exits;
7300 }
ac9f6dc0 7301 goto out;
b6c7a5dc
HB		 7302 }
7303
b6c7a5dc 7304 /* re-sync apic's tpr */
35754c98 7305 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7306 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7307 r = -EINVAL;
7308 goto out;
7309 }
7310 }
b6c7a5dc 7311
716d51ab
GN		 7312 if (unlikely(vcpu->arch.complete_userspace_io)) {
7313 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7314 vcpu->arch.complete_userspace_io = NULL;
7315 r = cui(vcpu);
7316 if (r <= 0)
5663d8f9 7317 goto out;
716d51ab
GN		 7318 } else
7319 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7320
460df4c1
PB		 7321 if (kvm_run->immediate_exit)
7322 r = -EINTR;
7323 else
7324 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7325
7326out:
5663d8f9 7327 kvm_put_guest_fpu(vcpu);
f1d86e46 7328 post_kvm_run_save(vcpu);
20b7035c 7329 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7330
b6c7a5dc
HB		 7331 return r;
7332}
7333
7334int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7335{
7ae441ea
GN		 7336 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7337 /*
7338 * We are here if userspace calls get_regs() in the middle of
7339 * instruction emulation. Registers state needs to be copied
4a969980 7340 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7341 * that usually, but some bad designed PV devices (vmware
7342 * backdoor interface) need this to work
7343 */
dd856efa 7344 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7345 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7346 }
5fdbf976
MT		 7347 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7348 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7349 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7350 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7351 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7352 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7353 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7354 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7355#ifdef CONFIG_X86_64
5fdbf976
MT		 7356 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7357 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7358 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7359 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7360 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7361 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7362 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7363 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7364#endif
7365
5fdbf976 7366 regs->rip = kvm_rip_read(vcpu);
91586a3b 7367 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7368
b6c7a5dc
HB		 7369 return 0;
7370}
7371
7372int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7373{
7ae441ea
GN		 7374 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7375 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7376
5fdbf976
MT		 7377 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7378 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7379 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7380 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7381 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7382 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7383 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7384 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7385#ifdef CONFIG_X86_64
5fdbf976
MT		 7386 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7387 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7388 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7389 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7390 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7391 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7392 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7393 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7394#endif
7395
5fdbf976 7396 kvm_rip_write(vcpu, regs->rip);
d73235d1 7397 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7398
b4f14abd
JK		 7399 vcpu->arch.exception.pending = false;
7400
3842d135
AK		 7401 kvm_make_request(KVM_REQ_EVENT, vcpu);
7402
b6c7a5dc
HB		 7403 return 0;
7404}
7405
b6c7a5dc
HB		 7406void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7407{
7408 struct kvm_segment cs;
7409
3e6e0aab 7410 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7411 *db = cs.db;
7412 *l = cs.l;
7413}
7414EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7415
7416int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7417 struct kvm_sregs *sregs)
7418{
89a27f4d 7419 struct desc_ptr dt;
b6c7a5dc 7420
3e6e0aab
GT		 7421 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7422 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7423 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7424 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7425 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7426 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7427
3e6e0aab
GT		 7428 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7429 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7430
7431 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7432 sregs->idt.limit = dt.size;
7433 sregs->idt.base = dt.address;
b6c7a5dc 7434 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7435 sregs->gdt.limit = dt.size;
7436 sregs->gdt.base = dt.address;
b6c7a5dc 7437
4d4ec087 7438 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7439 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7440 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7441 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7442 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7443 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7444 sregs->apic_base = kvm_get_apic_base(vcpu);
7445
923c61bb 7446 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7447
36752c9b 7448 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7449 set_bit(vcpu->arch.interrupt.nr,
7450 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7451
b6c7a5dc
HB		 7452 return 0;
7453}
7454
62d9f0db
MT		 7455int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7456 struct kvm_mp_state *mp_state)
7457{
66450a21 7458 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7459 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7460 vcpu->arch.pv.pv_unhalted)
7461 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7462 else
7463 mp_state->mp_state = vcpu->arch.mp_state;
7464
62d9f0db
MT		 7465 return 0;
7466}
7467
7468int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7469 struct kvm_mp_state *mp_state)
7470{
bce87cce 7471 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7472 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7473 return -EINVAL;
7474
28bf2888
DH		 7475 /* INITs are latched while in SMM */
7476 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7477 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7478 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7479 return -EINVAL;
7480
66450a21
JK		 7481 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7482 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7483 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7484 } else
7485 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7486 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7487 return 0;
7488}
7489
7f3d35fd
KW		 7490int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7491 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7492{
9d74191a 7493 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7494 int ret;
e01c2426 7495
8ec4722d 7496 init_emulate_ctxt(vcpu);
c697518a 7497
7f3d35fd 7498 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7499 has_error_code, error_code);
c697518a 7500
c697518a 7501 if (ret)
19d04437 7502 return EMULATE_FAIL;
37817f29 7503
9d74191a
TY		 7504 kvm_rip_write(vcpu, ctxt->eip);
7505 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7506 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7507 return EMULATE_DONE;
37817f29
IE		 7508}
7509EXPORT_SYMBOL_GPL(kvm_task_switch);
7510
f2981033
LT		 7511int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7512{
37b95951 7513 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7514 /*
7515 * When EFER.LME and CR0.PG are set, the processor is in
7516 * 64-bit mode (though maybe in a 32-bit code segment).
7517 * CR4.PAE and EFER.LMA must be set.
7518 */
37b95951 7519 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7520 || !(sregs->efer & EFER_LMA))
7521 return -EINVAL;
7522 } else {
7523 /*
7524 * Not in 64-bit mode: EFER.LMA is clear and the code
7525 * segment cannot be 64-bit.
7526 */
7527 if (sregs->efer & EFER_LMA || sregs->cs.l)
7528 return -EINVAL;
7529 }
7530
7531 return 0;
7532}
7533
b6c7a5dc
HB		 7534int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7535 struct kvm_sregs *sregs)
7536{
58cb628d 7537 struct msr_data apic_base_msr;
b6c7a5dc 7538 int mmu_reset_needed = 0;
63f42e02 7539 int pending_vec, max_bits, idx;
89a27f4d 7540 struct desc_ptr dt;
b6c7a5dc 7541
d6321d49
RK		 7542 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7543 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7544 return -EINVAL;
7545
f2981033
LT		 7546 if (kvm_valid_sregs(vcpu, sregs))
7547 return -EINVAL;
7548
d3802286
JM		 7549 apic_base_msr.data = sregs->apic_base;
7550 apic_base_msr.host_initiated = true;
7551 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7552 return -EINVAL;
7553
89a27f4d
GN		 7554 dt.size = sregs->idt.limit;
7555 dt.address = sregs->idt.base;
b6c7a5dc 7556 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7557 dt.size = sregs->gdt.limit;
7558 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7559 kvm_x86_ops->set_gdt(vcpu, &dt);
7560
ad312c7c 7561 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7562 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7563 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7564 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7565
2d3ad1f4 7566 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7567
f6801dff 7568 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7569 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7570
4d4ec087 7571 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7572 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7573 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7574
fc78f519 7575 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7576 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7577 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7578 kvm_update_cpuid(vcpu);
63f42e02
XG		 7579
7580 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7581 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7582 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7583 mmu_reset_needed = 1;
7584 }
63f42e02 7585 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7586
7587 if (mmu_reset_needed)
7588 kvm_mmu_reset_context(vcpu);
7589
a50abc3b 7590 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7591 pending_vec = find_first_bit(
7592 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7593 if (pending_vec < max_bits) {
66fd3f7f 7594 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7595 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7596 }
7597
3e6e0aab
GT		 7598 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7599 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7600 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7601 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7602 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7603 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7604
3e6e0aab
GT		 7605 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7606 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7607
5f0269f5
ME		 7608 update_cr8_intercept(vcpu);
7609
9c3e4aab 7610 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7611 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7612 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7613 !is_protmode(vcpu))
9c3e4aab
MT		 7614 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7615
3842d135
AK		 7616 kvm_make_request(KVM_REQ_EVENT, vcpu);
7617
b6c7a5dc
HB		 7618 return 0;
7619}
7620
d0bfb940
JK		 7621int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7622 struct kvm_guest_debug *dbg)
b6c7a5dc 7623{
355be0b9 7624 unsigned long rflags;
ae675ef0 7625 int i, r;
b6c7a5dc 7626
4f926bf2
JK		 7627 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7628 r = -EBUSY;
7629 if (vcpu->arch.exception.pending)
2122ff5e 7630 goto out;
4f926bf2
JK		 7631 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7632 kvm_queue_exception(vcpu, DB_VECTOR);
7633 else
7634 kvm_queue_exception(vcpu, BP_VECTOR);
7635 }
7636
91586a3b
JK		 7637 /*
7638 * Read rflags as long as potentially injected trace flags are still
7639 * filtered out.
7640 */
7641 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7642
7643 vcpu->guest_debug = dbg->control;
7644 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7645 vcpu->guest_debug = 0;
7646
7647 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7648 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7649 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7650 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7651 } else {
7652 for (i = 0; i < KVM_NR_DB_REGS; i++)
7653 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7654 }
c8639010 7655 kvm_update_dr7(vcpu);
ae675ef0 7656
f92653ee
JK		 7657 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7658 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7659 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7660
91586a3b
JK		 7661 /*
7662 * Trigger an rflags update that will inject or remove the trace
7663 * flags.
7664 */
7665 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7666
a96036b8 7667 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7668
4f926bf2 7669 r = 0;
d0bfb940 7670
2122ff5e 7671out:
b6c7a5dc
HB		 7672
7673 return r;
7674}
7675
8b006791
ZX		 7676/*
7677 * Translate a guest virtual address to a guest physical address.
7678 */
7679int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7680 struct kvm_translation *tr)
7681{
7682 unsigned long vaddr = tr->linear_address;
7683 gpa_t gpa;
f656ce01 7684 int idx;
8b006791 7685
f656ce01 7686 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7687 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7688 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7689 tr->physical_address = gpa;
7690 tr->valid = gpa != UNMAPPED_GVA;
7691 tr->writeable = 1;
7692 tr->usermode = 0;
8b006791
ZX		 7693
7694 return 0;
7695}
7696
d0752060
HB		 7697int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7698{
c47ada30 7699 struct fxregs_state *fxsave =
7366ed77 7700 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7701
d0752060
HB		 7702 memcpy(fpu->fpr, fxsave->st_space, 128);
7703 fpu->fcw = fxsave->cwd;
7704 fpu->fsw = fxsave->swd;
7705 fpu->ftwx = fxsave->twd;
7706 fpu->last_opcode = fxsave->fop;
7707 fpu->last_ip = fxsave->rip;
7708 fpu->last_dp = fxsave->rdp;
7709 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7710
d0752060
HB		 7711 return 0;
7712}
7713
7714int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7715{
c47ada30 7716 struct fxregs_state *fxsave =
7366ed77 7717 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7718
d0752060
HB		 7719 memcpy(fxsave->st_space, fpu->fpr, 128);
7720 fxsave->cwd = fpu->fcw;
7721 fxsave->swd = fpu->fsw;
7722 fxsave->twd = fpu->ftwx;
7723 fxsave->fop = fpu->last_opcode;
7724 fxsave->rip = fpu->last_ip;
7725 fxsave->rdp = fpu->last_dp;
7726 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7727
d0752060
HB		 7728 return 0;
7729}
7730
0ee6a517 7731static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7732{
bf935b0b 7733 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7734 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7735 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7736 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7737
2acf923e
DC		 7738 /*
7739 * Ensure guest xcr0 is valid for loading
7740 */
d91cab78 7741 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7742
ad312c7c 7743 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7744}
d0752060 7745
f775b13e 7746/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7747void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7748{
f775b13e
RR		 7749 preempt_disable();
7750 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7751 /* PKRU is separately restored in kvm_x86_ops->run. */
7752 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7753 ~XFEATURE_MASK_PKRU);
f775b13e 7754 preempt_enable();
0c04851c 7755 trace_kvm_fpu(1);
d0752060 7756}
d0752060 7757
f775b13e 7758/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 7759void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7760{
f775b13e 7761 preempt_disable();
4f836347 7762 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 7763 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7764 preempt_enable();
f096ed85 7765 ++vcpu->stat.fpu_reload;
0c04851c 7766 trace_kvm_fpu(0);
d0752060 7767}
e9b11c17
ZX		 7768
7769void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7770{
bd768e14
IY		 7771 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7772
12f9a48f 7773 kvmclock_reset(vcpu);
7f1ea208 7774
e9b11c17 7775 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7776 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7777}
7778
7779struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7780 unsigned int id)
7781{
c447e76b
LL		 7782 struct kvm_vcpu *vcpu;
7783
6755bae8
ZA		 7784 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7785 printk_once(KERN_WARNING
7786 "kvm: SMP vm created on host with unstable TSC; "
7787 "guest TSC will not be reliable\n");
c447e76b
LL		 7788
7789 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7790
c447e76b 7791 return vcpu;
26e5215f 7792}
e9b11c17 7793
26e5215f
AK		 7794int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7795{
7796 int r;
e9b11c17 7797
19efffa2 7798 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7799 r = vcpu_load(vcpu);
7800 if (r)
7801 return r;
d28bc9dd 7802 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7803 kvm_mmu_setup(vcpu);
e9b11c17 7804 vcpu_put(vcpu);
26e5215f 7805 return r;
e9b11c17
ZX		 7806}
7807
31928aa5 7808void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7809{
8fe8ab46 7810 struct msr_data msr;
332967a3 7811 struct kvm *kvm = vcpu->kvm;
42897d86 7812
d3457c87
RK		 7813 kvm_hv_vcpu_postcreate(vcpu);
7814
31928aa5
DD		 7815 if (vcpu_load(vcpu))
7816 return;
8fe8ab46
WA		 7817 msr.data = 0x0;
7818 msr.index = MSR_IA32_TSC;
7819 msr.host_initiated = true;
7820 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7821 vcpu_put(vcpu);
7822
630994b3
MT		 7823 if (!kvmclock_periodic_sync)
7824 return;
7825
332967a3
AJ		 7826 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7827 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7828}
7829
d40ccc62 7830void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7831{
9fc77441 7832 int r;
344d9588
GN		 7833 vcpu->arch.apf.msr_val = 0;
7834
9fc77441
MT		 7835 r = vcpu_load(vcpu);
7836 BUG_ON(r);
e9b11c17
ZX		 7837 kvm_mmu_unload(vcpu);
7838 vcpu_put(vcpu);
7839
7840 kvm_x86_ops->vcpu_free(vcpu);
7841}
7842
d28bc9dd 7843void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7844{
a04c389c
RK		 7845 kvm_lapic_reset(vcpu, init_event);
7846
e69fab5d
PB		 7847 vcpu->arch.hflags = 0;
7848
c43203ca 7849 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7850 atomic_set(&vcpu->arch.nmi_queued, 0);
7851 vcpu->arch.nmi_pending = 0;
448fa4a9 7852 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7853 kvm_clear_interrupt_queue(vcpu);
7854 kvm_clear_exception_queue(vcpu);
664f8e26 7855 vcpu->arch.exception.pending = false;
448fa4a9 7856
42dbaa5a 7857 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7858 kvm_update_dr0123(vcpu);
6f43ed01 7859 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7860 kvm_update_dr6(vcpu);
42dbaa5a 7861 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7862 kvm_update_dr7(vcpu);
42dbaa5a 7863
1119022c
NA		 7864 vcpu->arch.cr2 = 0;
7865
3842d135 7866 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7867 vcpu->arch.apf.msr_val = 0;
c9aaa895 7868 vcpu->arch.st.msr_val = 0;
3842d135 7869
12f9a48f
GC		 7870 kvmclock_reset(vcpu);
7871
af585b92
GN		 7872 kvm_clear_async_pf_completion_queue(vcpu);
7873 kvm_async_pf_hash_reset(vcpu);
7874 vcpu->arch.apf.halted = false;
3842d135 7875
a554d207
WL		 7876 if (kvm_mpx_supported()) {
7877 void *mpx_state_buffer;
7878
7879 /*
7880 * To avoid have the INIT path from kvm_apic_has_events() that be
7881 * called with loaded FPU and does not let userspace fix the state.
7882 */
f775b13e
RR		 7883 if (init_event)
7884 kvm_put_guest_fpu(vcpu);
a554d207
WL		 7885 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7886 XFEATURE_MASK_BNDREGS);
7887 if (mpx_state_buffer)
7888 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7889 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7890 XFEATURE_MASK_BNDCSR);
7891 if (mpx_state_buffer)
7892 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 7893 if (init_event)
7894 kvm_load_guest_fpu(vcpu);
a554d207
WL		 7895 }
7896
64d60670 7897 if (!init_event) {
d28bc9dd 7898 kvm_pmu_reset(vcpu);
64d60670 7899 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7900
7901 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7902 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7903
7904 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7905 }
f5132b01 7906
66f7b72e
JS		 7907 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7908 vcpu->arch.regs_avail = ~0;
7909 vcpu->arch.regs_dirty = ~0;
7910
a554d207
WL		 7911 vcpu->arch.ia32_xss = 0;
7912
d28bc9dd 7913 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7914}
7915
2b4a273b 7916void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7917{
7918 struct kvm_segment cs;
7919
7920 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7921 cs.selector = vector << 8;
7922 cs.base = vector << 12;
7923 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7924 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7925}
7926
13a34e06 7927int kvm_arch_hardware_enable(void)
e9b11c17 7928{
ca84d1a2
ZA		 7929 struct kvm *kvm;
7930 struct kvm_vcpu *vcpu;
7931 int i;
0dd6a6ed
ZA		 7932 int ret;
7933 u64 local_tsc;
7934 u64 max_tsc = 0;
7935 bool stable, backwards_tsc = false;
18863bdd
AK		 7936
7937 kvm_shared_msr_cpu_online();
13a34e06 7938 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7939 if (ret != 0)
7940 return ret;
7941
4ea1636b 7942 local_tsc = rdtsc();
0dd6a6ed
ZA		 7943 stable = !check_tsc_unstable();
7944 list_for_each_entry(kvm, &vm_list, vm_list) {
7945 kvm_for_each_vcpu(i, vcpu, kvm) {
7946 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7947 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7948 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7949 backwards_tsc = true;
7950 if (vcpu->arch.last_host_tsc > max_tsc)
7951 max_tsc = vcpu->arch.last_host_tsc;
7952 }
7953 }
7954 }
7955
7956 /*
7957 * Sometimes, even reliable TSCs go backwards. This happens on
7958 * platforms that reset TSC during suspend or hibernate actions, but
7959 * maintain synchronization. We must compensate. Fortunately, we can
7960 * detect that condition here, which happens early in CPU bringup,
7961 * before any KVM threads can be running. Unfortunately, we can't
7962 * bring the TSCs fully up to date with real time, as we aren't yet far
7963 * enough into CPU bringup that we know how much real time has actually
108b249c 7964 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7965 * variables that haven't been updated yet.
7966 *
7967 * So we simply find the maximum observed TSC above, then record the
7968 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7969 * the adjustment will be applied. Note that we accumulate
7970 * adjustments, in case multiple suspend cycles happen before some VCPU
7971 * gets a chance to run again. In the event that no KVM threads get a
7972 * chance to run, we will miss the entire elapsed period, as we'll have
7973 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7974 * loose cycle time. This isn't too big a deal, since the loss will be
7975 * uniform across all VCPUs (not to mention the scenario is extremely
7976 * unlikely). It is possible that a second hibernate recovery happens
7977 * much faster than a first, causing the observed TSC here to be
7978 * smaller; this would require additional padding adjustment, which is
7979 * why we set last_host_tsc to the local tsc observed here.
7980 *
7981 * N.B. - this code below runs only on platforms with reliable TSC,
7982 * as that is the only way backwards_tsc is set above. Also note
7983 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7984 * have the same delta_cyc adjustment applied if backwards_tsc
7985 * is detected. Note further, this adjustment is only done once,
7986 * as we reset last_host_tsc on all VCPUs to stop this from being
7987 * called multiple times (one for each physical CPU bringup).
7988 *
4a969980 7989 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7990 * will be compensated by the logic in vcpu_load, which sets the TSC to
7991 * catchup mode. This will catchup all VCPUs to real time, but cannot
7992 * guarantee that they stay in perfect synchronization.
7993 */
7994 if (backwards_tsc) {
7995 u64 delta_cyc = max_tsc - local_tsc;
7996 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7997 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7998 kvm_for_each_vcpu(i, vcpu, kvm) {
7999 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8000 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8001 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8002 }
8003
8004 /*
8005 * We have to disable TSC offset matching.. if you were
8006 * booting a VM while issuing an S4 host suspend....
8007 * you may have some problem. Solving this issue is
8008 * left as an exercise to the reader.
8009 */
8010 kvm->arch.last_tsc_nsec = 0;
8011 kvm->arch.last_tsc_write = 0;
8012 }
8013
8014 }
8015 return 0;
e9b11c17
ZX		 8016}
8017
13a34e06 8018void kvm_arch_hardware_disable(void)
e9b11c17 8019{
13a34e06
RK		 8020 kvm_x86_ops->hardware_disable();
8021 drop_user_return_notifiers();
e9b11c17
ZX		 8022}
8023
8024int kvm_arch_hardware_setup(void)
8025{
9e9c3fe4
NA		 8026 int r;
8027
8028 r = kvm_x86_ops->hardware_setup();
8029 if (r != 0)
8030 return r;
8031
35181e86
HZ		 8032 if (kvm_has_tsc_control) {
8033 /*
8034 * Make sure the user can only configure tsc_khz values that
8035 * fit into a signed integer.
8036 * A min value is not calculated needed because it will always
8037 * be 1 on all machines.
8038 */
8039 u64 max = min(0x7fffffffULL,
8040 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8041 kvm_max_guest_tsc_khz = max;
8042
ad721883 8043 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8044 }
ad721883 8045
9e9c3fe4
NA		 8046 kvm_init_msr_list();
8047 return 0;
e9b11c17
ZX		 8048}
8049
8050void kvm_arch_hardware_unsetup(void)
8051{
8052 kvm_x86_ops->hardware_unsetup();
8053}
8054
8055void kvm_arch_check_processor_compat(void *rtn)
8056{
8057 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8058}
8059
8060bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8061{
8062 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8063}
8064EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8065
8066bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8067{
8068 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8069}
8070
54e9818f 8071struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8072EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8073
e9b11c17
ZX		 8074int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8075{
8076 struct page *page;
e9b11c17
ZX		 8077 int r;
8078
b2a05fef 8079 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8080 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8081 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8082 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8083 else
a4535290 8084 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8085
8086 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8087 if (!page) {
8088 r = -ENOMEM;
8089 goto fail;
8090 }
ad312c7c 8091 vcpu->arch.pio_data = page_address(page);
e9b11c17 8092
cc578287 8093 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8094
e9b11c17
ZX		 8095 r = kvm_mmu_create(vcpu);
8096 if (r < 0)
8097 goto fail_free_pio_data;
8098
26de7988 8099 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8100 r = kvm_create_lapic(vcpu);
8101 if (r < 0)
8102 goto fail_mmu_destroy;
54e9818f
GN		 8103 } else
8104 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8105
890ca9ae
HY		 8106 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8107 GFP_KERNEL);
8108 if (!vcpu->arch.mce_banks) {
8109 r = -ENOMEM;
443c39bc 8110 goto fail_free_lapic;
890ca9ae
HY		 8111 }
8112 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8113
f1797359
WY		 8114 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8115 r = -ENOMEM;
f5f48ee1 8116 goto fail_free_mce_banks;
f1797359 8117 }
f5f48ee1 8118
0ee6a517 8119 fx_init(vcpu);
66f7b72e 8120
4344ee98 8121 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8122
5a4f55cd
EK		 8123 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8124
74545705
RK		 8125 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8126
af585b92 8127 kvm_async_pf_hash_reset(vcpu);
f5132b01 8128 kvm_pmu_init(vcpu);
af585b92 8129
1c1a9ce9 8130 vcpu->arch.pending_external_vector = -1;
de63ad4c 8131 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8132
5c919412
AS		 8133 kvm_hv_vcpu_init(vcpu);
8134
e9b11c17 8135 return 0;
0ee6a517 8136
f5f48ee1
SY		 8137fail_free_mce_banks:
8138 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8139fail_free_lapic:
8140 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8141fail_mmu_destroy:
8142 kvm_mmu_destroy(vcpu);
8143fail_free_pio_data:
ad312c7c 8144 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8145fail:
8146 return r;
8147}
8148
8149void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8150{
f656ce01
MT		 8151 int idx;
8152
1f4b34f8 8153 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8154 kvm_pmu_destroy(vcpu);
36cb93fd 8155 kfree(vcpu->arch.mce_banks);
e9b11c17 8156 kvm_free_lapic(vcpu);
f656ce01 8157 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8158 kvm_mmu_destroy(vcpu);
f656ce01 8159 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8160 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8161 if (!lapic_in_kernel(vcpu))
54e9818f 8162 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8163}
d19a9cd2 8164
e790d9ef
RK		 8165void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8166{
f0ace387 8167 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8168 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8169}
8170
e08b9637 8171int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8172{
e08b9637
CO		 8173 if (type)
8174 return -EINVAL;
8175
6ef768fa 8176 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8177 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8178 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8179 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8180 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8181
5550af4d
SY		 8182 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8183 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8184 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8185 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8186 &kvm->arch.irq_sources_bitmap);
5550af4d 8187
038f8c11 8188 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8189 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8190 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8191 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8192
108b249c 8193 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8194 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8195
7e44e449 8196 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8197 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8198
0eb05bf2 8199 kvm_page_track_init(kvm);
13d268ca 8200 kvm_mmu_init_vm(kvm);
0eb05bf2 8201
03543133
SS		 8202 if (kvm_x86_ops->vm_init)
8203 return kvm_x86_ops->vm_init(kvm);
8204
d89f5eff 8205 return 0;
d19a9cd2
ZX		 8206}
8207
8208static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8209{
9fc77441
MT		 8210 int r;
8211 r = vcpu_load(vcpu);
8212 BUG_ON(r);
d19a9cd2
ZX		 8213 kvm_mmu_unload(vcpu);
8214 vcpu_put(vcpu);
8215}
8216
8217static void kvm_free_vcpus(struct kvm *kvm)
8218{
8219 unsigned int i;
988a2cae 8220 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8221
8222 /*
8223 * Unpin any mmu pages first.
8224 */
af585b92
GN		 8225 kvm_for_each_vcpu(i, vcpu, kvm) {
8226 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8227 kvm_unload_vcpu_mmu(vcpu);
af585b92 8228 }
988a2cae
GN		 8229 kvm_for_each_vcpu(i, vcpu, kvm)
8230 kvm_arch_vcpu_free(vcpu);
8231
8232 mutex_lock(&kvm->lock);
8233 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8234 kvm->vcpus[i] = NULL;
d19a9cd2 8235
988a2cae
GN		 8236 atomic_set(&kvm->online_vcpus, 0);
8237 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8238}
8239
ad8ba2cd
SY		 8240void kvm_arch_sync_events(struct kvm *kvm)
8241{
332967a3 8242 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8243 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8244 kvm_free_pit(kvm);
ad8ba2cd
SY		 8245}
8246
1d8007bd 8247int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8248{
8249 int i, r;
25188b99 8250 unsigned long hva;
f0d648bd
PB		 8251 struct kvm_memslots *slots = kvm_memslots(kvm);
8252 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8253
8254 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8255 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8256 return -EINVAL;
9da0e4d5 8257
f0d648bd
PB		 8258 slot = id_to_memslot(slots, id);
8259 if (size) {
b21629da 8260 if (slot->npages)
f0d648bd
PB		 8261 return -EEXIST;
8262
8263 /*
8264 * MAP_SHARED to prevent internal slot pages from being moved
8265 * by fork()/COW.
8266 */
8267 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8268 MAP_SHARED | MAP_ANONYMOUS, 0);
8269 if (IS_ERR((void *)hva))
8270 return PTR_ERR((void *)hva);
8271 } else {
8272 if (!slot->npages)
8273 return 0;
8274
8275 hva = 0;
8276 }
8277
8278 old = *slot;
9da0e4d5 8279 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8280 struct kvm_userspace_memory_region m;
9da0e4d5 8281
1d8007bd
PB		 8282 m.slot = id | (i << 16);
8283 m.flags = 0;
8284 m.guest_phys_addr = gpa;
f0d648bd 8285 m.userspace_addr = hva;
1d8007bd 8286 m.memory_size = size;
9da0e4d5
PB		 8287 r = __kvm_set_memory_region(kvm, &m);
8288 if (r < 0)
8289 return r;
8290 }
8291
55a4a47b
EB		 8292 if (!size)
8293 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8294
9da0e4d5
PB		 8295 return 0;
8296}
8297EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8298
1d8007bd 8299int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8300{
8301 int r;
8302
8303 mutex_lock(&kvm->slots_lock);
1d8007bd 8304 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8305 mutex_unlock(&kvm->slots_lock);
8306
8307 return r;
8308}
8309EXPORT_SYMBOL_GPL(x86_set_memory_region);
8310
d19a9cd2
ZX		 8311void kvm_arch_destroy_vm(struct kvm *kvm)
8312{
27469d29
AH		 8313 if (current->mm == kvm->mm) {
8314 /*
8315 * Free memory regions allocated on behalf of userspace,
8316 * unless the the memory map has changed due to process exit
8317 * or fd copying.
8318 */
1d8007bd
PB		 8319 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8320 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8321 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8322 }
03543133
SS		 8323 if (kvm_x86_ops->vm_destroy)
8324 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8325 kvm_pic_destroy(kvm);
8326 kvm_ioapic_destroy(kvm);
d19a9cd2 8327 kvm_free_vcpus(kvm);
af1bae54 8328 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8329 kvm_mmu_uninit_vm(kvm);
2beb6dad 8330 kvm_page_track_cleanup(kvm);
d19a9cd2 8331}
0de10343 8332
5587027c 8333void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8334 struct kvm_memory_slot *dont)
8335{
8336 int i;
8337
d89cc617
TY		 8338 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8339 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8340 kvfree(free->arch.rmap[i]);
d89cc617 8341 free->arch.rmap[i] = NULL;
77d11309 8342 }
d89cc617
TY		 8343 if (i == 0)
8344 continue;
8345
8346 if (!dont || free->arch.lpage_info[i - 1] !=
8347 dont->arch.lpage_info[i - 1]) {
548ef284 8348 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8349 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8350 }
8351 }
21ebbeda
XG		 8352
8353 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8354}
8355
5587027c
AK		 8356int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8357 unsigned long npages)
db3fe4eb
TY		 8358{
8359 int i;
8360
d89cc617 8361 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8362 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8363 unsigned long ugfn;
8364 int lpages;
d89cc617 8365 int level = i + 1;
db3fe4eb
TY		 8366
8367 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8368 slot->base_gfn, level) + 1;
8369
d89cc617 8370 slot->arch.rmap[i] =
a7c3e901 8371 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8372 if (!slot->arch.rmap[i])
77d11309 8373 goto out_free;
d89cc617
TY		 8374 if (i == 0)
8375 continue;
77d11309 8376
a7c3e901 8377 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8378 if (!linfo)
db3fe4eb
TY		 8379 goto out_free;
8380
92f94f1e
XG		 8381 slot->arch.lpage_info[i - 1] = linfo;
8382
db3fe4eb 8383 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8384 linfo[0].disallow_lpage = 1;
db3fe4eb 8385 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8386 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8387 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8388 /*
8389 * If the gfn and userspace address are not aligned wrt each
8390 * other, or if explicitly asked to, disable large page
8391 * support for this slot
8392 */
8393 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8394 !kvm_largepages_enabled()) {
8395 unsigned long j;
8396
8397 for (j = 0; j < lpages; ++j)
92f94f1e 8398 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8399 }
8400 }
8401
21ebbeda
XG		 8402 if (kvm_page_track_create_memslot(slot, npages))
8403 goto out_free;
8404
db3fe4eb
TY		 8405 return 0;
8406
8407out_free:
d89cc617 8408 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8409 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8410 slot->arch.rmap[i] = NULL;
8411 if (i == 0)
8412 continue;
8413
548ef284 8414 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8415 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8416 }
8417 return -ENOMEM;
8418}
8419
15f46015 8420void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8421{
e6dff7d1
TY		 8422 /*
8423 * memslots->generation has been incremented.
8424 * mmio generation may have reached its maximum value.
8425 */
54bf36aa 8426 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8427}
8428
f7784b8e
MT		 8429int kvm_arch_prepare_memory_region(struct kvm *kvm,
8430 struct kvm_memory_slot *memslot,
09170a49 8431 const struct kvm_userspace_memory_region *mem,
7b6195a9 8432 enum kvm_mr_change change)
0de10343 8433{
f7784b8e
MT		 8434 return 0;
8435}
8436
88178fd4
KH		 8437static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8438 struct kvm_memory_slot *new)
8439{
8440 /* Still write protect RO slot */
8441 if (new->flags & KVM_MEM_READONLY) {
8442 kvm_mmu_slot_remove_write_access(kvm, new);
8443 return;
8444 }
8445
8446 /*
8447 * Call kvm_x86_ops dirty logging hooks when they are valid.
8448 *
8449 * kvm_x86_ops->slot_disable_log_dirty is called when:
8450 *
8451 * - KVM_MR_CREATE with dirty logging is disabled
8452 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8453 *
8454 * The reason is, in case of PML, we need to set D-bit for any slots
8455 * with dirty logging disabled in order to eliminate unnecessary GPA
8456 * logging in PML buffer (and potential PML buffer full VMEXT). This
8457 * guarantees leaving PML enabled during guest's lifetime won't have
8458 * any additonal overhead from PML when guest is running with dirty
8459 * logging disabled for memory slots.
8460 *
8461 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8462 * to dirty logging mode.
8463 *
8464 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8465 *
8466 * In case of write protect:
8467 *
8468 * Write protect all pages for dirty logging.
8469 *
8470 * All the sptes including the large sptes which point to this
8471 * slot are set to readonly. We can not create any new large
8472 * spte on this slot until the end of the logging.
8473 *
8474 * See the comments in fast_page_fault().
8475 */
8476 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8477 if (kvm_x86_ops->slot_enable_log_dirty)
8478 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8479 else
8480 kvm_mmu_slot_remove_write_access(kvm, new);
8481 } else {
8482 if (kvm_x86_ops->slot_disable_log_dirty)
8483 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8484 }
8485}
8486
f7784b8e 8487void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8488 const struct kvm_userspace_memory_region *mem,
8482644a 8489 const struct kvm_memory_slot *old,
f36f3f28 8490 const struct kvm_memory_slot *new,
8482644a 8491 enum kvm_mr_change change)
f7784b8e 8492{
8482644a 8493 int nr_mmu_pages = 0;
f7784b8e 8494
48c0e4e9
XG		 8495 if (!kvm->arch.n_requested_mmu_pages)
8496 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8497
48c0e4e9 8498 if (nr_mmu_pages)
0de10343 8499 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8500
3ea3b7fa
WL		 8501 /*
8502 * Dirty logging tracks sptes in 4k granularity, meaning that large
8503 * sptes have to be split. If live migration is successful, the guest
8504 * in the source machine will be destroyed and large sptes will be
8505 * created in the destination. However, if the guest continues to run
8506 * in the source machine (for example if live migration fails), small
8507 * sptes will remain around and cause bad performance.
8508 *
8509 * Scan sptes if dirty logging has been stopped, dropping those
8510 * which can be collapsed into a single large-page spte. Later
8511 * page faults will create the large-page sptes.
8512 */
8513 if ((change != KVM_MR_DELETE) &&
8514 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8515 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8516 kvm_mmu_zap_collapsible_sptes(kvm, new);
8517
c972f3b1 8518 /*
88178fd4 8519 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8520 *
88178fd4
KH		 8521 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8522 * been zapped so no dirty logging staff is needed for old slot. For
8523 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8524 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8525 *
8526 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8527 */
88178fd4 8528 if (change != KVM_MR_DELETE)
f36f3f28 8529 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8530}
1d737c8a 8531
2df72e9b 8532void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8533{
6ca18b69 8534 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8535}
8536
2df72e9b
MT		 8537void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8538 struct kvm_memory_slot *slot)
8539{
ae7cd873 8540 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8541}
8542
5d9bc648
PB		 8543static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8544{
8545 if (!list_empty_careful(&vcpu->async_pf.done))
8546 return true;
8547
8548 if (kvm_apic_has_events(vcpu))
8549 return true;
8550
8551 if (vcpu->arch.pv.pv_unhalted)
8552 return true;
8553
a5f01f8e
WL		 8554 if (vcpu->arch.exception.pending)
8555 return true;
8556
47a66eed
Z		 8557 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8558 (vcpu->arch.nmi_pending &&
8559 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8560 return true;
8561
47a66eed
Z		 8562 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8563 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8564 return true;
8565
5d9bc648
PB		 8566 if (kvm_arch_interrupt_allowed(vcpu) &&
8567 kvm_cpu_has_interrupt(vcpu))
8568 return true;
8569
1f4b34f8
AS		 8570 if (kvm_hv_has_stimer_pending(vcpu))
8571 return true;
8572
5d9bc648
PB		 8573 return false;
8574}
8575
1d737c8a
ZX		 8576int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8577{
5d9bc648 8578 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8579}
5736199a 8580
199b5763
LM		 8581bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8582{
de63ad4c 8583 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8584}
8585
b6d33834 8586int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8587{
b6d33834 8588 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8589}
78646121
GN		 8590
8591int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8592{
8593 return kvm_x86_ops->interrupt_allowed(vcpu);
8594}
229456fc 8595
82b32774 8596unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8597{
82b32774
NA		 8598 if (is_64_bit_mode(vcpu))
8599 return kvm_rip_read(vcpu);
8600 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8601 kvm_rip_read(vcpu));
8602}
8603EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8604
82b32774
NA		 8605bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8606{
8607 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8608}
8609EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8610
94fe45da
JK		 8611unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8612{
8613 unsigned long rflags;
8614
8615 rflags = kvm_x86_ops->get_rflags(vcpu);
8616 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8617 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8618 return rflags;
8619}
8620EXPORT_SYMBOL_GPL(kvm_get_rflags);
8621
6addfc42 8622static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8623{
8624 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8625 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8626 rflags |= X86_EFLAGS_TF;
94fe45da 8627 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8628}
8629
8630void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8631{
8632 __kvm_set_rflags(vcpu, rflags);
3842d135 8633 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8634}
8635EXPORT_SYMBOL_GPL(kvm_set_rflags);
8636
56028d08
GN		 8637void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8638{
8639 int r;
8640
fb67e14f 8641 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8642 work->wakeup_all)
56028d08
GN		 8643 return;
8644
8645 r = kvm_mmu_reload(vcpu);
8646 if (unlikely(r))
8647 return;
8648
fb67e14f
XG		 8649 if (!vcpu->arch.mmu.direct_map &&
8650 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8651 return;
8652
56028d08
GN		 8653 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8654}
8655
af585b92
GN		 8656static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8657{
8658 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8659}
8660
8661static inline u32 kvm_async_pf_next_probe(u32 key)
8662{
8663 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8664}
8665
8666static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8667{
8668 u32 key = kvm_async_pf_hash_fn(gfn);
8669
8670 while (vcpu->arch.apf.gfns[key] != ~0)
8671 key = kvm_async_pf_next_probe(key);
8672
8673 vcpu->arch.apf.gfns[key] = gfn;
8674}
8675
8676static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8677{
8678 int i;
8679 u32 key = kvm_async_pf_hash_fn(gfn);
8680
8681 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8682 (vcpu->arch.apf.gfns[key] != gfn &&
8683 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8684 key = kvm_async_pf_next_probe(key);
8685
8686 return key;
8687}
8688
8689bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8690{
8691 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8692}
8693
8694static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8695{
8696 u32 i, j, k;
8697
8698 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8699 while (true) {
8700 vcpu->arch.apf.gfns[i] = ~0;
8701 do {
8702 j = kvm_async_pf_next_probe(j);
8703 if (vcpu->arch.apf.gfns[j] == ~0)
8704 return;
8705 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8706 /*
8707 * k lies cyclically in ]i,j]
8708 * | i.k.j |
8709 * |....j i.k.| or |.k..j i...|
8710 */
8711 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8712 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8713 i = j;
8714 }
8715}
8716
7c90705b
GN		 8717static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8718{
4e335d9e
PB		 8719
8720 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8721 sizeof(val));
7c90705b
GN		 8722}
8723
9a6e7c39
WL		 8724static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8725{
8726
8727 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8728 sizeof(u32));
8729}
8730
af585b92
GN		 8731void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8732 struct kvm_async_pf *work)
8733{
6389ee94
AK		 8734 struct x86_exception fault;
8735
7c90705b 8736 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8737 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8738
8739 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8740 (vcpu->arch.apf.send_user_only &&
8741 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8742 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8743 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8744 fault.vector = PF_VECTOR;
8745 fault.error_code_valid = true;
8746 fault.error_code = 0;
8747 fault.nested_page_fault = false;
8748 fault.address = work->arch.token;
adfe20fb 8749 fault.async_page_fault = true;
6389ee94 8750 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8751 }
af585b92
GN		 8752}
8753
8754void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8755 struct kvm_async_pf *work)
8756{
6389ee94 8757 struct x86_exception fault;
9a6e7c39 8758 u32 val;
6389ee94 8759
f2e10669 8760 if (work->wakeup_all)
7c90705b
GN		 8761 work->arch.token = ~0; /* broadcast wakeup */
8762 else
8763 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8764 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8765
9a6e7c39
WL		 8766 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8767 !apf_get_user(vcpu, &val)) {
8768 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8769 vcpu->arch.exception.pending &&
8770 vcpu->arch.exception.nr == PF_VECTOR &&
8771 !apf_put_user(vcpu, 0)) {
8772 vcpu->arch.exception.injected = false;
8773 vcpu->arch.exception.pending = false;
8774 vcpu->arch.exception.nr = 0;
8775 vcpu->arch.exception.has_error_code = false;
8776 vcpu->arch.exception.error_code = 0;
8777 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8778 fault.vector = PF_VECTOR;
8779 fault.error_code_valid = true;
8780 fault.error_code = 0;
8781 fault.nested_page_fault = false;
8782 fault.address = work->arch.token;
8783 fault.async_page_fault = true;
8784 kvm_inject_page_fault(vcpu, &fault);
8785 }
7c90705b 8786 }
e6d53e3b 8787 vcpu->arch.apf.halted = false;
a4fa1635 8788 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8789}
8790
8791bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8792{
8793 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8794 return true;
8795 else
9bc1f09f 8796 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8797}
8798
5544eb9b
PB		 8799void kvm_arch_start_assignment(struct kvm *kvm)
8800{
8801 atomic_inc(&kvm->arch.assigned_device_count);
8802}
8803EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8804
8805void kvm_arch_end_assignment(struct kvm *kvm)
8806{
8807 atomic_dec(&kvm->arch.assigned_device_count);
8808}
8809EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8810
8811bool kvm_arch_has_assigned_device(struct kvm *kvm)
8812{
8813 return atomic_read(&kvm->arch.assigned_device_count);
8814}
8815EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8816
e0f0bbc5
AW		 8817void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8818{
8819 atomic_inc(&kvm->arch.noncoherent_dma_count);
8820}
8821EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8822
8823void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8824{
8825 atomic_dec(&kvm->arch.noncoherent_dma_count);
8826}
8827EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8828
8829bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8830{
8831 return atomic_read(&kvm->arch.noncoherent_dma_count);
8832}
8833EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8834
14717e20
AW		 8835bool kvm_arch_has_irq_bypass(void)
8836{
8837 return kvm_x86_ops->update_pi_irte != NULL;
8838}
8839
87276880
FW		 8840int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8841 struct irq_bypass_producer *prod)
8842{
8843 struct kvm_kernel_irqfd *irqfd =
8844 container_of(cons, struct kvm_kernel_irqfd, consumer);
8845
14717e20 8846 irqfd->producer = prod;
87276880 8847
14717e20
AW		 8848 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8849 prod->irq, irqfd->gsi, 1);
87276880
FW		 8850}
8851
8852void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8853 struct irq_bypass_producer *prod)
8854{
8855 int ret;
8856 struct kvm_kernel_irqfd *irqfd =
8857 container_of(cons, struct kvm_kernel_irqfd, consumer);
8858
87276880
FW		 8859 WARN_ON(irqfd->producer != prod);
8860 irqfd->producer = NULL;
8861
8862 /*
8863 * When producer of consumer is unregistered, we change back to
8864 * remapped mode, so we can re-use the current implementation
bb3541f1 8865 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8866 * int this case doesn't want to receive the interrupts.
8867 */
8868 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8869 if (ret)
8870 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8871 " fails: %d\n", irqfd->consumer.token, ret);
8872}
8873
8874int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8875 uint32_t guest_irq, bool set)
8876{
8877 if (!kvm_x86_ops->update_pi_irte)
8878 return -EINVAL;
8879
8880 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8881}
8882
52004014
FW		 8883bool kvm_vector_hashing_enabled(void)
8884{
8885 return vector_hashing;
8886}
8887EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8888
229456fc 8889EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8890EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8891EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8892EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8893EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8894EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8895EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8896EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8897EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8898EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8899EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8900EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8901EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8902EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8903EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8904EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8905EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8906EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8907EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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