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KVM: VMX: Fix VPID capability detection
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
9ed96e87
MT		 110unsigned int min_timer_period_us = 500;
111module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
112
630994b3
MT		 113static bool __read_mostly kvmclock_periodic_sync = true;
114module_param(kvmclock_periodic_sync, bool, S_IRUGO);
115
893590c7 116bool __read_mostly kvm_has_tsc_control;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 118u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 119EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 120u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
121EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
122u64 __read_mostly kvm_max_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 124u64 __read_mostly kvm_default_tsc_scaling_ratio;
125EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 126
cc578287 127/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 128static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 129module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
130
d0659d94 131/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 132unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 133module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
134
52004014
FW		 135static bool __read_mostly vector_hashing = true;
136module_param(vector_hashing, bool, S_IRUGO);
137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 183 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 184 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
185 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
186 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
187 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
188 { "mmu_flooded", VM_STAT(mmu_flooded) },
189 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 190 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 191 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 192 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 193 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 194 { "max_mmu_page_hash_collisions",
195 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 196 { NULL }
197};
198
2acf923e
DC		 199u64 __read_mostly host_xcr0;
200
b6785def 201static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 202
af585b92
GN		 203static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
204{
205 int i;
206 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
207 vcpu->arch.apf.gfns[i] = ~0;
208}
209
18863bdd
AK		 210static void kvm_on_user_return(struct user_return_notifier *urn)
211{
212 unsigned slot;
18863bdd
AK		 213 struct kvm_shared_msrs *locals
214 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 215 struct kvm_shared_msr_values *values;
1650b4eb
IA		 216 unsigned long flags;
217
218 /*
219 * Disabling irqs at this point since the following code could be
220 * interrupted and executed through kvm_arch_hardware_disable()
221 */
222 local_irq_save(flags);
223 if (locals->registered) {
224 locals->registered = false;
225 user_return_notifier_unregister(urn);
226 }
227 local_irq_restore(flags);
18863bdd 228 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 229 values = &locals->values[slot];
230 if (values->host != values->curr) {
231 wrmsrl(shared_msrs_global.msrs[slot], values->host);
232 values->curr = values->host;
18863bdd
AK		 233 }
234 }
18863bdd
AK		 235}
236
2bf78fa7 237static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 238{
18863bdd 239 u64 value;
013f6a5d
MT		 240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 242
2bf78fa7
SY		 243 /* only read, and nobody should modify it at this time,
244 * so don't need lock */
245 if (slot >= shared_msrs_global.nr) {
246 printk(KERN_ERR "kvm: invalid MSR slot!");
247 return;
248 }
249 rdmsrl_safe(msr, &value);
250 smsr->values[slot].host = value;
251 smsr->values[slot].curr = value;
252}
253
254void kvm_define_shared_msr(unsigned slot, u32 msr)
255{
0123be42 256 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 257 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 258 if (slot >= shared_msrs_global.nr)
259 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
262
263static void kvm_shared_msr_cpu_online(void)
264{
265 unsigned i;
18863bdd
AK		 266
267 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 268 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 269}
270
8b3c3104 271int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 272{
013f6a5d
MT		 273 unsigned int cpu = smp_processor_id();
274 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 275 int err;
18863bdd 276
2bf78fa7 277 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 278 return 0;
2bf78fa7 279 smsr->values[slot].curr = value;
8b3c3104
AH		 280 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
281 if (err)
282 return 1;
283
18863bdd
AK		 284 if (!smsr->registered) {
285 smsr->urn.on_user_return = kvm_on_user_return;
286 user_return_notifier_register(&smsr->urn);
287 smsr->registered = true;
288 }
8b3c3104 289 return 0;
18863bdd
AK		 290}
291EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
292
13a34e06 293static void drop_user_return_notifiers(void)
3548bab5 294{
013f6a5d
MT		 295 unsigned int cpu = smp_processor_id();
296 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 297
298 if (smsr->registered)
299 kvm_on_user_return(&smsr->urn);
300}
301
6866b83e
CO		 302u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
303{
8a5a87d9 304 return vcpu->arch.apic_base;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_get_apic_base);
307
58cb628d
JK		 308int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
309{
310 u64 old_state = vcpu->arch.apic_base &
311 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
312 u64 new_state = msr_info->data &
313 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 314 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
315 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 316
d3802286
JM		 317 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
318 return 1;
58cb628d 319 if (!msr_info->host_initiated &&
d3802286 320 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 321 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
322 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
323 old_state == 0)))
324 return 1;
325
326 kvm_lapic_set_base(vcpu, msr_info->data);
327 return 0;
6866b83e
CO		 328}
329EXPORT_SYMBOL_GPL(kvm_set_apic_base);
330
2605fc21 331asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 332{
333 /* Fault while not rebooting. We want the trace. */
334 BUG();
335}
336EXPORT_SYMBOL_GPL(kvm_spurious_fault);
337
3fd28fce
ED		 338#define EXCPT_BENIGN 0
339#define EXCPT_CONTRIBUTORY 1
340#define EXCPT_PF 2
341
342static int exception_class(int vector)
343{
344 switch (vector) {
345 case PF_VECTOR:
346 return EXCPT_PF;
347 case DE_VECTOR:
348 case TS_VECTOR:
349 case NP_VECTOR:
350 case SS_VECTOR:
351 case GP_VECTOR:
352 return EXCPT_CONTRIBUTORY;
353 default:
354 break;
355 }
356 return EXCPT_BENIGN;
357}
358
d6e8c854
NA		 359#define EXCPT_FAULT 0
360#define EXCPT_TRAP 1
361#define EXCPT_ABORT 2
362#define EXCPT_INTERRUPT 3
363
364static int exception_type(int vector)
365{
366 unsigned int mask;
367
368 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
369 return EXCPT_INTERRUPT;
370
371 mask = 1 << vector;
372
373 /* #DB is trap, as instruction watchpoints are handled elsewhere */
374 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
375 return EXCPT_TRAP;
376
377 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
378 return EXCPT_ABORT;
379
380 /* Reserved exceptions will result in fault */
381 return EXCPT_FAULT;
382}
383
3fd28fce 384static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 385 unsigned nr, bool has_error, u32 error_code,
386 bool reinject)
3fd28fce
ED		 387{
388 u32 prev_nr;
389 int class1, class2;
390
3842d135
AK		 391 kvm_make_request(KVM_REQ_EVENT, vcpu);
392
664f8e26 393 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 394 queue:
3ffb2468
NA		 395 if (has_error && !is_protmode(vcpu))
396 has_error = false;
664f8e26
WL		 397 if (reinject) {
398 /*
399 * On vmentry, vcpu->arch.exception.pending is only
400 * true if an event injection was blocked by
401 * nested_run_pending. In that case, however,
402 * vcpu_enter_guest requests an immediate exit,
403 * and the guest shouldn't proceed far enough to
404 * need reinjection.
405 */
406 WARN_ON_ONCE(vcpu->arch.exception.pending);
407 vcpu->arch.exception.injected = true;
408 } else {
409 vcpu->arch.exception.pending = true;
410 vcpu->arch.exception.injected = false;
411 }
3fd28fce
ED		 412 vcpu->arch.exception.has_error_code = has_error;
413 vcpu->arch.exception.nr = nr;
414 vcpu->arch.exception.error_code = error_code;
415 return;
416 }
417
418 /* to check exception */
419 prev_nr = vcpu->arch.exception.nr;
420 if (prev_nr == DF_VECTOR) {
421 /* triple fault -> shutdown */
a8eeb04a 422 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 423 return;
424 }
425 class1 = exception_class(prev_nr);
426 class2 = exception_class(nr);
427 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
428 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 429 /*
430 * Generate double fault per SDM Table 5-5. Set
431 * exception.pending = true so that the double fault
432 * can trigger a nested vmexit.
433 */
3fd28fce 434 vcpu->arch.exception.pending = true;
664f8e26 435 vcpu->arch.exception.injected = false;
3fd28fce
ED		 436 vcpu->arch.exception.has_error_code = true;
437 vcpu->arch.exception.nr = DF_VECTOR;
438 vcpu->arch.exception.error_code = 0;
439 } else
440 /* replace previous exception with a new one in a hope
441 that instruction re-execution will regenerate lost
442 exception */
443 goto queue;
444}
445
298101da
AK		 446void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
447{
ce7ddec4 448 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 449}
450EXPORT_SYMBOL_GPL(kvm_queue_exception);
451
ce7ddec4
JR		 452void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
453{
454 kvm_multiple_exception(vcpu, nr, false, 0, true);
455}
456EXPORT_SYMBOL_GPL(kvm_requeue_exception);
457
6affcbed 458int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 459{
db8fcefa
AP		 460 if (err)
461 kvm_inject_gp(vcpu, 0);
462 else
6affcbed
KH		 463 return kvm_skip_emulated_instruction(vcpu);
464
465 return 1;
db8fcefa
AP		 466}
467EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 468
6389ee94 469void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 470{
471 ++vcpu->stat.pf_guest;
adfe20fb
WL		 472 vcpu->arch.exception.nested_apf =
473 is_guest_mode(vcpu) && fault->async_page_fault;
474 if (vcpu->arch.exception.nested_apf)
475 vcpu->arch.apf.nested_apf_token = fault->address;
476 else
477 vcpu->arch.cr2 = fault->address;
6389ee94 478 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 479}
27d6c865 480EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 481
ef54bcfe 482static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 483{
6389ee94
AK		 484 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
485 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 486 else
6389ee94 487 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 488
489 return fault->nested_page_fault;
d4f8cf66
JR		 490}
491
3419ffc8
SY		 492void kvm_inject_nmi(struct kvm_vcpu *vcpu)
493{
7460fb4a
AK		 494 atomic_inc(&vcpu->arch.nmi_queued);
495 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 496}
497EXPORT_SYMBOL_GPL(kvm_inject_nmi);
498
298101da
AK		 499void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
500{
ce7ddec4 501 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 502}
503EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
504
ce7ddec4
JR		 505void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
506{
507 kvm_multiple_exception(vcpu, nr, true, error_code, true);
508}
509EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
510
0a79b009
AK		 511/*
512 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
513 * a #GP and return false.
514 */
515bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 516{
0a79b009
AK		 517 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
518 return true;
519 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
520 return false;
298101da 521}
0a79b009 522EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 523
16f8a6f9
NA		 524bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
525{
526 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
527 return true;
528
529 kvm_queue_exception(vcpu, UD_VECTOR);
530 return false;
531}
532EXPORT_SYMBOL_GPL(kvm_require_dr);
533
ec92fe44
JR		 534/*
535 * This function will be used to read from the physical memory of the currently
54bf36aa 536 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 537 * can read from guest physical or from the guest's guest physical memory.
538 */
539int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
540 gfn_t ngfn, void *data, int offset, int len,
541 u32 access)
542{
54987b7a 543 struct x86_exception exception;
ec92fe44
JR		 544 gfn_t real_gfn;
545 gpa_t ngpa;
546
547 ngpa = gfn_to_gpa(ngfn);
54987b7a 548 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 549 if (real_gfn == UNMAPPED_GVA)
550 return -EFAULT;
551
552 real_gfn = gpa_to_gfn(real_gfn);
553
54bf36aa 554 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 555}
556EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
557
69b0049a 558static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 559 void *data, int offset, int len, u32 access)
560{
561 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
562 data, offset, len, access);
563}
564
a03490ed
CO		 565/*
566 * Load the pae pdptrs. Return true is they are all valid.
567 */
ff03a073 568int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 569{
570 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
571 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
572 int i;
573 int ret;
ff03a073 574 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 575
ff03a073
JR		 576 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
577 offset * sizeof(u64), sizeof(pdpte),
578 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 579 if (ret < 0) {
580 ret = 0;
581 goto out;
582 }
583 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 584 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 585 (pdpte[i] &
586 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 587 ret = 0;
588 goto out;
589 }
590 }
591 ret = 1;
592
ff03a073 593 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 594 __set_bit(VCPU_EXREG_PDPTR,
595 (unsigned long *)&vcpu->arch.regs_avail);
596 __set_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 598out:
a03490ed
CO		 599
600 return ret;
601}
cc4b6871 602EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 603
9ed38ffa 604bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 605{
ff03a073 606 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 607 bool changed = true;
3d06b8bf
JR		 608 int offset;
609 gfn_t gfn;
d835dfec
AK		 610 int r;
611
612 if (is_long_mode(vcpu) || !is_pae(vcpu))
613 return false;
614
6de4f3ad
AK		 615 if (!test_bit(VCPU_EXREG_PDPTR,
616 (unsigned long *)&vcpu->arch.regs_avail))
617 return true;
618
a512177e
PB		 619 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
620 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 621 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
622 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 623 if (r < 0)
624 goto out;
ff03a073 625 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 626out:
d835dfec
AK		 627
628 return changed;
629}
9ed38ffa 630EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 631
49a9b07e 632int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 633{
aad82703 634 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 635 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 636
f9a48e6a
AK		 637 cr0 |= X86_CR0_ET;
638
ab344828 639#ifdef CONFIG_X86_64
0f12244f
GN		 640 if (cr0 & 0xffffffff00000000UL)
641 return 1;
ab344828
GN		 642#endif
643
644 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 645
0f12244f
GN		 646 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
647 return 1;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
650 return 1;
a03490ed
CO		 651
652 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
653#ifdef CONFIG_X86_64
f6801dff 654 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 655 int cs_db, cs_l;
656
0f12244f
GN		 657 if (!is_pae(vcpu))
658 return 1;
a03490ed 659 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 660 if (cs_l)
661 return 1;
a03490ed
CO		 662 } else
663#endif
ff03a073 664 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 665 kvm_read_cr3(vcpu)))
0f12244f 666 return 1;
a03490ed
CO		 667 }
668
ad756a16
MJ		 669 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
670 return 1;
671
a03490ed 672 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 673
d170c419 674 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 675 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 676 kvm_async_pf_hash_reset(vcpu);
677 }
e5f3f027 678
aad82703
SY		 679 if ((cr0 ^ old_cr0) & update_bits)
680 kvm_mmu_reset_context(vcpu);
b18d5431 681
879ae188
LE		 682 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
683 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
684 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 685 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
686
0f12244f
GN		 687 return 0;
688}
2d3ad1f4 689EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 690
2d3ad1f4 691void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 692{
49a9b07e 693 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 696
42bdf991
MT		 697static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
698{
699 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
700 !vcpu->guest_xcr0_loaded) {
701 /* kvm_set_xcr() also depends on this */
702 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
703 vcpu->guest_xcr0_loaded = 1;
704 }
705}
706
707static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
708{
709 if (vcpu->guest_xcr0_loaded) {
710 if (vcpu->arch.xcr0 != host_xcr0)
711 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
712 vcpu->guest_xcr0_loaded = 0;
713 }
714}
715
69b0049a 716static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 717{
56c103ec
LJ		 718 u64 xcr0 = xcr;
719 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 720 u64 valid_bits;
2acf923e
DC		 721
722 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
723 if (index != XCR_XFEATURE_ENABLED_MASK)
724 return 1;
d91cab78 725 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 728 return 1;
46c34cb0
PB		 729
730 /*
731 * Do not allow the guest to set bits that we do not support
732 * saving. However, xcr0 bit 0 is always set, even if the
733 * emulated CPU does not support XSAVE (see fx_init).
734 */
d91cab78 735 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 736 if (xcr0 & ~valid_bits)
2acf923e 737 return 1;
46c34cb0 738
d91cab78
DH		 739 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
740 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 741 return 1;
742
d91cab78
DH		 743 if (xcr0 & XFEATURE_MASK_AVX512) {
744 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 745 return 1;
d91cab78 746 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 747 return 1;
748 }
2acf923e 749 vcpu->arch.xcr0 = xcr0;
56c103ec 750
d91cab78 751 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 752 kvm_update_cpuid(vcpu);
2acf923e
DC		 753 return 0;
754}
755
756int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
757{
764bcbc5
Z		 758 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
759 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 760 kvm_inject_gp(vcpu, 0);
761 return 1;
762 }
763 return 0;
764}
765EXPORT_SYMBOL_GPL(kvm_set_xcr);
766
a83b29c6 767int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 768{
fc78f519 769 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 770 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 771 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 772
0f12244f
GN		 773 if (cr4 & CR4_RESERVED_BITS)
774 return 1;
a03490ed 775
d6321d49 776 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 777 return 1;
778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 789 return 1;
790
fd8cb433 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 792 return 1;
793
a03490ed 794 if (is_long_mode(vcpu)) {
0f12244f
GN		 795 if (!(cr4 & X86_CR4_PAE))
796 return 1;
a2edf57f
AK		 797 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
798 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 799 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
800 kvm_read_cr3(vcpu)))
0f12244f
GN		 801 return 1;
802
ad756a16 803 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 804 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 805 return 1;
806
807 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
808 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
809 return 1;
810 }
811
5e1746d6 812 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 813 return 1;
a03490ed 814
ad756a16
MJ		 815 if (((cr4 ^ old_cr4) & pdptr_bits) ||
816 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 817 kvm_mmu_reset_context(vcpu);
0f12244f 818
b9baba86 819 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 820 kvm_update_cpuid(vcpu);
2acf923e 821
0f12244f
GN		 822 return 0;
823}
2d3ad1f4 824EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 825
2390218b 826int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 827{
ac146235 828#ifdef CONFIG_X86_64
9d88fca7 829 cr3 &= ~CR3_PCID_INVD;
ac146235 830#endif
9d88fca7 831
9f8fe504 832 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 833 kvm_mmu_sync_roots(vcpu);
77c3913b 834 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 835 return 0;
d835dfec
AK		 836 }
837
d1cd3ce9
YZ		 838 if (is_long_mode(vcpu) &&
839 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
840 return 1;
841 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 842 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 843 return 1;
a03490ed 844
0f12244f 845 vcpu->arch.cr3 = cr3;
aff48baa 846 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 847 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 848 return 0;
849}
2d3ad1f4 850EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 851
eea1cff9 852int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 853{
0f12244f
GN		 854 if (cr8 & CR8_RESERVED_BITS)
855 return 1;
35754c98 856 if (lapic_in_kernel(vcpu))
a03490ed
CO		 857 kvm_lapic_set_tpr(vcpu, cr8);
858 else
ad312c7c 859 vcpu->arch.cr8 = cr8;
0f12244f
GN		 860 return 0;
861}
2d3ad1f4 862EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 863
2d3ad1f4 864unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 865{
35754c98 866 if (lapic_in_kernel(vcpu))
a03490ed
CO		 867 return kvm_lapic_get_cr8(vcpu);
868 else
ad312c7c 869 return vcpu->arch.cr8;
a03490ed 870}
2d3ad1f4 871EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 872
ae561ede
NA		 873static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
874{
875 int i;
876
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
878 for (i = 0; i < KVM_NR_DB_REGS; i++)
879 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
880 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
881 }
882}
883
73aaf249
JK		 884static void kvm_update_dr6(struct kvm_vcpu *vcpu)
885{
886 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
887 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
888}
889
c8639010
JK		 890static void kvm_update_dr7(struct kvm_vcpu *vcpu)
891{
892 unsigned long dr7;
893
894 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
895 dr7 = vcpu->arch.guest_debug_dr7;
896 else
897 dr7 = vcpu->arch.dr7;
898 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 899 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
900 if (dr7 & DR7_BP_EN_MASK)
901 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 902}
903
6f43ed01
NA		 904static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
905{
906 u64 fixed = DR6_FIXED_1;
907
d6321d49 908 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 909 fixed |= DR6_RTM;
910 return fixed;
911}
912
338dbc97 913static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 914{
915 switch (dr) {
916 case 0 ... 3:
917 vcpu->arch.db[dr] = val;
918 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
919 vcpu->arch.eff_db[dr] = val;
920 break;
921 case 4:
020df079
GN		 922 /* fall through */
923 case 6:
338dbc97
GN		 924 if (val & 0xffffffff00000000ULL)
925 return -1; /* #GP */
6f43ed01 926 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 927 kvm_update_dr6(vcpu);
020df079
GN		 928 break;
929 case 5:
020df079
GN		 930 /* fall through */
931 default: /* 7 */
338dbc97
GN		 932 if (val & 0xffffffff00000000ULL)
933 return -1; /* #GP */
020df079 934 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 935 kvm_update_dr7(vcpu);
020df079
GN		 936 break;
937 }
938
939 return 0;
940}
338dbc97
GN		 941
942int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
943{
16f8a6f9 944 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 945 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 946 return 1;
947 }
948 return 0;
338dbc97 949}
020df079
GN		 950EXPORT_SYMBOL_GPL(kvm_set_dr);
951
16f8a6f9 952int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 953{
954 switch (dr) {
955 case 0 ... 3:
956 *val = vcpu->arch.db[dr];
957 break;
958 case 4:
020df079
GN		 959 /* fall through */
960 case 6:
73aaf249
JK		 961 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
962 *val = vcpu->arch.dr6;
963 else
964 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 965 break;
966 case 5:
020df079
GN		 967 /* fall through */
968 default: /* 7 */
969 *val = vcpu->arch.dr7;
970 break;
971 }
338dbc97
GN		 972 return 0;
973}
020df079
GN		 974EXPORT_SYMBOL_GPL(kvm_get_dr);
975
022cd0e8
AK		 976bool kvm_rdpmc(struct kvm_vcpu *vcpu)
977{
978 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
979 u64 data;
980 int err;
981
c6702c9d 982 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 983 if (err)
984 return err;
985 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
986 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
987 return err;
988}
989EXPORT_SYMBOL_GPL(kvm_rdpmc);
990
043405e1
CO		 991/*
992 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
993 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
994 *
995 * This list is modified at module load time to reflect the
e3267cbb 996 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 997 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
998 * may depend on host virtualization features rather than host cpu features.
043405e1 999 */
e3267cbb 1000
043405e1
CO		 1001static u32 msrs_to_save[] = {
1002 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1003 MSR_STAR,
043405e1
CO		 1004#ifdef CONFIG_X86_64
1005 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1006#endif
b3897a49 1007 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1008 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1009};
1010
1011static unsigned num_msrs_to_save;
1012
62ef68bb
PB		 1013static u32 emulated_msrs[] = {
1014 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1015 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1016 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1017 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1018 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1019 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1020 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1021 HV_X64_MSR_RESET,
11c4b1ca 1022 HV_X64_MSR_VP_INDEX,
9eec50b8 1023 HV_X64_MSR_VP_RUNTIME,
5c919412 1024 HV_X64_MSR_SCONTROL,
1f4b34f8 1025 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1026 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1027 MSR_KVM_PV_EOI_EN,
1028
ba904635 1029 MSR_IA32_TSC_ADJUST,
a3e06bbe 1030 MSR_IA32_TSCDEADLINE,
043405e1 1031 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1032 MSR_IA32_MCG_STATUS,
1033 MSR_IA32_MCG_CTL,
c45dcc71 1034 MSR_IA32_MCG_EXT_CTL,
64d60670 1035 MSR_IA32_SMBASE,
db2336a8
KH		 1036 MSR_PLATFORM_INFO,
1037 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1038};
1039
62ef68bb
PB		 1040static unsigned num_emulated_msrs;
1041
384bb783 1042bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1043{
b69e8cae 1044 if (efer & efer_reserved_bits)
384bb783 1045 return false;
15c4a640 1046
1b4d56b8 1047 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1048 return false;
1b2fd70c 1049
1b4d56b8 1050 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1051 return false;
d8017474 1052
384bb783
JK		 1053 return true;
1054}
1055EXPORT_SYMBOL_GPL(kvm_valid_efer);
1056
1057static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1058{
1059 u64 old_efer = vcpu->arch.efer;
1060
1061 if (!kvm_valid_efer(vcpu, efer))
1062 return 1;
1063
1064 if (is_paging(vcpu)
1065 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1066 return 1;
1067
15c4a640 1068 efer &= ~EFER_LMA;
f6801dff 1069 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1070
a3d204e2
SY		 1071 kvm_x86_ops->set_efer(vcpu, efer);
1072
aad82703
SY		 1073 /* Update reserved bits */
1074 if ((efer ^ old_efer) & EFER_NX)
1075 kvm_mmu_reset_context(vcpu);
1076
b69e8cae 1077 return 0;
15c4a640
CO		 1078}
1079
f2b4b7dd
JR		 1080void kvm_enable_efer_bits(u64 mask)
1081{
1082 efer_reserved_bits &= ~mask;
1083}
1084EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1085
15c4a640
CO		 1086/*
1087 * Writes msr value into into the appropriate "register".
1088 * Returns 0 on success, non-0 otherwise.
1089 * Assumes vcpu_load() was already called.
1090 */
8fe8ab46 1091int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1092{
854e8bb1
NA		 1093 switch (msr->index) {
1094 case MSR_FS_BASE:
1095 case MSR_GS_BASE:
1096 case MSR_KERNEL_GS_BASE:
1097 case MSR_CSTAR:
1098 case MSR_LSTAR:
fd8cb433 1099 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1100 return 1;
1101 break;
1102 case MSR_IA32_SYSENTER_EIP:
1103 case MSR_IA32_SYSENTER_ESP:
1104 /*
1105 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1106 * non-canonical address is written on Intel but not on
1107 * AMD (which ignores the top 32-bits, because it does
1108 * not implement 64-bit SYSENTER).
1109 *
1110 * 64-bit code should hence be able to write a non-canonical
1111 * value on AMD. Making the address canonical ensures that
1112 * vmentry does not fail on Intel after writing a non-canonical
1113 * value, and that something deterministic happens if the guest
1114 * invokes 64-bit SYSENTER.
1115 */
fd8cb433 1116 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1117 }
8fe8ab46 1118 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1119}
854e8bb1 1120EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1121
313a3dc7
CO		 1122/*
1123 * Adapt set_msr() to msr_io()'s calling convention
1124 */
609e36d3
PB		 1125static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1126{
1127 struct msr_data msr;
1128 int r;
1129
1130 msr.index = index;
1131 msr.host_initiated = true;
1132 r = kvm_get_msr(vcpu, &msr);
1133 if (r)
1134 return r;
1135
1136 *data = msr.data;
1137 return 0;
1138}
1139
313a3dc7
CO		 1140static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1141{
8fe8ab46
WA		 1142 struct msr_data msr;
1143
1144 msr.data = *data;
1145 msr.index = index;
1146 msr.host_initiated = true;
1147 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1148}
1149
16e8d74d
MT		 1150#ifdef CONFIG_X86_64
1151struct pvclock_gtod_data {
1152 seqcount_t seq;
1153
1154 struct { /* extract of a clocksource struct */
1155 int vclock_mode;
a5a1d1c2
TG		 1156 u64 cycle_last;
1157 u64 mask;
16e8d74d
MT		 1158 u32 mult;
1159 u32 shift;
1160 } clock;
1161
cbcf2dd3
TG		 1162 u64 boot_ns;
1163 u64 nsec_base;
55dd00a7 1164 u64 wall_time_sec;
16e8d74d
MT		 1165};
1166
1167static struct pvclock_gtod_data pvclock_gtod_data;
1168
1169static void update_pvclock_gtod(struct timekeeper *tk)
1170{
1171 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1172 u64 boot_ns;
1173
876e7881 1174 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1175
1176 write_seqcount_begin(&vdata->seq);
1177
1178 /* copy pvclock gtod data */
876e7881
PZ		 1179 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1180 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1181 vdata->clock.mask = tk->tkr_mono.mask;
1182 vdata->clock.mult = tk->tkr_mono.mult;
1183 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1184
cbcf2dd3 1185 vdata->boot_ns = boot_ns;
876e7881 1186 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1187
55dd00a7
MT		 1188 vdata->wall_time_sec = tk->xtime_sec;
1189
16e8d74d
MT		 1190 write_seqcount_end(&vdata->seq);
1191}
1192#endif
1193
bab5bb39
NK		 1194void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1195{
1196 /*
1197 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1198 * vcpu_enter_guest. This function is only called from
1199 * the physical CPU that is running vcpu.
1200 */
1201 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1202}
16e8d74d 1203
18068523
GOC		 1204static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1205{
9ed3c444
AK		 1206 int version;
1207 int r;
50d0a0f9 1208 struct pvclock_wall_clock wc;
87aeb54f 1209 struct timespec64 boot;
18068523
GOC		 1210
1211 if (!wall_clock)
1212 return;
1213
9ed3c444
AK		 1214 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1215 if (r)
1216 return;
1217
1218 if (version & 1)
1219 ++version; /* first time write, random junk */
1220
1221 ++version;
18068523 1222
1dab1345
NK		 1223 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1224 return;
18068523 1225
50d0a0f9
GH		 1226 /*
1227 * The guest calculates current wall clock time by adding
34c238a1 1228 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1229 * wall clock specified here. guest system time equals host
1230 * system time for us, thus we must fill in host boot time here.
1231 */
87aeb54f 1232 getboottime64(&boot);
50d0a0f9 1233
4b648665 1234 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1235 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1236 boot = timespec64_sub(boot, ts);
4b648665 1237 }
87aeb54f 1238 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1239 wc.nsec = boot.tv_nsec;
1240 wc.version = version;
18068523
GOC		 1241
1242 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1243
1244 version++;
1245 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1246}
1247
50d0a0f9
GH		 1248static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1249{
b51012de
PB		 1250 do_shl32_div32(dividend, divisor);
1251 return dividend;
50d0a0f9
GH		 1252}
1253
3ae13faa 1254static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1255 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1256{
5f4e3f88 1257 uint64_t scaled64;
50d0a0f9
GH		 1258 int32_t shift = 0;
1259 uint64_t tps64;
1260 uint32_t tps32;
1261
3ae13faa
PB		 1262 tps64 = base_hz;
1263 scaled64 = scaled_hz;
50933623 1264 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1265 tps64 >>= 1;
1266 shift--;
1267 }
1268
1269 tps32 = (uint32_t)tps64;
50933623
JK		 1270 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1271 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1272 scaled64 >>= 1;
1273 else
1274 tps32 <<= 1;
50d0a0f9
GH		 1275 shift++;
1276 }
1277
5f4e3f88
ZA		 1278 *pshift = shift;
1279 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1280
3ae13faa
PB		 1281 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1282 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1283}
1284
d828199e 1285#ifdef CONFIG_X86_64
16e8d74d 1286static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1287#endif
16e8d74d 1288
c8076604 1289static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1290static unsigned long max_tsc_khz;
c8076604 1291
cc578287 1292static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1293{
cc578287
ZA		 1294 u64 v = (u64)khz * (1000000 + ppm);
1295 do_div(v, 1000000);
1296 return v;
1e993611
JR		 1297}
1298
381d585c
HZ		 1299static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1300{
1301 u64 ratio;
1302
1303 /* Guest TSC same frequency as host TSC? */
1304 if (!scale) {
1305 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1306 return 0;
1307 }
1308
1309 /* TSC scaling supported? */
1310 if (!kvm_has_tsc_control) {
1311 if (user_tsc_khz > tsc_khz) {
1312 vcpu->arch.tsc_catchup = 1;
1313 vcpu->arch.tsc_always_catchup = 1;
1314 return 0;
1315 } else {
1316 WARN(1, "user requested TSC rate below hardware speed\n");
1317 return -1;
1318 }
1319 }
1320
1321 /* TSC scaling required - calculate ratio */
1322 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1323 user_tsc_khz, tsc_khz);
1324
1325 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1326 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1327 user_tsc_khz);
1328 return -1;
1329 }
1330
1331 vcpu->arch.tsc_scaling_ratio = ratio;
1332 return 0;
1333}
1334
4941b8cb 1335static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1336{
cc578287
ZA		 1337 u32 thresh_lo, thresh_hi;
1338 int use_scaling = 0;
217fc9cf 1339
03ba32ca 1340 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1341 if (user_tsc_khz == 0) {
ad721883
HZ		 1342 /* set tsc_scaling_ratio to a safe value */
1343 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1344 return -1;
ad721883 1345 }
03ba32ca 1346
c285545f 1347 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1348 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1349 &vcpu->arch.virtual_tsc_shift,
1350 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1351 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1352
1353 /*
1354 * Compute the variation in TSC rate which is acceptable
1355 * within the range of tolerance and decide if the
1356 * rate being applied is within that bounds of the hardware
1357 * rate. If so, no scaling or compensation need be done.
1358 */
1359 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1360 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1361 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1362 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1363 use_scaling = 1;
1364 }
4941b8cb 1365 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1366}
1367
1368static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1369{
e26101b1 1370 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1371 vcpu->arch.virtual_tsc_mult,
1372 vcpu->arch.virtual_tsc_shift);
e26101b1 1373 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1374 return tsc;
1375}
1376
69b0049a 1377static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1378{
1379#ifdef CONFIG_X86_64
1380 bool vcpus_matched;
b48aa97e
MT		 1381 struct kvm_arch *ka = &vcpu->kvm->arch;
1382 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1383
1384 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1385 atomic_read(&vcpu->kvm->online_vcpus));
1386
7f187922
MT		 1387 /*
1388 * Once the masterclock is enabled, always perform request in
1389 * order to update it.
1390 *
1391 * In order to enable masterclock, the host clocksource must be TSC
1392 * and the vcpus need to have matched TSCs. When that happens,
1393 * perform request to enable masterclock.
1394 */
1395 if (ka->use_master_clock ||
1396 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1397 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1398
1399 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1400 atomic_read(&vcpu->kvm->online_vcpus),
1401 ka->use_master_clock, gtod->clock.vclock_mode);
1402#endif
1403}
1404
ba904635
WA		 1405static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1406{
3e3f5026 1407 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1408 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1409}
1410
35181e86
HZ		 1411/*
1412 * Multiply tsc by a fixed point number represented by ratio.
1413 *
1414 * The most significant 64-N bits (mult) of ratio represent the
1415 * integral part of the fixed point number; the remaining N bits
1416 * (frac) represent the fractional part, ie. ratio represents a fixed
1417 * point number (mult + frac * 2^(-N)).
1418 *
1419 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1420 */
1421static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1422{
1423 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1424}
1425
1426u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1427{
1428 u64 _tsc = tsc;
1429 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1430
1431 if (ratio != kvm_default_tsc_scaling_ratio)
1432 _tsc = __scale_tsc(ratio, tsc);
1433
1434 return _tsc;
1435}
1436EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1437
07c1419a
HZ		 1438static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1439{
1440 u64 tsc;
1441
1442 tsc = kvm_scale_tsc(vcpu, rdtsc());
1443
1444 return target_tsc - tsc;
1445}
1446
4ba76538
HZ		 1447u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1448{
ea26e4ec 1449 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1450}
1451EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1452
a545ab6a
LC		 1453static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1454{
1455 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1456 vcpu->arch.tsc_offset = offset;
1457}
1458
8fe8ab46 1459void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1460{
1461 struct kvm *kvm = vcpu->kvm;
f38e098f 1462 u64 offset, ns, elapsed;
99e3e30a 1463 unsigned long flags;
b48aa97e 1464 bool matched;
0d3da0d2 1465 bool already_matched;
8fe8ab46 1466 u64 data = msr->data;
c5e8ec8e 1467 bool synchronizing = false;
99e3e30a 1468
038f8c11 1469 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1470 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1471 ns = ktime_get_boot_ns();
f38e098f 1472 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1473
03ba32ca 1474 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1475 if (data == 0 && msr->host_initiated) {
1476 /*
1477 * detection of vcpu initialization -- need to sync
1478 * with other vCPUs. This particularly helps to keep
1479 * kvm_clock stable after CPU hotplug
1480 */
1481 synchronizing = true;
1482 } else {
1483 u64 tsc_exp = kvm->arch.last_tsc_write +
1484 nsec_to_cycles(vcpu, elapsed);
1485 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1486 /*
1487 * Special case: TSC write with a small delta (1 second)
1488 * of virtual cycle time against real time is
1489 * interpreted as an attempt to synchronize the CPU.
1490 */
1491 synchronizing = data < tsc_exp + tsc_hz &&
1492 data + tsc_hz > tsc_exp;
1493 }
c5e8ec8e 1494 }
f38e098f
ZA		 1495
1496 /*
5d3cb0f6
ZA		 1497 * For a reliable TSC, we can match TSC offsets, and for an unstable
1498 * TSC, we add elapsed time in this computation. We could let the
1499 * compensation code attempt to catch up if we fall behind, but
1500 * it's better to try to match offsets from the beginning.
1501 */
c5e8ec8e 1502 if (synchronizing &&
5d3cb0f6 1503 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1504 if (!check_tsc_unstable()) {
e26101b1 1505 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1506 pr_debug("kvm: matched tsc offset for %llu\n", data);
1507 } else {
857e4099 1508 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1509 data += delta;
07c1419a 1510 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1511 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1512 }
b48aa97e 1513 matched = true;
0d3da0d2 1514 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1515 } else {
1516 /*
1517 * We split periods of matched TSC writes into generations.
1518 * For each generation, we track the original measured
1519 * nanosecond time, offset, and write, so if TSCs are in
1520 * sync, we can match exact offset, and if not, we can match
4a969980 1521 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1522 *
1523 * These values are tracked in kvm->arch.cur_xxx variables.
1524 */
1525 kvm->arch.cur_tsc_generation++;
1526 kvm->arch.cur_tsc_nsec = ns;
1527 kvm->arch.cur_tsc_write = data;
1528 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1529 matched = false;
0d3da0d2 1530 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1531 kvm->arch.cur_tsc_generation, data);
f38e098f 1532 }
e26101b1
ZA		 1533
1534 /*
1535 * We also track th most recent recorded KHZ, write and time to
1536 * allow the matching interval to be extended at each write.
1537 */
f38e098f
ZA		 1538 kvm->arch.last_tsc_nsec = ns;
1539 kvm->arch.last_tsc_write = data;
5d3cb0f6 1540 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1541
b183aa58 1542 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1543
1544 /* Keep track of which generation this VCPU has synchronized to */
1545 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1546 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1547 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1548
d6321d49 1549 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1550 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1551
a545ab6a 1552 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1553 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1554
1555 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1556 if (!matched) {
b48aa97e 1557 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1558 } else if (!already_matched) {
1559 kvm->arch.nr_vcpus_matched_tsc++;
1560 }
b48aa97e
MT		 1561
1562 kvm_track_tsc_matching(vcpu);
1563 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1564}
e26101b1 1565
99e3e30a
ZA		 1566EXPORT_SYMBOL_GPL(kvm_write_tsc);
1567
58ea6767
HZ		 1568static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1569 s64 adjustment)
1570{
ea26e4ec 1571 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1572}
1573
1574static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1575{
1576 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1577 WARN_ON(adjustment < 0);
1578 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1579 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1580}
1581
d828199e
MT		 1582#ifdef CONFIG_X86_64
1583
a5a1d1c2 1584static u64 read_tsc(void)
d828199e 1585{
a5a1d1c2 1586 u64 ret = (u64)rdtsc_ordered();
03b9730b 1587 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1588
1589 if (likely(ret >= last))
1590 return ret;
1591
1592 /*
1593 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1594 * predictable (it's just a function of time and the likely is
d828199e
MT		 1595 * very likely) and there's a data dependence, so force GCC
1596 * to generate a branch instead. I don't barrier() because
1597 * we don't actually need a barrier, and if this function
1598 * ever gets inlined it will generate worse code.
1599 */
1600 asm volatile ("");
1601 return last;
1602}
1603
a5a1d1c2 1604static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1605{
1606 long v;
1607 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1608
1609 *cycle_now = read_tsc();
1610
1611 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1612 return v * gtod->clock.mult;
1613}
1614
a5a1d1c2 1615static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1616{
cbcf2dd3 1617 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1618 unsigned long seq;
d828199e 1619 int mode;
cbcf2dd3 1620 u64 ns;
d828199e 1621
d828199e
MT		 1622 do {
1623 seq = read_seqcount_begin(&gtod->seq);
1624 mode = gtod->clock.vclock_mode;
cbcf2dd3 1625 ns = gtod->nsec_base;
d828199e
MT		 1626 ns += vgettsc(cycle_now);
1627 ns >>= gtod->clock.shift;
cbcf2dd3 1628 ns += gtod->boot_ns;
d828199e 1629 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1630 *t = ns;
d828199e
MT		 1631
1632 return mode;
1633}
1634
55dd00a7
MT		 1635static int do_realtime(struct timespec *ts, u64 *cycle_now)
1636{
1637 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1638 unsigned long seq;
1639 int mode;
1640 u64 ns;
1641
1642 do {
1643 seq = read_seqcount_begin(&gtod->seq);
1644 mode = gtod->clock.vclock_mode;
1645 ts->tv_sec = gtod->wall_time_sec;
1646 ns = gtod->nsec_base;
1647 ns += vgettsc(cycle_now);
1648 ns >>= gtod->clock.shift;
1649 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1650
1651 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1652 ts->tv_nsec = ns;
1653
1654 return mode;
1655}
1656
d828199e 1657/* returns true if host is using tsc clocksource */
a5a1d1c2 1658static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1659{
d828199e
MT		 1660 /* checked again under seqlock below */
1661 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1662 return false;
1663
cbcf2dd3 1664 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1665}
55dd00a7
MT		 1666
1667/* returns true if host is using tsc clocksource */
1668static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1669 u64 *cycle_now)
1670{
1671 /* checked again under seqlock below */
1672 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1673 return false;
1674
1675 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1676}
d828199e
MT		 1677#endif
1678
1679/*
1680 *
b48aa97e
MT		 1681 * Assuming a stable TSC across physical CPUS, and a stable TSC
1682 * across virtual CPUs, the following condition is possible.
1683 * Each numbered line represents an event visible to both
d828199e
MT		 1684 * CPUs at the next numbered event.
1685 *
1686 * "timespecX" represents host monotonic time. "tscX" represents
1687 * RDTSC value.
1688 *
1689 * VCPU0 on CPU0 | VCPU1 on CPU1
1690 *
1691 * 1. read timespec0,tsc0
1692 * 2. | timespec1 = timespec0 + N
1693 * | tsc1 = tsc0 + M
1694 * 3. transition to guest | transition to guest
1695 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1696 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1697 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1698 *
1699 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1700 *
1701 * - ret0 < ret1
1702 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1703 * ...
1704 * - 0 < N - M => M < N
1705 *
1706 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1707 * always the case (the difference between two distinct xtime instances
1708 * might be smaller then the difference between corresponding TSC reads,
1709 * when updating guest vcpus pvclock areas).
1710 *
1711 * To avoid that problem, do not allow visibility of distinct
1712 * system_timestamp/tsc_timestamp values simultaneously: use a master
1713 * copy of host monotonic time values. Update that master copy
1714 * in lockstep.
1715 *
b48aa97e 1716 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1717 *
1718 */
1719
1720static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1721{
1722#ifdef CONFIG_X86_64
1723 struct kvm_arch *ka = &kvm->arch;
1724 int vclock_mode;
b48aa97e
MT		 1725 bool host_tsc_clocksource, vcpus_matched;
1726
1727 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1728 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1729
1730 /*
1731 * If the host uses TSC clock, then passthrough TSC as stable
1732 * to the guest.
1733 */
b48aa97e 1734 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1735 &ka->master_kernel_ns,
1736 &ka->master_cycle_now);
1737
16a96021 1738 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1739 && !ka->backwards_tsc_observed
54750f2c 1740 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1741
d828199e
MT		 1742 if (ka->use_master_clock)
1743 atomic_set(&kvm_guest_has_master_clock, 1);
1744
1745 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1746 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1747 vcpus_matched);
d828199e
MT		 1748#endif
1749}
1750
2860c4b1
PB		 1751void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1752{
1753 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1754}
1755
2e762ff7
MT		 1756static void kvm_gen_update_masterclock(struct kvm *kvm)
1757{
1758#ifdef CONFIG_X86_64
1759 int i;
1760 struct kvm_vcpu *vcpu;
1761 struct kvm_arch *ka = &kvm->arch;
1762
1763 spin_lock(&ka->pvclock_gtod_sync_lock);
1764 kvm_make_mclock_inprogress_request(kvm);
1765 /* no guest entries from this point */
1766 pvclock_update_vm_gtod_copy(kvm);
1767
1768 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1769 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1770
1771 /* guest entries allowed */
1772 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1773 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1774
1775 spin_unlock(&ka->pvclock_gtod_sync_lock);
1776#endif
1777}
1778
e891a32e 1779u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1780{
108b249c 1781 struct kvm_arch *ka = &kvm->arch;
8b953440 1782 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1783 u64 ret;
108b249c 1784
8b953440
PB		 1785 spin_lock(&ka->pvclock_gtod_sync_lock);
1786 if (!ka->use_master_clock) {
1787 spin_unlock(&ka->pvclock_gtod_sync_lock);
1788 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1789 }
1790
8b953440
PB		 1791 hv_clock.tsc_timestamp = ka->master_cycle_now;
1792 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1793 spin_unlock(&ka->pvclock_gtod_sync_lock);
1794
e2c2206a
WL		 1795 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1796 get_cpu();
1797
8b953440
PB		 1798 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1799 &hv_clock.tsc_shift,
1800 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1801 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1802
1803 put_cpu();
1804
1805 return ret;
108b249c
PB		 1806}
1807
0d6dd2ff
PB		 1808static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1809{
1810 struct kvm_vcpu_arch *vcpu = &v->arch;
1811 struct pvclock_vcpu_time_info guest_hv_clock;
1812
4e335d9e 1813 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1814 &guest_hv_clock, sizeof(guest_hv_clock))))
1815 return;
1816
1817 /* This VCPU is paused, but it's legal for a guest to read another
1818 * VCPU's kvmclock, so we really have to follow the specification where
1819 * it says that version is odd if data is being modified, and even after
1820 * it is consistent.
1821 *
1822 * Version field updates must be kept separate. This is because
1823 * kvm_write_guest_cached might use a "rep movs" instruction, and
1824 * writes within a string instruction are weakly ordered. So there
1825 * are three writes overall.
1826 *
1827 * As a small optimization, only write the version field in the first
1828 * and third write. The vcpu->pv_time cache is still valid, because the
1829 * version field is the first in the struct.
1830 */
1831 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1832
1833 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1834 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1835 &vcpu->hv_clock,
1836 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1837
1838 smp_wmb();
1839
1840 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1841 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1842
1843 if (vcpu->pvclock_set_guest_stopped_request) {
1844 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1845 vcpu->pvclock_set_guest_stopped_request = false;
1846 }
1847
1848 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1849
4e335d9e
PB		 1850 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1851 &vcpu->hv_clock,
1852 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1853
1854 smp_wmb();
1855
1856 vcpu->hv_clock.version++;
4e335d9e
PB		 1857 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1858 &vcpu->hv_clock,
1859 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1860}
1861
34c238a1 1862static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1863{
78db6a50 1864 unsigned long flags, tgt_tsc_khz;
18068523 1865 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1866 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1867 s64 kernel_ns;
d828199e 1868 u64 tsc_timestamp, host_tsc;
51d59c6b 1869 u8 pvclock_flags;
d828199e
MT		 1870 bool use_master_clock;
1871
1872 kernel_ns = 0;
1873 host_tsc = 0;
18068523 1874
d828199e
MT		 1875 /*
1876 * If the host uses TSC clock, then passthrough TSC as stable
1877 * to the guest.
1878 */
1879 spin_lock(&ka->pvclock_gtod_sync_lock);
1880 use_master_clock = ka->use_master_clock;
1881 if (use_master_clock) {
1882 host_tsc = ka->master_cycle_now;
1883 kernel_ns = ka->master_kernel_ns;
1884 }
1885 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1886
1887 /* Keep irq disabled to prevent changes to the clock */
1888 local_irq_save(flags);
78db6a50
PB		 1889 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1890 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1891 local_irq_restore(flags);
1892 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1893 return 1;
1894 }
d828199e 1895 if (!use_master_clock) {
4ea1636b 1896 host_tsc = rdtsc();
108b249c 1897 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1898 }
1899
4ba76538 1900 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1901
c285545f
ZA		 1902 /*
1903 * We may have to catch up the TSC to match elapsed wall clock
1904 * time for two reasons, even if kvmclock is used.
1905 * 1) CPU could have been running below the maximum TSC rate
1906 * 2) Broken TSC compensation resets the base at each VCPU
1907 * entry to avoid unknown leaps of TSC even when running
1908 * again on the same CPU. This may cause apparent elapsed
1909 * time to disappear, and the guest to stand still or run
1910 * very slowly.
1911 */
1912 if (vcpu->tsc_catchup) {
1913 u64 tsc = compute_guest_tsc(v, kernel_ns);
1914 if (tsc > tsc_timestamp) {
f1e2b260 1915 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1916 tsc_timestamp = tsc;
1917 }
50d0a0f9
GH		 1918 }
1919
18068523
GOC		 1920 local_irq_restore(flags);
1921
0d6dd2ff 1922 /* With all the info we got, fill in the values */
18068523 1923
78db6a50
PB		 1924 if (kvm_has_tsc_control)
1925 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1926
1927 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1928 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1929 &vcpu->hv_clock.tsc_shift,
1930 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1931 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1932 }
1933
1d5f066e 1934 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1935 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1936 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1937
d828199e 1938 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1939 pvclock_flags = 0;
d828199e
MT		 1940 if (use_master_clock)
1941 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1942
78c0337a
MT		 1943 vcpu->hv_clock.flags = pvclock_flags;
1944
095cf55d
PB		 1945 if (vcpu->pv_time_enabled)
1946 kvm_setup_pvclock_page(v);
1947 if (v == kvm_get_vcpu(v->kvm, 0))
1948 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1949 return 0;
c8076604
GH		 1950}
1951
0061d53d
MT		 1952/*
1953 * kvmclock updates which are isolated to a given vcpu, such as
1954 * vcpu->cpu migration, should not allow system_timestamp from
1955 * the rest of the vcpus to remain static. Otherwise ntp frequency
1956 * correction applies to one vcpu's system_timestamp but not
1957 * the others.
1958 *
1959 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1960 * We need to rate-limit these requests though, as they can
1961 * considerably slow guests that have a large number of vcpus.
1962 * The time for a remote vcpu to update its kvmclock is bound
1963 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1964 */
1965
7e44e449
AJ		 1966#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1967
1968static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1969{
1970 int i;
7e44e449
AJ		 1971 struct delayed_work *dwork = to_delayed_work(work);
1972 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1973 kvmclock_update_work);
1974 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1975 struct kvm_vcpu *vcpu;
1976
1977 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1978 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1979 kvm_vcpu_kick(vcpu);
1980 }
1981}
1982
7e44e449
AJ		 1983static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1984{
1985 struct kvm *kvm = v->kvm;
1986
105b21bb 1987 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1988 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1989 KVMCLOCK_UPDATE_DELAY);
1990}
1991
332967a3
AJ		 1992#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1993
1994static void kvmclock_sync_fn(struct work_struct *work)
1995{
1996 struct delayed_work *dwork = to_delayed_work(work);
1997 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1998 kvmclock_sync_work);
1999 struct kvm *kvm = container_of(ka, struct kvm, arch);
2000
630994b3
MT		 2001 if (!kvmclock_periodic_sync)
2002 return;
2003
332967a3
AJ		 2004 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2005 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2006 KVMCLOCK_SYNC_PERIOD);
2007}
2008
890ca9ae 2009static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 2010{
890ca9ae
HY		 2011 u64 mcg_cap = vcpu->arch.mcg_cap;
2012 unsigned bank_num = mcg_cap & 0xff;
2013
15c4a640 2014 switch (msr) {
15c4a640 2015 case MSR_IA32_MCG_STATUS:
890ca9ae 2016 vcpu->arch.mcg_status = data;
15c4a640 2017 break;
c7ac679c 2018 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2019 if (!(mcg_cap & MCG_CTL_P))
2020 return 1;
2021 if (data != 0 && data != ~(u64)0)
2022 return -1;
2023 vcpu->arch.mcg_ctl = data;
2024 break;
2025 default:
2026 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2027 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2028 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2029 /* only 0 or all 1s can be written to IA32_MCi_CTL
2030 * some Linux kernels though clear bit 10 in bank 4 to
2031 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2032 * this to avoid an uncatched #GP in the guest
2033 */
890ca9ae 2034 if ((offset & 0x3) == 0 &&
114be429 2035 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2036 return -1;
2037 vcpu->arch.mce_banks[offset] = data;
2038 break;
2039 }
2040 return 1;
2041 }
2042 return 0;
2043}
2044
ffde22ac
ES		 2045static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2046{
2047 struct kvm *kvm = vcpu->kvm;
2048 int lm = is_long_mode(vcpu);
2049 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2050 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2051 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2052 : kvm->arch.xen_hvm_config.blob_size_32;
2053 u32 page_num = data & ~PAGE_MASK;
2054 u64 page_addr = data & PAGE_MASK;
2055 u8 *page;
2056 int r;
2057
2058 r = -E2BIG;
2059 if (page_num >= blob_size)
2060 goto out;
2061 r = -ENOMEM;
ff5c2c03
SL		 2062 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2063 if (IS_ERR(page)) {
2064 r = PTR_ERR(page);
ffde22ac 2065 goto out;
ff5c2c03 2066 }
54bf36aa 2067 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2068 goto out_free;
2069 r = 0;
2070out_free:
2071 kfree(page);
2072out:
2073 return r;
2074}
2075
344d9588
GN		 2076static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2077{
2078 gpa_t gpa = data & ~0x3f;
2079
52a5c155
WL		 2080 /* Bits 3:5 are reserved, Should be zero */
2081 if (data & 0x38)
344d9588
GN		 2082 return 1;
2083
2084 vcpu->arch.apf.msr_val = data;
2085
2086 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2087 kvm_clear_async_pf_completion_queue(vcpu);
2088 kvm_async_pf_hash_reset(vcpu);
2089 return 0;
2090 }
2091
4e335d9e 2092 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2093 sizeof(u32)))
344d9588
GN		 2094 return 1;
2095
6adba527 2096 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2097 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2098 kvm_async_pf_wakeup_all(vcpu);
2099 return 0;
2100}
2101
12f9a48f
GC		 2102static void kvmclock_reset(struct kvm_vcpu *vcpu)
2103{
0b79459b 2104 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2105}
2106
c9aaa895
GC		 2107static void record_steal_time(struct kvm_vcpu *vcpu)
2108{
2109 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2110 return;
2111
4e335d9e 2112 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2113 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2114 return;
2115
0b9f6c46
PX		 2116 vcpu->arch.st.steal.preempted = 0;
2117
35f3fae1
WL		 2118 if (vcpu->arch.st.steal.version & 1)
2119 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2120
2121 vcpu->arch.st.steal.version += 1;
2122
4e335d9e 2123 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2124 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2125
2126 smp_wmb();
2127
c54cdf14
LC		 2128 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2129 vcpu->arch.st.last_steal;
2130 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2131
4e335d9e 2132 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2133 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2134
2135 smp_wmb();
2136
2137 vcpu->arch.st.steal.version += 1;
c9aaa895 2138
4e335d9e 2139 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2140 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2141}
2142
8fe8ab46 2143int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2144{
5753785f 2145 bool pr = false;
8fe8ab46
WA		 2146 u32 msr = msr_info->index;
2147 u64 data = msr_info->data;
5753785f 2148
15c4a640 2149 switch (msr) {
2e32b719
BP		 2150 case MSR_AMD64_NB_CFG:
2151 case MSR_IA32_UCODE_REV:
2152 case MSR_IA32_UCODE_WRITE:
2153 case MSR_VM_HSAVE_PA:
2154 case MSR_AMD64_PATCH_LOADER:
2155 case MSR_AMD64_BU_CFG2:
405a353a 2156 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2157 break;
2158
15c4a640 2159 case MSR_EFER:
b69e8cae 2160 return set_efer(vcpu, data);
8f1589d9
AP		 2161 case MSR_K7_HWCR:
2162 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2163 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2164 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2165 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2166 if (data != 0) {
a737f256
CD		 2167 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2168 data);
8f1589d9
AP		 2169 return 1;
2170 }
15c4a640 2171 break;
f7c6d140
AP		 2172 case MSR_FAM10H_MMIO_CONF_BASE:
2173 if (data != 0) {
a737f256
CD		 2174 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2175 "0x%llx\n", data);
f7c6d140
AP		 2176 return 1;
2177 }
15c4a640 2178 break;
b5e2fec0
AG		 2179 case MSR_IA32_DEBUGCTLMSR:
2180 if (!data) {
2181 /* We support the non-activated case already */
2182 break;
2183 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2184 /* Values other than LBR and BTF are vendor-specific,
2185 thus reserved and should throw a #GP */
2186 return 1;
2187 }
a737f256
CD		 2188 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2189 __func__, data);
b5e2fec0 2190 break;
9ba075a6 2191 case 0x200 ... 0x2ff:
ff53604b 2192 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2193 case MSR_IA32_APICBASE:
58cb628d 2194 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2195 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2196 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2197 case MSR_IA32_TSCDEADLINE:
2198 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2199 break;
ba904635 2200 case MSR_IA32_TSC_ADJUST:
d6321d49 2201 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2202 if (!msr_info->host_initiated) {
d913b904 2203 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2204 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2205 }
2206 vcpu->arch.ia32_tsc_adjust_msr = data;
2207 }
2208 break;
15c4a640 2209 case MSR_IA32_MISC_ENABLE:
ad312c7c 2210 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2211 break;
64d60670
PB		 2212 case MSR_IA32_SMBASE:
2213 if (!msr_info->host_initiated)
2214 return 1;
2215 vcpu->arch.smbase = data;
2216 break;
11c6bffa 2217 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2218 case MSR_KVM_WALL_CLOCK:
2219 vcpu->kvm->arch.wall_clock = data;
2220 kvm_write_wall_clock(vcpu->kvm, data);
2221 break;
11c6bffa 2222 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2223 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2224 struct kvm_arch *ka = &vcpu->kvm->arch;
2225
12f9a48f 2226 kvmclock_reset(vcpu);
18068523 2227
54750f2c
MT		 2228 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2229 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2230
2231 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2232 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2233
2234 ka->boot_vcpu_runs_old_kvmclock = tmp;
2235 }
2236
18068523 2237 vcpu->arch.time = data;
0061d53d 2238 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2239
2240 /* we verify if the enable bit is set... */
2241 if (!(data & 1))
2242 break;
2243
4e335d9e 2244 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2245 &vcpu->arch.pv_time, data & ~1ULL,
2246 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2247 vcpu->arch.pv_time_enabled = false;
2248 else
2249 vcpu->arch.pv_time_enabled = true;
32cad84f 2250
18068523
GOC		 2251 break;
2252 }
344d9588
GN		 2253 case MSR_KVM_ASYNC_PF_EN:
2254 if (kvm_pv_enable_async_pf(vcpu, data))
2255 return 1;
2256 break;
c9aaa895
GC		 2257 case MSR_KVM_STEAL_TIME:
2258
2259 if (unlikely(!sched_info_on()))
2260 return 1;
2261
2262 if (data & KVM_STEAL_RESERVED_MASK)
2263 return 1;
2264
4e335d9e 2265 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2266 data & KVM_STEAL_VALID_BITS,
2267 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2268 return 1;
2269
2270 vcpu->arch.st.msr_val = data;
2271
2272 if (!(data & KVM_MSR_ENABLED))
2273 break;
2274
c9aaa895
GC		 2275 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2276
2277 break;
ae7a2a3f
MT		 2278 case MSR_KVM_PV_EOI_EN:
2279 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2280 return 1;
2281 break;
c9aaa895 2282
890ca9ae
HY		 2283 case MSR_IA32_MCG_CTL:
2284 case MSR_IA32_MCG_STATUS:
81760dcc 2285 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2286 return set_msr_mce(vcpu, msr, data);
71db6023 2287
6912ac32
WH		 2288 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2289 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2290 pr = true; /* fall through */
2291 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2292 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2293 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2294 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2295
2296 if (pr || data != 0)
a737f256
CD		 2297 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2298 "0x%x data 0x%llx\n", msr, data);
5753785f 2299 break;
84e0cefa
JS		 2300 case MSR_K7_CLK_CTL:
2301 /*
2302 * Ignore all writes to this no longer documented MSR.
2303 * Writes are only relevant for old K7 processors,
2304 * all pre-dating SVM, but a recommended workaround from
4a969980 2305 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2306 * affected processor models on the command line, hence
2307 * the need to ignore the workaround.
2308 */
2309 break;
55cd8e5a 2310 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2311 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2312 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2313 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2314 return kvm_hv_set_msr_common(vcpu, msr, data,
2315 msr_info->host_initiated);
91c9c3ed 2316 case MSR_IA32_BBL_CR_CTL3:
2317 /* Drop writes to this legacy MSR -- see rdmsr
2318 * counterpart for further detail.
2319 */
796f4687 2320 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2321 break;
2b036c6b 2322 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2323 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2324 return 1;
2325 vcpu->arch.osvw.length = data;
2326 break;
2327 case MSR_AMD64_OSVW_STATUS:
d6321d49 2328 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2329 return 1;
2330 vcpu->arch.osvw.status = data;
2331 break;
db2336a8
KH		 2332 case MSR_PLATFORM_INFO:
2333 if (!msr_info->host_initiated ||
2334 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2335 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2336 cpuid_fault_enabled(vcpu)))
2337 return 1;
2338 vcpu->arch.msr_platform_info = data;
2339 break;
2340 case MSR_MISC_FEATURES_ENABLES:
2341 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2342 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2343 !supports_cpuid_fault(vcpu)))
2344 return 1;
2345 vcpu->arch.msr_misc_features_enables = data;
2346 break;
15c4a640 2347 default:
ffde22ac
ES		 2348 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2349 return xen_hvm_config(vcpu, data);
c6702c9d 2350 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2351 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2352 if (!ignore_msrs) {
ae0f5499 2353 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2354 msr, data);
ed85c068
AP		 2355 return 1;
2356 } else {
796f4687 2357 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2358 msr, data);
ed85c068
AP		 2359 break;
2360 }
15c4a640
CO		 2361 }
2362 return 0;
2363}
2364EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2365
2366
2367/*
2368 * Reads an msr value (of 'msr_index') into 'pdata'.
2369 * Returns 0 on success, non-0 otherwise.
2370 * Assumes vcpu_load() was already called.
2371 */
609e36d3 2372int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2373{
609e36d3 2374 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2375}
ff651cb6 2376EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2377
890ca9ae 2378static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2379{
2380 u64 data;
890ca9ae
HY		 2381 u64 mcg_cap = vcpu->arch.mcg_cap;
2382 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2383
2384 switch (msr) {
15c4a640
CO		 2385 case MSR_IA32_P5_MC_ADDR:
2386 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2387 data = 0;
2388 break;
15c4a640 2389 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2390 data = vcpu->arch.mcg_cap;
2391 break;
c7ac679c 2392 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2393 if (!(mcg_cap & MCG_CTL_P))
2394 return 1;
2395 data = vcpu->arch.mcg_ctl;
2396 break;
2397 case MSR_IA32_MCG_STATUS:
2398 data = vcpu->arch.mcg_status;
2399 break;
2400 default:
2401 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2402 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2403 u32 offset = msr - MSR_IA32_MC0_CTL;
2404 data = vcpu->arch.mce_banks[offset];
2405 break;
2406 }
2407 return 1;
2408 }
2409 *pdata = data;
2410 return 0;
2411}
2412
609e36d3 2413int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2414{
609e36d3 2415 switch (msr_info->index) {
890ca9ae 2416 case MSR_IA32_PLATFORM_ID:
15c4a640 2417 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2418 case MSR_IA32_DEBUGCTLMSR:
2419 case MSR_IA32_LASTBRANCHFROMIP:
2420 case MSR_IA32_LASTBRANCHTOIP:
2421 case MSR_IA32_LASTINTFROMIP:
2422 case MSR_IA32_LASTINTTOIP:
60af2ecd 2423 case MSR_K8_SYSCFG:
3afb1121
PB		 2424 case MSR_K8_TSEG_ADDR:
2425 case MSR_K8_TSEG_MASK:
60af2ecd 2426 case MSR_K7_HWCR:
61a6bd67 2427 case MSR_VM_HSAVE_PA:
1fdbd48c 2428 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2429 case MSR_AMD64_NB_CFG:
f7c6d140 2430 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2431 case MSR_AMD64_BU_CFG2:
0c2df2a1 2432 case MSR_IA32_PERF_CTL:
405a353a 2433 case MSR_AMD64_DC_CFG:
609e36d3 2434 msr_info->data = 0;
15c4a640 2435 break;
6912ac32
WH		 2436 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2437 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2438 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2439 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2440 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2441 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2442 msr_info->data = 0;
5753785f 2443 break;
742bc670 2444 case MSR_IA32_UCODE_REV:
609e36d3 2445 msr_info->data = 0x100000000ULL;
742bc670 2446 break;
9ba075a6 2447 case MSR_MTRRcap:
9ba075a6 2448 case 0x200 ... 0x2ff:
ff53604b 2449 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2450 case 0xcd: /* fsb frequency */
609e36d3 2451 msr_info->data = 3;
15c4a640 2452 break;
7b914098
JS		 2453 /*
2454 * MSR_EBC_FREQUENCY_ID
2455 * Conservative value valid for even the basic CPU models.
2456 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2457 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2458 * and 266MHz for model 3, or 4. Set Core Clock
2459 * Frequency to System Bus Frequency Ratio to 1 (bits
2460 * 31:24) even though these are only valid for CPU
2461 * models > 2, however guests may end up dividing or
2462 * multiplying by zero otherwise.
2463 */
2464 case MSR_EBC_FREQUENCY_ID:
609e36d3 2465 msr_info->data = 1 << 24;
7b914098 2466 break;
15c4a640 2467 case MSR_IA32_APICBASE:
609e36d3 2468 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2469 break;
0105d1a5 2470 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2471 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2472 break;
a3e06bbe 2473 case MSR_IA32_TSCDEADLINE:
609e36d3 2474 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2475 break;
ba904635 2476 case MSR_IA32_TSC_ADJUST:
609e36d3 2477 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2478 break;
15c4a640 2479 case MSR_IA32_MISC_ENABLE:
609e36d3 2480 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2481 break;
64d60670
PB		 2482 case MSR_IA32_SMBASE:
2483 if (!msr_info->host_initiated)
2484 return 1;
2485 msr_info->data = vcpu->arch.smbase;
15c4a640 2486 break;
847f0ad8
AG		 2487 case MSR_IA32_PERF_STATUS:
2488 /* TSC increment by tick */
609e36d3 2489 msr_info->data = 1000ULL;
847f0ad8 2490 /* CPU multiplier */
b0996ae4 2491 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2492 break;
15c4a640 2493 case MSR_EFER:
609e36d3 2494 msr_info->data = vcpu->arch.efer;
15c4a640 2495 break;
18068523 2496 case MSR_KVM_WALL_CLOCK:
11c6bffa 2497 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2498 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2499 break;
2500 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2501 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2502 msr_info->data = vcpu->arch.time;
18068523 2503 break;
344d9588 2504 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2505 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2506 break;
c9aaa895 2507 case MSR_KVM_STEAL_TIME:
609e36d3 2508 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2509 break;
1d92128f 2510 case MSR_KVM_PV_EOI_EN:
609e36d3 2511 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2512 break;
890ca9ae
HY		 2513 case MSR_IA32_P5_MC_ADDR:
2514 case MSR_IA32_P5_MC_TYPE:
2515 case MSR_IA32_MCG_CAP:
2516 case MSR_IA32_MCG_CTL:
2517 case MSR_IA32_MCG_STATUS:
81760dcc 2518 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2519 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2520 case MSR_K7_CLK_CTL:
2521 /*
2522 * Provide expected ramp-up count for K7. All other
2523 * are set to zero, indicating minimum divisors for
2524 * every field.
2525 *
2526 * This prevents guest kernels on AMD host with CPU
2527 * type 6, model 8 and higher from exploding due to
2528 * the rdmsr failing.
2529 */
609e36d3 2530 msr_info->data = 0x20000000;
84e0cefa 2531 break;
55cd8e5a 2532 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2533 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2534 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2535 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2536 return kvm_hv_get_msr_common(vcpu,
2537 msr_info->index, &msr_info->data);
55cd8e5a 2538 break;
91c9c3ed 2539 case MSR_IA32_BBL_CR_CTL3:
2540 /* This legacy MSR exists but isn't fully documented in current
2541 * silicon. It is however accessed by winxp in very narrow
2542 * scenarios where it sets bit #19, itself documented as
2543 * a "reserved" bit. Best effort attempt to source coherent
2544 * read data here should the balance of the register be
2545 * interpreted by the guest:
2546 *
2547 * L2 cache control register 3: 64GB range, 256KB size,
2548 * enabled, latency 0x1, configured
2549 */
609e36d3 2550 msr_info->data = 0xbe702111;
91c9c3ed 2551 break;
2b036c6b 2552 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2553 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2554 return 1;
609e36d3 2555 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2556 break;
2557 case MSR_AMD64_OSVW_STATUS:
d6321d49 2558 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2559 return 1;
609e36d3 2560 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2561 break;
db2336a8
KH		 2562 case MSR_PLATFORM_INFO:
2563 msr_info->data = vcpu->arch.msr_platform_info;
2564 break;
2565 case MSR_MISC_FEATURES_ENABLES:
2566 msr_info->data = vcpu->arch.msr_misc_features_enables;
2567 break;
15c4a640 2568 default:
c6702c9d 2569 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2570 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2571 if (!ignore_msrs) {
ae0f5499
BD		 2572 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2573 msr_info->index);
ed85c068
AP		 2574 return 1;
2575 } else {
609e36d3
PB		 2576 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2577 msr_info->data = 0;
ed85c068
AP		 2578 }
2579 break;
15c4a640 2580 }
15c4a640
CO		 2581 return 0;
2582}
2583EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2584
313a3dc7
CO		 2585/*
2586 * Read or write a bunch of msrs. All parameters are kernel addresses.
2587 *
2588 * @return number of msrs set successfully.
2589 */
2590static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2591 struct kvm_msr_entry *entries,
2592 int (*do_msr)(struct kvm_vcpu *vcpu,
2593 unsigned index, u64 *data))
2594{
f656ce01 2595 int i, idx;
313a3dc7 2596
f656ce01 2597 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2598 for (i = 0; i < msrs->nmsrs; ++i)
2599 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2600 break;
f656ce01 2601 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2602
313a3dc7
CO		 2603 return i;
2604}
2605
2606/*
2607 * Read or write a bunch of msrs. Parameters are user addresses.
2608 *
2609 * @return number of msrs set successfully.
2610 */
2611static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2612 int (*do_msr)(struct kvm_vcpu *vcpu,
2613 unsigned index, u64 *data),
2614 int writeback)
2615{
2616 struct kvm_msrs msrs;
2617 struct kvm_msr_entry *entries;
2618 int r, n;
2619 unsigned size;
2620
2621 r = -EFAULT;
2622 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2623 goto out;
2624
2625 r = -E2BIG;
2626 if (msrs.nmsrs >= MAX_IO_MSRS)
2627 goto out;
2628
313a3dc7 2629 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2630 entries = memdup_user(user_msrs->entries, size);
2631 if (IS_ERR(entries)) {
2632 r = PTR_ERR(entries);
313a3dc7 2633 goto out;
ff5c2c03 2634 }
313a3dc7
CO		 2635
2636 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2637 if (r < 0)
2638 goto out_free;
2639
2640 r = -EFAULT;
2641 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2642 goto out_free;
2643
2644 r = n;
2645
2646out_free:
7a73c028 2647 kfree(entries);
313a3dc7
CO		 2648out:
2649 return r;
2650}
2651
784aa3d7 2652int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2653{
2654 int r;
2655
2656 switch (ext) {
2657 case KVM_CAP_IRQCHIP:
2658 case KVM_CAP_HLT:
2659 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2660 case KVM_CAP_SET_TSS_ADDR:
07716717 2661 case KVM_CAP_EXT_CPUID:
9c15bb1d 2662 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2663 case KVM_CAP_CLOCKSOURCE:
7837699f 2664 case KVM_CAP_PIT:
a28e4f5a 2665 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2666 case KVM_CAP_MP_STATE:
ed848624 2667 case KVM_CAP_SYNC_MMU:
a355c85c 2668 case KVM_CAP_USER_NMI:
52d939a0 2669 case KVM_CAP_REINJECT_CONTROL:
4925663a 2670 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2671 case KVM_CAP_IOEVENTFD:
f848a5a8 2672 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2673 case KVM_CAP_PIT2:
e9f42757 2674 case KVM_CAP_PIT_STATE2:
b927a3ce 2675 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2676 case KVM_CAP_XEN_HVM:
3cfc3092 2677 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2678 case KVM_CAP_HYPERV:
10388a07 2679 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2680 case KVM_CAP_HYPERV_SPIN:
5c919412 2681 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2682 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2683 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2684 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2685 case KVM_CAP_DEBUGREGS:
d2be1651 2686 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2687 case KVM_CAP_XSAVE:
344d9588 2688 case KVM_CAP_ASYNC_PF:
92a1f12d 2689 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2690 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2691 case KVM_CAP_READONLY_MEM:
5f66b620 2692 case KVM_CAP_HYPERV_TIME:
100943c5 2693 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2694 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2695 case KVM_CAP_ENABLE_CAP_VM:
2696 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2697 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2698 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2699 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2700 r = 1;
2701 break;
e3fd9a93
PB		 2702 case KVM_CAP_ADJUST_CLOCK:
2703 r = KVM_CLOCK_TSC_STABLE;
2704 break;
668fffa3
MT		 2705 case KVM_CAP_X86_GUEST_MWAIT:
2706 r = kvm_mwait_in_guest();
2707 break;
6d396b55
PB		 2708 case KVM_CAP_X86_SMM:
2709 /* SMBASE is usually relocated above 1M on modern chipsets,
2710 * and SMM handlers might indeed rely on 4G segment limits,
2711 * so do not report SMM to be available if real mode is
2712 * emulated via vm86 mode. Still, do not go to great lengths
2713 * to avoid userspace's usage of the feature, because it is a
2714 * fringe case that is not enabled except via specific settings
2715 * of the module parameters.
2716 */
2717 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2718 break;
774ead3a
AK		 2719 case KVM_CAP_VAPIC:
2720 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2721 break;
f725230a 2722 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2723 r = KVM_SOFT_MAX_VCPUS;
2724 break;
2725 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2726 r = KVM_MAX_VCPUS;
2727 break;
a988b910 2728 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2729 r = KVM_USER_MEM_SLOTS;
a988b910 2730 break;
a68a6a72
MT		 2731 case KVM_CAP_PV_MMU: /* obsolete */
2732 r = 0;
2f333bcb 2733 break;
890ca9ae
HY		 2734 case KVM_CAP_MCE:
2735 r = KVM_MAX_MCE_BANKS;
2736 break;
2d5b5a66 2737 case KVM_CAP_XCRS:
d366bf7e 2738 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2739 break;
92a1f12d
JR		 2740 case KVM_CAP_TSC_CONTROL:
2741 r = kvm_has_tsc_control;
2742 break;
37131313
RK		 2743 case KVM_CAP_X2APIC_API:
2744 r = KVM_X2APIC_API_VALID_FLAGS;
2745 break;
018d00d2
ZX		 2746 default:
2747 r = 0;
2748 break;
2749 }
2750 return r;
2751
2752}
2753
043405e1
CO		 2754long kvm_arch_dev_ioctl(struct file *filp,
2755 unsigned int ioctl, unsigned long arg)
2756{
2757 void __user *argp = (void __user *)arg;
2758 long r;
2759
2760 switch (ioctl) {
2761 case KVM_GET_MSR_INDEX_LIST: {
2762 struct kvm_msr_list __user *user_msr_list = argp;
2763 struct kvm_msr_list msr_list;
2764 unsigned n;
2765
2766 r = -EFAULT;
2767 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2768 goto out;
2769 n = msr_list.nmsrs;
62ef68bb 2770 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2771 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2772 goto out;
2773 r = -E2BIG;
e125e7b6 2774 if (n < msr_list.nmsrs)
043405e1
CO		 2775 goto out;
2776 r = -EFAULT;
2777 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2778 num_msrs_to_save * sizeof(u32)))
2779 goto out;
e125e7b6 2780 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2781 &emulated_msrs,
62ef68bb 2782 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2783 goto out;
2784 r = 0;
2785 break;
2786 }
9c15bb1d
BP		 2787 case KVM_GET_SUPPORTED_CPUID:
2788 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2789 struct kvm_cpuid2 __user *cpuid_arg = argp;
2790 struct kvm_cpuid2 cpuid;
2791
2792 r = -EFAULT;
2793 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2794 goto out;
9c15bb1d
BP		 2795
2796 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2797 ioctl);
674eea0f
AK		 2798 if (r)
2799 goto out;
2800
2801 r = -EFAULT;
2802 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2803 goto out;
2804 r = 0;
2805 break;
2806 }
890ca9ae 2807 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2808 r = -EFAULT;
c45dcc71
AR		 2809 if (copy_to_user(argp, &kvm_mce_cap_supported,
2810 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2811 goto out;
2812 r = 0;
2813 break;
2814 }
043405e1
CO		 2815 default:
2816 r = -EINVAL;
2817 }
2818out:
2819 return r;
2820}
2821
f5f48ee1
SY		 2822static void wbinvd_ipi(void *garbage)
2823{
2824 wbinvd();
2825}
2826
2827static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2828{
e0f0bbc5 2829 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2830}
2831
313a3dc7
CO		 2832void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2833{
f5f48ee1
SY		 2834 /* Address WBINVD may be executed by guest */
2835 if (need_emulate_wbinvd(vcpu)) {
2836 if (kvm_x86_ops->has_wbinvd_exit())
2837 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2838 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2839 smp_call_function_single(vcpu->cpu,
2840 wbinvd_ipi, NULL, 1);
2841 }
2842
313a3dc7 2843 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2844
0dd6a6ed
ZA		 2845 /* Apply any externally detected TSC adjustments (due to suspend) */
2846 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2847 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2848 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2849 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2850 }
8f6055cb 2851
48434c20 2852 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2853 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2854 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2855 if (tsc_delta < 0)
2856 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2857
c285545f 2858 if (check_tsc_unstable()) {
07c1419a 2859 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2860 vcpu->arch.last_guest_tsc);
a545ab6a 2861 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2862 vcpu->arch.tsc_catchup = 1;
c285545f 2863 }
a749e247
PB		 2864
2865 if (kvm_lapic_hv_timer_in_use(vcpu))
2866 kvm_lapic_restart_hv_timer(vcpu);
2867
d98d07ca
MT		 2868 /*
2869 * On a host with synchronized TSC, there is no need to update
2870 * kvmclock on vcpu->cpu migration
2871 */
2872 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2873 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2874 if (vcpu->cpu != cpu)
1bd2009e 2875 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2876 vcpu->cpu = cpu;
6b7d7e76 2877 }
c9aaa895 2878
c9aaa895 2879 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2880}
2881
0b9f6c46
PX		 2882static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2883{
2884 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2885 return;
2886
2887 vcpu->arch.st.steal.preempted = 1;
2888
4e335d9e 2889 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2890 &vcpu->arch.st.steal.preempted,
2891 offsetof(struct kvm_steal_time, preempted),
2892 sizeof(vcpu->arch.st.steal.preempted));
2893}
2894
313a3dc7
CO		 2895void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2896{
cc0d907c 2897 int idx;
de63ad4c
LM		 2898
2899 if (vcpu->preempted)
2900 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2901
931f261b
AA		 2902 /*
2903 * Disable page faults because we're in atomic context here.
2904 * kvm_write_guest_offset_cached() would call might_fault()
2905 * that relies on pagefault_disable() to tell if there's a
2906 * bug. NOTE: the write to guest memory may not go through if
2907 * during postcopy live migration or if there's heavy guest
2908 * paging.
2909 */
2910 pagefault_disable();
cc0d907c
AA		 2911 /*
2912 * kvm_memslots() will be called by
2913 * kvm_write_guest_offset_cached() so take the srcu lock.
2914 */
2915 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2916 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2917 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2918 pagefault_enable();
02daab21 2919 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2920 kvm_put_guest_fpu(vcpu);
4ea1636b 2921 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2922}
2923
313a3dc7
CO		 2924static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2925 struct kvm_lapic_state *s)
2926{
76dfafd5 2927 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2928 kvm_x86_ops->sync_pir_to_irr(vcpu);
2929
a92e2543 2930 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2931}
2932
2933static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2934 struct kvm_lapic_state *s)
2935{
a92e2543
RK		 2936 int r;
2937
2938 r = kvm_apic_set_state(vcpu, s);
2939 if (r)
2940 return r;
cb142eb7 2941 update_cr8_intercept(vcpu);
313a3dc7
CO		 2942
2943 return 0;
2944}
2945
127a457a
MG		 2946static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2947{
2948 return (!lapic_in_kernel(vcpu) ||
2949 kvm_apic_accept_pic_intr(vcpu));
2950}
2951
782d422b
MG		 2952/*
2953 * if userspace requested an interrupt window, check that the
2954 * interrupt window is open.
2955 *
2956 * No need to exit to userspace if we already have an interrupt queued.
2957 */
2958static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2959{
2960 return kvm_arch_interrupt_allowed(vcpu) &&
2961 !kvm_cpu_has_interrupt(vcpu) &&
2962 !kvm_event_needs_reinjection(vcpu) &&
2963 kvm_cpu_accept_dm_intr(vcpu);
2964}
2965
f77bc6a4
ZX		 2966static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2967 struct kvm_interrupt *irq)
2968{
02cdb50f 2969 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2970 return -EINVAL;
1c1a9ce9
SR		 2971
2972 if (!irqchip_in_kernel(vcpu->kvm)) {
2973 kvm_queue_interrupt(vcpu, irq->irq, false);
2974 kvm_make_request(KVM_REQ_EVENT, vcpu);
2975 return 0;
2976 }
2977
2978 /*
2979 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2980 * fail for in-kernel 8259.
2981 */
2982 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2983 return -ENXIO;
f77bc6a4 2984
1c1a9ce9
SR		 2985 if (vcpu->arch.pending_external_vector != -1)
2986 return -EEXIST;
f77bc6a4 2987
1c1a9ce9 2988 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2989 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2990 return 0;
2991}
2992
c4abb7c9
JK		 2993static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2994{
c4abb7c9 2995 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2996
2997 return 0;
2998}
2999
f077825a
PB		 3000static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3001{
64d60670
PB		 3002 kvm_make_request(KVM_REQ_SMI, vcpu);
3003
f077825a
PB		 3004 return 0;
3005}
3006
b209749f
AK		 3007static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3008 struct kvm_tpr_access_ctl *tac)
3009{
3010 if (tac->flags)
3011 return -EINVAL;
3012 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3013 return 0;
3014}
3015
890ca9ae
HY		 3016static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3017 u64 mcg_cap)
3018{
3019 int r;
3020 unsigned bank_num = mcg_cap & 0xff, bank;
3021
3022 r = -EINVAL;
a9e38c3e 3023 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3024 goto out;
c45dcc71 3025 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3026 goto out;
3027 r = 0;
3028 vcpu->arch.mcg_cap = mcg_cap;
3029 /* Init IA32_MCG_CTL to all 1s */
3030 if (mcg_cap & MCG_CTL_P)
3031 vcpu->arch.mcg_ctl = ~(u64)0;
3032 /* Init IA32_MCi_CTL to all 1s */
3033 for (bank = 0; bank < bank_num; bank++)
3034 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3035
3036 if (kvm_x86_ops->setup_mce)
3037 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3038out:
3039 return r;
3040}
3041
3042static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3043 struct kvm_x86_mce *mce)
3044{
3045 u64 mcg_cap = vcpu->arch.mcg_cap;
3046 unsigned bank_num = mcg_cap & 0xff;
3047 u64 *banks = vcpu->arch.mce_banks;
3048
3049 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3050 return -EINVAL;
3051 /*
3052 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3053 * reporting is disabled
3054 */
3055 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3056 vcpu->arch.mcg_ctl != ~(u64)0)
3057 return 0;
3058 banks += 4 * mce->bank;
3059 /*
3060 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3061 * reporting is disabled for the bank
3062 */
3063 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3064 return 0;
3065 if (mce->status & MCI_STATUS_UC) {
3066 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3067 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3068 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3069 return 0;
3070 }
3071 if (banks[1] & MCI_STATUS_VAL)
3072 mce->status |= MCI_STATUS_OVER;
3073 banks[2] = mce->addr;
3074 banks[3] = mce->misc;
3075 vcpu->arch.mcg_status = mce->mcg_status;
3076 banks[1] = mce->status;
3077 kvm_queue_exception(vcpu, MC_VECTOR);
3078 } else if (!(banks[1] & MCI_STATUS_VAL)
3079 || !(banks[1] & MCI_STATUS_UC)) {
3080 if (banks[1] & MCI_STATUS_VAL)
3081 mce->status |= MCI_STATUS_OVER;
3082 banks[2] = mce->addr;
3083 banks[3] = mce->misc;
3084 banks[1] = mce->status;
3085 } else
3086 banks[1] |= MCI_STATUS_OVER;
3087 return 0;
3088}
3089
3cfc3092
JK		 3090static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3091 struct kvm_vcpu_events *events)
3092{
7460fb4a 3093 process_nmi(vcpu);
664f8e26
WL		 3094 /*
3095 * FIXME: pass injected and pending separately. This is only
3096 * needed for nested virtualization, whose state cannot be
3097 * migrated yet. For now we can combine them.
3098 */
03b82a30 3099 events->exception.injected =
664f8e26
WL		 3100 (vcpu->arch.exception.pending ||
3101 vcpu->arch.exception.injected) &&
03b82a30 3102 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3103 events->exception.nr = vcpu->arch.exception.nr;
3104 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3105 events->exception.pad = 0;
3cfc3092
JK		 3106 events->exception.error_code = vcpu->arch.exception.error_code;
3107
03b82a30
JK		 3108 events->interrupt.injected =
3109 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3110 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3111 events->interrupt.soft = 0;
37ccdcbe 3112 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3113
3114 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3115 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3116 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3117 events->nmi.pad = 0;
3cfc3092 3118
66450a21 3119 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3120
f077825a
PB		 3121 events->smi.smm = is_smm(vcpu);
3122 events->smi.pending = vcpu->arch.smi_pending;
3123 events->smi.smm_inside_nmi =
3124 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3125 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3126
dab4b911 3127 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3128 | KVM_VCPUEVENT_VALID_SHADOW
3129 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3130 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3131}
3132
6ef4e07e
XG		 3133static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3134
3cfc3092
JK		 3135static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3136 struct kvm_vcpu_events *events)
3137{
dab4b911 3138 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3139 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3140 | KVM_VCPUEVENT_VALID_SHADOW
3141 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3142 return -EINVAL;
3143
78e546c8 3144 if (events->exception.injected &&
28d06353
JM		 3145 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3146 is_guest_mode(vcpu)))
78e546c8
PB		 3147 return -EINVAL;
3148
28bf2888
DH		 3149 /* INITs are latched while in SMM */
3150 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3151 (events->smi.smm || events->smi.pending) &&
3152 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3153 return -EINVAL;
3154
7460fb4a 3155 process_nmi(vcpu);
664f8e26 3156 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3157 vcpu->arch.exception.pending = events->exception.injected;
3158 vcpu->arch.exception.nr = events->exception.nr;
3159 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3160 vcpu->arch.exception.error_code = events->exception.error_code;
3161
3162 vcpu->arch.interrupt.pending = events->interrupt.injected;
3163 vcpu->arch.interrupt.nr = events->interrupt.nr;
3164 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3165 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3166 kvm_x86_ops->set_interrupt_shadow(vcpu,
3167 events->interrupt.shadow);
3cfc3092
JK		 3168
3169 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3170 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3171 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3172 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3173
66450a21 3174 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3175 lapic_in_kernel(vcpu))
66450a21 3176 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3177
f077825a 3178 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3179 u32 hflags = vcpu->arch.hflags;
f077825a 3180 if (events->smi.smm)
6ef4e07e 3181 hflags |= HF_SMM_MASK;
f077825a 3182 else
6ef4e07e
XG		 3183 hflags &= ~HF_SMM_MASK;
3184 kvm_set_hflags(vcpu, hflags);
3185
f077825a 3186 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3187
3188 if (events->smi.smm) {
3189 if (events->smi.smm_inside_nmi)
3190 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3191 else
f4ef1910
WL		 3192 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3193 if (lapic_in_kernel(vcpu)) {
3194 if (events->smi.latched_init)
3195 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3196 else
3197 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3198 }
f077825a
PB		 3199 }
3200 }
3201
3842d135
AK		 3202 kvm_make_request(KVM_REQ_EVENT, vcpu);
3203
3cfc3092
JK		 3204 return 0;
3205}
3206
a1efbe77
JK		 3207static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3208 struct kvm_debugregs *dbgregs)
3209{
73aaf249
JK		 3210 unsigned long val;
3211
a1efbe77 3212 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3213 kvm_get_dr(vcpu, 6, &val);
73aaf249 3214 dbgregs->dr6 = val;
a1efbe77
JK		 3215 dbgregs->dr7 = vcpu->arch.dr7;
3216 dbgregs->flags = 0;
97e69aa6 3217 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3218}
3219
3220static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3221 struct kvm_debugregs *dbgregs)
3222{
3223 if (dbgregs->flags)
3224 return -EINVAL;
3225
d14bdb55
PB		 3226 if (dbgregs->dr6 & ~0xffffffffull)
3227 return -EINVAL;
3228 if (dbgregs->dr7 & ~0xffffffffull)
3229 return -EINVAL;
3230
a1efbe77 3231 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3232 kvm_update_dr0123(vcpu);
a1efbe77 3233 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3234 kvm_update_dr6(vcpu);
a1efbe77 3235 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3236 kvm_update_dr7(vcpu);
a1efbe77 3237
a1efbe77
JK		 3238 return 0;
3239}
3240
df1daba7
PB		 3241#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3242
3243static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3244{
c47ada30 3245 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3246 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3247 u64 valid;
3248
3249 /*
3250 * Copy legacy XSAVE area, to avoid complications with CPUID
3251 * leaves 0 and 1 in the loop below.
3252 */
3253 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3254
3255 /* Set XSTATE_BV */
00c87e9a 3256 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3257 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3258
3259 /*
3260 * Copy each region from the possibly compacted offset to the
3261 * non-compacted offset.
3262 */
d91cab78 3263 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3264 while (valid) {
3265 u64 feature = valid & -valid;
3266 int index = fls64(feature) - 1;
3267 void *src = get_xsave_addr(xsave, feature);
3268
3269 if (src) {
3270 u32 size, offset, ecx, edx;
3271 cpuid_count(XSTATE_CPUID, index,
3272 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3273 if (feature == XFEATURE_MASK_PKRU)
3274 memcpy(dest + offset, &vcpu->arch.pkru,
3275 sizeof(vcpu->arch.pkru));
3276 else
3277 memcpy(dest + offset, src, size);
3278
df1daba7
PB		 3279 }
3280
3281 valid -= feature;
3282 }
3283}
3284
3285static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3286{
c47ada30 3287 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3288 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3289 u64 valid;
3290
3291 /*
3292 * Copy legacy XSAVE area, to avoid complications with CPUID
3293 * leaves 0 and 1 in the loop below.
3294 */
3295 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3296
3297 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3298 xsave->header.xfeatures = xstate_bv;
782511b0 3299 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3300 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3301
3302 /*
3303 * Copy each region from the non-compacted offset to the
3304 * possibly compacted offset.
3305 */
d91cab78 3306 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3307 while (valid) {
3308 u64 feature = valid & -valid;
3309 int index = fls64(feature) - 1;
3310 void *dest = get_xsave_addr(xsave, feature);
3311
3312 if (dest) {
3313 u32 size, offset, ecx, edx;
3314 cpuid_count(XSTATE_CPUID, index,
3315 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3316 if (feature == XFEATURE_MASK_PKRU)
3317 memcpy(&vcpu->arch.pkru, src + offset,
3318 sizeof(vcpu->arch.pkru));
3319 else
3320 memcpy(dest, src + offset, size);
ee4100da 3321 }
df1daba7
PB		 3322
3323 valid -= feature;
3324 }
3325}
3326
2d5b5a66
SY		 3327static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3328 struct kvm_xsave *guest_xsave)
3329{
d366bf7e 3330 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3331 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3332 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3333 } else {
2d5b5a66 3334 memcpy(guest_xsave->region,
7366ed77 3335 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3336 sizeof(struct fxregs_state));
2d5b5a66 3337 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3338 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3339 }
3340}
3341
a575813b
WL		 3342#define XSAVE_MXCSR_OFFSET 24
3343
2d5b5a66
SY		 3344static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3345 struct kvm_xsave *guest_xsave)
3346{
3347 u64 xstate_bv =
3348 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3349 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3350
d366bf7e 3351 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3352 /*
3353 * Here we allow setting states that are not present in
3354 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3355 * with old userspace.
3356 */
a575813b
WL		 3357 if (xstate_bv & ~kvm_supported_xcr0() ||
3358 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3359 return -EINVAL;
df1daba7 3360 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3361 } else {
a575813b
WL		 3362 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3363 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3364 return -EINVAL;
7366ed77 3365 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3366 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3367 }
3368 return 0;
3369}
3370
3371static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3372 struct kvm_xcrs *guest_xcrs)
3373{
d366bf7e 3374 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3375 guest_xcrs->nr_xcrs = 0;
3376 return;
3377 }
3378
3379 guest_xcrs->nr_xcrs = 1;
3380 guest_xcrs->flags = 0;
3381 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3382 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3383}
3384
3385static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3386 struct kvm_xcrs *guest_xcrs)
3387{
3388 int i, r = 0;
3389
d366bf7e 3390 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3391 return -EINVAL;
3392
3393 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3394 return -EINVAL;
3395
3396 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3397 /* Only support XCR0 currently */
c67a04cb 3398 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3399 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3400 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3401 break;
3402 }
3403 if (r)
3404 r = -EINVAL;
3405 return r;
3406}
3407
1c0b28c2
EM		 3408/*
3409 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3410 * stopped by the hypervisor. This function will be called from the host only.
3411 * EINVAL is returned when the host attempts to set the flag for a guest that
3412 * does not support pv clocks.
3413 */
3414static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3415{
0b79459b 3416 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3417 return -EINVAL;
51d59c6b 3418 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3419 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3420 return 0;
3421}
3422
5c919412
AS		 3423static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3424 struct kvm_enable_cap *cap)
3425{
3426 if (cap->flags)
3427 return -EINVAL;
3428
3429 switch (cap->cap) {
efc479e6
RK		 3430 case KVM_CAP_HYPERV_SYNIC2:
3431 if (cap->args[0])
3432 return -EINVAL;
5c919412 3433 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3434 if (!irqchip_in_kernel(vcpu->kvm))
3435 return -EINVAL;
efc479e6
RK		 3436 return kvm_hv_activate_synic(vcpu, cap->cap ==
3437 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3438 default:
3439 return -EINVAL;
3440 }
3441}
3442
313a3dc7
CO		 3443long kvm_arch_vcpu_ioctl(struct file *filp,
3444 unsigned int ioctl, unsigned long arg)
3445{
3446 struct kvm_vcpu *vcpu = filp->private_data;
3447 void __user *argp = (void __user *)arg;
3448 int r;
d1ac91d8
AK		 3449 union {
3450 struct kvm_lapic_state *lapic;
3451 struct kvm_xsave *xsave;
3452 struct kvm_xcrs *xcrs;
3453 void *buffer;
3454 } u;
3455
3456 u.buffer = NULL;
313a3dc7
CO		 3457 switch (ioctl) {
3458 case KVM_GET_LAPIC: {
2204ae3c 3459 r = -EINVAL;
bce87cce 3460 if (!lapic_in_kernel(vcpu))
2204ae3c 3461 goto out;
d1ac91d8 3462 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3463
b772ff36 3464 r = -ENOMEM;
d1ac91d8 3465 if (!u.lapic)
b772ff36 3466 goto out;
d1ac91d8 3467 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3468 if (r)
3469 goto out;
3470 r = -EFAULT;
d1ac91d8 3471 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3472 goto out;
3473 r = 0;
3474 break;
3475 }
3476 case KVM_SET_LAPIC: {
2204ae3c 3477 r = -EINVAL;
bce87cce 3478 if (!lapic_in_kernel(vcpu))
2204ae3c 3479 goto out;
ff5c2c03 3480 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3481 if (IS_ERR(u.lapic))
3482 return PTR_ERR(u.lapic);
ff5c2c03 3483
d1ac91d8 3484 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3485 break;
3486 }
f77bc6a4
ZX		 3487 case KVM_INTERRUPT: {
3488 struct kvm_interrupt irq;
3489
3490 r = -EFAULT;
3491 if (copy_from_user(&irq, argp, sizeof irq))
3492 goto out;
3493 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3494 break;
3495 }
c4abb7c9
JK		 3496 case KVM_NMI: {
3497 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3498 break;
3499 }
f077825a
PB		 3500 case KVM_SMI: {
3501 r = kvm_vcpu_ioctl_smi(vcpu);
3502 break;
3503 }
313a3dc7
CO		 3504 case KVM_SET_CPUID: {
3505 struct kvm_cpuid __user *cpuid_arg = argp;
3506 struct kvm_cpuid cpuid;
3507
3508 r = -EFAULT;
3509 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3510 goto out;
3511 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3512 break;
3513 }
07716717
DK		 3514 case KVM_SET_CPUID2: {
3515 struct kvm_cpuid2 __user *cpuid_arg = argp;
3516 struct kvm_cpuid2 cpuid;
3517
3518 r = -EFAULT;
3519 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3520 goto out;
3521 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3522 cpuid_arg->entries);
07716717
DK		 3523 break;
3524 }
3525 case KVM_GET_CPUID2: {
3526 struct kvm_cpuid2 __user *cpuid_arg = argp;
3527 struct kvm_cpuid2 cpuid;
3528
3529 r = -EFAULT;
3530 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3531 goto out;
3532 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3533 cpuid_arg->entries);
07716717
DK		 3534 if (r)
3535 goto out;
3536 r = -EFAULT;
3537 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3538 goto out;
3539 r = 0;
3540 break;
3541 }
313a3dc7 3542 case KVM_GET_MSRS:
609e36d3 3543 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3544 break;
3545 case KVM_SET_MSRS:
3546 r = msr_io(vcpu, argp, do_set_msr, 0);
3547 break;
b209749f
AK		 3548 case KVM_TPR_ACCESS_REPORTING: {
3549 struct kvm_tpr_access_ctl tac;
3550
3551 r = -EFAULT;
3552 if (copy_from_user(&tac, argp, sizeof tac))
3553 goto out;
3554 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3555 if (r)
3556 goto out;
3557 r = -EFAULT;
3558 if (copy_to_user(argp, &tac, sizeof tac))
3559 goto out;
3560 r = 0;
3561 break;
3562 };
b93463aa
AK		 3563 case KVM_SET_VAPIC_ADDR: {
3564 struct kvm_vapic_addr va;
7301d6ab 3565 int idx;
b93463aa
AK		 3566
3567 r = -EINVAL;
35754c98 3568 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3569 goto out;
3570 r = -EFAULT;
3571 if (copy_from_user(&va, argp, sizeof va))
3572 goto out;
7301d6ab 3573 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3574 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3575 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3576 break;
3577 }
890ca9ae
HY		 3578 case KVM_X86_SETUP_MCE: {
3579 u64 mcg_cap;
3580
3581 r = -EFAULT;
3582 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3583 goto out;
3584 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3585 break;
3586 }
3587 case KVM_X86_SET_MCE: {
3588 struct kvm_x86_mce mce;
3589
3590 r = -EFAULT;
3591 if (copy_from_user(&mce, argp, sizeof mce))
3592 goto out;
3593 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3594 break;
3595 }
3cfc3092
JK		 3596 case KVM_GET_VCPU_EVENTS: {
3597 struct kvm_vcpu_events events;
3598
3599 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3600
3601 r = -EFAULT;
3602 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3603 break;
3604 r = 0;
3605 break;
3606 }
3607 case KVM_SET_VCPU_EVENTS: {
3608 struct kvm_vcpu_events events;
3609
3610 r = -EFAULT;
3611 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3612 break;
3613
3614 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3615 break;
3616 }
a1efbe77
JK		 3617 case KVM_GET_DEBUGREGS: {
3618 struct kvm_debugregs dbgregs;
3619
3620 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3621
3622 r = -EFAULT;
3623 if (copy_to_user(argp, &dbgregs,
3624 sizeof(struct kvm_debugregs)))
3625 break;
3626 r = 0;
3627 break;
3628 }
3629 case KVM_SET_DEBUGREGS: {
3630 struct kvm_debugregs dbgregs;
3631
3632 r = -EFAULT;
3633 if (copy_from_user(&dbgregs, argp,
3634 sizeof(struct kvm_debugregs)))
3635 break;
3636
3637 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3638 break;
3639 }
2d5b5a66 3640 case KVM_GET_XSAVE: {
d1ac91d8 3641 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3642 r = -ENOMEM;
d1ac91d8 3643 if (!u.xsave)
2d5b5a66
SY		 3644 break;
3645
d1ac91d8 3646 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3647
3648 r = -EFAULT;
d1ac91d8 3649 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3650 break;
3651 r = 0;
3652 break;
3653 }
3654 case KVM_SET_XSAVE: {
ff5c2c03 3655 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3656 if (IS_ERR(u.xsave))
3657 return PTR_ERR(u.xsave);
2d5b5a66 3658
d1ac91d8 3659 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3660 break;
3661 }
3662 case KVM_GET_XCRS: {
d1ac91d8 3663 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3664 r = -ENOMEM;
d1ac91d8 3665 if (!u.xcrs)
2d5b5a66
SY		 3666 break;
3667
d1ac91d8 3668 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3669
3670 r = -EFAULT;
d1ac91d8 3671 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3672 sizeof(struct kvm_xcrs)))
3673 break;
3674 r = 0;
3675 break;
3676 }
3677 case KVM_SET_XCRS: {
ff5c2c03 3678 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3679 if (IS_ERR(u.xcrs))
3680 return PTR_ERR(u.xcrs);
2d5b5a66 3681
d1ac91d8 3682 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3683 break;
3684 }
92a1f12d
JR		 3685 case KVM_SET_TSC_KHZ: {
3686 u32 user_tsc_khz;
3687
3688 r = -EINVAL;
92a1f12d
JR		 3689 user_tsc_khz = (u32)arg;
3690
3691 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3692 goto out;
3693
cc578287
ZA		 3694 if (user_tsc_khz == 0)
3695 user_tsc_khz = tsc_khz;
3696
381d585c
HZ		 3697 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3698 r = 0;
92a1f12d 3699
92a1f12d
JR		 3700 goto out;
3701 }
3702 case KVM_GET_TSC_KHZ: {
cc578287 3703 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3704 goto out;
3705 }
1c0b28c2
EM		 3706 case KVM_KVMCLOCK_CTRL: {
3707 r = kvm_set_guest_paused(vcpu);
3708 goto out;
3709 }
5c919412
AS		 3710 case KVM_ENABLE_CAP: {
3711 struct kvm_enable_cap cap;
3712
3713 r = -EFAULT;
3714 if (copy_from_user(&cap, argp, sizeof(cap)))
3715 goto out;
3716 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3717 break;
3718 }
313a3dc7
CO		 3719 default:
3720 r = -EINVAL;
3721 }
3722out:
d1ac91d8 3723 kfree(u.buffer);
313a3dc7
CO		 3724 return r;
3725}
3726
5b1c1493
CO		 3727int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3728{
3729 return VM_FAULT_SIGBUS;
3730}
3731
1fe779f8
CO		 3732static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3733{
3734 int ret;
3735
3736 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3737 return -EINVAL;
1fe779f8
CO		 3738 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3739 return ret;
3740}
3741
b927a3ce
SY		 3742static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3743 u64 ident_addr)
3744{
3745 kvm->arch.ept_identity_map_addr = ident_addr;
3746 return 0;
3747}
3748
1fe779f8
CO		 3749static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3750 u32 kvm_nr_mmu_pages)
3751{
3752 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3753 return -EINVAL;
3754
79fac95e 3755 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3756
3757 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3758 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3759
79fac95e 3760 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3761 return 0;
3762}
3763
3764static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3765{
39de71ec 3766 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3767}
3768
1fe779f8
CO		 3769static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3770{
90bca052 3771 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3772 int r;
3773
3774 r = 0;
3775 switch (chip->chip_id) {
3776 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3777 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3778 sizeof(struct kvm_pic_state));
3779 break;
3780 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3781 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3782 sizeof(struct kvm_pic_state));
3783 break;
3784 case KVM_IRQCHIP_IOAPIC:
33392b49 3785 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3786 break;
3787 default:
3788 r = -EINVAL;
3789 break;
3790 }
3791 return r;
3792}
3793
3794static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3795{
90bca052 3796 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3797 int r;
3798
3799 r = 0;
3800 switch (chip->chip_id) {
3801 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3802 spin_lock(&pic->lock);
3803 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3804 sizeof(struct kvm_pic_state));
90bca052 3805 spin_unlock(&pic->lock);
1fe779f8
CO		 3806 break;
3807 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3808 spin_lock(&pic->lock);
3809 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3810 sizeof(struct kvm_pic_state));
90bca052 3811 spin_unlock(&pic->lock);
1fe779f8
CO		 3812 break;
3813 case KVM_IRQCHIP_IOAPIC:
33392b49 3814 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3815 break;
3816 default:
3817 r = -EINVAL;
3818 break;
3819 }
90bca052 3820 kvm_pic_update_irq(pic);
1fe779f8
CO		 3821 return r;
3822}
3823
e0f63cb9
SY		 3824static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3825{
34f3941c
RK		 3826 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3827
3828 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3829
3830 mutex_lock(&kps->lock);
3831 memcpy(ps, &kps->channels, sizeof(*ps));
3832 mutex_unlock(&kps->lock);
2da29bcc 3833 return 0;
e0f63cb9
SY		 3834}
3835
3836static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3837{
0185604c 3838 int i;
09edea72
RK		 3839 struct kvm_pit *pit = kvm->arch.vpit;
3840
3841 mutex_lock(&pit->pit_state.lock);
34f3941c 3842 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3843 for (i = 0; i < 3; i++)
09edea72
RK		 3844 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3845 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3846 return 0;
e9f42757
BK		 3847}
3848
3849static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3850{
e9f42757
BK		 3851 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3852 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3853 sizeof(ps->channels));
3854 ps->flags = kvm->arch.vpit->pit_state.flags;
3855 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3856 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3857 return 0;
e9f42757
BK		 3858}
3859
3860static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3861{
2da29bcc 3862 int start = 0;
0185604c 3863 int i;
e9f42757 3864 u32 prev_legacy, cur_legacy;
09edea72
RK		 3865 struct kvm_pit *pit = kvm->arch.vpit;
3866
3867 mutex_lock(&pit->pit_state.lock);
3868 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3869 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3870 if (!prev_legacy && cur_legacy)
3871 start = 1;
09edea72
RK		 3872 memcpy(&pit->pit_state.channels, &ps->channels,
3873 sizeof(pit->pit_state.channels));
3874 pit->pit_state.flags = ps->flags;
0185604c 3875 for (i = 0; i < 3; i++)
09edea72 3876 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3877 start && i == 0);
09edea72 3878 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3879 return 0;
e0f63cb9
SY		 3880}
3881
52d939a0
MT		 3882static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3883 struct kvm_reinject_control *control)
3884{
71474e2f
RK		 3885 struct kvm_pit *pit = kvm->arch.vpit;
3886
3887 if (!pit)
52d939a0 3888 return -ENXIO;
b39c90b6 3889
71474e2f
RK		 3890 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3891 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3892 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3893 */
3894 mutex_lock(&pit->pit_state.lock);
3895 kvm_pit_set_reinject(pit, control->pit_reinject);
3896 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3897
52d939a0
MT		 3898 return 0;
3899}
3900
95d4c16c 3901/**
60c34612
TY		 3902 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3903 * @kvm: kvm instance
3904 * @log: slot id and address to which we copy the log
95d4c16c 3905 *
e108ff2f
PB		 3906 * Steps 1-4 below provide general overview of dirty page logging. See
3907 * kvm_get_dirty_log_protect() function description for additional details.
3908 *
3909 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3910 * always flush the TLB (step 4) even if previous step failed and the dirty
3911 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3912 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3913 * writes will be marked dirty for next log read.
95d4c16c 3914 *
60c34612
TY		 3915 * 1. Take a snapshot of the bit and clear it if needed.
3916 * 2. Write protect the corresponding page.
e108ff2f
PB		 3917 * 3. Copy the snapshot to the userspace.
3918 * 4. Flush TLB's if needed.
5bb064dc 3919 */
60c34612 3920int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3921{
60c34612 3922 bool is_dirty = false;
e108ff2f 3923 int r;
5bb064dc 3924
79fac95e 3925 mutex_lock(&kvm->slots_lock);
5bb064dc 3926
88178fd4
KH		 3927 /*
3928 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3929 */
3930 if (kvm_x86_ops->flush_log_dirty)
3931 kvm_x86_ops->flush_log_dirty(kvm);
3932
e108ff2f 3933 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3934
3935 /*
3936 * All the TLBs can be flushed out of mmu lock, see the comments in
3937 * kvm_mmu_slot_remove_write_access().
3938 */
e108ff2f 3939 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3940 if (is_dirty)
3941 kvm_flush_remote_tlbs(kvm);
3942
79fac95e 3943 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3944 return r;
3945}
3946
aa2fbe6d
YZ		 3947int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3948 bool line_status)
23d43cf9
CD		 3949{
3950 if (!irqchip_in_kernel(kvm))
3951 return -ENXIO;
3952
3953 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3954 irq_event->irq, irq_event->level,
3955 line_status);
23d43cf9
CD		 3956 return 0;
3957}
3958
90de4a18
NA		 3959static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3960 struct kvm_enable_cap *cap)
3961{
3962 int r;
3963
3964 if (cap->flags)
3965 return -EINVAL;
3966
3967 switch (cap->cap) {
3968 case KVM_CAP_DISABLE_QUIRKS:
3969 kvm->arch.disabled_quirks = cap->args[0];
3970 r = 0;
3971 break;
49df6397
SR		 3972 case KVM_CAP_SPLIT_IRQCHIP: {
3973 mutex_lock(&kvm->lock);
b053b2ae
SR		 3974 r = -EINVAL;
3975 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3976 goto split_irqchip_unlock;
49df6397
SR		 3977 r = -EEXIST;
3978 if (irqchip_in_kernel(kvm))
3979 goto split_irqchip_unlock;
557abc40 3980 if (kvm->created_vcpus)
49df6397
SR		 3981 goto split_irqchip_unlock;
3982 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3983 if (r)
49df6397
SR		 3984 goto split_irqchip_unlock;
3985 /* Pairs with irqchip_in_kernel. */
3986 smp_wmb();
49776faf 3987 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3988 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3989 r = 0;
3990split_irqchip_unlock:
3991 mutex_unlock(&kvm->lock);
3992 break;
3993 }
37131313
RK		 3994 case KVM_CAP_X2APIC_API:
3995 r = -EINVAL;
3996 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3997 break;
3998
3999 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4000 kvm->arch.x2apic_format = true;
c519265f
RK		 4001 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4002 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4003
4004 r = 0;
4005 break;
90de4a18
NA		 4006 default:
4007 r = -EINVAL;
4008 break;
4009 }
4010 return r;
4011}
4012
1fe779f8
CO		 4013long kvm_arch_vm_ioctl(struct file *filp,
4014 unsigned int ioctl, unsigned long arg)
4015{
4016 struct kvm *kvm = filp->private_data;
4017 void __user *argp = (void __user *)arg;
367e1319 4018 int r = -ENOTTY;
f0d66275
DH		 4019 /*
4020 * This union makes it completely explicit to gcc-3.x
4021 * that these two variables' stack usage should be
4022 * combined, not added together.
4023 */
4024 union {
4025 struct kvm_pit_state ps;
e9f42757 4026 struct kvm_pit_state2 ps2;
c5ff41ce 4027 struct kvm_pit_config pit_config;
f0d66275 4028 } u;
1fe779f8
CO		 4029
4030 switch (ioctl) {
4031 case KVM_SET_TSS_ADDR:
4032 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4033 break;
b927a3ce
SY		 4034 case KVM_SET_IDENTITY_MAP_ADDR: {
4035 u64 ident_addr;
4036
1af1ac91
DH		 4037 mutex_lock(&kvm->lock);
4038 r = -EINVAL;
4039 if (kvm->created_vcpus)
4040 goto set_identity_unlock;
b927a3ce
SY		 4041 r = -EFAULT;
4042 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4043 goto set_identity_unlock;
b927a3ce 4044 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4045set_identity_unlock:
4046 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4047 break;
4048 }
1fe779f8
CO		 4049 case KVM_SET_NR_MMU_PAGES:
4050 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4051 break;
4052 case KVM_GET_NR_MMU_PAGES:
4053 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4054 break;
3ddea128 4055 case KVM_CREATE_IRQCHIP: {
3ddea128 4056 mutex_lock(&kvm->lock);
09941366 4057
3ddea128 4058 r = -EEXIST;
35e6eaa3 4059 if (irqchip_in_kernel(kvm))
3ddea128 4060 goto create_irqchip_unlock;
09941366 4061
3e515705 4062 r = -EINVAL;
557abc40 4063 if (kvm->created_vcpus)
3e515705 4064 goto create_irqchip_unlock;
09941366
RK		 4065
4066 r = kvm_pic_init(kvm);
4067 if (r)
3ddea128 4068 goto create_irqchip_unlock;
09941366
RK		 4069
4070 r = kvm_ioapic_init(kvm);
4071 if (r) {
09941366 4072 kvm_pic_destroy(kvm);
3ddea128 4073 goto create_irqchip_unlock;
09941366
RK		 4074 }
4075
399ec807
AK		 4076 r = kvm_setup_default_irq_routing(kvm);
4077 if (r) {
72bb2fcd 4078 kvm_ioapic_destroy(kvm);
09941366 4079 kvm_pic_destroy(kvm);
71ba994c 4080 goto create_irqchip_unlock;
399ec807 4081 }
49776faf 4082 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4083 smp_wmb();
49776faf 4084 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4085 create_irqchip_unlock:
4086 mutex_unlock(&kvm->lock);
1fe779f8 4087 break;
3ddea128 4088 }
7837699f 4089 case KVM_CREATE_PIT:
c5ff41ce
JK		 4090 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4091 goto create_pit;
4092 case KVM_CREATE_PIT2:
4093 r = -EFAULT;
4094 if (copy_from_user(&u.pit_config, argp,
4095 sizeof(struct kvm_pit_config)))
4096 goto out;
4097 create_pit:
250715a6 4098 mutex_lock(&kvm->lock);
269e05e4
AK		 4099 r = -EEXIST;
4100 if (kvm->arch.vpit)
4101 goto create_pit_unlock;
7837699f 4102 r = -ENOMEM;
c5ff41ce 4103 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4104 if (kvm->arch.vpit)
4105 r = 0;
269e05e4 4106 create_pit_unlock:
250715a6 4107 mutex_unlock(&kvm->lock);
7837699f 4108 break;
1fe779f8
CO		 4109 case KVM_GET_IRQCHIP: {
4110 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4111 struct kvm_irqchip *chip;
1fe779f8 4112
ff5c2c03
SL		 4113 chip = memdup_user(argp, sizeof(*chip));
4114 if (IS_ERR(chip)) {
4115 r = PTR_ERR(chip);
1fe779f8 4116 goto out;
ff5c2c03
SL		 4117 }
4118
1fe779f8 4119 r = -ENXIO;
826da321 4120 if (!irqchip_kernel(kvm))
f0d66275
DH		 4121 goto get_irqchip_out;
4122 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4123 if (r)
f0d66275 4124 goto get_irqchip_out;
1fe779f8 4125 r = -EFAULT;
f0d66275
DH		 4126 if (copy_to_user(argp, chip, sizeof *chip))
4127 goto get_irqchip_out;
1fe779f8 4128 r = 0;
f0d66275
DH		 4129 get_irqchip_out:
4130 kfree(chip);
1fe779f8
CO		 4131 break;
4132 }
4133 case KVM_SET_IRQCHIP: {
4134 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4135 struct kvm_irqchip *chip;
1fe779f8 4136
ff5c2c03
SL		 4137 chip = memdup_user(argp, sizeof(*chip));
4138 if (IS_ERR(chip)) {
4139 r = PTR_ERR(chip);
1fe779f8 4140 goto out;
ff5c2c03
SL		 4141 }
4142
1fe779f8 4143 r = -ENXIO;
826da321 4144 if (!irqchip_kernel(kvm))
f0d66275
DH		 4145 goto set_irqchip_out;
4146 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4147 if (r)
f0d66275 4148 goto set_irqchip_out;
1fe779f8 4149 r = 0;
f0d66275
DH		 4150 set_irqchip_out:
4151 kfree(chip);
1fe779f8
CO		 4152 break;
4153 }
e0f63cb9 4154 case KVM_GET_PIT: {
e0f63cb9 4155 r = -EFAULT;
f0d66275 4156 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4157 goto out;
4158 r = -ENXIO;
4159 if (!kvm->arch.vpit)
4160 goto out;
f0d66275 4161 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4162 if (r)
4163 goto out;
4164 r = -EFAULT;
f0d66275 4165 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4166 goto out;
4167 r = 0;
4168 break;
4169 }
4170 case KVM_SET_PIT: {
e0f63cb9 4171 r = -EFAULT;
f0d66275 4172 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4173 goto out;
4174 r = -ENXIO;
4175 if (!kvm->arch.vpit)
4176 goto out;
f0d66275 4177 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4178 break;
4179 }
e9f42757
BK		 4180 case KVM_GET_PIT2: {
4181 r = -ENXIO;
4182 if (!kvm->arch.vpit)
4183 goto out;
4184 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4185 if (r)
4186 goto out;
4187 r = -EFAULT;
4188 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4189 goto out;
4190 r = 0;
4191 break;
4192 }
4193 case KVM_SET_PIT2: {
4194 r = -EFAULT;
4195 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4196 goto out;
4197 r = -ENXIO;
4198 if (!kvm->arch.vpit)
4199 goto out;
4200 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4201 break;
4202 }
52d939a0
MT		 4203 case KVM_REINJECT_CONTROL: {
4204 struct kvm_reinject_control control;
4205 r = -EFAULT;
4206 if (copy_from_user(&control, argp, sizeof(control)))
4207 goto out;
4208 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4209 break;
4210 }
d71ba788
PB		 4211 case KVM_SET_BOOT_CPU_ID:
4212 r = 0;
4213 mutex_lock(&kvm->lock);
557abc40 4214 if (kvm->created_vcpus)
d71ba788
PB		 4215 r = -EBUSY;
4216 else
4217 kvm->arch.bsp_vcpu_id = arg;
4218 mutex_unlock(&kvm->lock);
4219 break;
ffde22ac
ES		 4220 case KVM_XEN_HVM_CONFIG: {
4221 r = -EFAULT;
4222 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4223 sizeof(struct kvm_xen_hvm_config)))
4224 goto out;
4225 r = -EINVAL;
4226 if (kvm->arch.xen_hvm_config.flags)
4227 goto out;
4228 r = 0;
4229 break;
4230 }
afbcf7ab 4231 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4232 struct kvm_clock_data user_ns;
4233 u64 now_ns;
afbcf7ab
GC		 4234
4235 r = -EFAULT;
4236 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4237 goto out;
4238
4239 r = -EINVAL;
4240 if (user_ns.flags)
4241 goto out;
4242
4243 r = 0;
0bc48bea
RK		 4244 /*
4245 * TODO: userspace has to take care of races with VCPU_RUN, so
4246 * kvm_gen_update_masterclock() can be cut down to locked
4247 * pvclock_update_vm_gtod_copy().
4248 */
4249 kvm_gen_update_masterclock(kvm);
e891a32e 4250 now_ns = get_kvmclock_ns(kvm);
108b249c 4251 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4252 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4253 break;
4254 }
4255 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4256 struct kvm_clock_data user_ns;
4257 u64 now_ns;
4258
e891a32e 4259 now_ns = get_kvmclock_ns(kvm);
108b249c 4260 user_ns.clock = now_ns;
e3fd9a93 4261 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4262 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4263
4264 r = -EFAULT;
4265 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4266 goto out;
4267 r = 0;
4268 break;
4269 }
90de4a18
NA		 4270 case KVM_ENABLE_CAP: {
4271 struct kvm_enable_cap cap;
afbcf7ab 4272
90de4a18
NA		 4273 r = -EFAULT;
4274 if (copy_from_user(&cap, argp, sizeof(cap)))
4275 goto out;
4276 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4277 break;
4278 }
1fe779f8 4279 default:
ad6260da 4280 r = -ENOTTY;
1fe779f8
CO		 4281 }
4282out:
4283 return r;
4284}
4285
a16b043c 4286static void kvm_init_msr_list(void)
043405e1
CO		 4287{
4288 u32 dummy[2];
4289 unsigned i, j;
4290
62ef68bb 4291 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4292 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4293 continue;
93c4adc7
PB		 4294
4295 /*
4296 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4297 * to the guests in some cases.
93c4adc7
PB		 4298 */
4299 switch (msrs_to_save[i]) {
4300 case MSR_IA32_BNDCFGS:
4301 if (!kvm_x86_ops->mpx_supported())
4302 continue;
4303 break;
9dbe6cf9
PB		 4304 case MSR_TSC_AUX:
4305 if (!kvm_x86_ops->rdtscp_supported())
4306 continue;
4307 break;
93c4adc7
PB		 4308 default:
4309 break;
4310 }
4311
043405e1
CO		 4312 if (j < i)
4313 msrs_to_save[j] = msrs_to_save[i];
4314 j++;
4315 }
4316 num_msrs_to_save = j;
62ef68bb
PB		 4317
4318 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4319 switch (emulated_msrs[i]) {
6d396b55
PB		 4320 case MSR_IA32_SMBASE:
4321 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4322 continue;
4323 break;
62ef68bb
PB		 4324 default:
4325 break;
4326 }
4327
4328 if (j < i)
4329 emulated_msrs[j] = emulated_msrs[i];
4330 j++;
4331 }
4332 num_emulated_msrs = j;
043405e1
CO		 4333}
4334
bda9020e
MT		 4335static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4336 const void *v)
bbd9b64e 4337{
70252a10
AK		 4338 int handled = 0;
4339 int n;
4340
4341 do {
4342 n = min(len, 8);
bce87cce 4343 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4344 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4345 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4346 break;
4347 handled += n;
4348 addr += n;
4349 len -= n;
4350 v += n;
4351 } while (len);
bbd9b64e 4352
70252a10 4353 return handled;
bbd9b64e
CO		 4354}
4355
bda9020e 4356static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4357{
70252a10
AK		 4358 int handled = 0;
4359 int n;
4360
4361 do {
4362 n = min(len, 8);
bce87cce 4363 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4364 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4365 addr, n, v))
4366 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4367 break;
4368 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4369 handled += n;
4370 addr += n;
4371 len -= n;
4372 v += n;
4373 } while (len);
bbd9b64e 4374
70252a10 4375 return handled;
bbd9b64e
CO		 4376}
4377
2dafc6c2
GN		 4378static void kvm_set_segment(struct kvm_vcpu *vcpu,
4379 struct kvm_segment *var, int seg)
4380{
4381 kvm_x86_ops->set_segment(vcpu, var, seg);
4382}
4383
4384void kvm_get_segment(struct kvm_vcpu *vcpu,
4385 struct kvm_segment *var, int seg)
4386{
4387 kvm_x86_ops->get_segment(vcpu, var, seg);
4388}
4389
54987b7a
PB		 4390gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4391 struct x86_exception *exception)
02f59dc9
JR		 4392{
4393 gpa_t t_gpa;
02f59dc9
JR		 4394
4395 BUG_ON(!mmu_is_nested(vcpu));
4396
4397 /* NPT walks are always user-walks */
4398 access |= PFERR_USER_MASK;
54987b7a 4399 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4400
4401 return t_gpa;
4402}
4403
ab9ae313
AK		 4404gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4405 struct x86_exception *exception)
1871c602
GN		 4406{
4407 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4408 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4409}
4410
ab9ae313
AK		 4411 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4412 struct x86_exception *exception)
1871c602
GN		 4413{
4414 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4415 access |= PFERR_FETCH_MASK;
ab9ae313 4416 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4417}
4418
ab9ae313
AK		 4419gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4420 struct x86_exception *exception)
1871c602
GN		 4421{
4422 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4423 access |= PFERR_WRITE_MASK;
ab9ae313 4424 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4425}
4426
4427/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4428gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4429 struct x86_exception *exception)
1871c602 4430{
ab9ae313 4431 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4432}
4433
4434static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4435 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4436 struct x86_exception *exception)
bbd9b64e
CO		 4437{
4438 void *data = val;
10589a46 4439 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4440
4441 while (bytes) {
14dfe855 4442 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4443 exception);
bbd9b64e 4444 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4445 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4446 int ret;
4447
bcc55cba 4448 if (gpa == UNMAPPED_GVA)
ab9ae313 4449 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4450 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4451 offset, toread);
10589a46 4452 if (ret < 0) {
c3cd7ffa 4453 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4454 goto out;
4455 }
bbd9b64e 4456
77c2002e
IE		 4457 bytes -= toread;
4458 data += toread;
4459 addr += toread;
bbd9b64e 4460 }
10589a46 4461out:
10589a46 4462 return r;
bbd9b64e 4463}
77c2002e 4464
1871c602 4465/* used for instruction fetching */
0f65dd70
AK		 4466static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4467 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4468 struct x86_exception *exception)
1871c602 4469{
0f65dd70 4470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4471 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4472 unsigned offset;
4473 int ret;
0f65dd70 4474
44583cba
PB		 4475 /* Inline kvm_read_guest_virt_helper for speed. */
4476 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4477 exception);
4478 if (unlikely(gpa == UNMAPPED_GVA))
4479 return X86EMUL_PROPAGATE_FAULT;
4480
4481 offset = addr & (PAGE_SIZE-1);
4482 if (WARN_ON(offset + bytes > PAGE_SIZE))
4483 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4484 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4485 offset, bytes);
44583cba
PB		 4486 if (unlikely(ret < 0))
4487 return X86EMUL_IO_NEEDED;
4488
4489 return X86EMUL_CONTINUE;
1871c602
GN		 4490}
4491
064aea77 4492int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4493 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4494 struct x86_exception *exception)
1871c602 4495{
0f65dd70 4496 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4497 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4498
1871c602 4499 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4500 exception);
1871c602 4501}
064aea77 4502EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4503
0f65dd70
AK		 4504static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4505 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4506 struct x86_exception *exception)
1871c602 4507{
0f65dd70 4508 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4509 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4510}
4511
7a036a6f
RK		 4512static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4513 unsigned long addr, void *val, unsigned int bytes)
4514{
4515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4516 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4517
4518 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4519}
4520
6a4d7550 4521int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4522 gva_t addr, void *val,
2dafc6c2 4523 unsigned int bytes,
bcc55cba 4524 struct x86_exception *exception)
77c2002e 4525{
0f65dd70 4526 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4527 void *data = val;
4528 int r = X86EMUL_CONTINUE;
4529
4530 while (bytes) {
14dfe855
JR		 4531 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4532 PFERR_WRITE_MASK,
ab9ae313 4533 exception);
77c2002e
IE		 4534 unsigned offset = addr & (PAGE_SIZE-1);
4535 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4536 int ret;
4537
bcc55cba 4538 if (gpa == UNMAPPED_GVA)
ab9ae313 4539 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4540 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4541 if (ret < 0) {
c3cd7ffa 4542 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4543 goto out;
4544 }
4545
4546 bytes -= towrite;
4547 data += towrite;
4548 addr += towrite;
4549 }
4550out:
4551 return r;
4552}
6a4d7550 4553EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4554
0f89b207
TL		 4555static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4556 gpa_t gpa, bool write)
4557{
4558 /* For APIC access vmexit */
4559 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4560 return 1;
4561
4562 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4563 trace_vcpu_match_mmio(gva, gpa, write, true);
4564 return 1;
4565 }
4566
4567 return 0;
4568}
4569
af7cc7d1
XG		 4570static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4571 gpa_t *gpa, struct x86_exception *exception,
4572 bool write)
4573{
97d64b78
AK		 4574 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4575 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4576
be94f6b7
HH		 4577 /*
4578 * currently PKRU is only applied to ept enabled guest so
4579 * there is no pkey in EPT page table for L1 guest or EPT
4580 * shadow page table for L2 guest.
4581 */
97d64b78 4582 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4583 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4584 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4585 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4586 (gva & (PAGE_SIZE - 1));
4f022648 4587 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4588 return 1;
4589 }
4590
af7cc7d1
XG		 4591 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4592
4593 if (*gpa == UNMAPPED_GVA)
4594 return -1;
4595
0f89b207 4596 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4597}
4598
3200f405 4599int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4600 const void *val, int bytes)
bbd9b64e
CO		 4601{
4602 int ret;
4603
54bf36aa 4604 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4605 if (ret < 0)
bbd9b64e 4606 return 0;
0eb05bf2 4607 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4608 return 1;
4609}
4610
77d197b2
XG		 4611struct read_write_emulator_ops {
4612 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4613 int bytes);
4614 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4615 void *val, int bytes);
4616 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4617 int bytes, void *val);
4618 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4619 void *val, int bytes);
4620 bool write;
4621};
4622
4623static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4624{
4625 if (vcpu->mmio_read_completed) {
77d197b2 4626 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4627 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4628 vcpu->mmio_read_completed = 0;
4629 return 1;
4630 }
4631
4632 return 0;
4633}
4634
4635static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4636 void *val, int bytes)
4637{
54bf36aa 4638 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4639}
4640
4641static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4642 void *val, int bytes)
4643{
4644 return emulator_write_phys(vcpu, gpa, val, bytes);
4645}
4646
4647static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4648{
4649 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4650 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4651}
4652
4653static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4654 void *val, int bytes)
4655{
4656 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4657 return X86EMUL_IO_NEEDED;
4658}
4659
4660static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4661 void *val, int bytes)
4662{
f78146b0
AK		 4663 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4664
87da7e66 4665 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4666 return X86EMUL_CONTINUE;
4667}
4668
0fbe9b0b 4669static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4670 .read_write_prepare = read_prepare,
4671 .read_write_emulate = read_emulate,
4672 .read_write_mmio = vcpu_mmio_read,
4673 .read_write_exit_mmio = read_exit_mmio,
4674};
4675
0fbe9b0b 4676static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4677 .read_write_emulate = write_emulate,
4678 .read_write_mmio = write_mmio,
4679 .read_write_exit_mmio = write_exit_mmio,
4680 .write = true,
4681};
4682
22388a3c
XG		 4683static int emulator_read_write_onepage(unsigned long addr, void *val,
4684 unsigned int bytes,
4685 struct x86_exception *exception,
4686 struct kvm_vcpu *vcpu,
0fbe9b0b 4687 const struct read_write_emulator_ops *ops)
bbd9b64e 4688{
af7cc7d1
XG		 4689 gpa_t gpa;
4690 int handled, ret;
22388a3c 4691 bool write = ops->write;
f78146b0 4692 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4693 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4694
4695 /*
4696 * If the exit was due to a NPF we may already have a GPA.
4697 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4698 * Note, this cannot be used on string operations since string
4699 * operation using rep will only have the initial GPA from the NPF
4700 * occurred.
4701 */
4702 if (vcpu->arch.gpa_available &&
4703 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4704 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4705 gpa = vcpu->arch.gpa_val;
4706 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4707 } else {
4708 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4709 if (ret < 0)
4710 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4711 }
10589a46 4712
618232e2 4713 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4714 return X86EMUL_CONTINUE;
4715
bbd9b64e
CO		 4716 /*
4717 * Is this MMIO handled locally?
4718 */
22388a3c 4719 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4720 if (handled == bytes)
bbd9b64e 4721 return X86EMUL_CONTINUE;
bbd9b64e 4722
70252a10
AK		 4723 gpa += handled;
4724 bytes -= handled;
4725 val += handled;
4726
87da7e66
XG		 4727 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4728 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4729 frag->gpa = gpa;
4730 frag->data = val;
4731 frag->len = bytes;
f78146b0 4732 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4733}
4734
52eb5a6d
XL		 4735static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4736 unsigned long addr,
22388a3c
XG		 4737 void *val, unsigned int bytes,
4738 struct x86_exception *exception,
0fbe9b0b 4739 const struct read_write_emulator_ops *ops)
bbd9b64e 4740{
0f65dd70 4741 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4742 gpa_t gpa;
4743 int rc;
4744
4745 if (ops->read_write_prepare &&
4746 ops->read_write_prepare(vcpu, val, bytes))
4747 return X86EMUL_CONTINUE;
4748
4749 vcpu->mmio_nr_fragments = 0;
0f65dd70 4750
bbd9b64e
CO		 4751 /* Crossing a page boundary? */
4752 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4753 int now;
bbd9b64e
CO		 4754
4755 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4756 rc = emulator_read_write_onepage(addr, val, now, exception,
4757 vcpu, ops);
4758
bbd9b64e
CO		 4759 if (rc != X86EMUL_CONTINUE)
4760 return rc;
4761 addr += now;
bac15531
NA		 4762 if (ctxt->mode != X86EMUL_MODE_PROT64)
4763 addr = (u32)addr;
bbd9b64e
CO		 4764 val += now;
4765 bytes -= now;
4766 }
22388a3c 4767
f78146b0
AK		 4768 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4769 vcpu, ops);
4770 if (rc != X86EMUL_CONTINUE)
4771 return rc;
4772
4773 if (!vcpu->mmio_nr_fragments)
4774 return rc;
4775
4776 gpa = vcpu->mmio_fragments[0].gpa;
4777
4778 vcpu->mmio_needed = 1;
4779 vcpu->mmio_cur_fragment = 0;
4780
87da7e66 4781 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4782 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4783 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4784 vcpu->run->mmio.phys_addr = gpa;
4785
4786 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4787}
4788
4789static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4790 unsigned long addr,
4791 void *val,
4792 unsigned int bytes,
4793 struct x86_exception *exception)
4794{
4795 return emulator_read_write(ctxt, addr, val, bytes,
4796 exception, &read_emultor);
4797}
4798
52eb5a6d 4799static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4800 unsigned long addr,
4801 const void *val,
4802 unsigned int bytes,
4803 struct x86_exception *exception)
4804{
4805 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4806 exception, &write_emultor);
bbd9b64e 4807}
bbd9b64e 4808
daea3e73
AK		 4809#define CMPXCHG_TYPE(t, ptr, old, new) \
4810 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4811
4812#ifdef CONFIG_X86_64
4813# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4814#else
4815# define CMPXCHG64(ptr, old, new) \
9749a6c0 4816 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4817#endif
4818
0f65dd70
AK		 4819static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4820 unsigned long addr,
bbd9b64e
CO		 4821 const void *old,
4822 const void *new,
4823 unsigned int bytes,
0f65dd70 4824 struct x86_exception *exception)
bbd9b64e 4825{
0f65dd70 4826 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4827 gpa_t gpa;
4828 struct page *page;
4829 char *kaddr;
4830 bool exchanged;
2bacc55c 4831
daea3e73
AK		 4832 /* guests cmpxchg8b have to be emulated atomically */
4833 if (bytes > 8 || (bytes & (bytes - 1)))
4834 goto emul_write;
10589a46 4835
daea3e73 4836 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4837
daea3e73
AK		 4838 if (gpa == UNMAPPED_GVA ||
4839 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4840 goto emul_write;
2bacc55c 4841
daea3e73
AK		 4842 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4843 goto emul_write;
72dc67a6 4844
54bf36aa 4845 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4846 if (is_error_page(page))
c19b8bd6 4847 goto emul_write;
72dc67a6 4848
8fd75e12 4849 kaddr = kmap_atomic(page);
daea3e73
AK		 4850 kaddr += offset_in_page(gpa);
4851 switch (bytes) {
4852 case 1:
4853 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4854 break;
4855 case 2:
4856 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4857 break;
4858 case 4:
4859 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4860 break;
4861 case 8:
4862 exchanged = CMPXCHG64(kaddr, old, new);
4863 break;
4864 default:
4865 BUG();
2bacc55c 4866 }
8fd75e12 4867 kunmap_atomic(kaddr);
daea3e73
AK		 4868 kvm_release_page_dirty(page);
4869
4870 if (!exchanged)
4871 return X86EMUL_CMPXCHG_FAILED;
4872
54bf36aa 4873 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4874 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4875
4876 return X86EMUL_CONTINUE;
4a5f48f6 4877
3200f405 4878emul_write:
daea3e73 4879 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4880
0f65dd70 4881 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4882}
4883
cf8f70bf
GN		 4884static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4885{
cbfc6c91 4886 int r = 0, i;
cf8f70bf 4887
cbfc6c91
WL		 4888 for (i = 0; i < vcpu->arch.pio.count; i++) {
4889 if (vcpu->arch.pio.in)
4890 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4891 vcpu->arch.pio.size, pd);
4892 else
4893 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4894 vcpu->arch.pio.port, vcpu->arch.pio.size,
4895 pd);
4896 if (r)
4897 break;
4898 pd += vcpu->arch.pio.size;
4899 }
cf8f70bf
GN		 4900 return r;
4901}
4902
6f6fbe98
XG		 4903static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4904 unsigned short port, void *val,
4905 unsigned int count, bool in)
cf8f70bf 4906{
cf8f70bf 4907 vcpu->arch.pio.port = port;
6f6fbe98 4908 vcpu->arch.pio.in = in;
7972995b 4909 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4910 vcpu->arch.pio.size = size;
4911
4912 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4913 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4914 return 1;
4915 }
4916
4917 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4918 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4919 vcpu->run->io.size = size;
4920 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4921 vcpu->run->io.count = count;
4922 vcpu->run->io.port = port;
4923
4924 return 0;
4925}
4926
6f6fbe98
XG		 4927static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4928 int size, unsigned short port, void *val,
4929 unsigned int count)
cf8f70bf 4930{
ca1d4a9e 4931 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4932 int ret;
ca1d4a9e 4933
6f6fbe98
XG		 4934 if (vcpu->arch.pio.count)
4935 goto data_avail;
cf8f70bf 4936
cbfc6c91
WL		 4937 memset(vcpu->arch.pio_data, 0, size * count);
4938
6f6fbe98
XG		 4939 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4940 if (ret) {
4941data_avail:
4942 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4943 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4944 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4945 return 1;
4946 }
4947
cf8f70bf
GN		 4948 return 0;
4949}
4950
6f6fbe98
XG		 4951static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4952 int size, unsigned short port,
4953 const void *val, unsigned int count)
4954{
4955 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4956
4957 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4958 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4959 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4960}
4961
bbd9b64e
CO		 4962static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4963{
4964 return kvm_x86_ops->get_segment_base(vcpu, seg);
4965}
4966
3cb16fe7 4967static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4968{
3cb16fe7 4969 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4970}
4971
ae6a2375 4972static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4973{
4974 if (!need_emulate_wbinvd(vcpu))
4975 return X86EMUL_CONTINUE;
4976
4977 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4978 int cpu = get_cpu();
4979
4980 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4981 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4982 wbinvd_ipi, NULL, 1);
2eec7343 4983 put_cpu();
f5f48ee1 4984 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4985 } else
4986 wbinvd();
f5f48ee1
SY		 4987 return X86EMUL_CONTINUE;
4988}
5cb56059
JS		 4989
4990int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4991{
6affcbed
KH		 4992 kvm_emulate_wbinvd_noskip(vcpu);
4993 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4994}
f5f48ee1
SY		 4995EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4996
5cb56059
JS		 4997
4998
bcaf5cc5
AK		 4999static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5000{
5cb56059 5001 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5002}
5003
52eb5a6d
XL		 5004static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5005 unsigned long *dest)
bbd9b64e 5006{
16f8a6f9 5007 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5008}
5009
52eb5a6d
XL		 5010static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5011 unsigned long value)
bbd9b64e 5012{
338dbc97 5013
717746e3 5014 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5015}
5016
52a46617 5017static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5018{
52a46617 5019 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5020}
5021
717746e3 5022static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5023{
717746e3 5024 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5025 unsigned long value;
5026
5027 switch (cr) {
5028 case 0:
5029 value = kvm_read_cr0(vcpu);
5030 break;
5031 case 2:
5032 value = vcpu->arch.cr2;
5033 break;
5034 case 3:
9f8fe504 5035 value = kvm_read_cr3(vcpu);
52a46617
GN		 5036 break;
5037 case 4:
5038 value = kvm_read_cr4(vcpu);
5039 break;
5040 case 8:
5041 value = kvm_get_cr8(vcpu);
5042 break;
5043 default:
a737f256 5044 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5045 return 0;
5046 }
5047
5048 return value;
5049}
5050
717746e3 5051static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5052{
717746e3 5053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5054 int res = 0;
5055
52a46617
GN		 5056 switch (cr) {
5057 case 0:
49a9b07e 5058 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5059 break;
5060 case 2:
5061 vcpu->arch.cr2 = val;
5062 break;
5063 case 3:
2390218b 5064 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5065 break;
5066 case 4:
a83b29c6 5067 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5068 break;
5069 case 8:
eea1cff9 5070 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5071 break;
5072 default:
a737f256 5073 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5074 res = -1;
52a46617 5075 }
0f12244f
GN		 5076
5077 return res;
52a46617
GN		 5078}
5079
717746e3 5080static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5081{
717746e3 5082 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5083}
5084
4bff1e86 5085static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5086{
4bff1e86 5087 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5088}
5089
4bff1e86 5090static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5091{
4bff1e86 5092 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5093}
5094
1ac9d0cf
AK		 5095static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5096{
5097 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5098}
5099
5100static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5101{
5102 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5103}
5104
4bff1e86
AK		 5105static unsigned long emulator_get_cached_segment_base(
5106 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5107{
4bff1e86 5108 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5109}
5110
1aa36616
AK		 5111static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5112 struct desc_struct *desc, u32 *base3,
5113 int seg)
2dafc6c2
GN		 5114{
5115 struct kvm_segment var;
5116
4bff1e86 5117 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5118 *selector = var.selector;
2dafc6c2 5119
378a8b09
GN		 5120 if (var.unusable) {
5121 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5122 if (base3)
5123 *base3 = 0;
2dafc6c2 5124 return false;
378a8b09 5125 }
2dafc6c2
GN		 5126
5127 if (var.g)
5128 var.limit >>= 12;
5129 set_desc_limit(desc, var.limit);
5130 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5131#ifdef CONFIG_X86_64
5132 if (base3)
5133 *base3 = var.base >> 32;
5134#endif
2dafc6c2
GN		 5135 desc->type = var.type;
5136 desc->s = var.s;
5137 desc->dpl = var.dpl;
5138 desc->p = var.present;
5139 desc->avl = var.avl;
5140 desc->l = var.l;
5141 desc->d = var.db;
5142 desc->g = var.g;
5143
5144 return true;
5145}
5146
1aa36616
AK		 5147static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5148 struct desc_struct *desc, u32 base3,
5149 int seg)
2dafc6c2 5150{
4bff1e86 5151 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5152 struct kvm_segment var;
5153
1aa36616 5154 var.selector = selector;
2dafc6c2 5155 var.base = get_desc_base(desc);
5601d05b
GN		 5156#ifdef CONFIG_X86_64
5157 var.base |= ((u64)base3) << 32;
5158#endif
2dafc6c2
GN		 5159 var.limit = get_desc_limit(desc);
5160 if (desc->g)
5161 var.limit = (var.limit << 12) | 0xfff;
5162 var.type = desc->type;
2dafc6c2
GN		 5163 var.dpl = desc->dpl;
5164 var.db = desc->d;
5165 var.s = desc->s;
5166 var.l = desc->l;
5167 var.g = desc->g;
5168 var.avl = desc->avl;
5169 var.present = desc->p;
5170 var.unusable = !var.present;
5171 var.padding = 0;
5172
5173 kvm_set_segment(vcpu, &var, seg);
5174 return;
5175}
5176
717746e3
AK		 5177static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5178 u32 msr_index, u64 *pdata)
5179{
609e36d3
PB		 5180 struct msr_data msr;
5181 int r;
5182
5183 msr.index = msr_index;
5184 msr.host_initiated = false;
5185 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5186 if (r)
5187 return r;
5188
5189 *pdata = msr.data;
5190 return 0;
717746e3
AK		 5191}
5192
5193static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5194 u32 msr_index, u64 data)
5195{
8fe8ab46
WA		 5196 struct msr_data msr;
5197
5198 msr.data = data;
5199 msr.index = msr_index;
5200 msr.host_initiated = false;
5201 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5202}
5203
64d60670
PB		 5204static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5205{
5206 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5207
5208 return vcpu->arch.smbase;
5209}
5210
5211static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5212{
5213 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5214
5215 vcpu->arch.smbase = smbase;
5216}
5217
67f4d428
NA		 5218static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5219 u32 pmc)
5220{
c6702c9d 5221 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5222}
5223
222d21aa
AK		 5224static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5225 u32 pmc, u64 *pdata)
5226{
c6702c9d 5227 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5228}
5229
6c3287f7
AK		 5230static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5231{
5232 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5233}
5234
5037f6f3
AK		 5235static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5236{
5237 preempt_disable();
5197b808 5238 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5239}
5240
5241static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5242{
5243 preempt_enable();
5244}
5245
2953538e 5246static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5247 struct x86_instruction_info *info,
c4f035c6
AK		 5248 enum x86_intercept_stage stage)
5249{
2953538e 5250 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5251}
5252
e911eb3b
YZ		 5253static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5254 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5255{
e911eb3b 5256 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5257}
5258
dd856efa
AK		 5259static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5260{
5261 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5262}
5263
5264static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5265{
5266 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5267}
5268
801806d9
NA		 5269static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5270{
5271 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5272}
5273
6ed071f0
LP		 5274static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5275{
5276 return emul_to_vcpu(ctxt)->arch.hflags;
5277}
5278
5279static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5280{
5281 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5282}
5283
0234bf88
LP		 5284static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5285{
5286 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5287}
5288
0225fb50 5289static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5290 .read_gpr = emulator_read_gpr,
5291 .write_gpr = emulator_write_gpr,
1871c602 5292 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5293 .write_std = kvm_write_guest_virt_system,
7a036a6f 5294 .read_phys = kvm_read_guest_phys_system,
1871c602 5295 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5296 .read_emulated = emulator_read_emulated,
5297 .write_emulated = emulator_write_emulated,
5298 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5299 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5300 .pio_in_emulated = emulator_pio_in_emulated,
5301 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5302 .get_segment = emulator_get_segment,
5303 .set_segment = emulator_set_segment,
5951c442 5304 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5305 .get_gdt = emulator_get_gdt,
160ce1f1 5306 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5307 .set_gdt = emulator_set_gdt,
5308 .set_idt = emulator_set_idt,
52a46617
GN		 5309 .get_cr = emulator_get_cr,
5310 .set_cr = emulator_set_cr,
9c537244 5311 .cpl = emulator_get_cpl,
35aa5375
GN		 5312 .get_dr = emulator_get_dr,
5313 .set_dr = emulator_set_dr,
64d60670
PB		 5314 .get_smbase = emulator_get_smbase,
5315 .set_smbase = emulator_set_smbase,
717746e3
AK		 5316 .set_msr = emulator_set_msr,
5317 .get_msr = emulator_get_msr,
67f4d428 5318 .check_pmc = emulator_check_pmc,
222d21aa 5319 .read_pmc = emulator_read_pmc,
6c3287f7 5320 .halt = emulator_halt,
bcaf5cc5 5321 .wbinvd = emulator_wbinvd,
d6aa1000 5322 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5323 .get_fpu = emulator_get_fpu,
5324 .put_fpu = emulator_put_fpu,
c4f035c6 5325 .intercept = emulator_intercept,
bdb42f5a 5326 .get_cpuid = emulator_get_cpuid,
801806d9 5327 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5328 .get_hflags = emulator_get_hflags,
5329 .set_hflags = emulator_set_hflags,
0234bf88 5330 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5331};
5332
95cb2295
GN		 5333static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5334{
37ccdcbe 5335 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5336 /*
5337 * an sti; sti; sequence only disable interrupts for the first
5338 * instruction. So, if the last instruction, be it emulated or
5339 * not, left the system with the INT_STI flag enabled, it
5340 * means that the last instruction is an sti. We should not
5341 * leave the flag on in this case. The same goes for mov ss
5342 */
37ccdcbe
PB		 5343 if (int_shadow & mask)
5344 mask = 0;
6addfc42 5345 if (unlikely(int_shadow || mask)) {
95cb2295 5346 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5347 if (!mask)
5348 kvm_make_request(KVM_REQ_EVENT, vcpu);
5349 }
95cb2295
GN		 5350}
5351
ef54bcfe 5352static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5353{
5354 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5355 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5356 return kvm_propagate_fault(vcpu, &ctxt->exception);
5357
5358 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5359 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5360 ctxt->exception.error_code);
54b8486f 5361 else
da9cb575 5362 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5363 return false;
54b8486f
GN		 5364}
5365
8ec4722d
MG		 5366static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5367{
adf52235 5368 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5369 int cs_db, cs_l;
5370
8ec4722d
MG		 5371 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5372
adf52235 5373 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5374 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5375
adf52235
TY		 5376 ctxt->eip = kvm_rip_read(vcpu);
5377 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5378 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5379 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5380 cs_db ? X86EMUL_MODE_PROT32 :
5381 X86EMUL_MODE_PROT16;
a584539b 5382 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5383 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5384 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5385
dd856efa 5386 init_decode_cache(ctxt);
7ae441ea 5387 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5388}
5389
71f9833b 5390int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5391{
9d74191a 5392 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5393 int ret;
5394
5395 init_emulate_ctxt(vcpu);
5396
9dac77fa
AK		 5397 ctxt->op_bytes = 2;
5398 ctxt->ad_bytes = 2;
5399 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5400 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5401
5402 if (ret != X86EMUL_CONTINUE)
5403 return EMULATE_FAIL;
5404
9dac77fa 5405 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5406 kvm_rip_write(vcpu, ctxt->eip);
5407 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5408
5409 if (irq == NMI_VECTOR)
7460fb4a 5410 vcpu->arch.nmi_pending = 0;
63995653
MG		 5411 else
5412 vcpu->arch.interrupt.pending = false;
5413
5414 return EMULATE_DONE;
5415}
5416EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5417
6d77dbfc
GN		 5418static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5419{
fc3a9157
JR		 5420 int r = EMULATE_DONE;
5421
6d77dbfc
GN		 5422 ++vcpu->stat.insn_emulation_fail;
5423 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5424 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5425 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5426 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5427 vcpu->run->internal.ndata = 0;
5428 r = EMULATE_FAIL;
5429 }
6d77dbfc 5430 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5431
5432 return r;
6d77dbfc
GN		 5433}
5434
93c05d3e 5435static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5436 bool write_fault_to_shadow_pgtable,
5437 int emulation_type)
a6f177ef 5438{
95b3cf69 5439 gpa_t gpa = cr2;
ba049e93 5440 kvm_pfn_t pfn;
a6f177ef 5441
991eebf9
GN		 5442 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5443 return false;
5444
95b3cf69
XG		 5445 if (!vcpu->arch.mmu.direct_map) {
5446 /*
5447 * Write permission should be allowed since only
5448 * write access need to be emulated.
5449 */
5450 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5451
95b3cf69
XG		 5452 /*
5453 * If the mapping is invalid in guest, let cpu retry
5454 * it to generate fault.
5455 */
5456 if (gpa == UNMAPPED_GVA)
5457 return true;
5458 }
a6f177ef 5459
8e3d9d06
XG		 5460 /*
5461 * Do not retry the unhandleable instruction if it faults on the
5462 * readonly host memory, otherwise it will goto a infinite loop:
5463 * retry instruction -> write #PF -> emulation fail -> retry
5464 * instruction -> ...
5465 */
5466 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5467
5468 /*
5469 * If the instruction failed on the error pfn, it can not be fixed,
5470 * report the error to userspace.
5471 */
5472 if (is_error_noslot_pfn(pfn))
5473 return false;
5474
5475 kvm_release_pfn_clean(pfn);
5476
5477 /* The instructions are well-emulated on direct mmu. */
5478 if (vcpu->arch.mmu.direct_map) {
5479 unsigned int indirect_shadow_pages;
5480
5481 spin_lock(&vcpu->kvm->mmu_lock);
5482 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5483 spin_unlock(&vcpu->kvm->mmu_lock);
5484
5485 if (indirect_shadow_pages)
5486 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5487
a6f177ef 5488 return true;
8e3d9d06 5489 }
a6f177ef 5490
95b3cf69
XG		 5491 /*
5492 * if emulation was due to access to shadowed page table
5493 * and it failed try to unshadow page and re-enter the
5494 * guest to let CPU execute the instruction.
5495 */
5496 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5497
5498 /*
5499 * If the access faults on its page table, it can not
5500 * be fixed by unprotecting shadow page and it should
5501 * be reported to userspace.
5502 */
5503 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5504}
5505
1cb3f3ae
XG		 5506static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5507 unsigned long cr2, int emulation_type)
5508{
5509 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5510 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5511
5512 last_retry_eip = vcpu->arch.last_retry_eip;
5513 last_retry_addr = vcpu->arch.last_retry_addr;
5514
5515 /*
5516 * If the emulation is caused by #PF and it is non-page_table
5517 * writing instruction, it means the VM-EXIT is caused by shadow
5518 * page protected, we can zap the shadow page and retry this
5519 * instruction directly.
5520 *
5521 * Note: if the guest uses a non-page-table modifying instruction
5522 * on the PDE that points to the instruction, then we will unmap
5523 * the instruction and go to an infinite loop. So, we cache the
5524 * last retried eip and the last fault address, if we meet the eip
5525 * and the address again, we can break out of the potential infinite
5526 * loop.
5527 */
5528 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5529
5530 if (!(emulation_type & EMULTYPE_RETRY))
5531 return false;
5532
5533 if (x86_page_table_writing_insn(ctxt))
5534 return false;
5535
5536 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5537 return false;
5538
5539 vcpu->arch.last_retry_eip = ctxt->eip;
5540 vcpu->arch.last_retry_addr = cr2;
5541
5542 if (!vcpu->arch.mmu.direct_map)
5543 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5544
22368028 5545 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5546
5547 return true;
5548}
5549
716d51ab
GN		 5550static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5551static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5552
64d60670 5553static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5554{
64d60670 5555 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5556 /* This is a good place to trace that we are exiting SMM. */
5557 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5558
c43203ca
PB		 5559 /* Process a latched INIT or SMI, if any. */
5560 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5561 }
699023e2
PB		 5562
5563 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5564}
5565
5566static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5567{
5568 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5569
a584539b 5570 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5571
5572 if (changed & HF_SMM_MASK)
5573 kvm_smm_changed(vcpu);
a584539b
PB		 5574}
5575
4a1e10d5
PB		 5576static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5577 unsigned long *db)
5578{
5579 u32 dr6 = 0;
5580 int i;
5581 u32 enable, rwlen;
5582
5583 enable = dr7;
5584 rwlen = dr7 >> 16;
5585 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5586 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5587 dr6 |= (1 << i);
5588 return dr6;
5589}
5590
c8401dda 5591static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5592{
5593 struct kvm_run *kvm_run = vcpu->run;
5594
c8401dda
PB		 5595 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5596 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5597 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5598 kvm_run->debug.arch.exception = DB_VECTOR;
5599 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5600 *r = EMULATE_USER_EXIT;
5601 } else {
5602 /*
5603 * "Certain debug exceptions may clear bit 0-3. The
5604 * remaining contents of the DR6 register are never
5605 * cleared by the processor".
5606 */
5607 vcpu->arch.dr6 &= ~15;
5608 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5609 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5610 }
5611}
5612
6affcbed
KH		 5613int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5614{
5615 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5616 int r = EMULATE_DONE;
5617
5618 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5619
5620 /*
5621 * rflags is the old, "raw" value of the flags. The new value has
5622 * not been saved yet.
5623 *
5624 * This is correct even for TF set by the guest, because "the
5625 * processor will not generate this exception after the instruction
5626 * that sets the TF flag".
5627 */
5628 if (unlikely(rflags & X86_EFLAGS_TF))
5629 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5630 return r == EMULATE_DONE;
5631}
5632EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5633
4a1e10d5
PB		 5634static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5635{
4a1e10d5
PB		 5636 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5637 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5638 struct kvm_run *kvm_run = vcpu->run;
5639 unsigned long eip = kvm_get_linear_rip(vcpu);
5640 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5641 vcpu->arch.guest_debug_dr7,
5642 vcpu->arch.eff_db);
5643
5644 if (dr6 != 0) {
6f43ed01 5645 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5646 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5647 kvm_run->debug.arch.exception = DB_VECTOR;
5648 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5649 *r = EMULATE_USER_EXIT;
5650 return true;
5651 }
5652 }
5653
4161a569
NA		 5654 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5655 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5656 unsigned long eip = kvm_get_linear_rip(vcpu);
5657 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5658 vcpu->arch.dr7,
5659 vcpu->arch.db);
5660
5661 if (dr6 != 0) {
5662 vcpu->arch.dr6 &= ~15;
6f43ed01 5663 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5664 kvm_queue_exception(vcpu, DB_VECTOR);
5665 *r = EMULATE_DONE;
5666 return true;
5667 }
5668 }
5669
5670 return false;
5671}
5672
51d8b661
AP		 5673int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5674 unsigned long cr2,
dc25e89e
AP		 5675 int emulation_type,
5676 void *insn,
5677 int insn_len)
bbd9b64e 5678{
95cb2295 5679 int r;
9d74191a 5680 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5681 bool writeback = true;
93c05d3e 5682 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5683
93c05d3e
XG		 5684 /*
5685 * Clear write_fault_to_shadow_pgtable here to ensure it is
5686 * never reused.
5687 */
5688 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5689 kvm_clear_exception_queue(vcpu);
8d7d8102 5690
571008da 5691 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5692 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5693
5694 /*
5695 * We will reenter on the same instruction since
5696 * we do not set complete_userspace_io. This does not
5697 * handle watchpoints yet, those would be handled in
5698 * the emulate_ops.
5699 */
5700 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5701 return r;
5702
9d74191a
TY		 5703 ctxt->interruptibility = 0;
5704 ctxt->have_exception = false;
e0ad0b47 5705 ctxt->exception.vector = -1;
9d74191a 5706 ctxt->perm_ok = false;
bbd9b64e 5707
b51e974f 5708 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5709
9d74191a 5710 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5711
e46479f8 5712 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5713 ++vcpu->stat.insn_emulation;
1d2887e2 5714 if (r != EMULATION_OK) {
4005996e
AK		 5715 if (emulation_type & EMULTYPE_TRAP_UD)
5716 return EMULATE_FAIL;
991eebf9
GN		 5717 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5718 emulation_type))
bbd9b64e 5719 return EMULATE_DONE;
6d77dbfc
GN		 5720 if (emulation_type & EMULTYPE_SKIP)
5721 return EMULATE_FAIL;
5722 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5723 }
5724 }
5725
ba8afb6b 5726 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5727 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5728 if (ctxt->eflags & X86_EFLAGS_RF)
5729 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5730 return EMULATE_DONE;
5731 }
5732
1cb3f3ae
XG		 5733 if (retry_instruction(ctxt, cr2, emulation_type))
5734 return EMULATE_DONE;
5735
7ae441ea 5736 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5737 changes registers values during IO operation */
7ae441ea
GN		 5738 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5739 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5740 emulator_invalidate_register_cache(ctxt);
7ae441ea 5741 }
4d2179e1 5742
5cd21917 5743restart:
0f89b207
TL		 5744 /* Save the faulting GPA (cr2) in the address field */
5745 ctxt->exception.address = cr2;
5746
9d74191a 5747 r = x86_emulate_insn(ctxt);
bbd9b64e 5748
775fde86
JR		 5749 if (r == EMULATION_INTERCEPTED)
5750 return EMULATE_DONE;
5751
d2ddd1c4 5752 if (r == EMULATION_FAILED) {
991eebf9
GN		 5753 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5754 emulation_type))
c3cd7ffa
GN		 5755 return EMULATE_DONE;
5756
6d77dbfc 5757 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5758 }
5759
9d74191a 5760 if (ctxt->have_exception) {
d2ddd1c4 5761 r = EMULATE_DONE;
ef54bcfe
PB		 5762 if (inject_emulated_exception(vcpu))
5763 return r;
d2ddd1c4 5764 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5765 if (!vcpu->arch.pio.in) {
5766 /* FIXME: return into emulator if single-stepping. */
3457e419 5767 vcpu->arch.pio.count = 0;
0912c977 5768 } else {
7ae441ea 5769 writeback = false;
716d51ab
GN		 5770 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5771 }
ac0a48c3 5772 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5773 } else if (vcpu->mmio_needed) {
5774 if (!vcpu->mmio_is_write)
5775 writeback = false;
ac0a48c3 5776 r = EMULATE_USER_EXIT;
716d51ab 5777 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5778 } else if (r == EMULATION_RESTART)
5cd21917 5779 goto restart;
d2ddd1c4
GN		 5780 else
5781 r = EMULATE_DONE;
f850e2e6 5782
7ae441ea 5783 if (writeback) {
6addfc42 5784 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5785 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5786 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5787 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5788 if (r == EMULATE_DONE &&
5789 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5790 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5791 if (!ctxt->have_exception ||
5792 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5793 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5794
5795 /*
5796 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5797 * do nothing, and it will be requested again as soon as
5798 * the shadow expires. But we still need to check here,
5799 * because POPF has no interrupt shadow.
5800 */
5801 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5802 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5803 } else
5804 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5805
5806 return r;
de7d789a 5807}
51d8b661 5808EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5809
cf8f70bf 5810int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5811{
cf8f70bf 5812 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5813 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5814 size, port, &val, 1);
cf8f70bf 5815 /* do not return to emulator after return from userspace */
7972995b 5816 vcpu->arch.pio.count = 0;
de7d789a
CO		 5817 return ret;
5818}
cf8f70bf 5819EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5820
8370c3d0
TL		 5821static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5822{
5823 unsigned long val;
5824
5825 /* We should only ever be called with arch.pio.count equal to 1 */
5826 BUG_ON(vcpu->arch.pio.count != 1);
5827
5828 /* For size less than 4 we merge, else we zero extend */
5829 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5830 : 0;
5831
5832 /*
5833 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5834 * the copy and tracing
5835 */
5836 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5837 vcpu->arch.pio.port, &val, 1);
5838 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5839
5840 return 1;
5841}
5842
5843int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5844{
5845 unsigned long val;
5846 int ret;
5847
5848 /* For size less than 4 we merge, else we zero extend */
5849 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5850
5851 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5852 &val, 1);
5853 if (ret) {
5854 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5855 return ret;
5856 }
5857
5858 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5859
5860 return 0;
5861}
5862EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5863
251a5fd6 5864static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5865{
0a3aee0d 5866 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5867 return 0;
8cfdc000
ZA		 5868}
5869
5870static void tsc_khz_changed(void *data)
c8076604 5871{
8cfdc000
ZA		 5872 struct cpufreq_freqs *freq = data;
5873 unsigned long khz = 0;
5874
5875 if (data)
5876 khz = freq->new;
5877 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5878 khz = cpufreq_quick_get(raw_smp_processor_id());
5879 if (!khz)
5880 khz = tsc_khz;
0a3aee0d 5881 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5882}
5883
c8076604
GH		 5884static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5885 void *data)
5886{
5887 struct cpufreq_freqs *freq = data;
5888 struct kvm *kvm;
5889 struct kvm_vcpu *vcpu;
5890 int i, send_ipi = 0;
5891
8cfdc000
ZA		 5892 /*
5893 * We allow guests to temporarily run on slowing clocks,
5894 * provided we notify them after, or to run on accelerating
5895 * clocks, provided we notify them before. Thus time never
5896 * goes backwards.
5897 *
5898 * However, we have a problem. We can't atomically update
5899 * the frequency of a given CPU from this function; it is
5900 * merely a notifier, which can be called from any CPU.
5901 * Changing the TSC frequency at arbitrary points in time
5902 * requires a recomputation of local variables related to
5903 * the TSC for each VCPU. We must flag these local variables
5904 * to be updated and be sure the update takes place with the
5905 * new frequency before any guests proceed.
5906 *
5907 * Unfortunately, the combination of hotplug CPU and frequency
5908 * change creates an intractable locking scenario; the order
5909 * of when these callouts happen is undefined with respect to
5910 * CPU hotplug, and they can race with each other. As such,
5911 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5912 * undefined; you can actually have a CPU frequency change take
5913 * place in between the computation of X and the setting of the
5914 * variable. To protect against this problem, all updates of
5915 * the per_cpu tsc_khz variable are done in an interrupt
5916 * protected IPI, and all callers wishing to update the value
5917 * must wait for a synchronous IPI to complete (which is trivial
5918 * if the caller is on the CPU already). This establishes the
5919 * necessary total order on variable updates.
5920 *
5921 * Note that because a guest time update may take place
5922 * anytime after the setting of the VCPU's request bit, the
5923 * correct TSC value must be set before the request. However,
5924 * to ensure the update actually makes it to any guest which
5925 * starts running in hardware virtualization between the set
5926 * and the acquisition of the spinlock, we must also ping the
5927 * CPU after setting the request bit.
5928 *
5929 */
5930
c8076604
GH		 5931 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5932 return 0;
5933 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5934 return 0;
8cfdc000
ZA		 5935
5936 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5937
2f303b74 5938 spin_lock(&kvm_lock);
c8076604 5939 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5940 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5941 if (vcpu->cpu != freq->cpu)
5942 continue;
c285545f 5943 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5944 if (vcpu->cpu != smp_processor_id())
8cfdc000 5945 send_ipi = 1;
c8076604
GH		 5946 }
5947 }
2f303b74 5948 spin_unlock(&kvm_lock);
c8076604
GH		 5949
5950 if (freq->old < freq->new && send_ipi) {
5951 /*
5952 * We upscale the frequency. Must make the guest
5953 * doesn't see old kvmclock values while running with
5954 * the new frequency, otherwise we risk the guest sees
5955 * time go backwards.
5956 *
5957 * In case we update the frequency for another cpu
5958 * (which might be in guest context) send an interrupt
5959 * to kick the cpu out of guest context. Next time
5960 * guest context is entered kvmclock will be updated,
5961 * so the guest will not see stale values.
5962 */
8cfdc000 5963 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5964 }
5965 return 0;
5966}
5967
5968static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5969 .notifier_call = kvmclock_cpufreq_notifier
5970};
5971
251a5fd6 5972static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5973{
251a5fd6
SAS		 5974 tsc_khz_changed(NULL);
5975 return 0;
8cfdc000
ZA		 5976}
5977
b820cc0c
ZA		 5978static void kvm_timer_init(void)
5979{
c285545f 5980 max_tsc_khz = tsc_khz;
460dd42e 5981
b820cc0c 5982 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5983#ifdef CONFIG_CPU_FREQ
5984 struct cpufreq_policy policy;
758f588d
BP		 5985 int cpu;
5986
c285545f 5987 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5988 cpu = get_cpu();
5989 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5990 if (policy.cpuinfo.max_freq)
5991 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5992 put_cpu();
c285545f 5993#endif
b820cc0c
ZA		 5994 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5995 CPUFREQ_TRANSITION_NOTIFIER);
5996 }
c285545f 5997 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5998
73c1b41e 5999 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6000 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6001}
6002
ff9d07a0
ZY		 6003static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6004
f5132b01 6005int kvm_is_in_guest(void)
ff9d07a0 6006{
086c9855 6007 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6008}
6009
6010static int kvm_is_user_mode(void)
6011{
6012 int user_mode = 3;
dcf46b94 6013
086c9855
AS		 6014 if (__this_cpu_read(current_vcpu))
6015 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6016
ff9d07a0
ZY		 6017 return user_mode != 0;
6018}
6019
6020static unsigned long kvm_get_guest_ip(void)
6021{
6022 unsigned long ip = 0;
dcf46b94 6023
086c9855
AS		 6024 if (__this_cpu_read(current_vcpu))
6025 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6026
ff9d07a0
ZY		 6027 return ip;
6028}
6029
6030static struct perf_guest_info_callbacks kvm_guest_cbs = {
6031 .is_in_guest = kvm_is_in_guest,
6032 .is_user_mode = kvm_is_user_mode,
6033 .get_guest_ip = kvm_get_guest_ip,
6034};
6035
6036void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6037{
086c9855 6038 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6039}
6040EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6041
6042void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6043{
086c9855 6044 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6045}
6046EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6047
ce88decf
XG		 6048static void kvm_set_mmio_spte_mask(void)
6049{
6050 u64 mask;
6051 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6052
6053 /*
6054 * Set the reserved bits and the present bit of an paging-structure
6055 * entry to generate page fault with PFER.RSV = 1.
6056 */
885032b9 6057 /* Mask the reserved physical address bits. */
d1431483 6058 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6059
885032b9 6060 /* Set the present bit. */
ce88decf
XG		 6061 mask |= 1ull;
6062
6063#ifdef CONFIG_X86_64
6064 /*
6065 * If reserved bit is not supported, clear the present bit to disable
6066 * mmio page fault.
6067 */
6068 if (maxphyaddr == 52)
6069 mask &= ~1ull;
6070#endif
6071
dcdca5fe 6072 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6073}
6074
16e8d74d
MT		 6075#ifdef CONFIG_X86_64
6076static void pvclock_gtod_update_fn(struct work_struct *work)
6077{
d828199e
MT		 6078 struct kvm *kvm;
6079
6080 struct kvm_vcpu *vcpu;
6081 int i;
6082
2f303b74 6083 spin_lock(&kvm_lock);
d828199e
MT		 6084 list_for_each_entry(kvm, &vm_list, vm_list)
6085 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6086 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6087 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6088 spin_unlock(&kvm_lock);
16e8d74d
MT		 6089}
6090
6091static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6092
6093/*
6094 * Notification about pvclock gtod data update.
6095 */
6096static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6097 void *priv)
6098{
6099 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6100 struct timekeeper *tk = priv;
6101
6102 update_pvclock_gtod(tk);
6103
6104 /* disable master clock if host does not trust, or does not
6105 * use, TSC clocksource
6106 */
6107 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6108 atomic_read(&kvm_guest_has_master_clock) != 0)
6109 queue_work(system_long_wq, &pvclock_gtod_work);
6110
6111 return 0;
6112}
6113
6114static struct notifier_block pvclock_gtod_notifier = {
6115 .notifier_call = pvclock_gtod_notify,
6116};
6117#endif
6118
f8c16bba 6119int kvm_arch_init(void *opaque)
043405e1 6120{
b820cc0c 6121 int r;
6b61edf7 6122 struct kvm_x86_ops *ops = opaque;
f8c16bba 6123
f8c16bba
ZX		 6124 if (kvm_x86_ops) {
6125 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6126 r = -EEXIST;
6127 goto out;
f8c16bba
ZX		 6128 }
6129
6130 if (!ops->cpu_has_kvm_support()) {
6131 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6132 r = -EOPNOTSUPP;
6133 goto out;
f8c16bba
ZX		 6134 }
6135 if (ops->disabled_by_bios()) {
6136 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6137 r = -EOPNOTSUPP;
6138 goto out;
f8c16bba
ZX		 6139 }
6140
013f6a5d
MT		 6141 r = -ENOMEM;
6142 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6143 if (!shared_msrs) {
6144 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6145 goto out;
6146 }
6147
97db56ce
AK		 6148 r = kvm_mmu_module_init();
6149 if (r)
013f6a5d 6150 goto out_free_percpu;
97db56ce 6151
ce88decf 6152 kvm_set_mmio_spte_mask();
97db56ce 6153
f8c16bba 6154 kvm_x86_ops = ops;
920c8377 6155
7b52345e 6156 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6157 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6158 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6159 kvm_timer_init();
c8076604 6160
ff9d07a0
ZY		 6161 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6162
d366bf7e 6163 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6164 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6165
c5cc421b 6166 kvm_lapic_init();
16e8d74d
MT		 6167#ifdef CONFIG_X86_64
6168 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6169#endif
6170
f8c16bba 6171 return 0;
56c6d28a 6172
013f6a5d
MT		 6173out_free_percpu:
6174 free_percpu(shared_msrs);
56c6d28a 6175out:
56c6d28a 6176 return r;
043405e1 6177}
8776e519 6178
f8c16bba
ZX		 6179void kvm_arch_exit(void)
6180{
cef84c30 6181 kvm_lapic_exit();
ff9d07a0
ZY		 6182 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6183
888d256e
JK		 6184 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6185 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6186 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6187 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6188#ifdef CONFIG_X86_64
6189 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6190#endif
f8c16bba 6191 kvm_x86_ops = NULL;
56c6d28a 6192 kvm_mmu_module_exit();
013f6a5d 6193 free_percpu(shared_msrs);
56c6d28a 6194}
f8c16bba 6195
5cb56059 6196int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6197{
6198 ++vcpu->stat.halt_exits;
35754c98 6199 if (lapic_in_kernel(vcpu)) {
a4535290 6200 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6201 return 1;
6202 } else {
6203 vcpu->run->exit_reason = KVM_EXIT_HLT;
6204 return 0;
6205 }
6206}
5cb56059
JS		 6207EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6208
6209int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6210{
6affcbed
KH		 6211 int ret = kvm_skip_emulated_instruction(vcpu);
6212 /*
6213 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6214 * KVM_EXIT_DEBUG here.
6215 */
6216 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6217}
8776e519
HB		 6218EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6219
8ef81a9a 6220#ifdef CONFIG_X86_64
55dd00a7
MT		 6221static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6222 unsigned long clock_type)
6223{
6224 struct kvm_clock_pairing clock_pairing;
6225 struct timespec ts;
80fbd89c 6226 u64 cycle;
55dd00a7
MT		 6227 int ret;
6228
6229 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6230 return -KVM_EOPNOTSUPP;
6231
6232 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6233 return -KVM_EOPNOTSUPP;
6234
6235 clock_pairing.sec = ts.tv_sec;
6236 clock_pairing.nsec = ts.tv_nsec;
6237 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6238 clock_pairing.flags = 0;
6239
6240 ret = 0;
6241 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6242 sizeof(struct kvm_clock_pairing)))
6243 ret = -KVM_EFAULT;
6244
6245 return ret;
6246}
8ef81a9a 6247#endif
55dd00a7 6248
6aef266c
SV		 6249/*
6250 * kvm_pv_kick_cpu_op: Kick a vcpu.
6251 *
6252 * @apicid - apicid of vcpu to be kicked.
6253 */
6254static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6255{
24d2166b 6256 struct kvm_lapic_irq lapic_irq;
6aef266c 6257
24d2166b
R		 6258 lapic_irq.shorthand = 0;
6259 lapic_irq.dest_mode = 0;
ebd28fcb 6260 lapic_irq.level = 0;
24d2166b 6261 lapic_irq.dest_id = apicid;
93bbf0b8 6262 lapic_irq.msi_redir_hint = false;
6aef266c 6263
24d2166b 6264 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6265 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6266}
6267
d62caabb
AS		 6268void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6269{
6270 vcpu->arch.apicv_active = false;
6271 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6272}
6273
8776e519
HB		 6274int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6275{
6276 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6277 int op_64_bit, r;
8776e519 6278
6affcbed 6279 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6280
55cd8e5a
GN		 6281 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6282 return kvm_hv_hypercall(vcpu);
6283
5fdbf976
MT		 6284 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6285 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6286 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6287 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6288 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6289
229456fc 6290 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6291
a449c7aa
NA		 6292 op_64_bit = is_64_bit_mode(vcpu);
6293 if (!op_64_bit) {
8776e519
HB		 6294 nr &= 0xFFFFFFFF;
6295 a0 &= 0xFFFFFFFF;
6296 a1 &= 0xFFFFFFFF;
6297 a2 &= 0xFFFFFFFF;
6298 a3 &= 0xFFFFFFFF;
6299 }
6300
07708c4a
JK		 6301 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6302 ret = -KVM_EPERM;
6303 goto out;
6304 }
6305
8776e519 6306 switch (nr) {
b93463aa
AK		 6307 case KVM_HC_VAPIC_POLL_IRQ:
6308 ret = 0;
6309 break;
6aef266c
SV		 6310 case KVM_HC_KICK_CPU:
6311 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6312 ret = 0;
6313 break;
8ef81a9a 6314#ifdef CONFIG_X86_64
55dd00a7
MT		 6315 case KVM_HC_CLOCK_PAIRING:
6316 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6317 break;
8ef81a9a 6318#endif
8776e519
HB		 6319 default:
6320 ret = -KVM_ENOSYS;
6321 break;
6322 }
07708c4a 6323out:
a449c7aa
NA		 6324 if (!op_64_bit)
6325 ret = (u32)ret;
5fdbf976 6326 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6327 ++vcpu->stat.hypercalls;
2f333bcb 6328 return r;
8776e519
HB		 6329}
6330EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6331
b6785def 6332static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6333{
d6aa1000 6334 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6335 char instruction[3];
5fdbf976 6336 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6337
8776e519 6338 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6339
ce2e852e
DV		 6340 return emulator_write_emulated(ctxt, rip, instruction, 3,
6341 &ctxt->exception);
8776e519
HB		 6342}
6343
851ba692 6344static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6345{
782d422b
MG		 6346 return vcpu->run->request_interrupt_window &&
6347 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6348}
6349
851ba692 6350static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6351{
851ba692
AK		 6352 struct kvm_run *kvm_run = vcpu->run;
6353
91586a3b 6354 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6355 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6356 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6357 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6358 kvm_run->ready_for_interrupt_injection =
6359 pic_in_kernel(vcpu->kvm) ||
782d422b 6360 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6361}
6362
95ba8273
GN		 6363static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6364{
6365 int max_irr, tpr;
6366
6367 if (!kvm_x86_ops->update_cr8_intercept)
6368 return;
6369
bce87cce 6370 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6371 return;
6372
d62caabb
AS		 6373 if (vcpu->arch.apicv_active)
6374 return;
6375
8db3baa2
GN		 6376 if (!vcpu->arch.apic->vapic_addr)
6377 max_irr = kvm_lapic_find_highest_irr(vcpu);
6378 else
6379 max_irr = -1;
95ba8273
GN		 6380
6381 if (max_irr != -1)
6382 max_irr >>= 4;
6383
6384 tpr = kvm_lapic_get_cr8(vcpu);
6385
6386 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6387}
6388
b6b8a145 6389static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6390{
b6b8a145
JK		 6391 int r;
6392
95ba8273 6393 /* try to reinject previous events if any */
664f8e26
WL		 6394 if (vcpu->arch.exception.injected) {
6395 kvm_x86_ops->queue_exception(vcpu);
6396 return 0;
6397 }
6398
6399 /*
6400 * Exceptions must be injected immediately, or the exception
6401 * frame will have the address of the NMI or interrupt handler.
6402 */
6403 if (!vcpu->arch.exception.pending) {
6404 if (vcpu->arch.nmi_injected) {
6405 kvm_x86_ops->set_nmi(vcpu);
6406 return 0;
6407 }
6408
6409 if (vcpu->arch.interrupt.pending) {
6410 kvm_x86_ops->set_irq(vcpu);
6411 return 0;
6412 }
6413 }
6414
6415 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6416 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6417 if (r != 0)
6418 return r;
6419 }
6420
6421 /* try to inject new event if pending */
b59bb7bd 6422 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6423 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6424 vcpu->arch.exception.has_error_code,
6425 vcpu->arch.exception.error_code);
d6e8c854 6426
664f8e26
WL		 6427 vcpu->arch.exception.pending = false;
6428 vcpu->arch.exception.injected = true;
6429
d6e8c854
NA		 6430 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6431 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6432 X86_EFLAGS_RF);
6433
6bdf0662
NA		 6434 if (vcpu->arch.exception.nr == DB_VECTOR &&
6435 (vcpu->arch.dr7 & DR7_GD)) {
6436 vcpu->arch.dr7 &= ~DR7_GD;
6437 kvm_update_dr7(vcpu);
6438 }
6439
cfcd20e5 6440 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6441 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6442 vcpu->arch.smi_pending = false;
ee2cd4b7 6443 enter_smm(vcpu);
c43203ca 6444 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6445 --vcpu->arch.nmi_pending;
6446 vcpu->arch.nmi_injected = true;
6447 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6448 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6449 /*
6450 * Because interrupts can be injected asynchronously, we are
6451 * calling check_nested_events again here to avoid a race condition.
6452 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6453 * proposal and current concerns. Perhaps we should be setting
6454 * KVM_REQ_EVENT only on certain events and not unconditionally?
6455 */
6456 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6457 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6458 if (r != 0)
6459 return r;
6460 }
95ba8273 6461 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6462 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6463 false);
6464 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6465 }
6466 }
ee2cd4b7 6467
b6b8a145 6468 return 0;
95ba8273
GN		 6469}
6470
7460fb4a
AK		 6471static void process_nmi(struct kvm_vcpu *vcpu)
6472{
6473 unsigned limit = 2;
6474
6475 /*
6476 * x86 is limited to one NMI running, and one NMI pending after it.
6477 * If an NMI is already in progress, limit further NMIs to just one.
6478 * Otherwise, allow two (and we'll inject the first one immediately).
6479 */
6480 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6481 limit = 1;
6482
6483 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6484 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6485 kvm_make_request(KVM_REQ_EVENT, vcpu);
6486}
6487
ee2cd4b7 6488static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6489{
6490 u32 flags = 0;
6491 flags |= seg->g << 23;
6492 flags |= seg->db << 22;
6493 flags |= seg->l << 21;
6494 flags |= seg->avl << 20;
6495 flags |= seg->present << 15;
6496 flags |= seg->dpl << 13;
6497 flags |= seg->s << 12;
6498 flags |= seg->type << 8;
6499 return flags;
6500}
6501
ee2cd4b7 6502static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6503{
6504 struct kvm_segment seg;
6505 int offset;
6506
6507 kvm_get_segment(vcpu, &seg, n);
6508 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6509
6510 if (n < 3)
6511 offset = 0x7f84 + n * 12;
6512 else
6513 offset = 0x7f2c + (n - 3) * 12;
6514
6515 put_smstate(u32, buf, offset + 8, seg.base);
6516 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6517 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6518}
6519
efbb288a 6520#ifdef CONFIG_X86_64
ee2cd4b7 6521static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6522{
6523 struct kvm_segment seg;
6524 int offset;
6525 u16 flags;
6526
6527 kvm_get_segment(vcpu, &seg, n);
6528 offset = 0x7e00 + n * 16;
6529
ee2cd4b7 6530 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6531 put_smstate(u16, buf, offset, seg.selector);
6532 put_smstate(u16, buf, offset + 2, flags);
6533 put_smstate(u32, buf, offset + 4, seg.limit);
6534 put_smstate(u64, buf, offset + 8, seg.base);
6535}
efbb288a 6536#endif
660a5d51 6537
ee2cd4b7 6538static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6539{
6540 struct desc_ptr dt;
6541 struct kvm_segment seg;
6542 unsigned long val;
6543 int i;
6544
6545 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6546 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6547 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6548 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6549
6550 for (i = 0; i < 8; i++)
6551 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6552
6553 kvm_get_dr(vcpu, 6, &val);
6554 put_smstate(u32, buf, 0x7fcc, (u32)val);
6555 kvm_get_dr(vcpu, 7, &val);
6556 put_smstate(u32, buf, 0x7fc8, (u32)val);
6557
6558 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6559 put_smstate(u32, buf, 0x7fc4, seg.selector);
6560 put_smstate(u32, buf, 0x7f64, seg.base);
6561 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6562 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6563
6564 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6565 put_smstate(u32, buf, 0x7fc0, seg.selector);
6566 put_smstate(u32, buf, 0x7f80, seg.base);
6567 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6568 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6569
6570 kvm_x86_ops->get_gdt(vcpu, &dt);
6571 put_smstate(u32, buf, 0x7f74, dt.address);
6572 put_smstate(u32, buf, 0x7f70, dt.size);
6573
6574 kvm_x86_ops->get_idt(vcpu, &dt);
6575 put_smstate(u32, buf, 0x7f58, dt.address);
6576 put_smstate(u32, buf, 0x7f54, dt.size);
6577
6578 for (i = 0; i < 6; i++)
ee2cd4b7 6579 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6580
6581 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6582
6583 /* revision id */
6584 put_smstate(u32, buf, 0x7efc, 0x00020000);
6585 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6586}
6587
ee2cd4b7 6588static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6589{
6590#ifdef CONFIG_X86_64
6591 struct desc_ptr dt;
6592 struct kvm_segment seg;
6593 unsigned long val;
6594 int i;
6595
6596 for (i = 0; i < 16; i++)
6597 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6598
6599 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6600 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6601
6602 kvm_get_dr(vcpu, 6, &val);
6603 put_smstate(u64, buf, 0x7f68, val);
6604 kvm_get_dr(vcpu, 7, &val);
6605 put_smstate(u64, buf, 0x7f60, val);
6606
6607 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6608 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6609 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6610
6611 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6612
6613 /* revision id */
6614 put_smstate(u32, buf, 0x7efc, 0x00020064);
6615
6616 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6617
6618 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6619 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6620 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6621 put_smstate(u32, buf, 0x7e94, seg.limit);
6622 put_smstate(u64, buf, 0x7e98, seg.base);
6623
6624 kvm_x86_ops->get_idt(vcpu, &dt);
6625 put_smstate(u32, buf, 0x7e84, dt.size);
6626 put_smstate(u64, buf, 0x7e88, dt.address);
6627
6628 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6629 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6630 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6631 put_smstate(u32, buf, 0x7e74, seg.limit);
6632 put_smstate(u64, buf, 0x7e78, seg.base);
6633
6634 kvm_x86_ops->get_gdt(vcpu, &dt);
6635 put_smstate(u32, buf, 0x7e64, dt.size);
6636 put_smstate(u64, buf, 0x7e68, dt.address);
6637
6638 for (i = 0; i < 6; i++)
ee2cd4b7 6639 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6640#else
6641 WARN_ON_ONCE(1);
6642#endif
6643}
6644
ee2cd4b7 6645static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6646{
660a5d51 6647 struct kvm_segment cs, ds;
18c3626e 6648 struct desc_ptr dt;
660a5d51
PB		 6649 char buf[512];
6650 u32 cr0;
6651
660a5d51 6652 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6653 memset(buf, 0, 512);
d6321d49 6654 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6655 enter_smm_save_state_64(vcpu, buf);
660a5d51 6656 else
ee2cd4b7 6657 enter_smm_save_state_32(vcpu, buf);
660a5d51 6658
0234bf88
LP		 6659 /*
6660 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6661 * vCPU state (e.g. leave guest mode) after we've saved the state into
6662 * the SMM state-save area.
6663 */
6664 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6665
6666 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6667 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6668
6669 if (kvm_x86_ops->get_nmi_mask(vcpu))
6670 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6671 else
6672 kvm_x86_ops->set_nmi_mask(vcpu, true);
6673
6674 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6675 kvm_rip_write(vcpu, 0x8000);
6676
6677 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6678 kvm_x86_ops->set_cr0(vcpu, cr0);
6679 vcpu->arch.cr0 = cr0;
6680
6681 kvm_x86_ops->set_cr4(vcpu, 0);
6682
18c3626e
PB		 6683 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6684 dt.address = dt.size = 0;
6685 kvm_x86_ops->set_idt(vcpu, &dt);
6686
660a5d51
PB		 6687 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6688
6689 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6690 cs.base = vcpu->arch.smbase;
6691
6692 ds.selector = 0;
6693 ds.base = 0;
6694
6695 cs.limit = ds.limit = 0xffffffff;
6696 cs.type = ds.type = 0x3;
6697 cs.dpl = ds.dpl = 0;
6698 cs.db = ds.db = 0;
6699 cs.s = ds.s = 1;
6700 cs.l = ds.l = 0;
6701 cs.g = ds.g = 1;
6702 cs.avl = ds.avl = 0;
6703 cs.present = ds.present = 1;
6704 cs.unusable = ds.unusable = 0;
6705 cs.padding = ds.padding = 0;
6706
6707 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6708 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6709 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6710 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6711 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6712 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6713
d6321d49 6714 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6715 kvm_x86_ops->set_efer(vcpu, 0);
6716
6717 kvm_update_cpuid(vcpu);
6718 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6719}
6720
ee2cd4b7 6721static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6722{
6723 vcpu->arch.smi_pending = true;
6724 kvm_make_request(KVM_REQ_EVENT, vcpu);
6725}
6726
2860c4b1
PB		 6727void kvm_make_scan_ioapic_request(struct kvm *kvm)
6728{
6729 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6730}
6731
3d81bc7e 6732static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6733{
5c919412
AS		 6734 u64 eoi_exit_bitmap[4];
6735
3d81bc7e
YZ		 6736 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6737 return;
c7c9c56c 6738
6308630b 6739 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6740
b053b2ae 6741 if (irqchip_split(vcpu->kvm))
6308630b 6742 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6743 else {
76dfafd5 6744 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6745 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6746 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6747 }
5c919412
AS		 6748 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6749 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6750 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6751}
6752
a70656b6
RK		 6753static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6754{
6755 ++vcpu->stat.tlb_flush;
6756 kvm_x86_ops->tlb_flush(vcpu);
6757}
6758
4256f43f
TC		 6759void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6760{
c24ae0dc
TC		 6761 struct page *page = NULL;
6762
35754c98 6763 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6764 return;
6765
4256f43f
TC		 6766 if (!kvm_x86_ops->set_apic_access_page_addr)
6767 return;
6768
c24ae0dc 6769 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6770 if (is_error_page(page))
6771 return;
c24ae0dc
TC		 6772 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6773
6774 /*
6775 * Do not pin apic access page in memory, the MMU notifier
6776 * will call us again if it is migrated or swapped out.
6777 */
6778 put_page(page);
4256f43f
TC		 6779}
6780EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6781
9357d939 6782/*
362c698f 6783 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6784 * exiting to the userspace. Otherwise, the value will be returned to the
6785 * userspace.
6786 */
851ba692 6787static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6788{
6789 int r;
62a193ed
MG		 6790 bool req_int_win =
6791 dm_request_for_irq_injection(vcpu) &&
6792 kvm_cpu_accept_dm_intr(vcpu);
6793
730dca42 6794 bool req_immediate_exit = false;
b6c7a5dc 6795
2fa6e1e1 6796 if (kvm_request_pending(vcpu)) {
a8eeb04a 6797 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6798 kvm_mmu_unload(vcpu);
a8eeb04a 6799 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6800 __kvm_migrate_timers(vcpu);
d828199e
MT		 6801 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6802 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6803 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6804 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6805 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6806 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6807 if (unlikely(r))
6808 goto out;
6809 }
a8eeb04a 6810 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6811 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6812 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6813 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6814 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6815 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6816 r = 0;
6817 goto out;
6818 }
a8eeb04a 6819 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6820 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6821 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6822 r = 0;
6823 goto out;
6824 }
af585b92
GN		 6825 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6826 /* Page is swapped out. Do synthetic halt */
6827 vcpu->arch.apf.halted = true;
6828 r = 1;
6829 goto out;
6830 }
c9aaa895
GC		 6831 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6832 record_steal_time(vcpu);
64d60670
PB		 6833 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6834 process_smi(vcpu);
7460fb4a
AK		 6835 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6836 process_nmi(vcpu);
f5132b01 6837 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6838 kvm_pmu_handle_event(vcpu);
f5132b01 6839 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6840 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6841 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6842 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6843 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6844 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6845 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6846 vcpu->run->eoi.vector =
6847 vcpu->arch.pending_ioapic_eoi;
6848 r = 0;
6849 goto out;
6850 }
6851 }
3d81bc7e
YZ		 6852 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6853 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6854 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6855 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6856 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6857 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6858 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6859 r = 0;
6860 goto out;
6861 }
e516cebb
AS		 6862 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6863 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6864 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6865 r = 0;
6866 goto out;
6867 }
db397571
AS		 6868 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6869 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6870 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6871 r = 0;
6872 goto out;
6873 }
f3b138c5
AS		 6874
6875 /*
6876 * KVM_REQ_HV_STIMER has to be processed after
6877 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6878 * depend on the guest clock being up-to-date
6879 */
1f4b34f8
AS		 6880 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6881 kvm_hv_process_stimers(vcpu);
2f52d58c 6882 }
b93463aa 6883
b463a6f7 6884 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6885 ++vcpu->stat.req_event;
66450a21
JK		 6886 kvm_apic_accept_events(vcpu);
6887 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6888 r = 1;
6889 goto out;
6890 }
6891
b6b8a145
JK		 6892 if (inject_pending_event(vcpu, req_int_win) != 0)
6893 req_immediate_exit = true;
321c5658 6894 else {
cc3d967f 6895 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6896 *
cc3d967f
LP		 6897 * SMIs have three cases:
6898 * 1) They can be nested, and then there is nothing to
6899 * do here because RSM will cause a vmexit anyway.
6900 * 2) There is an ISA-specific reason why SMI cannot be
6901 * injected, and the moment when this changes can be
6902 * intercepted.
6903 * 3) Or the SMI can be pending because
6904 * inject_pending_event has completed the injection
6905 * of an IRQ or NMI from the previous vmexit, and
6906 * then we request an immediate exit to inject the
6907 * SMI.
c43203ca
PB		 6908 */
6909 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6910 if (!kvm_x86_ops->enable_smi_window(vcpu))
6911 req_immediate_exit = true;
321c5658
YS		 6912 if (vcpu->arch.nmi_pending)
6913 kvm_x86_ops->enable_nmi_window(vcpu);
6914 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6915 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6916 WARN_ON(vcpu->arch.exception.pending);
321c5658 6917 }
b463a6f7
AK		 6918
6919 if (kvm_lapic_enabled(vcpu)) {
6920 update_cr8_intercept(vcpu);
6921 kvm_lapic_sync_to_vapic(vcpu);
6922 }
6923 }
6924
d8368af8
AK		 6925 r = kvm_mmu_reload(vcpu);
6926 if (unlikely(r)) {
d905c069 6927 goto cancel_injection;
d8368af8
AK		 6928 }
6929
b6c7a5dc
HB		 6930 preempt_disable();
6931
6932 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6933 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6934
6935 /*
6936 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6937 * IPI are then delayed after guest entry, which ensures that they
6938 * result in virtual interrupt delivery.
6939 */
6940 local_irq_disable();
6b7e2d09
XG		 6941 vcpu->mode = IN_GUEST_MODE;
6942
01b71917
MT		 6943 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6944
0f127d12 6945 /*
b95234c8 6946 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6947 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6948 *
6949 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6950 * pairs with the memory barrier implicit in pi_test_and_set_on
6951 * (see vmx_deliver_posted_interrupt).
6952 *
6953 * 3) This also orders the write to mode from any reads to the page
6954 * tables done while the VCPU is running. Please see the comment
6955 * in kvm_flush_remote_tlbs.
6b7e2d09 6956 */
01b71917 6957 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6958
b95234c8
PB		 6959 /*
6960 * This handles the case where a posted interrupt was
6961 * notified with kvm_vcpu_kick.
6962 */
6963 if (kvm_lapic_enabled(vcpu)) {
6964 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6965 kvm_x86_ops->sync_pir_to_irr(vcpu);
6966 }
32f88400 6967
2fa6e1e1 6968 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6969 || need_resched() || signal_pending(current)) {
6b7e2d09 6970 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6971 smp_wmb();
6c142801
AK		 6972 local_irq_enable();
6973 preempt_enable();
01b71917 6974 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6975 r = 1;
d905c069 6976 goto cancel_injection;
6c142801
AK		 6977 }
6978
fc5b7f3b
DM		 6979 kvm_load_guest_xcr0(vcpu);
6980
c43203ca
PB		 6981 if (req_immediate_exit) {
6982 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6983 smp_send_reschedule(vcpu->cpu);
c43203ca 6984 }
d6185f20 6985
8b89fe1f
PB		 6986 trace_kvm_entry(vcpu->vcpu_id);
6987 wait_lapic_expire(vcpu);
6edaa530 6988 guest_enter_irqoff();
b6c7a5dc 6989
42dbaa5a 6990 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6991 set_debugreg(0, 7);
6992 set_debugreg(vcpu->arch.eff_db[0], 0);
6993 set_debugreg(vcpu->arch.eff_db[1], 1);
6994 set_debugreg(vcpu->arch.eff_db[2], 2);
6995 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6996 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6997 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6998 }
b6c7a5dc 6999
851ba692 7000 kvm_x86_ops->run(vcpu);
b6c7a5dc 7001
c77fb5fe
PB		 7002 /*
7003 * Do this here before restoring debug registers on the host. And
7004 * since we do this before handling the vmexit, a DR access vmexit
7005 * can (a) read the correct value of the debug registers, (b) set
7006 * KVM_DEBUGREG_WONT_EXIT again.
7007 */
7008 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7009 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7010 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7011 kvm_update_dr0123(vcpu);
7012 kvm_update_dr6(vcpu);
7013 kvm_update_dr7(vcpu);
7014 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7015 }
7016
24f1e32c
FW		 7017 /*
7018 * If the guest has used debug registers, at least dr7
7019 * will be disabled while returning to the host.
7020 * If we don't have active breakpoints in the host, we don't
7021 * care about the messed up debug address registers. But if
7022 * we have some of them active, restore the old state.
7023 */
59d8eb53 7024 if (hw_breakpoint_active())
24f1e32c 7025 hw_breakpoint_restore();
42dbaa5a 7026
4ba76538 7027 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7028
6b7e2d09 7029 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7030 smp_wmb();
a547c6db 7031
fc5b7f3b
DM		 7032 kvm_put_guest_xcr0(vcpu);
7033
a547c6db 7034 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7035
7036 ++vcpu->stat.exits;
7037
f2485b3e 7038 guest_exit_irqoff();
b6c7a5dc 7039
f2485b3e 7040 local_irq_enable();
b6c7a5dc
HB		 7041 preempt_enable();
7042
f656ce01 7043 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7044
b6c7a5dc
HB		 7045 /*
7046 * Profile KVM exit RIPs:
7047 */
7048 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7049 unsigned long rip = kvm_rip_read(vcpu);
7050 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7051 }
7052
cc578287
ZA		 7053 if (unlikely(vcpu->arch.tsc_always_catchup))
7054 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7055
5cfb1d5a
MT		 7056 if (vcpu->arch.apic_attention)
7057 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7058
618232e2 7059 vcpu->arch.gpa_available = false;
851ba692 7060 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7061 return r;
7062
7063cancel_injection:
7064 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7065 if (unlikely(vcpu->arch.apic_attention))
7066 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7067out:
7068 return r;
7069}
b6c7a5dc 7070
362c698f
PB		 7071static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7072{
bf9f6ac8
FW		 7073 if (!kvm_arch_vcpu_runnable(vcpu) &&
7074 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7075 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7076 kvm_vcpu_block(vcpu);
7077 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7078
7079 if (kvm_x86_ops->post_block)
7080 kvm_x86_ops->post_block(vcpu);
7081
9c8fd1ba
PB		 7082 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7083 return 1;
7084 }
362c698f
PB		 7085
7086 kvm_apic_accept_events(vcpu);
7087 switch(vcpu->arch.mp_state) {
7088 case KVM_MP_STATE_HALTED:
7089 vcpu->arch.pv.pv_unhalted = false;
7090 vcpu->arch.mp_state =
7091 KVM_MP_STATE_RUNNABLE;
7092 case KVM_MP_STATE_RUNNABLE:
7093 vcpu->arch.apf.halted = false;
7094 break;
7095 case KVM_MP_STATE_INIT_RECEIVED:
7096 break;
7097 default:
7098 return -EINTR;
7099 break;
7100 }
7101 return 1;
7102}
09cec754 7103
5d9bc648
PB		 7104static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7105{
0ad3bed6
PB		 7106 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7107 kvm_x86_ops->check_nested_events(vcpu, false);
7108
5d9bc648
PB		 7109 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7110 !vcpu->arch.apf.halted);
7111}
7112
362c698f 7113static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7114{
7115 int r;
f656ce01 7116 struct kvm *kvm = vcpu->kvm;
d7690175 7117
f656ce01 7118 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7119
362c698f 7120 for (;;) {
58f800d5 7121 if (kvm_vcpu_running(vcpu)) {
851ba692 7122 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7123 } else {
362c698f 7124 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7125 }
7126
09cec754
GN		 7127 if (r <= 0)
7128 break;
7129
72875d8a 7130 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7131 if (kvm_cpu_has_pending_timer(vcpu))
7132 kvm_inject_pending_timer_irqs(vcpu);
7133
782d422b
MG		 7134 if (dm_request_for_irq_injection(vcpu) &&
7135 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7136 r = 0;
7137 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7138 ++vcpu->stat.request_irq_exits;
362c698f 7139 break;
09cec754 7140 }
af585b92
GN		 7141
7142 kvm_check_async_pf_completion(vcpu);
7143
09cec754
GN		 7144 if (signal_pending(current)) {
7145 r = -EINTR;
851ba692 7146 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7147 ++vcpu->stat.signal_exits;
362c698f 7148 break;
09cec754
GN		 7149 }
7150 if (need_resched()) {
f656ce01 7151 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7152 cond_resched();
f656ce01 7153 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7154 }
b6c7a5dc
HB		 7155 }
7156
f656ce01 7157 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7158
7159 return r;
7160}
7161
716d51ab
GN		 7162static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7163{
7164 int r;
7165 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7166 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7167 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7168 if (r != EMULATE_DONE)
7169 return 0;
7170 return 1;
7171}
7172
7173static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7174{
7175 BUG_ON(!vcpu->arch.pio.count);
7176
7177 return complete_emulated_io(vcpu);
7178}
7179
f78146b0
AK		 7180/*
7181 * Implements the following, as a state machine:
7182 *
7183 * read:
7184 * for each fragment
87da7e66
XG		 7185 * for each mmio piece in the fragment
7186 * write gpa, len
7187 * exit
7188 * copy data
f78146b0
AK		 7189 * execute insn
7190 *
7191 * write:
7192 * for each fragment
87da7e66
XG		 7193 * for each mmio piece in the fragment
7194 * write gpa, len
7195 * copy data
7196 * exit
f78146b0 7197 */
716d51ab 7198static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7199{
7200 struct kvm_run *run = vcpu->run;
f78146b0 7201 struct kvm_mmio_fragment *frag;
87da7e66 7202 unsigned len;
5287f194 7203
716d51ab 7204 BUG_ON(!vcpu->mmio_needed);
5287f194 7205
716d51ab 7206 /* Complete previous fragment */
87da7e66
XG		 7207 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7208 len = min(8u, frag->len);
716d51ab 7209 if (!vcpu->mmio_is_write)
87da7e66
XG		 7210 memcpy(frag->data, run->mmio.data, len);
7211
7212 if (frag->len <= 8) {
7213 /* Switch to the next fragment. */
7214 frag++;
7215 vcpu->mmio_cur_fragment++;
7216 } else {
7217 /* Go forward to the next mmio piece. */
7218 frag->data += len;
7219 frag->gpa += len;
7220 frag->len -= len;
7221 }
7222
a08d3b3b 7223 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7224 vcpu->mmio_needed = 0;
0912c977
PB		 7225
7226 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7227 if (vcpu->mmio_is_write)
716d51ab
GN		 7228 return 1;
7229 vcpu->mmio_read_completed = 1;
7230 return complete_emulated_io(vcpu);
7231 }
87da7e66 7232
716d51ab
GN		 7233 run->exit_reason = KVM_EXIT_MMIO;
7234 run->mmio.phys_addr = frag->gpa;
7235 if (vcpu->mmio_is_write)
87da7e66
XG		 7236 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7237 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7238 run->mmio.is_write = vcpu->mmio_is_write;
7239 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7240 return 0;
5287f194
AK		 7241}
7242
716d51ab 7243
b6c7a5dc
HB		 7244int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7245{
c5bedc68 7246 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7247 int r;
7248 sigset_t sigsaved;
7249
2ce03d85 7250 fpu__initialize(fpu);
e5c30142 7251
ac9f6dc0
AK		 7252 if (vcpu->sigset_active)
7253 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7254
a4535290 7255 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7256 if (kvm_run->immediate_exit) {
7257 r = -EINTR;
7258 goto out;
7259 }
b6c7a5dc 7260 kvm_vcpu_block(vcpu);
66450a21 7261 kvm_apic_accept_events(vcpu);
72875d8a 7262 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7263 r = -EAGAIN;
a0595000
JS		 7264 if (signal_pending(current)) {
7265 r = -EINTR;
7266 vcpu->run->exit_reason = KVM_EXIT_INTR;
7267 ++vcpu->stat.signal_exits;
7268 }
ac9f6dc0 7269 goto out;
b6c7a5dc
HB		 7270 }
7271
b6c7a5dc 7272 /* re-sync apic's tpr */
35754c98 7273 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7274 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7275 r = -EINVAL;
7276 goto out;
7277 }
7278 }
b6c7a5dc 7279
716d51ab
GN		 7280 if (unlikely(vcpu->arch.complete_userspace_io)) {
7281 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7282 vcpu->arch.complete_userspace_io = NULL;
7283 r = cui(vcpu);
7284 if (r <= 0)
7285 goto out;
7286 } else
7287 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7288
460df4c1
PB		 7289 if (kvm_run->immediate_exit)
7290 r = -EINTR;
7291 else
7292 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7293
7294out:
f1d86e46 7295 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7296 if (vcpu->sigset_active)
7297 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7298
b6c7a5dc
HB		 7299 return r;
7300}
7301
7302int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7303{
7ae441ea
GN		 7304 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7305 /*
7306 * We are here if userspace calls get_regs() in the middle of
7307 * instruction emulation. Registers state needs to be copied
4a969980 7308 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7309 * that usually, but some bad designed PV devices (vmware
7310 * backdoor interface) need this to work
7311 */
dd856efa 7312 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7313 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7314 }
5fdbf976
MT		 7315 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7316 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7317 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7318 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7319 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7320 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7321 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7322 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7323#ifdef CONFIG_X86_64
5fdbf976
MT		 7324 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7325 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7326 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7327 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7328 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7329 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7330 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7331 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7332#endif
7333
5fdbf976 7334 regs->rip = kvm_rip_read(vcpu);
91586a3b 7335 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7336
b6c7a5dc
HB		 7337 return 0;
7338}
7339
7340int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7341{
7ae441ea
GN		 7342 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7343 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7344
5fdbf976
MT		 7345 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7346 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7347 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7348 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7349 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7350 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7351 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7352 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7353#ifdef CONFIG_X86_64
5fdbf976
MT		 7354 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7355 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7356 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7357 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7358 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7359 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7360 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7361 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7362#endif
7363
5fdbf976 7364 kvm_rip_write(vcpu, regs->rip);
91586a3b 7365 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7366
b4f14abd
JK		 7367 vcpu->arch.exception.pending = false;
7368
3842d135
AK		 7369 kvm_make_request(KVM_REQ_EVENT, vcpu);
7370
b6c7a5dc
HB		 7371 return 0;
7372}
7373
b6c7a5dc
HB		 7374void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7375{
7376 struct kvm_segment cs;
7377
3e6e0aab 7378 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7379 *db = cs.db;
7380 *l = cs.l;
7381}
7382EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7383
7384int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7385 struct kvm_sregs *sregs)
7386{
89a27f4d 7387 struct desc_ptr dt;
b6c7a5dc 7388
3e6e0aab
GT		 7389 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7390 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7391 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7392 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7393 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7394 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7395
3e6e0aab
GT		 7396 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7397 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7398
7399 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7400 sregs->idt.limit = dt.size;
7401 sregs->idt.base = dt.address;
b6c7a5dc 7402 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7403 sregs->gdt.limit = dt.size;
7404 sregs->gdt.base = dt.address;
b6c7a5dc 7405
4d4ec087 7406 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7407 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7408 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7409 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7410 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7411 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7412 sregs->apic_base = kvm_get_apic_base(vcpu);
7413
923c61bb 7414 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7415
36752c9b 7416 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7417 set_bit(vcpu->arch.interrupt.nr,
7418 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7419
b6c7a5dc
HB		 7420 return 0;
7421}
7422
62d9f0db
MT		 7423int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7424 struct kvm_mp_state *mp_state)
7425{
66450a21 7426 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7427 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7428 vcpu->arch.pv.pv_unhalted)
7429 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7430 else
7431 mp_state->mp_state = vcpu->arch.mp_state;
7432
62d9f0db
MT		 7433 return 0;
7434}
7435
7436int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7437 struct kvm_mp_state *mp_state)
7438{
bce87cce 7439 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7440 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7441 return -EINVAL;
7442
28bf2888
DH		 7443 /* INITs are latched while in SMM */
7444 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7445 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7446 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7447 return -EINVAL;
7448
66450a21
JK		 7449 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7450 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7451 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7452 } else
7453 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7454 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7455 return 0;
7456}
7457
7f3d35fd
KW		 7458int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7459 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7460{
9d74191a 7461 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7462 int ret;
e01c2426 7463
8ec4722d 7464 init_emulate_ctxt(vcpu);
c697518a 7465
7f3d35fd 7466 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7467 has_error_code, error_code);
c697518a 7468
c697518a 7469 if (ret)
19d04437 7470 return EMULATE_FAIL;
37817f29 7471
9d74191a
TY		 7472 kvm_rip_write(vcpu, ctxt->eip);
7473 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7474 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7475 return EMULATE_DONE;
37817f29
IE		 7476}
7477EXPORT_SYMBOL_GPL(kvm_task_switch);
7478
b6c7a5dc
HB		 7479int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7480 struct kvm_sregs *sregs)
7481{
58cb628d 7482 struct msr_data apic_base_msr;
b6c7a5dc 7483 int mmu_reset_needed = 0;
63f42e02 7484 int pending_vec, max_bits, idx;
89a27f4d 7485 struct desc_ptr dt;
b6c7a5dc 7486
d6321d49
RK		 7487 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7488 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7489 return -EINVAL;
7490
d3802286
JM		 7491 apic_base_msr.data = sregs->apic_base;
7492 apic_base_msr.host_initiated = true;
7493 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7494 return -EINVAL;
7495
89a27f4d
GN		 7496 dt.size = sregs->idt.limit;
7497 dt.address = sregs->idt.base;
b6c7a5dc 7498 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7499 dt.size = sregs->gdt.limit;
7500 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7501 kvm_x86_ops->set_gdt(vcpu, &dt);
7502
ad312c7c 7503 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7504 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7505 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7506 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7507
2d3ad1f4 7508 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7509
f6801dff 7510 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7511 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7512
4d4ec087 7513 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7514 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7515 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7516
fc78f519 7517 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7518 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7519 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7520 kvm_update_cpuid(vcpu);
63f42e02
XG		 7521
7522 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7523 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7524 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7525 mmu_reset_needed = 1;
7526 }
63f42e02 7527 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7528
7529 if (mmu_reset_needed)
7530 kvm_mmu_reset_context(vcpu);
7531
a50abc3b 7532 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7533 pending_vec = find_first_bit(
7534 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7535 if (pending_vec < max_bits) {
66fd3f7f 7536 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7537 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7538 }
7539
3e6e0aab
GT		 7540 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7541 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7542 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7543 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7544 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7545 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7546
3e6e0aab
GT		 7547 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7548 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7549
5f0269f5
ME		 7550 update_cr8_intercept(vcpu);
7551
9c3e4aab 7552 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7553 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7554 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7555 !is_protmode(vcpu))
9c3e4aab
MT		 7556 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7557
3842d135
AK		 7558 kvm_make_request(KVM_REQ_EVENT, vcpu);
7559
b6c7a5dc
HB		 7560 return 0;
7561}
7562
d0bfb940
JK		 7563int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7564 struct kvm_guest_debug *dbg)
b6c7a5dc 7565{
355be0b9 7566 unsigned long rflags;
ae675ef0 7567 int i, r;
b6c7a5dc 7568
4f926bf2
JK		 7569 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7570 r = -EBUSY;
7571 if (vcpu->arch.exception.pending)
2122ff5e 7572 goto out;
4f926bf2
JK		 7573 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7574 kvm_queue_exception(vcpu, DB_VECTOR);
7575 else
7576 kvm_queue_exception(vcpu, BP_VECTOR);
7577 }
7578
91586a3b
JK		 7579 /*
7580 * Read rflags as long as potentially injected trace flags are still
7581 * filtered out.
7582 */
7583 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7584
7585 vcpu->guest_debug = dbg->control;
7586 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7587 vcpu->guest_debug = 0;
7588
7589 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7590 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7591 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7592 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7593 } else {
7594 for (i = 0; i < KVM_NR_DB_REGS; i++)
7595 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7596 }
c8639010 7597 kvm_update_dr7(vcpu);
ae675ef0 7598
f92653ee
JK		 7599 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7600 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7601 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7602
91586a3b
JK		 7603 /*
7604 * Trigger an rflags update that will inject or remove the trace
7605 * flags.
7606 */
7607 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7608
a96036b8 7609 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7610
4f926bf2 7611 r = 0;
d0bfb940 7612
2122ff5e 7613out:
b6c7a5dc
HB		 7614
7615 return r;
7616}
7617
8b006791
ZX		 7618/*
7619 * Translate a guest virtual address to a guest physical address.
7620 */
7621int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7622 struct kvm_translation *tr)
7623{
7624 unsigned long vaddr = tr->linear_address;
7625 gpa_t gpa;
f656ce01 7626 int idx;
8b006791 7627
f656ce01 7628 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7629 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7630 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7631 tr->physical_address = gpa;
7632 tr->valid = gpa != UNMAPPED_GVA;
7633 tr->writeable = 1;
7634 tr->usermode = 0;
8b006791
ZX		 7635
7636 return 0;
7637}
7638
d0752060
HB		 7639int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7640{
c47ada30 7641 struct fxregs_state *fxsave =
7366ed77 7642 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7643
d0752060
HB		 7644 memcpy(fpu->fpr, fxsave->st_space, 128);
7645 fpu->fcw = fxsave->cwd;
7646 fpu->fsw = fxsave->swd;
7647 fpu->ftwx = fxsave->twd;
7648 fpu->last_opcode = fxsave->fop;
7649 fpu->last_ip = fxsave->rip;
7650 fpu->last_dp = fxsave->rdp;
7651 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7652
d0752060
HB		 7653 return 0;
7654}
7655
7656int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7657{
c47ada30 7658 struct fxregs_state *fxsave =
7366ed77 7659 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7660
d0752060
HB		 7661 memcpy(fxsave->st_space, fpu->fpr, 128);
7662 fxsave->cwd = fpu->fcw;
7663 fxsave->swd = fpu->fsw;
7664 fxsave->twd = fpu->ftwx;
7665 fxsave->fop = fpu->last_opcode;
7666 fxsave->rip = fpu->last_ip;
7667 fxsave->rdp = fpu->last_dp;
7668 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7669
d0752060
HB		 7670 return 0;
7671}
7672
0ee6a517 7673static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7674{
bf935b0b 7675 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7676 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7677 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7678 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7679
2acf923e
DC		 7680 /*
7681 * Ensure guest xcr0 is valid for loading
7682 */
d91cab78 7683 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7684
ad312c7c 7685 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7686}
d0752060
HB		 7687
7688void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7689{
2608d7a1 7690 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7691 return;
7692
2acf923e
DC		 7693 /*
7694 * Restore all possible states in the guest,
7695 * and assume host would use all available bits.
7696 * Guest xcr0 would be loaded later.
7697 */
d0752060 7698 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7699 __kernel_fpu_begin();
38cfd5e3
PB		 7700 /* PKRU is separately restored in kvm_x86_ops->run. */
7701 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7702 ~XFEATURE_MASK_PKRU);
0c04851c 7703 trace_kvm_fpu(1);
d0752060 7704}
d0752060
HB		 7705
7706void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7707{
3d42de25 7708 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7709 return;
7710
7711 vcpu->guest_fpu_loaded = 0;
4f836347 7712 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7713 __kernel_fpu_end();
f096ed85 7714 ++vcpu->stat.fpu_reload;
0c04851c 7715 trace_kvm_fpu(0);
d0752060 7716}
e9b11c17
ZX		 7717
7718void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7719{
bd768e14
IY		 7720 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7721
12f9a48f 7722 kvmclock_reset(vcpu);
7f1ea208 7723
e9b11c17 7724 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7725 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7726}
7727
7728struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7729 unsigned int id)
7730{
c447e76b
LL		 7731 struct kvm_vcpu *vcpu;
7732
6755bae8
ZA		 7733 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7734 printk_once(KERN_WARNING
7735 "kvm: SMP vm created on host with unstable TSC; "
7736 "guest TSC will not be reliable\n");
c447e76b
LL		 7737
7738 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7739
c447e76b 7740 return vcpu;
26e5215f 7741}
e9b11c17 7742
26e5215f
AK		 7743int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7744{
7745 int r;
e9b11c17 7746
19efffa2 7747 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7748 r = vcpu_load(vcpu);
7749 if (r)
7750 return r;
d28bc9dd 7751 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7752 kvm_mmu_setup(vcpu);
e9b11c17 7753 vcpu_put(vcpu);
26e5215f 7754 return r;
e9b11c17
ZX		 7755}
7756
31928aa5 7757void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7758{
8fe8ab46 7759 struct msr_data msr;
332967a3 7760 struct kvm *kvm = vcpu->kvm;
42897d86 7761
d3457c87
RK		 7762 kvm_hv_vcpu_postcreate(vcpu);
7763
31928aa5
DD		 7764 if (vcpu_load(vcpu))
7765 return;
8fe8ab46
WA		 7766 msr.data = 0x0;
7767 msr.index = MSR_IA32_TSC;
7768 msr.host_initiated = true;
7769 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7770 vcpu_put(vcpu);
7771
630994b3
MT		 7772 if (!kvmclock_periodic_sync)
7773 return;
7774
332967a3
AJ		 7775 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7776 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7777}
7778
d40ccc62 7779void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7780{
9fc77441 7781 int r;
344d9588
GN		 7782 vcpu->arch.apf.msr_val = 0;
7783
9fc77441
MT		 7784 r = vcpu_load(vcpu);
7785 BUG_ON(r);
e9b11c17
ZX		 7786 kvm_mmu_unload(vcpu);
7787 vcpu_put(vcpu);
7788
7789 kvm_x86_ops->vcpu_free(vcpu);
7790}
7791
d28bc9dd 7792void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7793{
e69fab5d
PB		 7794 vcpu->arch.hflags = 0;
7795
c43203ca 7796 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7797 atomic_set(&vcpu->arch.nmi_queued, 0);
7798 vcpu->arch.nmi_pending = 0;
448fa4a9 7799 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7800 kvm_clear_interrupt_queue(vcpu);
7801 kvm_clear_exception_queue(vcpu);
664f8e26 7802 vcpu->arch.exception.pending = false;
448fa4a9 7803
42dbaa5a 7804 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7805 kvm_update_dr0123(vcpu);
6f43ed01 7806 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7807 kvm_update_dr6(vcpu);
42dbaa5a 7808 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7809 kvm_update_dr7(vcpu);
42dbaa5a 7810
1119022c
NA		 7811 vcpu->arch.cr2 = 0;
7812
3842d135 7813 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7814 vcpu->arch.apf.msr_val = 0;
c9aaa895 7815 vcpu->arch.st.msr_val = 0;
3842d135 7816
12f9a48f
GC		 7817 kvmclock_reset(vcpu);
7818
af585b92
GN		 7819 kvm_clear_async_pf_completion_queue(vcpu);
7820 kvm_async_pf_hash_reset(vcpu);
7821 vcpu->arch.apf.halted = false;
3842d135 7822
a554d207
WL		 7823 if (kvm_mpx_supported()) {
7824 void *mpx_state_buffer;
7825
7826 /*
7827 * To avoid have the INIT path from kvm_apic_has_events() that be
7828 * called with loaded FPU and does not let userspace fix the state.
7829 */
7830 kvm_put_guest_fpu(vcpu);
7831 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7832 XFEATURE_MASK_BNDREGS);
7833 if (mpx_state_buffer)
7834 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7835 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7836 XFEATURE_MASK_BNDCSR);
7837 if (mpx_state_buffer)
7838 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
7839 }
7840
64d60670 7841 if (!init_event) {
d28bc9dd 7842 kvm_pmu_reset(vcpu);
64d60670 7843 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7844
7845 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7846 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7847
7848 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7849 }
f5132b01 7850
66f7b72e
JS		 7851 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7852 vcpu->arch.regs_avail = ~0;
7853 vcpu->arch.regs_dirty = ~0;
7854
a554d207
WL		 7855 vcpu->arch.ia32_xss = 0;
7856
d28bc9dd 7857 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7858}
7859
2b4a273b 7860void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7861{
7862 struct kvm_segment cs;
7863
7864 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7865 cs.selector = vector << 8;
7866 cs.base = vector << 12;
7867 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7868 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7869}
7870
13a34e06 7871int kvm_arch_hardware_enable(void)
e9b11c17 7872{
ca84d1a2
ZA		 7873 struct kvm *kvm;
7874 struct kvm_vcpu *vcpu;
7875 int i;
0dd6a6ed
ZA		 7876 int ret;
7877 u64 local_tsc;
7878 u64 max_tsc = 0;
7879 bool stable, backwards_tsc = false;
18863bdd
AK		 7880
7881 kvm_shared_msr_cpu_online();
13a34e06 7882 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7883 if (ret != 0)
7884 return ret;
7885
4ea1636b 7886 local_tsc = rdtsc();
0dd6a6ed
ZA		 7887 stable = !check_tsc_unstable();
7888 list_for_each_entry(kvm, &vm_list, vm_list) {
7889 kvm_for_each_vcpu(i, vcpu, kvm) {
7890 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7891 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7892 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7893 backwards_tsc = true;
7894 if (vcpu->arch.last_host_tsc > max_tsc)
7895 max_tsc = vcpu->arch.last_host_tsc;
7896 }
7897 }
7898 }
7899
7900 /*
7901 * Sometimes, even reliable TSCs go backwards. This happens on
7902 * platforms that reset TSC during suspend or hibernate actions, but
7903 * maintain synchronization. We must compensate. Fortunately, we can
7904 * detect that condition here, which happens early in CPU bringup,
7905 * before any KVM threads can be running. Unfortunately, we can't
7906 * bring the TSCs fully up to date with real time, as we aren't yet far
7907 * enough into CPU bringup that we know how much real time has actually
108b249c 7908 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7909 * variables that haven't been updated yet.
7910 *
7911 * So we simply find the maximum observed TSC above, then record the
7912 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7913 * the adjustment will be applied. Note that we accumulate
7914 * adjustments, in case multiple suspend cycles happen before some VCPU
7915 * gets a chance to run again. In the event that no KVM threads get a
7916 * chance to run, we will miss the entire elapsed period, as we'll have
7917 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7918 * loose cycle time. This isn't too big a deal, since the loss will be
7919 * uniform across all VCPUs (not to mention the scenario is extremely
7920 * unlikely). It is possible that a second hibernate recovery happens
7921 * much faster than a first, causing the observed TSC here to be
7922 * smaller; this would require additional padding adjustment, which is
7923 * why we set last_host_tsc to the local tsc observed here.
7924 *
7925 * N.B. - this code below runs only on platforms with reliable TSC,
7926 * as that is the only way backwards_tsc is set above. Also note
7927 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7928 * have the same delta_cyc adjustment applied if backwards_tsc
7929 * is detected. Note further, this adjustment is only done once,
7930 * as we reset last_host_tsc on all VCPUs to stop this from being
7931 * called multiple times (one for each physical CPU bringup).
7932 *
4a969980 7933 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7934 * will be compensated by the logic in vcpu_load, which sets the TSC to
7935 * catchup mode. This will catchup all VCPUs to real time, but cannot
7936 * guarantee that they stay in perfect synchronization.
7937 */
7938 if (backwards_tsc) {
7939 u64 delta_cyc = max_tsc - local_tsc;
7940 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7941 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7942 kvm_for_each_vcpu(i, vcpu, kvm) {
7943 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7944 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7945 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7946 }
7947
7948 /*
7949 * We have to disable TSC offset matching.. if you were
7950 * booting a VM while issuing an S4 host suspend....
7951 * you may have some problem. Solving this issue is
7952 * left as an exercise to the reader.
7953 */
7954 kvm->arch.last_tsc_nsec = 0;
7955 kvm->arch.last_tsc_write = 0;
7956 }
7957
7958 }
7959 return 0;
e9b11c17
ZX		 7960}
7961
13a34e06 7962void kvm_arch_hardware_disable(void)
e9b11c17 7963{
13a34e06
RK		 7964 kvm_x86_ops->hardware_disable();
7965 drop_user_return_notifiers();
e9b11c17
ZX		 7966}
7967
7968int kvm_arch_hardware_setup(void)
7969{
9e9c3fe4
NA		 7970 int r;
7971
7972 r = kvm_x86_ops->hardware_setup();
7973 if (r != 0)
7974 return r;
7975
35181e86
HZ		 7976 if (kvm_has_tsc_control) {
7977 /*
7978 * Make sure the user can only configure tsc_khz values that
7979 * fit into a signed integer.
7980 * A min value is not calculated needed because it will always
7981 * be 1 on all machines.
7982 */
7983 u64 max = min(0x7fffffffULL,
7984 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7985 kvm_max_guest_tsc_khz = max;
7986
ad721883 7987 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7988 }
ad721883 7989
9e9c3fe4
NA		 7990 kvm_init_msr_list();
7991 return 0;
e9b11c17
ZX		 7992}
7993
7994void kvm_arch_hardware_unsetup(void)
7995{
7996 kvm_x86_ops->hardware_unsetup();
7997}
7998
7999void kvm_arch_check_processor_compat(void *rtn)
8000{
8001 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8002}
8003
8004bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8005{
8006 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8007}
8008EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8009
8010bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8011{
8012 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8013}
8014
54e9818f 8015struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8016EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8017
e9b11c17
ZX		 8018int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8019{
8020 struct page *page;
e9b11c17
ZX		 8021 int r;
8022
b2a05fef 8023 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8024 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8025 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8026 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8027 else
a4535290 8028 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8029
8030 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8031 if (!page) {
8032 r = -ENOMEM;
8033 goto fail;
8034 }
ad312c7c 8035 vcpu->arch.pio_data = page_address(page);
e9b11c17 8036
cc578287 8037 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8038
e9b11c17
ZX		 8039 r = kvm_mmu_create(vcpu);
8040 if (r < 0)
8041 goto fail_free_pio_data;
8042
26de7988 8043 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8044 r = kvm_create_lapic(vcpu);
8045 if (r < 0)
8046 goto fail_mmu_destroy;
54e9818f
GN		 8047 } else
8048 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8049
890ca9ae
HY		 8050 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8051 GFP_KERNEL);
8052 if (!vcpu->arch.mce_banks) {
8053 r = -ENOMEM;
443c39bc 8054 goto fail_free_lapic;
890ca9ae
HY		 8055 }
8056 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8057
f1797359
WY		 8058 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8059 r = -ENOMEM;
f5f48ee1 8060 goto fail_free_mce_banks;
f1797359 8061 }
f5f48ee1 8062
0ee6a517 8063 fx_init(vcpu);
66f7b72e 8064
4344ee98 8065 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8066
5a4f55cd
EK		 8067 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8068
74545705
RK		 8069 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8070
af585b92 8071 kvm_async_pf_hash_reset(vcpu);
f5132b01 8072 kvm_pmu_init(vcpu);
af585b92 8073
1c1a9ce9 8074 vcpu->arch.pending_external_vector = -1;
de63ad4c 8075 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8076
5c919412
AS		 8077 kvm_hv_vcpu_init(vcpu);
8078
e9b11c17 8079 return 0;
0ee6a517 8080
f5f48ee1
SY		 8081fail_free_mce_banks:
8082 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8083fail_free_lapic:
8084 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8085fail_mmu_destroy:
8086 kvm_mmu_destroy(vcpu);
8087fail_free_pio_data:
ad312c7c 8088 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8089fail:
8090 return r;
8091}
8092
8093void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8094{
f656ce01
MT		 8095 int idx;
8096
1f4b34f8 8097 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8098 kvm_pmu_destroy(vcpu);
36cb93fd 8099 kfree(vcpu->arch.mce_banks);
e9b11c17 8100 kvm_free_lapic(vcpu);
f656ce01 8101 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8102 kvm_mmu_destroy(vcpu);
f656ce01 8103 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8104 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8105 if (!lapic_in_kernel(vcpu))
54e9818f 8106 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8107}
d19a9cd2 8108
e790d9ef
RK		 8109void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8110{
ae97a3b8 8111 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8112}
8113
e08b9637 8114int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8115{
e08b9637
CO		 8116 if (type)
8117 return -EINVAL;
8118
6ef768fa 8119 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8120 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8121 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8122 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8123 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8124
5550af4d
SY		 8125 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8126 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8127 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8128 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8129 &kvm->arch.irq_sources_bitmap);
5550af4d 8130
038f8c11 8131 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8132 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8133 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8134 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8135
108b249c 8136 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8137 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8138
7e44e449 8139 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8140 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8141
0eb05bf2 8142 kvm_page_track_init(kvm);
13d268ca 8143 kvm_mmu_init_vm(kvm);
0eb05bf2 8144
03543133
SS		 8145 if (kvm_x86_ops->vm_init)
8146 return kvm_x86_ops->vm_init(kvm);
8147
d89f5eff 8148 return 0;
d19a9cd2
ZX		 8149}
8150
8151static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8152{
9fc77441
MT		 8153 int r;
8154 r = vcpu_load(vcpu);
8155 BUG_ON(r);
d19a9cd2
ZX		 8156 kvm_mmu_unload(vcpu);
8157 vcpu_put(vcpu);
8158}
8159
8160static void kvm_free_vcpus(struct kvm *kvm)
8161{
8162 unsigned int i;
988a2cae 8163 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8164
8165 /*
8166 * Unpin any mmu pages first.
8167 */
af585b92
GN		 8168 kvm_for_each_vcpu(i, vcpu, kvm) {
8169 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8170 kvm_unload_vcpu_mmu(vcpu);
af585b92 8171 }
988a2cae
GN		 8172 kvm_for_each_vcpu(i, vcpu, kvm)
8173 kvm_arch_vcpu_free(vcpu);
8174
8175 mutex_lock(&kvm->lock);
8176 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8177 kvm->vcpus[i] = NULL;
d19a9cd2 8178
988a2cae
GN		 8179 atomic_set(&kvm->online_vcpus, 0);
8180 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8181}
8182
ad8ba2cd
SY		 8183void kvm_arch_sync_events(struct kvm *kvm)
8184{
332967a3 8185 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8186 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8187 kvm_free_pit(kvm);
ad8ba2cd
SY		 8188}
8189
1d8007bd 8190int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8191{
8192 int i, r;
25188b99 8193 unsigned long hva;
f0d648bd
PB		 8194 struct kvm_memslots *slots = kvm_memslots(kvm);
8195 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8196
8197 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8198 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8199 return -EINVAL;
9da0e4d5 8200
f0d648bd
PB		 8201 slot = id_to_memslot(slots, id);
8202 if (size) {
b21629da 8203 if (slot->npages)
f0d648bd
PB		 8204 return -EEXIST;
8205
8206 /*
8207 * MAP_SHARED to prevent internal slot pages from being moved
8208 * by fork()/COW.
8209 */
8210 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8211 MAP_SHARED | MAP_ANONYMOUS, 0);
8212 if (IS_ERR((void *)hva))
8213 return PTR_ERR((void *)hva);
8214 } else {
8215 if (!slot->npages)
8216 return 0;
8217
8218 hva = 0;
8219 }
8220
8221 old = *slot;
9da0e4d5 8222 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8223 struct kvm_userspace_memory_region m;
9da0e4d5 8224
1d8007bd
PB		 8225 m.slot = id | (i << 16);
8226 m.flags = 0;
8227 m.guest_phys_addr = gpa;
f0d648bd 8228 m.userspace_addr = hva;
1d8007bd 8229 m.memory_size = size;
9da0e4d5
PB		 8230 r = __kvm_set_memory_region(kvm, &m);
8231 if (r < 0)
8232 return r;
8233 }
8234
f0d648bd
PB		 8235 if (!size) {
8236 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8237 WARN_ON(r < 0);
8238 }
8239
9da0e4d5
PB		 8240 return 0;
8241}
8242EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8243
1d8007bd 8244int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8245{
8246 int r;
8247
8248 mutex_lock(&kvm->slots_lock);
1d8007bd 8249 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8250 mutex_unlock(&kvm->slots_lock);
8251
8252 return r;
8253}
8254EXPORT_SYMBOL_GPL(x86_set_memory_region);
8255
d19a9cd2
ZX		 8256void kvm_arch_destroy_vm(struct kvm *kvm)
8257{
27469d29
AH		 8258 if (current->mm == kvm->mm) {
8259 /*
8260 * Free memory regions allocated on behalf of userspace,
8261 * unless the the memory map has changed due to process exit
8262 * or fd copying.
8263 */
1d8007bd
PB		 8264 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8265 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8266 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8267 }
03543133
SS		 8268 if (kvm_x86_ops->vm_destroy)
8269 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8270 kvm_pic_destroy(kvm);
8271 kvm_ioapic_destroy(kvm);
d19a9cd2 8272 kvm_free_vcpus(kvm);
af1bae54 8273 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8274 kvm_mmu_uninit_vm(kvm);
2beb6dad 8275 kvm_page_track_cleanup(kvm);
d19a9cd2 8276}
0de10343 8277
5587027c 8278void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8279 struct kvm_memory_slot *dont)
8280{
8281 int i;
8282
d89cc617
TY		 8283 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8284 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8285 kvfree(free->arch.rmap[i]);
d89cc617 8286 free->arch.rmap[i] = NULL;
77d11309 8287 }
d89cc617
TY		 8288 if (i == 0)
8289 continue;
8290
8291 if (!dont || free->arch.lpage_info[i - 1] !=
8292 dont->arch.lpage_info[i - 1]) {
548ef284 8293 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8294 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8295 }
8296 }
21ebbeda
XG		 8297
8298 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8299}
8300
5587027c
AK		 8301int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8302 unsigned long npages)
db3fe4eb
TY		 8303{
8304 int i;
8305
d89cc617 8306 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8307 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8308 unsigned long ugfn;
8309 int lpages;
d89cc617 8310 int level = i + 1;
db3fe4eb
TY		 8311
8312 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8313 slot->base_gfn, level) + 1;
8314
d89cc617 8315 slot->arch.rmap[i] =
a7c3e901 8316 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8317 if (!slot->arch.rmap[i])
77d11309 8318 goto out_free;
d89cc617
TY		 8319 if (i == 0)
8320 continue;
77d11309 8321
a7c3e901 8322 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8323 if (!linfo)
db3fe4eb
TY		 8324 goto out_free;
8325
92f94f1e
XG		 8326 slot->arch.lpage_info[i - 1] = linfo;
8327
db3fe4eb 8328 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8329 linfo[0].disallow_lpage = 1;
db3fe4eb 8330 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8331 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8332 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8333 /*
8334 * If the gfn and userspace address are not aligned wrt each
8335 * other, or if explicitly asked to, disable large page
8336 * support for this slot
8337 */
8338 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8339 !kvm_largepages_enabled()) {
8340 unsigned long j;
8341
8342 for (j = 0; j < lpages; ++j)
92f94f1e 8343 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8344 }
8345 }
8346
21ebbeda
XG		 8347 if (kvm_page_track_create_memslot(slot, npages))
8348 goto out_free;
8349
db3fe4eb
TY		 8350 return 0;
8351
8352out_free:
d89cc617 8353 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8354 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8355 slot->arch.rmap[i] = NULL;
8356 if (i == 0)
8357 continue;
8358
548ef284 8359 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8360 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8361 }
8362 return -ENOMEM;
8363}
8364
15f46015 8365void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8366{
e6dff7d1
TY		 8367 /*
8368 * memslots->generation has been incremented.
8369 * mmio generation may have reached its maximum value.
8370 */
54bf36aa 8371 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8372}
8373
f7784b8e
MT		 8374int kvm_arch_prepare_memory_region(struct kvm *kvm,
8375 struct kvm_memory_slot *memslot,
09170a49 8376 const struct kvm_userspace_memory_region *mem,
7b6195a9 8377 enum kvm_mr_change change)
0de10343 8378{
f7784b8e
MT		 8379 return 0;
8380}
8381
88178fd4
KH		 8382static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8383 struct kvm_memory_slot *new)
8384{
8385 /* Still write protect RO slot */
8386 if (new->flags & KVM_MEM_READONLY) {
8387 kvm_mmu_slot_remove_write_access(kvm, new);
8388 return;
8389 }
8390
8391 /*
8392 * Call kvm_x86_ops dirty logging hooks when they are valid.
8393 *
8394 * kvm_x86_ops->slot_disable_log_dirty is called when:
8395 *
8396 * - KVM_MR_CREATE with dirty logging is disabled
8397 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8398 *
8399 * The reason is, in case of PML, we need to set D-bit for any slots
8400 * with dirty logging disabled in order to eliminate unnecessary GPA
8401 * logging in PML buffer (and potential PML buffer full VMEXT). This
8402 * guarantees leaving PML enabled during guest's lifetime won't have
8403 * any additonal overhead from PML when guest is running with dirty
8404 * logging disabled for memory slots.
8405 *
8406 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8407 * to dirty logging mode.
8408 *
8409 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8410 *
8411 * In case of write protect:
8412 *
8413 * Write protect all pages for dirty logging.
8414 *
8415 * All the sptes including the large sptes which point to this
8416 * slot are set to readonly. We can not create any new large
8417 * spte on this slot until the end of the logging.
8418 *
8419 * See the comments in fast_page_fault().
8420 */
8421 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8422 if (kvm_x86_ops->slot_enable_log_dirty)
8423 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8424 else
8425 kvm_mmu_slot_remove_write_access(kvm, new);
8426 } else {
8427 if (kvm_x86_ops->slot_disable_log_dirty)
8428 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8429 }
8430}
8431
f7784b8e 8432void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8433 const struct kvm_userspace_memory_region *mem,
8482644a 8434 const struct kvm_memory_slot *old,
f36f3f28 8435 const struct kvm_memory_slot *new,
8482644a 8436 enum kvm_mr_change change)
f7784b8e 8437{
8482644a 8438 int nr_mmu_pages = 0;
f7784b8e 8439
48c0e4e9
XG		 8440 if (!kvm->arch.n_requested_mmu_pages)
8441 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8442
48c0e4e9 8443 if (nr_mmu_pages)
0de10343 8444 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8445
3ea3b7fa
WL		 8446 /*
8447 * Dirty logging tracks sptes in 4k granularity, meaning that large
8448 * sptes have to be split. If live migration is successful, the guest
8449 * in the source machine will be destroyed and large sptes will be
8450 * created in the destination. However, if the guest continues to run
8451 * in the source machine (for example if live migration fails), small
8452 * sptes will remain around and cause bad performance.
8453 *
8454 * Scan sptes if dirty logging has been stopped, dropping those
8455 * which can be collapsed into a single large-page spte. Later
8456 * page faults will create the large-page sptes.
8457 */
8458 if ((change != KVM_MR_DELETE) &&
8459 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8460 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8461 kvm_mmu_zap_collapsible_sptes(kvm, new);
8462
c972f3b1 8463 /*
88178fd4 8464 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8465 *
88178fd4
KH		 8466 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8467 * been zapped so no dirty logging staff is needed for old slot. For
8468 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8469 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8470 *
8471 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8472 */
88178fd4 8473 if (change != KVM_MR_DELETE)
f36f3f28 8474 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8475}
1d737c8a 8476
2df72e9b 8477void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8478{
6ca18b69 8479 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8480}
8481
2df72e9b
MT		 8482void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8483 struct kvm_memory_slot *slot)
8484{
ae7cd873 8485 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8486}
8487
5d9bc648
PB		 8488static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8489{
8490 if (!list_empty_careful(&vcpu->async_pf.done))
8491 return true;
8492
8493 if (kvm_apic_has_events(vcpu))
8494 return true;
8495
8496 if (vcpu->arch.pv.pv_unhalted)
8497 return true;
8498
a5f01f8e
WL		 8499 if (vcpu->arch.exception.pending)
8500 return true;
8501
47a66eed
Z		 8502 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8503 (vcpu->arch.nmi_pending &&
8504 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8505 return true;
8506
47a66eed
Z		 8507 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8508 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8509 return true;
8510
5d9bc648
PB		 8511 if (kvm_arch_interrupt_allowed(vcpu) &&
8512 kvm_cpu_has_interrupt(vcpu))
8513 return true;
8514
1f4b34f8
AS		 8515 if (kvm_hv_has_stimer_pending(vcpu))
8516 return true;
8517
5d9bc648
PB		 8518 return false;
8519}
8520
1d737c8a
ZX		 8521int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8522{
5d9bc648 8523 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8524}
5736199a 8525
199b5763
LM		 8526bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8527{
de63ad4c 8528 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8529}
8530
b6d33834 8531int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8532{
b6d33834 8533 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8534}
78646121
GN		 8535
8536int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8537{
8538 return kvm_x86_ops->interrupt_allowed(vcpu);
8539}
229456fc 8540
82b32774 8541unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8542{
82b32774
NA		 8543 if (is_64_bit_mode(vcpu))
8544 return kvm_rip_read(vcpu);
8545 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8546 kvm_rip_read(vcpu));
8547}
8548EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8549
82b32774
NA		 8550bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8551{
8552 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8553}
8554EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8555
94fe45da
JK		 8556unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8557{
8558 unsigned long rflags;
8559
8560 rflags = kvm_x86_ops->get_rflags(vcpu);
8561 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8562 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8563 return rflags;
8564}
8565EXPORT_SYMBOL_GPL(kvm_get_rflags);
8566
6addfc42 8567static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8568{
8569 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8570 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8571 rflags |= X86_EFLAGS_TF;
94fe45da 8572 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8573}
8574
8575void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8576{
8577 __kvm_set_rflags(vcpu, rflags);
3842d135 8578 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8579}
8580EXPORT_SYMBOL_GPL(kvm_set_rflags);
8581
56028d08
GN		 8582void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8583{
8584 int r;
8585
fb67e14f 8586 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8587 work->wakeup_all)
56028d08
GN		 8588 return;
8589
8590 r = kvm_mmu_reload(vcpu);
8591 if (unlikely(r))
8592 return;
8593
fb67e14f
XG		 8594 if (!vcpu->arch.mmu.direct_map &&
8595 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8596 return;
8597
56028d08
GN		 8598 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8599}
8600
af585b92
GN		 8601static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8602{
8603 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8604}
8605
8606static inline u32 kvm_async_pf_next_probe(u32 key)
8607{
8608 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8609}
8610
8611static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8612{
8613 u32 key = kvm_async_pf_hash_fn(gfn);
8614
8615 while (vcpu->arch.apf.gfns[key] != ~0)
8616 key = kvm_async_pf_next_probe(key);
8617
8618 vcpu->arch.apf.gfns[key] = gfn;
8619}
8620
8621static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8622{
8623 int i;
8624 u32 key = kvm_async_pf_hash_fn(gfn);
8625
8626 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8627 (vcpu->arch.apf.gfns[key] != gfn &&
8628 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8629 key = kvm_async_pf_next_probe(key);
8630
8631 return key;
8632}
8633
8634bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8635{
8636 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8637}
8638
8639static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8640{
8641 u32 i, j, k;
8642
8643 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8644 while (true) {
8645 vcpu->arch.apf.gfns[i] = ~0;
8646 do {
8647 j = kvm_async_pf_next_probe(j);
8648 if (vcpu->arch.apf.gfns[j] == ~0)
8649 return;
8650 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8651 /*
8652 * k lies cyclically in ]i,j]
8653 * | i.k.j |
8654 * |....j i.k.| or |.k..j i...|
8655 */
8656 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8657 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8658 i = j;
8659 }
8660}
8661
7c90705b
GN		 8662static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8663{
4e335d9e
PB		 8664
8665 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8666 sizeof(val));
7c90705b
GN		 8667}
8668
9a6e7c39
WL		 8669static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8670{
8671
8672 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8673 sizeof(u32));
8674}
8675
af585b92
GN		 8676void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8677 struct kvm_async_pf *work)
8678{
6389ee94
AK		 8679 struct x86_exception fault;
8680
7c90705b 8681 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8682 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8683
8684 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8685 (vcpu->arch.apf.send_user_only &&
8686 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8687 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8688 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8689 fault.vector = PF_VECTOR;
8690 fault.error_code_valid = true;
8691 fault.error_code = 0;
8692 fault.nested_page_fault = false;
8693 fault.address = work->arch.token;
adfe20fb 8694 fault.async_page_fault = true;
6389ee94 8695 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8696 }
af585b92
GN		 8697}
8698
8699void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8700 struct kvm_async_pf *work)
8701{
6389ee94 8702 struct x86_exception fault;
9a6e7c39 8703 u32 val;
6389ee94 8704
f2e10669 8705 if (work->wakeup_all)
7c90705b
GN		 8706 work->arch.token = ~0; /* broadcast wakeup */
8707 else
8708 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8709 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8710
9a6e7c39
WL		 8711 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8712 !apf_get_user(vcpu, &val)) {
8713 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8714 vcpu->arch.exception.pending &&
8715 vcpu->arch.exception.nr == PF_VECTOR &&
8716 !apf_put_user(vcpu, 0)) {
8717 vcpu->arch.exception.injected = false;
8718 vcpu->arch.exception.pending = false;
8719 vcpu->arch.exception.nr = 0;
8720 vcpu->arch.exception.has_error_code = false;
8721 vcpu->arch.exception.error_code = 0;
8722 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8723 fault.vector = PF_VECTOR;
8724 fault.error_code_valid = true;
8725 fault.error_code = 0;
8726 fault.nested_page_fault = false;
8727 fault.address = work->arch.token;
8728 fault.async_page_fault = true;
8729 kvm_inject_page_fault(vcpu, &fault);
8730 }
7c90705b 8731 }
e6d53e3b 8732 vcpu->arch.apf.halted = false;
a4fa1635 8733 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8734}
8735
8736bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8737{
8738 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8739 return true;
8740 else
9bc1f09f 8741 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8742}
8743
5544eb9b
PB		 8744void kvm_arch_start_assignment(struct kvm *kvm)
8745{
8746 atomic_inc(&kvm->arch.assigned_device_count);
8747}
8748EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8749
8750void kvm_arch_end_assignment(struct kvm *kvm)
8751{
8752 atomic_dec(&kvm->arch.assigned_device_count);
8753}
8754EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8755
8756bool kvm_arch_has_assigned_device(struct kvm *kvm)
8757{
8758 return atomic_read(&kvm->arch.assigned_device_count);
8759}
8760EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8761
e0f0bbc5
AW		 8762void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8763{
8764 atomic_inc(&kvm->arch.noncoherent_dma_count);
8765}
8766EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8767
8768void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8769{
8770 atomic_dec(&kvm->arch.noncoherent_dma_count);
8771}
8772EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8773
8774bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8775{
8776 return atomic_read(&kvm->arch.noncoherent_dma_count);
8777}
8778EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8779
14717e20
AW		 8780bool kvm_arch_has_irq_bypass(void)
8781{
8782 return kvm_x86_ops->update_pi_irte != NULL;
8783}
8784
87276880
FW		 8785int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8786 struct irq_bypass_producer *prod)
8787{
8788 struct kvm_kernel_irqfd *irqfd =
8789 container_of(cons, struct kvm_kernel_irqfd, consumer);
8790
14717e20 8791 irqfd->producer = prod;
87276880 8792
14717e20
AW		 8793 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8794 prod->irq, irqfd->gsi, 1);
87276880
FW		 8795}
8796
8797void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8798 struct irq_bypass_producer *prod)
8799{
8800 int ret;
8801 struct kvm_kernel_irqfd *irqfd =
8802 container_of(cons, struct kvm_kernel_irqfd, consumer);
8803
87276880
FW		 8804 WARN_ON(irqfd->producer != prod);
8805 irqfd->producer = NULL;
8806
8807 /*
8808 * When producer of consumer is unregistered, we change back to
8809 * remapped mode, so we can re-use the current implementation
bb3541f1 8810 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8811 * int this case doesn't want to receive the interrupts.
8812 */
8813 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8814 if (ret)
8815 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8816 " fails: %d\n", irqfd->consumer.token, ret);
8817}
8818
8819int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8820 uint32_t guest_irq, bool set)
8821{
8822 if (!kvm_x86_ops->update_pi_irte)
8823 return -EINVAL;
8824
8825 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8826}
8827
52004014
FW		 8828bool kvm_vector_hashing_enabled(void)
8829{
8830 return vector_hashing;
8831}
8832EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8833
229456fc 8834EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8835EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8836EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8837EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8838EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8839EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8840EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8841EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8842EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8843EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8844EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8845EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8846EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8847EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8848EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8849EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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