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KVM: x86: add support for UMIP
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM		 110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
9ed96e87
MT		 113unsigned int min_timer_period_us = 500;
114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT		 116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW		 138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK		 141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY		 151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
188 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
191 { "mmu_flooded", VM_STAT(mmu_flooded) },
192 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 194 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 196 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 197 { "max_mmu_page_hash_collisions",
198 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 199 { NULL }
200};
201
2acf923e
DC		 202u64 __read_mostly host_xcr0;
203
b6785def 204static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 205
af585b92
GN		 206static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
207{
208 int i;
209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
210 vcpu->arch.apf.gfns[i] = ~0;
211}
212
18863bdd
AK		 213static void kvm_on_user_return(struct user_return_notifier *urn)
214{
215 unsigned slot;
18863bdd
AK		 216 struct kvm_shared_msrs *locals
217 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 218 struct kvm_shared_msr_values *values;
1650b4eb
IA		 219 unsigned long flags;
220
221 /*
222 * Disabling irqs at this point since the following code could be
223 * interrupted and executed through kvm_arch_hardware_disable()
224 */
225 local_irq_save(flags);
226 if (locals->registered) {
227 locals->registered = false;
228 user_return_notifier_unregister(urn);
229 }
230 local_irq_restore(flags);
18863bdd 231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 232 values = &locals->values[slot];
233 if (values->host != values->curr) {
234 wrmsrl(shared_msrs_global.msrs[slot], values->host);
235 values->curr = values->host;
18863bdd
AK		 236 }
237 }
18863bdd
AK		 238}
239
2bf78fa7 240static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 241{
18863bdd 242 u64 value;
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 245
2bf78fa7
SY		 246 /* only read, and nobody should modify it at this time,
247 * so don't need lock */
248 if (slot >= shared_msrs_global.nr) {
249 printk(KERN_ERR "kvm: invalid MSR slot!");
250 return;
251 }
252 rdmsrl_safe(msr, &value);
253 smsr->values[slot].host = value;
254 smsr->values[slot].curr = value;
255}
256
257void kvm_define_shared_msr(unsigned slot, u32 msr)
258{
0123be42 259 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 260 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 261 if (slot >= shared_msrs_global.nr)
262 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 263}
264EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
265
266static void kvm_shared_msr_cpu_online(void)
267{
268 unsigned i;
18863bdd
AK		 269
270 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 271 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 272}
273
8b3c3104 274int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 278 int err;
18863bdd 279
2bf78fa7 280 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 281 return 0;
2bf78fa7 282 smsr->values[slot].curr = value;
8b3c3104
AH		 283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
284 if (err)
285 return 1;
286
18863bdd
AK		 287 if (!smsr->registered) {
288 smsr->urn.on_user_return = kvm_on_user_return;
289 user_return_notifier_register(&smsr->urn);
290 smsr->registered = true;
291 }
8b3c3104 292 return 0;
18863bdd
AK		 293}
294EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
295
13a34e06 296static void drop_user_return_notifiers(void)
3548bab5 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 300
301 if (smsr->registered)
302 kvm_on_user_return(&smsr->urn);
303}
304
6866b83e
CO		 305u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
306{
8a5a87d9 307 return vcpu->arch.apic_base;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_get_apic_base);
310
58cb628d
JK		 311int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
312{
313 u64 old_state = vcpu->arch.apic_base &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 new_state = msr_info->data &
316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 319
d3802286
JM		 320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
321 return 1;
58cb628d 322 if (!msr_info->host_initiated &&
d3802286 323 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
326 old_state == 0)))
327 return 1;
328
329 kvm_lapic_set_base(vcpu, msr_info->data);
330 return 0;
6866b83e
CO		 331}
332EXPORT_SYMBOL_GPL(kvm_set_apic_base);
333
2605fc21 334asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 335{
336 /* Fault while not rebooting. We want the trace. */
337 BUG();
338}
339EXPORT_SYMBOL_GPL(kvm_spurious_fault);
340
3fd28fce
ED		 341#define EXCPT_BENIGN 0
342#define EXCPT_CONTRIBUTORY 1
343#define EXCPT_PF 2
344
345static int exception_class(int vector)
346{
347 switch (vector) {
348 case PF_VECTOR:
349 return EXCPT_PF;
350 case DE_VECTOR:
351 case TS_VECTOR:
352 case NP_VECTOR:
353 case SS_VECTOR:
354 case GP_VECTOR:
355 return EXCPT_CONTRIBUTORY;
356 default:
357 break;
358 }
359 return EXCPT_BENIGN;
360}
361
d6e8c854
NA		 362#define EXCPT_FAULT 0
363#define EXCPT_TRAP 1
364#define EXCPT_ABORT 2
365#define EXCPT_INTERRUPT 3
366
367static int exception_type(int vector)
368{
369 unsigned int mask;
370
371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
372 return EXCPT_INTERRUPT;
373
374 mask = 1 << vector;
375
376 /* #DB is trap, as instruction watchpoints are handled elsewhere */
377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
378 return EXCPT_TRAP;
379
380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
381 return EXCPT_ABORT;
382
383 /* Reserved exceptions will result in fault */
384 return EXCPT_FAULT;
385}
386
3fd28fce 387static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 388 unsigned nr, bool has_error, u32 error_code,
389 bool reinject)
3fd28fce
ED		 390{
391 u32 prev_nr;
392 int class1, class2;
393
3842d135
AK		 394 kvm_make_request(KVM_REQ_EVENT, vcpu);
395
664f8e26 396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 397 queue:
3ffb2468
NA		 398 if (has_error && !is_protmode(vcpu))
399 has_error = false;
664f8e26
WL		 400 if (reinject) {
401 /*
402 * On vmentry, vcpu->arch.exception.pending is only
403 * true if an event injection was blocked by
404 * nested_run_pending. In that case, however,
405 * vcpu_enter_guest requests an immediate exit,
406 * and the guest shouldn't proceed far enough to
407 * need reinjection.
408 */
409 WARN_ON_ONCE(vcpu->arch.exception.pending);
410 vcpu->arch.exception.injected = true;
411 } else {
412 vcpu->arch.exception.pending = true;
413 vcpu->arch.exception.injected = false;
414 }
3fd28fce
ED		 415 vcpu->arch.exception.has_error_code = has_error;
416 vcpu->arch.exception.nr = nr;
417 vcpu->arch.exception.error_code = error_code;
418 return;
419 }
420
421 /* to check exception */
422 prev_nr = vcpu->arch.exception.nr;
423 if (prev_nr == DF_VECTOR) {
424 /* triple fault -> shutdown */
a8eeb04a 425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 426 return;
427 }
428 class1 = exception_class(prev_nr);
429 class2 = exception_class(nr);
430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 432 /*
433 * Generate double fault per SDM Table 5-5. Set
434 * exception.pending = true so that the double fault
435 * can trigger a nested vmexit.
436 */
3fd28fce 437 vcpu->arch.exception.pending = true;
664f8e26 438 vcpu->arch.exception.injected = false;
3fd28fce
ED		 439 vcpu->arch.exception.has_error_code = true;
440 vcpu->arch.exception.nr = DF_VECTOR;
441 vcpu->arch.exception.error_code = 0;
442 } else
443 /* replace previous exception with a new one in a hope
444 that instruction re-execution will regenerate lost
445 exception */
446 goto queue;
447}
448
298101da
AK		 449void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
450{
ce7ddec4 451 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 452}
453EXPORT_SYMBOL_GPL(kvm_queue_exception);
454
ce7ddec4
JR		 455void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
456{
457 kvm_multiple_exception(vcpu, nr, false, 0, true);
458}
459EXPORT_SYMBOL_GPL(kvm_requeue_exception);
460
6affcbed 461int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 462{
db8fcefa
AP		 463 if (err)
464 kvm_inject_gp(vcpu, 0);
465 else
6affcbed
KH		 466 return kvm_skip_emulated_instruction(vcpu);
467
468 return 1;
db8fcefa
AP		 469}
470EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 471
6389ee94 472void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 473{
474 ++vcpu->stat.pf_guest;
adfe20fb
WL		 475 vcpu->arch.exception.nested_apf =
476 is_guest_mode(vcpu) && fault->async_page_fault;
477 if (vcpu->arch.exception.nested_apf)
478 vcpu->arch.apf.nested_apf_token = fault->address;
479 else
480 vcpu->arch.cr2 = fault->address;
6389ee94 481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 482}
27d6c865 483EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 484
ef54bcfe 485static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 486{
6389ee94
AK		 487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 489 else
6389ee94 490 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 491
492 return fault->nested_page_fault;
d4f8cf66
JR		 493}
494
3419ffc8
SY		 495void kvm_inject_nmi(struct kvm_vcpu *vcpu)
496{
7460fb4a
AK		 497 atomic_inc(&vcpu->arch.nmi_queued);
498 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 499}
500EXPORT_SYMBOL_GPL(kvm_inject_nmi);
501
298101da
AK		 502void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
503{
ce7ddec4 504 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 505}
506EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
507
ce7ddec4
JR		 508void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
509{
510 kvm_multiple_exception(vcpu, nr, true, error_code, true);
511}
512EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
513
0a79b009
AK		 514/*
515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
516 * a #GP and return false.
517 */
518bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 519{
0a79b009
AK		 520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
521 return true;
522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
523 return false;
298101da 524}
0a79b009 525EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 526
16f8a6f9
NA		 527bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
528{
529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
530 return true;
531
532 kvm_queue_exception(vcpu, UD_VECTOR);
533 return false;
534}
535EXPORT_SYMBOL_GPL(kvm_require_dr);
536
ec92fe44
JR		 537/*
538 * This function will be used to read from the physical memory of the currently
54bf36aa 539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 540 * can read from guest physical or from the guest's guest physical memory.
541 */
542int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
543 gfn_t ngfn, void *data, int offset, int len,
544 u32 access)
545{
54987b7a 546 struct x86_exception exception;
ec92fe44
JR		 547 gfn_t real_gfn;
548 gpa_t ngpa;
549
550 ngpa = gfn_to_gpa(ngfn);
54987b7a 551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 552 if (real_gfn == UNMAPPED_GVA)
553 return -EFAULT;
554
555 real_gfn = gpa_to_gfn(real_gfn);
556
54bf36aa 557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 558}
559EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
560
69b0049a 561static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 562 void *data, int offset, int len, u32 access)
563{
564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
565 data, offset, len, access);
566}
567
a03490ed
CO		 568/*
569 * Load the pae pdptrs. Return true is they are all valid.
570 */
ff03a073 571int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 572{
573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
575 int i;
576 int ret;
ff03a073 577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 578
ff03a073
JR		 579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
580 offset * sizeof(u64), sizeof(pdpte),
581 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 582 if (ret < 0) {
583 ret = 0;
584 goto out;
585 }
586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 587 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 588 (pdpte[i] &
589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 590 ret = 0;
591 goto out;
592 }
593 }
594 ret = 1;
595
ff03a073 596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 597 __set_bit(VCPU_EXREG_PDPTR,
598 (unsigned long *)&vcpu->arch.regs_avail);
599 __set_bit(VCPU_EXREG_PDPTR,
600 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 601out:
a03490ed
CO		 602
603 return ret;
604}
cc4b6871 605EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 606
9ed38ffa 607bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 608{
ff03a073 609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 610 bool changed = true;
3d06b8bf
JR		 611 int offset;
612 gfn_t gfn;
d835dfec
AK		 613 int r;
614
615 if (is_long_mode(vcpu) || !is_pae(vcpu))
616 return false;
617
6de4f3ad
AK		 618 if (!test_bit(VCPU_EXREG_PDPTR,
619 (unsigned long *)&vcpu->arch.regs_avail))
620 return true;
621
a512177e
PB		 622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
625 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 626 if (r < 0)
627 goto out;
ff03a073 628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 629out:
d835dfec
AK		 630
631 return changed;
632}
9ed38ffa 633EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 634
49a9b07e 635int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 636{
aad82703 637 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 639
f9a48e6a
AK		 640 cr0 |= X86_CR0_ET;
641
ab344828 642#ifdef CONFIG_X86_64
0f12244f
GN		 643 if (cr0 & 0xffffffff00000000UL)
644 return 1;
ab344828
GN		 645#endif
646
647 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
650 return 1;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
653 return 1;
a03490ed
CO		 654
655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
656#ifdef CONFIG_X86_64
f6801dff 657 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 658 int cs_db, cs_l;
659
0f12244f
GN		 660 if (!is_pae(vcpu))
661 return 1;
a03490ed 662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 663 if (cs_l)
664 return 1;
a03490ed
CO		 665 } else
666#endif
ff03a073 667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 668 kvm_read_cr3(vcpu)))
0f12244f 669 return 1;
a03490ed
CO		 670 }
671
ad756a16
MJ		 672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
673 return 1;
674
a03490ed 675 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 676
d170c419 677 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 678 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 679 kvm_async_pf_hash_reset(vcpu);
680 }
e5f3f027 681
aad82703
SY		 682 if ((cr0 ^ old_cr0) & update_bits)
683 kvm_mmu_reset_context(vcpu);
b18d5431 684
879ae188
LE		 685 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
686 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
689
0f12244f
GN		 690 return 0;
691}
2d3ad1f4 692EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 693
2d3ad1f4 694void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 695{
49a9b07e 696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 697}
2d3ad1f4 698EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 699
42bdf991
MT		 700static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
701{
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
703 !vcpu->guest_xcr0_loaded) {
704 /* kvm_set_xcr() also depends on this */
705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
706 vcpu->guest_xcr0_loaded = 1;
707 }
708}
709
710static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (vcpu->guest_xcr0_loaded) {
713 if (vcpu->arch.xcr0 != host_xcr0)
714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
715 vcpu->guest_xcr0_loaded = 0;
716 }
717}
718
69b0049a 719static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 720{
56c103ec
LJ		 721 u64 xcr0 = xcr;
722 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 723 u64 valid_bits;
2acf923e
DC		 724
725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
726 if (index != XCR_XFEATURE_ENABLED_MASK)
727 return 1;
d91cab78 728 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 729 return 1;
d91cab78 730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 731 return 1;
46c34cb0
PB		 732
733 /*
734 * Do not allow the guest to set bits that we do not support
735 * saving. However, xcr0 bit 0 is always set, even if the
736 * emulated CPU does not support XSAVE (see fx_init).
737 */
d91cab78 738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 739 if (xcr0 & ~valid_bits)
2acf923e 740 return 1;
46c34cb0 741
d91cab78
DH		 742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
743 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 744 return 1;
745
d91cab78
DH		 746 if (xcr0 & XFEATURE_MASK_AVX512) {
747 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 748 return 1;
d91cab78 749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 750 return 1;
751 }
2acf923e 752 vcpu->arch.xcr0 = xcr0;
56c103ec 753
d91cab78 754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 755 kvm_update_cpuid(vcpu);
2acf923e
DC		 756 return 0;
757}
758
759int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
760{
764bcbc5
Z		 761 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
762 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 763 kvm_inject_gp(vcpu, 0);
764 return 1;
765 }
766 return 0;
767}
768EXPORT_SYMBOL_GPL(kvm_set_xcr);
769
a83b29c6 770int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 771{
fc78f519 772 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 775
0f12244f
GN		 776 if (cr4 & CR4_RESERVED_BITS)
777 return 1;
a03490ed 778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 789 return 1;
790
d6321d49 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 792 return 1;
793
fd8cb433 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 795 return 1;
796
df9b1e03
PB		 797 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
798 return 1;
799
a03490ed 800 if (is_long_mode(vcpu)) {
0f12244f
GN		 801 if (!(cr4 & X86_CR4_PAE))
802 return 1;
a2edf57f
AK		 803 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
804 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 805 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
806 kvm_read_cr3(vcpu)))
0f12244f
GN		 807 return 1;
808
ad756a16 809 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 810 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 811 return 1;
812
813 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
814 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
815 return 1;
816 }
817
5e1746d6 818 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 819 return 1;
a03490ed 820
ad756a16
MJ		 821 if (((cr4 ^ old_cr4) & pdptr_bits) ||
822 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 823 kvm_mmu_reset_context(vcpu);
0f12244f 824
b9baba86 825 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 826 kvm_update_cpuid(vcpu);
2acf923e 827
0f12244f
GN		 828 return 0;
829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 831
2390218b 832int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 833{
ac146235 834#ifdef CONFIG_X86_64
9d88fca7 835 cr3 &= ~CR3_PCID_INVD;
ac146235 836#endif
9d88fca7 837
9f8fe504 838 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 839 kvm_mmu_sync_roots(vcpu);
77c3913b 840 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 841 return 0;
d835dfec
AK		 842 }
843
d1cd3ce9
YZ		 844 if (is_long_mode(vcpu) &&
845 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
846 return 1;
847 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 848 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 849 return 1;
a03490ed 850
0f12244f 851 vcpu->arch.cr3 = cr3;
aff48baa 852 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 853 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 854 return 0;
855}
2d3ad1f4 856EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 857
eea1cff9 858int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 859{
0f12244f
GN		 860 if (cr8 & CR8_RESERVED_BITS)
861 return 1;
35754c98 862 if (lapic_in_kernel(vcpu))
a03490ed
CO		 863 kvm_lapic_set_tpr(vcpu, cr8);
864 else
ad312c7c 865 vcpu->arch.cr8 = cr8;
0f12244f
GN		 866 return 0;
867}
2d3ad1f4 868EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 869
2d3ad1f4 870unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 871{
35754c98 872 if (lapic_in_kernel(vcpu))
a03490ed
CO		 873 return kvm_lapic_get_cr8(vcpu);
874 else
ad312c7c 875 return vcpu->arch.cr8;
a03490ed 876}
2d3ad1f4 877EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 878
ae561ede
NA		 879static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
880{
881 int i;
882
883 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
884 for (i = 0; i < KVM_NR_DB_REGS; i++)
885 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
886 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
887 }
888}
889
73aaf249
JK		 890static void kvm_update_dr6(struct kvm_vcpu *vcpu)
891{
892 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
893 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
894}
895
c8639010
JK		 896static void kvm_update_dr7(struct kvm_vcpu *vcpu)
897{
898 unsigned long dr7;
899
900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
901 dr7 = vcpu->arch.guest_debug_dr7;
902 else
903 dr7 = vcpu->arch.dr7;
904 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 905 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
906 if (dr7 & DR7_BP_EN_MASK)
907 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 908}
909
6f43ed01
NA		 910static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
911{
912 u64 fixed = DR6_FIXED_1;
913
d6321d49 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 915 fixed |= DR6_RTM;
916 return fixed;
917}
918
338dbc97 919static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 920{
921 switch (dr) {
922 case 0 ... 3:
923 vcpu->arch.db[dr] = val;
924 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
925 vcpu->arch.eff_db[dr] = val;
926 break;
927 case 4:
020df079
GN		 928 /* fall through */
929 case 6:
338dbc97
GN		 930 if (val & 0xffffffff00000000ULL)
931 return -1; /* #GP */
6f43ed01 932 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 933 kvm_update_dr6(vcpu);
020df079
GN		 934 break;
935 case 5:
020df079
GN		 936 /* fall through */
937 default: /* 7 */
338dbc97
GN		 938 if (val & 0xffffffff00000000ULL)
939 return -1; /* #GP */
020df079 940 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 941 kvm_update_dr7(vcpu);
020df079
GN		 942 break;
943 }
944
945 return 0;
946}
338dbc97
GN		 947
948int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
949{
16f8a6f9 950 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 951 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 952 return 1;
953 }
954 return 0;
338dbc97 955}
020df079
GN		 956EXPORT_SYMBOL_GPL(kvm_set_dr);
957
16f8a6f9 958int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 959{
960 switch (dr) {
961 case 0 ... 3:
962 *val = vcpu->arch.db[dr];
963 break;
964 case 4:
020df079
GN		 965 /* fall through */
966 case 6:
73aaf249
JK		 967 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
968 *val = vcpu->arch.dr6;
969 else
970 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 971 break;
972 case 5:
020df079
GN		 973 /* fall through */
974 default: /* 7 */
975 *val = vcpu->arch.dr7;
976 break;
977 }
338dbc97
GN		 978 return 0;
979}
020df079
GN		 980EXPORT_SYMBOL_GPL(kvm_get_dr);
981
022cd0e8
AK		 982bool kvm_rdpmc(struct kvm_vcpu *vcpu)
983{
984 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
985 u64 data;
986 int err;
987
c6702c9d 988 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 989 if (err)
990 return err;
991 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
992 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
993 return err;
994}
995EXPORT_SYMBOL_GPL(kvm_rdpmc);
996
043405e1
CO		 997/*
998 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
999 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1000 *
1001 * This list is modified at module load time to reflect the
e3267cbb 1002 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1003 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1004 * may depend on host virtualization features rather than host cpu features.
043405e1 1005 */
e3267cbb 1006
043405e1
CO		 1007static u32 msrs_to_save[] = {
1008 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1009 MSR_STAR,
043405e1
CO		 1010#ifdef CONFIG_X86_64
1011 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1012#endif
b3897a49 1013 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1014 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
74469996 1015 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1016};
1017
1018static unsigned num_msrs_to_save;
1019
62ef68bb
PB		 1020static u32 emulated_msrs[] = {
1021 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1022 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1023 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1024 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1025 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1026 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1027 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1028 HV_X64_MSR_RESET,
11c4b1ca 1029 HV_X64_MSR_VP_INDEX,
9eec50b8 1030 HV_X64_MSR_VP_RUNTIME,
5c919412 1031 HV_X64_MSR_SCONTROL,
1f4b34f8 1032 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1033 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1034 MSR_KVM_PV_EOI_EN,
1035
ba904635 1036 MSR_IA32_TSC_ADJUST,
a3e06bbe 1037 MSR_IA32_TSCDEADLINE,
043405e1 1038 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1039 MSR_IA32_MCG_STATUS,
1040 MSR_IA32_MCG_CTL,
c45dcc71 1041 MSR_IA32_MCG_EXT_CTL,
64d60670 1042 MSR_IA32_SMBASE,
db2336a8
KH		 1043 MSR_PLATFORM_INFO,
1044 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1045};
1046
62ef68bb
PB		 1047static unsigned num_emulated_msrs;
1048
384bb783 1049bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1050{
b69e8cae 1051 if (efer & efer_reserved_bits)
384bb783 1052 return false;
15c4a640 1053
1b4d56b8 1054 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1055 return false;
1b2fd70c 1056
1b4d56b8 1057 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1058 return false;
d8017474 1059
384bb783
JK		 1060 return true;
1061}
1062EXPORT_SYMBOL_GPL(kvm_valid_efer);
1063
1064static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1065{
1066 u64 old_efer = vcpu->arch.efer;
1067
1068 if (!kvm_valid_efer(vcpu, efer))
1069 return 1;
1070
1071 if (is_paging(vcpu)
1072 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1073 return 1;
1074
15c4a640 1075 efer &= ~EFER_LMA;
f6801dff 1076 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1077
a3d204e2
SY		 1078 kvm_x86_ops->set_efer(vcpu, efer);
1079
aad82703
SY		 1080 /* Update reserved bits */
1081 if ((efer ^ old_efer) & EFER_NX)
1082 kvm_mmu_reset_context(vcpu);
1083
b69e8cae 1084 return 0;
15c4a640
CO		 1085}
1086
f2b4b7dd
JR		 1087void kvm_enable_efer_bits(u64 mask)
1088{
1089 efer_reserved_bits &= ~mask;
1090}
1091EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1092
15c4a640
CO		 1093/*
1094 * Writes msr value into into the appropriate "register".
1095 * Returns 0 on success, non-0 otherwise.
1096 * Assumes vcpu_load() was already called.
1097 */
8fe8ab46 1098int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1099{
854e8bb1
NA		 1100 switch (msr->index) {
1101 case MSR_FS_BASE:
1102 case MSR_GS_BASE:
1103 case MSR_KERNEL_GS_BASE:
1104 case MSR_CSTAR:
1105 case MSR_LSTAR:
fd8cb433 1106 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1107 return 1;
1108 break;
1109 case MSR_IA32_SYSENTER_EIP:
1110 case MSR_IA32_SYSENTER_ESP:
1111 /*
1112 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1113 * non-canonical address is written on Intel but not on
1114 * AMD (which ignores the top 32-bits, because it does
1115 * not implement 64-bit SYSENTER).
1116 *
1117 * 64-bit code should hence be able to write a non-canonical
1118 * value on AMD. Making the address canonical ensures that
1119 * vmentry does not fail on Intel after writing a non-canonical
1120 * value, and that something deterministic happens if the guest
1121 * invokes 64-bit SYSENTER.
1122 */
fd8cb433 1123 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1124 }
8fe8ab46 1125 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1126}
854e8bb1 1127EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1128
313a3dc7
CO		 1129/*
1130 * Adapt set_msr() to msr_io()'s calling convention
1131 */
609e36d3
PB		 1132static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1133{
1134 struct msr_data msr;
1135 int r;
1136
1137 msr.index = index;
1138 msr.host_initiated = true;
1139 r = kvm_get_msr(vcpu, &msr);
1140 if (r)
1141 return r;
1142
1143 *data = msr.data;
1144 return 0;
1145}
1146
313a3dc7
CO		 1147static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1148{
8fe8ab46
WA		 1149 struct msr_data msr;
1150
1151 msr.data = *data;
1152 msr.index = index;
1153 msr.host_initiated = true;
1154 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1155}
1156
16e8d74d
MT		 1157#ifdef CONFIG_X86_64
1158struct pvclock_gtod_data {
1159 seqcount_t seq;
1160
1161 struct { /* extract of a clocksource struct */
1162 int vclock_mode;
a5a1d1c2
TG		 1163 u64 cycle_last;
1164 u64 mask;
16e8d74d
MT		 1165 u32 mult;
1166 u32 shift;
1167 } clock;
1168
cbcf2dd3
TG		 1169 u64 boot_ns;
1170 u64 nsec_base;
55dd00a7 1171 u64 wall_time_sec;
16e8d74d
MT		 1172};
1173
1174static struct pvclock_gtod_data pvclock_gtod_data;
1175
1176static void update_pvclock_gtod(struct timekeeper *tk)
1177{
1178 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1179 u64 boot_ns;
1180
876e7881 1181 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1182
1183 write_seqcount_begin(&vdata->seq);
1184
1185 /* copy pvclock gtod data */
876e7881
PZ		 1186 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1187 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1188 vdata->clock.mask = tk->tkr_mono.mask;
1189 vdata->clock.mult = tk->tkr_mono.mult;
1190 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1191
cbcf2dd3 1192 vdata->boot_ns = boot_ns;
876e7881 1193 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1194
55dd00a7
MT		 1195 vdata->wall_time_sec = tk->xtime_sec;
1196
16e8d74d
MT		 1197 write_seqcount_end(&vdata->seq);
1198}
1199#endif
1200
bab5bb39
NK		 1201void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1202{
1203 /*
1204 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1205 * vcpu_enter_guest. This function is only called from
1206 * the physical CPU that is running vcpu.
1207 */
1208 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1209}
16e8d74d 1210
18068523
GOC		 1211static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1212{
9ed3c444
AK		 1213 int version;
1214 int r;
50d0a0f9 1215 struct pvclock_wall_clock wc;
87aeb54f 1216 struct timespec64 boot;
18068523
GOC		 1217
1218 if (!wall_clock)
1219 return;
1220
9ed3c444
AK		 1221 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1222 if (r)
1223 return;
1224
1225 if (version & 1)
1226 ++version; /* first time write, random junk */
1227
1228 ++version;
18068523 1229
1dab1345
NK		 1230 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1231 return;
18068523 1232
50d0a0f9
GH		 1233 /*
1234 * The guest calculates current wall clock time by adding
34c238a1 1235 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1236 * wall clock specified here. guest system time equals host
1237 * system time for us, thus we must fill in host boot time here.
1238 */
87aeb54f 1239 getboottime64(&boot);
50d0a0f9 1240
4b648665 1241 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1242 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1243 boot = timespec64_sub(boot, ts);
4b648665 1244 }
87aeb54f 1245 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1246 wc.nsec = boot.tv_nsec;
1247 wc.version = version;
18068523
GOC		 1248
1249 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1250
1251 version++;
1252 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1253}
1254
50d0a0f9
GH		 1255static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1256{
b51012de
PB		 1257 do_shl32_div32(dividend, divisor);
1258 return dividend;
50d0a0f9
GH		 1259}
1260
3ae13faa 1261static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1262 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1263{
5f4e3f88 1264 uint64_t scaled64;
50d0a0f9
GH		 1265 int32_t shift = 0;
1266 uint64_t tps64;
1267 uint32_t tps32;
1268
3ae13faa
PB		 1269 tps64 = base_hz;
1270 scaled64 = scaled_hz;
50933623 1271 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1272 tps64 >>= 1;
1273 shift--;
1274 }
1275
1276 tps32 = (uint32_t)tps64;
50933623
JK		 1277 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1278 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1279 scaled64 >>= 1;
1280 else
1281 tps32 <<= 1;
50d0a0f9
GH		 1282 shift++;
1283 }
1284
5f4e3f88
ZA		 1285 *pshift = shift;
1286 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1287
3ae13faa
PB		 1288 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1289 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1290}
1291
d828199e 1292#ifdef CONFIG_X86_64
16e8d74d 1293static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1294#endif
16e8d74d 1295
c8076604 1296static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1297static unsigned long max_tsc_khz;
c8076604 1298
cc578287 1299static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1300{
cc578287
ZA		 1301 u64 v = (u64)khz * (1000000 + ppm);
1302 do_div(v, 1000000);
1303 return v;
1e993611
JR		 1304}
1305
381d585c
HZ		 1306static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1307{
1308 u64 ratio;
1309
1310 /* Guest TSC same frequency as host TSC? */
1311 if (!scale) {
1312 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1313 return 0;
1314 }
1315
1316 /* TSC scaling supported? */
1317 if (!kvm_has_tsc_control) {
1318 if (user_tsc_khz > tsc_khz) {
1319 vcpu->arch.tsc_catchup = 1;
1320 vcpu->arch.tsc_always_catchup = 1;
1321 return 0;
1322 } else {
1323 WARN(1, "user requested TSC rate below hardware speed\n");
1324 return -1;
1325 }
1326 }
1327
1328 /* TSC scaling required - calculate ratio */
1329 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1330 user_tsc_khz, tsc_khz);
1331
1332 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1333 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1334 user_tsc_khz);
1335 return -1;
1336 }
1337
1338 vcpu->arch.tsc_scaling_ratio = ratio;
1339 return 0;
1340}
1341
4941b8cb 1342static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1343{
cc578287
ZA		 1344 u32 thresh_lo, thresh_hi;
1345 int use_scaling = 0;
217fc9cf 1346
03ba32ca 1347 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1348 if (user_tsc_khz == 0) {
ad721883
HZ		 1349 /* set tsc_scaling_ratio to a safe value */
1350 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1351 return -1;
ad721883 1352 }
03ba32ca 1353
c285545f 1354 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1355 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1356 &vcpu->arch.virtual_tsc_shift,
1357 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1358 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1359
1360 /*
1361 * Compute the variation in TSC rate which is acceptable
1362 * within the range of tolerance and decide if the
1363 * rate being applied is within that bounds of the hardware
1364 * rate. If so, no scaling or compensation need be done.
1365 */
1366 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1367 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1368 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1369 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1370 use_scaling = 1;
1371 }
4941b8cb 1372 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1373}
1374
1375static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1376{
e26101b1 1377 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1378 vcpu->arch.virtual_tsc_mult,
1379 vcpu->arch.virtual_tsc_shift);
e26101b1 1380 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1381 return tsc;
1382}
1383
69b0049a 1384static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1385{
1386#ifdef CONFIG_X86_64
1387 bool vcpus_matched;
b48aa97e
MT		 1388 struct kvm_arch *ka = &vcpu->kvm->arch;
1389 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1390
1391 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1392 atomic_read(&vcpu->kvm->online_vcpus));
1393
7f187922
MT		 1394 /*
1395 * Once the masterclock is enabled, always perform request in
1396 * order to update it.
1397 *
1398 * In order to enable masterclock, the host clocksource must be TSC
1399 * and the vcpus need to have matched TSCs. When that happens,
1400 * perform request to enable masterclock.
1401 */
1402 if (ka->use_master_clock ||
1403 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1404 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1405
1406 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1407 atomic_read(&vcpu->kvm->online_vcpus),
1408 ka->use_master_clock, gtod->clock.vclock_mode);
1409#endif
1410}
1411
ba904635
WA		 1412static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1413{
3e3f5026 1414 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1415 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1416}
1417
35181e86
HZ		 1418/*
1419 * Multiply tsc by a fixed point number represented by ratio.
1420 *
1421 * The most significant 64-N bits (mult) of ratio represent the
1422 * integral part of the fixed point number; the remaining N bits
1423 * (frac) represent the fractional part, ie. ratio represents a fixed
1424 * point number (mult + frac * 2^(-N)).
1425 *
1426 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1427 */
1428static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1429{
1430 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1431}
1432
1433u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1434{
1435 u64 _tsc = tsc;
1436 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1437
1438 if (ratio != kvm_default_tsc_scaling_ratio)
1439 _tsc = __scale_tsc(ratio, tsc);
1440
1441 return _tsc;
1442}
1443EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1444
07c1419a
HZ		 1445static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1446{
1447 u64 tsc;
1448
1449 tsc = kvm_scale_tsc(vcpu, rdtsc());
1450
1451 return target_tsc - tsc;
1452}
1453
4ba76538
HZ		 1454u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1455{
ea26e4ec 1456 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1457}
1458EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1459
a545ab6a
LC		 1460static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1461{
1462 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1463 vcpu->arch.tsc_offset = offset;
1464}
1465
8fe8ab46 1466void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1467{
1468 struct kvm *kvm = vcpu->kvm;
f38e098f 1469 u64 offset, ns, elapsed;
99e3e30a 1470 unsigned long flags;
b48aa97e 1471 bool matched;
0d3da0d2 1472 bool already_matched;
8fe8ab46 1473 u64 data = msr->data;
c5e8ec8e 1474 bool synchronizing = false;
99e3e30a 1475
038f8c11 1476 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1477 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1478 ns = ktime_get_boot_ns();
f38e098f 1479 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1480
03ba32ca 1481 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1482 if (data == 0 && msr->host_initiated) {
1483 /*
1484 * detection of vcpu initialization -- need to sync
1485 * with other vCPUs. This particularly helps to keep
1486 * kvm_clock stable after CPU hotplug
1487 */
1488 synchronizing = true;
1489 } else {
1490 u64 tsc_exp = kvm->arch.last_tsc_write +
1491 nsec_to_cycles(vcpu, elapsed);
1492 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1493 /*
1494 * Special case: TSC write with a small delta (1 second)
1495 * of virtual cycle time against real time is
1496 * interpreted as an attempt to synchronize the CPU.
1497 */
1498 synchronizing = data < tsc_exp + tsc_hz &&
1499 data + tsc_hz > tsc_exp;
1500 }
c5e8ec8e 1501 }
f38e098f
ZA		 1502
1503 /*
5d3cb0f6
ZA		 1504 * For a reliable TSC, we can match TSC offsets, and for an unstable
1505 * TSC, we add elapsed time in this computation. We could let the
1506 * compensation code attempt to catch up if we fall behind, but
1507 * it's better to try to match offsets from the beginning.
1508 */
c5e8ec8e 1509 if (synchronizing &&
5d3cb0f6 1510 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1511 if (!check_tsc_unstable()) {
e26101b1 1512 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1513 pr_debug("kvm: matched tsc offset for %llu\n", data);
1514 } else {
857e4099 1515 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1516 data += delta;
07c1419a 1517 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1518 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1519 }
b48aa97e 1520 matched = true;
0d3da0d2 1521 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1522 } else {
1523 /*
1524 * We split periods of matched TSC writes into generations.
1525 * For each generation, we track the original measured
1526 * nanosecond time, offset, and write, so if TSCs are in
1527 * sync, we can match exact offset, and if not, we can match
4a969980 1528 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1529 *
1530 * These values are tracked in kvm->arch.cur_xxx variables.
1531 */
1532 kvm->arch.cur_tsc_generation++;
1533 kvm->arch.cur_tsc_nsec = ns;
1534 kvm->arch.cur_tsc_write = data;
1535 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1536 matched = false;
0d3da0d2 1537 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1538 kvm->arch.cur_tsc_generation, data);
f38e098f 1539 }
e26101b1
ZA		 1540
1541 /*
1542 * We also track th most recent recorded KHZ, write and time to
1543 * allow the matching interval to be extended at each write.
1544 */
f38e098f
ZA		 1545 kvm->arch.last_tsc_nsec = ns;
1546 kvm->arch.last_tsc_write = data;
5d3cb0f6 1547 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1548
b183aa58 1549 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1550
1551 /* Keep track of which generation this VCPU has synchronized to */
1552 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1553 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1554 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1555
d6321d49 1556 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1557 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1558
a545ab6a 1559 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1560 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1561
1562 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1563 if (!matched) {
b48aa97e 1564 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1565 } else if (!already_matched) {
1566 kvm->arch.nr_vcpus_matched_tsc++;
1567 }
b48aa97e
MT		 1568
1569 kvm_track_tsc_matching(vcpu);
1570 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1571}
e26101b1 1572
99e3e30a
ZA		 1573EXPORT_SYMBOL_GPL(kvm_write_tsc);
1574
58ea6767
HZ		 1575static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1576 s64 adjustment)
1577{
ea26e4ec 1578 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1579}
1580
1581static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1582{
1583 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1584 WARN_ON(adjustment < 0);
1585 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1586 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1587}
1588
d828199e
MT		 1589#ifdef CONFIG_X86_64
1590
a5a1d1c2 1591static u64 read_tsc(void)
d828199e 1592{
a5a1d1c2 1593 u64 ret = (u64)rdtsc_ordered();
03b9730b 1594 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1595
1596 if (likely(ret >= last))
1597 return ret;
1598
1599 /*
1600 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1601 * predictable (it's just a function of time and the likely is
d828199e
MT		 1602 * very likely) and there's a data dependence, so force GCC
1603 * to generate a branch instead. I don't barrier() because
1604 * we don't actually need a barrier, and if this function
1605 * ever gets inlined it will generate worse code.
1606 */
1607 asm volatile ("");
1608 return last;
1609}
1610
a5a1d1c2 1611static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1612{
1613 long v;
1614 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1615
1616 *cycle_now = read_tsc();
1617
1618 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1619 return v * gtod->clock.mult;
1620}
1621
a5a1d1c2 1622static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1623{
cbcf2dd3 1624 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1625 unsigned long seq;
d828199e 1626 int mode;
cbcf2dd3 1627 u64 ns;
d828199e 1628
d828199e
MT		 1629 do {
1630 seq = read_seqcount_begin(&gtod->seq);
1631 mode = gtod->clock.vclock_mode;
cbcf2dd3 1632 ns = gtod->nsec_base;
d828199e
MT		 1633 ns += vgettsc(cycle_now);
1634 ns >>= gtod->clock.shift;
cbcf2dd3 1635 ns += gtod->boot_ns;
d828199e 1636 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1637 *t = ns;
d828199e
MT		 1638
1639 return mode;
1640}
1641
55dd00a7
MT		 1642static int do_realtime(struct timespec *ts, u64 *cycle_now)
1643{
1644 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1645 unsigned long seq;
1646 int mode;
1647 u64 ns;
1648
1649 do {
1650 seq = read_seqcount_begin(&gtod->seq);
1651 mode = gtod->clock.vclock_mode;
1652 ts->tv_sec = gtod->wall_time_sec;
1653 ns = gtod->nsec_base;
1654 ns += vgettsc(cycle_now);
1655 ns >>= gtod->clock.shift;
1656 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1657
1658 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1659 ts->tv_nsec = ns;
1660
1661 return mode;
1662}
1663
d828199e 1664/* returns true if host is using tsc clocksource */
a5a1d1c2 1665static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1666{
d828199e
MT		 1667 /* checked again under seqlock below */
1668 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1669 return false;
1670
cbcf2dd3 1671 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1672}
55dd00a7
MT		 1673
1674/* returns true if host is using tsc clocksource */
1675static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1676 u64 *cycle_now)
1677{
1678 /* checked again under seqlock below */
1679 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1680 return false;
1681
1682 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1683}
d828199e
MT		 1684#endif
1685
1686/*
1687 *
b48aa97e
MT		 1688 * Assuming a stable TSC across physical CPUS, and a stable TSC
1689 * across virtual CPUs, the following condition is possible.
1690 * Each numbered line represents an event visible to both
d828199e
MT		 1691 * CPUs at the next numbered event.
1692 *
1693 * "timespecX" represents host monotonic time. "tscX" represents
1694 * RDTSC value.
1695 *
1696 * VCPU0 on CPU0 | VCPU1 on CPU1
1697 *
1698 * 1. read timespec0,tsc0
1699 * 2. | timespec1 = timespec0 + N
1700 * | tsc1 = tsc0 + M
1701 * 3. transition to guest | transition to guest
1702 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1703 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1704 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1705 *
1706 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1707 *
1708 * - ret0 < ret1
1709 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1710 * ...
1711 * - 0 < N - M => M < N
1712 *
1713 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1714 * always the case (the difference between two distinct xtime instances
1715 * might be smaller then the difference between corresponding TSC reads,
1716 * when updating guest vcpus pvclock areas).
1717 *
1718 * To avoid that problem, do not allow visibility of distinct
1719 * system_timestamp/tsc_timestamp values simultaneously: use a master
1720 * copy of host monotonic time values. Update that master copy
1721 * in lockstep.
1722 *
b48aa97e 1723 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1724 *
1725 */
1726
1727static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1728{
1729#ifdef CONFIG_X86_64
1730 struct kvm_arch *ka = &kvm->arch;
1731 int vclock_mode;
b48aa97e
MT		 1732 bool host_tsc_clocksource, vcpus_matched;
1733
1734 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1735 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1736
1737 /*
1738 * If the host uses TSC clock, then passthrough TSC as stable
1739 * to the guest.
1740 */
b48aa97e 1741 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1742 &ka->master_kernel_ns,
1743 &ka->master_cycle_now);
1744
16a96021 1745 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1746 && !ka->backwards_tsc_observed
54750f2c 1747 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1748
d828199e
MT		 1749 if (ka->use_master_clock)
1750 atomic_set(&kvm_guest_has_master_clock, 1);
1751
1752 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1753 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1754 vcpus_matched);
d828199e
MT		 1755#endif
1756}
1757
2860c4b1
PB		 1758void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1759{
1760 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1761}
1762
2e762ff7
MT		 1763static void kvm_gen_update_masterclock(struct kvm *kvm)
1764{
1765#ifdef CONFIG_X86_64
1766 int i;
1767 struct kvm_vcpu *vcpu;
1768 struct kvm_arch *ka = &kvm->arch;
1769
1770 spin_lock(&ka->pvclock_gtod_sync_lock);
1771 kvm_make_mclock_inprogress_request(kvm);
1772 /* no guest entries from this point */
1773 pvclock_update_vm_gtod_copy(kvm);
1774
1775 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1776 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1777
1778 /* guest entries allowed */
1779 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1780 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1781
1782 spin_unlock(&ka->pvclock_gtod_sync_lock);
1783#endif
1784}
1785
e891a32e 1786u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1787{
108b249c 1788 struct kvm_arch *ka = &kvm->arch;
8b953440 1789 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1790 u64 ret;
108b249c 1791
8b953440
PB		 1792 spin_lock(&ka->pvclock_gtod_sync_lock);
1793 if (!ka->use_master_clock) {
1794 spin_unlock(&ka->pvclock_gtod_sync_lock);
1795 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1796 }
1797
8b953440
PB		 1798 hv_clock.tsc_timestamp = ka->master_cycle_now;
1799 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1800 spin_unlock(&ka->pvclock_gtod_sync_lock);
1801
e2c2206a
WL		 1802 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1803 get_cpu();
1804
e70b57a6
WL		 1805 if (__this_cpu_read(cpu_tsc_khz)) {
1806 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1807 &hv_clock.tsc_shift,
1808 &hv_clock.tsc_to_system_mul);
1809 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1810 } else
1811 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1812
1813 put_cpu();
1814
1815 return ret;
108b249c
PB		 1816}
1817
0d6dd2ff
PB		 1818static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1819{
1820 struct kvm_vcpu_arch *vcpu = &v->arch;
1821 struct pvclock_vcpu_time_info guest_hv_clock;
1822
4e335d9e 1823 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1824 &guest_hv_clock, sizeof(guest_hv_clock))))
1825 return;
1826
1827 /* This VCPU is paused, but it's legal for a guest to read another
1828 * VCPU's kvmclock, so we really have to follow the specification where
1829 * it says that version is odd if data is being modified, and even after
1830 * it is consistent.
1831 *
1832 * Version field updates must be kept separate. This is because
1833 * kvm_write_guest_cached might use a "rep movs" instruction, and
1834 * writes within a string instruction are weakly ordered. So there
1835 * are three writes overall.
1836 *
1837 * As a small optimization, only write the version field in the first
1838 * and third write. The vcpu->pv_time cache is still valid, because the
1839 * version field is the first in the struct.
1840 */
1841 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1842
51c4b8bb
LA		 1843 if (guest_hv_clock.version & 1)
1844 ++guest_hv_clock.version; /* first time write, random junk */
1845
0d6dd2ff 1846 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1847 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1848 &vcpu->hv_clock,
1849 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1850
1851 smp_wmb();
1852
1853 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1854 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1855
1856 if (vcpu->pvclock_set_guest_stopped_request) {
1857 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1858 vcpu->pvclock_set_guest_stopped_request = false;
1859 }
1860
1861 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1862
4e335d9e
PB		 1863 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1864 &vcpu->hv_clock,
1865 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1866
1867 smp_wmb();
1868
1869 vcpu->hv_clock.version++;
4e335d9e
PB		 1870 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1871 &vcpu->hv_clock,
1872 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1873}
1874
34c238a1 1875static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1876{
78db6a50 1877 unsigned long flags, tgt_tsc_khz;
18068523 1878 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1879 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1880 s64 kernel_ns;
d828199e 1881 u64 tsc_timestamp, host_tsc;
51d59c6b 1882 u8 pvclock_flags;
d828199e
MT		 1883 bool use_master_clock;
1884
1885 kernel_ns = 0;
1886 host_tsc = 0;
18068523 1887
d828199e
MT		 1888 /*
1889 * If the host uses TSC clock, then passthrough TSC as stable
1890 * to the guest.
1891 */
1892 spin_lock(&ka->pvclock_gtod_sync_lock);
1893 use_master_clock = ka->use_master_clock;
1894 if (use_master_clock) {
1895 host_tsc = ka->master_cycle_now;
1896 kernel_ns = ka->master_kernel_ns;
1897 }
1898 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1899
1900 /* Keep irq disabled to prevent changes to the clock */
1901 local_irq_save(flags);
78db6a50
PB		 1902 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1903 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1904 local_irq_restore(flags);
1905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1906 return 1;
1907 }
d828199e 1908 if (!use_master_clock) {
4ea1636b 1909 host_tsc = rdtsc();
108b249c 1910 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1911 }
1912
4ba76538 1913 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1914
c285545f
ZA		 1915 /*
1916 * We may have to catch up the TSC to match elapsed wall clock
1917 * time for two reasons, even if kvmclock is used.
1918 * 1) CPU could have been running below the maximum TSC rate
1919 * 2) Broken TSC compensation resets the base at each VCPU
1920 * entry to avoid unknown leaps of TSC even when running
1921 * again on the same CPU. This may cause apparent elapsed
1922 * time to disappear, and the guest to stand still or run
1923 * very slowly.
1924 */
1925 if (vcpu->tsc_catchup) {
1926 u64 tsc = compute_guest_tsc(v, kernel_ns);
1927 if (tsc > tsc_timestamp) {
f1e2b260 1928 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1929 tsc_timestamp = tsc;
1930 }
50d0a0f9
GH		 1931 }
1932
18068523
GOC		 1933 local_irq_restore(flags);
1934
0d6dd2ff 1935 /* With all the info we got, fill in the values */
18068523 1936
78db6a50
PB		 1937 if (kvm_has_tsc_control)
1938 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1939
1940 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1941 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1942 &vcpu->hv_clock.tsc_shift,
1943 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1944 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1945 }
1946
1d5f066e 1947 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1948 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1949 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1950
d828199e 1951 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1952 pvclock_flags = 0;
d828199e
MT		 1953 if (use_master_clock)
1954 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1955
78c0337a
MT		 1956 vcpu->hv_clock.flags = pvclock_flags;
1957
095cf55d
PB		 1958 if (vcpu->pv_time_enabled)
1959 kvm_setup_pvclock_page(v);
1960 if (v == kvm_get_vcpu(v->kvm, 0))
1961 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1962 return 0;
c8076604
GH		 1963}
1964
0061d53d
MT		 1965/*
1966 * kvmclock updates which are isolated to a given vcpu, such as
1967 * vcpu->cpu migration, should not allow system_timestamp from
1968 * the rest of the vcpus to remain static. Otherwise ntp frequency
1969 * correction applies to one vcpu's system_timestamp but not
1970 * the others.
1971 *
1972 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1973 * We need to rate-limit these requests though, as they can
1974 * considerably slow guests that have a large number of vcpus.
1975 * The time for a remote vcpu to update its kvmclock is bound
1976 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1977 */
1978
7e44e449
AJ		 1979#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1980
1981static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1982{
1983 int i;
7e44e449
AJ		 1984 struct delayed_work *dwork = to_delayed_work(work);
1985 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1986 kvmclock_update_work);
1987 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1988 struct kvm_vcpu *vcpu;
1989
1990 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1991 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1992 kvm_vcpu_kick(vcpu);
1993 }
1994}
1995
7e44e449
AJ		 1996static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1997{
1998 struct kvm *kvm = v->kvm;
1999
105b21bb 2000 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2001 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2002 KVMCLOCK_UPDATE_DELAY);
2003}
2004
332967a3
AJ		 2005#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2006
2007static void kvmclock_sync_fn(struct work_struct *work)
2008{
2009 struct delayed_work *dwork = to_delayed_work(work);
2010 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2011 kvmclock_sync_work);
2012 struct kvm *kvm = container_of(ka, struct kvm, arch);
2013
630994b3
MT		 2014 if (!kvmclock_periodic_sync)
2015 return;
2016
332967a3
AJ		 2017 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2018 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2019 KVMCLOCK_SYNC_PERIOD);
2020}
2021
9ffd986c 2022static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2023{
890ca9ae
HY		 2024 u64 mcg_cap = vcpu->arch.mcg_cap;
2025 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2026 u32 msr = msr_info->index;
2027 u64 data = msr_info->data;
890ca9ae 2028
15c4a640 2029 switch (msr) {
15c4a640 2030 case MSR_IA32_MCG_STATUS:
890ca9ae 2031 vcpu->arch.mcg_status = data;
15c4a640 2032 break;
c7ac679c 2033 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2034 if (!(mcg_cap & MCG_CTL_P))
2035 return 1;
2036 if (data != 0 && data != ~(u64)0)
2037 return -1;
2038 vcpu->arch.mcg_ctl = data;
2039 break;
2040 default:
2041 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2042 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2043 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2044 /* only 0 or all 1s can be written to IA32_MCi_CTL
2045 * some Linux kernels though clear bit 10 in bank 4 to
2046 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2047 * this to avoid an uncatched #GP in the guest
2048 */
890ca9ae 2049 if ((offset & 0x3) == 0 &&
114be429 2050 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2051 return -1;
9ffd986c
WL		 2052 if (!msr_info->host_initiated &&
2053 (offset & 0x3) == 1 && data != 0)
2054 return -1;
890ca9ae
HY		 2055 vcpu->arch.mce_banks[offset] = data;
2056 break;
2057 }
2058 return 1;
2059 }
2060 return 0;
2061}
2062
ffde22ac
ES		 2063static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2064{
2065 struct kvm *kvm = vcpu->kvm;
2066 int lm = is_long_mode(vcpu);
2067 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2068 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2069 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2070 : kvm->arch.xen_hvm_config.blob_size_32;
2071 u32 page_num = data & ~PAGE_MASK;
2072 u64 page_addr = data & PAGE_MASK;
2073 u8 *page;
2074 int r;
2075
2076 r = -E2BIG;
2077 if (page_num >= blob_size)
2078 goto out;
2079 r = -ENOMEM;
ff5c2c03
SL		 2080 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2081 if (IS_ERR(page)) {
2082 r = PTR_ERR(page);
ffde22ac 2083 goto out;
ff5c2c03 2084 }
54bf36aa 2085 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2086 goto out_free;
2087 r = 0;
2088out_free:
2089 kfree(page);
2090out:
2091 return r;
2092}
2093
344d9588
GN		 2094static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2095{
2096 gpa_t gpa = data & ~0x3f;
2097
52a5c155
WL		 2098 /* Bits 3:5 are reserved, Should be zero */
2099 if (data & 0x38)
344d9588
GN		 2100 return 1;
2101
2102 vcpu->arch.apf.msr_val = data;
2103
2104 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2105 kvm_clear_async_pf_completion_queue(vcpu);
2106 kvm_async_pf_hash_reset(vcpu);
2107 return 0;
2108 }
2109
4e335d9e 2110 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2111 sizeof(u32)))
344d9588
GN		 2112 return 1;
2113
6adba527 2114 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2115 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2116 kvm_async_pf_wakeup_all(vcpu);
2117 return 0;
2118}
2119
12f9a48f
GC		 2120static void kvmclock_reset(struct kvm_vcpu *vcpu)
2121{
0b79459b 2122 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2123}
2124
c9aaa895
GC		 2125static void record_steal_time(struct kvm_vcpu *vcpu)
2126{
2127 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2128 return;
2129
4e335d9e 2130 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2131 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2132 return;
2133
0b9f6c46
PX		 2134 vcpu->arch.st.steal.preempted = 0;
2135
35f3fae1
WL		 2136 if (vcpu->arch.st.steal.version & 1)
2137 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2138
2139 vcpu->arch.st.steal.version += 1;
2140
4e335d9e 2141 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2142 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2143
2144 smp_wmb();
2145
c54cdf14
LC		 2146 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2147 vcpu->arch.st.last_steal;
2148 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2149
4e335d9e 2150 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2151 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2152
2153 smp_wmb();
2154
2155 vcpu->arch.st.steal.version += 1;
c9aaa895 2156
4e335d9e 2157 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2158 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2159}
2160
8fe8ab46 2161int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2162{
5753785f 2163 bool pr = false;
8fe8ab46
WA		 2164 u32 msr = msr_info->index;
2165 u64 data = msr_info->data;
5753785f 2166
15c4a640 2167 switch (msr) {
2e32b719
BP		 2168 case MSR_AMD64_NB_CFG:
2169 case MSR_IA32_UCODE_REV:
2170 case MSR_IA32_UCODE_WRITE:
2171 case MSR_VM_HSAVE_PA:
2172 case MSR_AMD64_PATCH_LOADER:
2173 case MSR_AMD64_BU_CFG2:
405a353a 2174 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2175 break;
2176
15c4a640 2177 case MSR_EFER:
b69e8cae 2178 return set_efer(vcpu, data);
8f1589d9
AP		 2179 case MSR_K7_HWCR:
2180 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2181 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2182 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2183 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2184 if (data != 0) {
a737f256
CD		 2185 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2186 data);
8f1589d9
AP		 2187 return 1;
2188 }
15c4a640 2189 break;
f7c6d140
AP		 2190 case MSR_FAM10H_MMIO_CONF_BASE:
2191 if (data != 0) {
a737f256
CD		 2192 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2193 "0x%llx\n", data);
f7c6d140
AP		 2194 return 1;
2195 }
15c4a640 2196 break;
b5e2fec0
AG		 2197 case MSR_IA32_DEBUGCTLMSR:
2198 if (!data) {
2199 /* We support the non-activated case already */
2200 break;
2201 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2202 /* Values other than LBR and BTF are vendor-specific,
2203 thus reserved and should throw a #GP */
2204 return 1;
2205 }
a737f256
CD		 2206 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2207 __func__, data);
b5e2fec0 2208 break;
9ba075a6 2209 case 0x200 ... 0x2ff:
ff53604b 2210 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2211 case MSR_IA32_APICBASE:
58cb628d 2212 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2213 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2214 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2215 case MSR_IA32_TSCDEADLINE:
2216 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2217 break;
ba904635 2218 case MSR_IA32_TSC_ADJUST:
d6321d49 2219 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2220 if (!msr_info->host_initiated) {
d913b904 2221 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2222 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2223 }
2224 vcpu->arch.ia32_tsc_adjust_msr = data;
2225 }
2226 break;
15c4a640 2227 case MSR_IA32_MISC_ENABLE:
ad312c7c 2228 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2229 break;
64d60670
PB		 2230 case MSR_IA32_SMBASE:
2231 if (!msr_info->host_initiated)
2232 return 1;
2233 vcpu->arch.smbase = data;
2234 break;
11c6bffa 2235 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2236 case MSR_KVM_WALL_CLOCK:
2237 vcpu->kvm->arch.wall_clock = data;
2238 kvm_write_wall_clock(vcpu->kvm, data);
2239 break;
11c6bffa 2240 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2241 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2242 struct kvm_arch *ka = &vcpu->kvm->arch;
2243
12f9a48f 2244 kvmclock_reset(vcpu);
18068523 2245
54750f2c
MT		 2246 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2247 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2248
2249 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2250 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2251
2252 ka->boot_vcpu_runs_old_kvmclock = tmp;
2253 }
2254
18068523 2255 vcpu->arch.time = data;
0061d53d 2256 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2257
2258 /* we verify if the enable bit is set... */
2259 if (!(data & 1))
2260 break;
2261
4e335d9e 2262 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2263 &vcpu->arch.pv_time, data & ~1ULL,
2264 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2265 vcpu->arch.pv_time_enabled = false;
2266 else
2267 vcpu->arch.pv_time_enabled = true;
32cad84f 2268
18068523
GOC		 2269 break;
2270 }
344d9588
GN		 2271 case MSR_KVM_ASYNC_PF_EN:
2272 if (kvm_pv_enable_async_pf(vcpu, data))
2273 return 1;
2274 break;
c9aaa895
GC		 2275 case MSR_KVM_STEAL_TIME:
2276
2277 if (unlikely(!sched_info_on()))
2278 return 1;
2279
2280 if (data & KVM_STEAL_RESERVED_MASK)
2281 return 1;
2282
4e335d9e 2283 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2284 data & KVM_STEAL_VALID_BITS,
2285 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2286 return 1;
2287
2288 vcpu->arch.st.msr_val = data;
2289
2290 if (!(data & KVM_MSR_ENABLED))
2291 break;
2292
c9aaa895
GC		 2293 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2294
2295 break;
ae7a2a3f
MT		 2296 case MSR_KVM_PV_EOI_EN:
2297 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2298 return 1;
2299 break;
c9aaa895 2300
890ca9ae
HY		 2301 case MSR_IA32_MCG_CTL:
2302 case MSR_IA32_MCG_STATUS:
81760dcc 2303 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2304 return set_msr_mce(vcpu, msr_info);
71db6023 2305
6912ac32
WH		 2306 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2307 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2308 pr = true; /* fall through */
2309 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2310 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2311 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2312 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2313
2314 if (pr || data != 0)
a737f256
CD		 2315 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2316 "0x%x data 0x%llx\n", msr, data);
5753785f 2317 break;
84e0cefa
JS		 2318 case MSR_K7_CLK_CTL:
2319 /*
2320 * Ignore all writes to this no longer documented MSR.
2321 * Writes are only relevant for old K7 processors,
2322 * all pre-dating SVM, but a recommended workaround from
4a969980 2323 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2324 * affected processor models on the command line, hence
2325 * the need to ignore the workaround.
2326 */
2327 break;
55cd8e5a 2328 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2329 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2330 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2331 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2332 return kvm_hv_set_msr_common(vcpu, msr, data,
2333 msr_info->host_initiated);
91c9c3ed 2334 case MSR_IA32_BBL_CR_CTL3:
2335 /* Drop writes to this legacy MSR -- see rdmsr
2336 * counterpart for further detail.
2337 */
fab0aa3b
EM		 2338 if (report_ignored_msrs)
2339 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2340 msr, data);
91c9c3ed 2341 break;
2b036c6b 2342 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2343 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2344 return 1;
2345 vcpu->arch.osvw.length = data;
2346 break;
2347 case MSR_AMD64_OSVW_STATUS:
d6321d49 2348 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2349 return 1;
2350 vcpu->arch.osvw.status = data;
2351 break;
db2336a8
KH		 2352 case MSR_PLATFORM_INFO:
2353 if (!msr_info->host_initiated ||
2354 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2355 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2356 cpuid_fault_enabled(vcpu)))
2357 return 1;
2358 vcpu->arch.msr_platform_info = data;
2359 break;
2360 case MSR_MISC_FEATURES_ENABLES:
2361 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2362 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2363 !supports_cpuid_fault(vcpu)))
2364 return 1;
2365 vcpu->arch.msr_misc_features_enables = data;
2366 break;
15c4a640 2367 default:
ffde22ac
ES		 2368 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2369 return xen_hvm_config(vcpu, data);
c6702c9d 2370 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2371 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2372 if (!ignore_msrs) {
ae0f5499 2373 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2374 msr, data);
ed85c068
AP		 2375 return 1;
2376 } else {
fab0aa3b
EM		 2377 if (report_ignored_msrs)
2378 vcpu_unimpl(vcpu,
2379 "ignored wrmsr: 0x%x data 0x%llx\n",
2380 msr, data);
ed85c068
AP		 2381 break;
2382 }
15c4a640
CO		 2383 }
2384 return 0;
2385}
2386EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2387
2388
2389/*
2390 * Reads an msr value (of 'msr_index') into 'pdata'.
2391 * Returns 0 on success, non-0 otherwise.
2392 * Assumes vcpu_load() was already called.
2393 */
609e36d3 2394int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2395{
609e36d3 2396 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2397}
ff651cb6 2398EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2399
890ca9ae 2400static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2401{
2402 u64 data;
890ca9ae
HY		 2403 u64 mcg_cap = vcpu->arch.mcg_cap;
2404 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2405
2406 switch (msr) {
15c4a640
CO		 2407 case MSR_IA32_P5_MC_ADDR:
2408 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2409 data = 0;
2410 break;
15c4a640 2411 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2412 data = vcpu->arch.mcg_cap;
2413 break;
c7ac679c 2414 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2415 if (!(mcg_cap & MCG_CTL_P))
2416 return 1;
2417 data = vcpu->arch.mcg_ctl;
2418 break;
2419 case MSR_IA32_MCG_STATUS:
2420 data = vcpu->arch.mcg_status;
2421 break;
2422 default:
2423 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2424 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2425 u32 offset = msr - MSR_IA32_MC0_CTL;
2426 data = vcpu->arch.mce_banks[offset];
2427 break;
2428 }
2429 return 1;
2430 }
2431 *pdata = data;
2432 return 0;
2433}
2434
609e36d3 2435int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2436{
609e36d3 2437 switch (msr_info->index) {
890ca9ae 2438 case MSR_IA32_PLATFORM_ID:
15c4a640 2439 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2440 case MSR_IA32_DEBUGCTLMSR:
2441 case MSR_IA32_LASTBRANCHFROMIP:
2442 case MSR_IA32_LASTBRANCHTOIP:
2443 case MSR_IA32_LASTINTFROMIP:
2444 case MSR_IA32_LASTINTTOIP:
60af2ecd 2445 case MSR_K8_SYSCFG:
3afb1121
PB		 2446 case MSR_K8_TSEG_ADDR:
2447 case MSR_K8_TSEG_MASK:
60af2ecd 2448 case MSR_K7_HWCR:
61a6bd67 2449 case MSR_VM_HSAVE_PA:
1fdbd48c 2450 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2451 case MSR_AMD64_NB_CFG:
f7c6d140 2452 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2453 case MSR_AMD64_BU_CFG2:
0c2df2a1 2454 case MSR_IA32_PERF_CTL:
405a353a 2455 case MSR_AMD64_DC_CFG:
609e36d3 2456 msr_info->data = 0;
15c4a640 2457 break;
6912ac32
WH		 2458 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2459 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2460 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2461 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2462 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2463 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2464 msr_info->data = 0;
5753785f 2465 break;
742bc670 2466 case MSR_IA32_UCODE_REV:
609e36d3 2467 msr_info->data = 0x100000000ULL;
742bc670 2468 break;
9ba075a6 2469 case MSR_MTRRcap:
9ba075a6 2470 case 0x200 ... 0x2ff:
ff53604b 2471 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2472 case 0xcd: /* fsb frequency */
609e36d3 2473 msr_info->data = 3;
15c4a640 2474 break;
7b914098
JS		 2475 /*
2476 * MSR_EBC_FREQUENCY_ID
2477 * Conservative value valid for even the basic CPU models.
2478 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2479 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2480 * and 266MHz for model 3, or 4. Set Core Clock
2481 * Frequency to System Bus Frequency Ratio to 1 (bits
2482 * 31:24) even though these are only valid for CPU
2483 * models > 2, however guests may end up dividing or
2484 * multiplying by zero otherwise.
2485 */
2486 case MSR_EBC_FREQUENCY_ID:
609e36d3 2487 msr_info->data = 1 << 24;
7b914098 2488 break;
15c4a640 2489 case MSR_IA32_APICBASE:
609e36d3 2490 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2491 break;
0105d1a5 2492 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2493 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2494 break;
a3e06bbe 2495 case MSR_IA32_TSCDEADLINE:
609e36d3 2496 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2497 break;
ba904635 2498 case MSR_IA32_TSC_ADJUST:
609e36d3 2499 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2500 break;
15c4a640 2501 case MSR_IA32_MISC_ENABLE:
609e36d3 2502 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2503 break;
64d60670
PB		 2504 case MSR_IA32_SMBASE:
2505 if (!msr_info->host_initiated)
2506 return 1;
2507 msr_info->data = vcpu->arch.smbase;
15c4a640 2508 break;
847f0ad8
AG		 2509 case MSR_IA32_PERF_STATUS:
2510 /* TSC increment by tick */
609e36d3 2511 msr_info->data = 1000ULL;
847f0ad8 2512 /* CPU multiplier */
b0996ae4 2513 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2514 break;
15c4a640 2515 case MSR_EFER:
609e36d3 2516 msr_info->data = vcpu->arch.efer;
15c4a640 2517 break;
18068523 2518 case MSR_KVM_WALL_CLOCK:
11c6bffa 2519 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2520 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2521 break;
2522 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2523 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2524 msr_info->data = vcpu->arch.time;
18068523 2525 break;
344d9588 2526 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2527 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2528 break;
c9aaa895 2529 case MSR_KVM_STEAL_TIME:
609e36d3 2530 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2531 break;
1d92128f 2532 case MSR_KVM_PV_EOI_EN:
609e36d3 2533 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2534 break;
890ca9ae
HY		 2535 case MSR_IA32_P5_MC_ADDR:
2536 case MSR_IA32_P5_MC_TYPE:
2537 case MSR_IA32_MCG_CAP:
2538 case MSR_IA32_MCG_CTL:
2539 case MSR_IA32_MCG_STATUS:
81760dcc 2540 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2541 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2542 case MSR_K7_CLK_CTL:
2543 /*
2544 * Provide expected ramp-up count for K7. All other
2545 * are set to zero, indicating minimum divisors for
2546 * every field.
2547 *
2548 * This prevents guest kernels on AMD host with CPU
2549 * type 6, model 8 and higher from exploding due to
2550 * the rdmsr failing.
2551 */
609e36d3 2552 msr_info->data = 0x20000000;
84e0cefa 2553 break;
55cd8e5a 2554 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2555 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2556 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2557 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2558 return kvm_hv_get_msr_common(vcpu,
2559 msr_info->index, &msr_info->data);
55cd8e5a 2560 break;
91c9c3ed 2561 case MSR_IA32_BBL_CR_CTL3:
2562 /* This legacy MSR exists but isn't fully documented in current
2563 * silicon. It is however accessed by winxp in very narrow
2564 * scenarios where it sets bit #19, itself documented as
2565 * a "reserved" bit. Best effort attempt to source coherent
2566 * read data here should the balance of the register be
2567 * interpreted by the guest:
2568 *
2569 * L2 cache control register 3: 64GB range, 256KB size,
2570 * enabled, latency 0x1, configured
2571 */
609e36d3 2572 msr_info->data = 0xbe702111;
91c9c3ed 2573 break;
2b036c6b 2574 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2575 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2576 return 1;
609e36d3 2577 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2578 break;
2579 case MSR_AMD64_OSVW_STATUS:
d6321d49 2580 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2581 return 1;
609e36d3 2582 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2583 break;
db2336a8
KH		 2584 case MSR_PLATFORM_INFO:
2585 msr_info->data = vcpu->arch.msr_platform_info;
2586 break;
2587 case MSR_MISC_FEATURES_ENABLES:
2588 msr_info->data = vcpu->arch.msr_misc_features_enables;
2589 break;
15c4a640 2590 default:
c6702c9d 2591 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2592 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2593 if (!ignore_msrs) {
ae0f5499
BD		 2594 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2595 msr_info->index);
ed85c068
AP		 2596 return 1;
2597 } else {
fab0aa3b
EM		 2598 if (report_ignored_msrs)
2599 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2600 msr_info->index);
609e36d3 2601 msr_info->data = 0;
ed85c068
AP		 2602 }
2603 break;
15c4a640 2604 }
15c4a640
CO		 2605 return 0;
2606}
2607EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2608
313a3dc7
CO		 2609/*
2610 * Read or write a bunch of msrs. All parameters are kernel addresses.
2611 *
2612 * @return number of msrs set successfully.
2613 */
2614static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2615 struct kvm_msr_entry *entries,
2616 int (*do_msr)(struct kvm_vcpu *vcpu,
2617 unsigned index, u64 *data))
2618{
f656ce01 2619 int i, idx;
313a3dc7 2620
f656ce01 2621 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2622 for (i = 0; i < msrs->nmsrs; ++i)
2623 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2624 break;
f656ce01 2625 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2626
313a3dc7
CO		 2627 return i;
2628}
2629
2630/*
2631 * Read or write a bunch of msrs. Parameters are user addresses.
2632 *
2633 * @return number of msrs set successfully.
2634 */
2635static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2636 int (*do_msr)(struct kvm_vcpu *vcpu,
2637 unsigned index, u64 *data),
2638 int writeback)
2639{
2640 struct kvm_msrs msrs;
2641 struct kvm_msr_entry *entries;
2642 int r, n;
2643 unsigned size;
2644
2645 r = -EFAULT;
2646 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2647 goto out;
2648
2649 r = -E2BIG;
2650 if (msrs.nmsrs >= MAX_IO_MSRS)
2651 goto out;
2652
313a3dc7 2653 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2654 entries = memdup_user(user_msrs->entries, size);
2655 if (IS_ERR(entries)) {
2656 r = PTR_ERR(entries);
313a3dc7 2657 goto out;
ff5c2c03 2658 }
313a3dc7
CO		 2659
2660 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2661 if (r < 0)
2662 goto out_free;
2663
2664 r = -EFAULT;
2665 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2666 goto out_free;
2667
2668 r = n;
2669
2670out_free:
7a73c028 2671 kfree(entries);
313a3dc7
CO		 2672out:
2673 return r;
2674}
2675
784aa3d7 2676int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2677{
2678 int r;
2679
2680 switch (ext) {
2681 case KVM_CAP_IRQCHIP:
2682 case KVM_CAP_HLT:
2683 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2684 case KVM_CAP_SET_TSS_ADDR:
07716717 2685 case KVM_CAP_EXT_CPUID:
9c15bb1d 2686 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2687 case KVM_CAP_CLOCKSOURCE:
7837699f 2688 case KVM_CAP_PIT:
a28e4f5a 2689 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2690 case KVM_CAP_MP_STATE:
ed848624 2691 case KVM_CAP_SYNC_MMU:
a355c85c 2692 case KVM_CAP_USER_NMI:
52d939a0 2693 case KVM_CAP_REINJECT_CONTROL:
4925663a 2694 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2695 case KVM_CAP_IOEVENTFD:
f848a5a8 2696 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2697 case KVM_CAP_PIT2:
e9f42757 2698 case KVM_CAP_PIT_STATE2:
b927a3ce 2699 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2700 case KVM_CAP_XEN_HVM:
3cfc3092 2701 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2702 case KVM_CAP_HYPERV:
10388a07 2703 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2704 case KVM_CAP_HYPERV_SPIN:
5c919412 2705 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2706 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2707 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2708 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2709 case KVM_CAP_DEBUGREGS:
d2be1651 2710 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2711 case KVM_CAP_XSAVE:
344d9588 2712 case KVM_CAP_ASYNC_PF:
92a1f12d 2713 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2714 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2715 case KVM_CAP_READONLY_MEM:
5f66b620 2716 case KVM_CAP_HYPERV_TIME:
100943c5 2717 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2718 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2719 case KVM_CAP_ENABLE_CAP_VM:
2720 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2721 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2722 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2723 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2724 r = 1;
2725 break;
e3fd9a93
PB		 2726 case KVM_CAP_ADJUST_CLOCK:
2727 r = KVM_CLOCK_TSC_STABLE;
2728 break;
668fffa3
MT		 2729 case KVM_CAP_X86_GUEST_MWAIT:
2730 r = kvm_mwait_in_guest();
2731 break;
6d396b55
PB		 2732 case KVM_CAP_X86_SMM:
2733 /* SMBASE is usually relocated above 1M on modern chipsets,
2734 * and SMM handlers might indeed rely on 4G segment limits,
2735 * so do not report SMM to be available if real mode is
2736 * emulated via vm86 mode. Still, do not go to great lengths
2737 * to avoid userspace's usage of the feature, because it is a
2738 * fringe case that is not enabled except via specific settings
2739 * of the module parameters.
2740 */
2741 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2742 break;
774ead3a
AK		 2743 case KVM_CAP_VAPIC:
2744 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2745 break;
f725230a 2746 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2747 r = KVM_SOFT_MAX_VCPUS;
2748 break;
2749 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2750 r = KVM_MAX_VCPUS;
2751 break;
a988b910 2752 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2753 r = KVM_USER_MEM_SLOTS;
a988b910 2754 break;
a68a6a72
MT		 2755 case KVM_CAP_PV_MMU: /* obsolete */
2756 r = 0;
2f333bcb 2757 break;
890ca9ae
HY		 2758 case KVM_CAP_MCE:
2759 r = KVM_MAX_MCE_BANKS;
2760 break;
2d5b5a66 2761 case KVM_CAP_XCRS:
d366bf7e 2762 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2763 break;
92a1f12d
JR		 2764 case KVM_CAP_TSC_CONTROL:
2765 r = kvm_has_tsc_control;
2766 break;
37131313
RK		 2767 case KVM_CAP_X2APIC_API:
2768 r = KVM_X2APIC_API_VALID_FLAGS;
2769 break;
018d00d2
ZX		 2770 default:
2771 r = 0;
2772 break;
2773 }
2774 return r;
2775
2776}
2777
043405e1
CO		 2778long kvm_arch_dev_ioctl(struct file *filp,
2779 unsigned int ioctl, unsigned long arg)
2780{
2781 void __user *argp = (void __user *)arg;
2782 long r;
2783
2784 switch (ioctl) {
2785 case KVM_GET_MSR_INDEX_LIST: {
2786 struct kvm_msr_list __user *user_msr_list = argp;
2787 struct kvm_msr_list msr_list;
2788 unsigned n;
2789
2790 r = -EFAULT;
2791 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2792 goto out;
2793 n = msr_list.nmsrs;
62ef68bb 2794 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2795 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2796 goto out;
2797 r = -E2BIG;
e125e7b6 2798 if (n < msr_list.nmsrs)
043405e1
CO		 2799 goto out;
2800 r = -EFAULT;
2801 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2802 num_msrs_to_save * sizeof(u32)))
2803 goto out;
e125e7b6 2804 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2805 &emulated_msrs,
62ef68bb 2806 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2807 goto out;
2808 r = 0;
2809 break;
2810 }
9c15bb1d
BP		 2811 case KVM_GET_SUPPORTED_CPUID:
2812 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2813 struct kvm_cpuid2 __user *cpuid_arg = argp;
2814 struct kvm_cpuid2 cpuid;
2815
2816 r = -EFAULT;
2817 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2818 goto out;
9c15bb1d
BP		 2819
2820 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2821 ioctl);
674eea0f
AK		 2822 if (r)
2823 goto out;
2824
2825 r = -EFAULT;
2826 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2827 goto out;
2828 r = 0;
2829 break;
2830 }
890ca9ae 2831 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2832 r = -EFAULT;
c45dcc71
AR		 2833 if (copy_to_user(argp, &kvm_mce_cap_supported,
2834 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2835 goto out;
2836 r = 0;
2837 break;
2838 }
043405e1
CO		 2839 default:
2840 r = -EINVAL;
2841 }
2842out:
2843 return r;
2844}
2845
f5f48ee1
SY		 2846static void wbinvd_ipi(void *garbage)
2847{
2848 wbinvd();
2849}
2850
2851static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2852{
e0f0bbc5 2853 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2854}
2855
313a3dc7
CO		 2856void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2857{
f5f48ee1
SY		 2858 /* Address WBINVD may be executed by guest */
2859 if (need_emulate_wbinvd(vcpu)) {
2860 if (kvm_x86_ops->has_wbinvd_exit())
2861 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2862 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2863 smp_call_function_single(vcpu->cpu,
2864 wbinvd_ipi, NULL, 1);
2865 }
2866
313a3dc7 2867 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2868
0dd6a6ed
ZA		 2869 /* Apply any externally detected TSC adjustments (due to suspend) */
2870 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2871 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2872 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2873 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2874 }
8f6055cb 2875
48434c20 2876 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2877 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2878 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2879 if (tsc_delta < 0)
2880 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2881
c285545f 2882 if (check_tsc_unstable()) {
07c1419a 2883 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2884 vcpu->arch.last_guest_tsc);
a545ab6a 2885 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2886 vcpu->arch.tsc_catchup = 1;
c285545f 2887 }
a749e247
PB		 2888
2889 if (kvm_lapic_hv_timer_in_use(vcpu))
2890 kvm_lapic_restart_hv_timer(vcpu);
2891
d98d07ca
MT		 2892 /*
2893 * On a host with synchronized TSC, there is no need to update
2894 * kvmclock on vcpu->cpu migration
2895 */
2896 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2897 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2898 if (vcpu->cpu != cpu)
1bd2009e 2899 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2900 vcpu->cpu = cpu;
6b7d7e76 2901 }
c9aaa895 2902
c9aaa895 2903 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2904}
2905
0b9f6c46
PX		 2906static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2907{
2908 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2909 return;
2910
2911 vcpu->arch.st.steal.preempted = 1;
2912
4e335d9e 2913 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2914 &vcpu->arch.st.steal.preempted,
2915 offsetof(struct kvm_steal_time, preempted),
2916 sizeof(vcpu->arch.st.steal.preempted));
2917}
2918
313a3dc7
CO		 2919void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2920{
cc0d907c 2921 int idx;
de63ad4c
LM		 2922
2923 if (vcpu->preempted)
2924 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2925
931f261b
AA		 2926 /*
2927 * Disable page faults because we're in atomic context here.
2928 * kvm_write_guest_offset_cached() would call might_fault()
2929 * that relies on pagefault_disable() to tell if there's a
2930 * bug. NOTE: the write to guest memory may not go through if
2931 * during postcopy live migration or if there's heavy guest
2932 * paging.
2933 */
2934 pagefault_disable();
cc0d907c
AA		 2935 /*
2936 * kvm_memslots() will be called by
2937 * kvm_write_guest_offset_cached() so take the srcu lock.
2938 */
2939 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2940 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2941 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2942 pagefault_enable();
02daab21 2943 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 2944 vcpu->arch.last_host_tsc = rdtsc();
7046f30e
WL		 2945 /*
2946 * If userspace has set any breakpoints or watchpoints, dr6 is restored
2947 * on every vmexit, but if not, we might have a stale dr6 from the
2948 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
2949 */
2950 set_debugreg(0, 6);
313a3dc7
CO		 2951}
2952
313a3dc7
CO		 2953static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2954 struct kvm_lapic_state *s)
2955{
76dfafd5 2956 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2957 kvm_x86_ops->sync_pir_to_irr(vcpu);
2958
a92e2543 2959 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2960}
2961
2962static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2963 struct kvm_lapic_state *s)
2964{
a92e2543
RK		 2965 int r;
2966
2967 r = kvm_apic_set_state(vcpu, s);
2968 if (r)
2969 return r;
cb142eb7 2970 update_cr8_intercept(vcpu);
313a3dc7
CO		 2971
2972 return 0;
2973}
2974
127a457a
MG		 2975static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2976{
2977 return (!lapic_in_kernel(vcpu) ||
2978 kvm_apic_accept_pic_intr(vcpu));
2979}
2980
782d422b
MG		 2981/*
2982 * if userspace requested an interrupt window, check that the
2983 * interrupt window is open.
2984 *
2985 * No need to exit to userspace if we already have an interrupt queued.
2986 */
2987static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2988{
2989 return kvm_arch_interrupt_allowed(vcpu) &&
2990 !kvm_cpu_has_interrupt(vcpu) &&
2991 !kvm_event_needs_reinjection(vcpu) &&
2992 kvm_cpu_accept_dm_intr(vcpu);
2993}
2994
f77bc6a4
ZX		 2995static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2996 struct kvm_interrupt *irq)
2997{
02cdb50f 2998 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2999 return -EINVAL;
1c1a9ce9
SR		 3000
3001 if (!irqchip_in_kernel(vcpu->kvm)) {
3002 kvm_queue_interrupt(vcpu, irq->irq, false);
3003 kvm_make_request(KVM_REQ_EVENT, vcpu);
3004 return 0;
3005 }
3006
3007 /*
3008 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3009 * fail for in-kernel 8259.
3010 */
3011 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3012 return -ENXIO;
f77bc6a4 3013
1c1a9ce9
SR		 3014 if (vcpu->arch.pending_external_vector != -1)
3015 return -EEXIST;
f77bc6a4 3016
1c1a9ce9 3017 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3018 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3019 return 0;
3020}
3021
c4abb7c9
JK		 3022static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3023{
c4abb7c9 3024 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3025
3026 return 0;
3027}
3028
f077825a
PB		 3029static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3030{
64d60670
PB		 3031 kvm_make_request(KVM_REQ_SMI, vcpu);
3032
f077825a
PB		 3033 return 0;
3034}
3035
b209749f
AK		 3036static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3037 struct kvm_tpr_access_ctl *tac)
3038{
3039 if (tac->flags)
3040 return -EINVAL;
3041 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3042 return 0;
3043}
3044
890ca9ae
HY		 3045static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3046 u64 mcg_cap)
3047{
3048 int r;
3049 unsigned bank_num = mcg_cap & 0xff, bank;
3050
3051 r = -EINVAL;
a9e38c3e 3052 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3053 goto out;
c45dcc71 3054 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3055 goto out;
3056 r = 0;
3057 vcpu->arch.mcg_cap = mcg_cap;
3058 /* Init IA32_MCG_CTL to all 1s */
3059 if (mcg_cap & MCG_CTL_P)
3060 vcpu->arch.mcg_ctl = ~(u64)0;
3061 /* Init IA32_MCi_CTL to all 1s */
3062 for (bank = 0; bank < bank_num; bank++)
3063 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3064
3065 if (kvm_x86_ops->setup_mce)
3066 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3067out:
3068 return r;
3069}
3070
3071static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3072 struct kvm_x86_mce *mce)
3073{
3074 u64 mcg_cap = vcpu->arch.mcg_cap;
3075 unsigned bank_num = mcg_cap & 0xff;
3076 u64 *banks = vcpu->arch.mce_banks;
3077
3078 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3079 return -EINVAL;
3080 /*
3081 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3082 * reporting is disabled
3083 */
3084 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3085 vcpu->arch.mcg_ctl != ~(u64)0)
3086 return 0;
3087 banks += 4 * mce->bank;
3088 /*
3089 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3090 * reporting is disabled for the bank
3091 */
3092 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3093 return 0;
3094 if (mce->status & MCI_STATUS_UC) {
3095 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3096 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3097 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3098 return 0;
3099 }
3100 if (banks[1] & MCI_STATUS_VAL)
3101 mce->status |= MCI_STATUS_OVER;
3102 banks[2] = mce->addr;
3103 banks[3] = mce->misc;
3104 vcpu->arch.mcg_status = mce->mcg_status;
3105 banks[1] = mce->status;
3106 kvm_queue_exception(vcpu, MC_VECTOR);
3107 } else if (!(banks[1] & MCI_STATUS_VAL)
3108 || !(banks[1] & MCI_STATUS_UC)) {
3109 if (banks[1] & MCI_STATUS_VAL)
3110 mce->status |= MCI_STATUS_OVER;
3111 banks[2] = mce->addr;
3112 banks[3] = mce->misc;
3113 banks[1] = mce->status;
3114 } else
3115 banks[1] |= MCI_STATUS_OVER;
3116 return 0;
3117}
3118
3cfc3092
JK		 3119static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3120 struct kvm_vcpu_events *events)
3121{
7460fb4a 3122 process_nmi(vcpu);
664f8e26
WL		 3123 /*
3124 * FIXME: pass injected and pending separately. This is only
3125 * needed for nested virtualization, whose state cannot be
3126 * migrated yet. For now we can combine them.
3127 */
03b82a30 3128 events->exception.injected =
664f8e26
WL		 3129 (vcpu->arch.exception.pending ||
3130 vcpu->arch.exception.injected) &&
03b82a30 3131 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3132 events->exception.nr = vcpu->arch.exception.nr;
3133 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3134 events->exception.pad = 0;
3cfc3092
JK		 3135 events->exception.error_code = vcpu->arch.exception.error_code;
3136
03b82a30
JK		 3137 events->interrupt.injected =
3138 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3139 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3140 events->interrupt.soft = 0;
37ccdcbe 3141 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3142
3143 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3144 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3145 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3146 events->nmi.pad = 0;
3cfc3092 3147
66450a21 3148 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3149
f077825a
PB		 3150 events->smi.smm = is_smm(vcpu);
3151 events->smi.pending = vcpu->arch.smi_pending;
3152 events->smi.smm_inside_nmi =
3153 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3154 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3155
dab4b911 3156 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3157 | KVM_VCPUEVENT_VALID_SHADOW
3158 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3159 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3160}
3161
6ef4e07e
XG		 3162static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3163
3cfc3092
JK		 3164static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3165 struct kvm_vcpu_events *events)
3166{
dab4b911 3167 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3168 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3169 | KVM_VCPUEVENT_VALID_SHADOW
3170 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3171 return -EINVAL;
3172
78e546c8 3173 if (events->exception.injected &&
28d06353
JM		 3174 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3175 is_guest_mode(vcpu)))
78e546c8
PB		 3176 return -EINVAL;
3177
28bf2888
DH		 3178 /* INITs are latched while in SMM */
3179 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3180 (events->smi.smm || events->smi.pending) &&
3181 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3182 return -EINVAL;
3183
7460fb4a 3184 process_nmi(vcpu);
664f8e26 3185 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3186 vcpu->arch.exception.pending = events->exception.injected;
3187 vcpu->arch.exception.nr = events->exception.nr;
3188 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3189 vcpu->arch.exception.error_code = events->exception.error_code;
3190
3191 vcpu->arch.interrupt.pending = events->interrupt.injected;
3192 vcpu->arch.interrupt.nr = events->interrupt.nr;
3193 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3194 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3195 kvm_x86_ops->set_interrupt_shadow(vcpu,
3196 events->interrupt.shadow);
3cfc3092
JK		 3197
3198 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3199 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3200 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3201 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3202
66450a21 3203 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3204 lapic_in_kernel(vcpu))
66450a21 3205 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3206
f077825a 3207 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3208 u32 hflags = vcpu->arch.hflags;
f077825a 3209 if (events->smi.smm)
6ef4e07e 3210 hflags |= HF_SMM_MASK;
f077825a 3211 else
6ef4e07e
XG		 3212 hflags &= ~HF_SMM_MASK;
3213 kvm_set_hflags(vcpu, hflags);
3214
f077825a 3215 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3216
3217 if (events->smi.smm) {
3218 if (events->smi.smm_inside_nmi)
3219 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3220 else
f4ef1910
WL		 3221 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3222 if (lapic_in_kernel(vcpu)) {
3223 if (events->smi.latched_init)
3224 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3225 else
3226 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3227 }
f077825a
PB		 3228 }
3229 }
3230
3842d135
AK		 3231 kvm_make_request(KVM_REQ_EVENT, vcpu);
3232
3cfc3092
JK		 3233 return 0;
3234}
3235
a1efbe77
JK		 3236static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3237 struct kvm_debugregs *dbgregs)
3238{
73aaf249
JK		 3239 unsigned long val;
3240
a1efbe77 3241 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3242 kvm_get_dr(vcpu, 6, &val);
73aaf249 3243 dbgregs->dr6 = val;
a1efbe77
JK		 3244 dbgregs->dr7 = vcpu->arch.dr7;
3245 dbgregs->flags = 0;
97e69aa6 3246 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3247}
3248
3249static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3250 struct kvm_debugregs *dbgregs)
3251{
3252 if (dbgregs->flags)
3253 return -EINVAL;
3254
d14bdb55
PB		 3255 if (dbgregs->dr6 & ~0xffffffffull)
3256 return -EINVAL;
3257 if (dbgregs->dr7 & ~0xffffffffull)
3258 return -EINVAL;
3259
a1efbe77 3260 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3261 kvm_update_dr0123(vcpu);
a1efbe77 3262 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3263 kvm_update_dr6(vcpu);
a1efbe77 3264 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3265 kvm_update_dr7(vcpu);
a1efbe77 3266
a1efbe77
JK		 3267 return 0;
3268}
3269
df1daba7
PB		 3270#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3271
3272static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3273{
c47ada30 3274 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3275 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3276 u64 valid;
3277
3278 /*
3279 * Copy legacy XSAVE area, to avoid complications with CPUID
3280 * leaves 0 and 1 in the loop below.
3281 */
3282 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3283
3284 /* Set XSTATE_BV */
00c87e9a 3285 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3286 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3287
3288 /*
3289 * Copy each region from the possibly compacted offset to the
3290 * non-compacted offset.
3291 */
d91cab78 3292 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3293 while (valid) {
3294 u64 feature = valid & -valid;
3295 int index = fls64(feature) - 1;
3296 void *src = get_xsave_addr(xsave, feature);
3297
3298 if (src) {
3299 u32 size, offset, ecx, edx;
3300 cpuid_count(XSTATE_CPUID, index,
3301 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3302 if (feature == XFEATURE_MASK_PKRU)
3303 memcpy(dest + offset, &vcpu->arch.pkru,
3304 sizeof(vcpu->arch.pkru));
3305 else
3306 memcpy(dest + offset, src, size);
3307
df1daba7
PB		 3308 }
3309
3310 valid -= feature;
3311 }
3312}
3313
3314static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3315{
c47ada30 3316 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3317 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3318 u64 valid;
3319
3320 /*
3321 * Copy legacy XSAVE area, to avoid complications with CPUID
3322 * leaves 0 and 1 in the loop below.
3323 */
3324 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3325
3326 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3327 xsave->header.xfeatures = xstate_bv;
782511b0 3328 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3329 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3330
3331 /*
3332 * Copy each region from the non-compacted offset to the
3333 * possibly compacted offset.
3334 */
d91cab78 3335 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3336 while (valid) {
3337 u64 feature = valid & -valid;
3338 int index = fls64(feature) - 1;
3339 void *dest = get_xsave_addr(xsave, feature);
3340
3341 if (dest) {
3342 u32 size, offset, ecx, edx;
3343 cpuid_count(XSTATE_CPUID, index,
3344 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3345 if (feature == XFEATURE_MASK_PKRU)
3346 memcpy(&vcpu->arch.pkru, src + offset,
3347 sizeof(vcpu->arch.pkru));
3348 else
3349 memcpy(dest, src + offset, size);
ee4100da 3350 }
df1daba7
PB		 3351
3352 valid -= feature;
3353 }
3354}
3355
2d5b5a66
SY		 3356static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3357 struct kvm_xsave *guest_xsave)
3358{
d366bf7e 3359 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3360 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3361 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3362 } else {
2d5b5a66 3363 memcpy(guest_xsave->region,
7366ed77 3364 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3365 sizeof(struct fxregs_state));
2d5b5a66 3366 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3367 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3368 }
3369}
3370
a575813b
WL		 3371#define XSAVE_MXCSR_OFFSET 24
3372
2d5b5a66
SY		 3373static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3374 struct kvm_xsave *guest_xsave)
3375{
3376 u64 xstate_bv =
3377 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3378 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3379
d366bf7e 3380 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3381 /*
3382 * Here we allow setting states that are not present in
3383 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3384 * with old userspace.
3385 */
a575813b
WL		 3386 if (xstate_bv & ~kvm_supported_xcr0() ||
3387 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3388 return -EINVAL;
df1daba7 3389 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3390 } else {
a575813b
WL		 3391 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3392 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3393 return -EINVAL;
7366ed77 3394 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3395 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3396 }
3397 return 0;
3398}
3399
3400static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3401 struct kvm_xcrs *guest_xcrs)
3402{
d366bf7e 3403 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3404 guest_xcrs->nr_xcrs = 0;
3405 return;
3406 }
3407
3408 guest_xcrs->nr_xcrs = 1;
3409 guest_xcrs->flags = 0;
3410 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3411 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3412}
3413
3414static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3415 struct kvm_xcrs *guest_xcrs)
3416{
3417 int i, r = 0;
3418
d366bf7e 3419 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3420 return -EINVAL;
3421
3422 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3423 return -EINVAL;
3424
3425 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3426 /* Only support XCR0 currently */
c67a04cb 3427 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3428 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3429 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3430 break;
3431 }
3432 if (r)
3433 r = -EINVAL;
3434 return r;
3435}
3436
1c0b28c2
EM		 3437/*
3438 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3439 * stopped by the hypervisor. This function will be called from the host only.
3440 * EINVAL is returned when the host attempts to set the flag for a guest that
3441 * does not support pv clocks.
3442 */
3443static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3444{
0b79459b 3445 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3446 return -EINVAL;
51d59c6b 3447 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3448 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3449 return 0;
3450}
3451
5c919412
AS		 3452static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3453 struct kvm_enable_cap *cap)
3454{
3455 if (cap->flags)
3456 return -EINVAL;
3457
3458 switch (cap->cap) {
efc479e6
RK		 3459 case KVM_CAP_HYPERV_SYNIC2:
3460 if (cap->args[0])
3461 return -EINVAL;
5c919412 3462 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3463 if (!irqchip_in_kernel(vcpu->kvm))
3464 return -EINVAL;
efc479e6
RK		 3465 return kvm_hv_activate_synic(vcpu, cap->cap ==
3466 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3467 default:
3468 return -EINVAL;
3469 }
3470}
3471
313a3dc7
CO		 3472long kvm_arch_vcpu_ioctl(struct file *filp,
3473 unsigned int ioctl, unsigned long arg)
3474{
3475 struct kvm_vcpu *vcpu = filp->private_data;
3476 void __user *argp = (void __user *)arg;
3477 int r;
d1ac91d8
AK		 3478 union {
3479 struct kvm_lapic_state *lapic;
3480 struct kvm_xsave *xsave;
3481 struct kvm_xcrs *xcrs;
3482 void *buffer;
3483 } u;
3484
3485 u.buffer = NULL;
313a3dc7
CO		 3486 switch (ioctl) {
3487 case KVM_GET_LAPIC: {
2204ae3c 3488 r = -EINVAL;
bce87cce 3489 if (!lapic_in_kernel(vcpu))
2204ae3c 3490 goto out;
d1ac91d8 3491 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3492
b772ff36 3493 r = -ENOMEM;
d1ac91d8 3494 if (!u.lapic)
b772ff36 3495 goto out;
d1ac91d8 3496 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3497 if (r)
3498 goto out;
3499 r = -EFAULT;
d1ac91d8 3500 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3501 goto out;
3502 r = 0;
3503 break;
3504 }
3505 case KVM_SET_LAPIC: {
2204ae3c 3506 r = -EINVAL;
bce87cce 3507 if (!lapic_in_kernel(vcpu))
2204ae3c 3508 goto out;
ff5c2c03 3509 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3510 if (IS_ERR(u.lapic))
3511 return PTR_ERR(u.lapic);
ff5c2c03 3512
d1ac91d8 3513 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3514 break;
3515 }
f77bc6a4
ZX		 3516 case KVM_INTERRUPT: {
3517 struct kvm_interrupt irq;
3518
3519 r = -EFAULT;
3520 if (copy_from_user(&irq, argp, sizeof irq))
3521 goto out;
3522 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3523 break;
3524 }
c4abb7c9
JK		 3525 case KVM_NMI: {
3526 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3527 break;
3528 }
f077825a
PB		 3529 case KVM_SMI: {
3530 r = kvm_vcpu_ioctl_smi(vcpu);
3531 break;
3532 }
313a3dc7
CO		 3533 case KVM_SET_CPUID: {
3534 struct kvm_cpuid __user *cpuid_arg = argp;
3535 struct kvm_cpuid cpuid;
3536
3537 r = -EFAULT;
3538 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3539 goto out;
3540 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3541 break;
3542 }
07716717
DK		 3543 case KVM_SET_CPUID2: {
3544 struct kvm_cpuid2 __user *cpuid_arg = argp;
3545 struct kvm_cpuid2 cpuid;
3546
3547 r = -EFAULT;
3548 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3549 goto out;
3550 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3551 cpuid_arg->entries);
07716717
DK		 3552 break;
3553 }
3554 case KVM_GET_CPUID2: {
3555 struct kvm_cpuid2 __user *cpuid_arg = argp;
3556 struct kvm_cpuid2 cpuid;
3557
3558 r = -EFAULT;
3559 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3560 goto out;
3561 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3562 cpuid_arg->entries);
07716717
DK		 3563 if (r)
3564 goto out;
3565 r = -EFAULT;
3566 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3567 goto out;
3568 r = 0;
3569 break;
3570 }
313a3dc7 3571 case KVM_GET_MSRS:
609e36d3 3572 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3573 break;
3574 case KVM_SET_MSRS:
3575 r = msr_io(vcpu, argp, do_set_msr, 0);
3576 break;
b209749f
AK		 3577 case KVM_TPR_ACCESS_REPORTING: {
3578 struct kvm_tpr_access_ctl tac;
3579
3580 r = -EFAULT;
3581 if (copy_from_user(&tac, argp, sizeof tac))
3582 goto out;
3583 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3584 if (r)
3585 goto out;
3586 r = -EFAULT;
3587 if (copy_to_user(argp, &tac, sizeof tac))
3588 goto out;
3589 r = 0;
3590 break;
3591 };
b93463aa
AK		 3592 case KVM_SET_VAPIC_ADDR: {
3593 struct kvm_vapic_addr va;
7301d6ab 3594 int idx;
b93463aa
AK		 3595
3596 r = -EINVAL;
35754c98 3597 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3598 goto out;
3599 r = -EFAULT;
3600 if (copy_from_user(&va, argp, sizeof va))
3601 goto out;
7301d6ab 3602 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3603 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3604 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3605 break;
3606 }
890ca9ae
HY		 3607 case KVM_X86_SETUP_MCE: {
3608 u64 mcg_cap;
3609
3610 r = -EFAULT;
3611 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3612 goto out;
3613 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3614 break;
3615 }
3616 case KVM_X86_SET_MCE: {
3617 struct kvm_x86_mce mce;
3618
3619 r = -EFAULT;
3620 if (copy_from_user(&mce, argp, sizeof mce))
3621 goto out;
3622 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3623 break;
3624 }
3cfc3092
JK		 3625 case KVM_GET_VCPU_EVENTS: {
3626 struct kvm_vcpu_events events;
3627
3628 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3629
3630 r = -EFAULT;
3631 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3632 break;
3633 r = 0;
3634 break;
3635 }
3636 case KVM_SET_VCPU_EVENTS: {
3637 struct kvm_vcpu_events events;
3638
3639 r = -EFAULT;
3640 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3641 break;
3642
3643 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3644 break;
3645 }
a1efbe77
JK		 3646 case KVM_GET_DEBUGREGS: {
3647 struct kvm_debugregs dbgregs;
3648
3649 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3650
3651 r = -EFAULT;
3652 if (copy_to_user(argp, &dbgregs,
3653 sizeof(struct kvm_debugregs)))
3654 break;
3655 r = 0;
3656 break;
3657 }
3658 case KVM_SET_DEBUGREGS: {
3659 struct kvm_debugregs dbgregs;
3660
3661 r = -EFAULT;
3662 if (copy_from_user(&dbgregs, argp,
3663 sizeof(struct kvm_debugregs)))
3664 break;
3665
3666 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3667 break;
3668 }
2d5b5a66 3669 case KVM_GET_XSAVE: {
d1ac91d8 3670 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3671 r = -ENOMEM;
d1ac91d8 3672 if (!u.xsave)
2d5b5a66
SY		 3673 break;
3674
d1ac91d8 3675 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3676
3677 r = -EFAULT;
d1ac91d8 3678 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3679 break;
3680 r = 0;
3681 break;
3682 }
3683 case KVM_SET_XSAVE: {
ff5c2c03 3684 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3685 if (IS_ERR(u.xsave))
3686 return PTR_ERR(u.xsave);
2d5b5a66 3687
d1ac91d8 3688 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3689 break;
3690 }
3691 case KVM_GET_XCRS: {
d1ac91d8 3692 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3693 r = -ENOMEM;
d1ac91d8 3694 if (!u.xcrs)
2d5b5a66
SY		 3695 break;
3696
d1ac91d8 3697 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3698
3699 r = -EFAULT;
d1ac91d8 3700 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3701 sizeof(struct kvm_xcrs)))
3702 break;
3703 r = 0;
3704 break;
3705 }
3706 case KVM_SET_XCRS: {
ff5c2c03 3707 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3708 if (IS_ERR(u.xcrs))
3709 return PTR_ERR(u.xcrs);
2d5b5a66 3710
d1ac91d8 3711 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3712 break;
3713 }
92a1f12d
JR		 3714 case KVM_SET_TSC_KHZ: {
3715 u32 user_tsc_khz;
3716
3717 r = -EINVAL;
92a1f12d
JR		 3718 user_tsc_khz = (u32)arg;
3719
3720 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3721 goto out;
3722
cc578287
ZA		 3723 if (user_tsc_khz == 0)
3724 user_tsc_khz = tsc_khz;
3725
381d585c
HZ		 3726 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3727 r = 0;
92a1f12d 3728
92a1f12d
JR		 3729 goto out;
3730 }
3731 case KVM_GET_TSC_KHZ: {
cc578287 3732 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3733 goto out;
3734 }
1c0b28c2
EM		 3735 case KVM_KVMCLOCK_CTRL: {
3736 r = kvm_set_guest_paused(vcpu);
3737 goto out;
3738 }
5c919412
AS		 3739 case KVM_ENABLE_CAP: {
3740 struct kvm_enable_cap cap;
3741
3742 r = -EFAULT;
3743 if (copy_from_user(&cap, argp, sizeof(cap)))
3744 goto out;
3745 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3746 break;
3747 }
313a3dc7
CO		 3748 default:
3749 r = -EINVAL;
3750 }
3751out:
d1ac91d8 3752 kfree(u.buffer);
313a3dc7
CO		 3753 return r;
3754}
3755
5b1c1493
CO		 3756int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3757{
3758 return VM_FAULT_SIGBUS;
3759}
3760
1fe779f8
CO		 3761static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3762{
3763 int ret;
3764
3765 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3766 return -EINVAL;
1fe779f8
CO		 3767 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3768 return ret;
3769}
3770
b927a3ce
SY		 3771static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3772 u64 ident_addr)
3773{
3774 kvm->arch.ept_identity_map_addr = ident_addr;
3775 return 0;
3776}
3777
1fe779f8
CO		 3778static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3779 u32 kvm_nr_mmu_pages)
3780{
3781 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3782 return -EINVAL;
3783
79fac95e 3784 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3785
3786 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3787 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3788
79fac95e 3789 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3790 return 0;
3791}
3792
3793static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3794{
39de71ec 3795 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3796}
3797
1fe779f8
CO		 3798static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3799{
90bca052 3800 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3801 int r;
3802
3803 r = 0;
3804 switch (chip->chip_id) {
3805 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3806 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3807 sizeof(struct kvm_pic_state));
3808 break;
3809 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3810 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3811 sizeof(struct kvm_pic_state));
3812 break;
3813 case KVM_IRQCHIP_IOAPIC:
33392b49 3814 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3815 break;
3816 default:
3817 r = -EINVAL;
3818 break;
3819 }
3820 return r;
3821}
3822
3823static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3824{
90bca052 3825 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3826 int r;
3827
3828 r = 0;
3829 switch (chip->chip_id) {
3830 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3831 spin_lock(&pic->lock);
3832 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3833 sizeof(struct kvm_pic_state));
90bca052 3834 spin_unlock(&pic->lock);
1fe779f8
CO		 3835 break;
3836 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3837 spin_lock(&pic->lock);
3838 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3839 sizeof(struct kvm_pic_state));
90bca052 3840 spin_unlock(&pic->lock);
1fe779f8
CO		 3841 break;
3842 case KVM_IRQCHIP_IOAPIC:
33392b49 3843 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3844 break;
3845 default:
3846 r = -EINVAL;
3847 break;
3848 }
90bca052 3849 kvm_pic_update_irq(pic);
1fe779f8
CO		 3850 return r;
3851}
3852
e0f63cb9
SY		 3853static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3854{
34f3941c
RK		 3855 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3856
3857 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3858
3859 mutex_lock(&kps->lock);
3860 memcpy(ps, &kps->channels, sizeof(*ps));
3861 mutex_unlock(&kps->lock);
2da29bcc 3862 return 0;
e0f63cb9
SY		 3863}
3864
3865static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3866{
0185604c 3867 int i;
09edea72
RK		 3868 struct kvm_pit *pit = kvm->arch.vpit;
3869
3870 mutex_lock(&pit->pit_state.lock);
34f3941c 3871 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3872 for (i = 0; i < 3; i++)
09edea72
RK		 3873 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3874 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3875 return 0;
e9f42757
BK		 3876}
3877
3878static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3879{
e9f42757
BK		 3880 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3881 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3882 sizeof(ps->channels));
3883 ps->flags = kvm->arch.vpit->pit_state.flags;
3884 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3885 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3886 return 0;
e9f42757
BK		 3887}
3888
3889static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3890{
2da29bcc 3891 int start = 0;
0185604c 3892 int i;
e9f42757 3893 u32 prev_legacy, cur_legacy;
09edea72
RK		 3894 struct kvm_pit *pit = kvm->arch.vpit;
3895
3896 mutex_lock(&pit->pit_state.lock);
3897 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3898 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3899 if (!prev_legacy && cur_legacy)
3900 start = 1;
09edea72
RK		 3901 memcpy(&pit->pit_state.channels, &ps->channels,
3902 sizeof(pit->pit_state.channels));
3903 pit->pit_state.flags = ps->flags;
0185604c 3904 for (i = 0; i < 3; i++)
09edea72 3905 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3906 start && i == 0);
09edea72 3907 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3908 return 0;
e0f63cb9
SY		 3909}
3910
52d939a0
MT		 3911static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3912 struct kvm_reinject_control *control)
3913{
71474e2f
RK		 3914 struct kvm_pit *pit = kvm->arch.vpit;
3915
3916 if (!pit)
52d939a0 3917 return -ENXIO;
b39c90b6 3918
71474e2f
RK		 3919 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3920 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3921 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3922 */
3923 mutex_lock(&pit->pit_state.lock);
3924 kvm_pit_set_reinject(pit, control->pit_reinject);
3925 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3926
52d939a0
MT		 3927 return 0;
3928}
3929
95d4c16c 3930/**
60c34612
TY		 3931 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3932 * @kvm: kvm instance
3933 * @log: slot id and address to which we copy the log
95d4c16c 3934 *
e108ff2f
PB		 3935 * Steps 1-4 below provide general overview of dirty page logging. See
3936 * kvm_get_dirty_log_protect() function description for additional details.
3937 *
3938 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3939 * always flush the TLB (step 4) even if previous step failed and the dirty
3940 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3941 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3942 * writes will be marked dirty for next log read.
95d4c16c 3943 *
60c34612
TY		 3944 * 1. Take a snapshot of the bit and clear it if needed.
3945 * 2. Write protect the corresponding page.
e108ff2f
PB		 3946 * 3. Copy the snapshot to the userspace.
3947 * 4. Flush TLB's if needed.
5bb064dc 3948 */
60c34612 3949int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3950{
60c34612 3951 bool is_dirty = false;
e108ff2f 3952 int r;
5bb064dc 3953
79fac95e 3954 mutex_lock(&kvm->slots_lock);
5bb064dc 3955
88178fd4
KH		 3956 /*
3957 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3958 */
3959 if (kvm_x86_ops->flush_log_dirty)
3960 kvm_x86_ops->flush_log_dirty(kvm);
3961
e108ff2f 3962 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3963
3964 /*
3965 * All the TLBs can be flushed out of mmu lock, see the comments in
3966 * kvm_mmu_slot_remove_write_access().
3967 */
e108ff2f 3968 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3969 if (is_dirty)
3970 kvm_flush_remote_tlbs(kvm);
3971
79fac95e 3972 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3973 return r;
3974}
3975
aa2fbe6d
YZ		 3976int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3977 bool line_status)
23d43cf9
CD		 3978{
3979 if (!irqchip_in_kernel(kvm))
3980 return -ENXIO;
3981
3982 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3983 irq_event->irq, irq_event->level,
3984 line_status);
23d43cf9
CD		 3985 return 0;
3986}
3987
90de4a18
NA		 3988static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3989 struct kvm_enable_cap *cap)
3990{
3991 int r;
3992
3993 if (cap->flags)
3994 return -EINVAL;
3995
3996 switch (cap->cap) {
3997 case KVM_CAP_DISABLE_QUIRKS:
3998 kvm->arch.disabled_quirks = cap->args[0];
3999 r = 0;
4000 break;
49df6397
SR		 4001 case KVM_CAP_SPLIT_IRQCHIP: {
4002 mutex_lock(&kvm->lock);
b053b2ae
SR		 4003 r = -EINVAL;
4004 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4005 goto split_irqchip_unlock;
49df6397
SR		 4006 r = -EEXIST;
4007 if (irqchip_in_kernel(kvm))
4008 goto split_irqchip_unlock;
557abc40 4009 if (kvm->created_vcpus)
49df6397
SR		 4010 goto split_irqchip_unlock;
4011 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4012 if (r)
49df6397
SR		 4013 goto split_irqchip_unlock;
4014 /* Pairs with irqchip_in_kernel. */
4015 smp_wmb();
49776faf 4016 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4017 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4018 r = 0;
4019split_irqchip_unlock:
4020 mutex_unlock(&kvm->lock);
4021 break;
4022 }
37131313
RK		 4023 case KVM_CAP_X2APIC_API:
4024 r = -EINVAL;
4025 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4026 break;
4027
4028 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4029 kvm->arch.x2apic_format = true;
c519265f
RK		 4030 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4031 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4032
4033 r = 0;
4034 break;
90de4a18
NA		 4035 default:
4036 r = -EINVAL;
4037 break;
4038 }
4039 return r;
4040}
4041
1fe779f8
CO		 4042long kvm_arch_vm_ioctl(struct file *filp,
4043 unsigned int ioctl, unsigned long arg)
4044{
4045 struct kvm *kvm = filp->private_data;
4046 void __user *argp = (void __user *)arg;
367e1319 4047 int r = -ENOTTY;
f0d66275
DH		 4048 /*
4049 * This union makes it completely explicit to gcc-3.x
4050 * that these two variables' stack usage should be
4051 * combined, not added together.
4052 */
4053 union {
4054 struct kvm_pit_state ps;
e9f42757 4055 struct kvm_pit_state2 ps2;
c5ff41ce 4056 struct kvm_pit_config pit_config;
f0d66275 4057 } u;
1fe779f8
CO		 4058
4059 switch (ioctl) {
4060 case KVM_SET_TSS_ADDR:
4061 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4062 break;
b927a3ce
SY		 4063 case KVM_SET_IDENTITY_MAP_ADDR: {
4064 u64 ident_addr;
4065
1af1ac91
DH		 4066 mutex_lock(&kvm->lock);
4067 r = -EINVAL;
4068 if (kvm->created_vcpus)
4069 goto set_identity_unlock;
b927a3ce
SY		 4070 r = -EFAULT;
4071 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4072 goto set_identity_unlock;
b927a3ce 4073 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4074set_identity_unlock:
4075 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4076 break;
4077 }
1fe779f8
CO		 4078 case KVM_SET_NR_MMU_PAGES:
4079 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4080 break;
4081 case KVM_GET_NR_MMU_PAGES:
4082 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4083 break;
3ddea128 4084 case KVM_CREATE_IRQCHIP: {
3ddea128 4085 mutex_lock(&kvm->lock);
09941366 4086
3ddea128 4087 r = -EEXIST;
35e6eaa3 4088 if (irqchip_in_kernel(kvm))
3ddea128 4089 goto create_irqchip_unlock;
09941366 4090
3e515705 4091 r = -EINVAL;
557abc40 4092 if (kvm->created_vcpus)
3e515705 4093 goto create_irqchip_unlock;
09941366
RK		 4094
4095 r = kvm_pic_init(kvm);
4096 if (r)
3ddea128 4097 goto create_irqchip_unlock;
09941366
RK		 4098
4099 r = kvm_ioapic_init(kvm);
4100 if (r) {
09941366 4101 kvm_pic_destroy(kvm);
3ddea128 4102 goto create_irqchip_unlock;
09941366
RK		 4103 }
4104
399ec807
AK		 4105 r = kvm_setup_default_irq_routing(kvm);
4106 if (r) {
72bb2fcd 4107 kvm_ioapic_destroy(kvm);
09941366 4108 kvm_pic_destroy(kvm);
71ba994c 4109 goto create_irqchip_unlock;
399ec807 4110 }
49776faf 4111 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4112 smp_wmb();
49776faf 4113 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4114 create_irqchip_unlock:
4115 mutex_unlock(&kvm->lock);
1fe779f8 4116 break;
3ddea128 4117 }
7837699f 4118 case KVM_CREATE_PIT:
c5ff41ce
JK		 4119 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4120 goto create_pit;
4121 case KVM_CREATE_PIT2:
4122 r = -EFAULT;
4123 if (copy_from_user(&u.pit_config, argp,
4124 sizeof(struct kvm_pit_config)))
4125 goto out;
4126 create_pit:
250715a6 4127 mutex_lock(&kvm->lock);
269e05e4
AK		 4128 r = -EEXIST;
4129 if (kvm->arch.vpit)
4130 goto create_pit_unlock;
7837699f 4131 r = -ENOMEM;
c5ff41ce 4132 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4133 if (kvm->arch.vpit)
4134 r = 0;
269e05e4 4135 create_pit_unlock:
250715a6 4136 mutex_unlock(&kvm->lock);
7837699f 4137 break;
1fe779f8
CO		 4138 case KVM_GET_IRQCHIP: {
4139 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4140 struct kvm_irqchip *chip;
1fe779f8 4141
ff5c2c03
SL		 4142 chip = memdup_user(argp, sizeof(*chip));
4143 if (IS_ERR(chip)) {
4144 r = PTR_ERR(chip);
1fe779f8 4145 goto out;
ff5c2c03
SL		 4146 }
4147
1fe779f8 4148 r = -ENXIO;
826da321 4149 if (!irqchip_kernel(kvm))
f0d66275
DH		 4150 goto get_irqchip_out;
4151 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4152 if (r)
f0d66275 4153 goto get_irqchip_out;
1fe779f8 4154 r = -EFAULT;
f0d66275
DH		 4155 if (copy_to_user(argp, chip, sizeof *chip))
4156 goto get_irqchip_out;
1fe779f8 4157 r = 0;
f0d66275
DH		 4158 get_irqchip_out:
4159 kfree(chip);
1fe779f8
CO		 4160 break;
4161 }
4162 case KVM_SET_IRQCHIP: {
4163 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4164 struct kvm_irqchip *chip;
1fe779f8 4165
ff5c2c03
SL		 4166 chip = memdup_user(argp, sizeof(*chip));
4167 if (IS_ERR(chip)) {
4168 r = PTR_ERR(chip);
1fe779f8 4169 goto out;
ff5c2c03
SL		 4170 }
4171
1fe779f8 4172 r = -ENXIO;
826da321 4173 if (!irqchip_kernel(kvm))
f0d66275
DH		 4174 goto set_irqchip_out;
4175 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4176 if (r)
f0d66275 4177 goto set_irqchip_out;
1fe779f8 4178 r = 0;
f0d66275
DH		 4179 set_irqchip_out:
4180 kfree(chip);
1fe779f8
CO		 4181 break;
4182 }
e0f63cb9 4183 case KVM_GET_PIT: {
e0f63cb9 4184 r = -EFAULT;
f0d66275 4185 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4186 goto out;
4187 r = -ENXIO;
4188 if (!kvm->arch.vpit)
4189 goto out;
f0d66275 4190 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4191 if (r)
4192 goto out;
4193 r = -EFAULT;
f0d66275 4194 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4195 goto out;
4196 r = 0;
4197 break;
4198 }
4199 case KVM_SET_PIT: {
e0f63cb9 4200 r = -EFAULT;
f0d66275 4201 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4202 goto out;
4203 r = -ENXIO;
4204 if (!kvm->arch.vpit)
4205 goto out;
f0d66275 4206 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4207 break;
4208 }
e9f42757
BK		 4209 case KVM_GET_PIT2: {
4210 r = -ENXIO;
4211 if (!kvm->arch.vpit)
4212 goto out;
4213 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4214 if (r)
4215 goto out;
4216 r = -EFAULT;
4217 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4218 goto out;
4219 r = 0;
4220 break;
4221 }
4222 case KVM_SET_PIT2: {
4223 r = -EFAULT;
4224 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4225 goto out;
4226 r = -ENXIO;
4227 if (!kvm->arch.vpit)
4228 goto out;
4229 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4230 break;
4231 }
52d939a0
MT		 4232 case KVM_REINJECT_CONTROL: {
4233 struct kvm_reinject_control control;
4234 r = -EFAULT;
4235 if (copy_from_user(&control, argp, sizeof(control)))
4236 goto out;
4237 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4238 break;
4239 }
d71ba788
PB		 4240 case KVM_SET_BOOT_CPU_ID:
4241 r = 0;
4242 mutex_lock(&kvm->lock);
557abc40 4243 if (kvm->created_vcpus)
d71ba788
PB		 4244 r = -EBUSY;
4245 else
4246 kvm->arch.bsp_vcpu_id = arg;
4247 mutex_unlock(&kvm->lock);
4248 break;
ffde22ac
ES		 4249 case KVM_XEN_HVM_CONFIG: {
4250 r = -EFAULT;
4251 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4252 sizeof(struct kvm_xen_hvm_config)))
4253 goto out;
4254 r = -EINVAL;
4255 if (kvm->arch.xen_hvm_config.flags)
4256 goto out;
4257 r = 0;
4258 break;
4259 }
afbcf7ab 4260 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4261 struct kvm_clock_data user_ns;
4262 u64 now_ns;
afbcf7ab
GC		 4263
4264 r = -EFAULT;
4265 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4266 goto out;
4267
4268 r = -EINVAL;
4269 if (user_ns.flags)
4270 goto out;
4271
4272 r = 0;
0bc48bea
RK		 4273 /*
4274 * TODO: userspace has to take care of races with VCPU_RUN, so
4275 * kvm_gen_update_masterclock() can be cut down to locked
4276 * pvclock_update_vm_gtod_copy().
4277 */
4278 kvm_gen_update_masterclock(kvm);
e891a32e 4279 now_ns = get_kvmclock_ns(kvm);
108b249c 4280 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4281 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4282 break;
4283 }
4284 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4285 struct kvm_clock_data user_ns;
4286 u64 now_ns;
4287
e891a32e 4288 now_ns = get_kvmclock_ns(kvm);
108b249c 4289 user_ns.clock = now_ns;
e3fd9a93 4290 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4291 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4292
4293 r = -EFAULT;
4294 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4295 goto out;
4296 r = 0;
4297 break;
4298 }
90de4a18
NA		 4299 case KVM_ENABLE_CAP: {
4300 struct kvm_enable_cap cap;
afbcf7ab 4301
90de4a18
NA		 4302 r = -EFAULT;
4303 if (copy_from_user(&cap, argp, sizeof(cap)))
4304 goto out;
4305 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4306 break;
4307 }
1fe779f8 4308 default:
ad6260da 4309 r = -ENOTTY;
1fe779f8
CO		 4310 }
4311out:
4312 return r;
4313}
4314
a16b043c 4315static void kvm_init_msr_list(void)
043405e1
CO		 4316{
4317 u32 dummy[2];
4318 unsigned i, j;
4319
62ef68bb 4320 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4321 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4322 continue;
93c4adc7
PB		 4323
4324 /*
4325 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4326 * to the guests in some cases.
93c4adc7
PB		 4327 */
4328 switch (msrs_to_save[i]) {
4329 case MSR_IA32_BNDCFGS:
4330 if (!kvm_x86_ops->mpx_supported())
4331 continue;
4332 break;
9dbe6cf9
PB		 4333 case MSR_TSC_AUX:
4334 if (!kvm_x86_ops->rdtscp_supported())
4335 continue;
4336 break;
93c4adc7
PB		 4337 default:
4338 break;
4339 }
4340
043405e1
CO		 4341 if (j < i)
4342 msrs_to_save[j] = msrs_to_save[i];
4343 j++;
4344 }
4345 num_msrs_to_save = j;
62ef68bb
PB		 4346
4347 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4348 switch (emulated_msrs[i]) {
6d396b55
PB		 4349 case MSR_IA32_SMBASE:
4350 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4351 continue;
4352 break;
62ef68bb
PB		 4353 default:
4354 break;
4355 }
4356
4357 if (j < i)
4358 emulated_msrs[j] = emulated_msrs[i];
4359 j++;
4360 }
4361 num_emulated_msrs = j;
043405e1
CO		 4362}
4363
bda9020e
MT		 4364static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4365 const void *v)
bbd9b64e 4366{
70252a10
AK		 4367 int handled = 0;
4368 int n;
4369
4370 do {
4371 n = min(len, 8);
bce87cce 4372 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4373 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4374 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4375 break;
4376 handled += n;
4377 addr += n;
4378 len -= n;
4379 v += n;
4380 } while (len);
bbd9b64e 4381
70252a10 4382 return handled;
bbd9b64e
CO		 4383}
4384
bda9020e 4385static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4386{
70252a10
AK		 4387 int handled = 0;
4388 int n;
4389
4390 do {
4391 n = min(len, 8);
bce87cce 4392 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4393 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4394 addr, n, v))
4395 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4396 break;
e39d200f 4397 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4398 handled += n;
4399 addr += n;
4400 len -= n;
4401 v += n;
4402 } while (len);
bbd9b64e 4403
70252a10 4404 return handled;
bbd9b64e
CO		 4405}
4406
2dafc6c2
GN		 4407static void kvm_set_segment(struct kvm_vcpu *vcpu,
4408 struct kvm_segment *var, int seg)
4409{
4410 kvm_x86_ops->set_segment(vcpu, var, seg);
4411}
4412
4413void kvm_get_segment(struct kvm_vcpu *vcpu,
4414 struct kvm_segment *var, int seg)
4415{
4416 kvm_x86_ops->get_segment(vcpu, var, seg);
4417}
4418
54987b7a
PB		 4419gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4420 struct x86_exception *exception)
02f59dc9
JR		 4421{
4422 gpa_t t_gpa;
02f59dc9
JR		 4423
4424 BUG_ON(!mmu_is_nested(vcpu));
4425
4426 /* NPT walks are always user-walks */
4427 access |= PFERR_USER_MASK;
54987b7a 4428 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4429
4430 return t_gpa;
4431}
4432
ab9ae313
AK		 4433gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4434 struct x86_exception *exception)
1871c602
GN		 4435{
4436 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4437 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4438}
4439
ab9ae313
AK		 4440 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4441 struct x86_exception *exception)
1871c602
GN		 4442{
4443 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4444 access |= PFERR_FETCH_MASK;
ab9ae313 4445 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4446}
4447
ab9ae313
AK		 4448gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4449 struct x86_exception *exception)
1871c602
GN		 4450{
4451 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4452 access |= PFERR_WRITE_MASK;
ab9ae313 4453 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4454}
4455
4456/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4457gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4458 struct x86_exception *exception)
1871c602 4459{
ab9ae313 4460 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4461}
4462
4463static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4464 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4465 struct x86_exception *exception)
bbd9b64e
CO		 4466{
4467 void *data = val;
10589a46 4468 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4469
4470 while (bytes) {
14dfe855 4471 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4472 exception);
bbd9b64e 4473 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4474 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4475 int ret;
4476
bcc55cba 4477 if (gpa == UNMAPPED_GVA)
ab9ae313 4478 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4479 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4480 offset, toread);
10589a46 4481 if (ret < 0) {
c3cd7ffa 4482 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4483 goto out;
4484 }
bbd9b64e 4485
77c2002e
IE		 4486 bytes -= toread;
4487 data += toread;
4488 addr += toread;
bbd9b64e 4489 }
10589a46 4490out:
10589a46 4491 return r;
bbd9b64e 4492}
77c2002e 4493
1871c602 4494/* used for instruction fetching */
0f65dd70
AK		 4495static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4496 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4497 struct x86_exception *exception)
1871c602 4498{
0f65dd70 4499 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4500 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4501 unsigned offset;
4502 int ret;
0f65dd70 4503
44583cba
PB		 4504 /* Inline kvm_read_guest_virt_helper for speed. */
4505 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4506 exception);
4507 if (unlikely(gpa == UNMAPPED_GVA))
4508 return X86EMUL_PROPAGATE_FAULT;
4509
4510 offset = addr & (PAGE_SIZE-1);
4511 if (WARN_ON(offset + bytes > PAGE_SIZE))
4512 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4513 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4514 offset, bytes);
44583cba
PB		 4515 if (unlikely(ret < 0))
4516 return X86EMUL_IO_NEEDED;
4517
4518 return X86EMUL_CONTINUE;
1871c602
GN		 4519}
4520
064aea77 4521int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4522 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4523 struct x86_exception *exception)
1871c602 4524{
0f65dd70 4525 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4526 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4527
1871c602 4528 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4529 exception);
1871c602 4530}
064aea77 4531EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4532
0f65dd70
AK		 4533static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4534 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4535 struct x86_exception *exception)
1871c602 4536{
0f65dd70 4537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4538 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4539}
4540
7a036a6f
RK		 4541static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4542 unsigned long addr, void *val, unsigned int bytes)
4543{
4544 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4545 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4546
4547 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4548}
4549
6a4d7550 4550int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4551 gva_t addr, void *val,
2dafc6c2 4552 unsigned int bytes,
bcc55cba 4553 struct x86_exception *exception)
77c2002e 4554{
0f65dd70 4555 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4556 void *data = val;
4557 int r = X86EMUL_CONTINUE;
4558
4559 while (bytes) {
14dfe855
JR		 4560 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4561 PFERR_WRITE_MASK,
ab9ae313 4562 exception);
77c2002e
IE		 4563 unsigned offset = addr & (PAGE_SIZE-1);
4564 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4565 int ret;
4566
bcc55cba 4567 if (gpa == UNMAPPED_GVA)
ab9ae313 4568 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4569 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4570 if (ret < 0) {
c3cd7ffa 4571 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4572 goto out;
4573 }
4574
4575 bytes -= towrite;
4576 data += towrite;
4577 addr += towrite;
4578 }
4579out:
4580 return r;
4581}
6a4d7550 4582EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4583
0f89b207
TL		 4584static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4585 gpa_t gpa, bool write)
4586{
4587 /* For APIC access vmexit */
4588 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4589 return 1;
4590
4591 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4592 trace_vcpu_match_mmio(gva, gpa, write, true);
4593 return 1;
4594 }
4595
4596 return 0;
4597}
4598
af7cc7d1
XG		 4599static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4600 gpa_t *gpa, struct x86_exception *exception,
4601 bool write)
4602{
97d64b78
AK		 4603 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4604 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4605
be94f6b7
HH		 4606 /*
4607 * currently PKRU is only applied to ept enabled guest so
4608 * there is no pkey in EPT page table for L1 guest or EPT
4609 * shadow page table for L2 guest.
4610 */
97d64b78 4611 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4612 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4613 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4614 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4615 (gva & (PAGE_SIZE - 1));
4f022648 4616 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4617 return 1;
4618 }
4619
af7cc7d1
XG		 4620 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4621
4622 if (*gpa == UNMAPPED_GVA)
4623 return -1;
4624
0f89b207 4625 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4626}
4627
3200f405 4628int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4629 const void *val, int bytes)
bbd9b64e
CO		 4630{
4631 int ret;
4632
54bf36aa 4633 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4634 if (ret < 0)
bbd9b64e 4635 return 0;
0eb05bf2 4636 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4637 return 1;
4638}
4639
77d197b2
XG		 4640struct read_write_emulator_ops {
4641 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4642 int bytes);
4643 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4644 void *val, int bytes);
4645 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4646 int bytes, void *val);
4647 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4648 void *val, int bytes);
4649 bool write;
4650};
4651
4652static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4653{
4654 if (vcpu->mmio_read_completed) {
77d197b2 4655 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4656 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4657 vcpu->mmio_read_completed = 0;
4658 return 1;
4659 }
4660
4661 return 0;
4662}
4663
4664static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4665 void *val, int bytes)
4666{
54bf36aa 4667 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4668}
4669
4670static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4671 void *val, int bytes)
4672{
4673 return emulator_write_phys(vcpu, gpa, val, bytes);
4674}
4675
4676static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4677{
e39d200f 4678 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4679 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4680}
4681
4682static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4683 void *val, int bytes)
4684{
e39d200f 4685 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4686 return X86EMUL_IO_NEEDED;
4687}
4688
4689static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4690 void *val, int bytes)
4691{
f78146b0
AK		 4692 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4693
87da7e66 4694 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4695 return X86EMUL_CONTINUE;
4696}
4697
0fbe9b0b 4698static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4699 .read_write_prepare = read_prepare,
4700 .read_write_emulate = read_emulate,
4701 .read_write_mmio = vcpu_mmio_read,
4702 .read_write_exit_mmio = read_exit_mmio,
4703};
4704
0fbe9b0b 4705static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4706 .read_write_emulate = write_emulate,
4707 .read_write_mmio = write_mmio,
4708 .read_write_exit_mmio = write_exit_mmio,
4709 .write = true,
4710};
4711
22388a3c
XG		 4712static int emulator_read_write_onepage(unsigned long addr, void *val,
4713 unsigned int bytes,
4714 struct x86_exception *exception,
4715 struct kvm_vcpu *vcpu,
0fbe9b0b 4716 const struct read_write_emulator_ops *ops)
bbd9b64e 4717{
af7cc7d1
XG		 4718 gpa_t gpa;
4719 int handled, ret;
22388a3c 4720 bool write = ops->write;
f78146b0 4721 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4722 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4723
4724 /*
4725 * If the exit was due to a NPF we may already have a GPA.
4726 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4727 * Note, this cannot be used on string operations since string
4728 * operation using rep will only have the initial GPA from the NPF
4729 * occurred.
4730 */
4731 if (vcpu->arch.gpa_available &&
4732 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4733 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4734 gpa = vcpu->arch.gpa_val;
4735 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4736 } else {
4737 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4738 if (ret < 0)
4739 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4740 }
10589a46 4741
618232e2 4742 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4743 return X86EMUL_CONTINUE;
4744
bbd9b64e
CO		 4745 /*
4746 * Is this MMIO handled locally?
4747 */
22388a3c 4748 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4749 if (handled == bytes)
bbd9b64e 4750 return X86EMUL_CONTINUE;
bbd9b64e 4751
70252a10
AK		 4752 gpa += handled;
4753 bytes -= handled;
4754 val += handled;
4755
87da7e66
XG		 4756 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4757 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4758 frag->gpa = gpa;
4759 frag->data = val;
4760 frag->len = bytes;
f78146b0 4761 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4762}
4763
52eb5a6d
XL		 4764static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4765 unsigned long addr,
22388a3c
XG		 4766 void *val, unsigned int bytes,
4767 struct x86_exception *exception,
0fbe9b0b 4768 const struct read_write_emulator_ops *ops)
bbd9b64e 4769{
0f65dd70 4770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4771 gpa_t gpa;
4772 int rc;
4773
4774 if (ops->read_write_prepare &&
4775 ops->read_write_prepare(vcpu, val, bytes))
4776 return X86EMUL_CONTINUE;
4777
4778 vcpu->mmio_nr_fragments = 0;
0f65dd70 4779
bbd9b64e
CO		 4780 /* Crossing a page boundary? */
4781 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4782 int now;
bbd9b64e
CO		 4783
4784 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4785 rc = emulator_read_write_onepage(addr, val, now, exception,
4786 vcpu, ops);
4787
bbd9b64e
CO		 4788 if (rc != X86EMUL_CONTINUE)
4789 return rc;
4790 addr += now;
bac15531
NA		 4791 if (ctxt->mode != X86EMUL_MODE_PROT64)
4792 addr = (u32)addr;
bbd9b64e
CO		 4793 val += now;
4794 bytes -= now;
4795 }
22388a3c 4796
f78146b0
AK		 4797 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4798 vcpu, ops);
4799 if (rc != X86EMUL_CONTINUE)
4800 return rc;
4801
4802 if (!vcpu->mmio_nr_fragments)
4803 return rc;
4804
4805 gpa = vcpu->mmio_fragments[0].gpa;
4806
4807 vcpu->mmio_needed = 1;
4808 vcpu->mmio_cur_fragment = 0;
4809
87da7e66 4810 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4811 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4812 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4813 vcpu->run->mmio.phys_addr = gpa;
4814
4815 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4816}
4817
4818static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4819 unsigned long addr,
4820 void *val,
4821 unsigned int bytes,
4822 struct x86_exception *exception)
4823{
4824 return emulator_read_write(ctxt, addr, val, bytes,
4825 exception, &read_emultor);
4826}
4827
52eb5a6d 4828static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4829 unsigned long addr,
4830 const void *val,
4831 unsigned int bytes,
4832 struct x86_exception *exception)
4833{
4834 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4835 exception, &write_emultor);
bbd9b64e 4836}
bbd9b64e 4837
daea3e73
AK		 4838#define CMPXCHG_TYPE(t, ptr, old, new) \
4839 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4840
4841#ifdef CONFIG_X86_64
4842# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4843#else
4844# define CMPXCHG64(ptr, old, new) \
9749a6c0 4845 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4846#endif
4847
0f65dd70
AK		 4848static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4849 unsigned long addr,
bbd9b64e
CO		 4850 const void *old,
4851 const void *new,
4852 unsigned int bytes,
0f65dd70 4853 struct x86_exception *exception)
bbd9b64e 4854{
0f65dd70 4855 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4856 gpa_t gpa;
4857 struct page *page;
4858 char *kaddr;
4859 bool exchanged;
2bacc55c 4860
daea3e73
AK		 4861 /* guests cmpxchg8b have to be emulated atomically */
4862 if (bytes > 8 || (bytes & (bytes - 1)))
4863 goto emul_write;
10589a46 4864
daea3e73 4865 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4866
daea3e73
AK		 4867 if (gpa == UNMAPPED_GVA ||
4868 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4869 goto emul_write;
2bacc55c 4870
daea3e73
AK		 4871 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4872 goto emul_write;
72dc67a6 4873
54bf36aa 4874 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4875 if (is_error_page(page))
c19b8bd6 4876 goto emul_write;
72dc67a6 4877
8fd75e12 4878 kaddr = kmap_atomic(page);
daea3e73
AK		 4879 kaddr += offset_in_page(gpa);
4880 switch (bytes) {
4881 case 1:
4882 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4883 break;
4884 case 2:
4885 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4886 break;
4887 case 4:
4888 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4889 break;
4890 case 8:
4891 exchanged = CMPXCHG64(kaddr, old, new);
4892 break;
4893 default:
4894 BUG();
2bacc55c 4895 }
8fd75e12 4896 kunmap_atomic(kaddr);
daea3e73
AK		 4897 kvm_release_page_dirty(page);
4898
4899 if (!exchanged)
4900 return X86EMUL_CMPXCHG_FAILED;
4901
54bf36aa 4902 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4903 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4904
4905 return X86EMUL_CONTINUE;
4a5f48f6 4906
3200f405 4907emul_write:
daea3e73 4908 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4909
0f65dd70 4910 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4911}
4912
cf8f70bf
GN		 4913static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4914{
cbfc6c91 4915 int r = 0, i;
cf8f70bf 4916
cbfc6c91
WL		 4917 for (i = 0; i < vcpu->arch.pio.count; i++) {
4918 if (vcpu->arch.pio.in)
4919 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4920 vcpu->arch.pio.size, pd);
4921 else
4922 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4923 vcpu->arch.pio.port, vcpu->arch.pio.size,
4924 pd);
4925 if (r)
4926 break;
4927 pd += vcpu->arch.pio.size;
4928 }
cf8f70bf
GN		 4929 return r;
4930}
4931
6f6fbe98
XG		 4932static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4933 unsigned short port, void *val,
4934 unsigned int count, bool in)
cf8f70bf 4935{
cf8f70bf 4936 vcpu->arch.pio.port = port;
6f6fbe98 4937 vcpu->arch.pio.in = in;
7972995b 4938 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4939 vcpu->arch.pio.size = size;
4940
4941 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4942 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4943 return 1;
4944 }
4945
4946 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4947 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4948 vcpu->run->io.size = size;
4949 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4950 vcpu->run->io.count = count;
4951 vcpu->run->io.port = port;
4952
4953 return 0;
4954}
4955
6f6fbe98
XG		 4956static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4957 int size, unsigned short port, void *val,
4958 unsigned int count)
cf8f70bf 4959{
ca1d4a9e 4960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4961 int ret;
ca1d4a9e 4962
6f6fbe98
XG		 4963 if (vcpu->arch.pio.count)
4964 goto data_avail;
cf8f70bf 4965
cbfc6c91
WL		 4966 memset(vcpu->arch.pio_data, 0, size * count);
4967
6f6fbe98
XG		 4968 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4969 if (ret) {
4970data_avail:
4971 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4972 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4973 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4974 return 1;
4975 }
4976
cf8f70bf
GN		 4977 return 0;
4978}
4979
6f6fbe98
XG		 4980static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4981 int size, unsigned short port,
4982 const void *val, unsigned int count)
4983{
4984 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4985
4986 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4987 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4988 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4989}
4990
bbd9b64e
CO		 4991static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4992{
4993 return kvm_x86_ops->get_segment_base(vcpu, seg);
4994}
4995
3cb16fe7 4996static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4997{
3cb16fe7 4998 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4999}
5000
ae6a2375 5001static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5002{
5003 if (!need_emulate_wbinvd(vcpu))
5004 return X86EMUL_CONTINUE;
5005
5006 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5007 int cpu = get_cpu();
5008
5009 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5010 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5011 wbinvd_ipi, NULL, 1);
2eec7343 5012 put_cpu();
f5f48ee1 5013 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5014 } else
5015 wbinvd();
f5f48ee1
SY		 5016 return X86EMUL_CONTINUE;
5017}
5cb56059
JS		 5018
5019int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5020{
6affcbed
KH		 5021 kvm_emulate_wbinvd_noskip(vcpu);
5022 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5023}
f5f48ee1
SY		 5024EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5025
5cb56059
JS		 5026
5027
bcaf5cc5
AK		 5028static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5029{
5cb56059 5030 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5031}
5032
52eb5a6d
XL		 5033static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5034 unsigned long *dest)
bbd9b64e 5035{
16f8a6f9 5036 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5037}
5038
52eb5a6d
XL		 5039static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5040 unsigned long value)
bbd9b64e 5041{
338dbc97 5042
717746e3 5043 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5044}
5045
52a46617 5046static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5047{
52a46617 5048 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5049}
5050
717746e3 5051static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5052{
717746e3 5053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5054 unsigned long value;
5055
5056 switch (cr) {
5057 case 0:
5058 value = kvm_read_cr0(vcpu);
5059 break;
5060 case 2:
5061 value = vcpu->arch.cr2;
5062 break;
5063 case 3:
9f8fe504 5064 value = kvm_read_cr3(vcpu);
52a46617
GN		 5065 break;
5066 case 4:
5067 value = kvm_read_cr4(vcpu);
5068 break;
5069 case 8:
5070 value = kvm_get_cr8(vcpu);
5071 break;
5072 default:
a737f256 5073 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5074 return 0;
5075 }
5076
5077 return value;
5078}
5079
717746e3 5080static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5081{
717746e3 5082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5083 int res = 0;
5084
52a46617
GN		 5085 switch (cr) {
5086 case 0:
49a9b07e 5087 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5088 break;
5089 case 2:
5090 vcpu->arch.cr2 = val;
5091 break;
5092 case 3:
2390218b 5093 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5094 break;
5095 case 4:
a83b29c6 5096 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5097 break;
5098 case 8:
eea1cff9 5099 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5100 break;
5101 default:
a737f256 5102 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5103 res = -1;
52a46617 5104 }
0f12244f
GN		 5105
5106 return res;
52a46617
GN		 5107}
5108
717746e3 5109static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5110{
717746e3 5111 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5112}
5113
4bff1e86 5114static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5115{
4bff1e86 5116 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5117}
5118
4bff1e86 5119static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5120{
4bff1e86 5121 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5122}
5123
1ac9d0cf
AK		 5124static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5125{
5126 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5127}
5128
5129static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5130{
5131 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5132}
5133
4bff1e86
AK		 5134static unsigned long emulator_get_cached_segment_base(
5135 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5136{
4bff1e86 5137 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5138}
5139
1aa36616
AK		 5140static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5141 struct desc_struct *desc, u32 *base3,
5142 int seg)
2dafc6c2
GN		 5143{
5144 struct kvm_segment var;
5145
4bff1e86 5146 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5147 *selector = var.selector;
2dafc6c2 5148
378a8b09
GN		 5149 if (var.unusable) {
5150 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5151 if (base3)
5152 *base3 = 0;
2dafc6c2 5153 return false;
378a8b09 5154 }
2dafc6c2
GN		 5155
5156 if (var.g)
5157 var.limit >>= 12;
5158 set_desc_limit(desc, var.limit);
5159 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5160#ifdef CONFIG_X86_64
5161 if (base3)
5162 *base3 = var.base >> 32;
5163#endif
2dafc6c2
GN		 5164 desc->type = var.type;
5165 desc->s = var.s;
5166 desc->dpl = var.dpl;
5167 desc->p = var.present;
5168 desc->avl = var.avl;
5169 desc->l = var.l;
5170 desc->d = var.db;
5171 desc->g = var.g;
5172
5173 return true;
5174}
5175
1aa36616
AK		 5176static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5177 struct desc_struct *desc, u32 base3,
5178 int seg)
2dafc6c2 5179{
4bff1e86 5180 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5181 struct kvm_segment var;
5182
1aa36616 5183 var.selector = selector;
2dafc6c2 5184 var.base = get_desc_base(desc);
5601d05b
GN		 5185#ifdef CONFIG_X86_64
5186 var.base |= ((u64)base3) << 32;
5187#endif
2dafc6c2
GN		 5188 var.limit = get_desc_limit(desc);
5189 if (desc->g)
5190 var.limit = (var.limit << 12) | 0xfff;
5191 var.type = desc->type;
2dafc6c2
GN		 5192 var.dpl = desc->dpl;
5193 var.db = desc->d;
5194 var.s = desc->s;
5195 var.l = desc->l;
5196 var.g = desc->g;
5197 var.avl = desc->avl;
5198 var.present = desc->p;
5199 var.unusable = !var.present;
5200 var.padding = 0;
5201
5202 kvm_set_segment(vcpu, &var, seg);
5203 return;
5204}
5205
717746e3
AK		 5206static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5207 u32 msr_index, u64 *pdata)
5208{
609e36d3
PB		 5209 struct msr_data msr;
5210 int r;
5211
5212 msr.index = msr_index;
5213 msr.host_initiated = false;
5214 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5215 if (r)
5216 return r;
5217
5218 *pdata = msr.data;
5219 return 0;
717746e3
AK		 5220}
5221
5222static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5223 u32 msr_index, u64 data)
5224{
8fe8ab46
WA		 5225 struct msr_data msr;
5226
5227 msr.data = data;
5228 msr.index = msr_index;
5229 msr.host_initiated = false;
5230 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5231}
5232
64d60670
PB		 5233static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5234{
5235 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5236
5237 return vcpu->arch.smbase;
5238}
5239
5240static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5241{
5242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5243
5244 vcpu->arch.smbase = smbase;
5245}
5246
67f4d428
NA		 5247static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5248 u32 pmc)
5249{
c6702c9d 5250 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5251}
5252
222d21aa
AK		 5253static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5254 u32 pmc, u64 *pdata)
5255{
c6702c9d 5256 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5257}
5258
6c3287f7
AK		 5259static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5260{
5261 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5262}
5263
2953538e 5264static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5265 struct x86_instruction_info *info,
c4f035c6
AK		 5266 enum x86_intercept_stage stage)
5267{
2953538e 5268 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5269}
5270
e911eb3b
YZ		 5271static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5272 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5273{
e911eb3b 5274 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5275}
5276
dd856efa
AK		 5277static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5278{
5279 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5280}
5281
5282static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5283{
5284 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5285}
5286
801806d9
NA		 5287static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5288{
5289 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5290}
5291
6ed071f0
LP		 5292static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5293{
5294 return emul_to_vcpu(ctxt)->arch.hflags;
5295}
5296
5297static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5298{
5299 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5300}
5301
0234bf88
LP		 5302static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5303{
5304 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5305}
5306
0225fb50 5307static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5308 .read_gpr = emulator_read_gpr,
5309 .write_gpr = emulator_write_gpr,
1871c602 5310 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5311 .write_std = kvm_write_guest_virt_system,
7a036a6f 5312 .read_phys = kvm_read_guest_phys_system,
1871c602 5313 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5314 .read_emulated = emulator_read_emulated,
5315 .write_emulated = emulator_write_emulated,
5316 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5317 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5318 .pio_in_emulated = emulator_pio_in_emulated,
5319 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5320 .get_segment = emulator_get_segment,
5321 .set_segment = emulator_set_segment,
5951c442 5322 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5323 .get_gdt = emulator_get_gdt,
160ce1f1 5324 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5325 .set_gdt = emulator_set_gdt,
5326 .set_idt = emulator_set_idt,
52a46617
GN		 5327 .get_cr = emulator_get_cr,
5328 .set_cr = emulator_set_cr,
9c537244 5329 .cpl = emulator_get_cpl,
35aa5375
GN		 5330 .get_dr = emulator_get_dr,
5331 .set_dr = emulator_set_dr,
64d60670
PB		 5332 .get_smbase = emulator_get_smbase,
5333 .set_smbase = emulator_set_smbase,
717746e3
AK		 5334 .set_msr = emulator_set_msr,
5335 .get_msr = emulator_get_msr,
67f4d428 5336 .check_pmc = emulator_check_pmc,
222d21aa 5337 .read_pmc = emulator_read_pmc,
6c3287f7 5338 .halt = emulator_halt,
bcaf5cc5 5339 .wbinvd = emulator_wbinvd,
d6aa1000 5340 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5341 .intercept = emulator_intercept,
bdb42f5a 5342 .get_cpuid = emulator_get_cpuid,
801806d9 5343 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5344 .get_hflags = emulator_get_hflags,
5345 .set_hflags = emulator_set_hflags,
0234bf88 5346 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5347};
5348
95cb2295
GN		 5349static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5350{
37ccdcbe 5351 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5352 /*
5353 * an sti; sti; sequence only disable interrupts for the first
5354 * instruction. So, if the last instruction, be it emulated or
5355 * not, left the system with the INT_STI flag enabled, it
5356 * means that the last instruction is an sti. We should not
5357 * leave the flag on in this case. The same goes for mov ss
5358 */
37ccdcbe
PB		 5359 if (int_shadow & mask)
5360 mask = 0;
6addfc42 5361 if (unlikely(int_shadow || mask)) {
95cb2295 5362 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5363 if (!mask)
5364 kvm_make_request(KVM_REQ_EVENT, vcpu);
5365 }
95cb2295
GN		 5366}
5367
ef54bcfe 5368static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5369{
5370 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5371 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5372 return kvm_propagate_fault(vcpu, &ctxt->exception);
5373
5374 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5375 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5376 ctxt->exception.error_code);
54b8486f 5377 else
da9cb575 5378 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5379 return false;
54b8486f
GN		 5380}
5381
8ec4722d
MG		 5382static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5383{
adf52235 5384 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5385 int cs_db, cs_l;
5386
8ec4722d
MG		 5387 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5388
adf52235 5389 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5390 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5391
adf52235
TY		 5392 ctxt->eip = kvm_rip_read(vcpu);
5393 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5394 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5395 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5396 cs_db ? X86EMUL_MODE_PROT32 :
5397 X86EMUL_MODE_PROT16;
a584539b 5398 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5399 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5400 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5401
dd856efa 5402 init_decode_cache(ctxt);
7ae441ea 5403 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5404}
5405
71f9833b 5406int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5407{
9d74191a 5408 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5409 int ret;
5410
5411 init_emulate_ctxt(vcpu);
5412
9dac77fa
AK		 5413 ctxt->op_bytes = 2;
5414 ctxt->ad_bytes = 2;
5415 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5416 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5417
5418 if (ret != X86EMUL_CONTINUE)
5419 return EMULATE_FAIL;
5420
9dac77fa 5421 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5422 kvm_rip_write(vcpu, ctxt->eip);
5423 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5424
5425 if (irq == NMI_VECTOR)
7460fb4a 5426 vcpu->arch.nmi_pending = 0;
63995653
MG		 5427 else
5428 vcpu->arch.interrupt.pending = false;
5429
5430 return EMULATE_DONE;
5431}
5432EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5433
6d77dbfc
GN		 5434static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5435{
fc3a9157
JR		 5436 int r = EMULATE_DONE;
5437
6d77dbfc
GN		 5438 ++vcpu->stat.insn_emulation_fail;
5439 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5440 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5441 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5442 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5443 vcpu->run->internal.ndata = 0;
1f4dcb3b 5444 r = EMULATE_USER_EXIT;
fc3a9157 5445 }
6d77dbfc 5446 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5447
5448 return r;
6d77dbfc
GN		 5449}
5450
93c05d3e 5451static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5452 bool write_fault_to_shadow_pgtable,
5453 int emulation_type)
a6f177ef 5454{
95b3cf69 5455 gpa_t gpa = cr2;
ba049e93 5456 kvm_pfn_t pfn;
a6f177ef 5457
991eebf9
GN		 5458 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5459 return false;
5460
95b3cf69
XG		 5461 if (!vcpu->arch.mmu.direct_map) {
5462 /*
5463 * Write permission should be allowed since only
5464 * write access need to be emulated.
5465 */
5466 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5467
95b3cf69
XG		 5468 /*
5469 * If the mapping is invalid in guest, let cpu retry
5470 * it to generate fault.
5471 */
5472 if (gpa == UNMAPPED_GVA)
5473 return true;
5474 }
a6f177ef 5475
8e3d9d06
XG		 5476 /*
5477 * Do not retry the unhandleable instruction if it faults on the
5478 * readonly host memory, otherwise it will goto a infinite loop:
5479 * retry instruction -> write #PF -> emulation fail -> retry
5480 * instruction -> ...
5481 */
5482 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5483
5484 /*
5485 * If the instruction failed on the error pfn, it can not be fixed,
5486 * report the error to userspace.
5487 */
5488 if (is_error_noslot_pfn(pfn))
5489 return false;
5490
5491 kvm_release_pfn_clean(pfn);
5492
5493 /* The instructions are well-emulated on direct mmu. */
5494 if (vcpu->arch.mmu.direct_map) {
5495 unsigned int indirect_shadow_pages;
5496
5497 spin_lock(&vcpu->kvm->mmu_lock);
5498 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5499 spin_unlock(&vcpu->kvm->mmu_lock);
5500
5501 if (indirect_shadow_pages)
5502 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5503
a6f177ef 5504 return true;
8e3d9d06 5505 }
a6f177ef 5506
95b3cf69
XG		 5507 /*
5508 * if emulation was due to access to shadowed page table
5509 * and it failed try to unshadow page and re-enter the
5510 * guest to let CPU execute the instruction.
5511 */
5512 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5513
5514 /*
5515 * If the access faults on its page table, it can not
5516 * be fixed by unprotecting shadow page and it should
5517 * be reported to userspace.
5518 */
5519 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5520}
5521
1cb3f3ae
XG		 5522static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5523 unsigned long cr2, int emulation_type)
5524{
5525 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5526 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5527
5528 last_retry_eip = vcpu->arch.last_retry_eip;
5529 last_retry_addr = vcpu->arch.last_retry_addr;
5530
5531 /*
5532 * If the emulation is caused by #PF and it is non-page_table
5533 * writing instruction, it means the VM-EXIT is caused by shadow
5534 * page protected, we can zap the shadow page and retry this
5535 * instruction directly.
5536 *
5537 * Note: if the guest uses a non-page-table modifying instruction
5538 * on the PDE that points to the instruction, then we will unmap
5539 * the instruction and go to an infinite loop. So, we cache the
5540 * last retried eip and the last fault address, if we meet the eip
5541 * and the address again, we can break out of the potential infinite
5542 * loop.
5543 */
5544 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5545
5546 if (!(emulation_type & EMULTYPE_RETRY))
5547 return false;
5548
5549 if (x86_page_table_writing_insn(ctxt))
5550 return false;
5551
5552 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5553 return false;
5554
5555 vcpu->arch.last_retry_eip = ctxt->eip;
5556 vcpu->arch.last_retry_addr = cr2;
5557
5558 if (!vcpu->arch.mmu.direct_map)
5559 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5560
22368028 5561 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5562
5563 return true;
5564}
5565
716d51ab
GN		 5566static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5567static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5568
64d60670 5569static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5570{
64d60670 5571 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5572 /* This is a good place to trace that we are exiting SMM. */
5573 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5574
c43203ca
PB		 5575 /* Process a latched INIT or SMI, if any. */
5576 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5577 }
699023e2
PB		 5578
5579 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5580}
5581
5582static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5583{
5584 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5585
a584539b 5586 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5587
5588 if (changed & HF_SMM_MASK)
5589 kvm_smm_changed(vcpu);
a584539b
PB		 5590}
5591
4a1e10d5
PB		 5592static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5593 unsigned long *db)
5594{
5595 u32 dr6 = 0;
5596 int i;
5597 u32 enable, rwlen;
5598
5599 enable = dr7;
5600 rwlen = dr7 >> 16;
5601 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5602 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5603 dr6 |= (1 << i);
5604 return dr6;
5605}
5606
c8401dda 5607static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5608{
5609 struct kvm_run *kvm_run = vcpu->run;
5610
c8401dda
PB		 5611 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5612 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5613 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5614 kvm_run->debug.arch.exception = DB_VECTOR;
5615 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5616 *r = EMULATE_USER_EXIT;
5617 } else {
5618 /*
5619 * "Certain debug exceptions may clear bit 0-3. The
5620 * remaining contents of the DR6 register are never
5621 * cleared by the processor".
5622 */
5623 vcpu->arch.dr6 &= ~15;
5624 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5625 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5626 }
5627}
5628
6affcbed
KH		 5629int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5630{
5631 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5632 int r = EMULATE_DONE;
5633
5634 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5635
5636 /*
5637 * rflags is the old, "raw" value of the flags. The new value has
5638 * not been saved yet.
5639 *
5640 * This is correct even for TF set by the guest, because "the
5641 * processor will not generate this exception after the instruction
5642 * that sets the TF flag".
5643 */
5644 if (unlikely(rflags & X86_EFLAGS_TF))
5645 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5646 return r == EMULATE_DONE;
5647}
5648EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5649
4a1e10d5
PB		 5650static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5651{
4a1e10d5
PB		 5652 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5653 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5654 struct kvm_run *kvm_run = vcpu->run;
5655 unsigned long eip = kvm_get_linear_rip(vcpu);
5656 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5657 vcpu->arch.guest_debug_dr7,
5658 vcpu->arch.eff_db);
5659
5660 if (dr6 != 0) {
6f43ed01 5661 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5662 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5663 kvm_run->debug.arch.exception = DB_VECTOR;
5664 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5665 *r = EMULATE_USER_EXIT;
5666 return true;
5667 }
5668 }
5669
4161a569
NA		 5670 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5671 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5672 unsigned long eip = kvm_get_linear_rip(vcpu);
5673 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5674 vcpu->arch.dr7,
5675 vcpu->arch.db);
5676
5677 if (dr6 != 0) {
5678 vcpu->arch.dr6 &= ~15;
6f43ed01 5679 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5680 kvm_queue_exception(vcpu, DB_VECTOR);
5681 *r = EMULATE_DONE;
5682 return true;
5683 }
5684 }
5685
5686 return false;
5687}
5688
51d8b661
AP		 5689int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5690 unsigned long cr2,
dc25e89e
AP		 5691 int emulation_type,
5692 void *insn,
5693 int insn_len)
bbd9b64e 5694{
95cb2295 5695 int r;
9d74191a 5696 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5697 bool writeback = true;
93c05d3e 5698 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5699
93c05d3e
XG		 5700 /*
5701 * Clear write_fault_to_shadow_pgtable here to ensure it is
5702 * never reused.
5703 */
5704 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5705 kvm_clear_exception_queue(vcpu);
8d7d8102 5706
571008da 5707 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5708 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5709
5710 /*
5711 * We will reenter on the same instruction since
5712 * we do not set complete_userspace_io. This does not
5713 * handle watchpoints yet, those would be handled in
5714 * the emulate_ops.
5715 */
5716 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5717 return r;
5718
9d74191a
TY		 5719 ctxt->interruptibility = 0;
5720 ctxt->have_exception = false;
e0ad0b47 5721 ctxt->exception.vector = -1;
9d74191a 5722 ctxt->perm_ok = false;
bbd9b64e 5723
b51e974f 5724 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5725
9d74191a 5726 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5727
e46479f8 5728 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5729 ++vcpu->stat.insn_emulation;
1d2887e2 5730 if (r != EMULATION_OK) {
4005996e
AK		 5731 if (emulation_type & EMULTYPE_TRAP_UD)
5732 return EMULATE_FAIL;
991eebf9
GN		 5733 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5734 emulation_type))
bbd9b64e 5735 return EMULATE_DONE;
6ea6e843
PB		 5736 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5737 return EMULATE_DONE;
6d77dbfc
GN		 5738 if (emulation_type & EMULTYPE_SKIP)
5739 return EMULATE_FAIL;
5740 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5741 }
5742 }
5743
ba8afb6b 5744 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5745 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5746 if (ctxt->eflags & X86_EFLAGS_RF)
5747 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5748 return EMULATE_DONE;
5749 }
5750
1cb3f3ae
XG		 5751 if (retry_instruction(ctxt, cr2, emulation_type))
5752 return EMULATE_DONE;
5753
7ae441ea 5754 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5755 changes registers values during IO operation */
7ae441ea
GN		 5756 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5757 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5758 emulator_invalidate_register_cache(ctxt);
7ae441ea 5759 }
4d2179e1 5760
5cd21917 5761restart:
0f89b207
TL		 5762 /* Save the faulting GPA (cr2) in the address field */
5763 ctxt->exception.address = cr2;
5764
9d74191a 5765 r = x86_emulate_insn(ctxt);
bbd9b64e 5766
775fde86
JR		 5767 if (r == EMULATION_INTERCEPTED)
5768 return EMULATE_DONE;
5769
d2ddd1c4 5770 if (r == EMULATION_FAILED) {
991eebf9
GN		 5771 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5772 emulation_type))
c3cd7ffa
GN		 5773 return EMULATE_DONE;
5774
6d77dbfc 5775 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5776 }
5777
9d74191a 5778 if (ctxt->have_exception) {
d2ddd1c4 5779 r = EMULATE_DONE;
ef54bcfe
PB		 5780 if (inject_emulated_exception(vcpu))
5781 return r;
d2ddd1c4 5782 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5783 if (!vcpu->arch.pio.in) {
5784 /* FIXME: return into emulator if single-stepping. */
3457e419 5785 vcpu->arch.pio.count = 0;
0912c977 5786 } else {
7ae441ea 5787 writeback = false;
716d51ab
GN		 5788 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5789 }
ac0a48c3 5790 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5791 } else if (vcpu->mmio_needed) {
5792 if (!vcpu->mmio_is_write)
5793 writeback = false;
ac0a48c3 5794 r = EMULATE_USER_EXIT;
716d51ab 5795 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5796 } else if (r == EMULATION_RESTART)
5cd21917 5797 goto restart;
d2ddd1c4
GN		 5798 else
5799 r = EMULATE_DONE;
f850e2e6 5800
7ae441ea 5801 if (writeback) {
6addfc42 5802 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5803 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5804 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5805 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5806 if (r == EMULATE_DONE &&
5807 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5808 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5809 if (!ctxt->have_exception ||
5810 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5811 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5812
5813 /*
5814 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5815 * do nothing, and it will be requested again as soon as
5816 * the shadow expires. But we still need to check here,
5817 * because POPF has no interrupt shadow.
5818 */
5819 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5820 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5821 } else
5822 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5823
5824 return r;
de7d789a 5825}
51d8b661 5826EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5827
cf8f70bf 5828int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5829{
cf8f70bf 5830 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5831 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5832 size, port, &val, 1);
cf8f70bf 5833 /* do not return to emulator after return from userspace */
7972995b 5834 vcpu->arch.pio.count = 0;
de7d789a
CO		 5835 return ret;
5836}
cf8f70bf 5837EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5838
8370c3d0
TL		 5839static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5840{
5841 unsigned long val;
5842
5843 /* We should only ever be called with arch.pio.count equal to 1 */
5844 BUG_ON(vcpu->arch.pio.count != 1);
5845
5846 /* For size less than 4 we merge, else we zero extend */
5847 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5848 : 0;
5849
5850 /*
5851 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5852 * the copy and tracing
5853 */
5854 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5855 vcpu->arch.pio.port, &val, 1);
5856 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5857
5858 return 1;
5859}
5860
5861int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5862{
5863 unsigned long val;
5864 int ret;
5865
5866 /* For size less than 4 we merge, else we zero extend */
5867 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5868
5869 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5870 &val, 1);
5871 if (ret) {
5872 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5873 return ret;
5874 }
5875
5876 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5877
5878 return 0;
5879}
5880EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5881
251a5fd6 5882static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5883{
0a3aee0d 5884 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5885 return 0;
8cfdc000
ZA		 5886}
5887
5888static void tsc_khz_changed(void *data)
c8076604 5889{
8cfdc000
ZA		 5890 struct cpufreq_freqs *freq = data;
5891 unsigned long khz = 0;
5892
5893 if (data)
5894 khz = freq->new;
5895 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5896 khz = cpufreq_quick_get(raw_smp_processor_id());
5897 if (!khz)
5898 khz = tsc_khz;
0a3aee0d 5899 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5900}
5901
c8076604
GH		 5902static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5903 void *data)
5904{
5905 struct cpufreq_freqs *freq = data;
5906 struct kvm *kvm;
5907 struct kvm_vcpu *vcpu;
5908 int i, send_ipi = 0;
5909
8cfdc000
ZA		 5910 /*
5911 * We allow guests to temporarily run on slowing clocks,
5912 * provided we notify them after, or to run on accelerating
5913 * clocks, provided we notify them before. Thus time never
5914 * goes backwards.
5915 *
5916 * However, we have a problem. We can't atomically update
5917 * the frequency of a given CPU from this function; it is
5918 * merely a notifier, which can be called from any CPU.
5919 * Changing the TSC frequency at arbitrary points in time
5920 * requires a recomputation of local variables related to
5921 * the TSC for each VCPU. We must flag these local variables
5922 * to be updated and be sure the update takes place with the
5923 * new frequency before any guests proceed.
5924 *
5925 * Unfortunately, the combination of hotplug CPU and frequency
5926 * change creates an intractable locking scenario; the order
5927 * of when these callouts happen is undefined with respect to
5928 * CPU hotplug, and they can race with each other. As such,
5929 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5930 * undefined; you can actually have a CPU frequency change take
5931 * place in between the computation of X and the setting of the
5932 * variable. To protect against this problem, all updates of
5933 * the per_cpu tsc_khz variable are done in an interrupt
5934 * protected IPI, and all callers wishing to update the value
5935 * must wait for a synchronous IPI to complete (which is trivial
5936 * if the caller is on the CPU already). This establishes the
5937 * necessary total order on variable updates.
5938 *
5939 * Note that because a guest time update may take place
5940 * anytime after the setting of the VCPU's request bit, the
5941 * correct TSC value must be set before the request. However,
5942 * to ensure the update actually makes it to any guest which
5943 * starts running in hardware virtualization between the set
5944 * and the acquisition of the spinlock, we must also ping the
5945 * CPU after setting the request bit.
5946 *
5947 */
5948
c8076604
GH		 5949 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5950 return 0;
5951 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5952 return 0;
8cfdc000
ZA		 5953
5954 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5955
2f303b74 5956 spin_lock(&kvm_lock);
c8076604 5957 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5958 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5959 if (vcpu->cpu != freq->cpu)
5960 continue;
c285545f 5961 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5962 if (vcpu->cpu != smp_processor_id())
8cfdc000 5963 send_ipi = 1;
c8076604
GH		 5964 }
5965 }
2f303b74 5966 spin_unlock(&kvm_lock);
c8076604
GH		 5967
5968 if (freq->old < freq->new && send_ipi) {
5969 /*
5970 * We upscale the frequency. Must make the guest
5971 * doesn't see old kvmclock values while running with
5972 * the new frequency, otherwise we risk the guest sees
5973 * time go backwards.
5974 *
5975 * In case we update the frequency for another cpu
5976 * (which might be in guest context) send an interrupt
5977 * to kick the cpu out of guest context. Next time
5978 * guest context is entered kvmclock will be updated,
5979 * so the guest will not see stale values.
5980 */
8cfdc000 5981 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5982 }
5983 return 0;
5984}
5985
5986static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5987 .notifier_call = kvmclock_cpufreq_notifier
5988};
5989
251a5fd6 5990static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5991{
251a5fd6
SAS		 5992 tsc_khz_changed(NULL);
5993 return 0;
8cfdc000
ZA		 5994}
5995
b820cc0c
ZA		 5996static void kvm_timer_init(void)
5997{
c285545f 5998 max_tsc_khz = tsc_khz;
460dd42e 5999
b820cc0c 6000 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6001#ifdef CONFIG_CPU_FREQ
6002 struct cpufreq_policy policy;
758f588d
BP		 6003 int cpu;
6004
c285545f 6005 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6006 cpu = get_cpu();
6007 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6008 if (policy.cpuinfo.max_freq)
6009 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6010 put_cpu();
c285545f 6011#endif
b820cc0c
ZA		 6012 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6013 CPUFREQ_TRANSITION_NOTIFIER);
6014 }
c285545f 6015 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6016
73c1b41e 6017 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6018 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6019}
6020
ff9d07a0
ZY		 6021static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6022
f5132b01 6023int kvm_is_in_guest(void)
ff9d07a0 6024{
086c9855 6025 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6026}
6027
6028static int kvm_is_user_mode(void)
6029{
6030 int user_mode = 3;
dcf46b94 6031
086c9855
AS		 6032 if (__this_cpu_read(current_vcpu))
6033 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6034
ff9d07a0
ZY		 6035 return user_mode != 0;
6036}
6037
6038static unsigned long kvm_get_guest_ip(void)
6039{
6040 unsigned long ip = 0;
dcf46b94 6041
086c9855
AS		 6042 if (__this_cpu_read(current_vcpu))
6043 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6044
ff9d07a0
ZY		 6045 return ip;
6046}
6047
6048static struct perf_guest_info_callbacks kvm_guest_cbs = {
6049 .is_in_guest = kvm_is_in_guest,
6050 .is_user_mode = kvm_is_user_mode,
6051 .get_guest_ip = kvm_get_guest_ip,
6052};
6053
6054void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6055{
086c9855 6056 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6057}
6058EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6059
6060void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6061{
086c9855 6062 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6063}
6064EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6065
ce88decf
XG		 6066static void kvm_set_mmio_spte_mask(void)
6067{
6068 u64 mask;
6069 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6070
6071 /*
6072 * Set the reserved bits and the present bit of an paging-structure
6073 * entry to generate page fault with PFER.RSV = 1.
6074 */
885032b9 6075 /* Mask the reserved physical address bits. */
d1431483 6076 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6077
885032b9 6078 /* Set the present bit. */
ce88decf
XG		 6079 mask |= 1ull;
6080
6081#ifdef CONFIG_X86_64
6082 /*
6083 * If reserved bit is not supported, clear the present bit to disable
6084 * mmio page fault.
6085 */
6086 if (maxphyaddr == 52)
6087 mask &= ~1ull;
6088#endif
6089
dcdca5fe 6090 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6091}
6092
16e8d74d
MT		 6093#ifdef CONFIG_X86_64
6094static void pvclock_gtod_update_fn(struct work_struct *work)
6095{
d828199e
MT		 6096 struct kvm *kvm;
6097
6098 struct kvm_vcpu *vcpu;
6099 int i;
6100
2f303b74 6101 spin_lock(&kvm_lock);
d828199e
MT		 6102 list_for_each_entry(kvm, &vm_list, vm_list)
6103 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6104 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6105 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6106 spin_unlock(&kvm_lock);
16e8d74d
MT		 6107}
6108
6109static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6110
6111/*
6112 * Notification about pvclock gtod data update.
6113 */
6114static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6115 void *priv)
6116{
6117 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6118 struct timekeeper *tk = priv;
6119
6120 update_pvclock_gtod(tk);
6121
6122 /* disable master clock if host does not trust, or does not
6123 * use, TSC clocksource
6124 */
6125 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6126 atomic_read(&kvm_guest_has_master_clock) != 0)
6127 queue_work(system_long_wq, &pvclock_gtod_work);
6128
6129 return 0;
6130}
6131
6132static struct notifier_block pvclock_gtod_notifier = {
6133 .notifier_call = pvclock_gtod_notify,
6134};
6135#endif
6136
f8c16bba 6137int kvm_arch_init(void *opaque)
043405e1 6138{
b820cc0c 6139 int r;
6b61edf7 6140 struct kvm_x86_ops *ops = opaque;
f8c16bba 6141
f8c16bba
ZX		 6142 if (kvm_x86_ops) {
6143 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6144 r = -EEXIST;
6145 goto out;
f8c16bba
ZX		 6146 }
6147
6148 if (!ops->cpu_has_kvm_support()) {
6149 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6150 r = -EOPNOTSUPP;
6151 goto out;
f8c16bba
ZX		 6152 }
6153 if (ops->disabled_by_bios()) {
1cdfde02 6154 printk(KERN_WARNING "kvm: disabled by bios\n");
56c6d28a
ZX		 6155 r = -EOPNOTSUPP;
6156 goto out;
f8c16bba
ZX		 6157 }
6158
013f6a5d
MT		 6159 r = -ENOMEM;
6160 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6161 if (!shared_msrs) {
6162 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6163 goto out;
6164 }
6165
97db56ce
AK		 6166 r = kvm_mmu_module_init();
6167 if (r)
013f6a5d 6168 goto out_free_percpu;
97db56ce 6169
ce88decf 6170 kvm_set_mmio_spte_mask();
97db56ce 6171
f8c16bba 6172 kvm_x86_ops = ops;
920c8377 6173
7b52345e 6174 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6175 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6176 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6177 kvm_timer_init();
c8076604 6178
ff9d07a0
ZY		 6179 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6180
d366bf7e 6181 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6182 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6183
c5cc421b 6184 kvm_lapic_init();
16e8d74d
MT		 6185#ifdef CONFIG_X86_64
6186 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6187#endif
6188
f8c16bba 6189 return 0;
56c6d28a 6190
013f6a5d
MT		 6191out_free_percpu:
6192 free_percpu(shared_msrs);
56c6d28a 6193out:
56c6d28a 6194 return r;
043405e1 6195}
8776e519 6196
f8c16bba
ZX		 6197void kvm_arch_exit(void)
6198{
cef84c30 6199 kvm_lapic_exit();
ff9d07a0
ZY		 6200 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6201
888d256e
JK		 6202 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6203 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6204 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6205 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6206#ifdef CONFIG_X86_64
6207 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6208#endif
f8c16bba 6209 kvm_x86_ops = NULL;
56c6d28a 6210 kvm_mmu_module_exit();
013f6a5d 6211 free_percpu(shared_msrs);
56c6d28a 6212}
f8c16bba 6213
5cb56059 6214int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6215{
6216 ++vcpu->stat.halt_exits;
35754c98 6217 if (lapic_in_kernel(vcpu)) {
a4535290 6218 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6219 return 1;
6220 } else {
6221 vcpu->run->exit_reason = KVM_EXIT_HLT;
6222 return 0;
6223 }
6224}
5cb56059
JS		 6225EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6226
6227int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6228{
6affcbed
KH		 6229 int ret = kvm_skip_emulated_instruction(vcpu);
6230 /*
6231 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6232 * KVM_EXIT_DEBUG here.
6233 */
6234 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6235}
8776e519
HB		 6236EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6237
8ef81a9a 6238#ifdef CONFIG_X86_64
55dd00a7
MT		 6239static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6240 unsigned long clock_type)
6241{
6242 struct kvm_clock_pairing clock_pairing;
6243 struct timespec ts;
80fbd89c 6244 u64 cycle;
55dd00a7
MT		 6245 int ret;
6246
6247 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6248 return -KVM_EOPNOTSUPP;
6249
6250 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6251 return -KVM_EOPNOTSUPP;
6252
6253 clock_pairing.sec = ts.tv_sec;
6254 clock_pairing.nsec = ts.tv_nsec;
6255 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6256 clock_pairing.flags = 0;
6257
6258 ret = 0;
6259 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6260 sizeof(struct kvm_clock_pairing)))
6261 ret = -KVM_EFAULT;
6262
6263 return ret;
6264}
8ef81a9a 6265#endif
55dd00a7 6266
6aef266c
SV		 6267/*
6268 * kvm_pv_kick_cpu_op: Kick a vcpu.
6269 *
6270 * @apicid - apicid of vcpu to be kicked.
6271 */
6272static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6273{
24d2166b 6274 struct kvm_lapic_irq lapic_irq;
6aef266c 6275
24d2166b
R		 6276 lapic_irq.shorthand = 0;
6277 lapic_irq.dest_mode = 0;
ebd28fcb 6278 lapic_irq.level = 0;
24d2166b 6279 lapic_irq.dest_id = apicid;
93bbf0b8 6280 lapic_irq.msi_redir_hint = false;
6aef266c 6281
24d2166b 6282 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6283 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6284}
6285
d62caabb
AS		 6286void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6287{
6288 vcpu->arch.apicv_active = false;
6289 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6290}
6291
8776e519
HB		 6292int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6293{
6294 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6295 int op_64_bit, r;
8776e519 6296
6affcbed 6297 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6298
55cd8e5a
GN		 6299 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6300 return kvm_hv_hypercall(vcpu);
6301
5fdbf976
MT		 6302 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6303 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6304 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6305 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6306 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6307
229456fc 6308 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6309
a449c7aa
NA		 6310 op_64_bit = is_64_bit_mode(vcpu);
6311 if (!op_64_bit) {
8776e519
HB		 6312 nr &= 0xFFFFFFFF;
6313 a0 &= 0xFFFFFFFF;
6314 a1 &= 0xFFFFFFFF;
6315 a2 &= 0xFFFFFFFF;
6316 a3 &= 0xFFFFFFFF;
6317 }
6318
07708c4a
JK		 6319 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6320 ret = -KVM_EPERM;
6321 goto out;
6322 }
6323
8776e519 6324 switch (nr) {
b93463aa
AK		 6325 case KVM_HC_VAPIC_POLL_IRQ:
6326 ret = 0;
6327 break;
6aef266c
SV		 6328 case KVM_HC_KICK_CPU:
6329 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6330 ret = 0;
6331 break;
8ef81a9a 6332#ifdef CONFIG_X86_64
55dd00a7
MT		 6333 case KVM_HC_CLOCK_PAIRING:
6334 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6335 break;
8ef81a9a 6336#endif
8776e519
HB		 6337 default:
6338 ret = -KVM_ENOSYS;
6339 break;
6340 }
07708c4a 6341out:
a449c7aa
NA		 6342 if (!op_64_bit)
6343 ret = (u32)ret;
5fdbf976 6344 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6345 ++vcpu->stat.hypercalls;
2f333bcb 6346 return r;
8776e519
HB		 6347}
6348EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6349
b6785def 6350static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6351{
d6aa1000 6352 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6353 char instruction[3];
5fdbf976 6354 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6355
8776e519 6356 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6357
ce2e852e
DV		 6358 return emulator_write_emulated(ctxt, rip, instruction, 3,
6359 &ctxt->exception);
8776e519
HB		 6360}
6361
851ba692 6362static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6363{
782d422b
MG		 6364 return vcpu->run->request_interrupt_window &&
6365 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6366}
6367
851ba692 6368static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6369{
851ba692
AK		 6370 struct kvm_run *kvm_run = vcpu->run;
6371
91586a3b 6372 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6373 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6374 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6375 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6376 kvm_run->ready_for_interrupt_injection =
6377 pic_in_kernel(vcpu->kvm) ||
782d422b 6378 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6379}
6380
95ba8273
GN		 6381static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6382{
6383 int max_irr, tpr;
6384
6385 if (!kvm_x86_ops->update_cr8_intercept)
6386 return;
6387
bce87cce 6388 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6389 return;
6390
d62caabb
AS		 6391 if (vcpu->arch.apicv_active)
6392 return;
6393
8db3baa2
GN		 6394 if (!vcpu->arch.apic->vapic_addr)
6395 max_irr = kvm_lapic_find_highest_irr(vcpu);
6396 else
6397 max_irr = -1;
95ba8273
GN		 6398
6399 if (max_irr != -1)
6400 max_irr >>= 4;
6401
6402 tpr = kvm_lapic_get_cr8(vcpu);
6403
6404 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6405}
6406
b6b8a145 6407static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6408{
b6b8a145
JK		 6409 int r;
6410
95ba8273 6411 /* try to reinject previous events if any */
664f8e26
WL		 6412 if (vcpu->arch.exception.injected) {
6413 kvm_x86_ops->queue_exception(vcpu);
6414 return 0;
6415 }
6416
6417 /*
6418 * Exceptions must be injected immediately, or the exception
6419 * frame will have the address of the NMI or interrupt handler.
6420 */
6421 if (!vcpu->arch.exception.pending) {
6422 if (vcpu->arch.nmi_injected) {
6423 kvm_x86_ops->set_nmi(vcpu);
6424 return 0;
6425 }
6426
6427 if (vcpu->arch.interrupt.pending) {
6428 kvm_x86_ops->set_irq(vcpu);
6429 return 0;
6430 }
6431 }
6432
6433 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6434 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6435 if (r != 0)
6436 return r;
6437 }
6438
6439 /* try to inject new event if pending */
b59bb7bd 6440 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6441 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6442 vcpu->arch.exception.has_error_code,
6443 vcpu->arch.exception.error_code);
d6e8c854 6444
664f8e26
WL		 6445 vcpu->arch.exception.pending = false;
6446 vcpu->arch.exception.injected = true;
6447
d6e8c854
NA		 6448 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6449 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6450 X86_EFLAGS_RF);
6451
6bdf0662
NA		 6452 if (vcpu->arch.exception.nr == DB_VECTOR &&
6453 (vcpu->arch.dr7 & DR7_GD)) {
6454 vcpu->arch.dr7 &= ~DR7_GD;
6455 kvm_update_dr7(vcpu);
6456 }
6457
cfcd20e5 6458 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6459 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6460 vcpu->arch.smi_pending = false;
ee2cd4b7 6461 enter_smm(vcpu);
c43203ca 6462 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6463 --vcpu->arch.nmi_pending;
6464 vcpu->arch.nmi_injected = true;
6465 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6466 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6467 /*
6468 * Because interrupts can be injected asynchronously, we are
6469 * calling check_nested_events again here to avoid a race condition.
6470 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6471 * proposal and current concerns. Perhaps we should be setting
6472 * KVM_REQ_EVENT only on certain events and not unconditionally?
6473 */
6474 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6475 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6476 if (r != 0)
6477 return r;
6478 }
95ba8273 6479 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6480 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6481 false);
6482 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6483 }
6484 }
ee2cd4b7 6485
b6b8a145 6486 return 0;
95ba8273
GN		 6487}
6488
7460fb4a
AK		 6489static void process_nmi(struct kvm_vcpu *vcpu)
6490{
6491 unsigned limit = 2;
6492
6493 /*
6494 * x86 is limited to one NMI running, and one NMI pending after it.
6495 * If an NMI is already in progress, limit further NMIs to just one.
6496 * Otherwise, allow two (and we'll inject the first one immediately).
6497 */
6498 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6499 limit = 1;
6500
6501 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6502 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6503 kvm_make_request(KVM_REQ_EVENT, vcpu);
6504}
6505
ee2cd4b7 6506static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6507{
6508 u32 flags = 0;
6509 flags |= seg->g << 23;
6510 flags |= seg->db << 22;
6511 flags |= seg->l << 21;
6512 flags |= seg->avl << 20;
6513 flags |= seg->present << 15;
6514 flags |= seg->dpl << 13;
6515 flags |= seg->s << 12;
6516 flags |= seg->type << 8;
6517 return flags;
6518}
6519
ee2cd4b7 6520static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6521{
6522 struct kvm_segment seg;
6523 int offset;
6524
6525 kvm_get_segment(vcpu, &seg, n);
6526 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6527
6528 if (n < 3)
6529 offset = 0x7f84 + n * 12;
6530 else
6531 offset = 0x7f2c + (n - 3) * 12;
6532
6533 put_smstate(u32, buf, offset + 8, seg.base);
6534 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6535 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6536}
6537
efbb288a 6538#ifdef CONFIG_X86_64
ee2cd4b7 6539static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6540{
6541 struct kvm_segment seg;
6542 int offset;
6543 u16 flags;
6544
6545 kvm_get_segment(vcpu, &seg, n);
6546 offset = 0x7e00 + n * 16;
6547
ee2cd4b7 6548 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6549 put_smstate(u16, buf, offset, seg.selector);
6550 put_smstate(u16, buf, offset + 2, flags);
6551 put_smstate(u32, buf, offset + 4, seg.limit);
6552 put_smstate(u64, buf, offset + 8, seg.base);
6553}
efbb288a 6554#endif
660a5d51 6555
ee2cd4b7 6556static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6557{
6558 struct desc_ptr dt;
6559 struct kvm_segment seg;
6560 unsigned long val;
6561 int i;
6562
6563 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6564 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6565 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6566 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6567
6568 for (i = 0; i < 8; i++)
6569 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6570
6571 kvm_get_dr(vcpu, 6, &val);
6572 put_smstate(u32, buf, 0x7fcc, (u32)val);
6573 kvm_get_dr(vcpu, 7, &val);
6574 put_smstate(u32, buf, 0x7fc8, (u32)val);
6575
6576 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6577 put_smstate(u32, buf, 0x7fc4, seg.selector);
6578 put_smstate(u32, buf, 0x7f64, seg.base);
6579 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6580 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6581
6582 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6583 put_smstate(u32, buf, 0x7fc0, seg.selector);
6584 put_smstate(u32, buf, 0x7f80, seg.base);
6585 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6586 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6587
6588 kvm_x86_ops->get_gdt(vcpu, &dt);
6589 put_smstate(u32, buf, 0x7f74, dt.address);
6590 put_smstate(u32, buf, 0x7f70, dt.size);
6591
6592 kvm_x86_ops->get_idt(vcpu, &dt);
6593 put_smstate(u32, buf, 0x7f58, dt.address);
6594 put_smstate(u32, buf, 0x7f54, dt.size);
6595
6596 for (i = 0; i < 6; i++)
ee2cd4b7 6597 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6598
6599 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6600
6601 /* revision id */
6602 put_smstate(u32, buf, 0x7efc, 0x00020000);
6603 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6604}
6605
ee2cd4b7 6606static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6607{
6608#ifdef CONFIG_X86_64
6609 struct desc_ptr dt;
6610 struct kvm_segment seg;
6611 unsigned long val;
6612 int i;
6613
6614 for (i = 0; i < 16; i++)
6615 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6616
6617 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6618 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6619
6620 kvm_get_dr(vcpu, 6, &val);
6621 put_smstate(u64, buf, 0x7f68, val);
6622 kvm_get_dr(vcpu, 7, &val);
6623 put_smstate(u64, buf, 0x7f60, val);
6624
6625 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6626 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6627 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6628
6629 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6630
6631 /* revision id */
6632 put_smstate(u32, buf, 0x7efc, 0x00020064);
6633
6634 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6635
6636 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6637 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6638 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6639 put_smstate(u32, buf, 0x7e94, seg.limit);
6640 put_smstate(u64, buf, 0x7e98, seg.base);
6641
6642 kvm_x86_ops->get_idt(vcpu, &dt);
6643 put_smstate(u32, buf, 0x7e84, dt.size);
6644 put_smstate(u64, buf, 0x7e88, dt.address);
6645
6646 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6647 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6648 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6649 put_smstate(u32, buf, 0x7e74, seg.limit);
6650 put_smstate(u64, buf, 0x7e78, seg.base);
6651
6652 kvm_x86_ops->get_gdt(vcpu, &dt);
6653 put_smstate(u32, buf, 0x7e64, dt.size);
6654 put_smstate(u64, buf, 0x7e68, dt.address);
6655
6656 for (i = 0; i < 6; i++)
ee2cd4b7 6657 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6658#else
6659 WARN_ON_ONCE(1);
6660#endif
6661}
6662
ee2cd4b7 6663static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6664{
660a5d51 6665 struct kvm_segment cs, ds;
18c3626e 6666 struct desc_ptr dt;
660a5d51
PB		 6667 char buf[512];
6668 u32 cr0;
6669
660a5d51 6670 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6671 memset(buf, 0, 512);
d6321d49 6672 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6673 enter_smm_save_state_64(vcpu, buf);
660a5d51 6674 else
ee2cd4b7 6675 enter_smm_save_state_32(vcpu, buf);
660a5d51 6676
0234bf88
LP		 6677 /*
6678 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6679 * vCPU state (e.g. leave guest mode) after we've saved the state into
6680 * the SMM state-save area.
6681 */
6682 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6683
6684 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6685 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6686
6687 if (kvm_x86_ops->get_nmi_mask(vcpu))
6688 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6689 else
6690 kvm_x86_ops->set_nmi_mask(vcpu, true);
6691
6692 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6693 kvm_rip_write(vcpu, 0x8000);
6694
6695 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6696 kvm_x86_ops->set_cr0(vcpu, cr0);
6697 vcpu->arch.cr0 = cr0;
6698
6699 kvm_x86_ops->set_cr4(vcpu, 0);
6700
18c3626e
PB		 6701 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6702 dt.address = dt.size = 0;
6703 kvm_x86_ops->set_idt(vcpu, &dt);
6704
660a5d51
PB		 6705 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6706
6707 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6708 cs.base = vcpu->arch.smbase;
6709
6710 ds.selector = 0;
6711 ds.base = 0;
6712
6713 cs.limit = ds.limit = 0xffffffff;
6714 cs.type = ds.type = 0x3;
6715 cs.dpl = ds.dpl = 0;
6716 cs.db = ds.db = 0;
6717 cs.s = ds.s = 1;
6718 cs.l = ds.l = 0;
6719 cs.g = ds.g = 1;
6720 cs.avl = ds.avl = 0;
6721 cs.present = ds.present = 1;
6722 cs.unusable = ds.unusable = 0;
6723 cs.padding = ds.padding = 0;
6724
6725 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6726 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6727 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6728 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6729 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6730 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6731
d6321d49 6732 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6733 kvm_x86_ops->set_efer(vcpu, 0);
6734
6735 kvm_update_cpuid(vcpu);
6736 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6737}
6738
ee2cd4b7 6739static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6740{
6741 vcpu->arch.smi_pending = true;
6742 kvm_make_request(KVM_REQ_EVENT, vcpu);
6743}
6744
2860c4b1
PB		 6745void kvm_make_scan_ioapic_request(struct kvm *kvm)
6746{
6747 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6748}
6749
3d81bc7e 6750static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6751{
5c919412
AS		 6752 u64 eoi_exit_bitmap[4];
6753
3d81bc7e
YZ		 6754 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6755 return;
c7c9c56c 6756
6308630b 6757 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6758
b053b2ae 6759 if (irqchip_split(vcpu->kvm))
6308630b 6760 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6761 else {
76dfafd5 6762 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6763 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6764 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6765 }
5c919412
AS		 6766 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6767 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6768 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6769}
6770
a70656b6
RK		 6771static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6772{
6773 ++vcpu->stat.tlb_flush;
6774 kvm_x86_ops->tlb_flush(vcpu);
6775}
6776
b1394e74
RK		 6777void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6778 unsigned long start, unsigned long end)
6779{
6780 unsigned long apic_address;
6781
6782 /*
6783 * The physical address of apic access page is stored in the VMCS.
6784 * Update it when it becomes invalid.
6785 */
6786 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6787 if (start <= apic_address && apic_address < end)
6788 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6789}
6790
4256f43f
TC		 6791void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6792{
c24ae0dc
TC		 6793 struct page *page = NULL;
6794
35754c98 6795 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6796 return;
6797
4256f43f
TC		 6798 if (!kvm_x86_ops->set_apic_access_page_addr)
6799 return;
6800
c24ae0dc 6801 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6802 if (is_error_page(page))
6803 return;
c24ae0dc
TC		 6804 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6805
6806 /*
6807 * Do not pin apic access page in memory, the MMU notifier
6808 * will call us again if it is migrated or swapped out.
6809 */
6810 put_page(page);
4256f43f
TC		 6811}
6812EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6813
9357d939 6814/*
362c698f 6815 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6816 * exiting to the userspace. Otherwise, the value will be returned to the
6817 * userspace.
6818 */
851ba692 6819static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6820{
6821 int r;
62a193ed
MG		 6822 bool req_int_win =
6823 dm_request_for_irq_injection(vcpu) &&
6824 kvm_cpu_accept_dm_intr(vcpu);
6825
730dca42 6826 bool req_immediate_exit = false;
b6c7a5dc 6827
2fa6e1e1 6828 if (kvm_request_pending(vcpu)) {
a8eeb04a 6829 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6830 kvm_mmu_unload(vcpu);
a8eeb04a 6831 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6832 __kvm_migrate_timers(vcpu);
d828199e
MT		 6833 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6834 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6835 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6836 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6837 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6838 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6839 if (unlikely(r))
6840 goto out;
6841 }
a8eeb04a 6842 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6843 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6844 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6845 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6846 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6847 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6848 r = 0;
6849 goto out;
6850 }
a8eeb04a 6851 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6852 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6853 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6854 r = 0;
6855 goto out;
6856 }
af585b92
GN		 6857 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6858 /* Page is swapped out. Do synthetic halt */
6859 vcpu->arch.apf.halted = true;
6860 r = 1;
6861 goto out;
6862 }
c9aaa895
GC		 6863 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6864 record_steal_time(vcpu);
64d60670
PB		 6865 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6866 process_smi(vcpu);
7460fb4a
AK		 6867 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6868 process_nmi(vcpu);
f5132b01 6869 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6870 kvm_pmu_handle_event(vcpu);
f5132b01 6871 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6872 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6873 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6874 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6875 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6876 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6877 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6878 vcpu->run->eoi.vector =
6879 vcpu->arch.pending_ioapic_eoi;
6880 r = 0;
6881 goto out;
6882 }
6883 }
3d81bc7e
YZ		 6884 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6885 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6886 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6887 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6888 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6889 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6890 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6891 r = 0;
6892 goto out;
6893 }
e516cebb
AS		 6894 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6895 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6896 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6897 r = 0;
6898 goto out;
6899 }
db397571
AS		 6900 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6901 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6902 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6903 r = 0;
6904 goto out;
6905 }
f3b138c5
AS		 6906
6907 /*
6908 * KVM_REQ_HV_STIMER has to be processed after
6909 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6910 * depend on the guest clock being up-to-date
6911 */
1f4b34f8
AS		 6912 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6913 kvm_hv_process_stimers(vcpu);
2f52d58c 6914 }
b93463aa 6915
b463a6f7 6916 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6917 ++vcpu->stat.req_event;
66450a21
JK		 6918 kvm_apic_accept_events(vcpu);
6919 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6920 r = 1;
6921 goto out;
6922 }
6923
b6b8a145
JK		 6924 if (inject_pending_event(vcpu, req_int_win) != 0)
6925 req_immediate_exit = true;
321c5658 6926 else {
cc3d967f 6927 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6928 *
cc3d967f
LP		 6929 * SMIs have three cases:
6930 * 1) They can be nested, and then there is nothing to
6931 * do here because RSM will cause a vmexit anyway.
6932 * 2) There is an ISA-specific reason why SMI cannot be
6933 * injected, and the moment when this changes can be
6934 * intercepted.
6935 * 3) Or the SMI can be pending because
6936 * inject_pending_event has completed the injection
6937 * of an IRQ or NMI from the previous vmexit, and
6938 * then we request an immediate exit to inject the
6939 * SMI.
c43203ca
PB		 6940 */
6941 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6942 if (!kvm_x86_ops->enable_smi_window(vcpu))
6943 req_immediate_exit = true;
321c5658
YS		 6944 if (vcpu->arch.nmi_pending)
6945 kvm_x86_ops->enable_nmi_window(vcpu);
6946 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6947 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6948 WARN_ON(vcpu->arch.exception.pending);
321c5658 6949 }
b463a6f7
AK		 6950
6951 if (kvm_lapic_enabled(vcpu)) {
6952 update_cr8_intercept(vcpu);
6953 kvm_lapic_sync_to_vapic(vcpu);
6954 }
6955 }
6956
d8368af8
AK		 6957 r = kvm_mmu_reload(vcpu);
6958 if (unlikely(r)) {
d905c069 6959 goto cancel_injection;
d8368af8
AK		 6960 }
6961
b6c7a5dc
HB		 6962 preempt_disable();
6963
6964 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 6965
6966 /*
6967 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6968 * IPI are then delayed after guest entry, which ensures that they
6969 * result in virtual interrupt delivery.
6970 */
6971 local_irq_disable();
6b7e2d09
XG		 6972 vcpu->mode = IN_GUEST_MODE;
6973
01b71917
MT		 6974 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6975
0f127d12 6976 /*
b95234c8 6977 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6978 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6979 *
6980 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6981 * pairs with the memory barrier implicit in pi_test_and_set_on
6982 * (see vmx_deliver_posted_interrupt).
6983 *
6984 * 3) This also orders the write to mode from any reads to the page
6985 * tables done while the VCPU is running. Please see the comment
6986 * in kvm_flush_remote_tlbs.
6b7e2d09 6987 */
01b71917 6988 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6989
b95234c8
PB		 6990 /*
6991 * This handles the case where a posted interrupt was
6992 * notified with kvm_vcpu_kick.
6993 */
6994 if (kvm_lapic_enabled(vcpu)) {
6995 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6996 kvm_x86_ops->sync_pir_to_irr(vcpu);
6997 }
32f88400 6998
2fa6e1e1 6999 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7000 || need_resched() || signal_pending(current)) {
6b7e2d09 7001 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7002 smp_wmb();
6c142801
AK		 7003 local_irq_enable();
7004 preempt_enable();
01b71917 7005 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7006 r = 1;
d905c069 7007 goto cancel_injection;
6c142801
AK		 7008 }
7009
fc5b7f3b
DM		 7010 kvm_load_guest_xcr0(vcpu);
7011
c43203ca
PB		 7012 if (req_immediate_exit) {
7013 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7014 smp_send_reschedule(vcpu->cpu);
c43203ca 7015 }
d6185f20 7016
8b89fe1f
PB		 7017 trace_kvm_entry(vcpu->vcpu_id);
7018 wait_lapic_expire(vcpu);
6edaa530 7019 guest_enter_irqoff();
b6c7a5dc 7020
42dbaa5a 7021 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7022 set_debugreg(0, 7);
7023 set_debugreg(vcpu->arch.eff_db[0], 0);
7024 set_debugreg(vcpu->arch.eff_db[1], 1);
7025 set_debugreg(vcpu->arch.eff_db[2], 2);
7026 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7027 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7028 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7029 }
b6c7a5dc 7030
851ba692 7031 kvm_x86_ops->run(vcpu);
b6c7a5dc 7032
c77fb5fe
PB		 7033 /*
7034 * Do this here before restoring debug registers on the host. And
7035 * since we do this before handling the vmexit, a DR access vmexit
7036 * can (a) read the correct value of the debug registers, (b) set
7037 * KVM_DEBUGREG_WONT_EXIT again.
7038 */
7039 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7040 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7041 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7042 kvm_update_dr0123(vcpu);
7043 kvm_update_dr6(vcpu);
7044 kvm_update_dr7(vcpu);
7045 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7046 }
7047
24f1e32c
FW		 7048 /*
7049 * If the guest has used debug registers, at least dr7
7050 * will be disabled while returning to the host.
7051 * If we don't have active breakpoints in the host, we don't
7052 * care about the messed up debug address registers. But if
7053 * we have some of them active, restore the old state.
7054 */
59d8eb53 7055 if (hw_breakpoint_active())
24f1e32c 7056 hw_breakpoint_restore();
42dbaa5a 7057
4ba76538 7058 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7059
6b7e2d09 7060 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7061 smp_wmb();
a547c6db 7062
fc5b7f3b
DM		 7063 kvm_put_guest_xcr0(vcpu);
7064
a547c6db 7065 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7066
7067 ++vcpu->stat.exits;
7068
f2485b3e 7069 guest_exit_irqoff();
b6c7a5dc 7070
f2485b3e 7071 local_irq_enable();
b6c7a5dc
HB		 7072 preempt_enable();
7073
f656ce01 7074 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7075
b6c7a5dc
HB		 7076 /*
7077 * Profile KVM exit RIPs:
7078 */
7079 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7080 unsigned long rip = kvm_rip_read(vcpu);
7081 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7082 }
7083
cc578287
ZA		 7084 if (unlikely(vcpu->arch.tsc_always_catchup))
7085 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7086
5cfb1d5a
MT		 7087 if (vcpu->arch.apic_attention)
7088 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7089
618232e2 7090 vcpu->arch.gpa_available = false;
851ba692 7091 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7092 return r;
7093
7094cancel_injection:
7095 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7096 if (unlikely(vcpu->arch.apic_attention))
7097 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7098out:
7099 return r;
7100}
b6c7a5dc 7101
362c698f
PB		 7102static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7103{
bf9f6ac8
FW		 7104 if (!kvm_arch_vcpu_runnable(vcpu) &&
7105 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7106 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7107 kvm_vcpu_block(vcpu);
7108 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7109
7110 if (kvm_x86_ops->post_block)
7111 kvm_x86_ops->post_block(vcpu);
7112
9c8fd1ba
PB		 7113 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7114 return 1;
7115 }
362c698f
PB		 7116
7117 kvm_apic_accept_events(vcpu);
7118 switch(vcpu->arch.mp_state) {
7119 case KVM_MP_STATE_HALTED:
7120 vcpu->arch.pv.pv_unhalted = false;
7121 vcpu->arch.mp_state =
7122 KVM_MP_STATE_RUNNABLE;
7123 case KVM_MP_STATE_RUNNABLE:
7124 vcpu->arch.apf.halted = false;
7125 break;
7126 case KVM_MP_STATE_INIT_RECEIVED:
7127 break;
7128 default:
7129 return -EINTR;
7130 break;
7131 }
7132 return 1;
7133}
09cec754 7134
5d9bc648
PB		 7135static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7136{
0ad3bed6
PB		 7137 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7138 kvm_x86_ops->check_nested_events(vcpu, false);
7139
5d9bc648
PB		 7140 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7141 !vcpu->arch.apf.halted);
7142}
7143
362c698f 7144static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7145{
7146 int r;
f656ce01 7147 struct kvm *kvm = vcpu->kvm;
d7690175 7148
f656ce01 7149 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7150
362c698f 7151 for (;;) {
58f800d5 7152 if (kvm_vcpu_running(vcpu)) {
851ba692 7153 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7154 } else {
362c698f 7155 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7156 }
7157
09cec754
GN		 7158 if (r <= 0)
7159 break;
7160
72875d8a 7161 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7162 if (kvm_cpu_has_pending_timer(vcpu))
7163 kvm_inject_pending_timer_irqs(vcpu);
7164
782d422b
MG		 7165 if (dm_request_for_irq_injection(vcpu) &&
7166 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7167 r = 0;
7168 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7169 ++vcpu->stat.request_irq_exits;
362c698f 7170 break;
09cec754 7171 }
af585b92
GN		 7172
7173 kvm_check_async_pf_completion(vcpu);
7174
09cec754
GN		 7175 if (signal_pending(current)) {
7176 r = -EINTR;
851ba692 7177 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7178 ++vcpu->stat.signal_exits;
362c698f 7179 break;
09cec754
GN		 7180 }
7181 if (need_resched()) {
f656ce01 7182 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7183 cond_resched();
f656ce01 7184 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7185 }
b6c7a5dc
HB		 7186 }
7187
f656ce01 7188 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7189
7190 return r;
7191}
7192
716d51ab
GN		 7193static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7194{
7195 int r;
7196 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7197 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7198 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7199 if (r != EMULATE_DONE)
7200 return 0;
7201 return 1;
7202}
7203
7204static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7205{
7206 BUG_ON(!vcpu->arch.pio.count);
7207
7208 return complete_emulated_io(vcpu);
7209}
7210
f78146b0
AK		 7211/*
7212 * Implements the following, as a state machine:
7213 *
7214 * read:
7215 * for each fragment
87da7e66
XG		 7216 * for each mmio piece in the fragment
7217 * write gpa, len
7218 * exit
7219 * copy data
f78146b0
AK		 7220 * execute insn
7221 *
7222 * write:
7223 * for each fragment
87da7e66
XG		 7224 * for each mmio piece in the fragment
7225 * write gpa, len
7226 * copy data
7227 * exit
f78146b0 7228 */
716d51ab 7229static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7230{
7231 struct kvm_run *run = vcpu->run;
f78146b0 7232 struct kvm_mmio_fragment *frag;
87da7e66 7233 unsigned len;
5287f194 7234
716d51ab 7235 BUG_ON(!vcpu->mmio_needed);
5287f194 7236
716d51ab 7237 /* Complete previous fragment */
87da7e66
XG		 7238 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7239 len = min(8u, frag->len);
716d51ab 7240 if (!vcpu->mmio_is_write)
87da7e66
XG		 7241 memcpy(frag->data, run->mmio.data, len);
7242
7243 if (frag->len <= 8) {
7244 /* Switch to the next fragment. */
7245 frag++;
7246 vcpu->mmio_cur_fragment++;
7247 } else {
7248 /* Go forward to the next mmio piece. */
7249 frag->data += len;
7250 frag->gpa += len;
7251 frag->len -= len;
7252 }
7253
a08d3b3b 7254 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7255 vcpu->mmio_needed = 0;
0912c977
PB		 7256
7257 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7258 if (vcpu->mmio_is_write)
716d51ab
GN		 7259 return 1;
7260 vcpu->mmio_read_completed = 1;
7261 return complete_emulated_io(vcpu);
7262 }
87da7e66 7263
716d51ab
GN		 7264 run->exit_reason = KVM_EXIT_MMIO;
7265 run->mmio.phys_addr = frag->gpa;
7266 if (vcpu->mmio_is_write)
87da7e66
XG		 7267 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7268 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7269 run->mmio.is_write = vcpu->mmio_is_write;
7270 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7271 return 0;
5287f194
AK		 7272}
7273
716d51ab 7274
b6c7a5dc
HB		 7275int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7276{
7277 int r;
b6c7a5dc 7278
20b7035c 7279 kvm_sigset_activate(vcpu);
ac9f6dc0 7280
5663d8f9
PX		 7281 kvm_load_guest_fpu(vcpu);
7282
a4535290 7283 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7284 if (kvm_run->immediate_exit) {
7285 r = -EINTR;
7286 goto out;
7287 }
b6c7a5dc 7288 kvm_vcpu_block(vcpu);
66450a21 7289 kvm_apic_accept_events(vcpu);
72875d8a 7290 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7291 r = -EAGAIN;
a0595000
JS		 7292 if (signal_pending(current)) {
7293 r = -EINTR;
7294 vcpu->run->exit_reason = KVM_EXIT_INTR;
7295 ++vcpu->stat.signal_exits;
7296 }
ac9f6dc0 7297 goto out;
b6c7a5dc
HB		 7298 }
7299
b6c7a5dc 7300 /* re-sync apic's tpr */
35754c98 7301 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7302 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7303 r = -EINVAL;
7304 goto out;
7305 }
7306 }
b6c7a5dc 7307
716d51ab
GN		 7308 if (unlikely(vcpu->arch.complete_userspace_io)) {
7309 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7310 vcpu->arch.complete_userspace_io = NULL;
7311 r = cui(vcpu);
7312 if (r <= 0)
5663d8f9 7313 goto out;
716d51ab
GN		 7314 } else
7315 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7316
460df4c1
PB		 7317 if (kvm_run->immediate_exit)
7318 r = -EINTR;
7319 else
7320 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7321
7322out:
5663d8f9 7323 kvm_put_guest_fpu(vcpu);
f1d86e46 7324 post_kvm_run_save(vcpu);
20b7035c 7325 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7326
b6c7a5dc
HB		 7327 return r;
7328}
7329
7330int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7331{
7ae441ea
GN		 7332 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7333 /*
7334 * We are here if userspace calls get_regs() in the middle of
7335 * instruction emulation. Registers state needs to be copied
4a969980 7336 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7337 * that usually, but some bad designed PV devices (vmware
7338 * backdoor interface) need this to work
7339 */
dd856efa 7340 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7341 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7342 }
5fdbf976
MT		 7343 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7344 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7345 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7346 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7347 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7348 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7349 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7350 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7351#ifdef CONFIG_X86_64
5fdbf976
MT		 7352 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7353 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7354 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7355 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7356 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7357 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7358 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7359 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7360#endif
7361
5fdbf976 7362 regs->rip = kvm_rip_read(vcpu);
91586a3b 7363 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7364
b6c7a5dc
HB		 7365 return 0;
7366}
7367
7368int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7369{
7ae441ea
GN		 7370 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7371 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7372
5fdbf976
MT		 7373 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7374 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7375 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7376 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7377 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7378 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7379 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7380 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7381#ifdef CONFIG_X86_64
5fdbf976
MT		 7382 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7383 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7384 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7385 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7386 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7387 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7388 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7389 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7390#endif
7391
5fdbf976 7392 kvm_rip_write(vcpu, regs->rip);
d73235d1 7393 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7394
b4f14abd
JK		 7395 vcpu->arch.exception.pending = false;
7396
3842d135
AK		 7397 kvm_make_request(KVM_REQ_EVENT, vcpu);
7398
b6c7a5dc
HB		 7399 return 0;
7400}
7401
b6c7a5dc
HB		 7402void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7403{
7404 struct kvm_segment cs;
7405
3e6e0aab 7406 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7407 *db = cs.db;
7408 *l = cs.l;
7409}
7410EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7411
7412int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7413 struct kvm_sregs *sregs)
7414{
89a27f4d 7415 struct desc_ptr dt;
b6c7a5dc 7416
3e6e0aab
GT		 7417 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7418 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7419 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7420 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7421 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7422 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7423
3e6e0aab
GT		 7424 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7425 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7426
7427 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7428 sregs->idt.limit = dt.size;
7429 sregs->idt.base = dt.address;
b6c7a5dc 7430 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7431 sregs->gdt.limit = dt.size;
7432 sregs->gdt.base = dt.address;
b6c7a5dc 7433
4d4ec087 7434 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7435 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7436 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7437 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7438 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7439 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7440 sregs->apic_base = kvm_get_apic_base(vcpu);
7441
923c61bb 7442 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7443
36752c9b 7444 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7445 set_bit(vcpu->arch.interrupt.nr,
7446 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7447
b6c7a5dc
HB		 7448 return 0;
7449}
7450
62d9f0db
MT		 7451int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7452 struct kvm_mp_state *mp_state)
7453{
66450a21 7454 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7455 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7456 vcpu->arch.pv.pv_unhalted)
7457 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7458 else
7459 mp_state->mp_state = vcpu->arch.mp_state;
7460
62d9f0db
MT		 7461 return 0;
7462}
7463
7464int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7465 struct kvm_mp_state *mp_state)
7466{
bce87cce 7467 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7468 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7469 return -EINVAL;
7470
28bf2888
DH		 7471 /* INITs are latched while in SMM */
7472 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7473 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7474 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7475 return -EINVAL;
7476
66450a21
JK		 7477 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7478 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7479 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7480 } else
7481 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7482 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7483 return 0;
7484}
7485
7f3d35fd
KW		 7486int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7487 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7488{
9d74191a 7489 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7490 int ret;
e01c2426 7491
8ec4722d 7492 init_emulate_ctxt(vcpu);
c697518a 7493
7f3d35fd 7494 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7495 has_error_code, error_code);
c697518a 7496
c697518a 7497 if (ret)
19d04437 7498 return EMULATE_FAIL;
37817f29 7499
9d74191a
TY		 7500 kvm_rip_write(vcpu, ctxt->eip);
7501 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7502 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7503 return EMULATE_DONE;
37817f29
IE		 7504}
7505EXPORT_SYMBOL_GPL(kvm_task_switch);
7506
f2981033
LT		 7507int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7508{
37b95951 7509 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7510 /*
7511 * When EFER.LME and CR0.PG are set, the processor is in
7512 * 64-bit mode (though maybe in a 32-bit code segment).
7513 * CR4.PAE and EFER.LMA must be set.
7514 */
37b95951 7515 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7516 || !(sregs->efer & EFER_LMA))
7517 return -EINVAL;
7518 } else {
7519 /*
7520 * Not in 64-bit mode: EFER.LMA is clear and the code
7521 * segment cannot be 64-bit.
7522 */
7523 if (sregs->efer & EFER_LMA || sregs->cs.l)
7524 return -EINVAL;
7525 }
7526
7527 return 0;
7528}
7529
b6c7a5dc
HB		 7530int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7531 struct kvm_sregs *sregs)
7532{
58cb628d 7533 struct msr_data apic_base_msr;
b6c7a5dc 7534 int mmu_reset_needed = 0;
63f42e02 7535 int pending_vec, max_bits, idx;
89a27f4d 7536 struct desc_ptr dt;
b6c7a5dc 7537
d6321d49
RK		 7538 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7539 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7540 return -EINVAL;
7541
f2981033
LT		 7542 if (kvm_valid_sregs(vcpu, sregs))
7543 return -EINVAL;
7544
d3802286
JM		 7545 apic_base_msr.data = sregs->apic_base;
7546 apic_base_msr.host_initiated = true;
7547 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7548 return -EINVAL;
7549
89a27f4d
GN		 7550 dt.size = sregs->idt.limit;
7551 dt.address = sregs->idt.base;
b6c7a5dc 7552 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7553 dt.size = sregs->gdt.limit;
7554 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7555 kvm_x86_ops->set_gdt(vcpu, &dt);
7556
ad312c7c 7557 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7558 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7559 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7560 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7561
2d3ad1f4 7562 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7563
f6801dff 7564 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7565 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7566
4d4ec087 7567 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7568 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7569 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7570
fc78f519 7571 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7572 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7573 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7574 kvm_update_cpuid(vcpu);
63f42e02
XG		 7575
7576 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7577 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7578 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7579 mmu_reset_needed = 1;
7580 }
63f42e02 7581 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7582
7583 if (mmu_reset_needed)
7584 kvm_mmu_reset_context(vcpu);
7585
a50abc3b 7586 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7587 pending_vec = find_first_bit(
7588 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7589 if (pending_vec < max_bits) {
66fd3f7f 7590 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7591 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7592 }
7593
3e6e0aab
GT		 7594 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7595 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7596 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7597 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7598 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7599 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7600
3e6e0aab
GT		 7601 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7602 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7603
5f0269f5
ME		 7604 update_cr8_intercept(vcpu);
7605
9c3e4aab 7606 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7607 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7608 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7609 !is_protmode(vcpu))
9c3e4aab
MT		 7610 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7611
3842d135
AK		 7612 kvm_make_request(KVM_REQ_EVENT, vcpu);
7613
b6c7a5dc
HB		 7614 return 0;
7615}
7616
d0bfb940
JK		 7617int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7618 struct kvm_guest_debug *dbg)
b6c7a5dc 7619{
355be0b9 7620 unsigned long rflags;
ae675ef0 7621 int i, r;
b6c7a5dc 7622
4f926bf2
JK		 7623 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7624 r = -EBUSY;
7625 if (vcpu->arch.exception.pending)
2122ff5e 7626 goto out;
4f926bf2
JK		 7627 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7628 kvm_queue_exception(vcpu, DB_VECTOR);
7629 else
7630 kvm_queue_exception(vcpu, BP_VECTOR);
7631 }
7632
91586a3b
JK		 7633 /*
7634 * Read rflags as long as potentially injected trace flags are still
7635 * filtered out.
7636 */
7637 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7638
7639 vcpu->guest_debug = dbg->control;
7640 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7641 vcpu->guest_debug = 0;
7642
7643 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7644 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7645 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7646 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7647 } else {
7648 for (i = 0; i < KVM_NR_DB_REGS; i++)
7649 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7650 }
c8639010 7651 kvm_update_dr7(vcpu);
ae675ef0 7652
f92653ee
JK		 7653 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7654 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7655 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7656
91586a3b
JK		 7657 /*
7658 * Trigger an rflags update that will inject or remove the trace
7659 * flags.
7660 */
7661 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7662
a96036b8 7663 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7664
4f926bf2 7665 r = 0;
d0bfb940 7666
2122ff5e 7667out:
b6c7a5dc
HB		 7668
7669 return r;
7670}
7671
8b006791
ZX		 7672/*
7673 * Translate a guest virtual address to a guest physical address.
7674 */
7675int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7676 struct kvm_translation *tr)
7677{
7678 unsigned long vaddr = tr->linear_address;
7679 gpa_t gpa;
f656ce01 7680 int idx;
8b006791 7681
f656ce01 7682 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7683 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7684 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7685 tr->physical_address = gpa;
7686 tr->valid = gpa != UNMAPPED_GVA;
7687 tr->writeable = 1;
7688 tr->usermode = 0;
8b006791
ZX		 7689
7690 return 0;
7691}
7692
d0752060
HB		 7693int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7694{
c47ada30 7695 struct fxregs_state *fxsave =
7366ed77 7696 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7697
d0752060
HB		 7698 memcpy(fpu->fpr, fxsave->st_space, 128);
7699 fpu->fcw = fxsave->cwd;
7700 fpu->fsw = fxsave->swd;
7701 fpu->ftwx = fxsave->twd;
7702 fpu->last_opcode = fxsave->fop;
7703 fpu->last_ip = fxsave->rip;
7704 fpu->last_dp = fxsave->rdp;
7705 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7706
d0752060
HB		 7707 return 0;
7708}
7709
7710int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7711{
c47ada30 7712 struct fxregs_state *fxsave =
7366ed77 7713 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7714
d0752060
HB		 7715 memcpy(fxsave->st_space, fpu->fpr, 128);
7716 fxsave->cwd = fpu->fcw;
7717 fxsave->swd = fpu->fsw;
7718 fxsave->twd = fpu->ftwx;
7719 fxsave->fop = fpu->last_opcode;
7720 fxsave->rip = fpu->last_ip;
7721 fxsave->rdp = fpu->last_dp;
7722 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7723
d0752060
HB		 7724 return 0;
7725}
7726
0ee6a517 7727static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7728{
bf935b0b 7729 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7730 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7731 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7732 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7733
2acf923e
DC		 7734 /*
7735 * Ensure guest xcr0 is valid for loading
7736 */
d91cab78 7737 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7738
ad312c7c 7739 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7740}
d0752060 7741
f775b13e 7742/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7743void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7744{
f775b13e
RR		 7745 preempt_disable();
7746 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7747 /* PKRU is separately restored in kvm_x86_ops->run. */
7748 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7749 ~XFEATURE_MASK_PKRU);
f775b13e 7750 preempt_enable();
0c04851c 7751 trace_kvm_fpu(1);
d0752060 7752}
d0752060 7753
f775b13e 7754/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 7755void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7756{
f775b13e 7757 preempt_disable();
4f836347 7758 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 7759 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7760 preempt_enable();
f096ed85 7761 ++vcpu->stat.fpu_reload;
0c04851c 7762 trace_kvm_fpu(0);
d0752060 7763}
e9b11c17
ZX		 7764
7765void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7766{
bd768e14
IY		 7767 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7768
12f9a48f 7769 kvmclock_reset(vcpu);
7f1ea208 7770
e9b11c17 7771 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7772 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7773}
7774
7775struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7776 unsigned int id)
7777{
c447e76b
LL		 7778 struct kvm_vcpu *vcpu;
7779
6755bae8
ZA		 7780 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7781 printk_once(KERN_WARNING
7782 "kvm: SMP vm created on host with unstable TSC; "
7783 "guest TSC will not be reliable\n");
c447e76b
LL		 7784
7785 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7786
c447e76b 7787 return vcpu;
26e5215f 7788}
e9b11c17 7789
26e5215f
AK		 7790int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7791{
7792 int r;
e9b11c17 7793
19efffa2 7794 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7795 r = vcpu_load(vcpu);
7796 if (r)
7797 return r;
d28bc9dd 7798 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7799 kvm_mmu_setup(vcpu);
e9b11c17 7800 vcpu_put(vcpu);
26e5215f 7801 return r;
e9b11c17
ZX		 7802}
7803
31928aa5 7804void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7805{
8fe8ab46 7806 struct msr_data msr;
332967a3 7807 struct kvm *kvm = vcpu->kvm;
42897d86 7808
d3457c87
RK		 7809 kvm_hv_vcpu_postcreate(vcpu);
7810
31928aa5
DD		 7811 if (vcpu_load(vcpu))
7812 return;
8fe8ab46
WA		 7813 msr.data = 0x0;
7814 msr.index = MSR_IA32_TSC;
7815 msr.host_initiated = true;
7816 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7817 vcpu_put(vcpu);
7818
630994b3
MT		 7819 if (!kvmclock_periodic_sync)
7820 return;
7821
332967a3
AJ		 7822 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7823 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7824}
7825
d40ccc62 7826void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7827{
9fc77441 7828 int r;
344d9588
GN		 7829 vcpu->arch.apf.msr_val = 0;
7830
9fc77441
MT		 7831 r = vcpu_load(vcpu);
7832 BUG_ON(r);
e9b11c17
ZX		 7833 kvm_mmu_unload(vcpu);
7834 vcpu_put(vcpu);
7835
7836 kvm_x86_ops->vcpu_free(vcpu);
7837}
7838
d28bc9dd 7839void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7840{
a04c389c
RK		 7841 kvm_lapic_reset(vcpu, init_event);
7842
e69fab5d
PB		 7843 vcpu->arch.hflags = 0;
7844
c43203ca 7845 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7846 atomic_set(&vcpu->arch.nmi_queued, 0);
7847 vcpu->arch.nmi_pending = 0;
448fa4a9 7848 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7849 kvm_clear_interrupt_queue(vcpu);
7850 kvm_clear_exception_queue(vcpu);
664f8e26 7851 vcpu->arch.exception.pending = false;
448fa4a9 7852
42dbaa5a 7853 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7854 kvm_update_dr0123(vcpu);
6f43ed01 7855 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7856 kvm_update_dr6(vcpu);
42dbaa5a 7857 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7858 kvm_update_dr7(vcpu);
42dbaa5a 7859
1119022c
NA		 7860 vcpu->arch.cr2 = 0;
7861
3842d135 7862 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7863 vcpu->arch.apf.msr_val = 0;
c9aaa895 7864 vcpu->arch.st.msr_val = 0;
3842d135 7865
12f9a48f
GC		 7866 kvmclock_reset(vcpu);
7867
af585b92
GN		 7868 kvm_clear_async_pf_completion_queue(vcpu);
7869 kvm_async_pf_hash_reset(vcpu);
7870 vcpu->arch.apf.halted = false;
3842d135 7871
a554d207
WL		 7872 if (kvm_mpx_supported()) {
7873 void *mpx_state_buffer;
7874
7875 /*
7876 * To avoid have the INIT path from kvm_apic_has_events() that be
7877 * called with loaded FPU and does not let userspace fix the state.
7878 */
f775b13e
RR		 7879 if (init_event)
7880 kvm_put_guest_fpu(vcpu);
a554d207
WL		 7881 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7882 XFEATURE_MASK_BNDREGS);
7883 if (mpx_state_buffer)
7884 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7885 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7886 XFEATURE_MASK_BNDCSR);
7887 if (mpx_state_buffer)
7888 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 7889 if (init_event)
7890 kvm_load_guest_fpu(vcpu);
a554d207
WL		 7891 }
7892
64d60670 7893 if (!init_event) {
d28bc9dd 7894 kvm_pmu_reset(vcpu);
64d60670 7895 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7896
7897 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7898 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7899
7900 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7901 }
f5132b01 7902
66f7b72e
JS		 7903 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7904 vcpu->arch.regs_avail = ~0;
7905 vcpu->arch.regs_dirty = ~0;
7906
a554d207
WL		 7907 vcpu->arch.ia32_xss = 0;
7908
d28bc9dd 7909 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7910}
7911
2b4a273b 7912void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7913{
7914 struct kvm_segment cs;
7915
7916 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7917 cs.selector = vector << 8;
7918 cs.base = vector << 12;
7919 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7920 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7921}
7922
13a34e06 7923int kvm_arch_hardware_enable(void)
e9b11c17 7924{
ca84d1a2
ZA		 7925 struct kvm *kvm;
7926 struct kvm_vcpu *vcpu;
7927 int i;
0dd6a6ed
ZA		 7928 int ret;
7929 u64 local_tsc;
7930 u64 max_tsc = 0;
7931 bool stable, backwards_tsc = false;
18863bdd
AK		 7932
7933 kvm_shared_msr_cpu_online();
13a34e06 7934 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7935 if (ret != 0)
7936 return ret;
7937
4ea1636b 7938 local_tsc = rdtsc();
0dd6a6ed
ZA		 7939 stable = !check_tsc_unstable();
7940 list_for_each_entry(kvm, &vm_list, vm_list) {
7941 kvm_for_each_vcpu(i, vcpu, kvm) {
7942 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7943 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7944 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7945 backwards_tsc = true;
7946 if (vcpu->arch.last_host_tsc > max_tsc)
7947 max_tsc = vcpu->arch.last_host_tsc;
7948 }
7949 }
7950 }
7951
7952 /*
7953 * Sometimes, even reliable TSCs go backwards. This happens on
7954 * platforms that reset TSC during suspend or hibernate actions, but
7955 * maintain synchronization. We must compensate. Fortunately, we can
7956 * detect that condition here, which happens early in CPU bringup,
7957 * before any KVM threads can be running. Unfortunately, we can't
7958 * bring the TSCs fully up to date with real time, as we aren't yet far
7959 * enough into CPU bringup that we know how much real time has actually
108b249c 7960 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7961 * variables that haven't been updated yet.
7962 *
7963 * So we simply find the maximum observed TSC above, then record the
7964 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7965 * the adjustment will be applied. Note that we accumulate
7966 * adjustments, in case multiple suspend cycles happen before some VCPU
7967 * gets a chance to run again. In the event that no KVM threads get a
7968 * chance to run, we will miss the entire elapsed period, as we'll have
7969 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7970 * loose cycle time. This isn't too big a deal, since the loss will be
7971 * uniform across all VCPUs (not to mention the scenario is extremely
7972 * unlikely). It is possible that a second hibernate recovery happens
7973 * much faster than a first, causing the observed TSC here to be
7974 * smaller; this would require additional padding adjustment, which is
7975 * why we set last_host_tsc to the local tsc observed here.
7976 *
7977 * N.B. - this code below runs only on platforms with reliable TSC,
7978 * as that is the only way backwards_tsc is set above. Also note
7979 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7980 * have the same delta_cyc adjustment applied if backwards_tsc
7981 * is detected. Note further, this adjustment is only done once,
7982 * as we reset last_host_tsc on all VCPUs to stop this from being
7983 * called multiple times (one for each physical CPU bringup).
7984 *
4a969980 7985 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7986 * will be compensated by the logic in vcpu_load, which sets the TSC to
7987 * catchup mode. This will catchup all VCPUs to real time, but cannot
7988 * guarantee that they stay in perfect synchronization.
7989 */
7990 if (backwards_tsc) {
7991 u64 delta_cyc = max_tsc - local_tsc;
7992 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7993 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7994 kvm_for_each_vcpu(i, vcpu, kvm) {
7995 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7996 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7997 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7998 }
7999
8000 /*
8001 * We have to disable TSC offset matching.. if you were
8002 * booting a VM while issuing an S4 host suspend....
8003 * you may have some problem. Solving this issue is
8004 * left as an exercise to the reader.
8005 */
8006 kvm->arch.last_tsc_nsec = 0;
8007 kvm->arch.last_tsc_write = 0;
8008 }
8009
8010 }
8011 return 0;
e9b11c17
ZX		 8012}
8013
13a34e06 8014void kvm_arch_hardware_disable(void)
e9b11c17 8015{
13a34e06
RK		 8016 kvm_x86_ops->hardware_disable();
8017 drop_user_return_notifiers();
e9b11c17
ZX		 8018}
8019
8020int kvm_arch_hardware_setup(void)
8021{
9e9c3fe4
NA		 8022 int r;
8023
8024 r = kvm_x86_ops->hardware_setup();
8025 if (r != 0)
8026 return r;
8027
35181e86
HZ		 8028 if (kvm_has_tsc_control) {
8029 /*
8030 * Make sure the user can only configure tsc_khz values that
8031 * fit into a signed integer.
8032 * A min value is not calculated needed because it will always
8033 * be 1 on all machines.
8034 */
8035 u64 max = min(0x7fffffffULL,
8036 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8037 kvm_max_guest_tsc_khz = max;
8038
ad721883 8039 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8040 }
ad721883 8041
9e9c3fe4
NA		 8042 kvm_init_msr_list();
8043 return 0;
e9b11c17
ZX		 8044}
8045
8046void kvm_arch_hardware_unsetup(void)
8047{
8048 kvm_x86_ops->hardware_unsetup();
8049}
8050
8051void kvm_arch_check_processor_compat(void *rtn)
8052{
8053 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8054}
8055
8056bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8057{
8058 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8059}
8060EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8061
8062bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8063{
8064 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8065}
8066
54e9818f 8067struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8068EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8069
e9b11c17
ZX		 8070int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8071{
8072 struct page *page;
e9b11c17
ZX		 8073 int r;
8074
b2a05fef 8075 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8076 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8077 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8078 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8079 else
a4535290 8080 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8081
8082 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8083 if (!page) {
8084 r = -ENOMEM;
8085 goto fail;
8086 }
ad312c7c 8087 vcpu->arch.pio_data = page_address(page);
e9b11c17 8088
cc578287 8089 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8090
e9b11c17
ZX		 8091 r = kvm_mmu_create(vcpu);
8092 if (r < 0)
8093 goto fail_free_pio_data;
8094
26de7988 8095 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8096 r = kvm_create_lapic(vcpu);
8097 if (r < 0)
8098 goto fail_mmu_destroy;
54e9818f
GN		 8099 } else
8100 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8101
890ca9ae
HY		 8102 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8103 GFP_KERNEL);
8104 if (!vcpu->arch.mce_banks) {
8105 r = -ENOMEM;
443c39bc 8106 goto fail_free_lapic;
890ca9ae
HY		 8107 }
8108 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8109
f1797359
WY		 8110 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8111 r = -ENOMEM;
f5f48ee1 8112 goto fail_free_mce_banks;
f1797359 8113 }
f5f48ee1 8114
0ee6a517 8115 fx_init(vcpu);
66f7b72e 8116
4344ee98 8117 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8118
5a4f55cd
EK		 8119 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8120
74545705
RK		 8121 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8122
af585b92 8123 kvm_async_pf_hash_reset(vcpu);
f5132b01 8124 kvm_pmu_init(vcpu);
af585b92 8125
1c1a9ce9 8126 vcpu->arch.pending_external_vector = -1;
de63ad4c 8127 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8128
5c919412
AS		 8129 kvm_hv_vcpu_init(vcpu);
8130
e9b11c17 8131 return 0;
0ee6a517 8132
f5f48ee1
SY		 8133fail_free_mce_banks:
8134 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8135fail_free_lapic:
8136 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8137fail_mmu_destroy:
8138 kvm_mmu_destroy(vcpu);
8139fail_free_pio_data:
ad312c7c 8140 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8141fail:
8142 return r;
8143}
8144
8145void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8146{
f656ce01
MT		 8147 int idx;
8148
1f4b34f8 8149 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8150 kvm_pmu_destroy(vcpu);
36cb93fd 8151 kfree(vcpu->arch.mce_banks);
e9b11c17 8152 kvm_free_lapic(vcpu);
f656ce01 8153 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8154 kvm_mmu_destroy(vcpu);
f656ce01 8155 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8156 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8157 if (!lapic_in_kernel(vcpu))
54e9818f 8158 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8159}
d19a9cd2 8160
e790d9ef
RK		 8161void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8162{
ae97a3b8 8163 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8164}
8165
e08b9637 8166int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8167{
e08b9637
CO		 8168 if (type)
8169 return -EINVAL;
8170
6ef768fa 8171 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8172 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8173 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8174 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8175 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8176
5550af4d
SY		 8177 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8178 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8179 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8180 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8181 &kvm->arch.irq_sources_bitmap);
5550af4d 8182
038f8c11 8183 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8184 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8185 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8186 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8187
108b249c 8188 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8189 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8190
7e44e449 8191 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8192 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8193
0eb05bf2 8194 kvm_page_track_init(kvm);
13d268ca 8195 kvm_mmu_init_vm(kvm);
0eb05bf2 8196
03543133
SS		 8197 if (kvm_x86_ops->vm_init)
8198 return kvm_x86_ops->vm_init(kvm);
8199
d89f5eff 8200 return 0;
d19a9cd2
ZX		 8201}
8202
8203static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8204{
9fc77441
MT		 8205 int r;
8206 r = vcpu_load(vcpu);
8207 BUG_ON(r);
d19a9cd2
ZX		 8208 kvm_mmu_unload(vcpu);
8209 vcpu_put(vcpu);
8210}
8211
8212static void kvm_free_vcpus(struct kvm *kvm)
8213{
8214 unsigned int i;
988a2cae 8215 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8216
8217 /*
8218 * Unpin any mmu pages first.
8219 */
af585b92
GN		 8220 kvm_for_each_vcpu(i, vcpu, kvm) {
8221 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8222 kvm_unload_vcpu_mmu(vcpu);
af585b92 8223 }
988a2cae
GN		 8224 kvm_for_each_vcpu(i, vcpu, kvm)
8225 kvm_arch_vcpu_free(vcpu);
8226
8227 mutex_lock(&kvm->lock);
8228 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8229 kvm->vcpus[i] = NULL;
d19a9cd2 8230
988a2cae
GN		 8231 atomic_set(&kvm->online_vcpus, 0);
8232 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8233}
8234
ad8ba2cd
SY		 8235void kvm_arch_sync_events(struct kvm *kvm)
8236{
332967a3 8237 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8238 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8239 kvm_free_pit(kvm);
ad8ba2cd
SY		 8240}
8241
1d8007bd 8242int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8243{
8244 int i, r;
25188b99 8245 unsigned long hva;
f0d648bd
PB		 8246 struct kvm_memslots *slots = kvm_memslots(kvm);
8247 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8248
8249 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8250 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8251 return -EINVAL;
9da0e4d5 8252
f0d648bd
PB		 8253 slot = id_to_memslot(slots, id);
8254 if (size) {
b21629da 8255 if (slot->npages)
f0d648bd
PB		 8256 return -EEXIST;
8257
8258 /*
8259 * MAP_SHARED to prevent internal slot pages from being moved
8260 * by fork()/COW.
8261 */
8262 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8263 MAP_SHARED | MAP_ANONYMOUS, 0);
8264 if (IS_ERR((void *)hva))
8265 return PTR_ERR((void *)hva);
8266 } else {
8267 if (!slot->npages)
8268 return 0;
8269
8270 hva = 0;
8271 }
8272
8273 old = *slot;
9da0e4d5 8274 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8275 struct kvm_userspace_memory_region m;
9da0e4d5 8276
1d8007bd
PB		 8277 m.slot = id | (i << 16);
8278 m.flags = 0;
8279 m.guest_phys_addr = gpa;
f0d648bd 8280 m.userspace_addr = hva;
1d8007bd 8281 m.memory_size = size;
9da0e4d5
PB		 8282 r = __kvm_set_memory_region(kvm, &m);
8283 if (r < 0)
8284 return r;
8285 }
8286
55a4a47b
EB		 8287 if (!size)
8288 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8289
9da0e4d5
PB		 8290 return 0;
8291}
8292EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8293
1d8007bd 8294int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8295{
8296 int r;
8297
8298 mutex_lock(&kvm->slots_lock);
1d8007bd 8299 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8300 mutex_unlock(&kvm->slots_lock);
8301
8302 return r;
8303}
8304EXPORT_SYMBOL_GPL(x86_set_memory_region);
8305
d19a9cd2
ZX		 8306void kvm_arch_destroy_vm(struct kvm *kvm)
8307{
27469d29
AH		 8308 if (current->mm == kvm->mm) {
8309 /*
8310 * Free memory regions allocated on behalf of userspace,
8311 * unless the the memory map has changed due to process exit
8312 * or fd copying.
8313 */
1d8007bd
PB		 8314 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8315 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8316 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8317 }
03543133
SS		 8318 if (kvm_x86_ops->vm_destroy)
8319 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8320 kvm_pic_destroy(kvm);
8321 kvm_ioapic_destroy(kvm);
d19a9cd2 8322 kvm_free_vcpus(kvm);
af1bae54 8323 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8324 kvm_mmu_uninit_vm(kvm);
2beb6dad 8325 kvm_page_track_cleanup(kvm);
d19a9cd2 8326}
0de10343 8327
5587027c 8328void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8329 struct kvm_memory_slot *dont)
8330{
8331 int i;
8332
d89cc617
TY		 8333 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8334 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8335 kvfree(free->arch.rmap[i]);
d89cc617 8336 free->arch.rmap[i] = NULL;
77d11309 8337 }
d89cc617
TY		 8338 if (i == 0)
8339 continue;
8340
8341 if (!dont || free->arch.lpage_info[i - 1] !=
8342 dont->arch.lpage_info[i - 1]) {
548ef284 8343 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8344 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8345 }
8346 }
21ebbeda
XG		 8347
8348 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8349}
8350
5587027c
AK		 8351int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8352 unsigned long npages)
db3fe4eb
TY		 8353{
8354 int i;
8355
d89cc617 8356 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8357 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8358 unsigned long ugfn;
8359 int lpages;
d89cc617 8360 int level = i + 1;
db3fe4eb
TY		 8361
8362 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8363 slot->base_gfn, level) + 1;
8364
d89cc617 8365 slot->arch.rmap[i] =
a7c3e901 8366 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8367 if (!slot->arch.rmap[i])
77d11309 8368 goto out_free;
d89cc617
TY		 8369 if (i == 0)
8370 continue;
77d11309 8371
a7c3e901 8372 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8373 if (!linfo)
db3fe4eb
TY		 8374 goto out_free;
8375
92f94f1e
XG		 8376 slot->arch.lpage_info[i - 1] = linfo;
8377
db3fe4eb 8378 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8379 linfo[0].disallow_lpage = 1;
db3fe4eb 8380 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8381 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8382 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8383 /*
8384 * If the gfn and userspace address are not aligned wrt each
8385 * other, or if explicitly asked to, disable large page
8386 * support for this slot
8387 */
8388 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8389 !kvm_largepages_enabled()) {
8390 unsigned long j;
8391
8392 for (j = 0; j < lpages; ++j)
92f94f1e 8393 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8394 }
8395 }
8396
21ebbeda
XG		 8397 if (kvm_page_track_create_memslot(slot, npages))
8398 goto out_free;
8399
db3fe4eb
TY		 8400 return 0;
8401
8402out_free:
d89cc617 8403 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8404 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8405 slot->arch.rmap[i] = NULL;
8406 if (i == 0)
8407 continue;
8408
548ef284 8409 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8410 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8411 }
8412 return -ENOMEM;
8413}
8414
15f46015 8415void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8416{
e6dff7d1
TY		 8417 /*
8418 * memslots->generation has been incremented.
8419 * mmio generation may have reached its maximum value.
8420 */
54bf36aa 8421 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8422}
8423
f7784b8e
MT		 8424int kvm_arch_prepare_memory_region(struct kvm *kvm,
8425 struct kvm_memory_slot *memslot,
09170a49 8426 const struct kvm_userspace_memory_region *mem,
7b6195a9 8427 enum kvm_mr_change change)
0de10343 8428{
f7784b8e
MT		 8429 return 0;
8430}
8431
88178fd4
KH		 8432static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8433 struct kvm_memory_slot *new)
8434{
8435 /* Still write protect RO slot */
8436 if (new->flags & KVM_MEM_READONLY) {
8437 kvm_mmu_slot_remove_write_access(kvm, new);
8438 return;
8439 }
8440
8441 /*
8442 * Call kvm_x86_ops dirty logging hooks when they are valid.
8443 *
8444 * kvm_x86_ops->slot_disable_log_dirty is called when:
8445 *
8446 * - KVM_MR_CREATE with dirty logging is disabled
8447 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8448 *
8449 * The reason is, in case of PML, we need to set D-bit for any slots
8450 * with dirty logging disabled in order to eliminate unnecessary GPA
8451 * logging in PML buffer (and potential PML buffer full VMEXT). This
8452 * guarantees leaving PML enabled during guest's lifetime won't have
8453 * any additonal overhead from PML when guest is running with dirty
8454 * logging disabled for memory slots.
8455 *
8456 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8457 * to dirty logging mode.
8458 *
8459 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8460 *
8461 * In case of write protect:
8462 *
8463 * Write protect all pages for dirty logging.
8464 *
8465 * All the sptes including the large sptes which point to this
8466 * slot are set to readonly. We can not create any new large
8467 * spte on this slot until the end of the logging.
8468 *
8469 * See the comments in fast_page_fault().
8470 */
8471 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8472 if (kvm_x86_ops->slot_enable_log_dirty)
8473 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8474 else
8475 kvm_mmu_slot_remove_write_access(kvm, new);
8476 } else {
8477 if (kvm_x86_ops->slot_disable_log_dirty)
8478 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8479 }
8480}
8481
f7784b8e 8482void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8483 const struct kvm_userspace_memory_region *mem,
8482644a 8484 const struct kvm_memory_slot *old,
f36f3f28 8485 const struct kvm_memory_slot *new,
8482644a 8486 enum kvm_mr_change change)
f7784b8e 8487{
8482644a 8488 int nr_mmu_pages = 0;
f7784b8e 8489
48c0e4e9
XG		 8490 if (!kvm->arch.n_requested_mmu_pages)
8491 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8492
48c0e4e9 8493 if (nr_mmu_pages)
0de10343 8494 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8495
3ea3b7fa
WL		 8496 /*
8497 * Dirty logging tracks sptes in 4k granularity, meaning that large
8498 * sptes have to be split. If live migration is successful, the guest
8499 * in the source machine will be destroyed and large sptes will be
8500 * created in the destination. However, if the guest continues to run
8501 * in the source machine (for example if live migration fails), small
8502 * sptes will remain around and cause bad performance.
8503 *
8504 * Scan sptes if dirty logging has been stopped, dropping those
8505 * which can be collapsed into a single large-page spte. Later
8506 * page faults will create the large-page sptes.
8507 */
8508 if ((change != KVM_MR_DELETE) &&
8509 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8510 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8511 kvm_mmu_zap_collapsible_sptes(kvm, new);
8512
c972f3b1 8513 /*
88178fd4 8514 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8515 *
88178fd4
KH		 8516 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8517 * been zapped so no dirty logging staff is needed for old slot. For
8518 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8519 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8520 *
8521 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8522 */
88178fd4 8523 if (change != KVM_MR_DELETE)
f36f3f28 8524 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8525}
1d737c8a 8526
2df72e9b 8527void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8528{
6ca18b69 8529 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8530}
8531
2df72e9b
MT		 8532void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8533 struct kvm_memory_slot *slot)
8534{
ae7cd873 8535 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8536}
8537
5d9bc648
PB		 8538static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8539{
8540 if (!list_empty_careful(&vcpu->async_pf.done))
8541 return true;
8542
8543 if (kvm_apic_has_events(vcpu))
8544 return true;
8545
8546 if (vcpu->arch.pv.pv_unhalted)
8547 return true;
8548
a5f01f8e
WL		 8549 if (vcpu->arch.exception.pending)
8550 return true;
8551
47a66eed
Z		 8552 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8553 (vcpu->arch.nmi_pending &&
8554 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8555 return true;
8556
47a66eed
Z		 8557 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8558 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8559 return true;
8560
5d9bc648
PB		 8561 if (kvm_arch_interrupt_allowed(vcpu) &&
8562 kvm_cpu_has_interrupt(vcpu))
8563 return true;
8564
1f4b34f8
AS		 8565 if (kvm_hv_has_stimer_pending(vcpu))
8566 return true;
8567
5d9bc648
PB		 8568 return false;
8569}
8570
1d737c8a
ZX		 8571int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8572{
5d9bc648 8573 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8574}
5736199a 8575
199b5763
LM		 8576bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8577{
de63ad4c 8578 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8579}
8580
b6d33834 8581int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8582{
b6d33834 8583 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8584}
78646121
GN		 8585
8586int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8587{
8588 return kvm_x86_ops->interrupt_allowed(vcpu);
8589}
229456fc 8590
82b32774 8591unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8592{
82b32774
NA		 8593 if (is_64_bit_mode(vcpu))
8594 return kvm_rip_read(vcpu);
8595 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8596 kvm_rip_read(vcpu));
8597}
8598EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8599
82b32774
NA		 8600bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8601{
8602 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8603}
8604EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8605
94fe45da
JK		 8606unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8607{
8608 unsigned long rflags;
8609
8610 rflags = kvm_x86_ops->get_rflags(vcpu);
8611 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8612 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8613 return rflags;
8614}
8615EXPORT_SYMBOL_GPL(kvm_get_rflags);
8616
6addfc42 8617static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8618{
8619 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8620 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8621 rflags |= X86_EFLAGS_TF;
94fe45da 8622 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8623}
8624
8625void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8626{
8627 __kvm_set_rflags(vcpu, rflags);
3842d135 8628 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8629}
8630EXPORT_SYMBOL_GPL(kvm_set_rflags);
8631
56028d08
GN		 8632void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8633{
8634 int r;
8635
fb67e14f 8636 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8637 work->wakeup_all)
56028d08
GN		 8638 return;
8639
8640 r = kvm_mmu_reload(vcpu);
8641 if (unlikely(r))
8642 return;
8643
fb67e14f
XG		 8644 if (!vcpu->arch.mmu.direct_map &&
8645 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8646 return;
8647
56028d08
GN		 8648 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8649}
8650
af585b92
GN		 8651static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8652{
8653 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8654}
8655
8656static inline u32 kvm_async_pf_next_probe(u32 key)
8657{
8658 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8659}
8660
8661static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8662{
8663 u32 key = kvm_async_pf_hash_fn(gfn);
8664
8665 while (vcpu->arch.apf.gfns[key] != ~0)
8666 key = kvm_async_pf_next_probe(key);
8667
8668 vcpu->arch.apf.gfns[key] = gfn;
8669}
8670
8671static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8672{
8673 int i;
8674 u32 key = kvm_async_pf_hash_fn(gfn);
8675
8676 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8677 (vcpu->arch.apf.gfns[key] != gfn &&
8678 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8679 key = kvm_async_pf_next_probe(key);
8680
8681 return key;
8682}
8683
8684bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8685{
8686 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8687}
8688
8689static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8690{
8691 u32 i, j, k;
8692
8693 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8694 while (true) {
8695 vcpu->arch.apf.gfns[i] = ~0;
8696 do {
8697 j = kvm_async_pf_next_probe(j);
8698 if (vcpu->arch.apf.gfns[j] == ~0)
8699 return;
8700 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8701 /*
8702 * k lies cyclically in ]i,j]
8703 * | i.k.j |
8704 * |....j i.k.| or |.k..j i...|
8705 */
8706 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8707 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8708 i = j;
8709 }
8710}
8711
7c90705b
GN		 8712static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8713{
4e335d9e
PB		 8714
8715 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8716 sizeof(val));
7c90705b
GN		 8717}
8718
9a6e7c39
WL		 8719static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8720{
8721
8722 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8723 sizeof(u32));
8724}
8725
af585b92
GN		 8726void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8727 struct kvm_async_pf *work)
8728{
6389ee94
AK		 8729 struct x86_exception fault;
8730
7c90705b 8731 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8732 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8733
8734 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8735 (vcpu->arch.apf.send_user_only &&
8736 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8737 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8738 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8739 fault.vector = PF_VECTOR;
8740 fault.error_code_valid = true;
8741 fault.error_code = 0;
8742 fault.nested_page_fault = false;
8743 fault.address = work->arch.token;
adfe20fb 8744 fault.async_page_fault = true;
6389ee94 8745 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8746 }
af585b92
GN		 8747}
8748
8749void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8750 struct kvm_async_pf *work)
8751{
6389ee94 8752 struct x86_exception fault;
9a6e7c39 8753 u32 val;
6389ee94 8754
f2e10669 8755 if (work->wakeup_all)
7c90705b
GN		 8756 work->arch.token = ~0; /* broadcast wakeup */
8757 else
8758 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8759 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8760
9a6e7c39
WL		 8761 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8762 !apf_get_user(vcpu, &val)) {
8763 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8764 vcpu->arch.exception.pending &&
8765 vcpu->arch.exception.nr == PF_VECTOR &&
8766 !apf_put_user(vcpu, 0)) {
8767 vcpu->arch.exception.injected = false;
8768 vcpu->arch.exception.pending = false;
8769 vcpu->arch.exception.nr = 0;
8770 vcpu->arch.exception.has_error_code = false;
8771 vcpu->arch.exception.error_code = 0;
8772 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8773 fault.vector = PF_VECTOR;
8774 fault.error_code_valid = true;
8775 fault.error_code = 0;
8776 fault.nested_page_fault = false;
8777 fault.address = work->arch.token;
8778 fault.async_page_fault = true;
8779 kvm_inject_page_fault(vcpu, &fault);
8780 }
7c90705b 8781 }
e6d53e3b 8782 vcpu->arch.apf.halted = false;
a4fa1635 8783 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8784}
8785
8786bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8787{
8788 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8789 return true;
8790 else
9bc1f09f 8791 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8792}
8793
5544eb9b
PB		 8794void kvm_arch_start_assignment(struct kvm *kvm)
8795{
8796 atomic_inc(&kvm->arch.assigned_device_count);
8797}
8798EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8799
8800void kvm_arch_end_assignment(struct kvm *kvm)
8801{
8802 atomic_dec(&kvm->arch.assigned_device_count);
8803}
8804EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8805
8806bool kvm_arch_has_assigned_device(struct kvm *kvm)
8807{
8808 return atomic_read(&kvm->arch.assigned_device_count);
8809}
8810EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8811
e0f0bbc5
AW		 8812void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8813{
8814 atomic_inc(&kvm->arch.noncoherent_dma_count);
8815}
8816EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8817
8818void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8819{
8820 atomic_dec(&kvm->arch.noncoherent_dma_count);
8821}
8822EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8823
8824bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8825{
8826 return atomic_read(&kvm->arch.noncoherent_dma_count);
8827}
8828EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8829
14717e20
AW		 8830bool kvm_arch_has_irq_bypass(void)
8831{
8832 return kvm_x86_ops->update_pi_irte != NULL;
8833}
8834
87276880
FW		 8835int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8836 struct irq_bypass_producer *prod)
8837{
8838 struct kvm_kernel_irqfd *irqfd =
8839 container_of(cons, struct kvm_kernel_irqfd, consumer);
8840
14717e20 8841 irqfd->producer = prod;
87276880 8842
14717e20
AW		 8843 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8844 prod->irq, irqfd->gsi, 1);
87276880
FW		 8845}
8846
8847void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8848 struct irq_bypass_producer *prod)
8849{
8850 int ret;
8851 struct kvm_kernel_irqfd *irqfd =
8852 container_of(cons, struct kvm_kernel_irqfd, consumer);
8853
87276880
FW		 8854 WARN_ON(irqfd->producer != prod);
8855 irqfd->producer = NULL;
8856
8857 /*
8858 * When producer of consumer is unregistered, we change back to
8859 * remapped mode, so we can re-use the current implementation
bb3541f1 8860 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8861 * int this case doesn't want to receive the interrupts.
8862 */
8863 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8864 if (ret)
8865 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8866 " fails: %d\n", irqfd->consumer.token, ret);
8867}
8868
8869int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8870 uint32_t guest_irq, bool set)
8871{
8872 if (!kvm_x86_ops->update_pi_irte)
8873 return -EINVAL;
8874
8875 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8876}
8877
52004014
FW		 8878bool kvm_vector_hashing_enabled(void)
8879{
8880 return vector_hashing;
8881}
8882EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8883
229456fc 8884EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8885EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8886EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8887EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8888EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8889EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8890EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8891EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8892EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8893EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8894EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8895EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8896EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8897EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8898EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8899EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8900EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8901EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8902EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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