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KVM: MMU: Expose the LA57 feature to VM.
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
18863bdd
AK		 137#define KVM_NR_SHARED_MSRS 16
138
139struct kvm_shared_msrs_global {
140 int nr;
2bf78fa7 141 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144struct kvm_shared_msrs {
145 struct user_return_notifier urn;
146 bool registered;
2bf78fa7
SY		 147 struct kvm_shared_msr_values {
148 u64 host;
149 u64 curr;
150 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 151};
152
153static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 154static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 155
417bc304 156struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 157 { "pf_fixed", VCPU_STAT(pf_fixed) },
158 { "pf_guest", VCPU_STAT(pf_guest) },
159 { "tlb_flush", VCPU_STAT(tlb_flush) },
160 { "invlpg", VCPU_STAT(invlpg) },
161 { "exits", VCPU_STAT(exits) },
162 { "io_exits", VCPU_STAT(io_exits) },
163 { "mmio_exits", VCPU_STAT(mmio_exits) },
164 { "signal_exits", VCPU_STAT(signal_exits) },
165 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 166 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 167 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 168 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 169 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 170 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 171 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 172 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 173 { "request_irq", VCPU_STAT(request_irq_exits) },
174 { "irq_exits", VCPU_STAT(irq_exits) },
175 { "host_state_reload", VCPU_STAT(host_state_reload) },
176 { "efer_reload", VCPU_STAT(efer_reload) },
177 { "fpu_reload", VCPU_STAT(fpu_reload) },
178 { "insn_emulation", VCPU_STAT(insn_emulation) },
179 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 180 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 181 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 182 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 195 { NULL }
196};
197
2acf923e
DC		 198u64 __read_mostly host_xcr0;
199
b6785def 200static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 201
af585b92
GN		 202static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
203{
204 int i;
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
207}
208
18863bdd
AK		 209static void kvm_on_user_return(struct user_return_notifier *urn)
210{
211 unsigned slot;
18863bdd
AK		 212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 214 struct kvm_shared_msr_values *values;
1650b4eb
IA		 215 unsigned long flags;
216
217 /*
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
220 */
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
225 }
226 local_irq_restore(flags);
18863bdd 227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
18863bdd
AK		 232 }
233 }
18863bdd
AK		 234}
235
2bf78fa7 236static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 237{
18863bdd 238 u64 value;
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 241
2bf78fa7
SY		 242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
246 return;
247 }
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
251}
252
253void kvm_define_shared_msr(unsigned slot, u32 msr)
254{
0123be42 255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 256 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
261
262static void kvm_shared_msr_cpu_online(void)
263{
264 unsigned i;
18863bdd
AK		 265
266 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 267 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 268}
269
8b3c3104 270int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 274 int err;
18863bdd 275
2bf78fa7 276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 277 return 0;
2bf78fa7 278 smsr->values[slot].curr = value;
8b3c3104
AH		 279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
280 if (err)
281 return 1;
282
18863bdd
AK		 283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
287 }
8b3c3104 288 return 0;
18863bdd
AK		 289}
290EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
291
13a34e06 292static void drop_user_return_notifiers(void)
3548bab5 293{
013f6a5d
MT		 294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 296
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
299}
300
6866b83e
CO		 301u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
302{
8a5a87d9 303 return vcpu->arch.apic_base;
6866b83e
CO		 304}
305EXPORT_SYMBOL_GPL(kvm_get_apic_base);
306
58cb628d
JK		 307int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
308{
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
314 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 315
d3802286
JM		 316 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
317 return 1;
58cb628d 318 if (!msr_info->host_initiated &&
d3802286 319 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
322 old_state == 0)))
323 return 1;
324
325 kvm_lapic_set_base(vcpu, msr_info->data);
326 return 0;
6866b83e
CO		 327}
328EXPORT_SYMBOL_GPL(kvm_set_apic_base);
329
2605fc21 330asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 331{
332 /* Fault while not rebooting. We want the trace. */
333 BUG();
334}
335EXPORT_SYMBOL_GPL(kvm_spurious_fault);
336
3fd28fce
ED		 337#define EXCPT_BENIGN 0
338#define EXCPT_CONTRIBUTORY 1
339#define EXCPT_PF 2
340
341static int exception_class(int vector)
342{
343 switch (vector) {
344 case PF_VECTOR:
345 return EXCPT_PF;
346 case DE_VECTOR:
347 case TS_VECTOR:
348 case NP_VECTOR:
349 case SS_VECTOR:
350 case GP_VECTOR:
351 return EXCPT_CONTRIBUTORY;
352 default:
353 break;
354 }
355 return EXCPT_BENIGN;
356}
357
d6e8c854
NA		 358#define EXCPT_FAULT 0
359#define EXCPT_TRAP 1
360#define EXCPT_ABORT 2
361#define EXCPT_INTERRUPT 3
362
363static int exception_type(int vector)
364{
365 unsigned int mask;
366
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
369
370 mask = 1 << vector;
371
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
374 return EXCPT_TRAP;
375
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
377 return EXCPT_ABORT;
378
379 /* Reserved exceptions will result in fault */
380 return EXCPT_FAULT;
381}
382
3fd28fce 383static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 384 unsigned nr, bool has_error, u32 error_code,
385 bool reinject)
3fd28fce
ED		 386{
387 u32 prev_nr;
388 int class1, class2;
389
3842d135
AK		 390 kvm_make_request(KVM_REQ_EVENT, vcpu);
391
3fd28fce
ED		 392 if (!vcpu->arch.exception.pending) {
393 queue:
3ffb2468
NA		 394 if (has_error && !is_protmode(vcpu))
395 has_error = false;
3fd28fce
ED		 396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
3f0fd292 400 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 401 return;
402 }
403
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
a8eeb04a 408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 409 return;
410 }
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
420 } else
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
423 exception */
424 goto queue;
425}
426
298101da
AK		 427void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
428{
ce7ddec4 429 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 430}
431EXPORT_SYMBOL_GPL(kvm_queue_exception);
432
ce7ddec4
JR		 433void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
434{
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
436}
437EXPORT_SYMBOL_GPL(kvm_requeue_exception);
438
6affcbed 439int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 440{
db8fcefa
AP		 441 if (err)
442 kvm_inject_gp(vcpu, 0);
443 else
6affcbed
KH		 444 return kvm_skip_emulated_instruction(vcpu);
445
446 return 1;
db8fcefa
AP		 447}
448EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 449
6389ee94 450void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 451{
452 ++vcpu->stat.pf_guest;
adfe20fb
WL		 453 vcpu->arch.exception.nested_apf =
454 is_guest_mode(vcpu) && fault->async_page_fault;
455 if (vcpu->arch.exception.nested_apf)
456 vcpu->arch.apf.nested_apf_token = fault->address;
457 else
458 vcpu->arch.cr2 = fault->address;
6389ee94 459 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 460}
27d6c865 461EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 462
ef54bcfe 463static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 464{
6389ee94
AK		 465 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
466 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 467 else
6389ee94 468 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 469
470 return fault->nested_page_fault;
d4f8cf66
JR		 471}
472
3419ffc8
SY		 473void kvm_inject_nmi(struct kvm_vcpu *vcpu)
474{
7460fb4a
AK		 475 atomic_inc(&vcpu->arch.nmi_queued);
476 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 477}
478EXPORT_SYMBOL_GPL(kvm_inject_nmi);
479
298101da
AK		 480void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
481{
ce7ddec4 482 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 483}
484EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
485
ce7ddec4
JR		 486void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
487{
488 kvm_multiple_exception(vcpu, nr, true, error_code, true);
489}
490EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
491
0a79b009
AK		 492/*
493 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
494 * a #GP and return false.
495 */
496bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 497{
0a79b009
AK		 498 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
499 return true;
500 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
501 return false;
298101da 502}
0a79b009 503EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 504
16f8a6f9
NA		 505bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
506{
507 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
508 return true;
509
510 kvm_queue_exception(vcpu, UD_VECTOR);
511 return false;
512}
513EXPORT_SYMBOL_GPL(kvm_require_dr);
514
ec92fe44
JR		 515/*
516 * This function will be used to read from the physical memory of the currently
54bf36aa 517 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 518 * can read from guest physical or from the guest's guest physical memory.
519 */
520int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
521 gfn_t ngfn, void *data, int offset, int len,
522 u32 access)
523{
54987b7a 524 struct x86_exception exception;
ec92fe44
JR		 525 gfn_t real_gfn;
526 gpa_t ngpa;
527
528 ngpa = gfn_to_gpa(ngfn);
54987b7a 529 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 530 if (real_gfn == UNMAPPED_GVA)
531 return -EFAULT;
532
533 real_gfn = gpa_to_gfn(real_gfn);
534
54bf36aa 535 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 536}
537EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
538
69b0049a 539static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 540 void *data, int offset, int len, u32 access)
541{
542 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
543 data, offset, len, access);
544}
545
a03490ed
CO		 546/*
547 * Load the pae pdptrs. Return true is they are all valid.
548 */
ff03a073 549int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 550{
551 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
552 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
553 int i;
554 int ret;
ff03a073 555 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 556
ff03a073
JR		 557 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
558 offset * sizeof(u64), sizeof(pdpte),
559 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 560 if (ret < 0) {
561 ret = 0;
562 goto out;
563 }
564 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 565 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 566 (pdpte[i] &
567 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 568 ret = 0;
569 goto out;
570 }
571 }
572 ret = 1;
573
ff03a073 574 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 575 __set_bit(VCPU_EXREG_PDPTR,
576 (unsigned long *)&vcpu->arch.regs_avail);
577 __set_bit(VCPU_EXREG_PDPTR,
578 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 579out:
a03490ed
CO		 580
581 return ret;
582}
cc4b6871 583EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 584
9ed38ffa 585bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 586{
ff03a073 587 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 588 bool changed = true;
3d06b8bf
JR		 589 int offset;
590 gfn_t gfn;
d835dfec
AK		 591 int r;
592
593 if (is_long_mode(vcpu) || !is_pae(vcpu))
594 return false;
595
6de4f3ad
AK		 596 if (!test_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_avail))
598 return true;
599
a512177e
PB		 600 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
601 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 602 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
603 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 604 if (r < 0)
605 goto out;
ff03a073 606 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 607out:
d835dfec
AK		 608
609 return changed;
610}
9ed38ffa 611EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 612
49a9b07e 613int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 614{
aad82703 615 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 616 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 617
f9a48e6a
AK		 618 cr0 |= X86_CR0_ET;
619
ab344828 620#ifdef CONFIG_X86_64
0f12244f
GN		 621 if (cr0 & 0xffffffff00000000UL)
622 return 1;
ab344828
GN		 623#endif
624
625 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
628 return 1;
a03490ed 629
0f12244f
GN		 630 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
631 return 1;
a03490ed
CO		 632
633 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
634#ifdef CONFIG_X86_64
f6801dff 635 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 636 int cs_db, cs_l;
637
0f12244f
GN		 638 if (!is_pae(vcpu))
639 return 1;
a03490ed 640 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 641 if (cs_l)
642 return 1;
a03490ed
CO		 643 } else
644#endif
ff03a073 645 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 646 kvm_read_cr3(vcpu)))
0f12244f 647 return 1;
a03490ed
CO		 648 }
649
ad756a16
MJ		 650 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
651 return 1;
652
a03490ed 653 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 654
d170c419 655 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 656 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 657 kvm_async_pf_hash_reset(vcpu);
658 }
e5f3f027 659
aad82703
SY		 660 if ((cr0 ^ old_cr0) & update_bits)
661 kvm_mmu_reset_context(vcpu);
b18d5431 662
879ae188
LE		 663 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
664 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
665 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 666 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
667
0f12244f
GN		 668 return 0;
669}
2d3ad1f4 670EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 671
2d3ad1f4 672void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 673{
49a9b07e 674 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 677
42bdf991
MT		 678static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
679{
680 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
681 !vcpu->guest_xcr0_loaded) {
682 /* kvm_set_xcr() also depends on this */
683 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
684 vcpu->guest_xcr0_loaded = 1;
685 }
686}
687
688static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
689{
690 if (vcpu->guest_xcr0_loaded) {
691 if (vcpu->arch.xcr0 != host_xcr0)
692 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
693 vcpu->guest_xcr0_loaded = 0;
694 }
695}
696
69b0049a 697static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 698{
56c103ec
LJ		 699 u64 xcr0 = xcr;
700 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 701 u64 valid_bits;
2acf923e
DC		 702
703 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
704 if (index != XCR_XFEATURE_ENABLED_MASK)
705 return 1;
d91cab78 706 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 709 return 1;
46c34cb0
PB		 710
711 /*
712 * Do not allow the guest to set bits that we do not support
713 * saving. However, xcr0 bit 0 is always set, even if the
714 * emulated CPU does not support XSAVE (see fx_init).
715 */
d91cab78 716 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 717 if (xcr0 & ~valid_bits)
2acf923e 718 return 1;
46c34cb0 719
d91cab78
DH		 720 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
721 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 722 return 1;
723
d91cab78
DH		 724 if (xcr0 & XFEATURE_MASK_AVX512) {
725 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 728 return 1;
729 }
2acf923e 730 vcpu->arch.xcr0 = xcr0;
56c103ec 731
d91cab78 732 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 733 kvm_update_cpuid(vcpu);
2acf923e
DC		 734 return 0;
735}
736
737int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
738{
764bcbc5
Z		 739 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
740 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 741 kvm_inject_gp(vcpu, 0);
742 return 1;
743 }
744 return 0;
745}
746EXPORT_SYMBOL_GPL(kvm_set_xcr);
747
a83b29c6 748int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 749{
fc78f519 750 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 751 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 752 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 753
0f12244f
GN		 754 if (cr4 & CR4_RESERVED_BITS)
755 return 1;
a03490ed 756
d6321d49 757 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 758 return 1;
759
d6321d49 760 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
c68b734f
YW		 761 return 1;
762
d6321d49 763 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
97ec8c06
FW		 764 return 1;
765
d6321d49 766 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 767 return 1;
768
d6321d49 769 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
b9baba86
HH		 770 return 1;
771
fd8cb433
YZ		 772 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
773 return 1;
774
a03490ed 775 if (is_long_mode(vcpu)) {
0f12244f
GN		 776 if (!(cr4 & X86_CR4_PAE))
777 return 1;
a2edf57f
AK		 778 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
779 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 780 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
781 kvm_read_cr3(vcpu)))
0f12244f
GN		 782 return 1;
783
ad756a16 784 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 786 return 1;
787
788 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
789 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
790 return 1;
791 }
792
5e1746d6 793 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 794 return 1;
a03490ed 795
ad756a16
MJ		 796 if (((cr4 ^ old_cr4) & pdptr_bits) ||
797 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 798 kvm_mmu_reset_context(vcpu);
0f12244f 799
b9baba86 800 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 801 kvm_update_cpuid(vcpu);
2acf923e 802
0f12244f
GN		 803 return 0;
804}
2d3ad1f4 805EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 806
2390218b 807int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 808{
ac146235 809#ifdef CONFIG_X86_64
9d88fca7 810 cr3 &= ~CR3_PCID_INVD;
ac146235 811#endif
9d88fca7 812
9f8fe504 813 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 814 kvm_mmu_sync_roots(vcpu);
77c3913b 815 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 816 return 0;
d835dfec
AK		 817 }
818
d1cd3ce9
YZ		 819 if (is_long_mode(vcpu) &&
820 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
821 return 1;
822 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 823 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 824 return 1;
a03490ed 825
0f12244f 826 vcpu->arch.cr3 = cr3;
aff48baa 827 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 828 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 829 return 0;
830}
2d3ad1f4 831EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 832
eea1cff9 833int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 834{
0f12244f
GN		 835 if (cr8 & CR8_RESERVED_BITS)
836 return 1;
35754c98 837 if (lapic_in_kernel(vcpu))
a03490ed
CO		 838 kvm_lapic_set_tpr(vcpu, cr8);
839 else
ad312c7c 840 vcpu->arch.cr8 = cr8;
0f12244f
GN		 841 return 0;
842}
2d3ad1f4 843EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 844
2d3ad1f4 845unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 846{
35754c98 847 if (lapic_in_kernel(vcpu))
a03490ed
CO		 848 return kvm_lapic_get_cr8(vcpu);
849 else
ad312c7c 850 return vcpu->arch.cr8;
a03490ed 851}
2d3ad1f4 852EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 853
ae561ede
NA		 854static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
855{
856 int i;
857
858 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
859 for (i = 0; i < KVM_NR_DB_REGS; i++)
860 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
861 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
862 }
863}
864
73aaf249
JK		 865static void kvm_update_dr6(struct kvm_vcpu *vcpu)
866{
867 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
868 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
869}
870
c8639010
JK		 871static void kvm_update_dr7(struct kvm_vcpu *vcpu)
872{
873 unsigned long dr7;
874
875 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
876 dr7 = vcpu->arch.guest_debug_dr7;
877 else
878 dr7 = vcpu->arch.dr7;
879 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 880 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
881 if (dr7 & DR7_BP_EN_MASK)
882 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 883}
884
6f43ed01
NA		 885static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
886{
887 u64 fixed = DR6_FIXED_1;
888
d6321d49 889 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 890 fixed |= DR6_RTM;
891 return fixed;
892}
893
338dbc97 894static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 895{
896 switch (dr) {
897 case 0 ... 3:
898 vcpu->arch.db[dr] = val;
899 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
900 vcpu->arch.eff_db[dr] = val;
901 break;
902 case 4:
020df079
GN		 903 /* fall through */
904 case 6:
338dbc97
GN		 905 if (val & 0xffffffff00000000ULL)
906 return -1; /* #GP */
6f43ed01 907 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 908 kvm_update_dr6(vcpu);
020df079
GN		 909 break;
910 case 5:
020df079
GN		 911 /* fall through */
912 default: /* 7 */
338dbc97
GN		 913 if (val & 0xffffffff00000000ULL)
914 return -1; /* #GP */
020df079 915 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 916 kvm_update_dr7(vcpu);
020df079
GN		 917 break;
918 }
919
920 return 0;
921}
338dbc97
GN		 922
923int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
924{
16f8a6f9 925 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 926 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 927 return 1;
928 }
929 return 0;
338dbc97 930}
020df079
GN		 931EXPORT_SYMBOL_GPL(kvm_set_dr);
932
16f8a6f9 933int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 934{
935 switch (dr) {
936 case 0 ... 3:
937 *val = vcpu->arch.db[dr];
938 break;
939 case 4:
020df079
GN		 940 /* fall through */
941 case 6:
73aaf249
JK		 942 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
943 *val = vcpu->arch.dr6;
944 else
945 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 946 break;
947 case 5:
020df079
GN		 948 /* fall through */
949 default: /* 7 */
950 *val = vcpu->arch.dr7;
951 break;
952 }
338dbc97
GN		 953 return 0;
954}
020df079
GN		 955EXPORT_SYMBOL_GPL(kvm_get_dr);
956
022cd0e8
AK		 957bool kvm_rdpmc(struct kvm_vcpu *vcpu)
958{
959 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
960 u64 data;
961 int err;
962
c6702c9d 963 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 964 if (err)
965 return err;
966 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
967 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
968 return err;
969}
970EXPORT_SYMBOL_GPL(kvm_rdpmc);
971
043405e1
CO		 972/*
973 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
974 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
975 *
976 * This list is modified at module load time to reflect the
e3267cbb 977 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 978 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
979 * may depend on host virtualization features rather than host cpu features.
043405e1 980 */
e3267cbb 981
043405e1
CO		 982static u32 msrs_to_save[] = {
983 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 984 MSR_STAR,
043405e1
CO		 985#ifdef CONFIG_X86_64
986 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
987#endif
b3897a49 988 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 989 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 990};
991
992static unsigned num_msrs_to_save;
993
62ef68bb
PB		 994static u32 emulated_msrs[] = {
995 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
996 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
997 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
998 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 999 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1000 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1001 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1002 HV_X64_MSR_RESET,
11c4b1ca 1003 HV_X64_MSR_VP_INDEX,
9eec50b8 1004 HV_X64_MSR_VP_RUNTIME,
5c919412 1005 HV_X64_MSR_SCONTROL,
1f4b34f8 1006 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1007 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1008 MSR_KVM_PV_EOI_EN,
1009
ba904635 1010 MSR_IA32_TSC_ADJUST,
a3e06bbe 1011 MSR_IA32_TSCDEADLINE,
043405e1 1012 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1013 MSR_IA32_MCG_STATUS,
1014 MSR_IA32_MCG_CTL,
c45dcc71 1015 MSR_IA32_MCG_EXT_CTL,
64d60670 1016 MSR_IA32_SMBASE,
db2336a8
KH		 1017 MSR_PLATFORM_INFO,
1018 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1019};
1020
62ef68bb
PB		 1021static unsigned num_emulated_msrs;
1022
384bb783 1023bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1024{
b69e8cae 1025 if (efer & efer_reserved_bits)
384bb783 1026 return false;
15c4a640 1027
1b4d56b8 1028 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1029 return false;
1b2fd70c 1030
1b4d56b8 1031 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1032 return false;
d8017474 1033
384bb783
JK		 1034 return true;
1035}
1036EXPORT_SYMBOL_GPL(kvm_valid_efer);
1037
1038static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1039{
1040 u64 old_efer = vcpu->arch.efer;
1041
1042 if (!kvm_valid_efer(vcpu, efer))
1043 return 1;
1044
1045 if (is_paging(vcpu)
1046 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1047 return 1;
1048
15c4a640 1049 efer &= ~EFER_LMA;
f6801dff 1050 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1051
a3d204e2
SY		 1052 kvm_x86_ops->set_efer(vcpu, efer);
1053
aad82703
SY		 1054 /* Update reserved bits */
1055 if ((efer ^ old_efer) & EFER_NX)
1056 kvm_mmu_reset_context(vcpu);
1057
b69e8cae 1058 return 0;
15c4a640
CO		 1059}
1060
f2b4b7dd
JR		 1061void kvm_enable_efer_bits(u64 mask)
1062{
1063 efer_reserved_bits &= ~mask;
1064}
1065EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1066
15c4a640
CO		 1067/*
1068 * Writes msr value into into the appropriate "register".
1069 * Returns 0 on success, non-0 otherwise.
1070 * Assumes vcpu_load() was already called.
1071 */
8fe8ab46 1072int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1073{
854e8bb1
NA		 1074 switch (msr->index) {
1075 case MSR_FS_BASE:
1076 case MSR_GS_BASE:
1077 case MSR_KERNEL_GS_BASE:
1078 case MSR_CSTAR:
1079 case MSR_LSTAR:
fd8cb433 1080 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1081 return 1;
1082 break;
1083 case MSR_IA32_SYSENTER_EIP:
1084 case MSR_IA32_SYSENTER_ESP:
1085 /*
1086 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1087 * non-canonical address is written on Intel but not on
1088 * AMD (which ignores the top 32-bits, because it does
1089 * not implement 64-bit SYSENTER).
1090 *
1091 * 64-bit code should hence be able to write a non-canonical
1092 * value on AMD. Making the address canonical ensures that
1093 * vmentry does not fail on Intel after writing a non-canonical
1094 * value, and that something deterministic happens if the guest
1095 * invokes 64-bit SYSENTER.
1096 */
fd8cb433 1097 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1098 }
8fe8ab46 1099 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1100}
854e8bb1 1101EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1102
313a3dc7
CO		 1103/*
1104 * Adapt set_msr() to msr_io()'s calling convention
1105 */
609e36d3
PB		 1106static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1107{
1108 struct msr_data msr;
1109 int r;
1110
1111 msr.index = index;
1112 msr.host_initiated = true;
1113 r = kvm_get_msr(vcpu, &msr);
1114 if (r)
1115 return r;
1116
1117 *data = msr.data;
1118 return 0;
1119}
1120
313a3dc7
CO		 1121static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1122{
8fe8ab46
WA		 1123 struct msr_data msr;
1124
1125 msr.data = *data;
1126 msr.index = index;
1127 msr.host_initiated = true;
1128 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1129}
1130
16e8d74d
MT		 1131#ifdef CONFIG_X86_64
1132struct pvclock_gtod_data {
1133 seqcount_t seq;
1134
1135 struct { /* extract of a clocksource struct */
1136 int vclock_mode;
a5a1d1c2
TG		 1137 u64 cycle_last;
1138 u64 mask;
16e8d74d
MT		 1139 u32 mult;
1140 u32 shift;
1141 } clock;
1142
cbcf2dd3
TG		 1143 u64 boot_ns;
1144 u64 nsec_base;
55dd00a7 1145 u64 wall_time_sec;
16e8d74d
MT		 1146};
1147
1148static struct pvclock_gtod_data pvclock_gtod_data;
1149
1150static void update_pvclock_gtod(struct timekeeper *tk)
1151{
1152 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1153 u64 boot_ns;
1154
876e7881 1155 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1156
1157 write_seqcount_begin(&vdata->seq);
1158
1159 /* copy pvclock gtod data */
876e7881
PZ		 1160 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1161 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1162 vdata->clock.mask = tk->tkr_mono.mask;
1163 vdata->clock.mult = tk->tkr_mono.mult;
1164 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1165
cbcf2dd3 1166 vdata->boot_ns = boot_ns;
876e7881 1167 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1168
55dd00a7
MT		 1169 vdata->wall_time_sec = tk->xtime_sec;
1170
16e8d74d
MT		 1171 write_seqcount_end(&vdata->seq);
1172}
1173#endif
1174
bab5bb39
NK		 1175void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1176{
1177 /*
1178 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1179 * vcpu_enter_guest. This function is only called from
1180 * the physical CPU that is running vcpu.
1181 */
1182 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1183}
16e8d74d 1184
18068523
GOC		 1185static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1186{
9ed3c444
AK		 1187 int version;
1188 int r;
50d0a0f9 1189 struct pvclock_wall_clock wc;
87aeb54f 1190 struct timespec64 boot;
18068523
GOC		 1191
1192 if (!wall_clock)
1193 return;
1194
9ed3c444
AK		 1195 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1196 if (r)
1197 return;
1198
1199 if (version & 1)
1200 ++version; /* first time write, random junk */
1201
1202 ++version;
18068523 1203
1dab1345
NK		 1204 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1205 return;
18068523 1206
50d0a0f9
GH		 1207 /*
1208 * The guest calculates current wall clock time by adding
34c238a1 1209 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1210 * wall clock specified here. guest system time equals host
1211 * system time for us, thus we must fill in host boot time here.
1212 */
87aeb54f 1213 getboottime64(&boot);
50d0a0f9 1214
4b648665 1215 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1216 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1217 boot = timespec64_sub(boot, ts);
4b648665 1218 }
87aeb54f 1219 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1220 wc.nsec = boot.tv_nsec;
1221 wc.version = version;
18068523
GOC		 1222
1223 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1224
1225 version++;
1226 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1227}
1228
50d0a0f9
GH		 1229static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1230{
b51012de
PB		 1231 do_shl32_div32(dividend, divisor);
1232 return dividend;
50d0a0f9
GH		 1233}
1234
3ae13faa 1235static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1236 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1237{
5f4e3f88 1238 uint64_t scaled64;
50d0a0f9
GH		 1239 int32_t shift = 0;
1240 uint64_t tps64;
1241 uint32_t tps32;
1242
3ae13faa
PB		 1243 tps64 = base_hz;
1244 scaled64 = scaled_hz;
50933623 1245 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1246 tps64 >>= 1;
1247 shift--;
1248 }
1249
1250 tps32 = (uint32_t)tps64;
50933623
JK		 1251 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1252 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1253 scaled64 >>= 1;
1254 else
1255 tps32 <<= 1;
50d0a0f9
GH		 1256 shift++;
1257 }
1258
5f4e3f88
ZA		 1259 *pshift = shift;
1260 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1261
3ae13faa
PB		 1262 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1263 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1264}
1265
d828199e 1266#ifdef CONFIG_X86_64
16e8d74d 1267static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1268#endif
16e8d74d 1269
c8076604 1270static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1271static unsigned long max_tsc_khz;
c8076604 1272
cc578287 1273static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1274{
cc578287
ZA		 1275 u64 v = (u64)khz * (1000000 + ppm);
1276 do_div(v, 1000000);
1277 return v;
1e993611
JR		 1278}
1279
381d585c
HZ		 1280static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1281{
1282 u64 ratio;
1283
1284 /* Guest TSC same frequency as host TSC? */
1285 if (!scale) {
1286 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1287 return 0;
1288 }
1289
1290 /* TSC scaling supported? */
1291 if (!kvm_has_tsc_control) {
1292 if (user_tsc_khz > tsc_khz) {
1293 vcpu->arch.tsc_catchup = 1;
1294 vcpu->arch.tsc_always_catchup = 1;
1295 return 0;
1296 } else {
1297 WARN(1, "user requested TSC rate below hardware speed\n");
1298 return -1;
1299 }
1300 }
1301
1302 /* TSC scaling required - calculate ratio */
1303 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1304 user_tsc_khz, tsc_khz);
1305
1306 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1307 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1308 user_tsc_khz);
1309 return -1;
1310 }
1311
1312 vcpu->arch.tsc_scaling_ratio = ratio;
1313 return 0;
1314}
1315
4941b8cb 1316static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1317{
cc578287
ZA		 1318 u32 thresh_lo, thresh_hi;
1319 int use_scaling = 0;
217fc9cf 1320
03ba32ca 1321 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1322 if (user_tsc_khz == 0) {
ad721883
HZ		 1323 /* set tsc_scaling_ratio to a safe value */
1324 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1325 return -1;
ad721883 1326 }
03ba32ca 1327
c285545f 1328 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1329 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1330 &vcpu->arch.virtual_tsc_shift,
1331 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1332 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1333
1334 /*
1335 * Compute the variation in TSC rate which is acceptable
1336 * within the range of tolerance and decide if the
1337 * rate being applied is within that bounds of the hardware
1338 * rate. If so, no scaling or compensation need be done.
1339 */
1340 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1341 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1342 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1343 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1344 use_scaling = 1;
1345 }
4941b8cb 1346 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1347}
1348
1349static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1350{
e26101b1 1351 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1352 vcpu->arch.virtual_tsc_mult,
1353 vcpu->arch.virtual_tsc_shift);
e26101b1 1354 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1355 return tsc;
1356}
1357
69b0049a 1358static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1359{
1360#ifdef CONFIG_X86_64
1361 bool vcpus_matched;
b48aa97e
MT		 1362 struct kvm_arch *ka = &vcpu->kvm->arch;
1363 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1364
1365 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1366 atomic_read(&vcpu->kvm->online_vcpus));
1367
7f187922
MT		 1368 /*
1369 * Once the masterclock is enabled, always perform request in
1370 * order to update it.
1371 *
1372 * In order to enable masterclock, the host clocksource must be TSC
1373 * and the vcpus need to have matched TSCs. When that happens,
1374 * perform request to enable masterclock.
1375 */
1376 if (ka->use_master_clock ||
1377 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1378 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1379
1380 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1381 atomic_read(&vcpu->kvm->online_vcpus),
1382 ka->use_master_clock, gtod->clock.vclock_mode);
1383#endif
1384}
1385
ba904635
WA		 1386static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1387{
3e3f5026 1388 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1389 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1390}
1391
35181e86
HZ		 1392/*
1393 * Multiply tsc by a fixed point number represented by ratio.
1394 *
1395 * The most significant 64-N bits (mult) of ratio represent the
1396 * integral part of the fixed point number; the remaining N bits
1397 * (frac) represent the fractional part, ie. ratio represents a fixed
1398 * point number (mult + frac * 2^(-N)).
1399 *
1400 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1401 */
1402static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1403{
1404 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1405}
1406
1407u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1408{
1409 u64 _tsc = tsc;
1410 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1411
1412 if (ratio != kvm_default_tsc_scaling_ratio)
1413 _tsc = __scale_tsc(ratio, tsc);
1414
1415 return _tsc;
1416}
1417EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1418
07c1419a
HZ		 1419static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1420{
1421 u64 tsc;
1422
1423 tsc = kvm_scale_tsc(vcpu, rdtsc());
1424
1425 return target_tsc - tsc;
1426}
1427
4ba76538
HZ		 1428u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1429{
ea26e4ec 1430 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1431}
1432EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1433
a545ab6a
LC		 1434static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1435{
1436 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1437 vcpu->arch.tsc_offset = offset;
1438}
1439
8fe8ab46 1440void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1441{
1442 struct kvm *kvm = vcpu->kvm;
f38e098f 1443 u64 offset, ns, elapsed;
99e3e30a 1444 unsigned long flags;
b48aa97e 1445 bool matched;
0d3da0d2 1446 bool already_matched;
8fe8ab46 1447 u64 data = msr->data;
c5e8ec8e 1448 bool synchronizing = false;
99e3e30a 1449
038f8c11 1450 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1451 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1452 ns = ktime_get_boot_ns();
f38e098f 1453 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1454
03ba32ca 1455 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1456 if (data == 0 && msr->host_initiated) {
1457 /*
1458 * detection of vcpu initialization -- need to sync
1459 * with other vCPUs. This particularly helps to keep
1460 * kvm_clock stable after CPU hotplug
1461 */
1462 synchronizing = true;
1463 } else {
1464 u64 tsc_exp = kvm->arch.last_tsc_write +
1465 nsec_to_cycles(vcpu, elapsed);
1466 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1467 /*
1468 * Special case: TSC write with a small delta (1 second)
1469 * of virtual cycle time against real time is
1470 * interpreted as an attempt to synchronize the CPU.
1471 */
1472 synchronizing = data < tsc_exp + tsc_hz &&
1473 data + tsc_hz > tsc_exp;
1474 }
c5e8ec8e 1475 }
f38e098f
ZA		 1476
1477 /*
5d3cb0f6
ZA		 1478 * For a reliable TSC, we can match TSC offsets, and for an unstable
1479 * TSC, we add elapsed time in this computation. We could let the
1480 * compensation code attempt to catch up if we fall behind, but
1481 * it's better to try to match offsets from the beginning.
1482 */
c5e8ec8e 1483 if (synchronizing &&
5d3cb0f6 1484 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1485 if (!check_tsc_unstable()) {
e26101b1 1486 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1487 pr_debug("kvm: matched tsc offset for %llu\n", data);
1488 } else {
857e4099 1489 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1490 data += delta;
07c1419a 1491 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1492 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1493 }
b48aa97e 1494 matched = true;
0d3da0d2 1495 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1496 } else {
1497 /*
1498 * We split periods of matched TSC writes into generations.
1499 * For each generation, we track the original measured
1500 * nanosecond time, offset, and write, so if TSCs are in
1501 * sync, we can match exact offset, and if not, we can match
4a969980 1502 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1503 *
1504 * These values are tracked in kvm->arch.cur_xxx variables.
1505 */
1506 kvm->arch.cur_tsc_generation++;
1507 kvm->arch.cur_tsc_nsec = ns;
1508 kvm->arch.cur_tsc_write = data;
1509 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1510 matched = false;
0d3da0d2 1511 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1512 kvm->arch.cur_tsc_generation, data);
f38e098f 1513 }
e26101b1
ZA		 1514
1515 /*
1516 * We also track th most recent recorded KHZ, write and time to
1517 * allow the matching interval to be extended at each write.
1518 */
f38e098f
ZA		 1519 kvm->arch.last_tsc_nsec = ns;
1520 kvm->arch.last_tsc_write = data;
5d3cb0f6 1521 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1522
b183aa58 1523 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1524
1525 /* Keep track of which generation this VCPU has synchronized to */
1526 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1527 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1528 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1529
d6321d49 1530 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1531 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1532
a545ab6a 1533 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1534 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1535
1536 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1537 if (!matched) {
b48aa97e 1538 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1539 } else if (!already_matched) {
1540 kvm->arch.nr_vcpus_matched_tsc++;
1541 }
b48aa97e
MT		 1542
1543 kvm_track_tsc_matching(vcpu);
1544 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1545}
e26101b1 1546
99e3e30a
ZA		 1547EXPORT_SYMBOL_GPL(kvm_write_tsc);
1548
58ea6767
HZ		 1549static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1550 s64 adjustment)
1551{
ea26e4ec 1552 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1553}
1554
1555static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1556{
1557 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1558 WARN_ON(adjustment < 0);
1559 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1560 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1561}
1562
d828199e
MT		 1563#ifdef CONFIG_X86_64
1564
a5a1d1c2 1565static u64 read_tsc(void)
d828199e 1566{
a5a1d1c2 1567 u64 ret = (u64)rdtsc_ordered();
03b9730b 1568 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1569
1570 if (likely(ret >= last))
1571 return ret;
1572
1573 /*
1574 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1575 * predictable (it's just a function of time and the likely is
d828199e
MT		 1576 * very likely) and there's a data dependence, so force GCC
1577 * to generate a branch instead. I don't barrier() because
1578 * we don't actually need a barrier, and if this function
1579 * ever gets inlined it will generate worse code.
1580 */
1581 asm volatile ("");
1582 return last;
1583}
1584
a5a1d1c2 1585static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1586{
1587 long v;
1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1589
1590 *cycle_now = read_tsc();
1591
1592 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1593 return v * gtod->clock.mult;
1594}
1595
a5a1d1c2 1596static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1597{
cbcf2dd3 1598 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1599 unsigned long seq;
d828199e 1600 int mode;
cbcf2dd3 1601 u64 ns;
d828199e 1602
d828199e
MT		 1603 do {
1604 seq = read_seqcount_begin(&gtod->seq);
1605 mode = gtod->clock.vclock_mode;
cbcf2dd3 1606 ns = gtod->nsec_base;
d828199e
MT		 1607 ns += vgettsc(cycle_now);
1608 ns >>= gtod->clock.shift;
cbcf2dd3 1609 ns += gtod->boot_ns;
d828199e 1610 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1611 *t = ns;
d828199e
MT		 1612
1613 return mode;
1614}
1615
55dd00a7
MT		 1616static int do_realtime(struct timespec *ts, u64 *cycle_now)
1617{
1618 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1619 unsigned long seq;
1620 int mode;
1621 u64 ns;
1622
1623 do {
1624 seq = read_seqcount_begin(&gtod->seq);
1625 mode = gtod->clock.vclock_mode;
1626 ts->tv_sec = gtod->wall_time_sec;
1627 ns = gtod->nsec_base;
1628 ns += vgettsc(cycle_now);
1629 ns >>= gtod->clock.shift;
1630 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1631
1632 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1633 ts->tv_nsec = ns;
1634
1635 return mode;
1636}
1637
d828199e 1638/* returns true if host is using tsc clocksource */
a5a1d1c2 1639static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1640{
d828199e
MT		 1641 /* checked again under seqlock below */
1642 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1643 return false;
1644
cbcf2dd3 1645 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1646}
55dd00a7
MT		 1647
1648/* returns true if host is using tsc clocksource */
1649static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1650 u64 *cycle_now)
1651{
1652 /* checked again under seqlock below */
1653 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1654 return false;
1655
1656 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1657}
d828199e
MT		 1658#endif
1659
1660/*
1661 *
b48aa97e
MT		 1662 * Assuming a stable TSC across physical CPUS, and a stable TSC
1663 * across virtual CPUs, the following condition is possible.
1664 * Each numbered line represents an event visible to both
d828199e
MT		 1665 * CPUs at the next numbered event.
1666 *
1667 * "timespecX" represents host monotonic time. "tscX" represents
1668 * RDTSC value.
1669 *
1670 * VCPU0 on CPU0 | VCPU1 on CPU1
1671 *
1672 * 1. read timespec0,tsc0
1673 * 2. | timespec1 = timespec0 + N
1674 * | tsc1 = tsc0 + M
1675 * 3. transition to guest | transition to guest
1676 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1677 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1678 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1679 *
1680 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1681 *
1682 * - ret0 < ret1
1683 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1684 * ...
1685 * - 0 < N - M => M < N
1686 *
1687 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1688 * always the case (the difference between two distinct xtime instances
1689 * might be smaller then the difference between corresponding TSC reads,
1690 * when updating guest vcpus pvclock areas).
1691 *
1692 * To avoid that problem, do not allow visibility of distinct
1693 * system_timestamp/tsc_timestamp values simultaneously: use a master
1694 * copy of host monotonic time values. Update that master copy
1695 * in lockstep.
1696 *
b48aa97e 1697 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1698 *
1699 */
1700
1701static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1702{
1703#ifdef CONFIG_X86_64
1704 struct kvm_arch *ka = &kvm->arch;
1705 int vclock_mode;
b48aa97e
MT		 1706 bool host_tsc_clocksource, vcpus_matched;
1707
1708 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1709 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1710
1711 /*
1712 * If the host uses TSC clock, then passthrough TSC as stable
1713 * to the guest.
1714 */
b48aa97e 1715 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1716 &ka->master_kernel_ns,
1717 &ka->master_cycle_now);
1718
16a96021 1719 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1720 && !ka->backwards_tsc_observed
54750f2c 1721 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1722
d828199e
MT		 1723 if (ka->use_master_clock)
1724 atomic_set(&kvm_guest_has_master_clock, 1);
1725
1726 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1727 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1728 vcpus_matched);
d828199e
MT		 1729#endif
1730}
1731
2860c4b1
PB		 1732void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1733{
1734 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1735}
1736
2e762ff7
MT		 1737static void kvm_gen_update_masterclock(struct kvm *kvm)
1738{
1739#ifdef CONFIG_X86_64
1740 int i;
1741 struct kvm_vcpu *vcpu;
1742 struct kvm_arch *ka = &kvm->arch;
1743
1744 spin_lock(&ka->pvclock_gtod_sync_lock);
1745 kvm_make_mclock_inprogress_request(kvm);
1746 /* no guest entries from this point */
1747 pvclock_update_vm_gtod_copy(kvm);
1748
1749 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1750 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1751
1752 /* guest entries allowed */
1753 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1754 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1755
1756 spin_unlock(&ka->pvclock_gtod_sync_lock);
1757#endif
1758}
1759
e891a32e 1760u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1761{
108b249c 1762 struct kvm_arch *ka = &kvm->arch;
8b953440 1763 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1764 u64 ret;
108b249c 1765
8b953440
PB		 1766 spin_lock(&ka->pvclock_gtod_sync_lock);
1767 if (!ka->use_master_clock) {
1768 spin_unlock(&ka->pvclock_gtod_sync_lock);
1769 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1770 }
1771
8b953440
PB		 1772 hv_clock.tsc_timestamp = ka->master_cycle_now;
1773 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1774 spin_unlock(&ka->pvclock_gtod_sync_lock);
1775
e2c2206a
WL		 1776 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1777 get_cpu();
1778
8b953440
PB		 1779 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1780 &hv_clock.tsc_shift,
1781 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1782 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1783
1784 put_cpu();
1785
1786 return ret;
108b249c
PB		 1787}
1788
0d6dd2ff
PB		 1789static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1790{
1791 struct kvm_vcpu_arch *vcpu = &v->arch;
1792 struct pvclock_vcpu_time_info guest_hv_clock;
1793
4e335d9e 1794 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1795 &guest_hv_clock, sizeof(guest_hv_clock))))
1796 return;
1797
1798 /* This VCPU is paused, but it's legal for a guest to read another
1799 * VCPU's kvmclock, so we really have to follow the specification where
1800 * it says that version is odd if data is being modified, and even after
1801 * it is consistent.
1802 *
1803 * Version field updates must be kept separate. This is because
1804 * kvm_write_guest_cached might use a "rep movs" instruction, and
1805 * writes within a string instruction are weakly ordered. So there
1806 * are three writes overall.
1807 *
1808 * As a small optimization, only write the version field in the first
1809 * and third write. The vcpu->pv_time cache is still valid, because the
1810 * version field is the first in the struct.
1811 */
1812 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1813
1814 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1815 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1816 &vcpu->hv_clock,
1817 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1818
1819 smp_wmb();
1820
1821 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1822 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1823
1824 if (vcpu->pvclock_set_guest_stopped_request) {
1825 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1826 vcpu->pvclock_set_guest_stopped_request = false;
1827 }
1828
1829 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1830
4e335d9e
PB		 1831 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1832 &vcpu->hv_clock,
1833 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1834
1835 smp_wmb();
1836
1837 vcpu->hv_clock.version++;
4e335d9e
PB		 1838 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1839 &vcpu->hv_clock,
1840 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1841}
1842
34c238a1 1843static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1844{
78db6a50 1845 unsigned long flags, tgt_tsc_khz;
18068523 1846 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1847 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1848 s64 kernel_ns;
d828199e 1849 u64 tsc_timestamp, host_tsc;
51d59c6b 1850 u8 pvclock_flags;
d828199e
MT		 1851 bool use_master_clock;
1852
1853 kernel_ns = 0;
1854 host_tsc = 0;
18068523 1855
d828199e
MT		 1856 /*
1857 * If the host uses TSC clock, then passthrough TSC as stable
1858 * to the guest.
1859 */
1860 spin_lock(&ka->pvclock_gtod_sync_lock);
1861 use_master_clock = ka->use_master_clock;
1862 if (use_master_clock) {
1863 host_tsc = ka->master_cycle_now;
1864 kernel_ns = ka->master_kernel_ns;
1865 }
1866 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1867
1868 /* Keep irq disabled to prevent changes to the clock */
1869 local_irq_save(flags);
78db6a50
PB		 1870 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1871 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1872 local_irq_restore(flags);
1873 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1874 return 1;
1875 }
d828199e 1876 if (!use_master_clock) {
4ea1636b 1877 host_tsc = rdtsc();
108b249c 1878 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1879 }
1880
4ba76538 1881 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1882
c285545f
ZA		 1883 /*
1884 * We may have to catch up the TSC to match elapsed wall clock
1885 * time for two reasons, even if kvmclock is used.
1886 * 1) CPU could have been running below the maximum TSC rate
1887 * 2) Broken TSC compensation resets the base at each VCPU
1888 * entry to avoid unknown leaps of TSC even when running
1889 * again on the same CPU. This may cause apparent elapsed
1890 * time to disappear, and the guest to stand still or run
1891 * very slowly.
1892 */
1893 if (vcpu->tsc_catchup) {
1894 u64 tsc = compute_guest_tsc(v, kernel_ns);
1895 if (tsc > tsc_timestamp) {
f1e2b260 1896 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1897 tsc_timestamp = tsc;
1898 }
50d0a0f9
GH		 1899 }
1900
18068523
GOC		 1901 local_irq_restore(flags);
1902
0d6dd2ff 1903 /* With all the info we got, fill in the values */
18068523 1904
78db6a50
PB		 1905 if (kvm_has_tsc_control)
1906 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1907
1908 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1909 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1910 &vcpu->hv_clock.tsc_shift,
1911 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1912 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1913 }
1914
1d5f066e 1915 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1916 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1917 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1918
d828199e 1919 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1920 pvclock_flags = 0;
d828199e
MT		 1921 if (use_master_clock)
1922 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1923
78c0337a
MT		 1924 vcpu->hv_clock.flags = pvclock_flags;
1925
095cf55d
PB		 1926 if (vcpu->pv_time_enabled)
1927 kvm_setup_pvclock_page(v);
1928 if (v == kvm_get_vcpu(v->kvm, 0))
1929 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1930 return 0;
c8076604
GH		 1931}
1932
0061d53d
MT		 1933/*
1934 * kvmclock updates which are isolated to a given vcpu, such as
1935 * vcpu->cpu migration, should not allow system_timestamp from
1936 * the rest of the vcpus to remain static. Otherwise ntp frequency
1937 * correction applies to one vcpu's system_timestamp but not
1938 * the others.
1939 *
1940 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1941 * We need to rate-limit these requests though, as they can
1942 * considerably slow guests that have a large number of vcpus.
1943 * The time for a remote vcpu to update its kvmclock is bound
1944 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1945 */
1946
7e44e449
AJ		 1947#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1948
1949static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1950{
1951 int i;
7e44e449
AJ		 1952 struct delayed_work *dwork = to_delayed_work(work);
1953 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1954 kvmclock_update_work);
1955 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1956 struct kvm_vcpu *vcpu;
1957
1958 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1959 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1960 kvm_vcpu_kick(vcpu);
1961 }
1962}
1963
7e44e449
AJ		 1964static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1965{
1966 struct kvm *kvm = v->kvm;
1967
105b21bb 1968 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1969 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1970 KVMCLOCK_UPDATE_DELAY);
1971}
1972
332967a3
AJ		 1973#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1974
1975static void kvmclock_sync_fn(struct work_struct *work)
1976{
1977 struct delayed_work *dwork = to_delayed_work(work);
1978 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1979 kvmclock_sync_work);
1980 struct kvm *kvm = container_of(ka, struct kvm, arch);
1981
630994b3
MT		 1982 if (!kvmclock_periodic_sync)
1983 return;
1984
332967a3
AJ		 1985 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1986 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1987 KVMCLOCK_SYNC_PERIOD);
1988}
1989
890ca9ae 1990static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1991{
890ca9ae
HY		 1992 u64 mcg_cap = vcpu->arch.mcg_cap;
1993 unsigned bank_num = mcg_cap & 0xff;
1994
15c4a640 1995 switch (msr) {
15c4a640 1996 case MSR_IA32_MCG_STATUS:
890ca9ae 1997 vcpu->arch.mcg_status = data;
15c4a640 1998 break;
c7ac679c 1999 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2000 if (!(mcg_cap & MCG_CTL_P))
2001 return 1;
2002 if (data != 0 && data != ~(u64)0)
2003 return -1;
2004 vcpu->arch.mcg_ctl = data;
2005 break;
2006 default:
2007 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2008 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2009 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2010 /* only 0 or all 1s can be written to IA32_MCi_CTL
2011 * some Linux kernels though clear bit 10 in bank 4 to
2012 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2013 * this to avoid an uncatched #GP in the guest
2014 */
890ca9ae 2015 if ((offset & 0x3) == 0 &&
114be429 2016 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2017 return -1;
2018 vcpu->arch.mce_banks[offset] = data;
2019 break;
2020 }
2021 return 1;
2022 }
2023 return 0;
2024}
2025
ffde22ac
ES		 2026static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2027{
2028 struct kvm *kvm = vcpu->kvm;
2029 int lm = is_long_mode(vcpu);
2030 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2031 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2032 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2033 : kvm->arch.xen_hvm_config.blob_size_32;
2034 u32 page_num = data & ~PAGE_MASK;
2035 u64 page_addr = data & PAGE_MASK;
2036 u8 *page;
2037 int r;
2038
2039 r = -E2BIG;
2040 if (page_num >= blob_size)
2041 goto out;
2042 r = -ENOMEM;
ff5c2c03
SL		 2043 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2044 if (IS_ERR(page)) {
2045 r = PTR_ERR(page);
ffde22ac 2046 goto out;
ff5c2c03 2047 }
54bf36aa 2048 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2049 goto out_free;
2050 r = 0;
2051out_free:
2052 kfree(page);
2053out:
2054 return r;
2055}
2056
344d9588
GN		 2057static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2058{
2059 gpa_t gpa = data & ~0x3f;
2060
52a5c155
WL		 2061 /* Bits 3:5 are reserved, Should be zero */
2062 if (data & 0x38)
344d9588
GN		 2063 return 1;
2064
2065 vcpu->arch.apf.msr_val = data;
2066
2067 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2068 kvm_clear_async_pf_completion_queue(vcpu);
2069 kvm_async_pf_hash_reset(vcpu);
2070 return 0;
2071 }
2072
4e335d9e 2073 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2074 sizeof(u32)))
344d9588
GN		 2075 return 1;
2076
6adba527 2077 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2078 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2079 kvm_async_pf_wakeup_all(vcpu);
2080 return 0;
2081}
2082
12f9a48f
GC		 2083static void kvmclock_reset(struct kvm_vcpu *vcpu)
2084{
0b79459b 2085 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2086}
2087
c9aaa895
GC		 2088static void record_steal_time(struct kvm_vcpu *vcpu)
2089{
2090 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2091 return;
2092
4e335d9e 2093 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2094 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2095 return;
2096
0b9f6c46
PX		 2097 vcpu->arch.st.steal.preempted = 0;
2098
35f3fae1
WL		 2099 if (vcpu->arch.st.steal.version & 1)
2100 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2101
2102 vcpu->arch.st.steal.version += 1;
2103
4e335d9e 2104 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2105 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2106
2107 smp_wmb();
2108
c54cdf14
LC		 2109 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2110 vcpu->arch.st.last_steal;
2111 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2112
4e335d9e 2113 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2114 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2115
2116 smp_wmb();
2117
2118 vcpu->arch.st.steal.version += 1;
c9aaa895 2119
4e335d9e 2120 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2121 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2122}
2123
8fe8ab46 2124int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2125{
5753785f 2126 bool pr = false;
8fe8ab46
WA		 2127 u32 msr = msr_info->index;
2128 u64 data = msr_info->data;
5753785f 2129
15c4a640 2130 switch (msr) {
2e32b719
BP		 2131 case MSR_AMD64_NB_CFG:
2132 case MSR_IA32_UCODE_REV:
2133 case MSR_IA32_UCODE_WRITE:
2134 case MSR_VM_HSAVE_PA:
2135 case MSR_AMD64_PATCH_LOADER:
2136 case MSR_AMD64_BU_CFG2:
405a353a 2137 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2138 break;
2139
15c4a640 2140 case MSR_EFER:
b69e8cae 2141 return set_efer(vcpu, data);
8f1589d9
AP		 2142 case MSR_K7_HWCR:
2143 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2144 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2145 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2146 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2147 if (data != 0) {
a737f256
CD		 2148 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2149 data);
8f1589d9
AP		 2150 return 1;
2151 }
15c4a640 2152 break;
f7c6d140
AP		 2153 case MSR_FAM10H_MMIO_CONF_BASE:
2154 if (data != 0) {
a737f256
CD		 2155 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2156 "0x%llx\n", data);
f7c6d140
AP		 2157 return 1;
2158 }
15c4a640 2159 break;
b5e2fec0
AG		 2160 case MSR_IA32_DEBUGCTLMSR:
2161 if (!data) {
2162 /* We support the non-activated case already */
2163 break;
2164 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2165 /* Values other than LBR and BTF are vendor-specific,
2166 thus reserved and should throw a #GP */
2167 return 1;
2168 }
a737f256
CD		 2169 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2170 __func__, data);
b5e2fec0 2171 break;
9ba075a6 2172 case 0x200 ... 0x2ff:
ff53604b 2173 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2174 case MSR_IA32_APICBASE:
58cb628d 2175 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2176 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2177 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2178 case MSR_IA32_TSCDEADLINE:
2179 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2180 break;
ba904635 2181 case MSR_IA32_TSC_ADJUST:
d6321d49 2182 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2183 if (!msr_info->host_initiated) {
d913b904 2184 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2185 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2186 }
2187 vcpu->arch.ia32_tsc_adjust_msr = data;
2188 }
2189 break;
15c4a640 2190 case MSR_IA32_MISC_ENABLE:
ad312c7c 2191 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2192 break;
64d60670
PB		 2193 case MSR_IA32_SMBASE:
2194 if (!msr_info->host_initiated)
2195 return 1;
2196 vcpu->arch.smbase = data;
2197 break;
11c6bffa 2198 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2199 case MSR_KVM_WALL_CLOCK:
2200 vcpu->kvm->arch.wall_clock = data;
2201 kvm_write_wall_clock(vcpu->kvm, data);
2202 break;
11c6bffa 2203 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2204 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2205 struct kvm_arch *ka = &vcpu->kvm->arch;
2206
12f9a48f 2207 kvmclock_reset(vcpu);
18068523 2208
54750f2c
MT		 2209 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2210 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2211
2212 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2213 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2214
2215 ka->boot_vcpu_runs_old_kvmclock = tmp;
2216 }
2217
18068523 2218 vcpu->arch.time = data;
0061d53d 2219 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2220
2221 /* we verify if the enable bit is set... */
2222 if (!(data & 1))
2223 break;
2224
4e335d9e 2225 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2226 &vcpu->arch.pv_time, data & ~1ULL,
2227 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2228 vcpu->arch.pv_time_enabled = false;
2229 else
2230 vcpu->arch.pv_time_enabled = true;
32cad84f 2231
18068523
GOC		 2232 break;
2233 }
344d9588
GN		 2234 case MSR_KVM_ASYNC_PF_EN:
2235 if (kvm_pv_enable_async_pf(vcpu, data))
2236 return 1;
2237 break;
c9aaa895
GC		 2238 case MSR_KVM_STEAL_TIME:
2239
2240 if (unlikely(!sched_info_on()))
2241 return 1;
2242
2243 if (data & KVM_STEAL_RESERVED_MASK)
2244 return 1;
2245
4e335d9e 2246 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2247 data & KVM_STEAL_VALID_BITS,
2248 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2249 return 1;
2250
2251 vcpu->arch.st.msr_val = data;
2252
2253 if (!(data & KVM_MSR_ENABLED))
2254 break;
2255
c9aaa895
GC		 2256 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2257
2258 break;
ae7a2a3f
MT		 2259 case MSR_KVM_PV_EOI_EN:
2260 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2261 return 1;
2262 break;
c9aaa895 2263
890ca9ae
HY		 2264 case MSR_IA32_MCG_CTL:
2265 case MSR_IA32_MCG_STATUS:
81760dcc 2266 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2267 return set_msr_mce(vcpu, msr, data);
71db6023 2268
6912ac32
WH		 2269 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2270 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2271 pr = true; /* fall through */
2272 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2273 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2274 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2275 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2276
2277 if (pr || data != 0)
a737f256
CD		 2278 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2279 "0x%x data 0x%llx\n", msr, data);
5753785f 2280 break;
84e0cefa
JS		 2281 case MSR_K7_CLK_CTL:
2282 /*
2283 * Ignore all writes to this no longer documented MSR.
2284 * Writes are only relevant for old K7 processors,
2285 * all pre-dating SVM, but a recommended workaround from
4a969980 2286 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2287 * affected processor models on the command line, hence
2288 * the need to ignore the workaround.
2289 */
2290 break;
55cd8e5a 2291 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2292 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2293 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2294 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2295 return kvm_hv_set_msr_common(vcpu, msr, data,
2296 msr_info->host_initiated);
91c9c3ed 2297 case MSR_IA32_BBL_CR_CTL3:
2298 /* Drop writes to this legacy MSR -- see rdmsr
2299 * counterpart for further detail.
2300 */
796f4687 2301 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2302 break;
2b036c6b 2303 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2304 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2305 return 1;
2306 vcpu->arch.osvw.length = data;
2307 break;
2308 case MSR_AMD64_OSVW_STATUS:
d6321d49 2309 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2310 return 1;
2311 vcpu->arch.osvw.status = data;
2312 break;
db2336a8
KH		 2313 case MSR_PLATFORM_INFO:
2314 if (!msr_info->host_initiated ||
2315 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2316 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2317 cpuid_fault_enabled(vcpu)))
2318 return 1;
2319 vcpu->arch.msr_platform_info = data;
2320 break;
2321 case MSR_MISC_FEATURES_ENABLES:
2322 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2323 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2324 !supports_cpuid_fault(vcpu)))
2325 return 1;
2326 vcpu->arch.msr_misc_features_enables = data;
2327 break;
15c4a640 2328 default:
ffde22ac
ES		 2329 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2330 return xen_hvm_config(vcpu, data);
c6702c9d 2331 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2332 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2333 if (!ignore_msrs) {
ae0f5499 2334 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2335 msr, data);
ed85c068
AP		 2336 return 1;
2337 } else {
796f4687 2338 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2339 msr, data);
ed85c068
AP		 2340 break;
2341 }
15c4a640
CO		 2342 }
2343 return 0;
2344}
2345EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2346
2347
2348/*
2349 * Reads an msr value (of 'msr_index') into 'pdata'.
2350 * Returns 0 on success, non-0 otherwise.
2351 * Assumes vcpu_load() was already called.
2352 */
609e36d3 2353int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2354{
609e36d3 2355 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2356}
ff651cb6 2357EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2358
890ca9ae 2359static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2360{
2361 u64 data;
890ca9ae
HY		 2362 u64 mcg_cap = vcpu->arch.mcg_cap;
2363 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2364
2365 switch (msr) {
15c4a640
CO		 2366 case MSR_IA32_P5_MC_ADDR:
2367 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2368 data = 0;
2369 break;
15c4a640 2370 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2371 data = vcpu->arch.mcg_cap;
2372 break;
c7ac679c 2373 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2374 if (!(mcg_cap & MCG_CTL_P))
2375 return 1;
2376 data = vcpu->arch.mcg_ctl;
2377 break;
2378 case MSR_IA32_MCG_STATUS:
2379 data = vcpu->arch.mcg_status;
2380 break;
2381 default:
2382 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2383 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2384 u32 offset = msr - MSR_IA32_MC0_CTL;
2385 data = vcpu->arch.mce_banks[offset];
2386 break;
2387 }
2388 return 1;
2389 }
2390 *pdata = data;
2391 return 0;
2392}
2393
609e36d3 2394int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2395{
609e36d3 2396 switch (msr_info->index) {
890ca9ae 2397 case MSR_IA32_PLATFORM_ID:
15c4a640 2398 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2399 case MSR_IA32_DEBUGCTLMSR:
2400 case MSR_IA32_LASTBRANCHFROMIP:
2401 case MSR_IA32_LASTBRANCHTOIP:
2402 case MSR_IA32_LASTINTFROMIP:
2403 case MSR_IA32_LASTINTTOIP:
60af2ecd 2404 case MSR_K8_SYSCFG:
3afb1121
PB		 2405 case MSR_K8_TSEG_ADDR:
2406 case MSR_K8_TSEG_MASK:
60af2ecd 2407 case MSR_K7_HWCR:
61a6bd67 2408 case MSR_VM_HSAVE_PA:
1fdbd48c 2409 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2410 case MSR_AMD64_NB_CFG:
f7c6d140 2411 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2412 case MSR_AMD64_BU_CFG2:
0c2df2a1 2413 case MSR_IA32_PERF_CTL:
405a353a 2414 case MSR_AMD64_DC_CFG:
609e36d3 2415 msr_info->data = 0;
15c4a640 2416 break;
6912ac32
WH		 2417 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2418 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2419 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2420 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2421 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2422 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2423 msr_info->data = 0;
5753785f 2424 break;
742bc670 2425 case MSR_IA32_UCODE_REV:
609e36d3 2426 msr_info->data = 0x100000000ULL;
742bc670 2427 break;
9ba075a6 2428 case MSR_MTRRcap:
9ba075a6 2429 case 0x200 ... 0x2ff:
ff53604b 2430 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2431 case 0xcd: /* fsb frequency */
609e36d3 2432 msr_info->data = 3;
15c4a640 2433 break;
7b914098
JS		 2434 /*
2435 * MSR_EBC_FREQUENCY_ID
2436 * Conservative value valid for even the basic CPU models.
2437 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2438 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2439 * and 266MHz for model 3, or 4. Set Core Clock
2440 * Frequency to System Bus Frequency Ratio to 1 (bits
2441 * 31:24) even though these are only valid for CPU
2442 * models > 2, however guests may end up dividing or
2443 * multiplying by zero otherwise.
2444 */
2445 case MSR_EBC_FREQUENCY_ID:
609e36d3 2446 msr_info->data = 1 << 24;
7b914098 2447 break;
15c4a640 2448 case MSR_IA32_APICBASE:
609e36d3 2449 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2450 break;
0105d1a5 2451 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2452 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2453 break;
a3e06bbe 2454 case MSR_IA32_TSCDEADLINE:
609e36d3 2455 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2456 break;
ba904635 2457 case MSR_IA32_TSC_ADJUST:
609e36d3 2458 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2459 break;
15c4a640 2460 case MSR_IA32_MISC_ENABLE:
609e36d3 2461 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2462 break;
64d60670
PB		 2463 case MSR_IA32_SMBASE:
2464 if (!msr_info->host_initiated)
2465 return 1;
2466 msr_info->data = vcpu->arch.smbase;
15c4a640 2467 break;
847f0ad8
AG		 2468 case MSR_IA32_PERF_STATUS:
2469 /* TSC increment by tick */
609e36d3 2470 msr_info->data = 1000ULL;
847f0ad8 2471 /* CPU multiplier */
b0996ae4 2472 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2473 break;
15c4a640 2474 case MSR_EFER:
609e36d3 2475 msr_info->data = vcpu->arch.efer;
15c4a640 2476 break;
18068523 2477 case MSR_KVM_WALL_CLOCK:
11c6bffa 2478 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2479 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2480 break;
2481 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2482 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2483 msr_info->data = vcpu->arch.time;
18068523 2484 break;
344d9588 2485 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2486 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2487 break;
c9aaa895 2488 case MSR_KVM_STEAL_TIME:
609e36d3 2489 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2490 break;
1d92128f 2491 case MSR_KVM_PV_EOI_EN:
609e36d3 2492 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2493 break;
890ca9ae
HY		 2494 case MSR_IA32_P5_MC_ADDR:
2495 case MSR_IA32_P5_MC_TYPE:
2496 case MSR_IA32_MCG_CAP:
2497 case MSR_IA32_MCG_CTL:
2498 case MSR_IA32_MCG_STATUS:
81760dcc 2499 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2500 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2501 case MSR_K7_CLK_CTL:
2502 /*
2503 * Provide expected ramp-up count for K7. All other
2504 * are set to zero, indicating minimum divisors for
2505 * every field.
2506 *
2507 * This prevents guest kernels on AMD host with CPU
2508 * type 6, model 8 and higher from exploding due to
2509 * the rdmsr failing.
2510 */
609e36d3 2511 msr_info->data = 0x20000000;
84e0cefa 2512 break;
55cd8e5a 2513 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2514 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2515 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2516 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2517 return kvm_hv_get_msr_common(vcpu,
2518 msr_info->index, &msr_info->data);
55cd8e5a 2519 break;
91c9c3ed 2520 case MSR_IA32_BBL_CR_CTL3:
2521 /* This legacy MSR exists but isn't fully documented in current
2522 * silicon. It is however accessed by winxp in very narrow
2523 * scenarios where it sets bit #19, itself documented as
2524 * a "reserved" bit. Best effort attempt to source coherent
2525 * read data here should the balance of the register be
2526 * interpreted by the guest:
2527 *
2528 * L2 cache control register 3: 64GB range, 256KB size,
2529 * enabled, latency 0x1, configured
2530 */
609e36d3 2531 msr_info->data = 0xbe702111;
91c9c3ed 2532 break;
2b036c6b 2533 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2534 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2535 return 1;
609e36d3 2536 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2537 break;
2538 case MSR_AMD64_OSVW_STATUS:
d6321d49 2539 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2540 return 1;
609e36d3 2541 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2542 break;
db2336a8
KH		 2543 case MSR_PLATFORM_INFO:
2544 msr_info->data = vcpu->arch.msr_platform_info;
2545 break;
2546 case MSR_MISC_FEATURES_ENABLES:
2547 msr_info->data = vcpu->arch.msr_misc_features_enables;
2548 break;
15c4a640 2549 default:
c6702c9d 2550 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2551 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2552 if (!ignore_msrs) {
ae0f5499
BD		 2553 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2554 msr_info->index);
ed85c068
AP		 2555 return 1;
2556 } else {
609e36d3
PB		 2557 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2558 msr_info->data = 0;
ed85c068
AP		 2559 }
2560 break;
15c4a640 2561 }
15c4a640
CO		 2562 return 0;
2563}
2564EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2565
313a3dc7
CO		 2566/*
2567 * Read or write a bunch of msrs. All parameters are kernel addresses.
2568 *
2569 * @return number of msrs set successfully.
2570 */
2571static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2572 struct kvm_msr_entry *entries,
2573 int (*do_msr)(struct kvm_vcpu *vcpu,
2574 unsigned index, u64 *data))
2575{
f656ce01 2576 int i, idx;
313a3dc7 2577
f656ce01 2578 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2579 for (i = 0; i < msrs->nmsrs; ++i)
2580 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2581 break;
f656ce01 2582 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2583
313a3dc7
CO		 2584 return i;
2585}
2586
2587/*
2588 * Read or write a bunch of msrs. Parameters are user addresses.
2589 *
2590 * @return number of msrs set successfully.
2591 */
2592static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2593 int (*do_msr)(struct kvm_vcpu *vcpu,
2594 unsigned index, u64 *data),
2595 int writeback)
2596{
2597 struct kvm_msrs msrs;
2598 struct kvm_msr_entry *entries;
2599 int r, n;
2600 unsigned size;
2601
2602 r = -EFAULT;
2603 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2604 goto out;
2605
2606 r = -E2BIG;
2607 if (msrs.nmsrs >= MAX_IO_MSRS)
2608 goto out;
2609
313a3dc7 2610 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2611 entries = memdup_user(user_msrs->entries, size);
2612 if (IS_ERR(entries)) {
2613 r = PTR_ERR(entries);
313a3dc7 2614 goto out;
ff5c2c03 2615 }
313a3dc7
CO		 2616
2617 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2618 if (r < 0)
2619 goto out_free;
2620
2621 r = -EFAULT;
2622 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2623 goto out_free;
2624
2625 r = n;
2626
2627out_free:
7a73c028 2628 kfree(entries);
313a3dc7
CO		 2629out:
2630 return r;
2631}
2632
784aa3d7 2633int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2634{
2635 int r;
2636
2637 switch (ext) {
2638 case KVM_CAP_IRQCHIP:
2639 case KVM_CAP_HLT:
2640 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2641 case KVM_CAP_SET_TSS_ADDR:
07716717 2642 case KVM_CAP_EXT_CPUID:
9c15bb1d 2643 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2644 case KVM_CAP_CLOCKSOURCE:
7837699f 2645 case KVM_CAP_PIT:
a28e4f5a 2646 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2647 case KVM_CAP_MP_STATE:
ed848624 2648 case KVM_CAP_SYNC_MMU:
a355c85c 2649 case KVM_CAP_USER_NMI:
52d939a0 2650 case KVM_CAP_REINJECT_CONTROL:
4925663a 2651 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2652 case KVM_CAP_IOEVENTFD:
f848a5a8 2653 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2654 case KVM_CAP_PIT2:
e9f42757 2655 case KVM_CAP_PIT_STATE2:
b927a3ce 2656 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2657 case KVM_CAP_XEN_HVM:
3cfc3092 2658 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2659 case KVM_CAP_HYPERV:
10388a07 2660 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2661 case KVM_CAP_HYPERV_SPIN:
5c919412 2662 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2663 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2664 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2665 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2666 case KVM_CAP_DEBUGREGS:
d2be1651 2667 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2668 case KVM_CAP_XSAVE:
344d9588 2669 case KVM_CAP_ASYNC_PF:
92a1f12d 2670 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2671 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2672 case KVM_CAP_READONLY_MEM:
5f66b620 2673 case KVM_CAP_HYPERV_TIME:
100943c5 2674 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2675 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2676 case KVM_CAP_ENABLE_CAP_VM:
2677 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2678 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2679 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2680 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2681 r = 1;
2682 break;
e3fd9a93
PB		 2683 case KVM_CAP_ADJUST_CLOCK:
2684 r = KVM_CLOCK_TSC_STABLE;
2685 break;
668fffa3
MT		 2686 case KVM_CAP_X86_GUEST_MWAIT:
2687 r = kvm_mwait_in_guest();
2688 break;
6d396b55
PB		 2689 case KVM_CAP_X86_SMM:
2690 /* SMBASE is usually relocated above 1M on modern chipsets,
2691 * and SMM handlers might indeed rely on 4G segment limits,
2692 * so do not report SMM to be available if real mode is
2693 * emulated via vm86 mode. Still, do not go to great lengths
2694 * to avoid userspace's usage of the feature, because it is a
2695 * fringe case that is not enabled except via specific settings
2696 * of the module parameters.
2697 */
2698 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2699 break;
774ead3a
AK		 2700 case KVM_CAP_VAPIC:
2701 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2702 break;
f725230a 2703 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2704 r = KVM_SOFT_MAX_VCPUS;
2705 break;
2706 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2707 r = KVM_MAX_VCPUS;
2708 break;
a988b910 2709 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2710 r = KVM_USER_MEM_SLOTS;
a988b910 2711 break;
a68a6a72
MT		 2712 case KVM_CAP_PV_MMU: /* obsolete */
2713 r = 0;
2f333bcb 2714 break;
890ca9ae
HY		 2715 case KVM_CAP_MCE:
2716 r = KVM_MAX_MCE_BANKS;
2717 break;
2d5b5a66 2718 case KVM_CAP_XCRS:
d366bf7e 2719 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2720 break;
92a1f12d
JR		 2721 case KVM_CAP_TSC_CONTROL:
2722 r = kvm_has_tsc_control;
2723 break;
37131313
RK		 2724 case KVM_CAP_X2APIC_API:
2725 r = KVM_X2APIC_API_VALID_FLAGS;
2726 break;
018d00d2
ZX		 2727 default:
2728 r = 0;
2729 break;
2730 }
2731 return r;
2732
2733}
2734
043405e1
CO		 2735long kvm_arch_dev_ioctl(struct file *filp,
2736 unsigned int ioctl, unsigned long arg)
2737{
2738 void __user *argp = (void __user *)arg;
2739 long r;
2740
2741 switch (ioctl) {
2742 case KVM_GET_MSR_INDEX_LIST: {
2743 struct kvm_msr_list __user *user_msr_list = argp;
2744 struct kvm_msr_list msr_list;
2745 unsigned n;
2746
2747 r = -EFAULT;
2748 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2749 goto out;
2750 n = msr_list.nmsrs;
62ef68bb 2751 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2752 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2753 goto out;
2754 r = -E2BIG;
e125e7b6 2755 if (n < msr_list.nmsrs)
043405e1
CO		 2756 goto out;
2757 r = -EFAULT;
2758 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2759 num_msrs_to_save * sizeof(u32)))
2760 goto out;
e125e7b6 2761 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2762 &emulated_msrs,
62ef68bb 2763 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2764 goto out;
2765 r = 0;
2766 break;
2767 }
9c15bb1d
BP		 2768 case KVM_GET_SUPPORTED_CPUID:
2769 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2770 struct kvm_cpuid2 __user *cpuid_arg = argp;
2771 struct kvm_cpuid2 cpuid;
2772
2773 r = -EFAULT;
2774 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2775 goto out;
9c15bb1d
BP		 2776
2777 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2778 ioctl);
674eea0f
AK		 2779 if (r)
2780 goto out;
2781
2782 r = -EFAULT;
2783 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2784 goto out;
2785 r = 0;
2786 break;
2787 }
890ca9ae 2788 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2789 r = -EFAULT;
c45dcc71
AR		 2790 if (copy_to_user(argp, &kvm_mce_cap_supported,
2791 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2792 goto out;
2793 r = 0;
2794 break;
2795 }
043405e1
CO		 2796 default:
2797 r = -EINVAL;
2798 }
2799out:
2800 return r;
2801}
2802
f5f48ee1
SY		 2803static void wbinvd_ipi(void *garbage)
2804{
2805 wbinvd();
2806}
2807
2808static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2809{
e0f0bbc5 2810 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2811}
2812
313a3dc7
CO		 2813void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2814{
f5f48ee1
SY		 2815 /* Address WBINVD may be executed by guest */
2816 if (need_emulate_wbinvd(vcpu)) {
2817 if (kvm_x86_ops->has_wbinvd_exit())
2818 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2819 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2820 smp_call_function_single(vcpu->cpu,
2821 wbinvd_ipi, NULL, 1);
2822 }
2823
313a3dc7 2824 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2825
0dd6a6ed
ZA		 2826 /* Apply any externally detected TSC adjustments (due to suspend) */
2827 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2828 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2829 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2830 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2831 }
8f6055cb 2832
48434c20 2833 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2834 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2835 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2836 if (tsc_delta < 0)
2837 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2838
c285545f 2839 if (check_tsc_unstable()) {
07c1419a 2840 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2841 vcpu->arch.last_guest_tsc);
a545ab6a 2842 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2843 vcpu->arch.tsc_catchup = 1;
c285545f 2844 }
a749e247
PB		 2845
2846 if (kvm_lapic_hv_timer_in_use(vcpu))
2847 kvm_lapic_restart_hv_timer(vcpu);
2848
d98d07ca
MT		 2849 /*
2850 * On a host with synchronized TSC, there is no need to update
2851 * kvmclock on vcpu->cpu migration
2852 */
2853 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2854 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2855 if (vcpu->cpu != cpu)
1bd2009e 2856 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2857 vcpu->cpu = cpu;
6b7d7e76 2858 }
c9aaa895 2859
c9aaa895 2860 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2861}
2862
0b9f6c46
PX		 2863static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2864{
2865 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2866 return;
2867
2868 vcpu->arch.st.steal.preempted = 1;
2869
4e335d9e 2870 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2871 &vcpu->arch.st.steal.preempted,
2872 offsetof(struct kvm_steal_time, preempted),
2873 sizeof(vcpu->arch.st.steal.preempted));
2874}
2875
313a3dc7
CO		 2876void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2877{
cc0d907c 2878 int idx;
de63ad4c
LM		 2879
2880 if (vcpu->preempted)
2881 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2882
931f261b
AA		 2883 /*
2884 * Disable page faults because we're in atomic context here.
2885 * kvm_write_guest_offset_cached() would call might_fault()
2886 * that relies on pagefault_disable() to tell if there's a
2887 * bug. NOTE: the write to guest memory may not go through if
2888 * during postcopy live migration or if there's heavy guest
2889 * paging.
2890 */
2891 pagefault_disable();
cc0d907c
AA		 2892 /*
2893 * kvm_memslots() will be called by
2894 * kvm_write_guest_offset_cached() so take the srcu lock.
2895 */
2896 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2897 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2898 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2899 pagefault_enable();
02daab21 2900 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2901 kvm_put_guest_fpu(vcpu);
4ea1636b 2902 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2903}
2904
313a3dc7
CO		 2905static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2906 struct kvm_lapic_state *s)
2907{
76dfafd5 2908 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2909 kvm_x86_ops->sync_pir_to_irr(vcpu);
2910
a92e2543 2911 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2912}
2913
2914static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2915 struct kvm_lapic_state *s)
2916{
a92e2543
RK		 2917 int r;
2918
2919 r = kvm_apic_set_state(vcpu, s);
2920 if (r)
2921 return r;
cb142eb7 2922 update_cr8_intercept(vcpu);
313a3dc7
CO		 2923
2924 return 0;
2925}
2926
127a457a
MG		 2927static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2928{
2929 return (!lapic_in_kernel(vcpu) ||
2930 kvm_apic_accept_pic_intr(vcpu));
2931}
2932
782d422b
MG		 2933/*
2934 * if userspace requested an interrupt window, check that the
2935 * interrupt window is open.
2936 *
2937 * No need to exit to userspace if we already have an interrupt queued.
2938 */
2939static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2940{
2941 return kvm_arch_interrupt_allowed(vcpu) &&
2942 !kvm_cpu_has_interrupt(vcpu) &&
2943 !kvm_event_needs_reinjection(vcpu) &&
2944 kvm_cpu_accept_dm_intr(vcpu);
2945}
2946
f77bc6a4
ZX		 2947static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2948 struct kvm_interrupt *irq)
2949{
02cdb50f 2950 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2951 return -EINVAL;
1c1a9ce9
SR		 2952
2953 if (!irqchip_in_kernel(vcpu->kvm)) {
2954 kvm_queue_interrupt(vcpu, irq->irq, false);
2955 kvm_make_request(KVM_REQ_EVENT, vcpu);
2956 return 0;
2957 }
2958
2959 /*
2960 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2961 * fail for in-kernel 8259.
2962 */
2963 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2964 return -ENXIO;
f77bc6a4 2965
1c1a9ce9
SR		 2966 if (vcpu->arch.pending_external_vector != -1)
2967 return -EEXIST;
f77bc6a4 2968
1c1a9ce9 2969 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2970 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2971 return 0;
2972}
2973
c4abb7c9
JK		 2974static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2975{
c4abb7c9 2976 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2977
2978 return 0;
2979}
2980
f077825a
PB		 2981static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2982{
64d60670
PB		 2983 kvm_make_request(KVM_REQ_SMI, vcpu);
2984
f077825a
PB		 2985 return 0;
2986}
2987
b209749f
AK		 2988static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2989 struct kvm_tpr_access_ctl *tac)
2990{
2991 if (tac->flags)
2992 return -EINVAL;
2993 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2994 return 0;
2995}
2996
890ca9ae
HY		 2997static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2998 u64 mcg_cap)
2999{
3000 int r;
3001 unsigned bank_num = mcg_cap & 0xff, bank;
3002
3003 r = -EINVAL;
a9e38c3e 3004 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3005 goto out;
c45dcc71 3006 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3007 goto out;
3008 r = 0;
3009 vcpu->arch.mcg_cap = mcg_cap;
3010 /* Init IA32_MCG_CTL to all 1s */
3011 if (mcg_cap & MCG_CTL_P)
3012 vcpu->arch.mcg_ctl = ~(u64)0;
3013 /* Init IA32_MCi_CTL to all 1s */
3014 for (bank = 0; bank < bank_num; bank++)
3015 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3016
3017 if (kvm_x86_ops->setup_mce)
3018 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3019out:
3020 return r;
3021}
3022
3023static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3024 struct kvm_x86_mce *mce)
3025{
3026 u64 mcg_cap = vcpu->arch.mcg_cap;
3027 unsigned bank_num = mcg_cap & 0xff;
3028 u64 *banks = vcpu->arch.mce_banks;
3029
3030 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3031 return -EINVAL;
3032 /*
3033 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3034 * reporting is disabled
3035 */
3036 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3037 vcpu->arch.mcg_ctl != ~(u64)0)
3038 return 0;
3039 banks += 4 * mce->bank;
3040 /*
3041 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3042 * reporting is disabled for the bank
3043 */
3044 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3045 return 0;
3046 if (mce->status & MCI_STATUS_UC) {
3047 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3048 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3049 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3050 return 0;
3051 }
3052 if (banks[1] & MCI_STATUS_VAL)
3053 mce->status |= MCI_STATUS_OVER;
3054 banks[2] = mce->addr;
3055 banks[3] = mce->misc;
3056 vcpu->arch.mcg_status = mce->mcg_status;
3057 banks[1] = mce->status;
3058 kvm_queue_exception(vcpu, MC_VECTOR);
3059 } else if (!(banks[1] & MCI_STATUS_VAL)
3060 || !(banks[1] & MCI_STATUS_UC)) {
3061 if (banks[1] & MCI_STATUS_VAL)
3062 mce->status |= MCI_STATUS_OVER;
3063 banks[2] = mce->addr;
3064 banks[3] = mce->misc;
3065 banks[1] = mce->status;
3066 } else
3067 banks[1] |= MCI_STATUS_OVER;
3068 return 0;
3069}
3070
3cfc3092
JK		 3071static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3072 struct kvm_vcpu_events *events)
3073{
7460fb4a 3074 process_nmi(vcpu);
03b82a30
JK		 3075 events->exception.injected =
3076 vcpu->arch.exception.pending &&
3077 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3078 events->exception.nr = vcpu->arch.exception.nr;
3079 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3080 events->exception.pad = 0;
3cfc3092
JK		 3081 events->exception.error_code = vcpu->arch.exception.error_code;
3082
03b82a30
JK		 3083 events->interrupt.injected =
3084 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3085 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3086 events->interrupt.soft = 0;
37ccdcbe 3087 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3088
3089 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3090 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3091 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3092 events->nmi.pad = 0;
3cfc3092 3093
66450a21 3094 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3095
f077825a
PB		 3096 events->smi.smm = is_smm(vcpu);
3097 events->smi.pending = vcpu->arch.smi_pending;
3098 events->smi.smm_inside_nmi =
3099 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3100 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3101
dab4b911 3102 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3103 | KVM_VCPUEVENT_VALID_SHADOW
3104 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3105 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3106}
3107
6ef4e07e
XG		 3108static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3109
3cfc3092
JK		 3110static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3111 struct kvm_vcpu_events *events)
3112{
dab4b911 3113 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3114 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3115 | KVM_VCPUEVENT_VALID_SHADOW
3116 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3117 return -EINVAL;
3118
78e546c8 3119 if (events->exception.injected &&
28d06353
JM		 3120 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3121 is_guest_mode(vcpu)))
78e546c8
PB		 3122 return -EINVAL;
3123
28bf2888
DH		 3124 /* INITs are latched while in SMM */
3125 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3126 (events->smi.smm || events->smi.pending) &&
3127 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3128 return -EINVAL;
3129
7460fb4a 3130 process_nmi(vcpu);
3cfc3092
JK		 3131 vcpu->arch.exception.pending = events->exception.injected;
3132 vcpu->arch.exception.nr = events->exception.nr;
3133 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3134 vcpu->arch.exception.error_code = events->exception.error_code;
3135
3136 vcpu->arch.interrupt.pending = events->interrupt.injected;
3137 vcpu->arch.interrupt.nr = events->interrupt.nr;
3138 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3139 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3140 kvm_x86_ops->set_interrupt_shadow(vcpu,
3141 events->interrupt.shadow);
3cfc3092
JK		 3142
3143 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3144 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3145 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3146 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3147
66450a21 3148 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3149 lapic_in_kernel(vcpu))
66450a21 3150 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3151
f077825a 3152 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3153 u32 hflags = vcpu->arch.hflags;
f077825a 3154 if (events->smi.smm)
6ef4e07e 3155 hflags |= HF_SMM_MASK;
f077825a 3156 else
6ef4e07e
XG		 3157 hflags &= ~HF_SMM_MASK;
3158 kvm_set_hflags(vcpu, hflags);
3159
f077825a 3160 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3161
3162 if (events->smi.smm) {
3163 if (events->smi.smm_inside_nmi)
3164 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3165 else
f4ef1910
WL		 3166 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3167 if (lapic_in_kernel(vcpu)) {
3168 if (events->smi.latched_init)
3169 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3170 else
3171 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3172 }
f077825a
PB		 3173 }
3174 }
3175
3842d135
AK		 3176 kvm_make_request(KVM_REQ_EVENT, vcpu);
3177
3cfc3092
JK		 3178 return 0;
3179}
3180
a1efbe77
JK		 3181static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3182 struct kvm_debugregs *dbgregs)
3183{
73aaf249
JK		 3184 unsigned long val;
3185
a1efbe77 3186 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3187 kvm_get_dr(vcpu, 6, &val);
73aaf249 3188 dbgregs->dr6 = val;
a1efbe77
JK		 3189 dbgregs->dr7 = vcpu->arch.dr7;
3190 dbgregs->flags = 0;
97e69aa6 3191 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3192}
3193
3194static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3195 struct kvm_debugregs *dbgregs)
3196{
3197 if (dbgregs->flags)
3198 return -EINVAL;
3199
d14bdb55
PB		 3200 if (dbgregs->dr6 & ~0xffffffffull)
3201 return -EINVAL;
3202 if (dbgregs->dr7 & ~0xffffffffull)
3203 return -EINVAL;
3204
a1efbe77 3205 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3206 kvm_update_dr0123(vcpu);
a1efbe77 3207 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3208 kvm_update_dr6(vcpu);
a1efbe77 3209 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3210 kvm_update_dr7(vcpu);
a1efbe77 3211
a1efbe77
JK		 3212 return 0;
3213}
3214
df1daba7
PB		 3215#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3216
3217static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3218{
c47ada30 3219 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3220 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3221 u64 valid;
3222
3223 /*
3224 * Copy legacy XSAVE area, to avoid complications with CPUID
3225 * leaves 0 and 1 in the loop below.
3226 */
3227 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3228
3229 /* Set XSTATE_BV */
00c87e9a 3230 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3231 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3232
3233 /*
3234 * Copy each region from the possibly compacted offset to the
3235 * non-compacted offset.
3236 */
d91cab78 3237 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3238 while (valid) {
3239 u64 feature = valid & -valid;
3240 int index = fls64(feature) - 1;
3241 void *src = get_xsave_addr(xsave, feature);
3242
3243 if (src) {
3244 u32 size, offset, ecx, edx;
3245 cpuid_count(XSTATE_CPUID, index,
3246 &size, &offset, &ecx, &edx);
3247 memcpy(dest + offset, src, size);
3248 }
3249
3250 valid -= feature;
3251 }
3252}
3253
3254static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3255{
c47ada30 3256 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3257 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3258 u64 valid;
3259
3260 /*
3261 * Copy legacy XSAVE area, to avoid complications with CPUID
3262 * leaves 0 and 1 in the loop below.
3263 */
3264 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3265
3266 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3267 xsave->header.xfeatures = xstate_bv;
782511b0 3268 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3269 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3270
3271 /*
3272 * Copy each region from the non-compacted offset to the
3273 * possibly compacted offset.
3274 */
d91cab78 3275 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3276 while (valid) {
3277 u64 feature = valid & -valid;
3278 int index = fls64(feature) - 1;
3279 void *dest = get_xsave_addr(xsave, feature);
3280
3281 if (dest) {
3282 u32 size, offset, ecx, edx;
3283 cpuid_count(XSTATE_CPUID, index,
3284 &size, &offset, &ecx, &edx);
3285 memcpy(dest, src + offset, size);
ee4100da 3286 }
df1daba7
PB		 3287
3288 valid -= feature;
3289 }
3290}
3291
2d5b5a66
SY		 3292static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3293 struct kvm_xsave *guest_xsave)
3294{
d366bf7e 3295 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3296 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3297 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3298 } else {
2d5b5a66 3299 memcpy(guest_xsave->region,
7366ed77 3300 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3301 sizeof(struct fxregs_state));
2d5b5a66 3302 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3303 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3304 }
3305}
3306
a575813b
WL		 3307#define XSAVE_MXCSR_OFFSET 24
3308
2d5b5a66
SY		 3309static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3310 struct kvm_xsave *guest_xsave)
3311{
3312 u64 xstate_bv =
3313 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3314 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3315
d366bf7e 3316 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3317 /*
3318 * Here we allow setting states that are not present in
3319 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3320 * with old userspace.
3321 */
a575813b
WL		 3322 if (xstate_bv & ~kvm_supported_xcr0() ||
3323 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3324 return -EINVAL;
df1daba7 3325 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3326 } else {
a575813b
WL		 3327 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3328 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3329 return -EINVAL;
7366ed77 3330 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3331 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3332 }
3333 return 0;
3334}
3335
3336static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3337 struct kvm_xcrs *guest_xcrs)
3338{
d366bf7e 3339 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3340 guest_xcrs->nr_xcrs = 0;
3341 return;
3342 }
3343
3344 guest_xcrs->nr_xcrs = 1;
3345 guest_xcrs->flags = 0;
3346 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3347 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3348}
3349
3350static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3351 struct kvm_xcrs *guest_xcrs)
3352{
3353 int i, r = 0;
3354
d366bf7e 3355 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3356 return -EINVAL;
3357
3358 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3359 return -EINVAL;
3360
3361 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3362 /* Only support XCR0 currently */
c67a04cb 3363 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3364 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3365 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3366 break;
3367 }
3368 if (r)
3369 r = -EINVAL;
3370 return r;
3371}
3372
1c0b28c2
EM		 3373/*
3374 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3375 * stopped by the hypervisor. This function will be called from the host only.
3376 * EINVAL is returned when the host attempts to set the flag for a guest that
3377 * does not support pv clocks.
3378 */
3379static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3380{
0b79459b 3381 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3382 return -EINVAL;
51d59c6b 3383 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3384 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3385 return 0;
3386}
3387
5c919412
AS		 3388static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3389 struct kvm_enable_cap *cap)
3390{
3391 if (cap->flags)
3392 return -EINVAL;
3393
3394 switch (cap->cap) {
efc479e6
RK		 3395 case KVM_CAP_HYPERV_SYNIC2:
3396 if (cap->args[0])
3397 return -EINVAL;
5c919412 3398 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3399 if (!irqchip_in_kernel(vcpu->kvm))
3400 return -EINVAL;
efc479e6
RK		 3401 return kvm_hv_activate_synic(vcpu, cap->cap ==
3402 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3403 default:
3404 return -EINVAL;
3405 }
3406}
3407
313a3dc7
CO		 3408long kvm_arch_vcpu_ioctl(struct file *filp,
3409 unsigned int ioctl, unsigned long arg)
3410{
3411 struct kvm_vcpu *vcpu = filp->private_data;
3412 void __user *argp = (void __user *)arg;
3413 int r;
d1ac91d8
AK		 3414 union {
3415 struct kvm_lapic_state *lapic;
3416 struct kvm_xsave *xsave;
3417 struct kvm_xcrs *xcrs;
3418 void *buffer;
3419 } u;
3420
3421 u.buffer = NULL;
313a3dc7
CO		 3422 switch (ioctl) {
3423 case KVM_GET_LAPIC: {
2204ae3c 3424 r = -EINVAL;
bce87cce 3425 if (!lapic_in_kernel(vcpu))
2204ae3c 3426 goto out;
d1ac91d8 3427 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3428
b772ff36 3429 r = -ENOMEM;
d1ac91d8 3430 if (!u.lapic)
b772ff36 3431 goto out;
d1ac91d8 3432 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3433 if (r)
3434 goto out;
3435 r = -EFAULT;
d1ac91d8 3436 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3437 goto out;
3438 r = 0;
3439 break;
3440 }
3441 case KVM_SET_LAPIC: {
2204ae3c 3442 r = -EINVAL;
bce87cce 3443 if (!lapic_in_kernel(vcpu))
2204ae3c 3444 goto out;
ff5c2c03 3445 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3446 if (IS_ERR(u.lapic))
3447 return PTR_ERR(u.lapic);
ff5c2c03 3448
d1ac91d8 3449 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3450 break;
3451 }
f77bc6a4
ZX		 3452 case KVM_INTERRUPT: {
3453 struct kvm_interrupt irq;
3454
3455 r = -EFAULT;
3456 if (copy_from_user(&irq, argp, sizeof irq))
3457 goto out;
3458 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3459 break;
3460 }
c4abb7c9
JK		 3461 case KVM_NMI: {
3462 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3463 break;
3464 }
f077825a
PB		 3465 case KVM_SMI: {
3466 r = kvm_vcpu_ioctl_smi(vcpu);
3467 break;
3468 }
313a3dc7
CO		 3469 case KVM_SET_CPUID: {
3470 struct kvm_cpuid __user *cpuid_arg = argp;
3471 struct kvm_cpuid cpuid;
3472
3473 r = -EFAULT;
3474 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3475 goto out;
3476 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3477 break;
3478 }
07716717
DK		 3479 case KVM_SET_CPUID2: {
3480 struct kvm_cpuid2 __user *cpuid_arg = argp;
3481 struct kvm_cpuid2 cpuid;
3482
3483 r = -EFAULT;
3484 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3485 goto out;
3486 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3487 cpuid_arg->entries);
07716717
DK		 3488 break;
3489 }
3490 case KVM_GET_CPUID2: {
3491 struct kvm_cpuid2 __user *cpuid_arg = argp;
3492 struct kvm_cpuid2 cpuid;
3493
3494 r = -EFAULT;
3495 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3496 goto out;
3497 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3498 cpuid_arg->entries);
07716717
DK		 3499 if (r)
3500 goto out;
3501 r = -EFAULT;
3502 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3503 goto out;
3504 r = 0;
3505 break;
3506 }
313a3dc7 3507 case KVM_GET_MSRS:
609e36d3 3508 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3509 break;
3510 case KVM_SET_MSRS:
3511 r = msr_io(vcpu, argp, do_set_msr, 0);
3512 break;
b209749f
AK		 3513 case KVM_TPR_ACCESS_REPORTING: {
3514 struct kvm_tpr_access_ctl tac;
3515
3516 r = -EFAULT;
3517 if (copy_from_user(&tac, argp, sizeof tac))
3518 goto out;
3519 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3520 if (r)
3521 goto out;
3522 r = -EFAULT;
3523 if (copy_to_user(argp, &tac, sizeof tac))
3524 goto out;
3525 r = 0;
3526 break;
3527 };
b93463aa
AK		 3528 case KVM_SET_VAPIC_ADDR: {
3529 struct kvm_vapic_addr va;
7301d6ab 3530 int idx;
b93463aa
AK		 3531
3532 r = -EINVAL;
35754c98 3533 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3534 goto out;
3535 r = -EFAULT;
3536 if (copy_from_user(&va, argp, sizeof va))
3537 goto out;
7301d6ab 3538 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3539 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3540 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3541 break;
3542 }
890ca9ae
HY		 3543 case KVM_X86_SETUP_MCE: {
3544 u64 mcg_cap;
3545
3546 r = -EFAULT;
3547 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3548 goto out;
3549 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3550 break;
3551 }
3552 case KVM_X86_SET_MCE: {
3553 struct kvm_x86_mce mce;
3554
3555 r = -EFAULT;
3556 if (copy_from_user(&mce, argp, sizeof mce))
3557 goto out;
3558 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3559 break;
3560 }
3cfc3092
JK		 3561 case KVM_GET_VCPU_EVENTS: {
3562 struct kvm_vcpu_events events;
3563
3564 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3565
3566 r = -EFAULT;
3567 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3568 break;
3569 r = 0;
3570 break;
3571 }
3572 case KVM_SET_VCPU_EVENTS: {
3573 struct kvm_vcpu_events events;
3574
3575 r = -EFAULT;
3576 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3577 break;
3578
3579 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3580 break;
3581 }
a1efbe77
JK		 3582 case KVM_GET_DEBUGREGS: {
3583 struct kvm_debugregs dbgregs;
3584
3585 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3586
3587 r = -EFAULT;
3588 if (copy_to_user(argp, &dbgregs,
3589 sizeof(struct kvm_debugregs)))
3590 break;
3591 r = 0;
3592 break;
3593 }
3594 case KVM_SET_DEBUGREGS: {
3595 struct kvm_debugregs dbgregs;
3596
3597 r = -EFAULT;
3598 if (copy_from_user(&dbgregs, argp,
3599 sizeof(struct kvm_debugregs)))
3600 break;
3601
3602 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3603 break;
3604 }
2d5b5a66 3605 case KVM_GET_XSAVE: {
d1ac91d8 3606 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3607 r = -ENOMEM;
d1ac91d8 3608 if (!u.xsave)
2d5b5a66
SY		 3609 break;
3610
d1ac91d8 3611 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3612
3613 r = -EFAULT;
d1ac91d8 3614 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3615 break;
3616 r = 0;
3617 break;
3618 }
3619 case KVM_SET_XSAVE: {
ff5c2c03 3620 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3621 if (IS_ERR(u.xsave))
3622 return PTR_ERR(u.xsave);
2d5b5a66 3623
d1ac91d8 3624 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3625 break;
3626 }
3627 case KVM_GET_XCRS: {
d1ac91d8 3628 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3629 r = -ENOMEM;
d1ac91d8 3630 if (!u.xcrs)
2d5b5a66
SY		 3631 break;
3632
d1ac91d8 3633 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3634
3635 r = -EFAULT;
d1ac91d8 3636 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3637 sizeof(struct kvm_xcrs)))
3638 break;
3639 r = 0;
3640 break;
3641 }
3642 case KVM_SET_XCRS: {
ff5c2c03 3643 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3644 if (IS_ERR(u.xcrs))
3645 return PTR_ERR(u.xcrs);
2d5b5a66 3646
d1ac91d8 3647 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3648 break;
3649 }
92a1f12d
JR		 3650 case KVM_SET_TSC_KHZ: {
3651 u32 user_tsc_khz;
3652
3653 r = -EINVAL;
92a1f12d
JR		 3654 user_tsc_khz = (u32)arg;
3655
3656 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3657 goto out;
3658
cc578287
ZA		 3659 if (user_tsc_khz == 0)
3660 user_tsc_khz = tsc_khz;
3661
381d585c
HZ		 3662 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3663 r = 0;
92a1f12d 3664
92a1f12d
JR		 3665 goto out;
3666 }
3667 case KVM_GET_TSC_KHZ: {
cc578287 3668 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3669 goto out;
3670 }
1c0b28c2
EM		 3671 case KVM_KVMCLOCK_CTRL: {
3672 r = kvm_set_guest_paused(vcpu);
3673 goto out;
3674 }
5c919412
AS		 3675 case KVM_ENABLE_CAP: {
3676 struct kvm_enable_cap cap;
3677
3678 r = -EFAULT;
3679 if (copy_from_user(&cap, argp, sizeof(cap)))
3680 goto out;
3681 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3682 break;
3683 }
313a3dc7
CO		 3684 default:
3685 r = -EINVAL;
3686 }
3687out:
d1ac91d8 3688 kfree(u.buffer);
313a3dc7
CO		 3689 return r;
3690}
3691
5b1c1493
CO		 3692int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3693{
3694 return VM_FAULT_SIGBUS;
3695}
3696
1fe779f8
CO		 3697static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3698{
3699 int ret;
3700
3701 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3702 return -EINVAL;
1fe779f8
CO		 3703 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3704 return ret;
3705}
3706
b927a3ce
SY		 3707static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3708 u64 ident_addr)
3709{
3710 kvm->arch.ept_identity_map_addr = ident_addr;
3711 return 0;
3712}
3713
1fe779f8
CO		 3714static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3715 u32 kvm_nr_mmu_pages)
3716{
3717 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3718 return -EINVAL;
3719
79fac95e 3720 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3721
3722 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3723 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3724
79fac95e 3725 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3726 return 0;
3727}
3728
3729static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3730{
39de71ec 3731 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3732}
3733
1fe779f8
CO		 3734static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3735{
90bca052 3736 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3737 int r;
3738
3739 r = 0;
3740 switch (chip->chip_id) {
3741 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3742 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3743 sizeof(struct kvm_pic_state));
3744 break;
3745 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3746 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3747 sizeof(struct kvm_pic_state));
3748 break;
3749 case KVM_IRQCHIP_IOAPIC:
33392b49 3750 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3751 break;
3752 default:
3753 r = -EINVAL;
3754 break;
3755 }
3756 return r;
3757}
3758
3759static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3760{
90bca052 3761 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3762 int r;
3763
3764 r = 0;
3765 switch (chip->chip_id) {
3766 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3767 spin_lock(&pic->lock);
3768 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3769 sizeof(struct kvm_pic_state));
90bca052 3770 spin_unlock(&pic->lock);
1fe779f8
CO		 3771 break;
3772 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3773 spin_lock(&pic->lock);
3774 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3775 sizeof(struct kvm_pic_state));
90bca052 3776 spin_unlock(&pic->lock);
1fe779f8
CO		 3777 break;
3778 case KVM_IRQCHIP_IOAPIC:
33392b49 3779 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3780 break;
3781 default:
3782 r = -EINVAL;
3783 break;
3784 }
90bca052 3785 kvm_pic_update_irq(pic);
1fe779f8
CO		 3786 return r;
3787}
3788
e0f63cb9
SY		 3789static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3790{
34f3941c
RK		 3791 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3792
3793 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3794
3795 mutex_lock(&kps->lock);
3796 memcpy(ps, &kps->channels, sizeof(*ps));
3797 mutex_unlock(&kps->lock);
2da29bcc 3798 return 0;
e0f63cb9
SY		 3799}
3800
3801static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3802{
0185604c 3803 int i;
09edea72
RK		 3804 struct kvm_pit *pit = kvm->arch.vpit;
3805
3806 mutex_lock(&pit->pit_state.lock);
34f3941c 3807 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3808 for (i = 0; i < 3; i++)
09edea72
RK		 3809 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3810 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3811 return 0;
e9f42757
BK		 3812}
3813
3814static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3815{
e9f42757
BK		 3816 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3817 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3818 sizeof(ps->channels));
3819 ps->flags = kvm->arch.vpit->pit_state.flags;
3820 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3821 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3822 return 0;
e9f42757
BK		 3823}
3824
3825static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3826{
2da29bcc 3827 int start = 0;
0185604c 3828 int i;
e9f42757 3829 u32 prev_legacy, cur_legacy;
09edea72
RK		 3830 struct kvm_pit *pit = kvm->arch.vpit;
3831
3832 mutex_lock(&pit->pit_state.lock);
3833 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3834 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3835 if (!prev_legacy && cur_legacy)
3836 start = 1;
09edea72
RK		 3837 memcpy(&pit->pit_state.channels, &ps->channels,
3838 sizeof(pit->pit_state.channels));
3839 pit->pit_state.flags = ps->flags;
0185604c 3840 for (i = 0; i < 3; i++)
09edea72 3841 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3842 start && i == 0);
09edea72 3843 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3844 return 0;
e0f63cb9
SY		 3845}
3846
52d939a0
MT		 3847static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3848 struct kvm_reinject_control *control)
3849{
71474e2f
RK		 3850 struct kvm_pit *pit = kvm->arch.vpit;
3851
3852 if (!pit)
52d939a0 3853 return -ENXIO;
b39c90b6 3854
71474e2f
RK		 3855 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3856 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3857 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3858 */
3859 mutex_lock(&pit->pit_state.lock);
3860 kvm_pit_set_reinject(pit, control->pit_reinject);
3861 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3862
52d939a0
MT		 3863 return 0;
3864}
3865
95d4c16c 3866/**
60c34612
TY		 3867 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3868 * @kvm: kvm instance
3869 * @log: slot id and address to which we copy the log
95d4c16c 3870 *
e108ff2f
PB		 3871 * Steps 1-4 below provide general overview of dirty page logging. See
3872 * kvm_get_dirty_log_protect() function description for additional details.
3873 *
3874 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3875 * always flush the TLB (step 4) even if previous step failed and the dirty
3876 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3877 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3878 * writes will be marked dirty for next log read.
95d4c16c 3879 *
60c34612
TY		 3880 * 1. Take a snapshot of the bit and clear it if needed.
3881 * 2. Write protect the corresponding page.
e108ff2f
PB		 3882 * 3. Copy the snapshot to the userspace.
3883 * 4. Flush TLB's if needed.
5bb064dc 3884 */
60c34612 3885int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3886{
60c34612 3887 bool is_dirty = false;
e108ff2f 3888 int r;
5bb064dc 3889
79fac95e 3890 mutex_lock(&kvm->slots_lock);
5bb064dc 3891
88178fd4
KH		 3892 /*
3893 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3894 */
3895 if (kvm_x86_ops->flush_log_dirty)
3896 kvm_x86_ops->flush_log_dirty(kvm);
3897
e108ff2f 3898 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3899
3900 /*
3901 * All the TLBs can be flushed out of mmu lock, see the comments in
3902 * kvm_mmu_slot_remove_write_access().
3903 */
e108ff2f 3904 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3905 if (is_dirty)
3906 kvm_flush_remote_tlbs(kvm);
3907
79fac95e 3908 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3909 return r;
3910}
3911
aa2fbe6d
YZ		 3912int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3913 bool line_status)
23d43cf9
CD		 3914{
3915 if (!irqchip_in_kernel(kvm))
3916 return -ENXIO;
3917
3918 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3919 irq_event->irq, irq_event->level,
3920 line_status);
23d43cf9
CD		 3921 return 0;
3922}
3923
90de4a18
NA		 3924static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3925 struct kvm_enable_cap *cap)
3926{
3927 int r;
3928
3929 if (cap->flags)
3930 return -EINVAL;
3931
3932 switch (cap->cap) {
3933 case KVM_CAP_DISABLE_QUIRKS:
3934 kvm->arch.disabled_quirks = cap->args[0];
3935 r = 0;
3936 break;
49df6397
SR		 3937 case KVM_CAP_SPLIT_IRQCHIP: {
3938 mutex_lock(&kvm->lock);
b053b2ae
SR		 3939 r = -EINVAL;
3940 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3941 goto split_irqchip_unlock;
49df6397
SR		 3942 r = -EEXIST;
3943 if (irqchip_in_kernel(kvm))
3944 goto split_irqchip_unlock;
557abc40 3945 if (kvm->created_vcpus)
49df6397
SR		 3946 goto split_irqchip_unlock;
3947 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3948 if (r)
49df6397
SR		 3949 goto split_irqchip_unlock;
3950 /* Pairs with irqchip_in_kernel. */
3951 smp_wmb();
49776faf 3952 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3953 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3954 r = 0;
3955split_irqchip_unlock:
3956 mutex_unlock(&kvm->lock);
3957 break;
3958 }
37131313
RK		 3959 case KVM_CAP_X2APIC_API:
3960 r = -EINVAL;
3961 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3962 break;
3963
3964 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3965 kvm->arch.x2apic_format = true;
c519265f
RK		 3966 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3967 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3968
3969 r = 0;
3970 break;
90de4a18
NA		 3971 default:
3972 r = -EINVAL;
3973 break;
3974 }
3975 return r;
3976}
3977
1fe779f8
CO		 3978long kvm_arch_vm_ioctl(struct file *filp,
3979 unsigned int ioctl, unsigned long arg)
3980{
3981 struct kvm *kvm = filp->private_data;
3982 void __user *argp = (void __user *)arg;
367e1319 3983 int r = -ENOTTY;
f0d66275
DH		 3984 /*
3985 * This union makes it completely explicit to gcc-3.x
3986 * that these two variables' stack usage should be
3987 * combined, not added together.
3988 */
3989 union {
3990 struct kvm_pit_state ps;
e9f42757 3991 struct kvm_pit_state2 ps2;
c5ff41ce 3992 struct kvm_pit_config pit_config;
f0d66275 3993 } u;
1fe779f8
CO		 3994
3995 switch (ioctl) {
3996 case KVM_SET_TSS_ADDR:
3997 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3998 break;
b927a3ce
SY		 3999 case KVM_SET_IDENTITY_MAP_ADDR: {
4000 u64 ident_addr;
4001
4002 r = -EFAULT;
4003 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4004 goto out;
4005 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4006 break;
4007 }
1fe779f8
CO		 4008 case KVM_SET_NR_MMU_PAGES:
4009 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4010 break;
4011 case KVM_GET_NR_MMU_PAGES:
4012 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4013 break;
3ddea128 4014 case KVM_CREATE_IRQCHIP: {
3ddea128 4015 mutex_lock(&kvm->lock);
09941366 4016
3ddea128 4017 r = -EEXIST;
35e6eaa3 4018 if (irqchip_in_kernel(kvm))
3ddea128 4019 goto create_irqchip_unlock;
09941366 4020
3e515705 4021 r = -EINVAL;
557abc40 4022 if (kvm->created_vcpus)
3e515705 4023 goto create_irqchip_unlock;
09941366
RK		 4024
4025 r = kvm_pic_init(kvm);
4026 if (r)
3ddea128 4027 goto create_irqchip_unlock;
09941366
RK		 4028
4029 r = kvm_ioapic_init(kvm);
4030 if (r) {
09941366 4031 kvm_pic_destroy(kvm);
3ddea128 4032 goto create_irqchip_unlock;
09941366
RK		 4033 }
4034
399ec807
AK		 4035 r = kvm_setup_default_irq_routing(kvm);
4036 if (r) {
72bb2fcd 4037 kvm_ioapic_destroy(kvm);
09941366 4038 kvm_pic_destroy(kvm);
71ba994c 4039 goto create_irqchip_unlock;
399ec807 4040 }
49776faf 4041 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4042 smp_wmb();
49776faf 4043 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4044 create_irqchip_unlock:
4045 mutex_unlock(&kvm->lock);
1fe779f8 4046 break;
3ddea128 4047 }
7837699f 4048 case KVM_CREATE_PIT:
c5ff41ce
JK		 4049 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4050 goto create_pit;
4051 case KVM_CREATE_PIT2:
4052 r = -EFAULT;
4053 if (copy_from_user(&u.pit_config, argp,
4054 sizeof(struct kvm_pit_config)))
4055 goto out;
4056 create_pit:
250715a6 4057 mutex_lock(&kvm->lock);
269e05e4
AK		 4058 r = -EEXIST;
4059 if (kvm->arch.vpit)
4060 goto create_pit_unlock;
7837699f 4061 r = -ENOMEM;
c5ff41ce 4062 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4063 if (kvm->arch.vpit)
4064 r = 0;
269e05e4 4065 create_pit_unlock:
250715a6 4066 mutex_unlock(&kvm->lock);
7837699f 4067 break;
1fe779f8
CO		 4068 case KVM_GET_IRQCHIP: {
4069 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4070 struct kvm_irqchip *chip;
1fe779f8 4071
ff5c2c03
SL		 4072 chip = memdup_user(argp, sizeof(*chip));
4073 if (IS_ERR(chip)) {
4074 r = PTR_ERR(chip);
1fe779f8 4075 goto out;
ff5c2c03
SL		 4076 }
4077
1fe779f8 4078 r = -ENXIO;
826da321 4079 if (!irqchip_kernel(kvm))
f0d66275
DH		 4080 goto get_irqchip_out;
4081 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4082 if (r)
f0d66275 4083 goto get_irqchip_out;
1fe779f8 4084 r = -EFAULT;
f0d66275
DH		 4085 if (copy_to_user(argp, chip, sizeof *chip))
4086 goto get_irqchip_out;
1fe779f8 4087 r = 0;
f0d66275
DH		 4088 get_irqchip_out:
4089 kfree(chip);
1fe779f8
CO		 4090 break;
4091 }
4092 case KVM_SET_IRQCHIP: {
4093 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4094 struct kvm_irqchip *chip;
1fe779f8 4095
ff5c2c03
SL		 4096 chip = memdup_user(argp, sizeof(*chip));
4097 if (IS_ERR(chip)) {
4098 r = PTR_ERR(chip);
1fe779f8 4099 goto out;
ff5c2c03
SL		 4100 }
4101
1fe779f8 4102 r = -ENXIO;
826da321 4103 if (!irqchip_kernel(kvm))
f0d66275
DH		 4104 goto set_irqchip_out;
4105 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4106 if (r)
f0d66275 4107 goto set_irqchip_out;
1fe779f8 4108 r = 0;
f0d66275
DH		 4109 set_irqchip_out:
4110 kfree(chip);
1fe779f8
CO		 4111 break;
4112 }
e0f63cb9 4113 case KVM_GET_PIT: {
e0f63cb9 4114 r = -EFAULT;
f0d66275 4115 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4116 goto out;
4117 r = -ENXIO;
4118 if (!kvm->arch.vpit)
4119 goto out;
f0d66275 4120 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4121 if (r)
4122 goto out;
4123 r = -EFAULT;
f0d66275 4124 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4125 goto out;
4126 r = 0;
4127 break;
4128 }
4129 case KVM_SET_PIT: {
e0f63cb9 4130 r = -EFAULT;
f0d66275 4131 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4132 goto out;
4133 r = -ENXIO;
4134 if (!kvm->arch.vpit)
4135 goto out;
f0d66275 4136 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4137 break;
4138 }
e9f42757
BK		 4139 case KVM_GET_PIT2: {
4140 r = -ENXIO;
4141 if (!kvm->arch.vpit)
4142 goto out;
4143 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4144 if (r)
4145 goto out;
4146 r = -EFAULT;
4147 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4148 goto out;
4149 r = 0;
4150 break;
4151 }
4152 case KVM_SET_PIT2: {
4153 r = -EFAULT;
4154 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4155 goto out;
4156 r = -ENXIO;
4157 if (!kvm->arch.vpit)
4158 goto out;
4159 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4160 break;
4161 }
52d939a0
MT		 4162 case KVM_REINJECT_CONTROL: {
4163 struct kvm_reinject_control control;
4164 r = -EFAULT;
4165 if (copy_from_user(&control, argp, sizeof(control)))
4166 goto out;
4167 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4168 break;
4169 }
d71ba788
PB		 4170 case KVM_SET_BOOT_CPU_ID:
4171 r = 0;
4172 mutex_lock(&kvm->lock);
557abc40 4173 if (kvm->created_vcpus)
d71ba788
PB		 4174 r = -EBUSY;
4175 else
4176 kvm->arch.bsp_vcpu_id = arg;
4177 mutex_unlock(&kvm->lock);
4178 break;
ffde22ac
ES		 4179 case KVM_XEN_HVM_CONFIG: {
4180 r = -EFAULT;
4181 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4182 sizeof(struct kvm_xen_hvm_config)))
4183 goto out;
4184 r = -EINVAL;
4185 if (kvm->arch.xen_hvm_config.flags)
4186 goto out;
4187 r = 0;
4188 break;
4189 }
afbcf7ab 4190 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4191 struct kvm_clock_data user_ns;
4192 u64 now_ns;
afbcf7ab
GC		 4193
4194 r = -EFAULT;
4195 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4196 goto out;
4197
4198 r = -EINVAL;
4199 if (user_ns.flags)
4200 goto out;
4201
4202 r = 0;
0bc48bea
RK		 4203 /*
4204 * TODO: userspace has to take care of races with VCPU_RUN, so
4205 * kvm_gen_update_masterclock() can be cut down to locked
4206 * pvclock_update_vm_gtod_copy().
4207 */
4208 kvm_gen_update_masterclock(kvm);
e891a32e 4209 now_ns = get_kvmclock_ns(kvm);
108b249c 4210 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4211 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4212 break;
4213 }
4214 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4215 struct kvm_clock_data user_ns;
4216 u64 now_ns;
4217
e891a32e 4218 now_ns = get_kvmclock_ns(kvm);
108b249c 4219 user_ns.clock = now_ns;
e3fd9a93 4220 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4221 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4222
4223 r = -EFAULT;
4224 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4225 goto out;
4226 r = 0;
4227 break;
4228 }
90de4a18
NA		 4229 case KVM_ENABLE_CAP: {
4230 struct kvm_enable_cap cap;
afbcf7ab 4231
90de4a18
NA		 4232 r = -EFAULT;
4233 if (copy_from_user(&cap, argp, sizeof(cap)))
4234 goto out;
4235 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4236 break;
4237 }
1fe779f8 4238 default:
ad6260da 4239 r = -ENOTTY;
1fe779f8
CO		 4240 }
4241out:
4242 return r;
4243}
4244
a16b043c 4245static void kvm_init_msr_list(void)
043405e1
CO		 4246{
4247 u32 dummy[2];
4248 unsigned i, j;
4249
62ef68bb 4250 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4251 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4252 continue;
93c4adc7
PB		 4253
4254 /*
4255 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4256 * to the guests in some cases.
93c4adc7
PB		 4257 */
4258 switch (msrs_to_save[i]) {
4259 case MSR_IA32_BNDCFGS:
4260 if (!kvm_x86_ops->mpx_supported())
4261 continue;
4262 break;
9dbe6cf9
PB		 4263 case MSR_TSC_AUX:
4264 if (!kvm_x86_ops->rdtscp_supported())
4265 continue;
4266 break;
93c4adc7
PB		 4267 default:
4268 break;
4269 }
4270
043405e1
CO		 4271 if (j < i)
4272 msrs_to_save[j] = msrs_to_save[i];
4273 j++;
4274 }
4275 num_msrs_to_save = j;
62ef68bb
PB		 4276
4277 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4278 switch (emulated_msrs[i]) {
6d396b55
PB		 4279 case MSR_IA32_SMBASE:
4280 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4281 continue;
4282 break;
62ef68bb
PB		 4283 default:
4284 break;
4285 }
4286
4287 if (j < i)
4288 emulated_msrs[j] = emulated_msrs[i];
4289 j++;
4290 }
4291 num_emulated_msrs = j;
043405e1
CO		 4292}
4293
bda9020e
MT		 4294static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4295 const void *v)
bbd9b64e 4296{
70252a10
AK		 4297 int handled = 0;
4298 int n;
4299
4300 do {
4301 n = min(len, 8);
bce87cce 4302 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4303 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4304 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4305 break;
4306 handled += n;
4307 addr += n;
4308 len -= n;
4309 v += n;
4310 } while (len);
bbd9b64e 4311
70252a10 4312 return handled;
bbd9b64e
CO		 4313}
4314
bda9020e 4315static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4316{
70252a10
AK		 4317 int handled = 0;
4318 int n;
4319
4320 do {
4321 n = min(len, 8);
bce87cce 4322 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4323 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4324 addr, n, v))
4325 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4326 break;
4327 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4328 handled += n;
4329 addr += n;
4330 len -= n;
4331 v += n;
4332 } while (len);
bbd9b64e 4333
70252a10 4334 return handled;
bbd9b64e
CO		 4335}
4336
2dafc6c2
GN		 4337static void kvm_set_segment(struct kvm_vcpu *vcpu,
4338 struct kvm_segment *var, int seg)
4339{
4340 kvm_x86_ops->set_segment(vcpu, var, seg);
4341}
4342
4343void kvm_get_segment(struct kvm_vcpu *vcpu,
4344 struct kvm_segment *var, int seg)
4345{
4346 kvm_x86_ops->get_segment(vcpu, var, seg);
4347}
4348
54987b7a
PB		 4349gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4350 struct x86_exception *exception)
02f59dc9
JR		 4351{
4352 gpa_t t_gpa;
02f59dc9
JR		 4353
4354 BUG_ON(!mmu_is_nested(vcpu));
4355
4356 /* NPT walks are always user-walks */
4357 access |= PFERR_USER_MASK;
54987b7a 4358 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4359
4360 return t_gpa;
4361}
4362
ab9ae313
AK		 4363gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4364 struct x86_exception *exception)
1871c602
GN		 4365{
4366 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4367 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4368}
4369
ab9ae313
AK		 4370 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4371 struct x86_exception *exception)
1871c602
GN		 4372{
4373 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4374 access |= PFERR_FETCH_MASK;
ab9ae313 4375 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4376}
4377
ab9ae313
AK		 4378gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4379 struct x86_exception *exception)
1871c602
GN		 4380{
4381 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4382 access |= PFERR_WRITE_MASK;
ab9ae313 4383 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4384}
4385
4386/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4387gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4388 struct x86_exception *exception)
1871c602 4389{
ab9ae313 4390 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4391}
4392
4393static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4394 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4395 struct x86_exception *exception)
bbd9b64e
CO		 4396{
4397 void *data = val;
10589a46 4398 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4399
4400 while (bytes) {
14dfe855 4401 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4402 exception);
bbd9b64e 4403 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4404 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4405 int ret;
4406
bcc55cba 4407 if (gpa == UNMAPPED_GVA)
ab9ae313 4408 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4409 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4410 offset, toread);
10589a46 4411 if (ret < 0) {
c3cd7ffa 4412 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4413 goto out;
4414 }
bbd9b64e 4415
77c2002e
IE		 4416 bytes -= toread;
4417 data += toread;
4418 addr += toread;
bbd9b64e 4419 }
10589a46 4420out:
10589a46 4421 return r;
bbd9b64e 4422}
77c2002e 4423
1871c602 4424/* used for instruction fetching */
0f65dd70
AK		 4425static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4426 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4427 struct x86_exception *exception)
1871c602 4428{
0f65dd70 4429 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4430 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4431 unsigned offset;
4432 int ret;
0f65dd70 4433
44583cba
PB		 4434 /* Inline kvm_read_guest_virt_helper for speed. */
4435 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4436 exception);
4437 if (unlikely(gpa == UNMAPPED_GVA))
4438 return X86EMUL_PROPAGATE_FAULT;
4439
4440 offset = addr & (PAGE_SIZE-1);
4441 if (WARN_ON(offset + bytes > PAGE_SIZE))
4442 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4443 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4444 offset, bytes);
44583cba
PB		 4445 if (unlikely(ret < 0))
4446 return X86EMUL_IO_NEEDED;
4447
4448 return X86EMUL_CONTINUE;
1871c602
GN		 4449}
4450
064aea77 4451int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4452 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4453 struct x86_exception *exception)
1871c602 4454{
0f65dd70 4455 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4456 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4457
1871c602 4458 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4459 exception);
1871c602 4460}
064aea77 4461EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4462
0f65dd70
AK		 4463static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4464 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4465 struct x86_exception *exception)
1871c602 4466{
0f65dd70 4467 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4468 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4469}
4470
7a036a6f
RK		 4471static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4472 unsigned long addr, void *val, unsigned int bytes)
4473{
4474 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4475 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4476
4477 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4478}
4479
6a4d7550 4480int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4481 gva_t addr, void *val,
2dafc6c2 4482 unsigned int bytes,
bcc55cba 4483 struct x86_exception *exception)
77c2002e 4484{
0f65dd70 4485 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4486 void *data = val;
4487 int r = X86EMUL_CONTINUE;
4488
4489 while (bytes) {
14dfe855
JR		 4490 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4491 PFERR_WRITE_MASK,
ab9ae313 4492 exception);
77c2002e
IE		 4493 unsigned offset = addr & (PAGE_SIZE-1);
4494 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4495 int ret;
4496
bcc55cba 4497 if (gpa == UNMAPPED_GVA)
ab9ae313 4498 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4499 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4500 if (ret < 0) {
c3cd7ffa 4501 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4502 goto out;
4503 }
4504
4505 bytes -= towrite;
4506 data += towrite;
4507 addr += towrite;
4508 }
4509out:
4510 return r;
4511}
6a4d7550 4512EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4513
0f89b207
TL		 4514static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4515 gpa_t gpa, bool write)
4516{
4517 /* For APIC access vmexit */
4518 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4519 return 1;
4520
4521 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4522 trace_vcpu_match_mmio(gva, gpa, write, true);
4523 return 1;
4524 }
4525
4526 return 0;
4527}
4528
af7cc7d1
XG		 4529static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4530 gpa_t *gpa, struct x86_exception *exception,
4531 bool write)
4532{
97d64b78
AK		 4533 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4534 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4535
be94f6b7
HH		 4536 /*
4537 * currently PKRU is only applied to ept enabled guest so
4538 * there is no pkey in EPT page table for L1 guest or EPT
4539 * shadow page table for L2 guest.
4540 */
97d64b78 4541 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4542 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4543 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4544 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4545 (gva & (PAGE_SIZE - 1));
4f022648 4546 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4547 return 1;
4548 }
4549
af7cc7d1
XG		 4550 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4551
4552 if (*gpa == UNMAPPED_GVA)
4553 return -1;
4554
0f89b207 4555 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4556}
4557
3200f405 4558int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4559 const void *val, int bytes)
bbd9b64e
CO		 4560{
4561 int ret;
4562
54bf36aa 4563 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4564 if (ret < 0)
bbd9b64e 4565 return 0;
0eb05bf2 4566 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4567 return 1;
4568}
4569
77d197b2
XG		 4570struct read_write_emulator_ops {
4571 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4572 int bytes);
4573 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4574 void *val, int bytes);
4575 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4576 int bytes, void *val);
4577 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4578 void *val, int bytes);
4579 bool write;
4580};
4581
4582static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4583{
4584 if (vcpu->mmio_read_completed) {
77d197b2 4585 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4586 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4587 vcpu->mmio_read_completed = 0;
4588 return 1;
4589 }
4590
4591 return 0;
4592}
4593
4594static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4595 void *val, int bytes)
4596{
54bf36aa 4597 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4598}
4599
4600static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4601 void *val, int bytes)
4602{
4603 return emulator_write_phys(vcpu, gpa, val, bytes);
4604}
4605
4606static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4607{
4608 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4609 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4610}
4611
4612static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4613 void *val, int bytes)
4614{
4615 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4616 return X86EMUL_IO_NEEDED;
4617}
4618
4619static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4620 void *val, int bytes)
4621{
f78146b0
AK		 4622 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4623
87da7e66 4624 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4625 return X86EMUL_CONTINUE;
4626}
4627
0fbe9b0b 4628static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4629 .read_write_prepare = read_prepare,
4630 .read_write_emulate = read_emulate,
4631 .read_write_mmio = vcpu_mmio_read,
4632 .read_write_exit_mmio = read_exit_mmio,
4633};
4634
0fbe9b0b 4635static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4636 .read_write_emulate = write_emulate,
4637 .read_write_mmio = write_mmio,
4638 .read_write_exit_mmio = write_exit_mmio,
4639 .write = true,
4640};
4641
22388a3c
XG		 4642static int emulator_read_write_onepage(unsigned long addr, void *val,
4643 unsigned int bytes,
4644 struct x86_exception *exception,
4645 struct kvm_vcpu *vcpu,
0fbe9b0b 4646 const struct read_write_emulator_ops *ops)
bbd9b64e 4647{
af7cc7d1
XG		 4648 gpa_t gpa;
4649 int handled, ret;
22388a3c 4650 bool write = ops->write;
f78146b0 4651 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4652 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4653
4654 /*
4655 * If the exit was due to a NPF we may already have a GPA.
4656 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4657 * Note, this cannot be used on string operations since string
4658 * operation using rep will only have the initial GPA from the NPF
4659 * occurred.
4660 */
4661 if (vcpu->arch.gpa_available &&
4662 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4663 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4664 gpa = vcpu->arch.gpa_val;
4665 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4666 } else {
4667 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4668 if (ret < 0)
4669 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4670 }
10589a46 4671
618232e2 4672 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4673 return X86EMUL_CONTINUE;
4674
bbd9b64e
CO		 4675 /*
4676 * Is this MMIO handled locally?
4677 */
22388a3c 4678 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4679 if (handled == bytes)
bbd9b64e 4680 return X86EMUL_CONTINUE;
bbd9b64e 4681
70252a10
AK		 4682 gpa += handled;
4683 bytes -= handled;
4684 val += handled;
4685
87da7e66
XG		 4686 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4687 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4688 frag->gpa = gpa;
4689 frag->data = val;
4690 frag->len = bytes;
f78146b0 4691 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4692}
4693
52eb5a6d
XL		 4694static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4695 unsigned long addr,
22388a3c
XG		 4696 void *val, unsigned int bytes,
4697 struct x86_exception *exception,
0fbe9b0b 4698 const struct read_write_emulator_ops *ops)
bbd9b64e 4699{
0f65dd70 4700 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4701 gpa_t gpa;
4702 int rc;
4703
4704 if (ops->read_write_prepare &&
4705 ops->read_write_prepare(vcpu, val, bytes))
4706 return X86EMUL_CONTINUE;
4707
4708 vcpu->mmio_nr_fragments = 0;
0f65dd70 4709
bbd9b64e
CO		 4710 /* Crossing a page boundary? */
4711 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4712 int now;
bbd9b64e
CO		 4713
4714 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4715 rc = emulator_read_write_onepage(addr, val, now, exception,
4716 vcpu, ops);
4717
bbd9b64e
CO		 4718 if (rc != X86EMUL_CONTINUE)
4719 return rc;
4720 addr += now;
bac15531
NA		 4721 if (ctxt->mode != X86EMUL_MODE_PROT64)
4722 addr = (u32)addr;
bbd9b64e
CO		 4723 val += now;
4724 bytes -= now;
4725 }
22388a3c 4726
f78146b0
AK		 4727 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4728 vcpu, ops);
4729 if (rc != X86EMUL_CONTINUE)
4730 return rc;
4731
4732 if (!vcpu->mmio_nr_fragments)
4733 return rc;
4734
4735 gpa = vcpu->mmio_fragments[0].gpa;
4736
4737 vcpu->mmio_needed = 1;
4738 vcpu->mmio_cur_fragment = 0;
4739
87da7e66 4740 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4741 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4742 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4743 vcpu->run->mmio.phys_addr = gpa;
4744
4745 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4746}
4747
4748static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4749 unsigned long addr,
4750 void *val,
4751 unsigned int bytes,
4752 struct x86_exception *exception)
4753{
4754 return emulator_read_write(ctxt, addr, val, bytes,
4755 exception, &read_emultor);
4756}
4757
52eb5a6d 4758static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4759 unsigned long addr,
4760 const void *val,
4761 unsigned int bytes,
4762 struct x86_exception *exception)
4763{
4764 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4765 exception, &write_emultor);
bbd9b64e 4766}
bbd9b64e 4767
daea3e73
AK		 4768#define CMPXCHG_TYPE(t, ptr, old, new) \
4769 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4770
4771#ifdef CONFIG_X86_64
4772# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4773#else
4774# define CMPXCHG64(ptr, old, new) \
9749a6c0 4775 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4776#endif
4777
0f65dd70
AK		 4778static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4779 unsigned long addr,
bbd9b64e
CO		 4780 const void *old,
4781 const void *new,
4782 unsigned int bytes,
0f65dd70 4783 struct x86_exception *exception)
bbd9b64e 4784{
0f65dd70 4785 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4786 gpa_t gpa;
4787 struct page *page;
4788 char *kaddr;
4789 bool exchanged;
2bacc55c 4790
daea3e73
AK		 4791 /* guests cmpxchg8b have to be emulated atomically */
4792 if (bytes > 8 || (bytes & (bytes - 1)))
4793 goto emul_write;
10589a46 4794
daea3e73 4795 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4796
daea3e73
AK		 4797 if (gpa == UNMAPPED_GVA ||
4798 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4799 goto emul_write;
2bacc55c 4800
daea3e73
AK		 4801 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4802 goto emul_write;
72dc67a6 4803
54bf36aa 4804 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4805 if (is_error_page(page))
c19b8bd6 4806 goto emul_write;
72dc67a6 4807
8fd75e12 4808 kaddr = kmap_atomic(page);
daea3e73
AK		 4809 kaddr += offset_in_page(gpa);
4810 switch (bytes) {
4811 case 1:
4812 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4813 break;
4814 case 2:
4815 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4816 break;
4817 case 4:
4818 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4819 break;
4820 case 8:
4821 exchanged = CMPXCHG64(kaddr, old, new);
4822 break;
4823 default:
4824 BUG();
2bacc55c 4825 }
8fd75e12 4826 kunmap_atomic(kaddr);
daea3e73
AK		 4827 kvm_release_page_dirty(page);
4828
4829 if (!exchanged)
4830 return X86EMUL_CMPXCHG_FAILED;
4831
54bf36aa 4832 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4833 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4834
4835 return X86EMUL_CONTINUE;
4a5f48f6 4836
3200f405 4837emul_write:
daea3e73 4838 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4839
0f65dd70 4840 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4841}
4842
cf8f70bf
GN		 4843static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4844{
cbfc6c91 4845 int r = 0, i;
cf8f70bf 4846
cbfc6c91
WL		 4847 for (i = 0; i < vcpu->arch.pio.count; i++) {
4848 if (vcpu->arch.pio.in)
4849 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4850 vcpu->arch.pio.size, pd);
4851 else
4852 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4853 vcpu->arch.pio.port, vcpu->arch.pio.size,
4854 pd);
4855 if (r)
4856 break;
4857 pd += vcpu->arch.pio.size;
4858 }
cf8f70bf
GN		 4859 return r;
4860}
4861
6f6fbe98
XG		 4862static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4863 unsigned short port, void *val,
4864 unsigned int count, bool in)
cf8f70bf 4865{
cf8f70bf 4866 vcpu->arch.pio.port = port;
6f6fbe98 4867 vcpu->arch.pio.in = in;
7972995b 4868 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4869 vcpu->arch.pio.size = size;
4870
4871 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4872 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4873 return 1;
4874 }
4875
4876 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4877 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4878 vcpu->run->io.size = size;
4879 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4880 vcpu->run->io.count = count;
4881 vcpu->run->io.port = port;
4882
4883 return 0;
4884}
4885
6f6fbe98
XG		 4886static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4887 int size, unsigned short port, void *val,
4888 unsigned int count)
cf8f70bf 4889{
ca1d4a9e 4890 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4891 int ret;
ca1d4a9e 4892
6f6fbe98
XG		 4893 if (vcpu->arch.pio.count)
4894 goto data_avail;
cf8f70bf 4895
cbfc6c91
WL		 4896 memset(vcpu->arch.pio_data, 0, size * count);
4897
6f6fbe98
XG		 4898 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4899 if (ret) {
4900data_avail:
4901 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4902 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4903 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4904 return 1;
4905 }
4906
cf8f70bf
GN		 4907 return 0;
4908}
4909
6f6fbe98
XG		 4910static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4911 int size, unsigned short port,
4912 const void *val, unsigned int count)
4913{
4914 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4915
4916 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4917 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4918 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4919}
4920
bbd9b64e
CO		 4921static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4922{
4923 return kvm_x86_ops->get_segment_base(vcpu, seg);
4924}
4925
3cb16fe7 4926static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4927{
3cb16fe7 4928 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4929}
4930
ae6a2375 4931static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4932{
4933 if (!need_emulate_wbinvd(vcpu))
4934 return X86EMUL_CONTINUE;
4935
4936 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4937 int cpu = get_cpu();
4938
4939 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4940 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4941 wbinvd_ipi, NULL, 1);
2eec7343 4942 put_cpu();
f5f48ee1 4943 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4944 } else
4945 wbinvd();
f5f48ee1
SY		 4946 return X86EMUL_CONTINUE;
4947}
5cb56059
JS		 4948
4949int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4950{
6affcbed
KH		 4951 kvm_emulate_wbinvd_noskip(vcpu);
4952 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4953}
f5f48ee1
SY		 4954EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4955
5cb56059
JS		 4956
4957
bcaf5cc5
AK		 4958static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4959{
5cb56059 4960 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4961}
4962
52eb5a6d
XL		 4963static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4964 unsigned long *dest)
bbd9b64e 4965{
16f8a6f9 4966 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4967}
4968
52eb5a6d
XL		 4969static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4970 unsigned long value)
bbd9b64e 4971{
338dbc97 4972
717746e3 4973 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4974}
4975
52a46617 4976static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4977{
52a46617 4978 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4979}
4980
717746e3 4981static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4982{
717746e3 4983 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4984 unsigned long value;
4985
4986 switch (cr) {
4987 case 0:
4988 value = kvm_read_cr0(vcpu);
4989 break;
4990 case 2:
4991 value = vcpu->arch.cr2;
4992 break;
4993 case 3:
9f8fe504 4994 value = kvm_read_cr3(vcpu);
52a46617
GN		 4995 break;
4996 case 4:
4997 value = kvm_read_cr4(vcpu);
4998 break;
4999 case 8:
5000 value = kvm_get_cr8(vcpu);
5001 break;
5002 default:
a737f256 5003 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5004 return 0;
5005 }
5006
5007 return value;
5008}
5009
717746e3 5010static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5011{
717746e3 5012 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5013 int res = 0;
5014
52a46617
GN		 5015 switch (cr) {
5016 case 0:
49a9b07e 5017 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5018 break;
5019 case 2:
5020 vcpu->arch.cr2 = val;
5021 break;
5022 case 3:
2390218b 5023 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5024 break;
5025 case 4:
a83b29c6 5026 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5027 break;
5028 case 8:
eea1cff9 5029 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5030 break;
5031 default:
a737f256 5032 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5033 res = -1;
52a46617 5034 }
0f12244f
GN		 5035
5036 return res;
52a46617
GN		 5037}
5038
717746e3 5039static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5040{
717746e3 5041 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5042}
5043
4bff1e86 5044static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5045{
4bff1e86 5046 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5047}
5048
4bff1e86 5049static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5050{
4bff1e86 5051 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5052}
5053
1ac9d0cf
AK		 5054static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5055{
5056 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5057}
5058
5059static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5060{
5061 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5062}
5063
4bff1e86
AK		 5064static unsigned long emulator_get_cached_segment_base(
5065 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5066{
4bff1e86 5067 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5068}
5069
1aa36616
AK		 5070static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5071 struct desc_struct *desc, u32 *base3,
5072 int seg)
2dafc6c2
GN		 5073{
5074 struct kvm_segment var;
5075
4bff1e86 5076 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5077 *selector = var.selector;
2dafc6c2 5078
378a8b09
GN		 5079 if (var.unusable) {
5080 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5081 if (base3)
5082 *base3 = 0;
2dafc6c2 5083 return false;
378a8b09 5084 }
2dafc6c2
GN		 5085
5086 if (var.g)
5087 var.limit >>= 12;
5088 set_desc_limit(desc, var.limit);
5089 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5090#ifdef CONFIG_X86_64
5091 if (base3)
5092 *base3 = var.base >> 32;
5093#endif
2dafc6c2
GN		 5094 desc->type = var.type;
5095 desc->s = var.s;
5096 desc->dpl = var.dpl;
5097 desc->p = var.present;
5098 desc->avl = var.avl;
5099 desc->l = var.l;
5100 desc->d = var.db;
5101 desc->g = var.g;
5102
5103 return true;
5104}
5105
1aa36616
AK		 5106static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5107 struct desc_struct *desc, u32 base3,
5108 int seg)
2dafc6c2 5109{
4bff1e86 5110 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5111 struct kvm_segment var;
5112
1aa36616 5113 var.selector = selector;
2dafc6c2 5114 var.base = get_desc_base(desc);
5601d05b
GN		 5115#ifdef CONFIG_X86_64
5116 var.base |= ((u64)base3) << 32;
5117#endif
2dafc6c2
GN		 5118 var.limit = get_desc_limit(desc);
5119 if (desc->g)
5120 var.limit = (var.limit << 12) | 0xfff;
5121 var.type = desc->type;
2dafc6c2
GN		 5122 var.dpl = desc->dpl;
5123 var.db = desc->d;
5124 var.s = desc->s;
5125 var.l = desc->l;
5126 var.g = desc->g;
5127 var.avl = desc->avl;
5128 var.present = desc->p;
5129 var.unusable = !var.present;
5130 var.padding = 0;
5131
5132 kvm_set_segment(vcpu, &var, seg);
5133 return;
5134}
5135
717746e3
AK		 5136static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5137 u32 msr_index, u64 *pdata)
5138{
609e36d3
PB		 5139 struct msr_data msr;
5140 int r;
5141
5142 msr.index = msr_index;
5143 msr.host_initiated = false;
5144 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5145 if (r)
5146 return r;
5147
5148 *pdata = msr.data;
5149 return 0;
717746e3
AK		 5150}
5151
5152static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5153 u32 msr_index, u64 data)
5154{
8fe8ab46
WA		 5155 struct msr_data msr;
5156
5157 msr.data = data;
5158 msr.index = msr_index;
5159 msr.host_initiated = false;
5160 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5161}
5162
64d60670
PB		 5163static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5164{
5165 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5166
5167 return vcpu->arch.smbase;
5168}
5169
5170static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5171{
5172 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5173
5174 vcpu->arch.smbase = smbase;
5175}
5176
67f4d428
NA		 5177static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5178 u32 pmc)
5179{
c6702c9d 5180 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5181}
5182
222d21aa
AK		 5183static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5184 u32 pmc, u64 *pdata)
5185{
c6702c9d 5186 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5187}
5188
6c3287f7
AK		 5189static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5190{
5191 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5192}
5193
5037f6f3
AK		 5194static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5195{
5196 preempt_disable();
5197b808 5197 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5198}
5199
5200static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5201{
5202 preempt_enable();
5203}
5204
2953538e 5205static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5206 struct x86_instruction_info *info,
c4f035c6
AK		 5207 enum x86_intercept_stage stage)
5208{
2953538e 5209 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5210}
5211
e911eb3b
YZ		 5212static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5213 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5214{
e911eb3b 5215 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5216}
5217
dd856efa
AK		 5218static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5219{
5220 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5221}
5222
5223static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5224{
5225 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5226}
5227
801806d9
NA		 5228static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5229{
5230 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5231}
5232
6ed071f0
LP		 5233static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5234{
5235 return emul_to_vcpu(ctxt)->arch.hflags;
5236}
5237
5238static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5239{
5240 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5241}
5242
0225fb50 5243static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5244 .read_gpr = emulator_read_gpr,
5245 .write_gpr = emulator_write_gpr,
1871c602 5246 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5247 .write_std = kvm_write_guest_virt_system,
7a036a6f 5248 .read_phys = kvm_read_guest_phys_system,
1871c602 5249 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5250 .read_emulated = emulator_read_emulated,
5251 .write_emulated = emulator_write_emulated,
5252 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5253 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5254 .pio_in_emulated = emulator_pio_in_emulated,
5255 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5256 .get_segment = emulator_get_segment,
5257 .set_segment = emulator_set_segment,
5951c442 5258 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5259 .get_gdt = emulator_get_gdt,
160ce1f1 5260 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5261 .set_gdt = emulator_set_gdt,
5262 .set_idt = emulator_set_idt,
52a46617
GN		 5263 .get_cr = emulator_get_cr,
5264 .set_cr = emulator_set_cr,
9c537244 5265 .cpl = emulator_get_cpl,
35aa5375
GN		 5266 .get_dr = emulator_get_dr,
5267 .set_dr = emulator_set_dr,
64d60670
PB		 5268 .get_smbase = emulator_get_smbase,
5269 .set_smbase = emulator_set_smbase,
717746e3
AK		 5270 .set_msr = emulator_set_msr,
5271 .get_msr = emulator_get_msr,
67f4d428 5272 .check_pmc = emulator_check_pmc,
222d21aa 5273 .read_pmc = emulator_read_pmc,
6c3287f7 5274 .halt = emulator_halt,
bcaf5cc5 5275 .wbinvd = emulator_wbinvd,
d6aa1000 5276 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5277 .get_fpu = emulator_get_fpu,
5278 .put_fpu = emulator_put_fpu,
c4f035c6 5279 .intercept = emulator_intercept,
bdb42f5a 5280 .get_cpuid = emulator_get_cpuid,
801806d9 5281 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5282 .get_hflags = emulator_get_hflags,
5283 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5284};
5285
95cb2295
GN		 5286static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5287{
37ccdcbe 5288 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5289 /*
5290 * an sti; sti; sequence only disable interrupts for the first
5291 * instruction. So, if the last instruction, be it emulated or
5292 * not, left the system with the INT_STI flag enabled, it
5293 * means that the last instruction is an sti. We should not
5294 * leave the flag on in this case. The same goes for mov ss
5295 */
37ccdcbe
PB		 5296 if (int_shadow & mask)
5297 mask = 0;
6addfc42 5298 if (unlikely(int_shadow || mask)) {
95cb2295 5299 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5300 if (!mask)
5301 kvm_make_request(KVM_REQ_EVENT, vcpu);
5302 }
95cb2295
GN		 5303}
5304
ef54bcfe 5305static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5306{
5307 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5308 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5309 return kvm_propagate_fault(vcpu, &ctxt->exception);
5310
5311 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5312 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5313 ctxt->exception.error_code);
54b8486f 5314 else
da9cb575 5315 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5316 return false;
54b8486f
GN		 5317}
5318
8ec4722d
MG		 5319static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5320{
adf52235 5321 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5322 int cs_db, cs_l;
5323
8ec4722d
MG		 5324 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5325
adf52235 5326 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5327 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5328
adf52235
TY		 5329 ctxt->eip = kvm_rip_read(vcpu);
5330 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5331 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5332 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5333 cs_db ? X86EMUL_MODE_PROT32 :
5334 X86EMUL_MODE_PROT16;
a584539b 5335 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5336 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5337 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5338
dd856efa 5339 init_decode_cache(ctxt);
7ae441ea 5340 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5341}
5342
71f9833b 5343int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5344{
9d74191a 5345 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5346 int ret;
5347
5348 init_emulate_ctxt(vcpu);
5349
9dac77fa
AK		 5350 ctxt->op_bytes = 2;
5351 ctxt->ad_bytes = 2;
5352 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5353 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5354
5355 if (ret != X86EMUL_CONTINUE)
5356 return EMULATE_FAIL;
5357
9dac77fa 5358 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5359 kvm_rip_write(vcpu, ctxt->eip);
5360 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5361
5362 if (irq == NMI_VECTOR)
7460fb4a 5363 vcpu->arch.nmi_pending = 0;
63995653
MG		 5364 else
5365 vcpu->arch.interrupt.pending = false;
5366
5367 return EMULATE_DONE;
5368}
5369EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5370
6d77dbfc
GN		 5371static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5372{
fc3a9157
JR		 5373 int r = EMULATE_DONE;
5374
6d77dbfc
GN		 5375 ++vcpu->stat.insn_emulation_fail;
5376 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5377 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5378 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5379 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5380 vcpu->run->internal.ndata = 0;
5381 r = EMULATE_FAIL;
5382 }
6d77dbfc 5383 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5384
5385 return r;
6d77dbfc
GN		 5386}
5387
93c05d3e 5388static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5389 bool write_fault_to_shadow_pgtable,
5390 int emulation_type)
a6f177ef 5391{
95b3cf69 5392 gpa_t gpa = cr2;
ba049e93 5393 kvm_pfn_t pfn;
a6f177ef 5394
991eebf9
GN		 5395 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5396 return false;
5397
95b3cf69
XG		 5398 if (!vcpu->arch.mmu.direct_map) {
5399 /*
5400 * Write permission should be allowed since only
5401 * write access need to be emulated.
5402 */
5403 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5404
95b3cf69
XG		 5405 /*
5406 * If the mapping is invalid in guest, let cpu retry
5407 * it to generate fault.
5408 */
5409 if (gpa == UNMAPPED_GVA)
5410 return true;
5411 }
a6f177ef 5412
8e3d9d06
XG		 5413 /*
5414 * Do not retry the unhandleable instruction if it faults on the
5415 * readonly host memory, otherwise it will goto a infinite loop:
5416 * retry instruction -> write #PF -> emulation fail -> retry
5417 * instruction -> ...
5418 */
5419 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5420
5421 /*
5422 * If the instruction failed on the error pfn, it can not be fixed,
5423 * report the error to userspace.
5424 */
5425 if (is_error_noslot_pfn(pfn))
5426 return false;
5427
5428 kvm_release_pfn_clean(pfn);
5429
5430 /* The instructions are well-emulated on direct mmu. */
5431 if (vcpu->arch.mmu.direct_map) {
5432 unsigned int indirect_shadow_pages;
5433
5434 spin_lock(&vcpu->kvm->mmu_lock);
5435 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5436 spin_unlock(&vcpu->kvm->mmu_lock);
5437
5438 if (indirect_shadow_pages)
5439 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5440
a6f177ef 5441 return true;
8e3d9d06 5442 }
a6f177ef 5443
95b3cf69
XG		 5444 /*
5445 * if emulation was due to access to shadowed page table
5446 * and it failed try to unshadow page and re-enter the
5447 * guest to let CPU execute the instruction.
5448 */
5449 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5450
5451 /*
5452 * If the access faults on its page table, it can not
5453 * be fixed by unprotecting shadow page and it should
5454 * be reported to userspace.
5455 */
5456 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5457}
5458
1cb3f3ae
XG		 5459static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5460 unsigned long cr2, int emulation_type)
5461{
5462 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5463 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5464
5465 last_retry_eip = vcpu->arch.last_retry_eip;
5466 last_retry_addr = vcpu->arch.last_retry_addr;
5467
5468 /*
5469 * If the emulation is caused by #PF and it is non-page_table
5470 * writing instruction, it means the VM-EXIT is caused by shadow
5471 * page protected, we can zap the shadow page and retry this
5472 * instruction directly.
5473 *
5474 * Note: if the guest uses a non-page-table modifying instruction
5475 * on the PDE that points to the instruction, then we will unmap
5476 * the instruction and go to an infinite loop. So, we cache the
5477 * last retried eip and the last fault address, if we meet the eip
5478 * and the address again, we can break out of the potential infinite
5479 * loop.
5480 */
5481 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5482
5483 if (!(emulation_type & EMULTYPE_RETRY))
5484 return false;
5485
5486 if (x86_page_table_writing_insn(ctxt))
5487 return false;
5488
5489 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5490 return false;
5491
5492 vcpu->arch.last_retry_eip = ctxt->eip;
5493 vcpu->arch.last_retry_addr = cr2;
5494
5495 if (!vcpu->arch.mmu.direct_map)
5496 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5497
22368028 5498 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5499
5500 return true;
5501}
5502
716d51ab
GN		 5503static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5504static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5505
64d60670 5506static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5507{
64d60670 5508 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5509 /* This is a good place to trace that we are exiting SMM. */
5510 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5511
c43203ca
PB		 5512 /* Process a latched INIT or SMI, if any. */
5513 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5514 }
699023e2
PB		 5515
5516 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5517}
5518
5519static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5520{
5521 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5522
a584539b 5523 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5524
5525 if (changed & HF_SMM_MASK)
5526 kvm_smm_changed(vcpu);
a584539b
PB		 5527}
5528
4a1e10d5
PB		 5529static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5530 unsigned long *db)
5531{
5532 u32 dr6 = 0;
5533 int i;
5534 u32 enable, rwlen;
5535
5536 enable = dr7;
5537 rwlen = dr7 >> 16;
5538 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5539 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5540 dr6 |= (1 << i);
5541 return dr6;
5542}
5543
c8401dda 5544static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5545{
5546 struct kvm_run *kvm_run = vcpu->run;
5547
c8401dda
PB		 5548 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5549 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5550 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5551 kvm_run->debug.arch.exception = DB_VECTOR;
5552 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5553 *r = EMULATE_USER_EXIT;
5554 } else {
5555 /*
5556 * "Certain debug exceptions may clear bit 0-3. The
5557 * remaining contents of the DR6 register are never
5558 * cleared by the processor".
5559 */
5560 vcpu->arch.dr6 &= ~15;
5561 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5562 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5563 }
5564}
5565
6affcbed
KH		 5566int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5567{
5568 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5569 int r = EMULATE_DONE;
5570
5571 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5572
5573 /*
5574 * rflags is the old, "raw" value of the flags. The new value has
5575 * not been saved yet.
5576 *
5577 * This is correct even for TF set by the guest, because "the
5578 * processor will not generate this exception after the instruction
5579 * that sets the TF flag".
5580 */
5581 if (unlikely(rflags & X86_EFLAGS_TF))
5582 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5583 return r == EMULATE_DONE;
5584}
5585EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5586
4a1e10d5
PB		 5587static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5588{
4a1e10d5
PB		 5589 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5590 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5591 struct kvm_run *kvm_run = vcpu->run;
5592 unsigned long eip = kvm_get_linear_rip(vcpu);
5593 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5594 vcpu->arch.guest_debug_dr7,
5595 vcpu->arch.eff_db);
5596
5597 if (dr6 != 0) {
6f43ed01 5598 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5599 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5600 kvm_run->debug.arch.exception = DB_VECTOR;
5601 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5602 *r = EMULATE_USER_EXIT;
5603 return true;
5604 }
5605 }
5606
4161a569
NA		 5607 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5608 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5609 unsigned long eip = kvm_get_linear_rip(vcpu);
5610 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5611 vcpu->arch.dr7,
5612 vcpu->arch.db);
5613
5614 if (dr6 != 0) {
5615 vcpu->arch.dr6 &= ~15;
6f43ed01 5616 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5617 kvm_queue_exception(vcpu, DB_VECTOR);
5618 *r = EMULATE_DONE;
5619 return true;
5620 }
5621 }
5622
5623 return false;
5624}
5625
51d8b661
AP		 5626int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5627 unsigned long cr2,
dc25e89e
AP		 5628 int emulation_type,
5629 void *insn,
5630 int insn_len)
bbd9b64e 5631{
95cb2295 5632 int r;
9d74191a 5633 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5634 bool writeback = true;
93c05d3e 5635 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5636
93c05d3e
XG		 5637 /*
5638 * Clear write_fault_to_shadow_pgtable here to ensure it is
5639 * never reused.
5640 */
5641 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5642 kvm_clear_exception_queue(vcpu);
8d7d8102 5643
571008da 5644 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5645 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5646
5647 /*
5648 * We will reenter on the same instruction since
5649 * we do not set complete_userspace_io. This does not
5650 * handle watchpoints yet, those would be handled in
5651 * the emulate_ops.
5652 */
5653 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5654 return r;
5655
9d74191a
TY		 5656 ctxt->interruptibility = 0;
5657 ctxt->have_exception = false;
e0ad0b47 5658 ctxt->exception.vector = -1;
9d74191a 5659 ctxt->perm_ok = false;
bbd9b64e 5660
b51e974f 5661 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5662
9d74191a 5663 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5664
e46479f8 5665 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5666 ++vcpu->stat.insn_emulation;
1d2887e2 5667 if (r != EMULATION_OK) {
4005996e
AK		 5668 if (emulation_type & EMULTYPE_TRAP_UD)
5669 return EMULATE_FAIL;
991eebf9
GN		 5670 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5671 emulation_type))
bbd9b64e 5672 return EMULATE_DONE;
6d77dbfc
GN		 5673 if (emulation_type & EMULTYPE_SKIP)
5674 return EMULATE_FAIL;
5675 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5676 }
5677 }
5678
ba8afb6b 5679 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5680 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5681 if (ctxt->eflags & X86_EFLAGS_RF)
5682 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5683 return EMULATE_DONE;
5684 }
5685
1cb3f3ae
XG		 5686 if (retry_instruction(ctxt, cr2, emulation_type))
5687 return EMULATE_DONE;
5688
7ae441ea 5689 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5690 changes registers values during IO operation */
7ae441ea
GN		 5691 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5692 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5693 emulator_invalidate_register_cache(ctxt);
7ae441ea 5694 }
4d2179e1 5695
5cd21917 5696restart:
0f89b207
TL		 5697 /* Save the faulting GPA (cr2) in the address field */
5698 ctxt->exception.address = cr2;
5699
9d74191a 5700 r = x86_emulate_insn(ctxt);
bbd9b64e 5701
775fde86
JR		 5702 if (r == EMULATION_INTERCEPTED)
5703 return EMULATE_DONE;
5704
d2ddd1c4 5705 if (r == EMULATION_FAILED) {
991eebf9
GN		 5706 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5707 emulation_type))
c3cd7ffa
GN		 5708 return EMULATE_DONE;
5709
6d77dbfc 5710 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5711 }
5712
9d74191a 5713 if (ctxt->have_exception) {
d2ddd1c4 5714 r = EMULATE_DONE;
ef54bcfe
PB		 5715 if (inject_emulated_exception(vcpu))
5716 return r;
d2ddd1c4 5717 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5718 if (!vcpu->arch.pio.in) {
5719 /* FIXME: return into emulator if single-stepping. */
3457e419 5720 vcpu->arch.pio.count = 0;
0912c977 5721 } else {
7ae441ea 5722 writeback = false;
716d51ab
GN		 5723 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5724 }
ac0a48c3 5725 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5726 } else if (vcpu->mmio_needed) {
5727 if (!vcpu->mmio_is_write)
5728 writeback = false;
ac0a48c3 5729 r = EMULATE_USER_EXIT;
716d51ab 5730 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5731 } else if (r == EMULATION_RESTART)
5cd21917 5732 goto restart;
d2ddd1c4
GN		 5733 else
5734 r = EMULATE_DONE;
f850e2e6 5735
7ae441ea 5736 if (writeback) {
6addfc42 5737 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5738 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5739 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5740 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5741 if (r == EMULATE_DONE &&
5742 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5743 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5744 if (!ctxt->have_exception ||
5745 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5746 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5747
5748 /*
5749 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5750 * do nothing, and it will be requested again as soon as
5751 * the shadow expires. But we still need to check here,
5752 * because POPF has no interrupt shadow.
5753 */
5754 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5755 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5756 } else
5757 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5758
5759 return r;
de7d789a 5760}
51d8b661 5761EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5762
cf8f70bf 5763int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5764{
cf8f70bf 5765 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5766 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5767 size, port, &val, 1);
cf8f70bf 5768 /* do not return to emulator after return from userspace */
7972995b 5769 vcpu->arch.pio.count = 0;
de7d789a
CO		 5770 return ret;
5771}
cf8f70bf 5772EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5773
8370c3d0
TL		 5774static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5775{
5776 unsigned long val;
5777
5778 /* We should only ever be called with arch.pio.count equal to 1 */
5779 BUG_ON(vcpu->arch.pio.count != 1);
5780
5781 /* For size less than 4 we merge, else we zero extend */
5782 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5783 : 0;
5784
5785 /*
5786 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5787 * the copy and tracing
5788 */
5789 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5790 vcpu->arch.pio.port, &val, 1);
5791 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5792
5793 return 1;
5794}
5795
5796int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5797{
5798 unsigned long val;
5799 int ret;
5800
5801 /* For size less than 4 we merge, else we zero extend */
5802 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5803
5804 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5805 &val, 1);
5806 if (ret) {
5807 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5808 return ret;
5809 }
5810
5811 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5812
5813 return 0;
5814}
5815EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5816
251a5fd6 5817static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5818{
0a3aee0d 5819 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5820 return 0;
8cfdc000
ZA		 5821}
5822
5823static void tsc_khz_changed(void *data)
c8076604 5824{
8cfdc000
ZA		 5825 struct cpufreq_freqs *freq = data;
5826 unsigned long khz = 0;
5827
5828 if (data)
5829 khz = freq->new;
5830 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5831 khz = cpufreq_quick_get(raw_smp_processor_id());
5832 if (!khz)
5833 khz = tsc_khz;
0a3aee0d 5834 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5835}
5836
c8076604
GH		 5837static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5838 void *data)
5839{
5840 struct cpufreq_freqs *freq = data;
5841 struct kvm *kvm;
5842 struct kvm_vcpu *vcpu;
5843 int i, send_ipi = 0;
5844
8cfdc000
ZA		 5845 /*
5846 * We allow guests to temporarily run on slowing clocks,
5847 * provided we notify them after, or to run on accelerating
5848 * clocks, provided we notify them before. Thus time never
5849 * goes backwards.
5850 *
5851 * However, we have a problem. We can't atomically update
5852 * the frequency of a given CPU from this function; it is
5853 * merely a notifier, which can be called from any CPU.
5854 * Changing the TSC frequency at arbitrary points in time
5855 * requires a recomputation of local variables related to
5856 * the TSC for each VCPU. We must flag these local variables
5857 * to be updated and be sure the update takes place with the
5858 * new frequency before any guests proceed.
5859 *
5860 * Unfortunately, the combination of hotplug CPU and frequency
5861 * change creates an intractable locking scenario; the order
5862 * of when these callouts happen is undefined with respect to
5863 * CPU hotplug, and they can race with each other. As such,
5864 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5865 * undefined; you can actually have a CPU frequency change take
5866 * place in between the computation of X and the setting of the
5867 * variable. To protect against this problem, all updates of
5868 * the per_cpu tsc_khz variable are done in an interrupt
5869 * protected IPI, and all callers wishing to update the value
5870 * must wait for a synchronous IPI to complete (which is trivial
5871 * if the caller is on the CPU already). This establishes the
5872 * necessary total order on variable updates.
5873 *
5874 * Note that because a guest time update may take place
5875 * anytime after the setting of the VCPU's request bit, the
5876 * correct TSC value must be set before the request. However,
5877 * to ensure the update actually makes it to any guest which
5878 * starts running in hardware virtualization between the set
5879 * and the acquisition of the spinlock, we must also ping the
5880 * CPU after setting the request bit.
5881 *
5882 */
5883
c8076604
GH		 5884 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5885 return 0;
5886 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5887 return 0;
8cfdc000
ZA		 5888
5889 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5890
2f303b74 5891 spin_lock(&kvm_lock);
c8076604 5892 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5893 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5894 if (vcpu->cpu != freq->cpu)
5895 continue;
c285545f 5896 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5897 if (vcpu->cpu != smp_processor_id())
8cfdc000 5898 send_ipi = 1;
c8076604
GH		 5899 }
5900 }
2f303b74 5901 spin_unlock(&kvm_lock);
c8076604
GH		 5902
5903 if (freq->old < freq->new && send_ipi) {
5904 /*
5905 * We upscale the frequency. Must make the guest
5906 * doesn't see old kvmclock values while running with
5907 * the new frequency, otherwise we risk the guest sees
5908 * time go backwards.
5909 *
5910 * In case we update the frequency for another cpu
5911 * (which might be in guest context) send an interrupt
5912 * to kick the cpu out of guest context. Next time
5913 * guest context is entered kvmclock will be updated,
5914 * so the guest will not see stale values.
5915 */
8cfdc000 5916 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5917 }
5918 return 0;
5919}
5920
5921static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5922 .notifier_call = kvmclock_cpufreq_notifier
5923};
5924
251a5fd6 5925static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5926{
251a5fd6
SAS		 5927 tsc_khz_changed(NULL);
5928 return 0;
8cfdc000
ZA		 5929}
5930
b820cc0c
ZA		 5931static void kvm_timer_init(void)
5932{
c285545f 5933 max_tsc_khz = tsc_khz;
460dd42e 5934
b820cc0c 5935 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5936#ifdef CONFIG_CPU_FREQ
5937 struct cpufreq_policy policy;
758f588d
BP		 5938 int cpu;
5939
c285545f 5940 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5941 cpu = get_cpu();
5942 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5943 if (policy.cpuinfo.max_freq)
5944 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5945 put_cpu();
c285545f 5946#endif
b820cc0c
ZA		 5947 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5948 CPUFREQ_TRANSITION_NOTIFIER);
5949 }
c285545f 5950 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5951
73c1b41e 5952 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5953 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5954}
5955
ff9d07a0
ZY		 5956static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5957
f5132b01 5958int kvm_is_in_guest(void)
ff9d07a0 5959{
086c9855 5960 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5961}
5962
5963static int kvm_is_user_mode(void)
5964{
5965 int user_mode = 3;
dcf46b94 5966
086c9855
AS		 5967 if (__this_cpu_read(current_vcpu))
5968 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5969
ff9d07a0
ZY		 5970 return user_mode != 0;
5971}
5972
5973static unsigned long kvm_get_guest_ip(void)
5974{
5975 unsigned long ip = 0;
dcf46b94 5976
086c9855
AS		 5977 if (__this_cpu_read(current_vcpu))
5978 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5979
ff9d07a0
ZY		 5980 return ip;
5981}
5982
5983static struct perf_guest_info_callbacks kvm_guest_cbs = {
5984 .is_in_guest = kvm_is_in_guest,
5985 .is_user_mode = kvm_is_user_mode,
5986 .get_guest_ip = kvm_get_guest_ip,
5987};
5988
5989void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5990{
086c9855 5991 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5992}
5993EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5994
5995void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5996{
086c9855 5997 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5998}
5999EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6000
ce88decf
XG		 6001static void kvm_set_mmio_spte_mask(void)
6002{
6003 u64 mask;
6004 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6005
6006 /*
6007 * Set the reserved bits and the present bit of an paging-structure
6008 * entry to generate page fault with PFER.RSV = 1.
6009 */
885032b9 6010 /* Mask the reserved physical address bits. */
d1431483 6011 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6012
885032b9 6013 /* Set the present bit. */
ce88decf
XG		 6014 mask |= 1ull;
6015
6016#ifdef CONFIG_X86_64
6017 /*
6018 * If reserved bit is not supported, clear the present bit to disable
6019 * mmio page fault.
6020 */
6021 if (maxphyaddr == 52)
6022 mask &= ~1ull;
6023#endif
6024
dcdca5fe 6025 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6026}
6027
16e8d74d
MT		 6028#ifdef CONFIG_X86_64
6029static void pvclock_gtod_update_fn(struct work_struct *work)
6030{
d828199e
MT		 6031 struct kvm *kvm;
6032
6033 struct kvm_vcpu *vcpu;
6034 int i;
6035
2f303b74 6036 spin_lock(&kvm_lock);
d828199e
MT		 6037 list_for_each_entry(kvm, &vm_list, vm_list)
6038 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6039 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6040 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6041 spin_unlock(&kvm_lock);
16e8d74d
MT		 6042}
6043
6044static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6045
6046/*
6047 * Notification about pvclock gtod data update.
6048 */
6049static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6050 void *priv)
6051{
6052 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6053 struct timekeeper *tk = priv;
6054
6055 update_pvclock_gtod(tk);
6056
6057 /* disable master clock if host does not trust, or does not
6058 * use, TSC clocksource
6059 */
6060 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6061 atomic_read(&kvm_guest_has_master_clock) != 0)
6062 queue_work(system_long_wq, &pvclock_gtod_work);
6063
6064 return 0;
6065}
6066
6067static struct notifier_block pvclock_gtod_notifier = {
6068 .notifier_call = pvclock_gtod_notify,
6069};
6070#endif
6071
f8c16bba 6072int kvm_arch_init(void *opaque)
043405e1 6073{
b820cc0c 6074 int r;
6b61edf7 6075 struct kvm_x86_ops *ops = opaque;
f8c16bba 6076
f8c16bba
ZX		 6077 if (kvm_x86_ops) {
6078 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6079 r = -EEXIST;
6080 goto out;
f8c16bba
ZX		 6081 }
6082
6083 if (!ops->cpu_has_kvm_support()) {
6084 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6085 r = -EOPNOTSUPP;
6086 goto out;
f8c16bba
ZX		 6087 }
6088 if (ops->disabled_by_bios()) {
6089 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6090 r = -EOPNOTSUPP;
6091 goto out;
f8c16bba
ZX		 6092 }
6093
013f6a5d
MT		 6094 r = -ENOMEM;
6095 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6096 if (!shared_msrs) {
6097 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6098 goto out;
6099 }
6100
97db56ce
AK		 6101 r = kvm_mmu_module_init();
6102 if (r)
013f6a5d 6103 goto out_free_percpu;
97db56ce 6104
ce88decf 6105 kvm_set_mmio_spte_mask();
97db56ce 6106
f8c16bba 6107 kvm_x86_ops = ops;
920c8377 6108
7b52345e 6109 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6110 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6111 PT_PRESENT_MASK, 0);
b820cc0c 6112 kvm_timer_init();
c8076604 6113
ff9d07a0
ZY		 6114 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6115
d366bf7e 6116 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6117 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6118
c5cc421b 6119 kvm_lapic_init();
16e8d74d
MT		 6120#ifdef CONFIG_X86_64
6121 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6122#endif
6123
f8c16bba 6124 return 0;
56c6d28a 6125
013f6a5d
MT		 6126out_free_percpu:
6127 free_percpu(shared_msrs);
56c6d28a 6128out:
56c6d28a 6129 return r;
043405e1 6130}
8776e519 6131
f8c16bba
ZX		 6132void kvm_arch_exit(void)
6133{
cef84c30 6134 kvm_lapic_exit();
ff9d07a0
ZY		 6135 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6136
888d256e
JK		 6137 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6138 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6139 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6140 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6141#ifdef CONFIG_X86_64
6142 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6143#endif
f8c16bba 6144 kvm_x86_ops = NULL;
56c6d28a 6145 kvm_mmu_module_exit();
013f6a5d 6146 free_percpu(shared_msrs);
56c6d28a 6147}
f8c16bba 6148
5cb56059 6149int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6150{
6151 ++vcpu->stat.halt_exits;
35754c98 6152 if (lapic_in_kernel(vcpu)) {
a4535290 6153 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6154 return 1;
6155 } else {
6156 vcpu->run->exit_reason = KVM_EXIT_HLT;
6157 return 0;
6158 }
6159}
5cb56059
JS		 6160EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6161
6162int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6163{
6affcbed
KH		 6164 int ret = kvm_skip_emulated_instruction(vcpu);
6165 /*
6166 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6167 * KVM_EXIT_DEBUG here.
6168 */
6169 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6170}
8776e519
HB		 6171EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6172
8ef81a9a 6173#ifdef CONFIG_X86_64
55dd00a7
MT		 6174static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6175 unsigned long clock_type)
6176{
6177 struct kvm_clock_pairing clock_pairing;
6178 struct timespec ts;
80fbd89c 6179 u64 cycle;
55dd00a7
MT		 6180 int ret;
6181
6182 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6183 return -KVM_EOPNOTSUPP;
6184
6185 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6186 return -KVM_EOPNOTSUPP;
6187
6188 clock_pairing.sec = ts.tv_sec;
6189 clock_pairing.nsec = ts.tv_nsec;
6190 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6191 clock_pairing.flags = 0;
6192
6193 ret = 0;
6194 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6195 sizeof(struct kvm_clock_pairing)))
6196 ret = -KVM_EFAULT;
6197
6198 return ret;
6199}
8ef81a9a 6200#endif
55dd00a7 6201
6aef266c
SV		 6202/*
6203 * kvm_pv_kick_cpu_op: Kick a vcpu.
6204 *
6205 * @apicid - apicid of vcpu to be kicked.
6206 */
6207static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6208{
24d2166b 6209 struct kvm_lapic_irq lapic_irq;
6aef266c 6210
24d2166b
R		 6211 lapic_irq.shorthand = 0;
6212 lapic_irq.dest_mode = 0;
ebd28fcb 6213 lapic_irq.level = 0;
24d2166b 6214 lapic_irq.dest_id = apicid;
93bbf0b8 6215 lapic_irq.msi_redir_hint = false;
6aef266c 6216
24d2166b 6217 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6218 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6219}
6220
d62caabb
AS		 6221void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6222{
6223 vcpu->arch.apicv_active = false;
6224 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6225}
6226
8776e519
HB		 6227int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6228{
6229 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6230 int op_64_bit, r;
8776e519 6231
6affcbed 6232 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6233
55cd8e5a
GN		 6234 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6235 return kvm_hv_hypercall(vcpu);
6236
5fdbf976
MT		 6237 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6238 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6239 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6240 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6241 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6242
229456fc 6243 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6244
a449c7aa
NA		 6245 op_64_bit = is_64_bit_mode(vcpu);
6246 if (!op_64_bit) {
8776e519
HB		 6247 nr &= 0xFFFFFFFF;
6248 a0 &= 0xFFFFFFFF;
6249 a1 &= 0xFFFFFFFF;
6250 a2 &= 0xFFFFFFFF;
6251 a3 &= 0xFFFFFFFF;
6252 }
6253
07708c4a
JK		 6254 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6255 ret = -KVM_EPERM;
6256 goto out;
6257 }
6258
8776e519 6259 switch (nr) {
b93463aa
AK		 6260 case KVM_HC_VAPIC_POLL_IRQ:
6261 ret = 0;
6262 break;
6aef266c
SV		 6263 case KVM_HC_KICK_CPU:
6264 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6265 ret = 0;
6266 break;
8ef81a9a 6267#ifdef CONFIG_X86_64
55dd00a7
MT		 6268 case KVM_HC_CLOCK_PAIRING:
6269 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6270 break;
8ef81a9a 6271#endif
8776e519
HB		 6272 default:
6273 ret = -KVM_ENOSYS;
6274 break;
6275 }
07708c4a 6276out:
a449c7aa
NA		 6277 if (!op_64_bit)
6278 ret = (u32)ret;
5fdbf976 6279 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6280 ++vcpu->stat.hypercalls;
2f333bcb 6281 return r;
8776e519
HB		 6282}
6283EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6284
b6785def 6285static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6286{
d6aa1000 6287 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6288 char instruction[3];
5fdbf976 6289 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6290
8776e519 6291 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6292
ce2e852e
DV		 6293 return emulator_write_emulated(ctxt, rip, instruction, 3,
6294 &ctxt->exception);
8776e519
HB		 6295}
6296
851ba692 6297static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6298{
782d422b
MG		 6299 return vcpu->run->request_interrupt_window &&
6300 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6301}
6302
851ba692 6303static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6304{
851ba692
AK		 6305 struct kvm_run *kvm_run = vcpu->run;
6306
91586a3b 6307 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6308 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6309 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6310 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6311 kvm_run->ready_for_interrupt_injection =
6312 pic_in_kernel(vcpu->kvm) ||
782d422b 6313 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6314}
6315
95ba8273
GN		 6316static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6317{
6318 int max_irr, tpr;
6319
6320 if (!kvm_x86_ops->update_cr8_intercept)
6321 return;
6322
bce87cce 6323 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6324 return;
6325
d62caabb
AS		 6326 if (vcpu->arch.apicv_active)
6327 return;
6328
8db3baa2
GN		 6329 if (!vcpu->arch.apic->vapic_addr)
6330 max_irr = kvm_lapic_find_highest_irr(vcpu);
6331 else
6332 max_irr = -1;
95ba8273
GN		 6333
6334 if (max_irr != -1)
6335 max_irr >>= 4;
6336
6337 tpr = kvm_lapic_get_cr8(vcpu);
6338
6339 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6340}
6341
b6b8a145 6342static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6343{
b6b8a145
JK		 6344 int r;
6345
95ba8273 6346 /* try to reinject previous events if any */
b59bb7bd 6347 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6348 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6349 vcpu->arch.exception.has_error_code,
6350 vcpu->arch.exception.error_code);
d6e8c854
NA		 6351
6352 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6353 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6354 X86_EFLAGS_RF);
6355
6bdf0662
NA		 6356 if (vcpu->arch.exception.nr == DB_VECTOR &&
6357 (vcpu->arch.dr7 & DR7_GD)) {
6358 vcpu->arch.dr7 &= ~DR7_GD;
6359 kvm_update_dr7(vcpu);
6360 }
6361
cfcd20e5 6362 kvm_x86_ops->queue_exception(vcpu);
b6b8a145 6363 return 0;
b59bb7bd
GN		 6364 }
6365
95ba8273
GN		 6366 if (vcpu->arch.nmi_injected) {
6367 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6368 return 0;
95ba8273
GN		 6369 }
6370
6371 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6372 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6373 return 0;
6374 }
6375
6376 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6377 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6378 if (r != 0)
6379 return r;
95ba8273
GN		 6380 }
6381
6382 /* try to inject new event if pending */
c43203ca
PB		 6383 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6384 vcpu->arch.smi_pending = false;
ee2cd4b7 6385 enter_smm(vcpu);
c43203ca 6386 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6387 --vcpu->arch.nmi_pending;
6388 vcpu->arch.nmi_injected = true;
6389 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6390 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6391 /*
6392 * Because interrupts can be injected asynchronously, we are
6393 * calling check_nested_events again here to avoid a race condition.
6394 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6395 * proposal and current concerns. Perhaps we should be setting
6396 * KVM_REQ_EVENT only on certain events and not unconditionally?
6397 */
6398 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6399 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6400 if (r != 0)
6401 return r;
6402 }
95ba8273 6403 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6404 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6405 false);
6406 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6407 }
6408 }
ee2cd4b7 6409
b6b8a145 6410 return 0;
95ba8273
GN		 6411}
6412
7460fb4a
AK		 6413static void process_nmi(struct kvm_vcpu *vcpu)
6414{
6415 unsigned limit = 2;
6416
6417 /*
6418 * x86 is limited to one NMI running, and one NMI pending after it.
6419 * If an NMI is already in progress, limit further NMIs to just one.
6420 * Otherwise, allow two (and we'll inject the first one immediately).
6421 */
6422 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6423 limit = 1;
6424
6425 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6426 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6427 kvm_make_request(KVM_REQ_EVENT, vcpu);
6428}
6429
660a5d51
PB		 6430#define put_smstate(type, buf, offset, val) \
6431 *(type *)((buf) + (offset) - 0x7e00) = val
6432
ee2cd4b7 6433static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6434{
6435 u32 flags = 0;
6436 flags |= seg->g << 23;
6437 flags |= seg->db << 22;
6438 flags |= seg->l << 21;
6439 flags |= seg->avl << 20;
6440 flags |= seg->present << 15;
6441 flags |= seg->dpl << 13;
6442 flags |= seg->s << 12;
6443 flags |= seg->type << 8;
6444 return flags;
6445}
6446
ee2cd4b7 6447static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6448{
6449 struct kvm_segment seg;
6450 int offset;
6451
6452 kvm_get_segment(vcpu, &seg, n);
6453 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6454
6455 if (n < 3)
6456 offset = 0x7f84 + n * 12;
6457 else
6458 offset = 0x7f2c + (n - 3) * 12;
6459
6460 put_smstate(u32, buf, offset + 8, seg.base);
6461 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6462 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6463}
6464
efbb288a 6465#ifdef CONFIG_X86_64
ee2cd4b7 6466static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6467{
6468 struct kvm_segment seg;
6469 int offset;
6470 u16 flags;
6471
6472 kvm_get_segment(vcpu, &seg, n);
6473 offset = 0x7e00 + n * 16;
6474
ee2cd4b7 6475 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6476 put_smstate(u16, buf, offset, seg.selector);
6477 put_smstate(u16, buf, offset + 2, flags);
6478 put_smstate(u32, buf, offset + 4, seg.limit);
6479 put_smstate(u64, buf, offset + 8, seg.base);
6480}
efbb288a 6481#endif
660a5d51 6482
ee2cd4b7 6483static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6484{
6485 struct desc_ptr dt;
6486 struct kvm_segment seg;
6487 unsigned long val;
6488 int i;
6489
6490 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6491 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6492 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6493 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6494
6495 for (i = 0; i < 8; i++)
6496 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6497
6498 kvm_get_dr(vcpu, 6, &val);
6499 put_smstate(u32, buf, 0x7fcc, (u32)val);
6500 kvm_get_dr(vcpu, 7, &val);
6501 put_smstate(u32, buf, 0x7fc8, (u32)val);
6502
6503 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6504 put_smstate(u32, buf, 0x7fc4, seg.selector);
6505 put_smstate(u32, buf, 0x7f64, seg.base);
6506 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6507 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6508
6509 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6510 put_smstate(u32, buf, 0x7fc0, seg.selector);
6511 put_smstate(u32, buf, 0x7f80, seg.base);
6512 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6513 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6514
6515 kvm_x86_ops->get_gdt(vcpu, &dt);
6516 put_smstate(u32, buf, 0x7f74, dt.address);
6517 put_smstate(u32, buf, 0x7f70, dt.size);
6518
6519 kvm_x86_ops->get_idt(vcpu, &dt);
6520 put_smstate(u32, buf, 0x7f58, dt.address);
6521 put_smstate(u32, buf, 0x7f54, dt.size);
6522
6523 for (i = 0; i < 6; i++)
ee2cd4b7 6524 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6525
6526 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6527
6528 /* revision id */
6529 put_smstate(u32, buf, 0x7efc, 0x00020000);
6530 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6531}
6532
ee2cd4b7 6533static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6534{
6535#ifdef CONFIG_X86_64
6536 struct desc_ptr dt;
6537 struct kvm_segment seg;
6538 unsigned long val;
6539 int i;
6540
6541 for (i = 0; i < 16; i++)
6542 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6543
6544 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6545 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6546
6547 kvm_get_dr(vcpu, 6, &val);
6548 put_smstate(u64, buf, 0x7f68, val);
6549 kvm_get_dr(vcpu, 7, &val);
6550 put_smstate(u64, buf, 0x7f60, val);
6551
6552 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6553 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6554 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6555
6556 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6557
6558 /* revision id */
6559 put_smstate(u32, buf, 0x7efc, 0x00020064);
6560
6561 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6562
6563 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6564 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6565 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6566 put_smstate(u32, buf, 0x7e94, seg.limit);
6567 put_smstate(u64, buf, 0x7e98, seg.base);
6568
6569 kvm_x86_ops->get_idt(vcpu, &dt);
6570 put_smstate(u32, buf, 0x7e84, dt.size);
6571 put_smstate(u64, buf, 0x7e88, dt.address);
6572
6573 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6574 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6575 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6576 put_smstate(u32, buf, 0x7e74, seg.limit);
6577 put_smstate(u64, buf, 0x7e78, seg.base);
6578
6579 kvm_x86_ops->get_gdt(vcpu, &dt);
6580 put_smstate(u32, buf, 0x7e64, dt.size);
6581 put_smstate(u64, buf, 0x7e68, dt.address);
6582
6583 for (i = 0; i < 6; i++)
ee2cd4b7 6584 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6585#else
6586 WARN_ON_ONCE(1);
6587#endif
6588}
6589
ee2cd4b7 6590static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6591{
660a5d51 6592 struct kvm_segment cs, ds;
18c3626e 6593 struct desc_ptr dt;
660a5d51
PB		 6594 char buf[512];
6595 u32 cr0;
6596
660a5d51
PB		 6597 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6598 vcpu->arch.hflags |= HF_SMM_MASK;
6599 memset(buf, 0, 512);
d6321d49 6600 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6601 enter_smm_save_state_64(vcpu, buf);
660a5d51 6602 else
ee2cd4b7 6603 enter_smm_save_state_32(vcpu, buf);
660a5d51 6604
54bf36aa 6605 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6606
6607 if (kvm_x86_ops->get_nmi_mask(vcpu))
6608 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6609 else
6610 kvm_x86_ops->set_nmi_mask(vcpu, true);
6611
6612 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6613 kvm_rip_write(vcpu, 0x8000);
6614
6615 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6616 kvm_x86_ops->set_cr0(vcpu, cr0);
6617 vcpu->arch.cr0 = cr0;
6618
6619 kvm_x86_ops->set_cr4(vcpu, 0);
6620
18c3626e
PB		 6621 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6622 dt.address = dt.size = 0;
6623 kvm_x86_ops->set_idt(vcpu, &dt);
6624
660a5d51
PB		 6625 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6626
6627 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6628 cs.base = vcpu->arch.smbase;
6629
6630 ds.selector = 0;
6631 ds.base = 0;
6632
6633 cs.limit = ds.limit = 0xffffffff;
6634 cs.type = ds.type = 0x3;
6635 cs.dpl = ds.dpl = 0;
6636 cs.db = ds.db = 0;
6637 cs.s = ds.s = 1;
6638 cs.l = ds.l = 0;
6639 cs.g = ds.g = 1;
6640 cs.avl = ds.avl = 0;
6641 cs.present = ds.present = 1;
6642 cs.unusable = ds.unusable = 0;
6643 cs.padding = ds.padding = 0;
6644
6645 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6646 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6647 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6648 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6649 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6650 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6651
d6321d49 6652 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6653 kvm_x86_ops->set_efer(vcpu, 0);
6654
6655 kvm_update_cpuid(vcpu);
6656 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6657}
6658
ee2cd4b7 6659static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6660{
6661 vcpu->arch.smi_pending = true;
6662 kvm_make_request(KVM_REQ_EVENT, vcpu);
6663}
6664
2860c4b1
PB		 6665void kvm_make_scan_ioapic_request(struct kvm *kvm)
6666{
6667 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6668}
6669
3d81bc7e 6670static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6671{
5c919412
AS		 6672 u64 eoi_exit_bitmap[4];
6673
3d81bc7e
YZ		 6674 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6675 return;
c7c9c56c 6676
6308630b 6677 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6678
b053b2ae 6679 if (irqchip_split(vcpu->kvm))
6308630b 6680 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6681 else {
76dfafd5 6682 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6683 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6684 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6685 }
5c919412
AS		 6686 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6687 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6688 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6689}
6690
a70656b6
RK		 6691static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6692{
6693 ++vcpu->stat.tlb_flush;
6694 kvm_x86_ops->tlb_flush(vcpu);
6695}
6696
4256f43f
TC		 6697void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6698{
c24ae0dc
TC		 6699 struct page *page = NULL;
6700
35754c98 6701 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6702 return;
6703
4256f43f
TC		 6704 if (!kvm_x86_ops->set_apic_access_page_addr)
6705 return;
6706
c24ae0dc 6707 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6708 if (is_error_page(page))
6709 return;
c24ae0dc
TC		 6710 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6711
6712 /*
6713 * Do not pin apic access page in memory, the MMU notifier
6714 * will call us again if it is migrated or swapped out.
6715 */
6716 put_page(page);
4256f43f
TC		 6717}
6718EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6719
fe71557a
TC		 6720void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6721 unsigned long address)
6722{
c24ae0dc
TC		 6723 /*
6724 * The physical address of apic access page is stored in the VMCS.
6725 * Update it when it becomes invalid.
6726 */
6727 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6728 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6729}
6730
9357d939 6731/*
362c698f 6732 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6733 * exiting to the userspace. Otherwise, the value will be returned to the
6734 * userspace.
6735 */
851ba692 6736static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6737{
6738 int r;
62a193ed
MG		 6739 bool req_int_win =
6740 dm_request_for_irq_injection(vcpu) &&
6741 kvm_cpu_accept_dm_intr(vcpu);
6742
730dca42 6743 bool req_immediate_exit = false;
b6c7a5dc 6744
2fa6e1e1 6745 if (kvm_request_pending(vcpu)) {
a8eeb04a 6746 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6747 kvm_mmu_unload(vcpu);
a8eeb04a 6748 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6749 __kvm_migrate_timers(vcpu);
d828199e
MT		 6750 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6751 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6752 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6753 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6754 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6755 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6756 if (unlikely(r))
6757 goto out;
6758 }
a8eeb04a 6759 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6760 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6761 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6762 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6763 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6764 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6765 r = 0;
6766 goto out;
6767 }
a8eeb04a 6768 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6769 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6770 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6771 r = 0;
6772 goto out;
6773 }
af585b92
GN		 6774 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6775 /* Page is swapped out. Do synthetic halt */
6776 vcpu->arch.apf.halted = true;
6777 r = 1;
6778 goto out;
6779 }
c9aaa895
GC		 6780 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6781 record_steal_time(vcpu);
64d60670
PB		 6782 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6783 process_smi(vcpu);
7460fb4a
AK		 6784 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6785 process_nmi(vcpu);
f5132b01 6786 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6787 kvm_pmu_handle_event(vcpu);
f5132b01 6788 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6789 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6790 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6791 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6792 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6793 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6794 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6795 vcpu->run->eoi.vector =
6796 vcpu->arch.pending_ioapic_eoi;
6797 r = 0;
6798 goto out;
6799 }
6800 }
3d81bc7e
YZ		 6801 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6802 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6803 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6804 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6805 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6806 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6807 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6808 r = 0;
6809 goto out;
6810 }
e516cebb
AS		 6811 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6812 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6813 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6814 r = 0;
6815 goto out;
6816 }
db397571
AS		 6817 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6818 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6819 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6820 r = 0;
6821 goto out;
6822 }
f3b138c5
AS		 6823
6824 /*
6825 * KVM_REQ_HV_STIMER has to be processed after
6826 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6827 * depend on the guest clock being up-to-date
6828 */
1f4b34f8
AS		 6829 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6830 kvm_hv_process_stimers(vcpu);
2f52d58c 6831 }
b93463aa 6832
b463a6f7 6833 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6834 ++vcpu->stat.req_event;
66450a21
JK		 6835 kvm_apic_accept_events(vcpu);
6836 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6837 r = 1;
6838 goto out;
6839 }
6840
b6b8a145
JK		 6841 if (inject_pending_event(vcpu, req_int_win) != 0)
6842 req_immediate_exit = true;
321c5658 6843 else {
c43203ca
PB		 6844 /* Enable NMI/IRQ window open exits if needed.
6845 *
6846 * SMIs have two cases: 1) they can be nested, and
6847 * then there is nothing to do here because RSM will
6848 * cause a vmexit anyway; 2) or the SMI can be pending
6849 * because inject_pending_event has completed the
6850 * injection of an IRQ or NMI from the previous vmexit,
6851 * and then we request an immediate exit to inject the SMI.
6852 */
6853 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6854 req_immediate_exit = true;
321c5658
YS		 6855 if (vcpu->arch.nmi_pending)
6856 kvm_x86_ops->enable_nmi_window(vcpu);
6857 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6858 kvm_x86_ops->enable_irq_window(vcpu);
6859 }
b463a6f7
AK		 6860
6861 if (kvm_lapic_enabled(vcpu)) {
6862 update_cr8_intercept(vcpu);
6863 kvm_lapic_sync_to_vapic(vcpu);
6864 }
6865 }
6866
d8368af8
AK		 6867 r = kvm_mmu_reload(vcpu);
6868 if (unlikely(r)) {
d905c069 6869 goto cancel_injection;
d8368af8
AK		 6870 }
6871
b6c7a5dc
HB		 6872 preempt_disable();
6873
6874 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6875 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6876
6877 /*
6878 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6879 * IPI are then delayed after guest entry, which ensures that they
6880 * result in virtual interrupt delivery.
6881 */
6882 local_irq_disable();
6b7e2d09
XG		 6883 vcpu->mode = IN_GUEST_MODE;
6884
01b71917
MT		 6885 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6886
0f127d12 6887 /*
b95234c8 6888 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6889 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6890 *
6891 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6892 * pairs with the memory barrier implicit in pi_test_and_set_on
6893 * (see vmx_deliver_posted_interrupt).
6894 *
6895 * 3) This also orders the write to mode from any reads to the page
6896 * tables done while the VCPU is running. Please see the comment
6897 * in kvm_flush_remote_tlbs.
6b7e2d09 6898 */
01b71917 6899 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6900
b95234c8
PB		 6901 /*
6902 * This handles the case where a posted interrupt was
6903 * notified with kvm_vcpu_kick.
6904 */
6905 if (kvm_lapic_enabled(vcpu)) {
6906 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6907 kvm_x86_ops->sync_pir_to_irr(vcpu);
6908 }
32f88400 6909
2fa6e1e1 6910 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6911 || need_resched() || signal_pending(current)) {
6b7e2d09 6912 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6913 smp_wmb();
6c142801
AK		 6914 local_irq_enable();
6915 preempt_enable();
01b71917 6916 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6917 r = 1;
d905c069 6918 goto cancel_injection;
6c142801
AK		 6919 }
6920
fc5b7f3b
DM		 6921 kvm_load_guest_xcr0(vcpu);
6922
c43203ca
PB		 6923 if (req_immediate_exit) {
6924 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6925 smp_send_reschedule(vcpu->cpu);
c43203ca 6926 }
d6185f20 6927
8b89fe1f
PB		 6928 trace_kvm_entry(vcpu->vcpu_id);
6929 wait_lapic_expire(vcpu);
6edaa530 6930 guest_enter_irqoff();
b6c7a5dc 6931
42dbaa5a 6932 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6933 set_debugreg(0, 7);
6934 set_debugreg(vcpu->arch.eff_db[0], 0);
6935 set_debugreg(vcpu->arch.eff_db[1], 1);
6936 set_debugreg(vcpu->arch.eff_db[2], 2);
6937 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6938 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6939 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6940 }
b6c7a5dc 6941
851ba692 6942 kvm_x86_ops->run(vcpu);
b6c7a5dc 6943
c77fb5fe
PB		 6944 /*
6945 * Do this here before restoring debug registers on the host. And
6946 * since we do this before handling the vmexit, a DR access vmexit
6947 * can (a) read the correct value of the debug registers, (b) set
6948 * KVM_DEBUGREG_WONT_EXIT again.
6949 */
6950 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6951 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6952 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6953 kvm_update_dr0123(vcpu);
6954 kvm_update_dr6(vcpu);
6955 kvm_update_dr7(vcpu);
6956 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6957 }
6958
24f1e32c
FW		 6959 /*
6960 * If the guest has used debug registers, at least dr7
6961 * will be disabled while returning to the host.
6962 * If we don't have active breakpoints in the host, we don't
6963 * care about the messed up debug address registers. But if
6964 * we have some of them active, restore the old state.
6965 */
59d8eb53 6966 if (hw_breakpoint_active())
24f1e32c 6967 hw_breakpoint_restore();
42dbaa5a 6968
4ba76538 6969 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6970
6b7e2d09 6971 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6972 smp_wmb();
a547c6db 6973
fc5b7f3b
DM		 6974 kvm_put_guest_xcr0(vcpu);
6975
a547c6db 6976 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6977
6978 ++vcpu->stat.exits;
6979
f2485b3e 6980 guest_exit_irqoff();
b6c7a5dc 6981
f2485b3e 6982 local_irq_enable();
b6c7a5dc
HB		 6983 preempt_enable();
6984
f656ce01 6985 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6986
b6c7a5dc
HB		 6987 /*
6988 * Profile KVM exit RIPs:
6989 */
6990 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6991 unsigned long rip = kvm_rip_read(vcpu);
6992 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6993 }
6994
cc578287
ZA		 6995 if (unlikely(vcpu->arch.tsc_always_catchup))
6996 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6997
5cfb1d5a
MT		 6998 if (vcpu->arch.apic_attention)
6999 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7000
618232e2 7001 vcpu->arch.gpa_available = false;
851ba692 7002 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7003 return r;
7004
7005cancel_injection:
7006 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7007 if (unlikely(vcpu->arch.apic_attention))
7008 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7009out:
7010 return r;
7011}
b6c7a5dc 7012
362c698f
PB		 7013static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7014{
bf9f6ac8
FW		 7015 if (!kvm_arch_vcpu_runnable(vcpu) &&
7016 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7017 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7018 kvm_vcpu_block(vcpu);
7019 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7020
7021 if (kvm_x86_ops->post_block)
7022 kvm_x86_ops->post_block(vcpu);
7023
9c8fd1ba
PB		 7024 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7025 return 1;
7026 }
362c698f
PB		 7027
7028 kvm_apic_accept_events(vcpu);
7029 switch(vcpu->arch.mp_state) {
7030 case KVM_MP_STATE_HALTED:
7031 vcpu->arch.pv.pv_unhalted = false;
7032 vcpu->arch.mp_state =
7033 KVM_MP_STATE_RUNNABLE;
7034 case KVM_MP_STATE_RUNNABLE:
7035 vcpu->arch.apf.halted = false;
7036 break;
7037 case KVM_MP_STATE_INIT_RECEIVED:
7038 break;
7039 default:
7040 return -EINTR;
7041 break;
7042 }
7043 return 1;
7044}
09cec754 7045
5d9bc648
PB		 7046static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7047{
0ad3bed6
PB		 7048 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7049 kvm_x86_ops->check_nested_events(vcpu, false);
7050
5d9bc648
PB		 7051 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7052 !vcpu->arch.apf.halted);
7053}
7054
362c698f 7055static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7056{
7057 int r;
f656ce01 7058 struct kvm *kvm = vcpu->kvm;
d7690175 7059
f656ce01 7060 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7061
362c698f 7062 for (;;) {
58f800d5 7063 if (kvm_vcpu_running(vcpu)) {
851ba692 7064 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7065 } else {
362c698f 7066 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7067 }
7068
09cec754
GN		 7069 if (r <= 0)
7070 break;
7071
72875d8a 7072 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7073 if (kvm_cpu_has_pending_timer(vcpu))
7074 kvm_inject_pending_timer_irqs(vcpu);
7075
782d422b
MG		 7076 if (dm_request_for_irq_injection(vcpu) &&
7077 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7078 r = 0;
7079 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7080 ++vcpu->stat.request_irq_exits;
362c698f 7081 break;
09cec754 7082 }
af585b92
GN		 7083
7084 kvm_check_async_pf_completion(vcpu);
7085
09cec754
GN		 7086 if (signal_pending(current)) {
7087 r = -EINTR;
851ba692 7088 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7089 ++vcpu->stat.signal_exits;
362c698f 7090 break;
09cec754
GN		 7091 }
7092 if (need_resched()) {
f656ce01 7093 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7094 cond_resched();
f656ce01 7095 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7096 }
b6c7a5dc
HB		 7097 }
7098
f656ce01 7099 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7100
7101 return r;
7102}
7103
716d51ab
GN		 7104static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7105{
7106 int r;
7107 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7108 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7109 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7110 if (r != EMULATE_DONE)
7111 return 0;
7112 return 1;
7113}
7114
7115static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7116{
7117 BUG_ON(!vcpu->arch.pio.count);
7118
7119 return complete_emulated_io(vcpu);
7120}
7121
f78146b0
AK		 7122/*
7123 * Implements the following, as a state machine:
7124 *
7125 * read:
7126 * for each fragment
87da7e66
XG		 7127 * for each mmio piece in the fragment
7128 * write gpa, len
7129 * exit
7130 * copy data
f78146b0
AK		 7131 * execute insn
7132 *
7133 * write:
7134 * for each fragment
87da7e66
XG		 7135 * for each mmio piece in the fragment
7136 * write gpa, len
7137 * copy data
7138 * exit
f78146b0 7139 */
716d51ab 7140static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7141{
7142 struct kvm_run *run = vcpu->run;
f78146b0 7143 struct kvm_mmio_fragment *frag;
87da7e66 7144 unsigned len;
5287f194 7145
716d51ab 7146 BUG_ON(!vcpu->mmio_needed);
5287f194 7147
716d51ab 7148 /* Complete previous fragment */
87da7e66
XG		 7149 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7150 len = min(8u, frag->len);
716d51ab 7151 if (!vcpu->mmio_is_write)
87da7e66
XG		 7152 memcpy(frag->data, run->mmio.data, len);
7153
7154 if (frag->len <= 8) {
7155 /* Switch to the next fragment. */
7156 frag++;
7157 vcpu->mmio_cur_fragment++;
7158 } else {
7159 /* Go forward to the next mmio piece. */
7160 frag->data += len;
7161 frag->gpa += len;
7162 frag->len -= len;
7163 }
7164
a08d3b3b 7165 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7166 vcpu->mmio_needed = 0;
0912c977
PB		 7167
7168 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7169 if (vcpu->mmio_is_write)
716d51ab
GN		 7170 return 1;
7171 vcpu->mmio_read_completed = 1;
7172 return complete_emulated_io(vcpu);
7173 }
87da7e66 7174
716d51ab
GN		 7175 run->exit_reason = KVM_EXIT_MMIO;
7176 run->mmio.phys_addr = frag->gpa;
7177 if (vcpu->mmio_is_write)
87da7e66
XG		 7178 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7179 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7180 run->mmio.is_write = vcpu->mmio_is_write;
7181 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7182 return 0;
5287f194
AK		 7183}
7184
716d51ab 7185
b6c7a5dc
HB		 7186int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7187{
c5bedc68 7188 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7189 int r;
7190 sigset_t sigsaved;
7191
c4d72e2d 7192 fpu__activate_curr(fpu);
e5c30142 7193
ac9f6dc0
AK		 7194 if (vcpu->sigset_active)
7195 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7196
a4535290 7197 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7198 kvm_vcpu_block(vcpu);
66450a21 7199 kvm_apic_accept_events(vcpu);
72875d8a 7200 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0
AK		 7201 r = -EAGAIN;
7202 goto out;
b6c7a5dc
HB		 7203 }
7204
b6c7a5dc 7205 /* re-sync apic's tpr */
35754c98 7206 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7207 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7208 r = -EINVAL;
7209 goto out;
7210 }
7211 }
b6c7a5dc 7212
716d51ab
GN		 7213 if (unlikely(vcpu->arch.complete_userspace_io)) {
7214 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7215 vcpu->arch.complete_userspace_io = NULL;
7216 r = cui(vcpu);
7217 if (r <= 0)
7218 goto out;
7219 } else
7220 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7221
460df4c1
PB		 7222 if (kvm_run->immediate_exit)
7223 r = -EINTR;
7224 else
7225 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7226
7227out:
f1d86e46 7228 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7229 if (vcpu->sigset_active)
7230 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7231
b6c7a5dc
HB		 7232 return r;
7233}
7234
7235int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7236{
7ae441ea
GN		 7237 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7238 /*
7239 * We are here if userspace calls get_regs() in the middle of
7240 * instruction emulation. Registers state needs to be copied
4a969980 7241 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7242 * that usually, but some bad designed PV devices (vmware
7243 * backdoor interface) need this to work
7244 */
dd856efa 7245 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7246 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7247 }
5fdbf976
MT		 7248 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7249 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7250 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7251 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7252 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7253 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7254 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7255 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7256#ifdef CONFIG_X86_64
5fdbf976
MT		 7257 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7258 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7259 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7260 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7261 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7262 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7263 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7264 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7265#endif
7266
5fdbf976 7267 regs->rip = kvm_rip_read(vcpu);
91586a3b 7268 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7269
b6c7a5dc
HB		 7270 return 0;
7271}
7272
7273int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7274{
7ae441ea
GN		 7275 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7276 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7277
5fdbf976
MT		 7278 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7279 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7280 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7281 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7282 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7283 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7284 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7285 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7286#ifdef CONFIG_X86_64
5fdbf976
MT		 7287 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7288 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7289 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7290 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7291 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7292 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7293 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7294 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7295#endif
7296
5fdbf976 7297 kvm_rip_write(vcpu, regs->rip);
91586a3b 7298 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7299
b4f14abd
JK		 7300 vcpu->arch.exception.pending = false;
7301
3842d135
AK		 7302 kvm_make_request(KVM_REQ_EVENT, vcpu);
7303
b6c7a5dc
HB		 7304 return 0;
7305}
7306
b6c7a5dc
HB		 7307void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7308{
7309 struct kvm_segment cs;
7310
3e6e0aab 7311 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7312 *db = cs.db;
7313 *l = cs.l;
7314}
7315EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7316
7317int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7318 struct kvm_sregs *sregs)
7319{
89a27f4d 7320 struct desc_ptr dt;
b6c7a5dc 7321
3e6e0aab
GT		 7322 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7323 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7324 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7325 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7326 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7327 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7328
3e6e0aab
GT		 7329 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7330 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7331
7332 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7333 sregs->idt.limit = dt.size;
7334 sregs->idt.base = dt.address;
b6c7a5dc 7335 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7336 sregs->gdt.limit = dt.size;
7337 sregs->gdt.base = dt.address;
b6c7a5dc 7338
4d4ec087 7339 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7340 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7341 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7342 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7343 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7344 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7345 sregs->apic_base = kvm_get_apic_base(vcpu);
7346
923c61bb 7347 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7348
36752c9b 7349 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7350 set_bit(vcpu->arch.interrupt.nr,
7351 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7352
b6c7a5dc
HB		 7353 return 0;
7354}
7355
62d9f0db
MT		 7356int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7357 struct kvm_mp_state *mp_state)
7358{
66450a21 7359 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7360 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7361 vcpu->arch.pv.pv_unhalted)
7362 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7363 else
7364 mp_state->mp_state = vcpu->arch.mp_state;
7365
62d9f0db
MT		 7366 return 0;
7367}
7368
7369int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7370 struct kvm_mp_state *mp_state)
7371{
bce87cce 7372 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7373 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7374 return -EINVAL;
7375
28bf2888
DH		 7376 /* INITs are latched while in SMM */
7377 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7378 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7379 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7380 return -EINVAL;
7381
66450a21
JK		 7382 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7383 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7384 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7385 } else
7386 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7387 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7388 return 0;
7389}
7390
7f3d35fd
KW		 7391int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7392 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7393{
9d74191a 7394 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7395 int ret;
e01c2426 7396
8ec4722d 7397 init_emulate_ctxt(vcpu);
c697518a 7398
7f3d35fd 7399 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7400 has_error_code, error_code);
c697518a 7401
c697518a 7402 if (ret)
19d04437 7403 return EMULATE_FAIL;
37817f29 7404
9d74191a
TY		 7405 kvm_rip_write(vcpu, ctxt->eip);
7406 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7407 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7408 return EMULATE_DONE;
37817f29
IE		 7409}
7410EXPORT_SYMBOL_GPL(kvm_task_switch);
7411
b6c7a5dc
HB		 7412int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7413 struct kvm_sregs *sregs)
7414{
58cb628d 7415 struct msr_data apic_base_msr;
b6c7a5dc 7416 int mmu_reset_needed = 0;
63f42e02 7417 int pending_vec, max_bits, idx;
89a27f4d 7418 struct desc_ptr dt;
b6c7a5dc 7419
d6321d49
RK		 7420 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7421 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7422 return -EINVAL;
7423
d3802286
JM		 7424 apic_base_msr.data = sregs->apic_base;
7425 apic_base_msr.host_initiated = true;
7426 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7427 return -EINVAL;
7428
89a27f4d
GN		 7429 dt.size = sregs->idt.limit;
7430 dt.address = sregs->idt.base;
b6c7a5dc 7431 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7432 dt.size = sregs->gdt.limit;
7433 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7434 kvm_x86_ops->set_gdt(vcpu, &dt);
7435
ad312c7c 7436 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7437 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7438 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7439 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7440
2d3ad1f4 7441 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7442
f6801dff 7443 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7444 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7445
4d4ec087 7446 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7447 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7448 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7449
fc78f519 7450 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7451 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7452 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7453 kvm_update_cpuid(vcpu);
63f42e02
XG		 7454
7455 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7456 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7457 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7458 mmu_reset_needed = 1;
7459 }
63f42e02 7460 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7461
7462 if (mmu_reset_needed)
7463 kvm_mmu_reset_context(vcpu);
7464
a50abc3b 7465 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7466 pending_vec = find_first_bit(
7467 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7468 if (pending_vec < max_bits) {
66fd3f7f 7469 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7470 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7471 }
7472
3e6e0aab
GT		 7473 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7474 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7475 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7476 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7477 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7478 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7479
3e6e0aab
GT		 7480 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7481 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7482
5f0269f5
ME		 7483 update_cr8_intercept(vcpu);
7484
9c3e4aab 7485 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7486 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7487 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7488 !is_protmode(vcpu))
9c3e4aab
MT		 7489 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7490
3842d135
AK		 7491 kvm_make_request(KVM_REQ_EVENT, vcpu);
7492
b6c7a5dc
HB		 7493 return 0;
7494}
7495
d0bfb940
JK		 7496int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7497 struct kvm_guest_debug *dbg)
b6c7a5dc 7498{
355be0b9 7499 unsigned long rflags;
ae675ef0 7500 int i, r;
b6c7a5dc 7501
4f926bf2
JK		 7502 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7503 r = -EBUSY;
7504 if (vcpu->arch.exception.pending)
2122ff5e 7505 goto out;
4f926bf2
JK		 7506 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7507 kvm_queue_exception(vcpu, DB_VECTOR);
7508 else
7509 kvm_queue_exception(vcpu, BP_VECTOR);
7510 }
7511
91586a3b
JK		 7512 /*
7513 * Read rflags as long as potentially injected trace flags are still
7514 * filtered out.
7515 */
7516 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7517
7518 vcpu->guest_debug = dbg->control;
7519 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7520 vcpu->guest_debug = 0;
7521
7522 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7523 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7524 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7525 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7526 } else {
7527 for (i = 0; i < KVM_NR_DB_REGS; i++)
7528 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7529 }
c8639010 7530 kvm_update_dr7(vcpu);
ae675ef0 7531
f92653ee
JK		 7532 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7533 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7534 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7535
91586a3b
JK		 7536 /*
7537 * Trigger an rflags update that will inject or remove the trace
7538 * flags.
7539 */
7540 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7541
a96036b8 7542 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7543
4f926bf2 7544 r = 0;
d0bfb940 7545
2122ff5e 7546out:
b6c7a5dc
HB		 7547
7548 return r;
7549}
7550
8b006791
ZX		 7551/*
7552 * Translate a guest virtual address to a guest physical address.
7553 */
7554int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7555 struct kvm_translation *tr)
7556{
7557 unsigned long vaddr = tr->linear_address;
7558 gpa_t gpa;
f656ce01 7559 int idx;
8b006791 7560
f656ce01 7561 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7562 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7563 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7564 tr->physical_address = gpa;
7565 tr->valid = gpa != UNMAPPED_GVA;
7566 tr->writeable = 1;
7567 tr->usermode = 0;
8b006791
ZX		 7568
7569 return 0;
7570}
7571
d0752060
HB		 7572int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7573{
c47ada30 7574 struct fxregs_state *fxsave =
7366ed77 7575 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7576
d0752060
HB		 7577 memcpy(fpu->fpr, fxsave->st_space, 128);
7578 fpu->fcw = fxsave->cwd;
7579 fpu->fsw = fxsave->swd;
7580 fpu->ftwx = fxsave->twd;
7581 fpu->last_opcode = fxsave->fop;
7582 fpu->last_ip = fxsave->rip;
7583 fpu->last_dp = fxsave->rdp;
7584 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7585
d0752060
HB		 7586 return 0;
7587}
7588
7589int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7590{
c47ada30 7591 struct fxregs_state *fxsave =
7366ed77 7592 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7593
d0752060
HB		 7594 memcpy(fxsave->st_space, fpu->fpr, 128);
7595 fxsave->cwd = fpu->fcw;
7596 fxsave->swd = fpu->fsw;
7597 fxsave->twd = fpu->ftwx;
7598 fxsave->fop = fpu->last_opcode;
7599 fxsave->rip = fpu->last_ip;
7600 fxsave->rdp = fpu->last_dp;
7601 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7602
d0752060
HB		 7603 return 0;
7604}
7605
0ee6a517 7606static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7607{
bf935b0b 7608 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7609 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7610 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7611 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7612
2acf923e
DC		 7613 /*
7614 * Ensure guest xcr0 is valid for loading
7615 */
d91cab78 7616 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7617
ad312c7c 7618 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7619}
d0752060
HB		 7620
7621void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7622{
2608d7a1 7623 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7624 return;
7625
2acf923e
DC		 7626 /*
7627 * Restore all possible states in the guest,
7628 * and assume host would use all available bits.
7629 * Guest xcr0 would be loaded later.
7630 */
d0752060 7631 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7632 __kernel_fpu_begin();
003e2e8b 7633 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7634 trace_kvm_fpu(1);
d0752060 7635}
d0752060
HB		 7636
7637void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7638{
3d42de25 7639 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7640 return;
7641
7642 vcpu->guest_fpu_loaded = 0;
4f836347 7643 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7644 __kernel_fpu_end();
f096ed85 7645 ++vcpu->stat.fpu_reload;
0c04851c 7646 trace_kvm_fpu(0);
d0752060 7647}
e9b11c17
ZX		 7648
7649void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7650{
bd768e14
IY		 7651 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7652
12f9a48f 7653 kvmclock_reset(vcpu);
7f1ea208 7654
e9b11c17 7655 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7656 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7657}
7658
7659struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7660 unsigned int id)
7661{
c447e76b
LL		 7662 struct kvm_vcpu *vcpu;
7663
6755bae8
ZA		 7664 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7665 printk_once(KERN_WARNING
7666 "kvm: SMP vm created on host with unstable TSC; "
7667 "guest TSC will not be reliable\n");
c447e76b
LL		 7668
7669 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7670
c447e76b 7671 return vcpu;
26e5215f 7672}
e9b11c17 7673
26e5215f
AK		 7674int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7675{
7676 int r;
e9b11c17 7677
19efffa2 7678 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7679 r = vcpu_load(vcpu);
7680 if (r)
7681 return r;
d28bc9dd 7682 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7683 kvm_mmu_setup(vcpu);
e9b11c17 7684 vcpu_put(vcpu);
26e5215f 7685 return r;
e9b11c17
ZX		 7686}
7687
31928aa5 7688void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7689{
8fe8ab46 7690 struct msr_data msr;
332967a3 7691 struct kvm *kvm = vcpu->kvm;
42897d86 7692
d3457c87
RK		 7693 kvm_hv_vcpu_postcreate(vcpu);
7694
31928aa5
DD		 7695 if (vcpu_load(vcpu))
7696 return;
8fe8ab46
WA		 7697 msr.data = 0x0;
7698 msr.index = MSR_IA32_TSC;
7699 msr.host_initiated = true;
7700 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7701 vcpu_put(vcpu);
7702
630994b3
MT		 7703 if (!kvmclock_periodic_sync)
7704 return;
7705
332967a3
AJ		 7706 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7707 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7708}
7709
d40ccc62 7710void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7711{
9fc77441 7712 int r;
344d9588
GN		 7713 vcpu->arch.apf.msr_val = 0;
7714
9fc77441
MT		 7715 r = vcpu_load(vcpu);
7716 BUG_ON(r);
e9b11c17
ZX		 7717 kvm_mmu_unload(vcpu);
7718 vcpu_put(vcpu);
7719
7720 kvm_x86_ops->vcpu_free(vcpu);
7721}
7722
d28bc9dd 7723void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7724{
e69fab5d
PB		 7725 vcpu->arch.hflags = 0;
7726
c43203ca 7727 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7728 atomic_set(&vcpu->arch.nmi_queued, 0);
7729 vcpu->arch.nmi_pending = 0;
448fa4a9 7730 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7731 kvm_clear_interrupt_queue(vcpu);
7732 kvm_clear_exception_queue(vcpu);
448fa4a9 7733
42dbaa5a 7734 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7735 kvm_update_dr0123(vcpu);
6f43ed01 7736 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7737 kvm_update_dr6(vcpu);
42dbaa5a 7738 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7739 kvm_update_dr7(vcpu);
42dbaa5a 7740
1119022c
NA		 7741 vcpu->arch.cr2 = 0;
7742
3842d135 7743 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7744 vcpu->arch.apf.msr_val = 0;
c9aaa895 7745 vcpu->arch.st.msr_val = 0;
3842d135 7746
12f9a48f
GC		 7747 kvmclock_reset(vcpu);
7748
af585b92
GN		 7749 kvm_clear_async_pf_completion_queue(vcpu);
7750 kvm_async_pf_hash_reset(vcpu);
7751 vcpu->arch.apf.halted = false;
3842d135 7752
64d60670 7753 if (!init_event) {
d28bc9dd 7754 kvm_pmu_reset(vcpu);
64d60670 7755 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7756
7757 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7758 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7759 }
f5132b01 7760
66f7b72e
JS		 7761 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7762 vcpu->arch.regs_avail = ~0;
7763 vcpu->arch.regs_dirty = ~0;
7764
d28bc9dd 7765 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7766}
7767
2b4a273b 7768void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7769{
7770 struct kvm_segment cs;
7771
7772 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7773 cs.selector = vector << 8;
7774 cs.base = vector << 12;
7775 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7776 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7777}
7778
13a34e06 7779int kvm_arch_hardware_enable(void)
e9b11c17 7780{
ca84d1a2
ZA		 7781 struct kvm *kvm;
7782 struct kvm_vcpu *vcpu;
7783 int i;
0dd6a6ed
ZA		 7784 int ret;
7785 u64 local_tsc;
7786 u64 max_tsc = 0;
7787 bool stable, backwards_tsc = false;
18863bdd
AK		 7788
7789 kvm_shared_msr_cpu_online();
13a34e06 7790 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7791 if (ret != 0)
7792 return ret;
7793
4ea1636b 7794 local_tsc = rdtsc();
0dd6a6ed
ZA		 7795 stable = !check_tsc_unstable();
7796 list_for_each_entry(kvm, &vm_list, vm_list) {
7797 kvm_for_each_vcpu(i, vcpu, kvm) {
7798 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7799 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7800 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7801 backwards_tsc = true;
7802 if (vcpu->arch.last_host_tsc > max_tsc)
7803 max_tsc = vcpu->arch.last_host_tsc;
7804 }
7805 }
7806 }
7807
7808 /*
7809 * Sometimes, even reliable TSCs go backwards. This happens on
7810 * platforms that reset TSC during suspend or hibernate actions, but
7811 * maintain synchronization. We must compensate. Fortunately, we can
7812 * detect that condition here, which happens early in CPU bringup,
7813 * before any KVM threads can be running. Unfortunately, we can't
7814 * bring the TSCs fully up to date with real time, as we aren't yet far
7815 * enough into CPU bringup that we know how much real time has actually
108b249c 7816 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7817 * variables that haven't been updated yet.
7818 *
7819 * So we simply find the maximum observed TSC above, then record the
7820 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7821 * the adjustment will be applied. Note that we accumulate
7822 * adjustments, in case multiple suspend cycles happen before some VCPU
7823 * gets a chance to run again. In the event that no KVM threads get a
7824 * chance to run, we will miss the entire elapsed period, as we'll have
7825 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7826 * loose cycle time. This isn't too big a deal, since the loss will be
7827 * uniform across all VCPUs (not to mention the scenario is extremely
7828 * unlikely). It is possible that a second hibernate recovery happens
7829 * much faster than a first, causing the observed TSC here to be
7830 * smaller; this would require additional padding adjustment, which is
7831 * why we set last_host_tsc to the local tsc observed here.
7832 *
7833 * N.B. - this code below runs only on platforms with reliable TSC,
7834 * as that is the only way backwards_tsc is set above. Also note
7835 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7836 * have the same delta_cyc adjustment applied if backwards_tsc
7837 * is detected. Note further, this adjustment is only done once,
7838 * as we reset last_host_tsc on all VCPUs to stop this from being
7839 * called multiple times (one for each physical CPU bringup).
7840 *
4a969980 7841 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7842 * will be compensated by the logic in vcpu_load, which sets the TSC to
7843 * catchup mode. This will catchup all VCPUs to real time, but cannot
7844 * guarantee that they stay in perfect synchronization.
7845 */
7846 if (backwards_tsc) {
7847 u64 delta_cyc = max_tsc - local_tsc;
7848 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7849 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7850 kvm_for_each_vcpu(i, vcpu, kvm) {
7851 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7852 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7853 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7854 }
7855
7856 /*
7857 * We have to disable TSC offset matching.. if you were
7858 * booting a VM while issuing an S4 host suspend....
7859 * you may have some problem. Solving this issue is
7860 * left as an exercise to the reader.
7861 */
7862 kvm->arch.last_tsc_nsec = 0;
7863 kvm->arch.last_tsc_write = 0;
7864 }
7865
7866 }
7867 return 0;
e9b11c17
ZX		 7868}
7869
13a34e06 7870void kvm_arch_hardware_disable(void)
e9b11c17 7871{
13a34e06
RK		 7872 kvm_x86_ops->hardware_disable();
7873 drop_user_return_notifiers();
e9b11c17
ZX		 7874}
7875
7876int kvm_arch_hardware_setup(void)
7877{
9e9c3fe4
NA		 7878 int r;
7879
7880 r = kvm_x86_ops->hardware_setup();
7881 if (r != 0)
7882 return r;
7883
35181e86
HZ		 7884 if (kvm_has_tsc_control) {
7885 /*
7886 * Make sure the user can only configure tsc_khz values that
7887 * fit into a signed integer.
7888 * A min value is not calculated needed because it will always
7889 * be 1 on all machines.
7890 */
7891 u64 max = min(0x7fffffffULL,
7892 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7893 kvm_max_guest_tsc_khz = max;
7894
ad721883 7895 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7896 }
ad721883 7897
9e9c3fe4
NA		 7898 kvm_init_msr_list();
7899 return 0;
e9b11c17
ZX		 7900}
7901
7902void kvm_arch_hardware_unsetup(void)
7903{
7904 kvm_x86_ops->hardware_unsetup();
7905}
7906
7907void kvm_arch_check_processor_compat(void *rtn)
7908{
7909 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7910}
7911
7912bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7913{
7914 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7915}
7916EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7917
7918bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7919{
7920 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7921}
7922
54e9818f 7923struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7924EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7925
e9b11c17
ZX		 7926int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7927{
7928 struct page *page;
7929 struct kvm *kvm;
7930 int r;
7931
7932 BUG_ON(vcpu->kvm == NULL);
7933 kvm = vcpu->kvm;
7934
d62caabb 7935 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7936 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7937 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7938 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7939 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7940 else
a4535290 7941 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7942
7943 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7944 if (!page) {
7945 r = -ENOMEM;
7946 goto fail;
7947 }
ad312c7c 7948 vcpu->arch.pio_data = page_address(page);
e9b11c17 7949
cc578287 7950 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7951
e9b11c17
ZX		 7952 r = kvm_mmu_create(vcpu);
7953 if (r < 0)
7954 goto fail_free_pio_data;
7955
7956 if (irqchip_in_kernel(kvm)) {
7957 r = kvm_create_lapic(vcpu);
7958 if (r < 0)
7959 goto fail_mmu_destroy;
54e9818f
GN		 7960 } else
7961 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7962
890ca9ae
HY		 7963 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7964 GFP_KERNEL);
7965 if (!vcpu->arch.mce_banks) {
7966 r = -ENOMEM;
443c39bc 7967 goto fail_free_lapic;
890ca9ae
HY		 7968 }
7969 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7970
f1797359
WY		 7971 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7972 r = -ENOMEM;
f5f48ee1 7973 goto fail_free_mce_banks;
f1797359 7974 }
f5f48ee1 7975
0ee6a517 7976 fx_init(vcpu);
66f7b72e 7977
ba904635 7978 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7979 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7980
7981 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7982 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7983
5a4f55cd
EK		 7984 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7985
74545705
RK		 7986 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7987
af585b92 7988 kvm_async_pf_hash_reset(vcpu);
f5132b01 7989 kvm_pmu_init(vcpu);
af585b92 7990
1c1a9ce9 7991 vcpu->arch.pending_external_vector = -1;
de63ad4c 7992 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 7993
5c919412
AS		 7994 kvm_hv_vcpu_init(vcpu);
7995
e9b11c17 7996 return 0;
0ee6a517 7997
f5f48ee1
SY		 7998fail_free_mce_banks:
7999 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8000fail_free_lapic:
8001 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8002fail_mmu_destroy:
8003 kvm_mmu_destroy(vcpu);
8004fail_free_pio_data:
ad312c7c 8005 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8006fail:
8007 return r;
8008}
8009
8010void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8011{
f656ce01
MT		 8012 int idx;
8013
1f4b34f8 8014 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8015 kvm_pmu_destroy(vcpu);
36cb93fd 8016 kfree(vcpu->arch.mce_banks);
e9b11c17 8017 kvm_free_lapic(vcpu);
f656ce01 8018 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8019 kvm_mmu_destroy(vcpu);
f656ce01 8020 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8021 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8022 if (!lapic_in_kernel(vcpu))
54e9818f 8023 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8024}
d19a9cd2 8025
e790d9ef
RK		 8026void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8027{
ae97a3b8 8028 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8029}
8030
e08b9637 8031int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8032{
e08b9637
CO		 8033 if (type)
8034 return -EINVAL;
8035
6ef768fa 8036 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8037 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8038 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8039 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8040 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8041
5550af4d
SY		 8042 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8043 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8044 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8045 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8046 &kvm->arch.irq_sources_bitmap);
5550af4d 8047
038f8c11 8048 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8049 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8050 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8051 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8052
108b249c 8053 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8054 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8055
7e44e449 8056 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8057 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8058
0eb05bf2 8059 kvm_page_track_init(kvm);
13d268ca 8060 kvm_mmu_init_vm(kvm);
0eb05bf2 8061
03543133
SS		 8062 if (kvm_x86_ops->vm_init)
8063 return kvm_x86_ops->vm_init(kvm);
8064
d89f5eff 8065 return 0;
d19a9cd2
ZX		 8066}
8067
8068static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8069{
9fc77441
MT		 8070 int r;
8071 r = vcpu_load(vcpu);
8072 BUG_ON(r);
d19a9cd2
ZX		 8073 kvm_mmu_unload(vcpu);
8074 vcpu_put(vcpu);
8075}
8076
8077static void kvm_free_vcpus(struct kvm *kvm)
8078{
8079 unsigned int i;
988a2cae 8080 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8081
8082 /*
8083 * Unpin any mmu pages first.
8084 */
af585b92
GN		 8085 kvm_for_each_vcpu(i, vcpu, kvm) {
8086 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8087 kvm_unload_vcpu_mmu(vcpu);
af585b92 8088 }
988a2cae
GN		 8089 kvm_for_each_vcpu(i, vcpu, kvm)
8090 kvm_arch_vcpu_free(vcpu);
8091
8092 mutex_lock(&kvm->lock);
8093 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8094 kvm->vcpus[i] = NULL;
d19a9cd2 8095
988a2cae
GN		 8096 atomic_set(&kvm->online_vcpus, 0);
8097 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8098}
8099
ad8ba2cd
SY		 8100void kvm_arch_sync_events(struct kvm *kvm)
8101{
332967a3 8102 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8103 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8104 kvm_free_pit(kvm);
ad8ba2cd
SY		 8105}
8106
1d8007bd 8107int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8108{
8109 int i, r;
25188b99 8110 unsigned long hva;
f0d648bd
PB		 8111 struct kvm_memslots *slots = kvm_memslots(kvm);
8112 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8113
8114 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8115 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8116 return -EINVAL;
9da0e4d5 8117
f0d648bd
PB		 8118 slot = id_to_memslot(slots, id);
8119 if (size) {
b21629da 8120 if (slot->npages)
f0d648bd
PB		 8121 return -EEXIST;
8122
8123 /*
8124 * MAP_SHARED to prevent internal slot pages from being moved
8125 * by fork()/COW.
8126 */
8127 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8128 MAP_SHARED | MAP_ANONYMOUS, 0);
8129 if (IS_ERR((void *)hva))
8130 return PTR_ERR((void *)hva);
8131 } else {
8132 if (!slot->npages)
8133 return 0;
8134
8135 hva = 0;
8136 }
8137
8138 old = *slot;
9da0e4d5 8139 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8140 struct kvm_userspace_memory_region m;
9da0e4d5 8141
1d8007bd
PB		 8142 m.slot = id | (i << 16);
8143 m.flags = 0;
8144 m.guest_phys_addr = gpa;
f0d648bd 8145 m.userspace_addr = hva;
1d8007bd 8146 m.memory_size = size;
9da0e4d5
PB		 8147 r = __kvm_set_memory_region(kvm, &m);
8148 if (r < 0)
8149 return r;
8150 }
8151
f0d648bd
PB		 8152 if (!size) {
8153 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8154 WARN_ON(r < 0);
8155 }
8156
9da0e4d5
PB		 8157 return 0;
8158}
8159EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8160
1d8007bd 8161int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8162{
8163 int r;
8164
8165 mutex_lock(&kvm->slots_lock);
1d8007bd 8166 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8167 mutex_unlock(&kvm->slots_lock);
8168
8169 return r;
8170}
8171EXPORT_SYMBOL_GPL(x86_set_memory_region);
8172
d19a9cd2
ZX		 8173void kvm_arch_destroy_vm(struct kvm *kvm)
8174{
27469d29
AH		 8175 if (current->mm == kvm->mm) {
8176 /*
8177 * Free memory regions allocated on behalf of userspace,
8178 * unless the the memory map has changed due to process exit
8179 * or fd copying.
8180 */
1d8007bd
PB		 8181 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8182 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8183 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8184 }
03543133
SS		 8185 if (kvm_x86_ops->vm_destroy)
8186 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8187 kvm_pic_destroy(kvm);
8188 kvm_ioapic_destroy(kvm);
d19a9cd2 8189 kvm_free_vcpus(kvm);
af1bae54 8190 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8191 kvm_mmu_uninit_vm(kvm);
2beb6dad 8192 kvm_page_track_cleanup(kvm);
d19a9cd2 8193}
0de10343 8194
5587027c 8195void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8196 struct kvm_memory_slot *dont)
8197{
8198 int i;
8199
d89cc617
TY		 8200 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8201 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8202 kvfree(free->arch.rmap[i]);
d89cc617 8203 free->arch.rmap[i] = NULL;
77d11309 8204 }
d89cc617
TY		 8205 if (i == 0)
8206 continue;
8207
8208 if (!dont || free->arch.lpage_info[i - 1] !=
8209 dont->arch.lpage_info[i - 1]) {
548ef284 8210 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8211 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8212 }
8213 }
21ebbeda
XG		 8214
8215 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8216}
8217
5587027c
AK		 8218int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8219 unsigned long npages)
db3fe4eb
TY		 8220{
8221 int i;
8222
d89cc617 8223 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8224 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8225 unsigned long ugfn;
8226 int lpages;
d89cc617 8227 int level = i + 1;
db3fe4eb
TY		 8228
8229 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8230 slot->base_gfn, level) + 1;
8231
d89cc617 8232 slot->arch.rmap[i] =
a7c3e901 8233 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8234 if (!slot->arch.rmap[i])
77d11309 8235 goto out_free;
d89cc617
TY		 8236 if (i == 0)
8237 continue;
77d11309 8238
a7c3e901 8239 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8240 if (!linfo)
db3fe4eb
TY		 8241 goto out_free;
8242
92f94f1e
XG		 8243 slot->arch.lpage_info[i - 1] = linfo;
8244
db3fe4eb 8245 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8246 linfo[0].disallow_lpage = 1;
db3fe4eb 8247 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8248 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8249 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8250 /*
8251 * If the gfn and userspace address are not aligned wrt each
8252 * other, or if explicitly asked to, disable large page
8253 * support for this slot
8254 */
8255 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8256 !kvm_largepages_enabled()) {
8257 unsigned long j;
8258
8259 for (j = 0; j < lpages; ++j)
92f94f1e 8260 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8261 }
8262 }
8263
21ebbeda
XG		 8264 if (kvm_page_track_create_memslot(slot, npages))
8265 goto out_free;
8266
db3fe4eb
TY		 8267 return 0;
8268
8269out_free:
d89cc617 8270 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8271 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8272 slot->arch.rmap[i] = NULL;
8273 if (i == 0)
8274 continue;
8275
548ef284 8276 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8277 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8278 }
8279 return -ENOMEM;
8280}
8281
15f46015 8282void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8283{
e6dff7d1
TY		 8284 /*
8285 * memslots->generation has been incremented.
8286 * mmio generation may have reached its maximum value.
8287 */
54bf36aa 8288 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8289}
8290
f7784b8e
MT		 8291int kvm_arch_prepare_memory_region(struct kvm *kvm,
8292 struct kvm_memory_slot *memslot,
09170a49 8293 const struct kvm_userspace_memory_region *mem,
7b6195a9 8294 enum kvm_mr_change change)
0de10343 8295{
f7784b8e
MT		 8296 return 0;
8297}
8298
88178fd4
KH		 8299static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8300 struct kvm_memory_slot *new)
8301{
8302 /* Still write protect RO slot */
8303 if (new->flags & KVM_MEM_READONLY) {
8304 kvm_mmu_slot_remove_write_access(kvm, new);
8305 return;
8306 }
8307
8308 /*
8309 * Call kvm_x86_ops dirty logging hooks when they are valid.
8310 *
8311 * kvm_x86_ops->slot_disable_log_dirty is called when:
8312 *
8313 * - KVM_MR_CREATE with dirty logging is disabled
8314 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8315 *
8316 * The reason is, in case of PML, we need to set D-bit for any slots
8317 * with dirty logging disabled in order to eliminate unnecessary GPA
8318 * logging in PML buffer (and potential PML buffer full VMEXT). This
8319 * guarantees leaving PML enabled during guest's lifetime won't have
8320 * any additonal overhead from PML when guest is running with dirty
8321 * logging disabled for memory slots.
8322 *
8323 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8324 * to dirty logging mode.
8325 *
8326 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8327 *
8328 * In case of write protect:
8329 *
8330 * Write protect all pages for dirty logging.
8331 *
8332 * All the sptes including the large sptes which point to this
8333 * slot are set to readonly. We can not create any new large
8334 * spte on this slot until the end of the logging.
8335 *
8336 * See the comments in fast_page_fault().
8337 */
8338 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8339 if (kvm_x86_ops->slot_enable_log_dirty)
8340 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8341 else
8342 kvm_mmu_slot_remove_write_access(kvm, new);
8343 } else {
8344 if (kvm_x86_ops->slot_disable_log_dirty)
8345 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8346 }
8347}
8348
f7784b8e 8349void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8350 const struct kvm_userspace_memory_region *mem,
8482644a 8351 const struct kvm_memory_slot *old,
f36f3f28 8352 const struct kvm_memory_slot *new,
8482644a 8353 enum kvm_mr_change change)
f7784b8e 8354{
8482644a 8355 int nr_mmu_pages = 0;
f7784b8e 8356
48c0e4e9
XG		 8357 if (!kvm->arch.n_requested_mmu_pages)
8358 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8359
48c0e4e9 8360 if (nr_mmu_pages)
0de10343 8361 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8362
3ea3b7fa
WL		 8363 /*
8364 * Dirty logging tracks sptes in 4k granularity, meaning that large
8365 * sptes have to be split. If live migration is successful, the guest
8366 * in the source machine will be destroyed and large sptes will be
8367 * created in the destination. However, if the guest continues to run
8368 * in the source machine (for example if live migration fails), small
8369 * sptes will remain around and cause bad performance.
8370 *
8371 * Scan sptes if dirty logging has been stopped, dropping those
8372 * which can be collapsed into a single large-page spte. Later
8373 * page faults will create the large-page sptes.
8374 */
8375 if ((change != KVM_MR_DELETE) &&
8376 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8377 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8378 kvm_mmu_zap_collapsible_sptes(kvm, new);
8379
c972f3b1 8380 /*
88178fd4 8381 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8382 *
88178fd4
KH		 8383 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8384 * been zapped so no dirty logging staff is needed for old slot. For
8385 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8386 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8387 *
8388 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8389 */
88178fd4 8390 if (change != KVM_MR_DELETE)
f36f3f28 8391 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8392}
1d737c8a 8393
2df72e9b 8394void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8395{
6ca18b69 8396 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8397}
8398
2df72e9b
MT		 8399void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8400 struct kvm_memory_slot *slot)
8401{
ae7cd873 8402 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8403}
8404
5d9bc648
PB		 8405static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8406{
8407 if (!list_empty_careful(&vcpu->async_pf.done))
8408 return true;
8409
8410 if (kvm_apic_has_events(vcpu))
8411 return true;
8412
8413 if (vcpu->arch.pv.pv_unhalted)
8414 return true;
8415
47a66eed
Z		 8416 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8417 (vcpu->arch.nmi_pending &&
8418 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8419 return true;
8420
47a66eed
Z		 8421 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8422 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8423 return true;
8424
5d9bc648
PB		 8425 if (kvm_arch_interrupt_allowed(vcpu) &&
8426 kvm_cpu_has_interrupt(vcpu))
8427 return true;
8428
1f4b34f8
AS		 8429 if (kvm_hv_has_stimer_pending(vcpu))
8430 return true;
8431
5d9bc648
PB		 8432 return false;
8433}
8434
1d737c8a
ZX		 8435int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8436{
5d9bc648 8437 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8438}
5736199a 8439
199b5763
LM		 8440bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8441{
de63ad4c 8442 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8443}
8444
b6d33834 8445int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8446{
b6d33834 8447 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8448}
78646121
GN		 8449
8450int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8451{
8452 return kvm_x86_ops->interrupt_allowed(vcpu);
8453}
229456fc 8454
82b32774 8455unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8456{
82b32774
NA		 8457 if (is_64_bit_mode(vcpu))
8458 return kvm_rip_read(vcpu);
8459 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8460 kvm_rip_read(vcpu));
8461}
8462EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8463
82b32774
NA		 8464bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8465{
8466 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8467}
8468EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8469
94fe45da
JK		 8470unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8471{
8472 unsigned long rflags;
8473
8474 rflags = kvm_x86_ops->get_rflags(vcpu);
8475 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8476 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8477 return rflags;
8478}
8479EXPORT_SYMBOL_GPL(kvm_get_rflags);
8480
6addfc42 8481static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8482{
8483 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8484 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8485 rflags |= X86_EFLAGS_TF;
94fe45da 8486 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8487}
8488
8489void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8490{
8491 __kvm_set_rflags(vcpu, rflags);
3842d135 8492 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8493}
8494EXPORT_SYMBOL_GPL(kvm_set_rflags);
8495
56028d08
GN		 8496void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8497{
8498 int r;
8499
fb67e14f 8500 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8501 work->wakeup_all)
56028d08
GN		 8502 return;
8503
8504 r = kvm_mmu_reload(vcpu);
8505 if (unlikely(r))
8506 return;
8507
fb67e14f
XG		 8508 if (!vcpu->arch.mmu.direct_map &&
8509 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8510 return;
8511
56028d08
GN		 8512 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8513}
8514
af585b92
GN		 8515static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8516{
8517 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8518}
8519
8520static inline u32 kvm_async_pf_next_probe(u32 key)
8521{
8522 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8523}
8524
8525static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8526{
8527 u32 key = kvm_async_pf_hash_fn(gfn);
8528
8529 while (vcpu->arch.apf.gfns[key] != ~0)
8530 key = kvm_async_pf_next_probe(key);
8531
8532 vcpu->arch.apf.gfns[key] = gfn;
8533}
8534
8535static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8536{
8537 int i;
8538 u32 key = kvm_async_pf_hash_fn(gfn);
8539
8540 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8541 (vcpu->arch.apf.gfns[key] != gfn &&
8542 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8543 key = kvm_async_pf_next_probe(key);
8544
8545 return key;
8546}
8547
8548bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8549{
8550 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8551}
8552
8553static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8554{
8555 u32 i, j, k;
8556
8557 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8558 while (true) {
8559 vcpu->arch.apf.gfns[i] = ~0;
8560 do {
8561 j = kvm_async_pf_next_probe(j);
8562 if (vcpu->arch.apf.gfns[j] == ~0)
8563 return;
8564 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8565 /*
8566 * k lies cyclically in ]i,j]
8567 * | i.k.j |
8568 * |....j i.k.| or |.k..j i...|
8569 */
8570 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8571 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8572 i = j;
8573 }
8574}
8575
7c90705b
GN		 8576static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8577{
4e335d9e
PB		 8578
8579 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8580 sizeof(val));
7c90705b
GN		 8581}
8582
af585b92
GN		 8583void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8584 struct kvm_async_pf *work)
8585{
6389ee94
AK		 8586 struct x86_exception fault;
8587
7c90705b 8588 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8589 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8590
8591 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8592 (vcpu->arch.apf.send_user_only &&
8593 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8594 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8595 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8596 fault.vector = PF_VECTOR;
8597 fault.error_code_valid = true;
8598 fault.error_code = 0;
8599 fault.nested_page_fault = false;
8600 fault.address = work->arch.token;
adfe20fb 8601 fault.async_page_fault = true;
6389ee94 8602 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8603 }
af585b92
GN		 8604}
8605
8606void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8607 struct kvm_async_pf *work)
8608{
6389ee94
AK		 8609 struct x86_exception fault;
8610
f2e10669 8611 if (work->wakeup_all)
7c90705b
GN		 8612 work->arch.token = ~0; /* broadcast wakeup */
8613 else
8614 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8615 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8616
8617 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8618 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8619 fault.vector = PF_VECTOR;
8620 fault.error_code_valid = true;
8621 fault.error_code = 0;
8622 fault.nested_page_fault = false;
8623 fault.address = work->arch.token;
adfe20fb 8624 fault.async_page_fault = true;
6389ee94 8625 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8626 }
e6d53e3b 8627 vcpu->arch.apf.halted = false;
a4fa1635 8628 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8629}
8630
8631bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8632{
8633 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8634 return true;
8635 else
9bc1f09f 8636 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8637}
8638
5544eb9b
PB		 8639void kvm_arch_start_assignment(struct kvm *kvm)
8640{
8641 atomic_inc(&kvm->arch.assigned_device_count);
8642}
8643EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8644
8645void kvm_arch_end_assignment(struct kvm *kvm)
8646{
8647 atomic_dec(&kvm->arch.assigned_device_count);
8648}
8649EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8650
8651bool kvm_arch_has_assigned_device(struct kvm *kvm)
8652{
8653 return atomic_read(&kvm->arch.assigned_device_count);
8654}
8655EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8656
e0f0bbc5
AW		 8657void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8658{
8659 atomic_inc(&kvm->arch.noncoherent_dma_count);
8660}
8661EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8662
8663void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8664{
8665 atomic_dec(&kvm->arch.noncoherent_dma_count);
8666}
8667EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8668
8669bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8670{
8671 return atomic_read(&kvm->arch.noncoherent_dma_count);
8672}
8673EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8674
14717e20
AW		 8675bool kvm_arch_has_irq_bypass(void)
8676{
8677 return kvm_x86_ops->update_pi_irte != NULL;
8678}
8679
87276880
FW		 8680int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8681 struct irq_bypass_producer *prod)
8682{
8683 struct kvm_kernel_irqfd *irqfd =
8684 container_of(cons, struct kvm_kernel_irqfd, consumer);
8685
14717e20 8686 irqfd->producer = prod;
87276880 8687
14717e20
AW		 8688 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8689 prod->irq, irqfd->gsi, 1);
87276880
FW		 8690}
8691
8692void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8693 struct irq_bypass_producer *prod)
8694{
8695 int ret;
8696 struct kvm_kernel_irqfd *irqfd =
8697 container_of(cons, struct kvm_kernel_irqfd, consumer);
8698
87276880
FW		 8699 WARN_ON(irqfd->producer != prod);
8700 irqfd->producer = NULL;
8701
8702 /*
8703 * When producer of consumer is unregistered, we change back to
8704 * remapped mode, so we can re-use the current implementation
bb3541f1 8705 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8706 * int this case doesn't want to receive the interrupts.
8707 */
8708 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8709 if (ret)
8710 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8711 " fails: %d\n", irqfd->consumer.token, ret);
8712}
8713
8714int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8715 uint32_t guest_irq, bool set)
8716{
8717 if (!kvm_x86_ops->update_pi_irte)
8718 return -EINVAL;
8719
8720 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8721}
8722
52004014
FW		 8723bool kvm_vector_hashing_enabled(void)
8724{
8725 return vector_hashing;
8726}
8727EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8728
229456fc 8729EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8730EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8731EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8732EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8733EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8734EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8735EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8737EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8738EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8739EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8740EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8741EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8742EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8743EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8744EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8745EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8746EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8747EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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