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Commit | Line | Data |
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54936004 | 1 | /* |
5b6dd868 | 2 | * Virtual page mapping |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
14a48c1d | 19 | |
7b31bbc2 | 20 | #include "qemu/osdep.h" |
a8d25326 | 21 | #include "qemu-common.h" |
da34e65c | 22 | #include "qapi/error.h" |
54936004 | 23 | |
f348b6d1 | 24 | #include "qemu/cutils.h" |
6180a181 | 25 | #include "cpu.h" |
63c91552 | 26 | #include "exec/exec-all.h" |
51180423 | 27 | #include "exec/target_page.h" |
b67d9a52 | 28 | #include "tcg.h" |
741da0d3 | 29 | #include "hw/qdev-core.h" |
c7e002c5 | 30 | #include "hw/qdev-properties.h" |
4485bd26 | 31 | #if !defined(CONFIG_USER_ONLY) |
47c8ca53 | 32 | #include "hw/boards.h" |
33c11879 | 33 | #include "hw/xen/xen.h" |
4485bd26 | 34 | #endif |
9c17d615 | 35 | #include "sysemu/kvm.h" |
2ff3de68 | 36 | #include "sysemu/sysemu.h" |
14a48c1d | 37 | #include "sysemu/tcg.h" |
1de7afc9 PB |
38 | #include "qemu/timer.h" |
39 | #include "qemu/config-file.h" | |
75a34036 | 40 | #include "qemu/error-report.h" |
b6b71cb5 | 41 | #include "qemu/qemu-print.h" |
53a5960a | 42 | #if defined(CONFIG_USER_ONLY) |
a9c94277 | 43 | #include "qemu.h" |
432d268c | 44 | #else /* !CONFIG_USER_ONLY */ |
741da0d3 | 45 | #include "exec/memory.h" |
df43d49c | 46 | #include "exec/ioport.h" |
741da0d3 | 47 | #include "sysemu/dma.h" |
b58c5c2d | 48 | #include "sysemu/hostmem.h" |
79ca7a1b | 49 | #include "sysemu/hw_accel.h" |
741da0d3 | 50 | #include "exec/address-spaces.h" |
9c17d615 | 51 | #include "sysemu/xen-mapcache.h" |
0ab8ed18 | 52 | #include "trace-root.h" |
d3a5038c | 53 | |
e2fa71f5 | 54 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE |
e2fa71f5 DDAG |
55 | #include <linux/falloc.h> |
56 | #endif | |
57 | ||
53a5960a | 58 | #endif |
0dc3f44a | 59 | #include "qemu/rcu_queue.h" |
4840f10e | 60 | #include "qemu/main-loop.h" |
5b6dd868 | 61 | #include "translate-all.h" |
7615936e | 62 | #include "sysemu/replay.h" |
0cac1b66 | 63 | |
022c62cb | 64 | #include "exec/memory-internal.h" |
220c3ebd | 65 | #include "exec/ram_addr.h" |
508127e2 | 66 | #include "exec/log.h" |
67d95c15 | 67 | |
9dfeca7c BR |
68 | #include "migration/vmstate.h" |
69 | ||
b35ba30f | 70 | #include "qemu/range.h" |
794e8f30 MT |
71 | #ifndef _WIN32 |
72 | #include "qemu/mmap-alloc.h" | |
73 | #endif | |
b35ba30f | 74 | |
be9b23c4 PX |
75 | #include "monitor/monitor.h" |
76 | ||
db7b5426 | 77 | //#define DEBUG_SUBPAGE |
1196be37 | 78 | |
e2eef170 | 79 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a MD |
80 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes |
81 | * are protected by the ramlist lock. | |
82 | */ | |
0d53d9fe | 83 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
84 | |
85 | static MemoryRegion *system_memory; | |
309cb471 | 86 | static MemoryRegion *system_io; |
62152b8a | 87 | |
f6790af6 AK |
88 | AddressSpace address_space_io; |
89 | AddressSpace address_space_memory; | |
2673a5da | 90 | |
0844e007 | 91 | MemoryRegion io_mem_rom, io_mem_notdirty; |
acc9d80b | 92 | static MemoryRegion io_mem_unassigned; |
e2eef170 | 93 | #endif |
9fa3e853 | 94 | |
20bccb82 PM |
95 | #ifdef TARGET_PAGE_BITS_VARY |
96 | int target_page_bits; | |
97 | bool target_page_bits_decided; | |
98 | #endif | |
99 | ||
f481ee2d PB |
100 | CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); |
101 | ||
6a00d601 FB |
102 | /* current CPU in the current thread. It is only valid inside |
103 | cpu_exec() */ | |
f240eb6f | 104 | __thread CPUState *current_cpu; |
2e70f6ef | 105 | /* 0 = Do not count executed instructions. |
bf20dc07 | 106 | 1 = Precise instruction counting. |
2e70f6ef | 107 | 2 = Adaptive rate instruction counting. */ |
5708fc66 | 108 | int use_icount; |
6a00d601 | 109 | |
a0be0c58 YZ |
110 | uintptr_t qemu_host_page_size; |
111 | intptr_t qemu_host_page_mask; | |
a0be0c58 | 112 | |
20bccb82 PM |
113 | bool set_preferred_target_page_bits(int bits) |
114 | { | |
115 | /* The target page size is the lowest common denominator for all | |
116 | * the CPUs in the system, so we can only make it smaller, never | |
117 | * larger. And we can't make it smaller once we've committed to | |
118 | * a particular size. | |
119 | */ | |
120 | #ifdef TARGET_PAGE_BITS_VARY | |
121 | assert(bits >= TARGET_PAGE_BITS_MIN); | |
122 | if (target_page_bits == 0 || target_page_bits > bits) { | |
123 | if (target_page_bits_decided) { | |
124 | return false; | |
125 | } | |
126 | target_page_bits = bits; | |
127 | } | |
128 | #endif | |
129 | return true; | |
130 | } | |
131 | ||
e2eef170 | 132 | #if !defined(CONFIG_USER_ONLY) |
4346ae3e | 133 | |
20bccb82 PM |
134 | static void finalize_target_page_bits(void) |
135 | { | |
136 | #ifdef TARGET_PAGE_BITS_VARY | |
137 | if (target_page_bits == 0) { | |
138 | target_page_bits = TARGET_PAGE_BITS_MIN; | |
139 | } | |
140 | target_page_bits_decided = true; | |
141 | #endif | |
142 | } | |
143 | ||
1db8abb1 PB |
144 | typedef struct PhysPageEntry PhysPageEntry; |
145 | ||
146 | struct PhysPageEntry { | |
9736e55b | 147 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ |
8b795765 | 148 | uint32_t skip : 6; |
9736e55b | 149 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ |
8b795765 | 150 | uint32_t ptr : 26; |
1db8abb1 PB |
151 | }; |
152 | ||
8b795765 MT |
153 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
154 | ||
03f49957 | 155 | /* Size of the L2 (and L3, etc) page tables. */ |
57271d63 | 156 | #define ADDR_SPACE_BITS 64 |
03f49957 | 157 | |
026736ce | 158 | #define P_L2_BITS 9 |
03f49957 PB |
159 | #define P_L2_SIZE (1 << P_L2_BITS) |
160 | ||
161 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
162 | ||
163 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
0475d94f | 164 | |
53cb28cb | 165 | typedef struct PhysPageMap { |
79e2b9ae PB |
166 | struct rcu_head rcu; |
167 | ||
53cb28cb MA |
168 | unsigned sections_nb; |
169 | unsigned sections_nb_alloc; | |
170 | unsigned nodes_nb; | |
171 | unsigned nodes_nb_alloc; | |
172 | Node *nodes; | |
173 | MemoryRegionSection *sections; | |
174 | } PhysPageMap; | |
175 | ||
1db8abb1 | 176 | struct AddressSpaceDispatch { |
729633c2 | 177 | MemoryRegionSection *mru_section; |
1db8abb1 PB |
178 | /* This is a multi-level map on the physical address space. |
179 | * The bottom level has pointers to MemoryRegionSections. | |
180 | */ | |
181 | PhysPageEntry phys_map; | |
53cb28cb | 182 | PhysPageMap map; |
1db8abb1 PB |
183 | }; |
184 | ||
90260c6c JK |
185 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
186 | typedef struct subpage_t { | |
187 | MemoryRegion iomem; | |
16620684 | 188 | FlatView *fv; |
90260c6c | 189 | hwaddr base; |
2615fabd | 190 | uint16_t sub_section[]; |
90260c6c JK |
191 | } subpage_t; |
192 | ||
b41aac4f LPF |
193 | #define PHYS_SECTION_UNASSIGNED 0 |
194 | #define PHYS_SECTION_NOTDIRTY 1 | |
195 | #define PHYS_SECTION_ROM 2 | |
196 | #define PHYS_SECTION_WATCH 3 | |
5312bd8b | 197 | |
e2eef170 | 198 | static void io_mem_init(void); |
62152b8a | 199 | static void memory_map_init(void); |
9458a9a1 | 200 | static void tcg_log_global_after_sync(MemoryListener *listener); |
09daed84 | 201 | static void tcg_commit(MemoryListener *listener); |
e2eef170 | 202 | |
1ec9b909 | 203 | static MemoryRegion io_mem_watch; |
32857f4d PM |
204 | |
205 | /** | |
206 | * CPUAddressSpace: all the information a CPU needs about an AddressSpace | |
207 | * @cpu: the CPU whose AddressSpace this is | |
208 | * @as: the AddressSpace itself | |
209 | * @memory_dispatch: its dispatch pointer (cached, RCU protected) | |
210 | * @tcg_as_listener: listener for tracking changes to the AddressSpace | |
211 | */ | |
212 | struct CPUAddressSpace { | |
213 | CPUState *cpu; | |
214 | AddressSpace *as; | |
215 | struct AddressSpaceDispatch *memory_dispatch; | |
216 | MemoryListener tcg_as_listener; | |
217 | }; | |
218 | ||
8deaf12c GH |
219 | struct DirtyBitmapSnapshot { |
220 | ram_addr_t start; | |
221 | ram_addr_t end; | |
222 | unsigned long dirty[]; | |
223 | }; | |
224 | ||
6658ffb8 | 225 | #endif |
fd6ce8f6 | 226 | |
6d9a1304 | 227 | #if !defined(CONFIG_USER_ONLY) |
d6f2ea22 | 228 | |
53cb28cb | 229 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
d6f2ea22 | 230 | { |
101420b8 | 231 | static unsigned alloc_hint = 16; |
53cb28cb | 232 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { |
101420b8 | 233 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint); |
53cb28cb MA |
234 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); |
235 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); | |
101420b8 | 236 | alloc_hint = map->nodes_nb_alloc; |
d6f2ea22 | 237 | } |
f7bf5461 AK |
238 | } |
239 | ||
db94604b | 240 | static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) |
f7bf5461 AK |
241 | { |
242 | unsigned i; | |
8b795765 | 243 | uint32_t ret; |
db94604b PB |
244 | PhysPageEntry e; |
245 | PhysPageEntry *p; | |
f7bf5461 | 246 | |
53cb28cb | 247 | ret = map->nodes_nb++; |
db94604b | 248 | p = map->nodes[ret]; |
f7bf5461 | 249 | assert(ret != PHYS_MAP_NODE_NIL); |
53cb28cb | 250 | assert(ret != map->nodes_nb_alloc); |
db94604b PB |
251 | |
252 | e.skip = leaf ? 0 : 1; | |
253 | e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL; | |
03f49957 | 254 | for (i = 0; i < P_L2_SIZE; ++i) { |
db94604b | 255 | memcpy(&p[i], &e, sizeof(e)); |
d6f2ea22 | 256 | } |
f7bf5461 | 257 | return ret; |
d6f2ea22 AK |
258 | } |
259 | ||
53cb28cb MA |
260 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
261 | hwaddr *index, hwaddr *nb, uint16_t leaf, | |
2999097b | 262 | int level) |
f7bf5461 AK |
263 | { |
264 | PhysPageEntry *p; | |
03f49957 | 265 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); |
108c49b8 | 266 | |
9736e55b | 267 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { |
db94604b | 268 | lp->ptr = phys_map_node_alloc(map, level == 0); |
92e873b9 | 269 | } |
db94604b | 270 | p = map->nodes[lp->ptr]; |
03f49957 | 271 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
f7bf5461 | 272 | |
03f49957 | 273 | while (*nb && lp < &p[P_L2_SIZE]) { |
07f07b31 | 274 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
9736e55b | 275 | lp->skip = 0; |
c19e8800 | 276 | lp->ptr = leaf; |
07f07b31 AK |
277 | *index += step; |
278 | *nb -= step; | |
2999097b | 279 | } else { |
53cb28cb | 280 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); |
2999097b AK |
281 | } |
282 | ++lp; | |
f7bf5461 AK |
283 | } |
284 | } | |
285 | ||
ac1970fb | 286 | static void phys_page_set(AddressSpaceDispatch *d, |
a8170e5e | 287 | hwaddr index, hwaddr nb, |
2999097b | 288 | uint16_t leaf) |
f7bf5461 | 289 | { |
2999097b | 290 | /* Wildly overreserve - it doesn't matter much. */ |
53cb28cb | 291 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); |
5cd2c5b6 | 292 | |
53cb28cb | 293 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
294 | } |
295 | ||
b35ba30f MT |
296 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, |
297 | * and update our entry so we can skip it and go directly to the destination. | |
298 | */ | |
efee678d | 299 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes) |
b35ba30f MT |
300 | { |
301 | unsigned valid_ptr = P_L2_SIZE; | |
302 | int valid = 0; | |
303 | PhysPageEntry *p; | |
304 | int i; | |
305 | ||
306 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
307 | return; | |
308 | } | |
309 | ||
310 | p = nodes[lp->ptr]; | |
311 | for (i = 0; i < P_L2_SIZE; i++) { | |
312 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
313 | continue; | |
314 | } | |
315 | ||
316 | valid_ptr = i; | |
317 | valid++; | |
318 | if (p[i].skip) { | |
efee678d | 319 | phys_page_compact(&p[i], nodes); |
b35ba30f MT |
320 | } |
321 | } | |
322 | ||
323 | /* We can only compress if there's only one child. */ | |
324 | if (valid != 1) { | |
325 | return; | |
326 | } | |
327 | ||
328 | assert(valid_ptr < P_L2_SIZE); | |
329 | ||
330 | /* Don't compress if it won't fit in the # of bits we have. */ | |
331 | if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { | |
332 | return; | |
333 | } | |
334 | ||
335 | lp->ptr = p[valid_ptr].ptr; | |
336 | if (!p[valid_ptr].skip) { | |
337 | /* If our only child is a leaf, make this a leaf. */ | |
338 | /* By design, we should have made this node a leaf to begin with so we | |
339 | * should never reach here. | |
340 | * But since it's so simple to handle this, let's do it just in case we | |
341 | * change this rule. | |
342 | */ | |
343 | lp->skip = 0; | |
344 | } else { | |
345 | lp->skip += p[valid_ptr].skip; | |
346 | } | |
347 | } | |
348 | ||
8629d3fc | 349 | void address_space_dispatch_compact(AddressSpaceDispatch *d) |
b35ba30f | 350 | { |
b35ba30f | 351 | if (d->phys_map.skip) { |
efee678d | 352 | phys_page_compact(&d->phys_map, d->map.nodes); |
b35ba30f MT |
353 | } |
354 | } | |
355 | ||
29cb533d FZ |
356 | static inline bool section_covers_addr(const MemoryRegionSection *section, |
357 | hwaddr addr) | |
358 | { | |
359 | /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means | |
360 | * the section must cover the entire address space. | |
361 | */ | |
258dfaaa | 362 | return int128_gethi(section->size) || |
29cb533d | 363 | range_covers_byte(section->offset_within_address_space, |
258dfaaa | 364 | int128_getlo(section->size), addr); |
29cb533d FZ |
365 | } |
366 | ||
003a0cf2 | 367 | static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr) |
92e873b9 | 368 | { |
003a0cf2 PX |
369 | PhysPageEntry lp = d->phys_map, *p; |
370 | Node *nodes = d->map.nodes; | |
371 | MemoryRegionSection *sections = d->map.sections; | |
97115a8d | 372 | hwaddr index = addr >> TARGET_PAGE_BITS; |
31ab2b4a | 373 | int i; |
f1f6e3b8 | 374 | |
9736e55b | 375 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
c19e8800 | 376 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
9affd6fc | 377 | return §ions[PHYS_SECTION_UNASSIGNED]; |
31ab2b4a | 378 | } |
9affd6fc | 379 | p = nodes[lp.ptr]; |
03f49957 | 380 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
5312bd8b | 381 | } |
b35ba30f | 382 | |
29cb533d | 383 | if (section_covers_addr(§ions[lp.ptr], addr)) { |
b35ba30f MT |
384 | return §ions[lp.ptr]; |
385 | } else { | |
386 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
387 | } | |
f3705d53 AK |
388 | } |
389 | ||
79e2b9ae | 390 | /* Called from RCU critical section */ |
c7086b4a | 391 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, |
90260c6c JK |
392 | hwaddr addr, |
393 | bool resolve_subpage) | |
9f029603 | 394 | { |
729633c2 | 395 | MemoryRegionSection *section = atomic_read(&d->mru_section); |
90260c6c JK |
396 | subpage_t *subpage; |
397 | ||
07c114bb PB |
398 | if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] || |
399 | !section_covers_addr(section, addr)) { | |
003a0cf2 | 400 | section = phys_page_find(d, addr); |
07c114bb | 401 | atomic_set(&d->mru_section, section); |
729633c2 | 402 | } |
90260c6c JK |
403 | if (resolve_subpage && section->mr->subpage) { |
404 | subpage = container_of(section->mr, subpage_t, iomem); | |
53cb28cb | 405 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
90260c6c JK |
406 | } |
407 | return section; | |
9f029603 JK |
408 | } |
409 | ||
79e2b9ae | 410 | /* Called from RCU critical section */ |
90260c6c | 411 | static MemoryRegionSection * |
c7086b4a | 412 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
90260c6c | 413 | hwaddr *plen, bool resolve_subpage) |
149f54b5 PB |
414 | { |
415 | MemoryRegionSection *section; | |
965eb2fc | 416 | MemoryRegion *mr; |
a87f3954 | 417 | Int128 diff; |
149f54b5 | 418 | |
c7086b4a | 419 | section = address_space_lookup_region(d, addr, resolve_subpage); |
149f54b5 PB |
420 | /* Compute offset within MemoryRegionSection */ |
421 | addr -= section->offset_within_address_space; | |
422 | ||
423 | /* Compute offset within MemoryRegion */ | |
424 | *xlat = addr + section->offset_within_region; | |
425 | ||
965eb2fc | 426 | mr = section->mr; |
b242e0e0 PB |
427 | |
428 | /* MMIO registers can be expected to perform full-width accesses based only | |
429 | * on their address, without considering adjacent registers that could | |
430 | * decode to completely different MemoryRegions. When such registers | |
431 | * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO | |
432 | * regions overlap wildly. For this reason we cannot clamp the accesses | |
433 | * here. | |
434 | * | |
435 | * If the length is small (as is the case for address_space_ldl/stl), | |
436 | * everything works fine. If the incoming length is large, however, | |
437 | * the caller really has to do the clamping through memory_access_size. | |
438 | */ | |
965eb2fc | 439 | if (memory_region_is_ram(mr)) { |
e4a511f8 | 440 | diff = int128_sub(section->size, int128_make64(addr)); |
965eb2fc PB |
441 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
442 | } | |
149f54b5 PB |
443 | return section; |
444 | } | |
90260c6c | 445 | |
a411c84b PB |
446 | /** |
447 | * address_space_translate_iommu - translate an address through an IOMMU | |
448 | * memory region and then through the target address space. | |
449 | * | |
450 | * @iommu_mr: the IOMMU memory region that we start the translation from | |
451 | * @addr: the address to be translated through the MMU | |
452 | * @xlat: the translated address offset within the destination memory region. | |
453 | * It cannot be %NULL. | |
454 | * @plen_out: valid read/write length of the translated address. It | |
455 | * cannot be %NULL. | |
456 | * @page_mask_out: page mask for the translated address. This | |
457 | * should only be meaningful for IOMMU translated | |
458 | * addresses, since there may be huge pages that this bit | |
459 | * would tell. It can be %NULL if we don't care about it. | |
460 | * @is_write: whether the translation operation is for write | |
461 | * @is_mmio: whether this can be MMIO, set true if it can | |
462 | * @target_as: the address space targeted by the IOMMU | |
2f7b009c | 463 | * @attrs: transaction attributes |
a411c84b PB |
464 | * |
465 | * This function is called from RCU critical section. It is the common | |
466 | * part of flatview_do_translate and address_space_translate_cached. | |
467 | */ | |
468 | static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr, | |
469 | hwaddr *xlat, | |
470 | hwaddr *plen_out, | |
471 | hwaddr *page_mask_out, | |
472 | bool is_write, | |
473 | bool is_mmio, | |
2f7b009c PM |
474 | AddressSpace **target_as, |
475 | MemTxAttrs attrs) | |
a411c84b PB |
476 | { |
477 | MemoryRegionSection *section; | |
478 | hwaddr page_mask = (hwaddr)-1; | |
479 | ||
480 | do { | |
481 | hwaddr addr = *xlat; | |
482 | IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
2c91bcf2 PM |
483 | int iommu_idx = 0; |
484 | IOMMUTLBEntry iotlb; | |
485 | ||
486 | if (imrc->attrs_to_index) { | |
487 | iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | |
488 | } | |
489 | ||
490 | iotlb = imrc->translate(iommu_mr, addr, is_write ? | |
491 | IOMMU_WO : IOMMU_RO, iommu_idx); | |
a411c84b PB |
492 | |
493 | if (!(iotlb.perm & (1 << is_write))) { | |
494 | goto unassigned; | |
495 | } | |
496 | ||
497 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
498 | | (addr & iotlb.addr_mask)); | |
499 | page_mask &= iotlb.addr_mask; | |
500 | *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1); | |
501 | *target_as = iotlb.target_as; | |
502 | ||
503 | section = address_space_translate_internal( | |
504 | address_space_to_dispatch(iotlb.target_as), addr, xlat, | |
505 | plen_out, is_mmio); | |
506 | ||
507 | iommu_mr = memory_region_get_iommu(section->mr); | |
508 | } while (unlikely(iommu_mr)); | |
509 | ||
510 | if (page_mask_out) { | |
511 | *page_mask_out = page_mask; | |
512 | } | |
513 | return *section; | |
514 | ||
515 | unassigned: | |
516 | return (MemoryRegionSection) { .mr = &io_mem_unassigned }; | |
517 | } | |
518 | ||
d5e5fafd PX |
519 | /** |
520 | * flatview_do_translate - translate an address in FlatView | |
521 | * | |
522 | * @fv: the flat view that we want to translate on | |
523 | * @addr: the address to be translated in above address space | |
524 | * @xlat: the translated address offset within memory region. It | |
525 | * cannot be @NULL. | |
526 | * @plen_out: valid read/write length of the translated address. It | |
527 | * can be @NULL when we don't care about it. | |
528 | * @page_mask_out: page mask for the translated address. This | |
529 | * should only be meaningful for IOMMU translated | |
530 | * addresses, since there may be huge pages that this bit | |
531 | * would tell. It can be @NULL if we don't care about it. | |
532 | * @is_write: whether the translation operation is for write | |
533 | * @is_mmio: whether this can be MMIO, set true if it can | |
ad2804d9 | 534 | * @target_as: the address space targeted by the IOMMU |
49e14aa8 | 535 | * @attrs: memory transaction attributes |
d5e5fafd PX |
536 | * |
537 | * This function is called from RCU critical section | |
538 | */ | |
16620684 AK |
539 | static MemoryRegionSection flatview_do_translate(FlatView *fv, |
540 | hwaddr addr, | |
541 | hwaddr *xlat, | |
d5e5fafd PX |
542 | hwaddr *plen_out, |
543 | hwaddr *page_mask_out, | |
16620684 AK |
544 | bool is_write, |
545 | bool is_mmio, | |
49e14aa8 PM |
546 | AddressSpace **target_as, |
547 | MemTxAttrs attrs) | |
052c8fa9 | 548 | { |
052c8fa9 | 549 | MemoryRegionSection *section; |
3df9d748 | 550 | IOMMUMemoryRegion *iommu_mr; |
d5e5fafd PX |
551 | hwaddr plen = (hwaddr)(-1); |
552 | ||
ad2804d9 PB |
553 | if (!plen_out) { |
554 | plen_out = &plen; | |
d5e5fafd | 555 | } |
052c8fa9 | 556 | |
a411c84b PB |
557 | section = address_space_translate_internal( |
558 | flatview_to_dispatch(fv), addr, xlat, | |
559 | plen_out, is_mmio); | |
052c8fa9 | 560 | |
a411c84b PB |
561 | iommu_mr = memory_region_get_iommu(section->mr); |
562 | if (unlikely(iommu_mr)) { | |
563 | return address_space_translate_iommu(iommu_mr, xlat, | |
564 | plen_out, page_mask_out, | |
565 | is_write, is_mmio, | |
2f7b009c | 566 | target_as, attrs); |
052c8fa9 | 567 | } |
d5e5fafd | 568 | if (page_mask_out) { |
a411c84b PB |
569 | /* Not behind an IOMMU, use default page size. */ |
570 | *page_mask_out = ~TARGET_PAGE_MASK; | |
d5e5fafd PX |
571 | } |
572 | ||
a764040c | 573 | return *section; |
052c8fa9 JW |
574 | } |
575 | ||
576 | /* Called from RCU critical section */ | |
a764040c | 577 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, |
7446eb07 | 578 | bool is_write, MemTxAttrs attrs) |
90260c6c | 579 | { |
a764040c | 580 | MemoryRegionSection section; |
076a93d7 | 581 | hwaddr xlat, page_mask; |
30951157 | 582 | |
076a93d7 PX |
583 | /* |
584 | * This can never be MMIO, and we don't really care about plen, | |
585 | * but page mask. | |
586 | */ | |
587 | section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat, | |
49e14aa8 PM |
588 | NULL, &page_mask, is_write, false, &as, |
589 | attrs); | |
30951157 | 590 | |
a764040c PX |
591 | /* Illegal translation */ |
592 | if (section.mr == &io_mem_unassigned) { | |
593 | goto iotlb_fail; | |
594 | } | |
30951157 | 595 | |
a764040c PX |
596 | /* Convert memory region offset into address space offset */ |
597 | xlat += section.offset_within_address_space - | |
598 | section.offset_within_region; | |
599 | ||
a764040c | 600 | return (IOMMUTLBEntry) { |
e76bb18f | 601 | .target_as = as, |
076a93d7 PX |
602 | .iova = addr & ~page_mask, |
603 | .translated_addr = xlat & ~page_mask, | |
604 | .addr_mask = page_mask, | |
a764040c PX |
605 | /* IOTLBs are for DMAs, and DMA only allows on RAMs. */ |
606 | .perm = IOMMU_RW, | |
607 | }; | |
608 | ||
609 | iotlb_fail: | |
610 | return (IOMMUTLBEntry) {0}; | |
611 | } | |
612 | ||
613 | /* Called from RCU critical section */ | |
16620684 | 614 | MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, |
efa99a2f PM |
615 | hwaddr *plen, bool is_write, |
616 | MemTxAttrs attrs) | |
a764040c PX |
617 | { |
618 | MemoryRegion *mr; | |
619 | MemoryRegionSection section; | |
16620684 | 620 | AddressSpace *as = NULL; |
a764040c PX |
621 | |
622 | /* This can be MMIO, so setup MMIO bit. */ | |
d5e5fafd | 623 | section = flatview_do_translate(fv, addr, xlat, plen, NULL, |
49e14aa8 | 624 | is_write, true, &as, attrs); |
a764040c PX |
625 | mr = section.mr; |
626 | ||
fe680d0d | 627 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { |
a87f3954 | 628 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; |
23820dbf | 629 | *plen = MIN(page, *plen); |
a87f3954 PB |
630 | } |
631 | ||
30951157 | 632 | return mr; |
90260c6c JK |
633 | } |
634 | ||
1f871c5e PM |
635 | typedef struct TCGIOMMUNotifier { |
636 | IOMMUNotifier n; | |
637 | MemoryRegion *mr; | |
638 | CPUState *cpu; | |
639 | int iommu_idx; | |
640 | bool active; | |
641 | } TCGIOMMUNotifier; | |
642 | ||
643 | static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb) | |
644 | { | |
645 | TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n); | |
646 | ||
647 | if (!notifier->active) { | |
648 | return; | |
649 | } | |
650 | tlb_flush(notifier->cpu); | |
651 | notifier->active = false; | |
652 | /* We leave the notifier struct on the list to avoid reallocating it later. | |
653 | * Generally the number of IOMMUs a CPU deals with will be small. | |
654 | * In any case we can't unregister the iommu notifier from a notify | |
655 | * callback. | |
656 | */ | |
657 | } | |
658 | ||
659 | static void tcg_register_iommu_notifier(CPUState *cpu, | |
660 | IOMMUMemoryRegion *iommu_mr, | |
661 | int iommu_idx) | |
662 | { | |
663 | /* Make sure this CPU has an IOMMU notifier registered for this | |
664 | * IOMMU/IOMMU index combination, so that we can flush its TLB | |
665 | * when the IOMMU tells us the mappings we've cached have changed. | |
666 | */ | |
667 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); | |
668 | TCGIOMMUNotifier *notifier; | |
669 | int i; | |
670 | ||
671 | for (i = 0; i < cpu->iommu_notifiers->len; i++) { | |
5601be3b | 672 | notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); |
1f871c5e PM |
673 | if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) { |
674 | break; | |
675 | } | |
676 | } | |
677 | if (i == cpu->iommu_notifiers->len) { | |
678 | /* Not found, add a new entry at the end of the array */ | |
679 | cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1); | |
5601be3b PM |
680 | notifier = g_new0(TCGIOMMUNotifier, 1); |
681 | g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier; | |
1f871c5e PM |
682 | |
683 | notifier->mr = mr; | |
684 | notifier->iommu_idx = iommu_idx; | |
685 | notifier->cpu = cpu; | |
686 | /* Rather than trying to register interest in the specific part | |
687 | * of the iommu's address space that we've accessed and then | |
688 | * expand it later as subsequent accesses touch more of it, we | |
689 | * just register interest in the whole thing, on the assumption | |
690 | * that iommu reconfiguration will be rare. | |
691 | */ | |
692 | iommu_notifier_init(¬ifier->n, | |
693 | tcg_iommu_unmap_notify, | |
694 | IOMMU_NOTIFIER_UNMAP, | |
695 | 0, | |
696 | HWADDR_MAX, | |
697 | iommu_idx); | |
698 | memory_region_register_iommu_notifier(notifier->mr, ¬ifier->n); | |
699 | } | |
700 | ||
701 | if (!notifier->active) { | |
702 | notifier->active = true; | |
703 | } | |
704 | } | |
705 | ||
706 | static void tcg_iommu_free_notifier_list(CPUState *cpu) | |
707 | { | |
708 | /* Destroy the CPU's notifier list */ | |
709 | int i; | |
710 | TCGIOMMUNotifier *notifier; | |
711 | ||
712 | for (i = 0; i < cpu->iommu_notifiers->len; i++) { | |
5601be3b | 713 | notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); |
1f871c5e | 714 | memory_region_unregister_iommu_notifier(notifier->mr, ¬ifier->n); |
5601be3b | 715 | g_free(notifier); |
1f871c5e PM |
716 | } |
717 | g_array_free(cpu->iommu_notifiers, true); | |
718 | } | |
719 | ||
79e2b9ae | 720 | /* Called from RCU critical section */ |
90260c6c | 721 | MemoryRegionSection * |
d7898cda | 722 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, |
1f871c5e PM |
723 | hwaddr *xlat, hwaddr *plen, |
724 | MemTxAttrs attrs, int *prot) | |
90260c6c | 725 | { |
30951157 | 726 | MemoryRegionSection *section; |
1f871c5e PM |
727 | IOMMUMemoryRegion *iommu_mr; |
728 | IOMMUMemoryRegionClass *imrc; | |
729 | IOMMUTLBEntry iotlb; | |
730 | int iommu_idx; | |
f35e44e7 | 731 | AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch); |
d7898cda | 732 | |
1f871c5e PM |
733 | for (;;) { |
734 | section = address_space_translate_internal(d, addr, &addr, plen, false); | |
735 | ||
736 | iommu_mr = memory_region_get_iommu(section->mr); | |
737 | if (!iommu_mr) { | |
738 | break; | |
739 | } | |
740 | ||
741 | imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
742 | ||
743 | iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | |
744 | tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); | |
745 | /* We need all the permissions, so pass IOMMU_NONE so the IOMMU | |
746 | * doesn't short-cut its translation table walk. | |
747 | */ | |
748 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx); | |
749 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
750 | | (addr & iotlb.addr_mask)); | |
751 | /* Update the caller's prot bits to remove permissions the IOMMU | |
752 | * is giving us a failure response for. If we get down to no | |
753 | * permissions left at all we can give up now. | |
754 | */ | |
755 | if (!(iotlb.perm & IOMMU_RO)) { | |
756 | *prot &= ~(PAGE_READ | PAGE_EXEC); | |
757 | } | |
758 | if (!(iotlb.perm & IOMMU_WO)) { | |
759 | *prot &= ~PAGE_WRITE; | |
760 | } | |
761 | ||
762 | if (!*prot) { | |
763 | goto translate_fail; | |
764 | } | |
765 | ||
766 | d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as)); | |
767 | } | |
30951157 | 768 | |
3df9d748 | 769 | assert(!memory_region_is_iommu(section->mr)); |
1f871c5e | 770 | *xlat = addr; |
30951157 | 771 | return section; |
1f871c5e PM |
772 | |
773 | translate_fail: | |
774 | return &d->map.sections[PHYS_SECTION_UNASSIGNED]; | |
90260c6c | 775 | } |
5b6dd868 | 776 | #endif |
fd6ce8f6 | 777 | |
b170fce3 | 778 | #if !defined(CONFIG_USER_ONLY) |
5b6dd868 BS |
779 | |
780 | static int cpu_common_post_load(void *opaque, int version_id) | |
fd6ce8f6 | 781 | { |
259186a7 | 782 | CPUState *cpu = opaque; |
a513fe19 | 783 | |
5b6dd868 BS |
784 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
785 | version_id is increased. */ | |
259186a7 | 786 | cpu->interrupt_request &= ~0x01; |
d10eb08f | 787 | tlb_flush(cpu); |
5b6dd868 | 788 | |
15a356c4 PD |
789 | /* loadvm has just updated the content of RAM, bypassing the |
790 | * usual mechanisms that ensure we flush TBs for writes to | |
791 | * memory we've translated code from. So we must flush all TBs, | |
792 | * which will now be stale. | |
793 | */ | |
794 | tb_flush(cpu); | |
795 | ||
5b6dd868 | 796 | return 0; |
a513fe19 | 797 | } |
7501267e | 798 | |
6c3bff0e PD |
799 | static int cpu_common_pre_load(void *opaque) |
800 | { | |
801 | CPUState *cpu = opaque; | |
802 | ||
adee6424 | 803 | cpu->exception_index = -1; |
6c3bff0e PD |
804 | |
805 | return 0; | |
806 | } | |
807 | ||
808 | static bool cpu_common_exception_index_needed(void *opaque) | |
809 | { | |
810 | CPUState *cpu = opaque; | |
811 | ||
adee6424 | 812 | return tcg_enabled() && cpu->exception_index != -1; |
6c3bff0e PD |
813 | } |
814 | ||
815 | static const VMStateDescription vmstate_cpu_common_exception_index = { | |
816 | .name = "cpu_common/exception_index", | |
817 | .version_id = 1, | |
818 | .minimum_version_id = 1, | |
5cd8cada | 819 | .needed = cpu_common_exception_index_needed, |
6c3bff0e PD |
820 | .fields = (VMStateField[]) { |
821 | VMSTATE_INT32(exception_index, CPUState), | |
822 | VMSTATE_END_OF_LIST() | |
823 | } | |
824 | }; | |
825 | ||
bac05aa9 AS |
826 | static bool cpu_common_crash_occurred_needed(void *opaque) |
827 | { | |
828 | CPUState *cpu = opaque; | |
829 | ||
830 | return cpu->crash_occurred; | |
831 | } | |
832 | ||
833 | static const VMStateDescription vmstate_cpu_common_crash_occurred = { | |
834 | .name = "cpu_common/crash_occurred", | |
835 | .version_id = 1, | |
836 | .minimum_version_id = 1, | |
837 | .needed = cpu_common_crash_occurred_needed, | |
838 | .fields = (VMStateField[]) { | |
839 | VMSTATE_BOOL(crash_occurred, CPUState), | |
840 | VMSTATE_END_OF_LIST() | |
841 | } | |
842 | }; | |
843 | ||
1a1562f5 | 844 | const VMStateDescription vmstate_cpu_common = { |
5b6dd868 BS |
845 | .name = "cpu_common", |
846 | .version_id = 1, | |
847 | .minimum_version_id = 1, | |
6c3bff0e | 848 | .pre_load = cpu_common_pre_load, |
5b6dd868 | 849 | .post_load = cpu_common_post_load, |
35d08458 | 850 | .fields = (VMStateField[]) { |
259186a7 AF |
851 | VMSTATE_UINT32(halted, CPUState), |
852 | VMSTATE_UINT32(interrupt_request, CPUState), | |
5b6dd868 | 853 | VMSTATE_END_OF_LIST() |
6c3bff0e | 854 | }, |
5cd8cada JQ |
855 | .subsections = (const VMStateDescription*[]) { |
856 | &vmstate_cpu_common_exception_index, | |
bac05aa9 | 857 | &vmstate_cpu_common_crash_occurred, |
5cd8cada | 858 | NULL |
5b6dd868 BS |
859 | } |
860 | }; | |
1a1562f5 | 861 | |
5b6dd868 | 862 | #endif |
ea041c0e | 863 | |
38d8f5c8 | 864 | CPUState *qemu_get_cpu(int index) |
ea041c0e | 865 | { |
bdc44640 | 866 | CPUState *cpu; |
ea041c0e | 867 | |
bdc44640 | 868 | CPU_FOREACH(cpu) { |
55e5c285 | 869 | if (cpu->cpu_index == index) { |
bdc44640 | 870 | return cpu; |
55e5c285 | 871 | } |
ea041c0e | 872 | } |
5b6dd868 | 873 | |
bdc44640 | 874 | return NULL; |
ea041c0e FB |
875 | } |
876 | ||
09daed84 | 877 | #if !defined(CONFIG_USER_ONLY) |
80ceb07a PX |
878 | void cpu_address_space_init(CPUState *cpu, int asidx, |
879 | const char *prefix, MemoryRegion *mr) | |
09daed84 | 880 | { |
12ebc9a7 | 881 | CPUAddressSpace *newas; |
80ceb07a | 882 | AddressSpace *as = g_new0(AddressSpace, 1); |
87a621d8 | 883 | char *as_name; |
80ceb07a PX |
884 | |
885 | assert(mr); | |
87a621d8 PX |
886 | as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index); |
887 | address_space_init(as, mr, as_name); | |
888 | g_free(as_name); | |
12ebc9a7 PM |
889 | |
890 | /* Target code should have set num_ases before calling us */ | |
891 | assert(asidx < cpu->num_ases); | |
892 | ||
56943e8c PM |
893 | if (asidx == 0) { |
894 | /* address space 0 gets the convenience alias */ | |
895 | cpu->as = as; | |
896 | } | |
897 | ||
12ebc9a7 PM |
898 | /* KVM cannot currently support multiple address spaces. */ |
899 | assert(asidx == 0 || !kvm_enabled()); | |
09daed84 | 900 | |
12ebc9a7 PM |
901 | if (!cpu->cpu_ases) { |
902 | cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases); | |
09daed84 | 903 | } |
32857f4d | 904 | |
12ebc9a7 PM |
905 | newas = &cpu->cpu_ases[asidx]; |
906 | newas->cpu = cpu; | |
907 | newas->as = as; | |
56943e8c | 908 | if (tcg_enabled()) { |
9458a9a1 | 909 | newas->tcg_as_listener.log_global_after_sync = tcg_log_global_after_sync; |
12ebc9a7 PM |
910 | newas->tcg_as_listener.commit = tcg_commit; |
911 | memory_listener_register(&newas->tcg_as_listener, as); | |
56943e8c | 912 | } |
09daed84 | 913 | } |
651a5bc0 PM |
914 | |
915 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) | |
916 | { | |
917 | /* Return the AddressSpace corresponding to the specified index */ | |
918 | return cpu->cpu_ases[asidx].as; | |
919 | } | |
09daed84 EI |
920 | #endif |
921 | ||
7bbc124e | 922 | void cpu_exec_unrealizefn(CPUState *cpu) |
1c59eb39 | 923 | { |
9dfeca7c BR |
924 | CPUClass *cc = CPU_GET_CLASS(cpu); |
925 | ||
267f685b | 926 | cpu_list_remove(cpu); |
9dfeca7c BR |
927 | |
928 | if (cc->vmsd != NULL) { | |
929 | vmstate_unregister(NULL, cc->vmsd, cpu); | |
930 | } | |
931 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | |
932 | vmstate_unregister(NULL, &vmstate_cpu_common, cpu); | |
933 | } | |
1f871c5e PM |
934 | #ifndef CONFIG_USER_ONLY |
935 | tcg_iommu_free_notifier_list(cpu); | |
936 | #endif | |
1c59eb39 BR |
937 | } |
938 | ||
c7e002c5 FZ |
939 | Property cpu_common_props[] = { |
940 | #ifndef CONFIG_USER_ONLY | |
941 | /* Create a memory property for softmmu CPU object, | |
2e5b09fd | 942 | * so users can wire up its memory. (This can't go in hw/core/cpu.c |
c7e002c5 FZ |
943 | * because that file is compiled only once for both user-mode |
944 | * and system builds.) The default if no link is set up is to use | |
945 | * the system address space. | |
946 | */ | |
947 | DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, | |
948 | MemoryRegion *), | |
949 | #endif | |
950 | DEFINE_PROP_END_OF_LIST(), | |
951 | }; | |
952 | ||
39e329e3 | 953 | void cpu_exec_initfn(CPUState *cpu) |
ea041c0e | 954 | { |
56943e8c | 955 | cpu->as = NULL; |
12ebc9a7 | 956 | cpu->num_ases = 0; |
56943e8c | 957 | |
291135b5 | 958 | #ifndef CONFIG_USER_ONLY |
291135b5 | 959 | cpu->thread_id = qemu_get_thread_id(); |
6731d864 PC |
960 | cpu->memory = system_memory; |
961 | object_ref(OBJECT(cpu->memory)); | |
291135b5 | 962 | #endif |
39e329e3 LV |
963 | } |
964 | ||
ce5b1bbf | 965 | void cpu_exec_realizefn(CPUState *cpu, Error **errp) |
39e329e3 | 966 | { |
55c3ceef | 967 | CPUClass *cc = CPU_GET_CLASS(cpu); |
2dda6354 | 968 | static bool tcg_target_initialized; |
291135b5 | 969 | |
267f685b | 970 | cpu_list_add(cpu); |
1bc7e522 | 971 | |
2dda6354 EC |
972 | if (tcg_enabled() && !tcg_target_initialized) { |
973 | tcg_target_initialized = true; | |
55c3ceef RH |
974 | cc->tcg_initialize(); |
975 | } | |
5005e253 | 976 | tlb_init(cpu); |
55c3ceef | 977 | |
1bc7e522 | 978 | #ifndef CONFIG_USER_ONLY |
e0d47944 | 979 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { |
741da0d3 | 980 | vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); |
e0d47944 | 981 | } |
b170fce3 | 982 | if (cc->vmsd != NULL) { |
741da0d3 | 983 | vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); |
b170fce3 | 984 | } |
1f871c5e | 985 | |
5601be3b | 986 | cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *)); |
741da0d3 | 987 | #endif |
ea041c0e FB |
988 | } |
989 | ||
c1c8cfe5 | 990 | const char *parse_cpu_option(const char *cpu_option) |
2278b939 IM |
991 | { |
992 | ObjectClass *oc; | |
993 | CPUClass *cc; | |
994 | gchar **model_pieces; | |
995 | const char *cpu_type; | |
996 | ||
c1c8cfe5 | 997 | model_pieces = g_strsplit(cpu_option, ",", 2); |
5b863f3e EH |
998 | if (!model_pieces[0]) { |
999 | error_report("-cpu option cannot be empty"); | |
1000 | exit(1); | |
1001 | } | |
2278b939 IM |
1002 | |
1003 | oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]); | |
1004 | if (oc == NULL) { | |
1005 | error_report("unable to find CPU model '%s'", model_pieces[0]); | |
1006 | g_strfreev(model_pieces); | |
1007 | exit(EXIT_FAILURE); | |
1008 | } | |
1009 | ||
1010 | cpu_type = object_class_get_name(oc); | |
1011 | cc = CPU_CLASS(oc); | |
1012 | cc->parse_features(cpu_type, model_pieces[1], &error_fatal); | |
1013 | g_strfreev(model_pieces); | |
1014 | return cpu_type; | |
1015 | } | |
1016 | ||
c40d4792 | 1017 | #if defined(CONFIG_USER_ONLY) |
8bca9a03 | 1018 | void tb_invalidate_phys_addr(target_ulong addr) |
1e7855a5 | 1019 | { |
406bc339 | 1020 | mmap_lock(); |
8bca9a03 | 1021 | tb_invalidate_phys_page_range(addr, addr + 1, 0); |
406bc339 PK |
1022 | mmap_unlock(); |
1023 | } | |
8bca9a03 PB |
1024 | |
1025 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | |
1026 | { | |
1027 | tb_invalidate_phys_addr(pc); | |
1028 | } | |
406bc339 | 1029 | #else |
8bca9a03 PB |
1030 | void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) |
1031 | { | |
1032 | ram_addr_t ram_addr; | |
1033 | MemoryRegion *mr; | |
1034 | hwaddr l = 1; | |
1035 | ||
c40d4792 PB |
1036 | if (!tcg_enabled()) { |
1037 | return; | |
1038 | } | |
1039 | ||
8bca9a03 PB |
1040 | rcu_read_lock(); |
1041 | mr = address_space_translate(as, addr, &addr, &l, false, attrs); | |
1042 | if (!(memory_region_is_ram(mr) | |
1043 | || memory_region_is_romd(mr))) { | |
1044 | rcu_read_unlock(); | |
1045 | return; | |
1046 | } | |
1047 | ram_addr = memory_region_get_ram_addr(mr) + addr; | |
1048 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); | |
1049 | rcu_read_unlock(); | |
1050 | } | |
1051 | ||
406bc339 PK |
1052 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
1053 | { | |
1054 | MemTxAttrs attrs; | |
1055 | hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); | |
1056 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | |
1057 | if (phys != -1) { | |
1058 | /* Locks grabbed by tb_invalidate_phys_addr */ | |
1059 | tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, | |
c874dc4f | 1060 | phys | (pc & ~TARGET_PAGE_MASK), attrs); |
406bc339 | 1061 | } |
1e7855a5 | 1062 | } |
406bc339 | 1063 | #endif |
d720b93d | 1064 | |
c527ee8f | 1065 | #if defined(CONFIG_USER_ONLY) |
75a34036 | 1066 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
c527ee8f PB |
1067 | |
1068 | { | |
1069 | } | |
1070 | ||
3ee887e8 PM |
1071 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
1072 | int flags) | |
1073 | { | |
1074 | return -ENOSYS; | |
1075 | } | |
1076 | ||
1077 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
1078 | { | |
1079 | } | |
1080 | ||
75a34036 | 1081 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
c527ee8f PB |
1082 | int flags, CPUWatchpoint **watchpoint) |
1083 | { | |
1084 | return -ENOSYS; | |
1085 | } | |
1086 | #else | |
6658ffb8 | 1087 | /* Add a watchpoint. */ |
75a34036 | 1088 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 1089 | int flags, CPUWatchpoint **watchpoint) |
6658ffb8 | 1090 | { |
c0ce998e | 1091 | CPUWatchpoint *wp; |
6658ffb8 | 1092 | |
05068c0d | 1093 | /* forbid ranges which are empty or run off the end of the address space */ |
07e2863d | 1094 | if (len == 0 || (addr + len - 1) < addr) { |
75a34036 AF |
1095 | error_report("tried to set invalid watchpoint at %" |
1096 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); | |
b4051334 AL |
1097 | return -EINVAL; |
1098 | } | |
7267c094 | 1099 | wp = g_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1100 | |
1101 | wp->vaddr = addr; | |
05068c0d | 1102 | wp->len = len; |
a1d1bb31 AL |
1103 | wp->flags = flags; |
1104 | ||
2dc9f411 | 1105 | /* keep all GDB-injected watchpoints in front */ |
ff4700b0 AF |
1106 | if (flags & BP_GDB) { |
1107 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); | |
1108 | } else { | |
1109 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); | |
1110 | } | |
6658ffb8 | 1111 | |
31b030d4 | 1112 | tlb_flush_page(cpu, addr); |
a1d1bb31 AL |
1113 | |
1114 | if (watchpoint) | |
1115 | *watchpoint = wp; | |
1116 | return 0; | |
6658ffb8 PB |
1117 | } |
1118 | ||
a1d1bb31 | 1119 | /* Remove a specific watchpoint. */ |
75a34036 | 1120 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 1121 | int flags) |
6658ffb8 | 1122 | { |
a1d1bb31 | 1123 | CPUWatchpoint *wp; |
6658ffb8 | 1124 | |
ff4700b0 | 1125 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 1126 | if (addr == wp->vaddr && len == wp->len |
6e140f28 | 1127 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
75a34036 | 1128 | cpu_watchpoint_remove_by_ref(cpu, wp); |
6658ffb8 PB |
1129 | return 0; |
1130 | } | |
1131 | } | |
a1d1bb31 | 1132 | return -ENOENT; |
6658ffb8 PB |
1133 | } |
1134 | ||
a1d1bb31 | 1135 | /* Remove a specific watchpoint by reference. */ |
75a34036 | 1136 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) |
a1d1bb31 | 1137 | { |
ff4700b0 | 1138 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); |
7d03f82f | 1139 | |
31b030d4 | 1140 | tlb_flush_page(cpu, watchpoint->vaddr); |
a1d1bb31 | 1141 | |
7267c094 | 1142 | g_free(watchpoint); |
a1d1bb31 AL |
1143 | } |
1144 | ||
1145 | /* Remove all matching watchpoints. */ | |
75a34036 | 1146 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 1147 | { |
c0ce998e | 1148 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1149 | |
ff4700b0 | 1150 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { |
75a34036 AF |
1151 | if (wp->flags & mask) { |
1152 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
1153 | } | |
c0ce998e | 1154 | } |
7d03f82f | 1155 | } |
05068c0d PM |
1156 | |
1157 | /* Return true if this watchpoint address matches the specified | |
1158 | * access (ie the address range covered by the watchpoint overlaps | |
1159 | * partially or completely with the address range covered by the | |
1160 | * access). | |
1161 | */ | |
1162 | static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, | |
1163 | vaddr addr, | |
1164 | vaddr len) | |
1165 | { | |
1166 | /* We know the lengths are non-zero, but a little caution is | |
1167 | * required to avoid errors in the case where the range ends | |
1168 | * exactly at the top of the address space and so addr + len | |
1169 | * wraps round to zero. | |
1170 | */ | |
1171 | vaddr wpend = wp->vaddr + wp->len - 1; | |
1172 | vaddr addrend = addr + len - 1; | |
1173 | ||
1174 | return !(addr > wpend || wp->vaddr > addrend); | |
1175 | } | |
1176 | ||
c527ee8f | 1177 | #endif |
7d03f82f | 1178 | |
a1d1bb31 | 1179 | /* Add a breakpoint. */ |
b3310ab3 | 1180 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, |
a1d1bb31 | 1181 | CPUBreakpoint **breakpoint) |
4c3a88a2 | 1182 | { |
c0ce998e | 1183 | CPUBreakpoint *bp; |
3b46e624 | 1184 | |
7267c094 | 1185 | bp = g_malloc(sizeof(*bp)); |
4c3a88a2 | 1186 | |
a1d1bb31 AL |
1187 | bp->pc = pc; |
1188 | bp->flags = flags; | |
1189 | ||
2dc9f411 | 1190 | /* keep all GDB-injected breakpoints in front */ |
00b941e5 | 1191 | if (flags & BP_GDB) { |
f0c3c505 | 1192 | QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); |
00b941e5 | 1193 | } else { |
f0c3c505 | 1194 | QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); |
00b941e5 | 1195 | } |
3b46e624 | 1196 | |
f0c3c505 | 1197 | breakpoint_invalidate(cpu, pc); |
a1d1bb31 | 1198 | |
00b941e5 | 1199 | if (breakpoint) { |
a1d1bb31 | 1200 | *breakpoint = bp; |
00b941e5 | 1201 | } |
4c3a88a2 | 1202 | return 0; |
4c3a88a2 FB |
1203 | } |
1204 | ||
a1d1bb31 | 1205 | /* Remove a specific breakpoint. */ |
b3310ab3 | 1206 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) |
a1d1bb31 | 1207 | { |
a1d1bb31 AL |
1208 | CPUBreakpoint *bp; |
1209 | ||
f0c3c505 | 1210 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { |
a1d1bb31 | 1211 | if (bp->pc == pc && bp->flags == flags) { |
b3310ab3 | 1212 | cpu_breakpoint_remove_by_ref(cpu, bp); |
a1d1bb31 AL |
1213 | return 0; |
1214 | } | |
7d03f82f | 1215 | } |
a1d1bb31 | 1216 | return -ENOENT; |
7d03f82f EI |
1217 | } |
1218 | ||
a1d1bb31 | 1219 | /* Remove a specific breakpoint by reference. */ |
b3310ab3 | 1220 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) |
4c3a88a2 | 1221 | { |
f0c3c505 AF |
1222 | QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); |
1223 | ||
1224 | breakpoint_invalidate(cpu, breakpoint->pc); | |
a1d1bb31 | 1225 | |
7267c094 | 1226 | g_free(breakpoint); |
a1d1bb31 AL |
1227 | } |
1228 | ||
1229 | /* Remove all matching breakpoints. */ | |
b3310ab3 | 1230 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 1231 | { |
c0ce998e | 1232 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1233 | |
f0c3c505 | 1234 | QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { |
b3310ab3 AF |
1235 | if (bp->flags & mask) { |
1236 | cpu_breakpoint_remove_by_ref(cpu, bp); | |
1237 | } | |
c0ce998e | 1238 | } |
4c3a88a2 FB |
1239 | } |
1240 | ||
c33a346e FB |
1241 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1242 | CPU loop after each instruction */ | |
3825b28f | 1243 | void cpu_single_step(CPUState *cpu, int enabled) |
c33a346e | 1244 | { |
ed2803da AF |
1245 | if (cpu->singlestep_enabled != enabled) { |
1246 | cpu->singlestep_enabled = enabled; | |
1247 | if (kvm_enabled()) { | |
38e478ec | 1248 | kvm_update_guest_debug(cpu, 0); |
ed2803da | 1249 | } else { |
ccbb4d44 | 1250 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 | 1251 | /* XXX: only flush what is necessary */ |
bbd77c18 | 1252 | tb_flush(cpu); |
e22a25c9 | 1253 | } |
c33a346e | 1254 | } |
c33a346e FB |
1255 | } |
1256 | ||
a47dddd7 | 1257 | void cpu_abort(CPUState *cpu, const char *fmt, ...) |
7501267e FB |
1258 | { |
1259 | va_list ap; | |
493ae1f0 | 1260 | va_list ap2; |
7501267e FB |
1261 | |
1262 | va_start(ap, fmt); | |
493ae1f0 | 1263 | va_copy(ap2, ap); |
7501267e FB |
1264 | fprintf(stderr, "qemu: fatal: "); |
1265 | vfprintf(stderr, fmt, ap); | |
1266 | fprintf(stderr, "\n"); | |
90c84c56 | 1267 | cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
013a2942 | 1268 | if (qemu_log_separate()) { |
1ee73216 | 1269 | qemu_log_lock(); |
93fcfe39 AL |
1270 | qemu_log("qemu: fatal: "); |
1271 | qemu_log_vprintf(fmt, ap2); | |
1272 | qemu_log("\n"); | |
a0762859 | 1273 | log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
31b1a7b4 | 1274 | qemu_log_flush(); |
1ee73216 | 1275 | qemu_log_unlock(); |
93fcfe39 | 1276 | qemu_log_close(); |
924edcae | 1277 | } |
493ae1f0 | 1278 | va_end(ap2); |
f9373291 | 1279 | va_end(ap); |
7615936e | 1280 | replay_finish(); |
fd052bf6 RV |
1281 | #if defined(CONFIG_USER_ONLY) |
1282 | { | |
1283 | struct sigaction act; | |
1284 | sigfillset(&act.sa_mask); | |
1285 | act.sa_handler = SIG_DFL; | |
8347c185 | 1286 | act.sa_flags = 0; |
fd052bf6 RV |
1287 | sigaction(SIGABRT, &act, NULL); |
1288 | } | |
1289 | #endif | |
7501267e FB |
1290 | abort(); |
1291 | } | |
1292 | ||
0124311e | 1293 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a | 1294 | /* Called from RCU critical section */ |
041603fe PB |
1295 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
1296 | { | |
1297 | RAMBlock *block; | |
1298 | ||
43771539 | 1299 | block = atomic_rcu_read(&ram_list.mru_block); |
9b8424d5 | 1300 | if (block && addr - block->offset < block->max_length) { |
68851b98 | 1301 | return block; |
041603fe | 1302 | } |
99e15582 | 1303 | RAMBLOCK_FOREACH(block) { |
9b8424d5 | 1304 | if (addr - block->offset < block->max_length) { |
041603fe PB |
1305 | goto found; |
1306 | } | |
1307 | } | |
1308 | ||
1309 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1310 | abort(); | |
1311 | ||
1312 | found: | |
43771539 PB |
1313 | /* It is safe to write mru_block outside the iothread lock. This |
1314 | * is what happens: | |
1315 | * | |
1316 | * mru_block = xxx | |
1317 | * rcu_read_unlock() | |
1318 | * xxx removed from list | |
1319 | * rcu_read_lock() | |
1320 | * read mru_block | |
1321 | * mru_block = NULL; | |
1322 | * call_rcu(reclaim_ramblock, xxx); | |
1323 | * rcu_read_unlock() | |
1324 | * | |
1325 | * atomic_rcu_set is not needed here. The block was already published | |
1326 | * when it was placed into the list. Here we're just making an extra | |
1327 | * copy of the pointer. | |
1328 | */ | |
041603fe PB |
1329 | ram_list.mru_block = block; |
1330 | return block; | |
1331 | } | |
1332 | ||
a2f4d5be | 1333 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) |
d24981d3 | 1334 | { |
9a13565d | 1335 | CPUState *cpu; |
041603fe | 1336 | ram_addr_t start1; |
a2f4d5be JQ |
1337 | RAMBlock *block; |
1338 | ram_addr_t end; | |
1339 | ||
f28d0dfd | 1340 | assert(tcg_enabled()); |
a2f4d5be JQ |
1341 | end = TARGET_PAGE_ALIGN(start + length); |
1342 | start &= TARGET_PAGE_MASK; | |
d24981d3 | 1343 | |
0dc3f44a | 1344 | rcu_read_lock(); |
041603fe PB |
1345 | block = qemu_get_ram_block(start); |
1346 | assert(block == qemu_get_ram_block(end - 1)); | |
1240be24 | 1347 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); |
9a13565d PC |
1348 | CPU_FOREACH(cpu) { |
1349 | tlb_reset_dirty(cpu, start1, length); | |
1350 | } | |
0dc3f44a | 1351 | rcu_read_unlock(); |
d24981d3 JQ |
1352 | } |
1353 | ||
5579c7f3 | 1354 | /* Note: start and end must be within the same ram block. */ |
03eebc9e SH |
1355 | bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, |
1356 | ram_addr_t length, | |
1357 | unsigned client) | |
1ccde1cb | 1358 | { |
5b82b703 | 1359 | DirtyMemoryBlocks *blocks; |
03eebc9e | 1360 | unsigned long end, page; |
5b82b703 | 1361 | bool dirty = false; |
077874e0 PX |
1362 | RAMBlock *ramblock; |
1363 | uint64_t mr_offset, mr_size; | |
03eebc9e SH |
1364 | |
1365 | if (length == 0) { | |
1366 | return false; | |
1367 | } | |
f23db169 | 1368 | |
03eebc9e SH |
1369 | end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; |
1370 | page = start >> TARGET_PAGE_BITS; | |
5b82b703 SH |
1371 | |
1372 | rcu_read_lock(); | |
1373 | ||
1374 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
077874e0 PX |
1375 | ramblock = qemu_get_ram_block(start); |
1376 | /* Range sanity check on the ramblock */ | |
1377 | assert(start >= ramblock->offset && | |
1378 | start + length <= ramblock->offset + ramblock->used_length); | |
5b82b703 SH |
1379 | |
1380 | while (page < end) { | |
1381 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1382 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1383 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1384 | ||
1385 | dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx], | |
1386 | offset, num); | |
1387 | page += num; | |
1388 | } | |
1389 | ||
077874e0 PX |
1390 | mr_offset = (ram_addr_t)(page << TARGET_PAGE_BITS) - ramblock->offset; |
1391 | mr_size = (end - page) << TARGET_PAGE_BITS; | |
1392 | memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size); | |
1393 | ||
5b82b703 | 1394 | rcu_read_unlock(); |
03eebc9e SH |
1395 | |
1396 | if (dirty && tcg_enabled()) { | |
a2f4d5be | 1397 | tlb_reset_dirty_range_all(start, length); |
5579c7f3 | 1398 | } |
03eebc9e SH |
1399 | |
1400 | return dirty; | |
1ccde1cb FB |
1401 | } |
1402 | ||
8deaf12c | 1403 | DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty |
5dea4079 | 1404 | (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client) |
8deaf12c GH |
1405 | { |
1406 | DirtyMemoryBlocks *blocks; | |
5dea4079 | 1407 | ram_addr_t start = memory_region_get_ram_addr(mr) + offset; |
8deaf12c GH |
1408 | unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL); |
1409 | ram_addr_t first = QEMU_ALIGN_DOWN(start, align); | |
1410 | ram_addr_t last = QEMU_ALIGN_UP(start + length, align); | |
1411 | DirtyBitmapSnapshot *snap; | |
1412 | unsigned long page, end, dest; | |
1413 | ||
1414 | snap = g_malloc0(sizeof(*snap) + | |
1415 | ((last - first) >> (TARGET_PAGE_BITS + 3))); | |
1416 | snap->start = first; | |
1417 | snap->end = last; | |
1418 | ||
1419 | page = first >> TARGET_PAGE_BITS; | |
1420 | end = last >> TARGET_PAGE_BITS; | |
1421 | dest = 0; | |
1422 | ||
1423 | rcu_read_lock(); | |
1424 | ||
1425 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1426 | ||
1427 | while (page < end) { | |
1428 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1429 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1430 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1431 | ||
1432 | assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL))); | |
1433 | assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL))); | |
1434 | offset >>= BITS_PER_LEVEL; | |
1435 | ||
1436 | bitmap_copy_and_clear_atomic(snap->dirty + dest, | |
1437 | blocks->blocks[idx] + offset, | |
1438 | num); | |
1439 | page += num; | |
1440 | dest += num >> BITS_PER_LEVEL; | |
1441 | } | |
1442 | ||
1443 | rcu_read_unlock(); | |
1444 | ||
1445 | if (tcg_enabled()) { | |
1446 | tlb_reset_dirty_range_all(start, length); | |
1447 | } | |
1448 | ||
077874e0 PX |
1449 | memory_region_clear_dirty_bitmap(mr, offset, length); |
1450 | ||
8deaf12c GH |
1451 | return snap; |
1452 | } | |
1453 | ||
1454 | bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, | |
1455 | ram_addr_t start, | |
1456 | ram_addr_t length) | |
1457 | { | |
1458 | unsigned long page, end; | |
1459 | ||
1460 | assert(start >= snap->start); | |
1461 | assert(start + length <= snap->end); | |
1462 | ||
1463 | end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS; | |
1464 | page = (start - snap->start) >> TARGET_PAGE_BITS; | |
1465 | ||
1466 | while (page < end) { | |
1467 | if (test_bit(page, snap->dirty)) { | |
1468 | return true; | |
1469 | } | |
1470 | page++; | |
1471 | } | |
1472 | return false; | |
1473 | } | |
1474 | ||
79e2b9ae | 1475 | /* Called from RCU critical section */ |
bb0e627a | 1476 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
149f54b5 PB |
1477 | MemoryRegionSection *section, |
1478 | target_ulong vaddr, | |
1479 | hwaddr paddr, hwaddr xlat, | |
1480 | int prot, | |
1481 | target_ulong *address) | |
e5548617 | 1482 | { |
a8170e5e | 1483 | hwaddr iotlb; |
e5548617 BS |
1484 | CPUWatchpoint *wp; |
1485 | ||
cc5bea60 | 1486 | if (memory_region_is_ram(section->mr)) { |
e5548617 | 1487 | /* Normal RAM. */ |
e4e69794 | 1488 | iotlb = memory_region_get_ram_addr(section->mr) + xlat; |
e5548617 | 1489 | if (!section->readonly) { |
b41aac4f | 1490 | iotlb |= PHYS_SECTION_NOTDIRTY; |
e5548617 | 1491 | } else { |
b41aac4f | 1492 | iotlb |= PHYS_SECTION_ROM; |
e5548617 BS |
1493 | } |
1494 | } else { | |
0b8e2c10 PM |
1495 | AddressSpaceDispatch *d; |
1496 | ||
16620684 | 1497 | d = flatview_to_dispatch(section->fv); |
0b8e2c10 | 1498 | iotlb = section - d->map.sections; |
149f54b5 | 1499 | iotlb += xlat; |
e5548617 BS |
1500 | } |
1501 | ||
1502 | /* Make accesses to pages with watchpoints go via the | |
1503 | watchpoint trap routines. */ | |
ff4700b0 | 1504 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 1505 | if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { |
e5548617 BS |
1506 | /* Avoid trapping reads of pages with a write breakpoint. */ |
1507 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
b41aac4f | 1508 | iotlb = PHYS_SECTION_WATCH + paddr; |
e5548617 BS |
1509 | *address |= TLB_MMIO; |
1510 | break; | |
1511 | } | |
1512 | } | |
1513 | } | |
1514 | ||
1515 | return iotlb; | |
1516 | } | |
9fa3e853 FB |
1517 | #endif /* defined(CONFIG_USER_ONLY) */ |
1518 | ||
e2eef170 | 1519 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 1520 | |
c227f099 | 1521 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 1522 | uint16_t section); |
16620684 | 1523 | static subpage_t *subpage_init(FlatView *fv, hwaddr base); |
54688b1e | 1524 | |
06329cce | 1525 | static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) = |
a2b257d6 | 1526 | qemu_anon_ram_alloc; |
91138037 MA |
1527 | |
1528 | /* | |
1529 | * Set a custom physical guest memory alloator. | |
1530 | * Accelerators with unusual needs may need this. Hopefully, we can | |
1531 | * get rid of it eventually. | |
1532 | */ | |
06329cce | 1533 | void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared)) |
91138037 MA |
1534 | { |
1535 | phys_mem_alloc = alloc; | |
1536 | } | |
1537 | ||
53cb28cb MA |
1538 | static uint16_t phys_section_add(PhysPageMap *map, |
1539 | MemoryRegionSection *section) | |
5312bd8b | 1540 | { |
68f3f65b PB |
1541 | /* The physical section number is ORed with a page-aligned |
1542 | * pointer to produce the iotlb entries. Thus it should | |
1543 | * never overflow into the page-aligned value. | |
1544 | */ | |
53cb28cb | 1545 | assert(map->sections_nb < TARGET_PAGE_SIZE); |
68f3f65b | 1546 | |
53cb28cb MA |
1547 | if (map->sections_nb == map->sections_nb_alloc) { |
1548 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
1549 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
1550 | map->sections_nb_alloc); | |
5312bd8b | 1551 | } |
53cb28cb | 1552 | map->sections[map->sections_nb] = *section; |
dfde4e6e | 1553 | memory_region_ref(section->mr); |
53cb28cb | 1554 | return map->sections_nb++; |
5312bd8b AK |
1555 | } |
1556 | ||
058bc4b5 PB |
1557 | static void phys_section_destroy(MemoryRegion *mr) |
1558 | { | |
55b4e80b DS |
1559 | bool have_sub_page = mr->subpage; |
1560 | ||
dfde4e6e PB |
1561 | memory_region_unref(mr); |
1562 | ||
55b4e80b | 1563 | if (have_sub_page) { |
058bc4b5 | 1564 | subpage_t *subpage = container_of(mr, subpage_t, iomem); |
b4fefef9 | 1565 | object_unref(OBJECT(&subpage->iomem)); |
058bc4b5 PB |
1566 | g_free(subpage); |
1567 | } | |
1568 | } | |
1569 | ||
6092666e | 1570 | static void phys_sections_free(PhysPageMap *map) |
5312bd8b | 1571 | { |
9affd6fc PB |
1572 | while (map->sections_nb > 0) { |
1573 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
058bc4b5 PB |
1574 | phys_section_destroy(section->mr); |
1575 | } | |
9affd6fc PB |
1576 | g_free(map->sections); |
1577 | g_free(map->nodes); | |
5312bd8b AK |
1578 | } |
1579 | ||
9950322a | 1580 | static void register_subpage(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1581 | { |
9950322a | 1582 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
0f0cb164 | 1583 | subpage_t *subpage; |
a8170e5e | 1584 | hwaddr base = section->offset_within_address_space |
0f0cb164 | 1585 | & TARGET_PAGE_MASK; |
003a0cf2 | 1586 | MemoryRegionSection *existing = phys_page_find(d, base); |
0f0cb164 AK |
1587 | MemoryRegionSection subsection = { |
1588 | .offset_within_address_space = base, | |
052e87b0 | 1589 | .size = int128_make64(TARGET_PAGE_SIZE), |
0f0cb164 | 1590 | }; |
a8170e5e | 1591 | hwaddr start, end; |
0f0cb164 | 1592 | |
f3705d53 | 1593 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
0f0cb164 | 1594 | |
f3705d53 | 1595 | if (!(existing->mr->subpage)) { |
16620684 AK |
1596 | subpage = subpage_init(fv, base); |
1597 | subsection.fv = fv; | |
0f0cb164 | 1598 | subsection.mr = &subpage->iomem; |
ac1970fb | 1599 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
53cb28cb | 1600 | phys_section_add(&d->map, &subsection)); |
0f0cb164 | 1601 | } else { |
f3705d53 | 1602 | subpage = container_of(existing->mr, subpage_t, iomem); |
0f0cb164 AK |
1603 | } |
1604 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
052e87b0 | 1605 | end = start + int128_get64(section->size) - 1; |
53cb28cb MA |
1606 | subpage_register(subpage, start, end, |
1607 | phys_section_add(&d->map, section)); | |
0f0cb164 AK |
1608 | } |
1609 | ||
1610 | ||
9950322a | 1611 | static void register_multipage(FlatView *fv, |
052e87b0 | 1612 | MemoryRegionSection *section) |
33417e70 | 1613 | { |
9950322a | 1614 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
a8170e5e | 1615 | hwaddr start_addr = section->offset_within_address_space; |
53cb28cb | 1616 | uint16_t section_index = phys_section_add(&d->map, section); |
052e87b0 PB |
1617 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
1618 | TARGET_PAGE_BITS)); | |
dd81124b | 1619 | |
733d5ef5 PB |
1620 | assert(num_pages); |
1621 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
33417e70 FB |
1622 | } |
1623 | ||
494d1997 WY |
1624 | /* |
1625 | * The range in *section* may look like this: | |
1626 | * | |
1627 | * |s|PPPPPPP|s| | |
1628 | * | |
1629 | * where s stands for subpage and P for page. | |
1630 | */ | |
8629d3fc | 1631 | void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1632 | { |
494d1997 | 1633 | MemoryRegionSection remain = *section; |
052e87b0 | 1634 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
0f0cb164 | 1635 | |
494d1997 WY |
1636 | /* register first subpage */ |
1637 | if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { | |
1638 | uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space) | |
1639 | - remain.offset_within_address_space; | |
733d5ef5 | 1640 | |
494d1997 | 1641 | MemoryRegionSection now = remain; |
052e87b0 | 1642 | now.size = int128_min(int128_make64(left), now.size); |
9950322a | 1643 | register_subpage(fv, &now); |
494d1997 WY |
1644 | if (int128_eq(remain.size, now.size)) { |
1645 | return; | |
1646 | } | |
052e87b0 PB |
1647 | remain.size = int128_sub(remain.size, now.size); |
1648 | remain.offset_within_address_space += int128_get64(now.size); | |
1649 | remain.offset_within_region += int128_get64(now.size); | |
494d1997 WY |
1650 | } |
1651 | ||
1652 | /* register whole pages */ | |
1653 | if (int128_ge(remain.size, page_size)) { | |
1654 | MemoryRegionSection now = remain; | |
1655 | now.size = int128_and(now.size, int128_neg(page_size)); | |
1656 | register_multipage(fv, &now); | |
1657 | if (int128_eq(remain.size, now.size)) { | |
1658 | return; | |
69b67646 | 1659 | } |
494d1997 WY |
1660 | remain.size = int128_sub(remain.size, now.size); |
1661 | remain.offset_within_address_space += int128_get64(now.size); | |
1662 | remain.offset_within_region += int128_get64(now.size); | |
0f0cb164 | 1663 | } |
494d1997 WY |
1664 | |
1665 | /* register last subpage */ | |
1666 | register_subpage(fv, &remain); | |
0f0cb164 AK |
1667 | } |
1668 | ||
62a2744c SY |
1669 | void qemu_flush_coalesced_mmio_buffer(void) |
1670 | { | |
1671 | if (kvm_enabled()) | |
1672 | kvm_flush_coalesced_mmio_buffer(); | |
1673 | } | |
1674 | ||
b2a8658e UD |
1675 | void qemu_mutex_lock_ramlist(void) |
1676 | { | |
1677 | qemu_mutex_lock(&ram_list.mutex); | |
1678 | } | |
1679 | ||
1680 | void qemu_mutex_unlock_ramlist(void) | |
1681 | { | |
1682 | qemu_mutex_unlock(&ram_list.mutex); | |
1683 | } | |
1684 | ||
be9b23c4 PX |
1685 | void ram_block_dump(Monitor *mon) |
1686 | { | |
1687 | RAMBlock *block; | |
1688 | char *psize; | |
1689 | ||
1690 | rcu_read_lock(); | |
1691 | monitor_printf(mon, "%24s %8s %18s %18s %18s\n", | |
1692 | "Block Name", "PSize", "Offset", "Used", "Total"); | |
1693 | RAMBLOCK_FOREACH(block) { | |
1694 | psize = size_to_str(block->page_size); | |
1695 | monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64 | |
1696 | " 0x%016" PRIx64 "\n", block->idstr, psize, | |
1697 | (uint64_t)block->offset, | |
1698 | (uint64_t)block->used_length, | |
1699 | (uint64_t)block->max_length); | |
1700 | g_free(psize); | |
1701 | } | |
1702 | rcu_read_unlock(); | |
1703 | } | |
1704 | ||
9c607668 AK |
1705 | #ifdef __linux__ |
1706 | /* | |
1707 | * FIXME TOCTTOU: this iterates over memory backends' mem-path, which | |
1708 | * may or may not name the same files / on the same filesystem now as | |
1709 | * when we actually open and map them. Iterate over the file | |
1710 | * descriptors instead, and use qemu_fd_getpagesize(). | |
1711 | */ | |
905b7ee4 | 1712 | static int find_min_backend_pagesize(Object *obj, void *opaque) |
9c607668 | 1713 | { |
9c607668 AK |
1714 | long *hpsize_min = opaque; |
1715 | ||
1716 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
7d5489e6 DG |
1717 | HostMemoryBackend *backend = MEMORY_BACKEND(obj); |
1718 | long hpsize = host_memory_backend_pagesize(backend); | |
2b108085 | 1719 | |
7d5489e6 | 1720 | if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) { |
0de6e2a3 | 1721 | *hpsize_min = hpsize; |
9c607668 AK |
1722 | } |
1723 | } | |
1724 | ||
1725 | return 0; | |
1726 | } | |
1727 | ||
905b7ee4 DH |
1728 | static int find_max_backend_pagesize(Object *obj, void *opaque) |
1729 | { | |
1730 | long *hpsize_max = opaque; | |
1731 | ||
1732 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
1733 | HostMemoryBackend *backend = MEMORY_BACKEND(obj); | |
1734 | long hpsize = host_memory_backend_pagesize(backend); | |
1735 | ||
1736 | if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) { | |
1737 | *hpsize_max = hpsize; | |
1738 | } | |
1739 | } | |
1740 | ||
1741 | return 0; | |
1742 | } | |
1743 | ||
1744 | /* | |
1745 | * TODO: We assume right now that all mapped host memory backends are | |
1746 | * used as RAM, however some might be used for different purposes. | |
1747 | */ | |
1748 | long qemu_minrampagesize(void) | |
9c607668 AK |
1749 | { |
1750 | long hpsize = LONG_MAX; | |
1751 | long mainrampagesize; | |
1752 | Object *memdev_root; | |
1753 | ||
0de6e2a3 | 1754 | mainrampagesize = qemu_mempath_getpagesize(mem_path); |
9c607668 AK |
1755 | |
1756 | /* it's possible we have memory-backend objects with | |
1757 | * hugepage-backed RAM. these may get mapped into system | |
1758 | * address space via -numa parameters or memory hotplug | |
1759 | * hooks. we want to take these into account, but we | |
1760 | * also want to make sure these supported hugepage | |
1761 | * sizes are applicable across the entire range of memory | |
1762 | * we may boot from, so we take the min across all | |
1763 | * backends, and assume normal pages in cases where a | |
1764 | * backend isn't backed by hugepages. | |
1765 | */ | |
1766 | memdev_root = object_resolve_path("/objects", NULL); | |
1767 | if (memdev_root) { | |
905b7ee4 | 1768 | object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize); |
9c607668 AK |
1769 | } |
1770 | if (hpsize == LONG_MAX) { | |
1771 | /* No additional memory regions found ==> Report main RAM page size */ | |
1772 | return mainrampagesize; | |
1773 | } | |
1774 | ||
1775 | /* If NUMA is disabled or the NUMA nodes are not backed with a | |
1776 | * memory-backend, then there is at least one node using "normal" RAM, | |
1777 | * so if its page size is smaller we have got to report that size instead. | |
1778 | */ | |
1779 | if (hpsize > mainrampagesize && | |
1780 | (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) { | |
1781 | static bool warned; | |
1782 | if (!warned) { | |
1783 | error_report("Huge page support disabled (n/a for main memory)."); | |
1784 | warned = true; | |
1785 | } | |
1786 | return mainrampagesize; | |
1787 | } | |
1788 | ||
1789 | return hpsize; | |
1790 | } | |
905b7ee4 DH |
1791 | |
1792 | long qemu_maxrampagesize(void) | |
1793 | { | |
1794 | long pagesize = qemu_mempath_getpagesize(mem_path); | |
1795 | Object *memdev_root = object_resolve_path("/objects", NULL); | |
1796 | ||
1797 | if (memdev_root) { | |
1798 | object_child_foreach(memdev_root, find_max_backend_pagesize, | |
1799 | &pagesize); | |
1800 | } | |
1801 | return pagesize; | |
1802 | } | |
9c607668 | 1803 | #else |
905b7ee4 DH |
1804 | long qemu_minrampagesize(void) |
1805 | { | |
1806 | return getpagesize(); | |
1807 | } | |
1808 | long qemu_maxrampagesize(void) | |
9c607668 AK |
1809 | { |
1810 | return getpagesize(); | |
1811 | } | |
1812 | #endif | |
1813 | ||
d5dbde46 | 1814 | #ifdef CONFIG_POSIX |
d6af99c9 HZ |
1815 | static int64_t get_file_size(int fd) |
1816 | { | |
1817 | int64_t size = lseek(fd, 0, SEEK_END); | |
1818 | if (size < 0) { | |
1819 | return -errno; | |
1820 | } | |
1821 | return size; | |
1822 | } | |
1823 | ||
8d37b030 MAL |
1824 | static int file_ram_open(const char *path, |
1825 | const char *region_name, | |
1826 | bool *created, | |
1827 | Error **errp) | |
c902760f MT |
1828 | { |
1829 | char *filename; | |
8ca761f6 PF |
1830 | char *sanitized_name; |
1831 | char *c; | |
5c3ece79 | 1832 | int fd = -1; |
c902760f | 1833 | |
8d37b030 | 1834 | *created = false; |
fd97fd44 MA |
1835 | for (;;) { |
1836 | fd = open(path, O_RDWR); | |
1837 | if (fd >= 0) { | |
1838 | /* @path names an existing file, use it */ | |
1839 | break; | |
8d31d6b6 | 1840 | } |
fd97fd44 MA |
1841 | if (errno == ENOENT) { |
1842 | /* @path names a file that doesn't exist, create it */ | |
1843 | fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644); | |
1844 | if (fd >= 0) { | |
8d37b030 | 1845 | *created = true; |
fd97fd44 MA |
1846 | break; |
1847 | } | |
1848 | } else if (errno == EISDIR) { | |
1849 | /* @path names a directory, create a file there */ | |
1850 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ | |
8d37b030 | 1851 | sanitized_name = g_strdup(region_name); |
fd97fd44 MA |
1852 | for (c = sanitized_name; *c != '\0'; c++) { |
1853 | if (*c == '/') { | |
1854 | *c = '_'; | |
1855 | } | |
1856 | } | |
8ca761f6 | 1857 | |
fd97fd44 MA |
1858 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, |
1859 | sanitized_name); | |
1860 | g_free(sanitized_name); | |
8d31d6b6 | 1861 | |
fd97fd44 MA |
1862 | fd = mkstemp(filename); |
1863 | if (fd >= 0) { | |
1864 | unlink(filename); | |
1865 | g_free(filename); | |
1866 | break; | |
1867 | } | |
1868 | g_free(filename); | |
8d31d6b6 | 1869 | } |
fd97fd44 MA |
1870 | if (errno != EEXIST && errno != EINTR) { |
1871 | error_setg_errno(errp, errno, | |
1872 | "can't open backing store %s for guest RAM", | |
1873 | path); | |
8d37b030 | 1874 | return -1; |
fd97fd44 MA |
1875 | } |
1876 | /* | |
1877 | * Try again on EINTR and EEXIST. The latter happens when | |
1878 | * something else creates the file between our two open(). | |
1879 | */ | |
8d31d6b6 | 1880 | } |
c902760f | 1881 | |
8d37b030 MAL |
1882 | return fd; |
1883 | } | |
1884 | ||
1885 | static void *file_ram_alloc(RAMBlock *block, | |
1886 | ram_addr_t memory, | |
1887 | int fd, | |
1888 | bool truncate, | |
1889 | Error **errp) | |
1890 | { | |
5cc8767d | 1891 | MachineState *ms = MACHINE(qdev_get_machine()); |
8d37b030 MAL |
1892 | void *area; |
1893 | ||
863e9621 | 1894 | block->page_size = qemu_fd_getpagesize(fd); |
98376843 HZ |
1895 | if (block->mr->align % block->page_size) { |
1896 | error_setg(errp, "alignment 0x%" PRIx64 | |
1897 | " must be multiples of page size 0x%zx", | |
1898 | block->mr->align, block->page_size); | |
1899 | return NULL; | |
61362b71 DH |
1900 | } else if (block->mr->align && !is_power_of_2(block->mr->align)) { |
1901 | error_setg(errp, "alignment 0x%" PRIx64 | |
1902 | " must be a power of two", block->mr->align); | |
1903 | return NULL; | |
98376843 HZ |
1904 | } |
1905 | block->mr->align = MAX(block->page_size, block->mr->align); | |
8360668e HZ |
1906 | #if defined(__s390x__) |
1907 | if (kvm_enabled()) { | |
1908 | block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN); | |
1909 | } | |
1910 | #endif | |
fd97fd44 | 1911 | |
863e9621 | 1912 | if (memory < block->page_size) { |
fd97fd44 | 1913 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " |
863e9621 DDAG |
1914 | "or larger than page size 0x%zx", |
1915 | memory, block->page_size); | |
8d37b030 | 1916 | return NULL; |
1775f111 HZ |
1917 | } |
1918 | ||
863e9621 | 1919 | memory = ROUND_UP(memory, block->page_size); |
c902760f MT |
1920 | |
1921 | /* | |
1922 | * ftruncate is not supported by hugetlbfs in older | |
1923 | * hosts, so don't bother bailing out on errors. | |
1924 | * If anything goes wrong with it under other filesystems, | |
1925 | * mmap will fail. | |
d6af99c9 HZ |
1926 | * |
1927 | * Do not truncate the non-empty backend file to avoid corrupting | |
1928 | * the existing data in the file. Disabling shrinking is not | |
1929 | * enough. For example, the current vNVDIMM implementation stores | |
1930 | * the guest NVDIMM labels at the end of the backend file. If the | |
1931 | * backend file is later extended, QEMU will not be able to find | |
1932 | * those labels. Therefore, extending the non-empty backend file | |
1933 | * is disabled as well. | |
c902760f | 1934 | */ |
8d37b030 | 1935 | if (truncate && ftruncate(fd, memory)) { |
9742bf26 | 1936 | perror("ftruncate"); |
7f56e740 | 1937 | } |
c902760f | 1938 | |
d2f39add | 1939 | area = qemu_ram_mmap(fd, memory, block->mr->align, |
2ac0f162 | 1940 | block->flags & RAM_SHARED, block->flags & RAM_PMEM); |
c902760f | 1941 | if (area == MAP_FAILED) { |
7f56e740 | 1942 | error_setg_errno(errp, errno, |
fd97fd44 | 1943 | "unable to map backing store for guest RAM"); |
8d37b030 | 1944 | return NULL; |
c902760f | 1945 | } |
ef36fa14 MT |
1946 | |
1947 | if (mem_prealloc) { | |
5cc8767d | 1948 | os_mem_prealloc(fd, area, memory, ms->smp.cpus, errp); |
056b68af | 1949 | if (errp && *errp) { |
53adb9d4 | 1950 | qemu_ram_munmap(fd, area, memory); |
8d37b030 | 1951 | return NULL; |
056b68af | 1952 | } |
ef36fa14 MT |
1953 | } |
1954 | ||
04b16653 | 1955 | block->fd = fd; |
c902760f MT |
1956 | return area; |
1957 | } | |
1958 | #endif | |
1959 | ||
154cc9ea DDAG |
1960 | /* Allocate space within the ram_addr_t space that governs the |
1961 | * dirty bitmaps. | |
1962 | * Called with the ramlist lock held. | |
1963 | */ | |
d17b5288 | 1964 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
1965 | { |
1966 | RAMBlock *block, *next_block; | |
3e837b2c | 1967 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 | 1968 | |
49cd9ac6 SH |
1969 | assert(size != 0); /* it would hand out same offset multiple times */ |
1970 | ||
0dc3f44a | 1971 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { |
04b16653 | 1972 | return 0; |
0d53d9fe | 1973 | } |
04b16653 | 1974 | |
99e15582 | 1975 | RAMBLOCK_FOREACH(block) { |
154cc9ea | 1976 | ram_addr_t candidate, next = RAM_ADDR_MAX; |
04b16653 | 1977 | |
801110ab DDAG |
1978 | /* Align blocks to start on a 'long' in the bitmap |
1979 | * which makes the bitmap sync'ing take the fast path. | |
1980 | */ | |
154cc9ea | 1981 | candidate = block->offset + block->max_length; |
801110ab | 1982 | candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS); |
04b16653 | 1983 | |
154cc9ea DDAG |
1984 | /* Search for the closest following block |
1985 | * and find the gap. | |
1986 | */ | |
99e15582 | 1987 | RAMBLOCK_FOREACH(next_block) { |
154cc9ea | 1988 | if (next_block->offset >= candidate) { |
04b16653 AW |
1989 | next = MIN(next, next_block->offset); |
1990 | } | |
1991 | } | |
154cc9ea DDAG |
1992 | |
1993 | /* If it fits remember our place and remember the size | |
1994 | * of gap, but keep going so that we might find a smaller | |
1995 | * gap to fill so avoiding fragmentation. | |
1996 | */ | |
1997 | if (next - candidate >= size && next - candidate < mingap) { | |
1998 | offset = candidate; | |
1999 | mingap = next - candidate; | |
04b16653 | 2000 | } |
154cc9ea DDAG |
2001 | |
2002 | trace_find_ram_offset_loop(size, candidate, offset, next, mingap); | |
04b16653 | 2003 | } |
3e837b2c AW |
2004 | |
2005 | if (offset == RAM_ADDR_MAX) { | |
2006 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
2007 | (uint64_t)size); | |
2008 | abort(); | |
2009 | } | |
2010 | ||
154cc9ea DDAG |
2011 | trace_find_ram_offset(size, offset); |
2012 | ||
04b16653 AW |
2013 | return offset; |
2014 | } | |
2015 | ||
c136180c | 2016 | static unsigned long last_ram_page(void) |
d17b5288 AW |
2017 | { |
2018 | RAMBlock *block; | |
2019 | ram_addr_t last = 0; | |
2020 | ||
0dc3f44a | 2021 | rcu_read_lock(); |
99e15582 | 2022 | RAMBLOCK_FOREACH(block) { |
62be4e3a | 2023 | last = MAX(last, block->offset + block->max_length); |
0d53d9fe | 2024 | } |
0dc3f44a | 2025 | rcu_read_unlock(); |
b8c48993 | 2026 | return last >> TARGET_PAGE_BITS; |
d17b5288 AW |
2027 | } |
2028 | ||
ddb97f1d JB |
2029 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
2030 | { | |
2031 | int ret; | |
ddb97f1d JB |
2032 | |
2033 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
47c8ca53 | 2034 | if (!machine_dump_guest_core(current_machine)) { |
ddb97f1d JB |
2035 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
2036 | if (ret) { | |
2037 | perror("qemu_madvise"); | |
2038 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
2039 | "but dump_guest_core=off specified\n"); | |
2040 | } | |
2041 | } | |
2042 | } | |
2043 | ||
422148d3 DDAG |
2044 | const char *qemu_ram_get_idstr(RAMBlock *rb) |
2045 | { | |
2046 | return rb->idstr; | |
2047 | } | |
2048 | ||
754cb9c0 YK |
2049 | void *qemu_ram_get_host_addr(RAMBlock *rb) |
2050 | { | |
2051 | return rb->host; | |
2052 | } | |
2053 | ||
2054 | ram_addr_t qemu_ram_get_offset(RAMBlock *rb) | |
2055 | { | |
2056 | return rb->offset; | |
2057 | } | |
2058 | ||
2059 | ram_addr_t qemu_ram_get_used_length(RAMBlock *rb) | |
2060 | { | |
2061 | return rb->used_length; | |
2062 | } | |
2063 | ||
463a4ac2 DDAG |
2064 | bool qemu_ram_is_shared(RAMBlock *rb) |
2065 | { | |
2066 | return rb->flags & RAM_SHARED; | |
2067 | } | |
2068 | ||
2ce16640 DDAG |
2069 | /* Note: Only set at the start of postcopy */ |
2070 | bool qemu_ram_is_uf_zeroable(RAMBlock *rb) | |
2071 | { | |
2072 | return rb->flags & RAM_UF_ZEROPAGE; | |
2073 | } | |
2074 | ||
2075 | void qemu_ram_set_uf_zeroable(RAMBlock *rb) | |
2076 | { | |
2077 | rb->flags |= RAM_UF_ZEROPAGE; | |
2078 | } | |
2079 | ||
b895de50 CLG |
2080 | bool qemu_ram_is_migratable(RAMBlock *rb) |
2081 | { | |
2082 | return rb->flags & RAM_MIGRATABLE; | |
2083 | } | |
2084 | ||
2085 | void qemu_ram_set_migratable(RAMBlock *rb) | |
2086 | { | |
2087 | rb->flags |= RAM_MIGRATABLE; | |
2088 | } | |
2089 | ||
2090 | void qemu_ram_unset_migratable(RAMBlock *rb) | |
2091 | { | |
2092 | rb->flags &= ~RAM_MIGRATABLE; | |
2093 | } | |
2094 | ||
ae3a7047 | 2095 | /* Called with iothread lock held. */ |
fa53a0e5 | 2096 | void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev) |
20cfe881 | 2097 | { |
fa53a0e5 | 2098 | RAMBlock *block; |
20cfe881 | 2099 | |
c5705a77 AK |
2100 | assert(new_block); |
2101 | assert(!new_block->idstr[0]); | |
84b89d78 | 2102 | |
09e5ab63 AL |
2103 | if (dev) { |
2104 | char *id = qdev_get_dev_path(dev); | |
84b89d78 CM |
2105 | if (id) { |
2106 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 2107 | g_free(id); |
84b89d78 CM |
2108 | } |
2109 | } | |
2110 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
2111 | ||
ab0a9956 | 2112 | rcu_read_lock(); |
99e15582 | 2113 | RAMBLOCK_FOREACH(block) { |
fa53a0e5 GA |
2114 | if (block != new_block && |
2115 | !strcmp(block->idstr, new_block->idstr)) { | |
84b89d78 CM |
2116 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
2117 | new_block->idstr); | |
2118 | abort(); | |
2119 | } | |
2120 | } | |
0dc3f44a | 2121 | rcu_read_unlock(); |
c5705a77 AK |
2122 | } |
2123 | ||
ae3a7047 | 2124 | /* Called with iothread lock held. */ |
fa53a0e5 | 2125 | void qemu_ram_unset_idstr(RAMBlock *block) |
20cfe881 | 2126 | { |
ae3a7047 MD |
2127 | /* FIXME: arch_init.c assumes that this is not called throughout |
2128 | * migration. Ignore the problem since hot-unplug during migration | |
2129 | * does not work anyway. | |
2130 | */ | |
20cfe881 HT |
2131 | if (block) { |
2132 | memset(block->idstr, 0, sizeof(block->idstr)); | |
2133 | } | |
2134 | } | |
2135 | ||
863e9621 DDAG |
2136 | size_t qemu_ram_pagesize(RAMBlock *rb) |
2137 | { | |
2138 | return rb->page_size; | |
2139 | } | |
2140 | ||
67f11b5c DDAG |
2141 | /* Returns the largest size of page in use */ |
2142 | size_t qemu_ram_pagesize_largest(void) | |
2143 | { | |
2144 | RAMBlock *block; | |
2145 | size_t largest = 0; | |
2146 | ||
99e15582 | 2147 | RAMBLOCK_FOREACH(block) { |
67f11b5c DDAG |
2148 | largest = MAX(largest, qemu_ram_pagesize(block)); |
2149 | } | |
2150 | ||
2151 | return largest; | |
2152 | } | |
2153 | ||
8490fc78 LC |
2154 | static int memory_try_enable_merging(void *addr, size_t len) |
2155 | { | |
75cc7f01 | 2156 | if (!machine_mem_merge(current_machine)) { |
8490fc78 LC |
2157 | /* disabled by the user */ |
2158 | return 0; | |
2159 | } | |
2160 | ||
2161 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
2162 | } | |
2163 | ||
62be4e3a MT |
2164 | /* Only legal before guest might have detected the memory size: e.g. on |
2165 | * incoming migration, or right after reset. | |
2166 | * | |
2167 | * As memory core doesn't know how is memory accessed, it is up to | |
2168 | * resize callback to update device state and/or add assertions to detect | |
2169 | * misuse, if necessary. | |
2170 | */ | |
fa53a0e5 | 2171 | int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) |
62be4e3a | 2172 | { |
62be4e3a MT |
2173 | assert(block); |
2174 | ||
4ed023ce | 2175 | newsize = HOST_PAGE_ALIGN(newsize); |
129ddaf3 | 2176 | |
62be4e3a MT |
2177 | if (block->used_length == newsize) { |
2178 | return 0; | |
2179 | } | |
2180 | ||
2181 | if (!(block->flags & RAM_RESIZEABLE)) { | |
2182 | error_setg_errno(errp, EINVAL, | |
2183 | "Length mismatch: %s: 0x" RAM_ADDR_FMT | |
2184 | " in != 0x" RAM_ADDR_FMT, block->idstr, | |
2185 | newsize, block->used_length); | |
2186 | return -EINVAL; | |
2187 | } | |
2188 | ||
2189 | if (block->max_length < newsize) { | |
2190 | error_setg_errno(errp, EINVAL, | |
2191 | "Length too large: %s: 0x" RAM_ADDR_FMT | |
2192 | " > 0x" RAM_ADDR_FMT, block->idstr, | |
2193 | newsize, block->max_length); | |
2194 | return -EINVAL; | |
2195 | } | |
2196 | ||
2197 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); | |
2198 | block->used_length = newsize; | |
58d2707e PB |
2199 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length, |
2200 | DIRTY_CLIENTS_ALL); | |
62be4e3a MT |
2201 | memory_region_set_size(block->mr, newsize); |
2202 | if (block->resized) { | |
2203 | block->resized(block->idstr, newsize, block->host); | |
2204 | } | |
2205 | return 0; | |
2206 | } | |
2207 | ||
5b82b703 SH |
2208 | /* Called with ram_list.mutex held */ |
2209 | static void dirty_memory_extend(ram_addr_t old_ram_size, | |
2210 | ram_addr_t new_ram_size) | |
2211 | { | |
2212 | ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size, | |
2213 | DIRTY_MEMORY_BLOCK_SIZE); | |
2214 | ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size, | |
2215 | DIRTY_MEMORY_BLOCK_SIZE); | |
2216 | int i; | |
2217 | ||
2218 | /* Only need to extend if block count increased */ | |
2219 | if (new_num_blocks <= old_num_blocks) { | |
2220 | return; | |
2221 | } | |
2222 | ||
2223 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { | |
2224 | DirtyMemoryBlocks *old_blocks; | |
2225 | DirtyMemoryBlocks *new_blocks; | |
2226 | int j; | |
2227 | ||
2228 | old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]); | |
2229 | new_blocks = g_malloc(sizeof(*new_blocks) + | |
2230 | sizeof(new_blocks->blocks[0]) * new_num_blocks); | |
2231 | ||
2232 | if (old_num_blocks) { | |
2233 | memcpy(new_blocks->blocks, old_blocks->blocks, | |
2234 | old_num_blocks * sizeof(old_blocks->blocks[0])); | |
2235 | } | |
2236 | ||
2237 | for (j = old_num_blocks; j < new_num_blocks; j++) { | |
2238 | new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE); | |
2239 | } | |
2240 | ||
2241 | atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks); | |
2242 | ||
2243 | if (old_blocks) { | |
2244 | g_free_rcu(old_blocks, rcu); | |
2245 | } | |
2246 | } | |
2247 | } | |
2248 | ||
06329cce | 2249 | static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared) |
c5705a77 | 2250 | { |
e1c57ab8 | 2251 | RAMBlock *block; |
0d53d9fe | 2252 | RAMBlock *last_block = NULL; |
2152f5ca | 2253 | ram_addr_t old_ram_size, new_ram_size; |
37aa7a0e | 2254 | Error *err = NULL; |
2152f5ca | 2255 | |
b8c48993 | 2256 | old_ram_size = last_ram_page(); |
c5705a77 | 2257 | |
b2a8658e | 2258 | qemu_mutex_lock_ramlist(); |
9b8424d5 | 2259 | new_block->offset = find_ram_offset(new_block->max_length); |
e1c57ab8 PB |
2260 | |
2261 | if (!new_block->host) { | |
2262 | if (xen_enabled()) { | |
9b8424d5 | 2263 | xen_ram_alloc(new_block->offset, new_block->max_length, |
37aa7a0e MA |
2264 | new_block->mr, &err); |
2265 | if (err) { | |
2266 | error_propagate(errp, err); | |
2267 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 2268 | return; |
37aa7a0e | 2269 | } |
e1c57ab8 | 2270 | } else { |
9b8424d5 | 2271 | new_block->host = phys_mem_alloc(new_block->max_length, |
06329cce | 2272 | &new_block->mr->align, shared); |
39228250 | 2273 | if (!new_block->host) { |
ef701d7b HT |
2274 | error_setg_errno(errp, errno, |
2275 | "cannot set up guest memory '%s'", | |
2276 | memory_region_name(new_block->mr)); | |
2277 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 2278 | return; |
39228250 | 2279 | } |
9b8424d5 | 2280 | memory_try_enable_merging(new_block->host, new_block->max_length); |
6977dfe6 | 2281 | } |
c902760f | 2282 | } |
94a6b54f | 2283 | |
dd631697 LZ |
2284 | new_ram_size = MAX(old_ram_size, |
2285 | (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS); | |
2286 | if (new_ram_size > old_ram_size) { | |
5b82b703 | 2287 | dirty_memory_extend(old_ram_size, new_ram_size); |
dd631697 | 2288 | } |
0d53d9fe MD |
2289 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, |
2290 | * QLIST (which has an RCU-friendly variant) does not have insertion at | |
2291 | * tail, so save the last element in last_block. | |
2292 | */ | |
99e15582 | 2293 | RAMBLOCK_FOREACH(block) { |
0d53d9fe | 2294 | last_block = block; |
9b8424d5 | 2295 | if (block->max_length < new_block->max_length) { |
abb26d63 PB |
2296 | break; |
2297 | } | |
2298 | } | |
2299 | if (block) { | |
0dc3f44a | 2300 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); |
0d53d9fe | 2301 | } else if (last_block) { |
0dc3f44a | 2302 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); |
0d53d9fe | 2303 | } else { /* list is empty */ |
0dc3f44a | 2304 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); |
abb26d63 | 2305 | } |
0d6d3c87 | 2306 | ram_list.mru_block = NULL; |
94a6b54f | 2307 | |
0dc3f44a MD |
2308 | /* Write list before version */ |
2309 | smp_wmb(); | |
f798b07f | 2310 | ram_list.version++; |
b2a8658e | 2311 | qemu_mutex_unlock_ramlist(); |
f798b07f | 2312 | |
9b8424d5 | 2313 | cpu_physical_memory_set_dirty_range(new_block->offset, |
58d2707e PB |
2314 | new_block->used_length, |
2315 | DIRTY_CLIENTS_ALL); | |
94a6b54f | 2316 | |
a904c911 PB |
2317 | if (new_block->host) { |
2318 | qemu_ram_setup_dump(new_block->host, new_block->max_length); | |
2319 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); | |
c2cd627d | 2320 | /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */ |
a904c911 | 2321 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK); |
0987d735 | 2322 | ram_block_notify_add(new_block->host, new_block->max_length); |
e1c57ab8 | 2323 | } |
94a6b54f | 2324 | } |
e9a1ab19 | 2325 | |
d5dbde46 | 2326 | #ifdef CONFIG_POSIX |
38b3362d | 2327 | RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr, |
cbfc0171 | 2328 | uint32_t ram_flags, int fd, |
38b3362d | 2329 | Error **errp) |
e1c57ab8 PB |
2330 | { |
2331 | RAMBlock *new_block; | |
ef701d7b | 2332 | Error *local_err = NULL; |
8d37b030 | 2333 | int64_t file_size; |
e1c57ab8 | 2334 | |
a4de8552 JH |
2335 | /* Just support these ram flags by now. */ |
2336 | assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0); | |
2337 | ||
e1c57ab8 | 2338 | if (xen_enabled()) { |
7f56e740 | 2339 | error_setg(errp, "-mem-path not supported with Xen"); |
528f46af | 2340 | return NULL; |
e1c57ab8 PB |
2341 | } |
2342 | ||
e45e7ae2 MAL |
2343 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
2344 | error_setg(errp, | |
2345 | "host lacks kvm mmu notifiers, -mem-path unsupported"); | |
2346 | return NULL; | |
2347 | } | |
2348 | ||
e1c57ab8 PB |
2349 | if (phys_mem_alloc != qemu_anon_ram_alloc) { |
2350 | /* | |
2351 | * file_ram_alloc() needs to allocate just like | |
2352 | * phys_mem_alloc, but we haven't bothered to provide | |
2353 | * a hook there. | |
2354 | */ | |
7f56e740 PB |
2355 | error_setg(errp, |
2356 | "-mem-path not supported with this accelerator"); | |
528f46af | 2357 | return NULL; |
e1c57ab8 PB |
2358 | } |
2359 | ||
4ed023ce | 2360 | size = HOST_PAGE_ALIGN(size); |
8d37b030 MAL |
2361 | file_size = get_file_size(fd); |
2362 | if (file_size > 0 && file_size < size) { | |
2363 | error_setg(errp, "backing store %s size 0x%" PRIx64 | |
2364 | " does not match 'size' option 0x" RAM_ADDR_FMT, | |
2365 | mem_path, file_size, size); | |
8d37b030 MAL |
2366 | return NULL; |
2367 | } | |
2368 | ||
e1c57ab8 PB |
2369 | new_block = g_malloc0(sizeof(*new_block)); |
2370 | new_block->mr = mr; | |
9b8424d5 MT |
2371 | new_block->used_length = size; |
2372 | new_block->max_length = size; | |
cbfc0171 | 2373 | new_block->flags = ram_flags; |
8d37b030 | 2374 | new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp); |
7f56e740 PB |
2375 | if (!new_block->host) { |
2376 | g_free(new_block); | |
528f46af | 2377 | return NULL; |
7f56e740 PB |
2378 | } |
2379 | ||
cbfc0171 | 2380 | ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED); |
ef701d7b HT |
2381 | if (local_err) { |
2382 | g_free(new_block); | |
2383 | error_propagate(errp, local_err); | |
528f46af | 2384 | return NULL; |
ef701d7b | 2385 | } |
528f46af | 2386 | return new_block; |
38b3362d MAL |
2387 | |
2388 | } | |
2389 | ||
2390 | ||
2391 | RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, | |
cbfc0171 | 2392 | uint32_t ram_flags, const char *mem_path, |
38b3362d MAL |
2393 | Error **errp) |
2394 | { | |
2395 | int fd; | |
2396 | bool created; | |
2397 | RAMBlock *block; | |
2398 | ||
2399 | fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp); | |
2400 | if (fd < 0) { | |
2401 | return NULL; | |
2402 | } | |
2403 | ||
cbfc0171 | 2404 | block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, errp); |
38b3362d MAL |
2405 | if (!block) { |
2406 | if (created) { | |
2407 | unlink(mem_path); | |
2408 | } | |
2409 | close(fd); | |
2410 | return NULL; | |
2411 | } | |
2412 | ||
2413 | return block; | |
e1c57ab8 | 2414 | } |
0b183fc8 | 2415 | #endif |
e1c57ab8 | 2416 | |
62be4e3a | 2417 | static |
528f46af FZ |
2418 | RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, |
2419 | void (*resized)(const char*, | |
2420 | uint64_t length, | |
2421 | void *host), | |
06329cce | 2422 | void *host, bool resizeable, bool share, |
528f46af | 2423 | MemoryRegion *mr, Error **errp) |
e1c57ab8 PB |
2424 | { |
2425 | RAMBlock *new_block; | |
ef701d7b | 2426 | Error *local_err = NULL; |
e1c57ab8 | 2427 | |
4ed023ce DDAG |
2428 | size = HOST_PAGE_ALIGN(size); |
2429 | max_size = HOST_PAGE_ALIGN(max_size); | |
e1c57ab8 PB |
2430 | new_block = g_malloc0(sizeof(*new_block)); |
2431 | new_block->mr = mr; | |
62be4e3a | 2432 | new_block->resized = resized; |
9b8424d5 MT |
2433 | new_block->used_length = size; |
2434 | new_block->max_length = max_size; | |
62be4e3a | 2435 | assert(max_size >= size); |
e1c57ab8 | 2436 | new_block->fd = -1; |
863e9621 | 2437 | new_block->page_size = getpagesize(); |
e1c57ab8 PB |
2438 | new_block->host = host; |
2439 | if (host) { | |
7bd4f430 | 2440 | new_block->flags |= RAM_PREALLOC; |
e1c57ab8 | 2441 | } |
62be4e3a MT |
2442 | if (resizeable) { |
2443 | new_block->flags |= RAM_RESIZEABLE; | |
2444 | } | |
06329cce | 2445 | ram_block_add(new_block, &local_err, share); |
ef701d7b HT |
2446 | if (local_err) { |
2447 | g_free(new_block); | |
2448 | error_propagate(errp, local_err); | |
528f46af | 2449 | return NULL; |
ef701d7b | 2450 | } |
528f46af | 2451 | return new_block; |
e1c57ab8 PB |
2452 | } |
2453 | ||
528f46af | 2454 | RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
62be4e3a MT |
2455 | MemoryRegion *mr, Error **errp) |
2456 | { | |
06329cce MA |
2457 | return qemu_ram_alloc_internal(size, size, NULL, host, false, |
2458 | false, mr, errp); | |
62be4e3a MT |
2459 | } |
2460 | ||
06329cce MA |
2461 | RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share, |
2462 | MemoryRegion *mr, Error **errp) | |
6977dfe6 | 2463 | { |
06329cce MA |
2464 | return qemu_ram_alloc_internal(size, size, NULL, NULL, false, |
2465 | share, mr, errp); | |
62be4e3a MT |
2466 | } |
2467 | ||
528f46af | 2468 | RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, |
62be4e3a MT |
2469 | void (*resized)(const char*, |
2470 | uint64_t length, | |
2471 | void *host), | |
2472 | MemoryRegion *mr, Error **errp) | |
2473 | { | |
06329cce MA |
2474 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, |
2475 | false, mr, errp); | |
6977dfe6 YT |
2476 | } |
2477 | ||
43771539 PB |
2478 | static void reclaim_ramblock(RAMBlock *block) |
2479 | { | |
2480 | if (block->flags & RAM_PREALLOC) { | |
2481 | ; | |
2482 | } else if (xen_enabled()) { | |
2483 | xen_invalidate_map_cache_entry(block->host); | |
2484 | #ifndef _WIN32 | |
2485 | } else if (block->fd >= 0) { | |
53adb9d4 | 2486 | qemu_ram_munmap(block->fd, block->host, block->max_length); |
43771539 PB |
2487 | close(block->fd); |
2488 | #endif | |
2489 | } else { | |
2490 | qemu_anon_ram_free(block->host, block->max_length); | |
2491 | } | |
2492 | g_free(block); | |
2493 | } | |
2494 | ||
f1060c55 | 2495 | void qemu_ram_free(RAMBlock *block) |
e9a1ab19 | 2496 | { |
85bc2a15 MAL |
2497 | if (!block) { |
2498 | return; | |
2499 | } | |
2500 | ||
0987d735 PB |
2501 | if (block->host) { |
2502 | ram_block_notify_remove(block->host, block->max_length); | |
2503 | } | |
2504 | ||
b2a8658e | 2505 | qemu_mutex_lock_ramlist(); |
f1060c55 FZ |
2506 | QLIST_REMOVE_RCU(block, next); |
2507 | ram_list.mru_block = NULL; | |
2508 | /* Write list before version */ | |
2509 | smp_wmb(); | |
2510 | ram_list.version++; | |
2511 | call_rcu(block, reclaim_ramblock, rcu); | |
b2a8658e | 2512 | qemu_mutex_unlock_ramlist(); |
e9a1ab19 FB |
2513 | } |
2514 | ||
cd19cfa2 HY |
2515 | #ifndef _WIN32 |
2516 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
2517 | { | |
2518 | RAMBlock *block; | |
2519 | ram_addr_t offset; | |
2520 | int flags; | |
2521 | void *area, *vaddr; | |
2522 | ||
99e15582 | 2523 | RAMBLOCK_FOREACH(block) { |
cd19cfa2 | 2524 | offset = addr - block->offset; |
9b8424d5 | 2525 | if (offset < block->max_length) { |
1240be24 | 2526 | vaddr = ramblock_ptr(block, offset); |
7bd4f430 | 2527 | if (block->flags & RAM_PREALLOC) { |
cd19cfa2 | 2528 | ; |
dfeaf2ab MA |
2529 | } else if (xen_enabled()) { |
2530 | abort(); | |
cd19cfa2 HY |
2531 | } else { |
2532 | flags = MAP_FIXED; | |
3435f395 | 2533 | if (block->fd >= 0) { |
dbcb8981 PB |
2534 | flags |= (block->flags & RAM_SHARED ? |
2535 | MAP_SHARED : MAP_PRIVATE); | |
3435f395 MA |
2536 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
2537 | flags, block->fd, offset); | |
cd19cfa2 | 2538 | } else { |
2eb9fbaa MA |
2539 | /* |
2540 | * Remap needs to match alloc. Accelerators that | |
2541 | * set phys_mem_alloc never remap. If they did, | |
2542 | * we'd need a remap hook here. | |
2543 | */ | |
2544 | assert(phys_mem_alloc == qemu_anon_ram_alloc); | |
2545 | ||
cd19cfa2 HY |
2546 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
2547 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2548 | flags, -1, 0); | |
cd19cfa2 HY |
2549 | } |
2550 | if (area != vaddr) { | |
493d89bf AF |
2551 | error_report("Could not remap addr: " |
2552 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "", | |
2553 | length, addr); | |
cd19cfa2 HY |
2554 | exit(1); |
2555 | } | |
8490fc78 | 2556 | memory_try_enable_merging(vaddr, length); |
ddb97f1d | 2557 | qemu_ram_setup_dump(vaddr, length); |
cd19cfa2 | 2558 | } |
cd19cfa2 HY |
2559 | } |
2560 | } | |
2561 | } | |
2562 | #endif /* !_WIN32 */ | |
2563 | ||
1b5ec234 | 2564 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
ae3a7047 MD |
2565 | * This should not be used for general purpose DMA. Use address_space_map |
2566 | * or address_space_rw instead. For local memory (e.g. video ram) that the | |
2567 | * device owns, use memory_region_get_ram_ptr. | |
0dc3f44a | 2568 | * |
49b24afc | 2569 | * Called within RCU critical section. |
1b5ec234 | 2570 | */ |
0878d0e1 | 2571 | void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) |
1b5ec234 | 2572 | { |
3655cb9c GA |
2573 | RAMBlock *block = ram_block; |
2574 | ||
2575 | if (block == NULL) { | |
2576 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2577 | addr -= block->offset; |
3655cb9c | 2578 | } |
ae3a7047 MD |
2579 | |
2580 | if (xen_enabled() && block->host == NULL) { | |
0d6d3c87 PB |
2581 | /* We need to check if the requested address is in the RAM |
2582 | * because we don't want to map the entire memory in QEMU. | |
2583 | * In that case just map until the end of the page. | |
2584 | */ | |
2585 | if (block->offset == 0) { | |
1ff7c598 | 2586 | return xen_map_cache(addr, 0, 0, false); |
0d6d3c87 | 2587 | } |
ae3a7047 | 2588 | |
1ff7c598 | 2589 | block->host = xen_map_cache(block->offset, block->max_length, 1, false); |
0d6d3c87 | 2590 | } |
0878d0e1 | 2591 | return ramblock_ptr(block, addr); |
dc828ca1 PB |
2592 | } |
2593 | ||
0878d0e1 | 2594 | /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr |
ae3a7047 | 2595 | * but takes a size argument. |
0dc3f44a | 2596 | * |
e81bcda5 | 2597 | * Called within RCU critical section. |
ae3a7047 | 2598 | */ |
3655cb9c | 2599 | static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr, |
f5aa69bd | 2600 | hwaddr *size, bool lock) |
38bee5dc | 2601 | { |
3655cb9c | 2602 | RAMBlock *block = ram_block; |
8ab934f9 SS |
2603 | if (*size == 0) { |
2604 | return NULL; | |
2605 | } | |
e81bcda5 | 2606 | |
3655cb9c GA |
2607 | if (block == NULL) { |
2608 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2609 | addr -= block->offset; |
3655cb9c | 2610 | } |
0878d0e1 | 2611 | *size = MIN(*size, block->max_length - addr); |
e81bcda5 PB |
2612 | |
2613 | if (xen_enabled() && block->host == NULL) { | |
2614 | /* We need to check if the requested address is in the RAM | |
2615 | * because we don't want to map the entire memory in QEMU. | |
2616 | * In that case just map the requested area. | |
2617 | */ | |
2618 | if (block->offset == 0) { | |
f5aa69bd | 2619 | return xen_map_cache(addr, *size, lock, lock); |
38bee5dc SS |
2620 | } |
2621 | ||
f5aa69bd | 2622 | block->host = xen_map_cache(block->offset, block->max_length, 1, lock); |
38bee5dc | 2623 | } |
e81bcda5 | 2624 | |
0878d0e1 | 2625 | return ramblock_ptr(block, addr); |
38bee5dc SS |
2626 | } |
2627 | ||
f90bb71b DDAG |
2628 | /* Return the offset of a hostpointer within a ramblock */ |
2629 | ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host) | |
2630 | { | |
2631 | ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host; | |
2632 | assert((uintptr_t)host >= (uintptr_t)rb->host); | |
2633 | assert(res < rb->max_length); | |
2634 | ||
2635 | return res; | |
2636 | } | |
2637 | ||
422148d3 DDAG |
2638 | /* |
2639 | * Translates a host ptr back to a RAMBlock, a ram_addr and an offset | |
2640 | * in that RAMBlock. | |
2641 | * | |
2642 | * ptr: Host pointer to look up | |
2643 | * round_offset: If true round the result offset down to a page boundary | |
2644 | * *ram_addr: set to result ram_addr | |
2645 | * *offset: set to result offset within the RAMBlock | |
2646 | * | |
2647 | * Returns: RAMBlock (or NULL if not found) | |
ae3a7047 MD |
2648 | * |
2649 | * By the time this function returns, the returned pointer is not protected | |
2650 | * by RCU anymore. If the caller is not within an RCU critical section and | |
2651 | * does not hold the iothread lock, it must have other means of protecting the | |
2652 | * pointer, such as a reference to the region that includes the incoming | |
2653 | * ram_addr_t. | |
2654 | */ | |
422148d3 | 2655 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
422148d3 | 2656 | ram_addr_t *offset) |
5579c7f3 | 2657 | { |
94a6b54f PB |
2658 | RAMBlock *block; |
2659 | uint8_t *host = ptr; | |
2660 | ||
868bb33f | 2661 | if (xen_enabled()) { |
f615f396 | 2662 | ram_addr_t ram_addr; |
0dc3f44a | 2663 | rcu_read_lock(); |
f615f396 PB |
2664 | ram_addr = xen_ram_addr_from_mapcache(ptr); |
2665 | block = qemu_get_ram_block(ram_addr); | |
422148d3 | 2666 | if (block) { |
d6b6aec4 | 2667 | *offset = ram_addr - block->offset; |
422148d3 | 2668 | } |
0dc3f44a | 2669 | rcu_read_unlock(); |
422148d3 | 2670 | return block; |
712c2b41 SS |
2671 | } |
2672 | ||
0dc3f44a MD |
2673 | rcu_read_lock(); |
2674 | block = atomic_rcu_read(&ram_list.mru_block); | |
9b8424d5 | 2675 | if (block && block->host && host - block->host < block->max_length) { |
23887b79 PB |
2676 | goto found; |
2677 | } | |
2678 | ||
99e15582 | 2679 | RAMBLOCK_FOREACH(block) { |
432d268c JN |
2680 | /* This case append when the block is not mapped. */ |
2681 | if (block->host == NULL) { | |
2682 | continue; | |
2683 | } | |
9b8424d5 | 2684 | if (host - block->host < block->max_length) { |
23887b79 | 2685 | goto found; |
f471a17e | 2686 | } |
94a6b54f | 2687 | } |
432d268c | 2688 | |
0dc3f44a | 2689 | rcu_read_unlock(); |
1b5ec234 | 2690 | return NULL; |
23887b79 PB |
2691 | |
2692 | found: | |
422148d3 DDAG |
2693 | *offset = (host - block->host); |
2694 | if (round_offset) { | |
2695 | *offset &= TARGET_PAGE_MASK; | |
2696 | } | |
0dc3f44a | 2697 | rcu_read_unlock(); |
422148d3 DDAG |
2698 | return block; |
2699 | } | |
2700 | ||
e3dd7493 DDAG |
2701 | /* |
2702 | * Finds the named RAMBlock | |
2703 | * | |
2704 | * name: The name of RAMBlock to find | |
2705 | * | |
2706 | * Returns: RAMBlock (or NULL if not found) | |
2707 | */ | |
2708 | RAMBlock *qemu_ram_block_by_name(const char *name) | |
2709 | { | |
2710 | RAMBlock *block; | |
2711 | ||
99e15582 | 2712 | RAMBLOCK_FOREACH(block) { |
e3dd7493 DDAG |
2713 | if (!strcmp(name, block->idstr)) { |
2714 | return block; | |
2715 | } | |
2716 | } | |
2717 | ||
2718 | return NULL; | |
2719 | } | |
2720 | ||
422148d3 DDAG |
2721 | /* Some of the softmmu routines need to translate from a host pointer |
2722 | (typically a TLB entry) back to a ram offset. */ | |
07bdaa41 | 2723 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
422148d3 DDAG |
2724 | { |
2725 | RAMBlock *block; | |
f615f396 | 2726 | ram_addr_t offset; |
422148d3 | 2727 | |
f615f396 | 2728 | block = qemu_ram_block_from_host(ptr, false, &offset); |
422148d3 | 2729 | if (!block) { |
07bdaa41 | 2730 | return RAM_ADDR_INVALID; |
422148d3 DDAG |
2731 | } |
2732 | ||
07bdaa41 | 2733 | return block->offset + offset; |
e890261f | 2734 | } |
f471a17e | 2735 | |
27266271 PM |
2736 | /* Called within RCU critical section. */ |
2737 | void memory_notdirty_write_prepare(NotDirtyInfo *ndi, | |
2738 | CPUState *cpu, | |
2739 | vaddr mem_vaddr, | |
2740 | ram_addr_t ram_addr, | |
2741 | unsigned size) | |
2742 | { | |
2743 | ndi->cpu = cpu; | |
2744 | ndi->ram_addr = ram_addr; | |
2745 | ndi->mem_vaddr = mem_vaddr; | |
2746 | ndi->size = size; | |
0ac20318 | 2747 | ndi->pages = NULL; |
ba051fb5 | 2748 | |
5aa1ef71 | 2749 | assert(tcg_enabled()); |
52159192 | 2750 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { |
0ac20318 EC |
2751 | ndi->pages = page_collection_lock(ram_addr, ram_addr + size); |
2752 | tb_invalidate_phys_page_fast(ndi->pages, ram_addr, size); | |
3a7d929e | 2753 | } |
27266271 PM |
2754 | } |
2755 | ||
2756 | /* Called within RCU critical section. */ | |
2757 | void memory_notdirty_write_complete(NotDirtyInfo *ndi) | |
2758 | { | |
0ac20318 | 2759 | if (ndi->pages) { |
f28d0dfd | 2760 | assert(tcg_enabled()); |
0ac20318 EC |
2761 | page_collection_unlock(ndi->pages); |
2762 | ndi->pages = NULL; | |
27266271 PM |
2763 | } |
2764 | ||
2765 | /* Set both VGA and migration bits for simplicity and to remove | |
2766 | * the notdirty callback faster. | |
2767 | */ | |
2768 | cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size, | |
2769 | DIRTY_CLIENTS_NOCODE); | |
2770 | /* we remove the notdirty callback only if the code has been | |
2771 | flushed */ | |
2772 | if (!cpu_physical_memory_is_clean(ndi->ram_addr)) { | |
2773 | tlb_set_dirty(ndi->cpu, ndi->mem_vaddr); | |
2774 | } | |
2775 | } | |
2776 | ||
2777 | /* Called within RCU critical section. */ | |
2778 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, | |
2779 | uint64_t val, unsigned size) | |
2780 | { | |
2781 | NotDirtyInfo ndi; | |
2782 | ||
2783 | memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr, | |
2784 | ram_addr, size); | |
2785 | ||
6d3ede54 | 2786 | stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val); |
27266271 | 2787 | memory_notdirty_write_complete(&ndi); |
9fa3e853 FB |
2788 | } |
2789 | ||
b018ddf6 | 2790 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
2791 | unsigned size, bool is_write, |
2792 | MemTxAttrs attrs) | |
b018ddf6 PB |
2793 | { |
2794 | return is_write; | |
2795 | } | |
2796 | ||
0e0df1e2 | 2797 | static const MemoryRegionOps notdirty_mem_ops = { |
0e0df1e2 | 2798 | .write = notdirty_mem_write, |
b018ddf6 | 2799 | .valid.accepts = notdirty_mem_accepts, |
0e0df1e2 | 2800 | .endianness = DEVICE_NATIVE_ENDIAN, |
ad52878f AB |
2801 | .valid = { |
2802 | .min_access_size = 1, | |
2803 | .max_access_size = 8, | |
2804 | .unaligned = false, | |
2805 | }, | |
2806 | .impl = { | |
2807 | .min_access_size = 1, | |
2808 | .max_access_size = 8, | |
2809 | .unaligned = false, | |
2810 | }, | |
1ccde1cb FB |
2811 | }; |
2812 | ||
0f459d16 | 2813 | /* Generate a debug exception if a watchpoint has been hit. */ |
66b9b43c | 2814 | static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) |
0f459d16 | 2815 | { |
93afeade | 2816 | CPUState *cpu = current_cpu; |
568496c0 | 2817 | CPUClass *cc = CPU_GET_CLASS(cpu); |
0f459d16 | 2818 | target_ulong vaddr; |
a1d1bb31 | 2819 | CPUWatchpoint *wp; |
0f459d16 | 2820 | |
5aa1ef71 | 2821 | assert(tcg_enabled()); |
ff4700b0 | 2822 | if (cpu->watchpoint_hit) { |
06d55cc1 AL |
2823 | /* We re-entered the check after replacing the TB. Now raise |
2824 | * the debug interrupt so that is will trigger after the | |
2825 | * current instruction. */ | |
93afeade | 2826 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); |
06d55cc1 AL |
2827 | return; |
2828 | } | |
93afeade | 2829 | vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
40612000 | 2830 | vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len); |
ff4700b0 | 2831 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d PM |
2832 | if (cpu_watchpoint_address_matches(wp, vaddr, len) |
2833 | && (wp->flags & flags)) { | |
08225676 PM |
2834 | if (flags == BP_MEM_READ) { |
2835 | wp->flags |= BP_WATCHPOINT_HIT_READ; | |
2836 | } else { | |
2837 | wp->flags |= BP_WATCHPOINT_HIT_WRITE; | |
2838 | } | |
2839 | wp->hitaddr = vaddr; | |
66b9b43c | 2840 | wp->hitattrs = attrs; |
ff4700b0 | 2841 | if (!cpu->watchpoint_hit) { |
568496c0 SF |
2842 | if (wp->flags & BP_CPU && |
2843 | !cc->debug_check_watchpoint(cpu, wp)) { | |
2844 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
2845 | continue; | |
2846 | } | |
ff4700b0 | 2847 | cpu->watchpoint_hit = wp; |
a5e99826 | 2848 | |
0ac20318 | 2849 | mmap_lock(); |
239c51a5 | 2850 | tb_check_watchpoint(cpu); |
6e140f28 | 2851 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
27103424 | 2852 | cpu->exception_index = EXCP_DEBUG; |
0ac20318 | 2853 | mmap_unlock(); |
5638d180 | 2854 | cpu_loop_exit(cpu); |
6e140f28 | 2855 | } else { |
9b990ee5 RH |
2856 | /* Force execution of one insn next time. */ |
2857 | cpu->cflags_next_tb = 1 | curr_cflags(); | |
0ac20318 | 2858 | mmap_unlock(); |
6886b980 | 2859 | cpu_loop_exit_noexc(cpu); |
6e140f28 | 2860 | } |
06d55cc1 | 2861 | } |
6e140f28 AL |
2862 | } else { |
2863 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
2864 | } |
2865 | } | |
2866 | } | |
2867 | ||
6658ffb8 PB |
2868 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
2869 | so these check for a hit then pass through to the normal out-of-line | |
2870 | phys routines. */ | |
66b9b43c PM |
2871 | static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata, |
2872 | unsigned size, MemTxAttrs attrs) | |
6658ffb8 | 2873 | { |
66b9b43c PM |
2874 | MemTxResult res; |
2875 | uint64_t data; | |
79ed0416 PM |
2876 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2877 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2878 | |
2879 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ); | |
1ec9b909 | 2880 | switch (size) { |
66b9b43c | 2881 | case 1: |
79ed0416 | 2882 | data = address_space_ldub(as, addr, attrs, &res); |
66b9b43c PM |
2883 | break; |
2884 | case 2: | |
79ed0416 | 2885 | data = address_space_lduw(as, addr, attrs, &res); |
66b9b43c PM |
2886 | break; |
2887 | case 4: | |
79ed0416 | 2888 | data = address_space_ldl(as, addr, attrs, &res); |
66b9b43c | 2889 | break; |
306526b5 PB |
2890 | case 8: |
2891 | data = address_space_ldq(as, addr, attrs, &res); | |
2892 | break; | |
1ec9b909 AK |
2893 | default: abort(); |
2894 | } | |
66b9b43c PM |
2895 | *pdata = data; |
2896 | return res; | |
6658ffb8 PB |
2897 | } |
2898 | ||
66b9b43c PM |
2899 | static MemTxResult watch_mem_write(void *opaque, hwaddr addr, |
2900 | uint64_t val, unsigned size, | |
2901 | MemTxAttrs attrs) | |
6658ffb8 | 2902 | { |
66b9b43c | 2903 | MemTxResult res; |
79ed0416 PM |
2904 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2905 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2906 | |
2907 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE); | |
1ec9b909 | 2908 | switch (size) { |
67364150 | 2909 | case 1: |
79ed0416 | 2910 | address_space_stb(as, addr, val, attrs, &res); |
67364150 MF |
2911 | break; |
2912 | case 2: | |
79ed0416 | 2913 | address_space_stw(as, addr, val, attrs, &res); |
67364150 MF |
2914 | break; |
2915 | case 4: | |
79ed0416 | 2916 | address_space_stl(as, addr, val, attrs, &res); |
67364150 | 2917 | break; |
306526b5 PB |
2918 | case 8: |
2919 | address_space_stq(as, addr, val, attrs, &res); | |
2920 | break; | |
1ec9b909 AK |
2921 | default: abort(); |
2922 | } | |
66b9b43c | 2923 | return res; |
6658ffb8 PB |
2924 | } |
2925 | ||
1ec9b909 | 2926 | static const MemoryRegionOps watch_mem_ops = { |
66b9b43c PM |
2927 | .read_with_attrs = watch_mem_read, |
2928 | .write_with_attrs = watch_mem_write, | |
1ec9b909 | 2929 | .endianness = DEVICE_NATIVE_ENDIAN, |
306526b5 PB |
2930 | .valid = { |
2931 | .min_access_size = 1, | |
2932 | .max_access_size = 8, | |
2933 | .unaligned = false, | |
2934 | }, | |
2935 | .impl = { | |
2936 | .min_access_size = 1, | |
2937 | .max_access_size = 8, | |
2938 | .unaligned = false, | |
2939 | }, | |
6658ffb8 | 2940 | }; |
6658ffb8 | 2941 | |
b2a44fca | 2942 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, |
0c249ff7 | 2943 | MemTxAttrs attrs, uint8_t *buf, hwaddr len); |
16620684 | 2944 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
0c249ff7 LZ |
2945 | const uint8_t *buf, hwaddr len); |
2946 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len, | |
eace72b7 | 2947 | bool is_write, MemTxAttrs attrs); |
16620684 | 2948 | |
f25a49e0 PM |
2949 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, |
2950 | unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2951 | { |
acc9d80b | 2952 | subpage_t *subpage = opaque; |
ff6cff75 | 2953 | uint8_t buf[8]; |
5c9eb028 | 2954 | MemTxResult res; |
791af8c8 | 2955 | |
db7b5426 | 2956 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2957 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, |
acc9d80b | 2958 | subpage, len, addr); |
db7b5426 | 2959 | #endif |
16620684 | 2960 | res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); |
5c9eb028 PM |
2961 | if (res) { |
2962 | return res; | |
f25a49e0 | 2963 | } |
6d3ede54 PM |
2964 | *data = ldn_p(buf, len); |
2965 | return MEMTX_OK; | |
db7b5426 BS |
2966 | } |
2967 | ||
f25a49e0 PM |
2968 | static MemTxResult subpage_write(void *opaque, hwaddr addr, |
2969 | uint64_t value, unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2970 | { |
acc9d80b | 2971 | subpage_t *subpage = opaque; |
ff6cff75 | 2972 | uint8_t buf[8]; |
acc9d80b | 2973 | |
db7b5426 | 2974 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2975 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx |
acc9d80b JK |
2976 | " value %"PRIx64"\n", |
2977 | __func__, subpage, len, addr, value); | |
db7b5426 | 2978 | #endif |
6d3ede54 | 2979 | stn_p(buf, len, value); |
16620684 | 2980 | return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); |
db7b5426 BS |
2981 | } |
2982 | ||
c353e4cc | 2983 | static bool subpage_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
2984 | unsigned len, bool is_write, |
2985 | MemTxAttrs attrs) | |
c353e4cc | 2986 | { |
acc9d80b | 2987 | subpage_t *subpage = opaque; |
c353e4cc | 2988 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2989 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", |
acc9d80b | 2990 | __func__, subpage, is_write ? 'w' : 'r', len, addr); |
c353e4cc PB |
2991 | #endif |
2992 | ||
16620684 | 2993 | return flatview_access_valid(subpage->fv, addr + subpage->base, |
eace72b7 | 2994 | len, is_write, attrs); |
c353e4cc PB |
2995 | } |
2996 | ||
70c68e44 | 2997 | static const MemoryRegionOps subpage_ops = { |
f25a49e0 PM |
2998 | .read_with_attrs = subpage_read, |
2999 | .write_with_attrs = subpage_write, | |
ff6cff75 PB |
3000 | .impl.min_access_size = 1, |
3001 | .impl.max_access_size = 8, | |
3002 | .valid.min_access_size = 1, | |
3003 | .valid.max_access_size = 8, | |
c353e4cc | 3004 | .valid.accepts = subpage_accepts, |
70c68e44 | 3005 | .endianness = DEVICE_NATIVE_ENDIAN, |
db7b5426 BS |
3006 | }; |
3007 | ||
c227f099 | 3008 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 3009 | uint16_t section) |
db7b5426 BS |
3010 | { |
3011 | int idx, eidx; | |
3012 | ||
3013 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
3014 | return -1; | |
3015 | idx = SUBPAGE_IDX(start); | |
3016 | eidx = SUBPAGE_IDX(end); | |
3017 | #if defined(DEBUG_SUBPAGE) | |
016e9d62 AK |
3018 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", |
3019 | __func__, mmio, start, end, idx, eidx, section); | |
db7b5426 | 3020 | #endif |
db7b5426 | 3021 | for (; idx <= eidx; idx++) { |
5312bd8b | 3022 | mmio->sub_section[idx] = section; |
db7b5426 BS |
3023 | } |
3024 | ||
3025 | return 0; | |
3026 | } | |
3027 | ||
16620684 | 3028 | static subpage_t *subpage_init(FlatView *fv, hwaddr base) |
db7b5426 | 3029 | { |
c227f099 | 3030 | subpage_t *mmio; |
db7b5426 | 3031 | |
2615fabd | 3032 | mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t)); |
16620684 | 3033 | mmio->fv = fv; |
1eec614b | 3034 | mmio->base = base; |
2c9b15ca | 3035 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
b4fefef9 | 3036 | NULL, TARGET_PAGE_SIZE); |
b3b00c78 | 3037 | mmio->iomem.subpage = true; |
db7b5426 | 3038 | #if defined(DEBUG_SUBPAGE) |
016e9d62 AK |
3039 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, |
3040 | mmio, base, TARGET_PAGE_SIZE); | |
db7b5426 | 3041 | #endif |
b41aac4f | 3042 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); |
db7b5426 BS |
3043 | |
3044 | return mmio; | |
3045 | } | |
3046 | ||
16620684 | 3047 | static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) |
5312bd8b | 3048 | { |
16620684 | 3049 | assert(fv); |
5312bd8b | 3050 | MemoryRegionSection section = { |
16620684 | 3051 | .fv = fv, |
5312bd8b AK |
3052 | .mr = mr, |
3053 | .offset_within_address_space = 0, | |
3054 | .offset_within_region = 0, | |
052e87b0 | 3055 | .size = int128_2_64(), |
5312bd8b AK |
3056 | }; |
3057 | ||
53cb28cb | 3058 | return phys_section_add(map, §ion); |
5312bd8b AK |
3059 | } |
3060 | ||
8af36743 PM |
3061 | static void readonly_mem_write(void *opaque, hwaddr addr, |
3062 | uint64_t val, unsigned size) | |
3063 | { | |
3064 | /* Ignore any write to ROM. */ | |
3065 | } | |
3066 | ||
3067 | static bool readonly_mem_accepts(void *opaque, hwaddr addr, | |
8372d383 PM |
3068 | unsigned size, bool is_write, |
3069 | MemTxAttrs attrs) | |
8af36743 PM |
3070 | { |
3071 | return is_write; | |
3072 | } | |
3073 | ||
3074 | /* This will only be used for writes, because reads are special cased | |
3075 | * to directly access the underlying host ram. | |
3076 | */ | |
3077 | static const MemoryRegionOps readonly_mem_ops = { | |
3078 | .write = readonly_mem_write, | |
3079 | .valid.accepts = readonly_mem_accepts, | |
3080 | .endianness = DEVICE_NATIVE_ENDIAN, | |
3081 | .valid = { | |
3082 | .min_access_size = 1, | |
3083 | .max_access_size = 8, | |
3084 | .unaligned = false, | |
3085 | }, | |
3086 | .impl = { | |
3087 | .min_access_size = 1, | |
3088 | .max_access_size = 8, | |
3089 | .unaligned = false, | |
3090 | }, | |
3091 | }; | |
3092 | ||
2d54f194 PM |
3093 | MemoryRegionSection *iotlb_to_section(CPUState *cpu, |
3094 | hwaddr index, MemTxAttrs attrs) | |
aa102231 | 3095 | { |
a54c87b6 PM |
3096 | int asidx = cpu_asidx_from_attrs(cpu, attrs); |
3097 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | |
32857f4d | 3098 | AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch); |
79e2b9ae | 3099 | MemoryRegionSection *sections = d->map.sections; |
9d82b5a7 | 3100 | |
2d54f194 | 3101 | return §ions[index & ~TARGET_PAGE_MASK]; |
aa102231 AK |
3102 | } |
3103 | ||
e9179ce1 AK |
3104 | static void io_mem_init(void) |
3105 | { | |
8af36743 PM |
3106 | memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops, |
3107 | NULL, NULL, UINT64_MAX); | |
2c9b15ca | 3108 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, |
1f6245e5 | 3109 | NULL, UINT64_MAX); |
8d04fb55 JK |
3110 | |
3111 | /* io_mem_notdirty calls tb_invalidate_phys_page_fast, | |
3112 | * which can be called without the iothread mutex. | |
3113 | */ | |
2c9b15ca | 3114 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, |
1f6245e5 | 3115 | NULL, UINT64_MAX); |
8d04fb55 JK |
3116 | memory_region_clear_global_locking(&io_mem_notdirty); |
3117 | ||
2c9b15ca | 3118 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, |
1f6245e5 | 3119 | NULL, UINT64_MAX); |
e9179ce1 AK |
3120 | } |
3121 | ||
8629d3fc | 3122 | AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) |
00752703 | 3123 | { |
53cb28cb MA |
3124 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); |
3125 | uint16_t n; | |
3126 | ||
16620684 | 3127 | n = dummy_section(&d->map, fv, &io_mem_unassigned); |
53cb28cb | 3128 | assert(n == PHYS_SECTION_UNASSIGNED); |
16620684 | 3129 | n = dummy_section(&d->map, fv, &io_mem_notdirty); |
53cb28cb | 3130 | assert(n == PHYS_SECTION_NOTDIRTY); |
16620684 | 3131 | n = dummy_section(&d->map, fv, &io_mem_rom); |
53cb28cb | 3132 | assert(n == PHYS_SECTION_ROM); |
16620684 | 3133 | n = dummy_section(&d->map, fv, &io_mem_watch); |
53cb28cb | 3134 | assert(n == PHYS_SECTION_WATCH); |
00752703 | 3135 | |
9736e55b | 3136 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; |
66a6df1d AK |
3137 | |
3138 | return d; | |
00752703 PB |
3139 | } |
3140 | ||
66a6df1d | 3141 | void address_space_dispatch_free(AddressSpaceDispatch *d) |
79e2b9ae PB |
3142 | { |
3143 | phys_sections_free(&d->map); | |
3144 | g_free(d); | |
3145 | } | |
3146 | ||
9458a9a1 PB |
3147 | static void do_nothing(CPUState *cpu, run_on_cpu_data d) |
3148 | { | |
3149 | } | |
3150 | ||
3151 | static void tcg_log_global_after_sync(MemoryListener *listener) | |
3152 | { | |
3153 | CPUAddressSpace *cpuas; | |
3154 | ||
3155 | /* Wait for the CPU to end the current TB. This avoids the following | |
3156 | * incorrect race: | |
3157 | * | |
3158 | * vCPU migration | |
3159 | * ---------------------- ------------------------- | |
3160 | * TLB check -> slow path | |
3161 | * notdirty_mem_write | |
3162 | * write to RAM | |
3163 | * mark dirty | |
3164 | * clear dirty flag | |
3165 | * TLB check -> fast path | |
3166 | * read memory | |
3167 | * write to RAM | |
3168 | * | |
3169 | * by pushing the migration thread's memory read after the vCPU thread has | |
3170 | * written the memory. | |
3171 | */ | |
3172 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); | |
3173 | run_on_cpu(cpuas->cpu, do_nothing, RUN_ON_CPU_NULL); | |
3174 | } | |
3175 | ||
1d71148e | 3176 | static void tcg_commit(MemoryListener *listener) |
50c1e149 | 3177 | { |
32857f4d PM |
3178 | CPUAddressSpace *cpuas; |
3179 | AddressSpaceDispatch *d; | |
117712c3 | 3180 | |
f28d0dfd | 3181 | assert(tcg_enabled()); |
117712c3 AK |
3182 | /* since each CPU stores ram addresses in its TLB cache, we must |
3183 | reset the modified entries */ | |
32857f4d PM |
3184 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); |
3185 | cpu_reloading_memory_map(); | |
3186 | /* The CPU and TLB are protected by the iothread lock. | |
3187 | * We reload the dispatch pointer now because cpu_reloading_memory_map() | |
3188 | * may have split the RCU critical section. | |
3189 | */ | |
66a6df1d | 3190 | d = address_space_to_dispatch(cpuas->as); |
f35e44e7 | 3191 | atomic_rcu_set(&cpuas->memory_dispatch, d); |
d10eb08f | 3192 | tlb_flush(cpuas->cpu); |
50c1e149 AK |
3193 | } |
3194 | ||
62152b8a AK |
3195 | static void memory_map_init(void) |
3196 | { | |
7267c094 | 3197 | system_memory = g_malloc(sizeof(*system_memory)); |
03f49957 | 3198 | |
57271d63 | 3199 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
7dca8043 | 3200 | address_space_init(&address_space_memory, system_memory, "memory"); |
309cb471 | 3201 | |
7267c094 | 3202 | system_io = g_malloc(sizeof(*system_io)); |
3bb28b72 JK |
3203 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
3204 | 65536); | |
7dca8043 | 3205 | address_space_init(&address_space_io, system_io, "I/O"); |
62152b8a AK |
3206 | } |
3207 | ||
3208 | MemoryRegion *get_system_memory(void) | |
3209 | { | |
3210 | return system_memory; | |
3211 | } | |
3212 | ||
309cb471 AK |
3213 | MemoryRegion *get_system_io(void) |
3214 | { | |
3215 | return system_io; | |
3216 | } | |
3217 | ||
e2eef170 PB |
3218 | #endif /* !defined(CONFIG_USER_ONLY) */ |
3219 | ||
13eb76e0 FB |
3220 | /* physical memory access (slow version, mainly for debug) */ |
3221 | #if defined(CONFIG_USER_ONLY) | |
f17ec444 | 3222 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
0c249ff7 | 3223 | uint8_t *buf, target_ulong len, int is_write) |
13eb76e0 | 3224 | { |
0c249ff7 LZ |
3225 | int flags; |
3226 | target_ulong l, page; | |
53a5960a | 3227 | void * p; |
13eb76e0 FB |
3228 | |
3229 | while (len > 0) { | |
3230 | page = addr & TARGET_PAGE_MASK; | |
3231 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3232 | if (l > len) | |
3233 | l = len; | |
3234 | flags = page_get_flags(page); | |
3235 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 3236 | return -1; |
13eb76e0 FB |
3237 | if (is_write) { |
3238 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 3239 | return -1; |
579a97f7 | 3240 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3241 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 3242 | return -1; |
72fb7daa AJ |
3243 | memcpy(p, buf, l); |
3244 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3245 | } else { |
3246 | if (!(flags & PAGE_READ)) | |
a68fe89c | 3247 | return -1; |
579a97f7 | 3248 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3249 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 3250 | return -1; |
72fb7daa | 3251 | memcpy(buf, p, l); |
5b257578 | 3252 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3253 | } |
3254 | len -= l; | |
3255 | buf += l; | |
3256 | addr += l; | |
3257 | } | |
a68fe89c | 3258 | return 0; |
13eb76e0 | 3259 | } |
8df1cd07 | 3260 | |
13eb76e0 | 3261 | #else |
51d7a9eb | 3262 | |
845b6214 | 3263 | static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, |
a8170e5e | 3264 | hwaddr length) |
51d7a9eb | 3265 | { |
e87f7778 | 3266 | uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
0878d0e1 PB |
3267 | addr += memory_region_get_ram_addr(mr); |
3268 | ||
e87f7778 PB |
3269 | /* No early return if dirty_log_mask is or becomes 0, because |
3270 | * cpu_physical_memory_set_dirty_range will still call | |
3271 | * xen_modified_memory. | |
3272 | */ | |
3273 | if (dirty_log_mask) { | |
3274 | dirty_log_mask = | |
3275 | cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); | |
3276 | } | |
3277 | if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { | |
5aa1ef71 | 3278 | assert(tcg_enabled()); |
e87f7778 PB |
3279 | tb_invalidate_phys_range(addr, addr + length); |
3280 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); | |
51d7a9eb | 3281 | } |
e87f7778 | 3282 | cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); |
51d7a9eb AP |
3283 | } |
3284 | ||
047be4ed SH |
3285 | void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size) |
3286 | { | |
3287 | /* | |
3288 | * In principle this function would work on other memory region types too, | |
3289 | * but the ROM device use case is the only one where this operation is | |
3290 | * necessary. Other memory regions should use the | |
3291 | * address_space_read/write() APIs. | |
3292 | */ | |
3293 | assert(memory_region_is_romd(mr)); | |
3294 | ||
3295 | invalidate_and_set_dirty(mr, addr, size); | |
3296 | } | |
3297 | ||
23326164 | 3298 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
82f2563f | 3299 | { |
e1622f4b | 3300 | unsigned access_size_max = mr->ops->valid.max_access_size; |
23326164 RH |
3301 | |
3302 | /* Regions are assumed to support 1-4 byte accesses unless | |
3303 | otherwise specified. */ | |
23326164 RH |
3304 | if (access_size_max == 0) { |
3305 | access_size_max = 4; | |
3306 | } | |
3307 | ||
3308 | /* Bound the maximum access by the alignment of the address. */ | |
3309 | if (!mr->ops->impl.unaligned) { | |
3310 | unsigned align_size_max = addr & -addr; | |
3311 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
3312 | access_size_max = align_size_max; | |
3313 | } | |
82f2563f | 3314 | } |
23326164 RH |
3315 | |
3316 | /* Don't attempt accesses larger than the maximum. */ | |
3317 | if (l > access_size_max) { | |
3318 | l = access_size_max; | |
82f2563f | 3319 | } |
6554f5c0 | 3320 | l = pow2floor(l); |
23326164 RH |
3321 | |
3322 | return l; | |
82f2563f PB |
3323 | } |
3324 | ||
4840f10e | 3325 | static bool prepare_mmio_access(MemoryRegion *mr) |
125b3806 | 3326 | { |
4840f10e JK |
3327 | bool unlocked = !qemu_mutex_iothread_locked(); |
3328 | bool release_lock = false; | |
3329 | ||
3330 | if (unlocked && mr->global_locking) { | |
3331 | qemu_mutex_lock_iothread(); | |
3332 | unlocked = false; | |
3333 | release_lock = true; | |
3334 | } | |
125b3806 | 3335 | if (mr->flush_coalesced_mmio) { |
4840f10e JK |
3336 | if (unlocked) { |
3337 | qemu_mutex_lock_iothread(); | |
3338 | } | |
125b3806 | 3339 | qemu_flush_coalesced_mmio_buffer(); |
4840f10e JK |
3340 | if (unlocked) { |
3341 | qemu_mutex_unlock_iothread(); | |
3342 | } | |
125b3806 | 3343 | } |
4840f10e JK |
3344 | |
3345 | return release_lock; | |
125b3806 PB |
3346 | } |
3347 | ||
a203ac70 | 3348 | /* Called within RCU critical section. */ |
16620684 AK |
3349 | static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, |
3350 | MemTxAttrs attrs, | |
3351 | const uint8_t *buf, | |
0c249ff7 | 3352 | hwaddr len, hwaddr addr1, |
16620684 | 3353 | hwaddr l, MemoryRegion *mr) |
13eb76e0 | 3354 | { |
13eb76e0 | 3355 | uint8_t *ptr; |
791af8c8 | 3356 | uint64_t val; |
3b643495 | 3357 | MemTxResult result = MEMTX_OK; |
4840f10e | 3358 | bool release_lock = false; |
3b46e624 | 3359 | |
a203ac70 | 3360 | for (;;) { |
eb7eeb88 PB |
3361 | if (!memory_access_is_direct(mr, true)) { |
3362 | release_lock |= prepare_mmio_access(mr); | |
3363 | l = memory_access_size(mr, l, addr1); | |
3364 | /* XXX: could force current_cpu to NULL to avoid | |
3365 | potential bugs */ | |
6d3ede54 PM |
3366 | val = ldn_p(buf, l); |
3367 | result |= memory_region_dispatch_write(mr, addr1, val, l, attrs); | |
13eb76e0 | 3368 | } else { |
eb7eeb88 | 3369 | /* RAM case */ |
f5aa69bd | 3370 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
eb7eeb88 PB |
3371 | memcpy(ptr, buf, l); |
3372 | invalidate_and_set_dirty(mr, addr1, l); | |
13eb76e0 | 3373 | } |
4840f10e JK |
3374 | |
3375 | if (release_lock) { | |
3376 | qemu_mutex_unlock_iothread(); | |
3377 | release_lock = false; | |
3378 | } | |
3379 | ||
13eb76e0 FB |
3380 | len -= l; |
3381 | buf += l; | |
3382 | addr += l; | |
a203ac70 PB |
3383 | |
3384 | if (!len) { | |
3385 | break; | |
3386 | } | |
3387 | ||
3388 | l = len; | |
efa99a2f | 3389 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); |
13eb76e0 | 3390 | } |
fd8aaa76 | 3391 | |
3b643495 | 3392 | return result; |
13eb76e0 | 3393 | } |
8df1cd07 | 3394 | |
4c6ebbb3 | 3395 | /* Called from RCU critical section. */ |
16620684 | 3396 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
0c249ff7 | 3397 | const uint8_t *buf, hwaddr len) |
ac1970fb | 3398 | { |
eb7eeb88 | 3399 | hwaddr l; |
eb7eeb88 PB |
3400 | hwaddr addr1; |
3401 | MemoryRegion *mr; | |
3402 | MemTxResult result = MEMTX_OK; | |
eb7eeb88 | 3403 | |
4c6ebbb3 | 3404 | l = len; |
efa99a2f | 3405 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); |
4c6ebbb3 PB |
3406 | result = flatview_write_continue(fv, addr, attrs, buf, len, |
3407 | addr1, l, mr); | |
a203ac70 PB |
3408 | |
3409 | return result; | |
3410 | } | |
3411 | ||
3412 | /* Called within RCU critical section. */ | |
16620684 AK |
3413 | MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, |
3414 | MemTxAttrs attrs, uint8_t *buf, | |
0c249ff7 | 3415 | hwaddr len, hwaddr addr1, hwaddr l, |
16620684 | 3416 | MemoryRegion *mr) |
a203ac70 PB |
3417 | { |
3418 | uint8_t *ptr; | |
3419 | uint64_t val; | |
3420 | MemTxResult result = MEMTX_OK; | |
3421 | bool release_lock = false; | |
eb7eeb88 | 3422 | |
a203ac70 | 3423 | for (;;) { |
eb7eeb88 PB |
3424 | if (!memory_access_is_direct(mr, false)) { |
3425 | /* I/O case */ | |
3426 | release_lock |= prepare_mmio_access(mr); | |
3427 | l = memory_access_size(mr, l, addr1); | |
6d3ede54 PM |
3428 | result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs); |
3429 | stn_p(buf, l, val); | |
eb7eeb88 PB |
3430 | } else { |
3431 | /* RAM case */ | |
f5aa69bd | 3432 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
eb7eeb88 PB |
3433 | memcpy(buf, ptr, l); |
3434 | } | |
3435 | ||
3436 | if (release_lock) { | |
3437 | qemu_mutex_unlock_iothread(); | |
3438 | release_lock = false; | |
3439 | } | |
3440 | ||
3441 | len -= l; | |
3442 | buf += l; | |
3443 | addr += l; | |
a203ac70 PB |
3444 | |
3445 | if (!len) { | |
3446 | break; | |
3447 | } | |
3448 | ||
3449 | l = len; | |
efa99a2f | 3450 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); |
a203ac70 PB |
3451 | } |
3452 | ||
3453 | return result; | |
3454 | } | |
3455 | ||
b2a44fca PB |
3456 | /* Called from RCU critical section. */ |
3457 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, | |
0c249ff7 | 3458 | MemTxAttrs attrs, uint8_t *buf, hwaddr len) |
a203ac70 PB |
3459 | { |
3460 | hwaddr l; | |
3461 | hwaddr addr1; | |
3462 | MemoryRegion *mr; | |
eb7eeb88 | 3463 | |
b2a44fca | 3464 | l = len; |
efa99a2f | 3465 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); |
b2a44fca PB |
3466 | return flatview_read_continue(fv, addr, attrs, buf, len, |
3467 | addr1, l, mr); | |
ac1970fb AK |
3468 | } |
3469 | ||
b2a44fca | 3470 | MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, |
0c249ff7 | 3471 | MemTxAttrs attrs, uint8_t *buf, hwaddr len) |
b2a44fca PB |
3472 | { |
3473 | MemTxResult result = MEMTX_OK; | |
3474 | FlatView *fv; | |
3475 | ||
3476 | if (len > 0) { | |
3477 | rcu_read_lock(); | |
3478 | fv = address_space_to_flatview(as); | |
3479 | result = flatview_read(fv, addr, attrs, buf, len); | |
3480 | rcu_read_unlock(); | |
3481 | } | |
3482 | ||
3483 | return result; | |
3484 | } | |
3485 | ||
4c6ebbb3 PB |
3486 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, |
3487 | MemTxAttrs attrs, | |
0c249ff7 | 3488 | const uint8_t *buf, hwaddr len) |
4c6ebbb3 PB |
3489 | { |
3490 | MemTxResult result = MEMTX_OK; | |
3491 | FlatView *fv; | |
3492 | ||
3493 | if (len > 0) { | |
3494 | rcu_read_lock(); | |
3495 | fv = address_space_to_flatview(as); | |
3496 | result = flatview_write(fv, addr, attrs, buf, len); | |
3497 | rcu_read_unlock(); | |
3498 | } | |
3499 | ||
3500 | return result; | |
3501 | } | |
3502 | ||
db84fd97 | 3503 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, |
0c249ff7 | 3504 | uint8_t *buf, hwaddr len, bool is_write) |
db84fd97 PB |
3505 | { |
3506 | if (is_write) { | |
3507 | return address_space_write(as, addr, attrs, buf, len); | |
3508 | } else { | |
3509 | return address_space_read_full(as, addr, attrs, buf, len); | |
3510 | } | |
3511 | } | |
3512 | ||
a8170e5e | 3513 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
0c249ff7 | 3514 | hwaddr len, int is_write) |
ac1970fb | 3515 | { |
5c9eb028 PM |
3516 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, |
3517 | buf, len, is_write); | |
ac1970fb AK |
3518 | } |
3519 | ||
582b55a9 AG |
3520 | enum write_rom_type { |
3521 | WRITE_DATA, | |
3522 | FLUSH_CACHE, | |
3523 | }; | |
3524 | ||
75693e14 PM |
3525 | static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, |
3526 | hwaddr addr, | |
3527 | MemTxAttrs attrs, | |
3528 | const uint8_t *buf, | |
0c249ff7 | 3529 | hwaddr len, |
75693e14 | 3530 | enum write_rom_type type) |
d0ecd2aa | 3531 | { |
149f54b5 | 3532 | hwaddr l; |
d0ecd2aa | 3533 | uint8_t *ptr; |
149f54b5 | 3534 | hwaddr addr1; |
5c8a00ce | 3535 | MemoryRegion *mr; |
3b46e624 | 3536 | |
41063e1e | 3537 | rcu_read_lock(); |
d0ecd2aa | 3538 | while (len > 0) { |
149f54b5 | 3539 | l = len; |
75693e14 | 3540 | mr = address_space_translate(as, addr, &addr1, &l, true, attrs); |
3b46e624 | 3541 | |
5c8a00ce PB |
3542 | if (!(memory_region_is_ram(mr) || |
3543 | memory_region_is_romd(mr))) { | |
b242e0e0 | 3544 | l = memory_access_size(mr, l, addr1); |
d0ecd2aa | 3545 | } else { |
d0ecd2aa | 3546 | /* ROM/RAM case */ |
0878d0e1 | 3547 | ptr = qemu_map_ram_ptr(mr->ram_block, addr1); |
582b55a9 AG |
3548 | switch (type) { |
3549 | case WRITE_DATA: | |
3550 | memcpy(ptr, buf, l); | |
845b6214 | 3551 | invalidate_and_set_dirty(mr, addr1, l); |
582b55a9 AG |
3552 | break; |
3553 | case FLUSH_CACHE: | |
3554 | flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); | |
3555 | break; | |
3556 | } | |
d0ecd2aa FB |
3557 | } |
3558 | len -= l; | |
3559 | buf += l; | |
3560 | addr += l; | |
3561 | } | |
41063e1e | 3562 | rcu_read_unlock(); |
75693e14 | 3563 | return MEMTX_OK; |
d0ecd2aa FB |
3564 | } |
3565 | ||
582b55a9 | 3566 | /* used for ROM loading : can write in RAM and ROM */ |
3c8133f9 PM |
3567 | MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, |
3568 | MemTxAttrs attrs, | |
0c249ff7 | 3569 | const uint8_t *buf, hwaddr len) |
582b55a9 | 3570 | { |
3c8133f9 PM |
3571 | return address_space_write_rom_internal(as, addr, attrs, |
3572 | buf, len, WRITE_DATA); | |
582b55a9 AG |
3573 | } |
3574 | ||
0c249ff7 | 3575 | void cpu_flush_icache_range(hwaddr start, hwaddr len) |
582b55a9 AG |
3576 | { |
3577 | /* | |
3578 | * This function should do the same thing as an icache flush that was | |
3579 | * triggered from within the guest. For TCG we are always cache coherent, | |
3580 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
3581 | * the host's instruction cache at least. | |
3582 | */ | |
3583 | if (tcg_enabled()) { | |
3584 | return; | |
3585 | } | |
3586 | ||
75693e14 PM |
3587 | address_space_write_rom_internal(&address_space_memory, |
3588 | start, MEMTXATTRS_UNSPECIFIED, | |
3589 | NULL, len, FLUSH_CACHE); | |
582b55a9 AG |
3590 | } |
3591 | ||
6d16c2f8 | 3592 | typedef struct { |
d3e71559 | 3593 | MemoryRegion *mr; |
6d16c2f8 | 3594 | void *buffer; |
a8170e5e AK |
3595 | hwaddr addr; |
3596 | hwaddr len; | |
c2cba0ff | 3597 | bool in_use; |
6d16c2f8 AL |
3598 | } BounceBuffer; |
3599 | ||
3600 | static BounceBuffer bounce; | |
3601 | ||
ba223c29 | 3602 | typedef struct MapClient { |
e95205e1 | 3603 | QEMUBH *bh; |
72cf2d4f | 3604 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3605 | } MapClient; |
3606 | ||
38e047b5 | 3607 | QemuMutex map_client_list_lock; |
b58deb34 | 3608 | static QLIST_HEAD(, MapClient) map_client_list |
72cf2d4f | 3609 | = QLIST_HEAD_INITIALIZER(map_client_list); |
ba223c29 | 3610 | |
e95205e1 FZ |
3611 | static void cpu_unregister_map_client_do(MapClient *client) |
3612 | { | |
3613 | QLIST_REMOVE(client, link); | |
3614 | g_free(client); | |
3615 | } | |
3616 | ||
33b6c2ed FZ |
3617 | static void cpu_notify_map_clients_locked(void) |
3618 | { | |
3619 | MapClient *client; | |
3620 | ||
3621 | while (!QLIST_EMPTY(&map_client_list)) { | |
3622 | client = QLIST_FIRST(&map_client_list); | |
e95205e1 FZ |
3623 | qemu_bh_schedule(client->bh); |
3624 | cpu_unregister_map_client_do(client); | |
33b6c2ed FZ |
3625 | } |
3626 | } | |
3627 | ||
e95205e1 | 3628 | void cpu_register_map_client(QEMUBH *bh) |
ba223c29 | 3629 | { |
7267c094 | 3630 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 | 3631 | |
38e047b5 | 3632 | qemu_mutex_lock(&map_client_list_lock); |
e95205e1 | 3633 | client->bh = bh; |
72cf2d4f | 3634 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
33b6c2ed FZ |
3635 | if (!atomic_read(&bounce.in_use)) { |
3636 | cpu_notify_map_clients_locked(); | |
3637 | } | |
38e047b5 | 3638 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3639 | } |
3640 | ||
38e047b5 | 3641 | void cpu_exec_init_all(void) |
ba223c29 | 3642 | { |
38e047b5 | 3643 | qemu_mutex_init(&ram_list.mutex); |
20bccb82 PM |
3644 | /* The data structures we set up here depend on knowing the page size, |
3645 | * so no more changes can be made after this point. | |
3646 | * In an ideal world, nothing we did before we had finished the | |
3647 | * machine setup would care about the target page size, and we could | |
3648 | * do this much later, rather than requiring board models to state | |
3649 | * up front what their requirements are. | |
3650 | */ | |
3651 | finalize_target_page_bits(); | |
38e047b5 | 3652 | io_mem_init(); |
680a4783 | 3653 | memory_map_init(); |
38e047b5 | 3654 | qemu_mutex_init(&map_client_list_lock); |
ba223c29 AL |
3655 | } |
3656 | ||
e95205e1 | 3657 | void cpu_unregister_map_client(QEMUBH *bh) |
ba223c29 AL |
3658 | { |
3659 | MapClient *client; | |
3660 | ||
e95205e1 FZ |
3661 | qemu_mutex_lock(&map_client_list_lock); |
3662 | QLIST_FOREACH(client, &map_client_list, link) { | |
3663 | if (client->bh == bh) { | |
3664 | cpu_unregister_map_client_do(client); | |
3665 | break; | |
3666 | } | |
ba223c29 | 3667 | } |
e95205e1 | 3668 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3669 | } |
3670 | ||
3671 | static void cpu_notify_map_clients(void) | |
3672 | { | |
38e047b5 | 3673 | qemu_mutex_lock(&map_client_list_lock); |
33b6c2ed | 3674 | cpu_notify_map_clients_locked(); |
38e047b5 | 3675 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3676 | } |
3677 | ||
0c249ff7 | 3678 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len, |
eace72b7 | 3679 | bool is_write, MemTxAttrs attrs) |
51644ab7 | 3680 | { |
5c8a00ce | 3681 | MemoryRegion *mr; |
51644ab7 PB |
3682 | hwaddr l, xlat; |
3683 | ||
3684 | while (len > 0) { | |
3685 | l = len; | |
efa99a2f | 3686 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); |
5c8a00ce PB |
3687 | if (!memory_access_is_direct(mr, is_write)) { |
3688 | l = memory_access_size(mr, l, addr); | |
eace72b7 | 3689 | if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) { |
51644ab7 PB |
3690 | return false; |
3691 | } | |
3692 | } | |
3693 | ||
3694 | len -= l; | |
3695 | addr += l; | |
3696 | } | |
3697 | return true; | |
3698 | } | |
3699 | ||
16620684 | 3700 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, |
0c249ff7 | 3701 | hwaddr len, bool is_write, |
fddffa42 | 3702 | MemTxAttrs attrs) |
16620684 | 3703 | { |
11e732a5 PB |
3704 | FlatView *fv; |
3705 | bool result; | |
3706 | ||
3707 | rcu_read_lock(); | |
3708 | fv = address_space_to_flatview(as); | |
eace72b7 | 3709 | result = flatview_access_valid(fv, addr, len, is_write, attrs); |
11e732a5 PB |
3710 | rcu_read_unlock(); |
3711 | return result; | |
16620684 AK |
3712 | } |
3713 | ||
715c31ec | 3714 | static hwaddr |
16620684 | 3715 | flatview_extend_translation(FlatView *fv, hwaddr addr, |
53d0790d PM |
3716 | hwaddr target_len, |
3717 | MemoryRegion *mr, hwaddr base, hwaddr len, | |
3718 | bool is_write, MemTxAttrs attrs) | |
715c31ec PB |
3719 | { |
3720 | hwaddr done = 0; | |
3721 | hwaddr xlat; | |
3722 | MemoryRegion *this_mr; | |
3723 | ||
3724 | for (;;) { | |
3725 | target_len -= len; | |
3726 | addr += len; | |
3727 | done += len; | |
3728 | if (target_len == 0) { | |
3729 | return done; | |
3730 | } | |
3731 | ||
3732 | len = target_len; | |
16620684 | 3733 | this_mr = flatview_translate(fv, addr, &xlat, |
efa99a2f | 3734 | &len, is_write, attrs); |
715c31ec PB |
3735 | if (this_mr != mr || xlat != base + done) { |
3736 | return done; | |
3737 | } | |
3738 | } | |
3739 | } | |
3740 | ||
6d16c2f8 AL |
3741 | /* Map a physical memory region into a host virtual address. |
3742 | * May map a subset of the requested range, given by and returned in *plen. | |
3743 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3744 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3745 | * Use cpu_register_map_client() to know when retrying the map operation is |
3746 | * likely to succeed. | |
6d16c2f8 | 3747 | */ |
ac1970fb | 3748 | void *address_space_map(AddressSpace *as, |
a8170e5e AK |
3749 | hwaddr addr, |
3750 | hwaddr *plen, | |
f26404fb PM |
3751 | bool is_write, |
3752 | MemTxAttrs attrs) | |
6d16c2f8 | 3753 | { |
a8170e5e | 3754 | hwaddr len = *plen; |
715c31ec PB |
3755 | hwaddr l, xlat; |
3756 | MemoryRegion *mr; | |
e81bcda5 | 3757 | void *ptr; |
ad0c60fa | 3758 | FlatView *fv; |
6d16c2f8 | 3759 | |
e3127ae0 PB |
3760 | if (len == 0) { |
3761 | return NULL; | |
3762 | } | |
38bee5dc | 3763 | |
e3127ae0 | 3764 | l = len; |
41063e1e | 3765 | rcu_read_lock(); |
ad0c60fa | 3766 | fv = address_space_to_flatview(as); |
efa99a2f | 3767 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); |
41063e1e | 3768 | |
e3127ae0 | 3769 | if (!memory_access_is_direct(mr, is_write)) { |
c2cba0ff | 3770 | if (atomic_xchg(&bounce.in_use, true)) { |
41063e1e | 3771 | rcu_read_unlock(); |
e3127ae0 | 3772 | return NULL; |
6d16c2f8 | 3773 | } |
e85d9db5 KW |
3774 | /* Avoid unbounded allocations */ |
3775 | l = MIN(l, TARGET_PAGE_SIZE); | |
3776 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
e3127ae0 PB |
3777 | bounce.addr = addr; |
3778 | bounce.len = l; | |
d3e71559 PB |
3779 | |
3780 | memory_region_ref(mr); | |
3781 | bounce.mr = mr; | |
e3127ae0 | 3782 | if (!is_write) { |
16620684 | 3783 | flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED, |
5c9eb028 | 3784 | bounce.buffer, l); |
8ab934f9 | 3785 | } |
6d16c2f8 | 3786 | |
41063e1e | 3787 | rcu_read_unlock(); |
e3127ae0 PB |
3788 | *plen = l; |
3789 | return bounce.buffer; | |
3790 | } | |
3791 | ||
e3127ae0 | 3792 | |
d3e71559 | 3793 | memory_region_ref(mr); |
16620684 | 3794 | *plen = flatview_extend_translation(fv, addr, len, mr, xlat, |
53d0790d | 3795 | l, is_write, attrs); |
f5aa69bd | 3796 | ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); |
e81bcda5 PB |
3797 | rcu_read_unlock(); |
3798 | ||
3799 | return ptr; | |
6d16c2f8 AL |
3800 | } |
3801 | ||
ac1970fb | 3802 | /* Unmaps a memory region previously mapped by address_space_map(). |
6d16c2f8 AL |
3803 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
3804 | * the amount of memory that was actually read or written by the caller. | |
3805 | */ | |
a8170e5e AK |
3806 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
3807 | int is_write, hwaddr access_len) | |
6d16c2f8 AL |
3808 | { |
3809 | if (buffer != bounce.buffer) { | |
d3e71559 PB |
3810 | MemoryRegion *mr; |
3811 | ram_addr_t addr1; | |
3812 | ||
07bdaa41 | 3813 | mr = memory_region_from_host(buffer, &addr1); |
d3e71559 | 3814 | assert(mr != NULL); |
6d16c2f8 | 3815 | if (is_write) { |
845b6214 | 3816 | invalidate_and_set_dirty(mr, addr1, access_len); |
6d16c2f8 | 3817 | } |
868bb33f | 3818 | if (xen_enabled()) { |
e41d7c69 | 3819 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 3820 | } |
d3e71559 | 3821 | memory_region_unref(mr); |
6d16c2f8 AL |
3822 | return; |
3823 | } | |
3824 | if (is_write) { | |
5c9eb028 PM |
3825 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, |
3826 | bounce.buffer, access_len); | |
6d16c2f8 | 3827 | } |
f8a83245 | 3828 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3829 | bounce.buffer = NULL; |
d3e71559 | 3830 | memory_region_unref(bounce.mr); |
c2cba0ff | 3831 | atomic_mb_set(&bounce.in_use, false); |
ba223c29 | 3832 | cpu_notify_map_clients(); |
6d16c2f8 | 3833 | } |
d0ecd2aa | 3834 | |
a8170e5e AK |
3835 | void *cpu_physical_memory_map(hwaddr addr, |
3836 | hwaddr *plen, | |
ac1970fb AK |
3837 | int is_write) |
3838 | { | |
f26404fb PM |
3839 | return address_space_map(&address_space_memory, addr, plen, is_write, |
3840 | MEMTXATTRS_UNSPECIFIED); | |
ac1970fb AK |
3841 | } |
3842 | ||
a8170e5e AK |
3843 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
3844 | int is_write, hwaddr access_len) | |
ac1970fb AK |
3845 | { |
3846 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
3847 | } | |
3848 | ||
0ce265ff PB |
3849 | #define ARG1_DECL AddressSpace *as |
3850 | #define ARG1 as | |
3851 | #define SUFFIX | |
3852 | #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) | |
0ce265ff PB |
3853 | #define RCU_READ_LOCK(...) rcu_read_lock() |
3854 | #define RCU_READ_UNLOCK(...) rcu_read_unlock() | |
3855 | #include "memory_ldst.inc.c" | |
1e78bcc1 | 3856 | |
1f4e496e PB |
3857 | int64_t address_space_cache_init(MemoryRegionCache *cache, |
3858 | AddressSpace *as, | |
3859 | hwaddr addr, | |
3860 | hwaddr len, | |
3861 | bool is_write) | |
3862 | { | |
48564041 PB |
3863 | AddressSpaceDispatch *d; |
3864 | hwaddr l; | |
3865 | MemoryRegion *mr; | |
3866 | ||
3867 | assert(len > 0); | |
3868 | ||
3869 | l = len; | |
3870 | cache->fv = address_space_get_flatview(as); | |
3871 | d = flatview_to_dispatch(cache->fv); | |
3872 | cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true); | |
3873 | ||
3874 | mr = cache->mrs.mr; | |
3875 | memory_region_ref(mr); | |
3876 | if (memory_access_is_direct(mr, is_write)) { | |
53d0790d PM |
3877 | /* We don't care about the memory attributes here as we're only |
3878 | * doing this if we found actual RAM, which behaves the same | |
3879 | * regardless of attributes; so UNSPECIFIED is fine. | |
3880 | */ | |
48564041 | 3881 | l = flatview_extend_translation(cache->fv, addr, len, mr, |
53d0790d PM |
3882 | cache->xlat, l, is_write, |
3883 | MEMTXATTRS_UNSPECIFIED); | |
48564041 PB |
3884 | cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true); |
3885 | } else { | |
3886 | cache->ptr = NULL; | |
3887 | } | |
3888 | ||
3889 | cache->len = l; | |
3890 | cache->is_write = is_write; | |
3891 | return l; | |
1f4e496e PB |
3892 | } |
3893 | ||
3894 | void address_space_cache_invalidate(MemoryRegionCache *cache, | |
3895 | hwaddr addr, | |
3896 | hwaddr access_len) | |
3897 | { | |
48564041 PB |
3898 | assert(cache->is_write); |
3899 | if (likely(cache->ptr)) { | |
3900 | invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len); | |
3901 | } | |
1f4e496e PB |
3902 | } |
3903 | ||
3904 | void address_space_cache_destroy(MemoryRegionCache *cache) | |
3905 | { | |
48564041 PB |
3906 | if (!cache->mrs.mr) { |
3907 | return; | |
3908 | } | |
3909 | ||
3910 | if (xen_enabled()) { | |
3911 | xen_invalidate_map_cache_entry(cache->ptr); | |
3912 | } | |
3913 | memory_region_unref(cache->mrs.mr); | |
3914 | flatview_unref(cache->fv); | |
3915 | cache->mrs.mr = NULL; | |
3916 | cache->fv = NULL; | |
3917 | } | |
3918 | ||
3919 | /* Called from RCU critical section. This function has the same | |
3920 | * semantics as address_space_translate, but it only works on a | |
3921 | * predefined range of a MemoryRegion that was mapped with | |
3922 | * address_space_cache_init. | |
3923 | */ | |
3924 | static inline MemoryRegion *address_space_translate_cached( | |
3925 | MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat, | |
bc6b1cec | 3926 | hwaddr *plen, bool is_write, MemTxAttrs attrs) |
48564041 PB |
3927 | { |
3928 | MemoryRegionSection section; | |
3929 | MemoryRegion *mr; | |
3930 | IOMMUMemoryRegion *iommu_mr; | |
3931 | AddressSpace *target_as; | |
3932 | ||
3933 | assert(!cache->ptr); | |
3934 | *xlat = addr + cache->xlat; | |
3935 | ||
3936 | mr = cache->mrs.mr; | |
3937 | iommu_mr = memory_region_get_iommu(mr); | |
3938 | if (!iommu_mr) { | |
3939 | /* MMIO region. */ | |
3940 | return mr; | |
3941 | } | |
3942 | ||
3943 | section = address_space_translate_iommu(iommu_mr, xlat, plen, | |
3944 | NULL, is_write, true, | |
2f7b009c | 3945 | &target_as, attrs); |
48564041 PB |
3946 | return section.mr; |
3947 | } | |
3948 | ||
3949 | /* Called from RCU critical section. address_space_read_cached uses this | |
3950 | * out of line function when the target is an MMIO or IOMMU region. | |
3951 | */ | |
3952 | void | |
3953 | address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr, | |
0c249ff7 | 3954 | void *buf, hwaddr len) |
48564041 PB |
3955 | { |
3956 | hwaddr addr1, l; | |
3957 | MemoryRegion *mr; | |
3958 | ||
3959 | l = len; | |
bc6b1cec PM |
3960 | mr = address_space_translate_cached(cache, addr, &addr1, &l, false, |
3961 | MEMTXATTRS_UNSPECIFIED); | |
48564041 PB |
3962 | flatview_read_continue(cache->fv, |
3963 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3964 | addr1, l, mr); | |
3965 | } | |
3966 | ||
3967 | /* Called from RCU critical section. address_space_write_cached uses this | |
3968 | * out of line function when the target is an MMIO or IOMMU region. | |
3969 | */ | |
3970 | void | |
3971 | address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, | |
0c249ff7 | 3972 | const void *buf, hwaddr len) |
48564041 PB |
3973 | { |
3974 | hwaddr addr1, l; | |
3975 | MemoryRegion *mr; | |
3976 | ||
3977 | l = len; | |
bc6b1cec PM |
3978 | mr = address_space_translate_cached(cache, addr, &addr1, &l, true, |
3979 | MEMTXATTRS_UNSPECIFIED); | |
48564041 PB |
3980 | flatview_write_continue(cache->fv, |
3981 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3982 | addr1, l, mr); | |
1f4e496e PB |
3983 | } |
3984 | ||
3985 | #define ARG1_DECL MemoryRegionCache *cache | |
3986 | #define ARG1 cache | |
48564041 PB |
3987 | #define SUFFIX _cached_slow |
3988 | #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__) | |
48564041 PB |
3989 | #define RCU_READ_LOCK() ((void)0) |
3990 | #define RCU_READ_UNLOCK() ((void)0) | |
1f4e496e PB |
3991 | #include "memory_ldst.inc.c" |
3992 | ||
5e2972fd | 3993 | /* virtual memory access for debug (includes writing to ROM) */ |
f17ec444 | 3994 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
0c249ff7 | 3995 | uint8_t *buf, target_ulong len, int is_write) |
13eb76e0 | 3996 | { |
a8170e5e | 3997 | hwaddr phys_addr; |
0c249ff7 | 3998 | target_ulong l, page; |
13eb76e0 | 3999 | |
79ca7a1b | 4000 | cpu_synchronize_state(cpu); |
13eb76e0 | 4001 | while (len > 0) { |
5232e4c7 PM |
4002 | int asidx; |
4003 | MemTxAttrs attrs; | |
4004 | ||
13eb76e0 | 4005 | page = addr & TARGET_PAGE_MASK; |
5232e4c7 PM |
4006 | phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); |
4007 | asidx = cpu_asidx_from_attrs(cpu, attrs); | |
13eb76e0 FB |
4008 | /* if no physical page mapped, return an error */ |
4009 | if (phys_addr == -1) | |
4010 | return -1; | |
4011 | l = (page + TARGET_PAGE_SIZE) - addr; | |
4012 | if (l > len) | |
4013 | l = len; | |
5e2972fd | 4014 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
2e38847b | 4015 | if (is_write) { |
3c8133f9 | 4016 | address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, |
ea7a5330 | 4017 | attrs, buf, l); |
2e38847b | 4018 | } else { |
5232e4c7 | 4019 | address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, |
ea7a5330 | 4020 | attrs, buf, l, 0); |
2e38847b | 4021 | } |
13eb76e0 FB |
4022 | len -= l; |
4023 | buf += l; | |
4024 | addr += l; | |
4025 | } | |
4026 | return 0; | |
4027 | } | |
038629a6 DDAG |
4028 | |
4029 | /* | |
4030 | * Allows code that needs to deal with migration bitmaps etc to still be built | |
4031 | * target independent. | |
4032 | */ | |
20afaed9 | 4033 | size_t qemu_target_page_size(void) |
038629a6 | 4034 | { |
20afaed9 | 4035 | return TARGET_PAGE_SIZE; |
038629a6 DDAG |
4036 | } |
4037 | ||
46d702b1 JQ |
4038 | int qemu_target_page_bits(void) |
4039 | { | |
4040 | return TARGET_PAGE_BITS; | |
4041 | } | |
4042 | ||
4043 | int qemu_target_page_bits_min(void) | |
4044 | { | |
4045 | return TARGET_PAGE_BITS_MIN; | |
4046 | } | |
a68fe89c | 4047 | #endif |
13eb76e0 | 4048 | |
98ed8ecf | 4049 | bool target_words_bigendian(void) |
8e4a424b BS |
4050 | { |
4051 | #if defined(TARGET_WORDS_BIGENDIAN) | |
4052 | return true; | |
4053 | #else | |
4054 | return false; | |
4055 | #endif | |
4056 | } | |
4057 | ||
76f35538 | 4058 | #ifndef CONFIG_USER_ONLY |
a8170e5e | 4059 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
76f35538 | 4060 | { |
5c8a00ce | 4061 | MemoryRegion*mr; |
149f54b5 | 4062 | hwaddr l = 1; |
41063e1e | 4063 | bool res; |
76f35538 | 4064 | |
41063e1e | 4065 | rcu_read_lock(); |
5c8a00ce | 4066 | mr = address_space_translate(&address_space_memory, |
bc6b1cec PM |
4067 | phys_addr, &phys_addr, &l, false, |
4068 | MEMTXATTRS_UNSPECIFIED); | |
76f35538 | 4069 | |
41063e1e PB |
4070 | res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); |
4071 | rcu_read_unlock(); | |
4072 | return res; | |
76f35538 | 4073 | } |
bd2fa51f | 4074 | |
e3807054 | 4075 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) |
bd2fa51f MH |
4076 | { |
4077 | RAMBlock *block; | |
e3807054 | 4078 | int ret = 0; |
bd2fa51f | 4079 | |
0dc3f44a | 4080 | rcu_read_lock(); |
99e15582 | 4081 | RAMBLOCK_FOREACH(block) { |
754cb9c0 | 4082 | ret = func(block, opaque); |
e3807054 DDAG |
4083 | if (ret) { |
4084 | break; | |
4085 | } | |
bd2fa51f | 4086 | } |
0dc3f44a | 4087 | rcu_read_unlock(); |
e3807054 | 4088 | return ret; |
bd2fa51f | 4089 | } |
d3a5038c DDAG |
4090 | |
4091 | /* | |
4092 | * Unmap pages of memory from start to start+length such that | |
4093 | * they a) read as 0, b) Trigger whatever fault mechanism | |
4094 | * the OS provides for postcopy. | |
4095 | * The pages must be unmapped by the end of the function. | |
4096 | * Returns: 0 on success, none-0 on failure | |
4097 | * | |
4098 | */ | |
4099 | int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length) | |
4100 | { | |
4101 | int ret = -1; | |
4102 | ||
4103 | uint8_t *host_startaddr = rb->host + start; | |
4104 | ||
4105 | if ((uintptr_t)host_startaddr & (rb->page_size - 1)) { | |
4106 | error_report("ram_block_discard_range: Unaligned start address: %p", | |
4107 | host_startaddr); | |
4108 | goto err; | |
4109 | } | |
4110 | ||
4111 | if ((start + length) <= rb->used_length) { | |
db144f70 | 4112 | bool need_madvise, need_fallocate; |
d3a5038c DDAG |
4113 | uint8_t *host_endaddr = host_startaddr + length; |
4114 | if ((uintptr_t)host_endaddr & (rb->page_size - 1)) { | |
4115 | error_report("ram_block_discard_range: Unaligned end address: %p", | |
4116 | host_endaddr); | |
4117 | goto err; | |
4118 | } | |
4119 | ||
4120 | errno = ENOTSUP; /* If we are missing MADVISE etc */ | |
4121 | ||
db144f70 DDAG |
4122 | /* The logic here is messy; |
4123 | * madvise DONTNEED fails for hugepages | |
4124 | * fallocate works on hugepages and shmem | |
4125 | */ | |
4126 | need_madvise = (rb->page_size == qemu_host_page_size); | |
4127 | need_fallocate = rb->fd != -1; | |
4128 | if (need_fallocate) { | |
4129 | /* For a file, this causes the area of the file to be zero'd | |
4130 | * if read, and for hugetlbfs also causes it to be unmapped | |
4131 | * so a userfault will trigger. | |
e2fa71f5 DDAG |
4132 | */ |
4133 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
4134 | ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, | |
4135 | start, length); | |
db144f70 DDAG |
4136 | if (ret) { |
4137 | ret = -errno; | |
4138 | error_report("ram_block_discard_range: Failed to fallocate " | |
4139 | "%s:%" PRIx64 " +%zx (%d)", | |
4140 | rb->idstr, start, length, ret); | |
4141 | goto err; | |
4142 | } | |
4143 | #else | |
4144 | ret = -ENOSYS; | |
4145 | error_report("ram_block_discard_range: fallocate not available/file" | |
4146 | "%s:%" PRIx64 " +%zx (%d)", | |
4147 | rb->idstr, start, length, ret); | |
4148 | goto err; | |
e2fa71f5 DDAG |
4149 | #endif |
4150 | } | |
db144f70 DDAG |
4151 | if (need_madvise) { |
4152 | /* For normal RAM this causes it to be unmapped, | |
4153 | * for shared memory it causes the local mapping to disappear | |
4154 | * and to fall back on the file contents (which we just | |
4155 | * fallocate'd away). | |
4156 | */ | |
4157 | #if defined(CONFIG_MADVISE) | |
4158 | ret = madvise(host_startaddr, length, MADV_DONTNEED); | |
4159 | if (ret) { | |
4160 | ret = -errno; | |
4161 | error_report("ram_block_discard_range: Failed to discard range " | |
4162 | "%s:%" PRIx64 " +%zx (%d)", | |
4163 | rb->idstr, start, length, ret); | |
4164 | goto err; | |
4165 | } | |
4166 | #else | |
4167 | ret = -ENOSYS; | |
4168 | error_report("ram_block_discard_range: MADVISE not available" | |
d3a5038c DDAG |
4169 | "%s:%" PRIx64 " +%zx (%d)", |
4170 | rb->idstr, start, length, ret); | |
db144f70 DDAG |
4171 | goto err; |
4172 | #endif | |
d3a5038c | 4173 | } |
db144f70 DDAG |
4174 | trace_ram_block_discard_range(rb->idstr, host_startaddr, length, |
4175 | need_madvise, need_fallocate, ret); | |
d3a5038c DDAG |
4176 | } else { |
4177 | error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64 | |
4178 | "/%zx/" RAM_ADDR_FMT")", | |
4179 | rb->idstr, start, length, rb->used_length); | |
4180 | } | |
4181 | ||
4182 | err: | |
4183 | return ret; | |
4184 | } | |
4185 | ||
a4de8552 JH |
4186 | bool ramblock_is_pmem(RAMBlock *rb) |
4187 | { | |
4188 | return rb->flags & RAM_PMEM; | |
4189 | } | |
4190 | ||
ec3f8c99 | 4191 | #endif |
a0be0c58 YZ |
4192 | |
4193 | void page_size_init(void) | |
4194 | { | |
4195 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
4196 | TARGET_PAGE_SIZE */ | |
a0be0c58 YZ |
4197 | if (qemu_host_page_size == 0) { |
4198 | qemu_host_page_size = qemu_real_host_page_size; | |
4199 | } | |
4200 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
4201 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
4202 | } | |
4203 | qemu_host_page_mask = -(intptr_t)qemu_host_page_size; | |
4204 | } | |
5e8fd947 AK |
4205 | |
4206 | #if !defined(CONFIG_USER_ONLY) | |
4207 | ||
b6b71cb5 | 4208 | static void mtree_print_phys_entries(int start, int end, int skip, int ptr) |
5e8fd947 AK |
4209 | { |
4210 | if (start == end - 1) { | |
b6b71cb5 | 4211 | qemu_printf("\t%3d ", start); |
5e8fd947 | 4212 | } else { |
b6b71cb5 | 4213 | qemu_printf("\t%3d..%-3d ", start, end - 1); |
5e8fd947 | 4214 | } |
b6b71cb5 | 4215 | qemu_printf(" skip=%d ", skip); |
5e8fd947 | 4216 | if (ptr == PHYS_MAP_NODE_NIL) { |
b6b71cb5 | 4217 | qemu_printf(" ptr=NIL"); |
5e8fd947 | 4218 | } else if (!skip) { |
b6b71cb5 | 4219 | qemu_printf(" ptr=#%d", ptr); |
5e8fd947 | 4220 | } else { |
b6b71cb5 | 4221 | qemu_printf(" ptr=[%d]", ptr); |
5e8fd947 | 4222 | } |
b6b71cb5 | 4223 | qemu_printf("\n"); |
5e8fd947 AK |
4224 | } |
4225 | ||
4226 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ | |
4227 | int128_sub((size), int128_one())) : 0) | |
4228 | ||
b6b71cb5 | 4229 | void mtree_print_dispatch(AddressSpaceDispatch *d, MemoryRegion *root) |
5e8fd947 AK |
4230 | { |
4231 | int i; | |
4232 | ||
b6b71cb5 MA |
4233 | qemu_printf(" Dispatch\n"); |
4234 | qemu_printf(" Physical sections\n"); | |
5e8fd947 AK |
4235 | |
4236 | for (i = 0; i < d->map.sections_nb; ++i) { | |
4237 | MemoryRegionSection *s = d->map.sections + i; | |
4238 | const char *names[] = { " [unassigned]", " [not dirty]", | |
4239 | " [ROM]", " [watch]" }; | |
4240 | ||
b6b71cb5 MA |
4241 | qemu_printf(" #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx |
4242 | " %s%s%s%s%s", | |
5e8fd947 AK |
4243 | i, |
4244 | s->offset_within_address_space, | |
4245 | s->offset_within_address_space + MR_SIZE(s->mr->size), | |
4246 | s->mr->name ? s->mr->name : "(noname)", | |
4247 | i < ARRAY_SIZE(names) ? names[i] : "", | |
4248 | s->mr == root ? " [ROOT]" : "", | |
4249 | s == d->mru_section ? " [MRU]" : "", | |
4250 | s->mr->is_iommu ? " [iommu]" : ""); | |
4251 | ||
4252 | if (s->mr->alias) { | |
b6b71cb5 | 4253 | qemu_printf(" alias=%s", s->mr->alias->name ? |
5e8fd947 AK |
4254 | s->mr->alias->name : "noname"); |
4255 | } | |
b6b71cb5 | 4256 | qemu_printf("\n"); |
5e8fd947 AK |
4257 | } |
4258 | ||
b6b71cb5 | 4259 | qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n", |
5e8fd947 AK |
4260 | P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip); |
4261 | for (i = 0; i < d->map.nodes_nb; ++i) { | |
4262 | int j, jprev; | |
4263 | PhysPageEntry prev; | |
4264 | Node *n = d->map.nodes + i; | |
4265 | ||
b6b71cb5 | 4266 | qemu_printf(" [%d]\n", i); |
5e8fd947 AK |
4267 | |
4268 | for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) { | |
4269 | PhysPageEntry *pe = *n + j; | |
4270 | ||
4271 | if (pe->ptr == prev.ptr && pe->skip == prev.skip) { | |
4272 | continue; | |
4273 | } | |
4274 | ||
b6b71cb5 | 4275 | mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr); |
5e8fd947 AK |
4276 | |
4277 | jprev = j; | |
4278 | prev = *pe; | |
4279 | } | |
4280 | ||
4281 | if (jprev != ARRAY_SIZE(*n)) { | |
b6b71cb5 | 4282 | mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr); |
5e8fd947 AK |
4283 | } |
4284 | } | |
4285 | } | |
4286 | ||
4287 | #endif |