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Commit | Line | Data |
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54936004 | 1 | /* |
5b6dd868 | 2 | * Virtual page mapping |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
7b31bbc2 | 19 | #include "qemu/osdep.h" |
da34e65c | 20 | #include "qapi/error.h" |
54936004 | 21 | |
f348b6d1 | 22 | #include "qemu/cutils.h" |
6180a181 | 23 | #include "cpu.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
51180423 | 25 | #include "exec/target_page.h" |
b67d9a52 | 26 | #include "tcg.h" |
741da0d3 | 27 | #include "hw/qdev-core.h" |
c7e002c5 | 28 | #include "hw/qdev-properties.h" |
4485bd26 | 29 | #if !defined(CONFIG_USER_ONLY) |
47c8ca53 | 30 | #include "hw/boards.h" |
33c11879 | 31 | #include "hw/xen/xen.h" |
4485bd26 | 32 | #endif |
9c17d615 | 33 | #include "sysemu/kvm.h" |
2ff3de68 | 34 | #include "sysemu/sysemu.h" |
1de7afc9 PB |
35 | #include "qemu/timer.h" |
36 | #include "qemu/config-file.h" | |
75a34036 | 37 | #include "qemu/error-report.h" |
53a5960a | 38 | #if defined(CONFIG_USER_ONLY) |
a9c94277 | 39 | #include "qemu.h" |
432d268c | 40 | #else /* !CONFIG_USER_ONLY */ |
741da0d3 PB |
41 | #include "hw/hw.h" |
42 | #include "exec/memory.h" | |
df43d49c | 43 | #include "exec/ioport.h" |
741da0d3 | 44 | #include "sysemu/dma.h" |
9c607668 | 45 | #include "sysemu/numa.h" |
79ca7a1b | 46 | #include "sysemu/hw_accel.h" |
741da0d3 | 47 | #include "exec/address-spaces.h" |
9c17d615 | 48 | #include "sysemu/xen-mapcache.h" |
0ab8ed18 | 49 | #include "trace-root.h" |
d3a5038c | 50 | |
e2fa71f5 | 51 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE |
e2fa71f5 DDAG |
52 | #include <linux/falloc.h> |
53 | #endif | |
54 | ||
53a5960a | 55 | #endif |
0dc3f44a | 56 | #include "qemu/rcu_queue.h" |
4840f10e | 57 | #include "qemu/main-loop.h" |
5b6dd868 | 58 | #include "translate-all.h" |
7615936e | 59 | #include "sysemu/replay.h" |
0cac1b66 | 60 | |
022c62cb | 61 | #include "exec/memory-internal.h" |
220c3ebd | 62 | #include "exec/ram_addr.h" |
508127e2 | 63 | #include "exec/log.h" |
67d95c15 | 64 | |
9dfeca7c BR |
65 | #include "migration/vmstate.h" |
66 | ||
b35ba30f | 67 | #include "qemu/range.h" |
794e8f30 MT |
68 | #ifndef _WIN32 |
69 | #include "qemu/mmap-alloc.h" | |
70 | #endif | |
b35ba30f | 71 | |
be9b23c4 PX |
72 | #include "monitor/monitor.h" |
73 | ||
db7b5426 | 74 | //#define DEBUG_SUBPAGE |
1196be37 | 75 | |
e2eef170 | 76 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a MD |
77 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes |
78 | * are protected by the ramlist lock. | |
79 | */ | |
0d53d9fe | 80 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
81 | |
82 | static MemoryRegion *system_memory; | |
309cb471 | 83 | static MemoryRegion *system_io; |
62152b8a | 84 | |
f6790af6 AK |
85 | AddressSpace address_space_io; |
86 | AddressSpace address_space_memory; | |
2673a5da | 87 | |
0844e007 | 88 | MemoryRegion io_mem_rom, io_mem_notdirty; |
acc9d80b | 89 | static MemoryRegion io_mem_unassigned; |
0e0df1e2 | 90 | |
7bd4f430 PB |
91 | /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ |
92 | #define RAM_PREALLOC (1 << 0) | |
93 | ||
dbcb8981 PB |
94 | /* RAM is mmap-ed with MAP_SHARED */ |
95 | #define RAM_SHARED (1 << 1) | |
96 | ||
62be4e3a MT |
97 | /* Only a portion of RAM (used_length) is actually used, and migrated. |
98 | * This used_length size can change across reboots. | |
99 | */ | |
100 | #define RAM_RESIZEABLE (1 << 2) | |
101 | ||
2ce16640 DDAG |
102 | /* UFFDIO_ZEROPAGE is available on this RAMBlock to atomically |
103 | * zero the page and wake waiting processes. | |
104 | * (Set during postcopy) | |
105 | */ | |
106 | #define RAM_UF_ZEROPAGE (1 << 3) | |
e2eef170 | 107 | #endif |
9fa3e853 | 108 | |
20bccb82 PM |
109 | #ifdef TARGET_PAGE_BITS_VARY |
110 | int target_page_bits; | |
111 | bool target_page_bits_decided; | |
112 | #endif | |
113 | ||
bdc44640 | 114 | struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); |
6a00d601 FB |
115 | /* current CPU in the current thread. It is only valid inside |
116 | cpu_exec() */ | |
f240eb6f | 117 | __thread CPUState *current_cpu; |
2e70f6ef | 118 | /* 0 = Do not count executed instructions. |
bf20dc07 | 119 | 1 = Precise instruction counting. |
2e70f6ef | 120 | 2 = Adaptive rate instruction counting. */ |
5708fc66 | 121 | int use_icount; |
6a00d601 | 122 | |
a0be0c58 YZ |
123 | uintptr_t qemu_host_page_size; |
124 | intptr_t qemu_host_page_mask; | |
a0be0c58 | 125 | |
20bccb82 PM |
126 | bool set_preferred_target_page_bits(int bits) |
127 | { | |
128 | /* The target page size is the lowest common denominator for all | |
129 | * the CPUs in the system, so we can only make it smaller, never | |
130 | * larger. And we can't make it smaller once we've committed to | |
131 | * a particular size. | |
132 | */ | |
133 | #ifdef TARGET_PAGE_BITS_VARY | |
134 | assert(bits >= TARGET_PAGE_BITS_MIN); | |
135 | if (target_page_bits == 0 || target_page_bits > bits) { | |
136 | if (target_page_bits_decided) { | |
137 | return false; | |
138 | } | |
139 | target_page_bits = bits; | |
140 | } | |
141 | #endif | |
142 | return true; | |
143 | } | |
144 | ||
e2eef170 | 145 | #if !defined(CONFIG_USER_ONLY) |
4346ae3e | 146 | |
20bccb82 PM |
147 | static void finalize_target_page_bits(void) |
148 | { | |
149 | #ifdef TARGET_PAGE_BITS_VARY | |
150 | if (target_page_bits == 0) { | |
151 | target_page_bits = TARGET_PAGE_BITS_MIN; | |
152 | } | |
153 | target_page_bits_decided = true; | |
154 | #endif | |
155 | } | |
156 | ||
1db8abb1 PB |
157 | typedef struct PhysPageEntry PhysPageEntry; |
158 | ||
159 | struct PhysPageEntry { | |
9736e55b | 160 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ |
8b795765 | 161 | uint32_t skip : 6; |
9736e55b | 162 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ |
8b795765 | 163 | uint32_t ptr : 26; |
1db8abb1 PB |
164 | }; |
165 | ||
8b795765 MT |
166 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
167 | ||
03f49957 | 168 | /* Size of the L2 (and L3, etc) page tables. */ |
57271d63 | 169 | #define ADDR_SPACE_BITS 64 |
03f49957 | 170 | |
026736ce | 171 | #define P_L2_BITS 9 |
03f49957 PB |
172 | #define P_L2_SIZE (1 << P_L2_BITS) |
173 | ||
174 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
175 | ||
176 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
0475d94f | 177 | |
53cb28cb | 178 | typedef struct PhysPageMap { |
79e2b9ae PB |
179 | struct rcu_head rcu; |
180 | ||
53cb28cb MA |
181 | unsigned sections_nb; |
182 | unsigned sections_nb_alloc; | |
183 | unsigned nodes_nb; | |
184 | unsigned nodes_nb_alloc; | |
185 | Node *nodes; | |
186 | MemoryRegionSection *sections; | |
187 | } PhysPageMap; | |
188 | ||
1db8abb1 | 189 | struct AddressSpaceDispatch { |
729633c2 | 190 | MemoryRegionSection *mru_section; |
1db8abb1 PB |
191 | /* This is a multi-level map on the physical address space. |
192 | * The bottom level has pointers to MemoryRegionSections. | |
193 | */ | |
194 | PhysPageEntry phys_map; | |
53cb28cb | 195 | PhysPageMap map; |
1db8abb1 PB |
196 | }; |
197 | ||
90260c6c JK |
198 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
199 | typedef struct subpage_t { | |
200 | MemoryRegion iomem; | |
16620684 | 201 | FlatView *fv; |
90260c6c | 202 | hwaddr base; |
2615fabd | 203 | uint16_t sub_section[]; |
90260c6c JK |
204 | } subpage_t; |
205 | ||
b41aac4f LPF |
206 | #define PHYS_SECTION_UNASSIGNED 0 |
207 | #define PHYS_SECTION_NOTDIRTY 1 | |
208 | #define PHYS_SECTION_ROM 2 | |
209 | #define PHYS_SECTION_WATCH 3 | |
5312bd8b | 210 | |
e2eef170 | 211 | static void io_mem_init(void); |
62152b8a | 212 | static void memory_map_init(void); |
09daed84 | 213 | static void tcg_commit(MemoryListener *listener); |
e2eef170 | 214 | |
1ec9b909 | 215 | static MemoryRegion io_mem_watch; |
32857f4d PM |
216 | |
217 | /** | |
218 | * CPUAddressSpace: all the information a CPU needs about an AddressSpace | |
219 | * @cpu: the CPU whose AddressSpace this is | |
220 | * @as: the AddressSpace itself | |
221 | * @memory_dispatch: its dispatch pointer (cached, RCU protected) | |
222 | * @tcg_as_listener: listener for tracking changes to the AddressSpace | |
223 | */ | |
224 | struct CPUAddressSpace { | |
225 | CPUState *cpu; | |
226 | AddressSpace *as; | |
227 | struct AddressSpaceDispatch *memory_dispatch; | |
228 | MemoryListener tcg_as_listener; | |
229 | }; | |
230 | ||
8deaf12c GH |
231 | struct DirtyBitmapSnapshot { |
232 | ram_addr_t start; | |
233 | ram_addr_t end; | |
234 | unsigned long dirty[]; | |
235 | }; | |
236 | ||
6658ffb8 | 237 | #endif |
fd6ce8f6 | 238 | |
6d9a1304 | 239 | #if !defined(CONFIG_USER_ONLY) |
d6f2ea22 | 240 | |
53cb28cb | 241 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
d6f2ea22 | 242 | { |
101420b8 | 243 | static unsigned alloc_hint = 16; |
53cb28cb | 244 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { |
101420b8 | 245 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint); |
53cb28cb MA |
246 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); |
247 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); | |
101420b8 | 248 | alloc_hint = map->nodes_nb_alloc; |
d6f2ea22 | 249 | } |
f7bf5461 AK |
250 | } |
251 | ||
db94604b | 252 | static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) |
f7bf5461 AK |
253 | { |
254 | unsigned i; | |
8b795765 | 255 | uint32_t ret; |
db94604b PB |
256 | PhysPageEntry e; |
257 | PhysPageEntry *p; | |
f7bf5461 | 258 | |
53cb28cb | 259 | ret = map->nodes_nb++; |
db94604b | 260 | p = map->nodes[ret]; |
f7bf5461 | 261 | assert(ret != PHYS_MAP_NODE_NIL); |
53cb28cb | 262 | assert(ret != map->nodes_nb_alloc); |
db94604b PB |
263 | |
264 | e.skip = leaf ? 0 : 1; | |
265 | e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL; | |
03f49957 | 266 | for (i = 0; i < P_L2_SIZE; ++i) { |
db94604b | 267 | memcpy(&p[i], &e, sizeof(e)); |
d6f2ea22 | 268 | } |
f7bf5461 | 269 | return ret; |
d6f2ea22 AK |
270 | } |
271 | ||
53cb28cb MA |
272 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
273 | hwaddr *index, hwaddr *nb, uint16_t leaf, | |
2999097b | 274 | int level) |
f7bf5461 AK |
275 | { |
276 | PhysPageEntry *p; | |
03f49957 | 277 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); |
108c49b8 | 278 | |
9736e55b | 279 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { |
db94604b | 280 | lp->ptr = phys_map_node_alloc(map, level == 0); |
92e873b9 | 281 | } |
db94604b | 282 | p = map->nodes[lp->ptr]; |
03f49957 | 283 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
f7bf5461 | 284 | |
03f49957 | 285 | while (*nb && lp < &p[P_L2_SIZE]) { |
07f07b31 | 286 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
9736e55b | 287 | lp->skip = 0; |
c19e8800 | 288 | lp->ptr = leaf; |
07f07b31 AK |
289 | *index += step; |
290 | *nb -= step; | |
2999097b | 291 | } else { |
53cb28cb | 292 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); |
2999097b AK |
293 | } |
294 | ++lp; | |
f7bf5461 AK |
295 | } |
296 | } | |
297 | ||
ac1970fb | 298 | static void phys_page_set(AddressSpaceDispatch *d, |
a8170e5e | 299 | hwaddr index, hwaddr nb, |
2999097b | 300 | uint16_t leaf) |
f7bf5461 | 301 | { |
2999097b | 302 | /* Wildly overreserve - it doesn't matter much. */ |
53cb28cb | 303 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); |
5cd2c5b6 | 304 | |
53cb28cb | 305 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
306 | } |
307 | ||
b35ba30f MT |
308 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, |
309 | * and update our entry so we can skip it and go directly to the destination. | |
310 | */ | |
efee678d | 311 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes) |
b35ba30f MT |
312 | { |
313 | unsigned valid_ptr = P_L2_SIZE; | |
314 | int valid = 0; | |
315 | PhysPageEntry *p; | |
316 | int i; | |
317 | ||
318 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
319 | return; | |
320 | } | |
321 | ||
322 | p = nodes[lp->ptr]; | |
323 | for (i = 0; i < P_L2_SIZE; i++) { | |
324 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
325 | continue; | |
326 | } | |
327 | ||
328 | valid_ptr = i; | |
329 | valid++; | |
330 | if (p[i].skip) { | |
efee678d | 331 | phys_page_compact(&p[i], nodes); |
b35ba30f MT |
332 | } |
333 | } | |
334 | ||
335 | /* We can only compress if there's only one child. */ | |
336 | if (valid != 1) { | |
337 | return; | |
338 | } | |
339 | ||
340 | assert(valid_ptr < P_L2_SIZE); | |
341 | ||
342 | /* Don't compress if it won't fit in the # of bits we have. */ | |
343 | if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { | |
344 | return; | |
345 | } | |
346 | ||
347 | lp->ptr = p[valid_ptr].ptr; | |
348 | if (!p[valid_ptr].skip) { | |
349 | /* If our only child is a leaf, make this a leaf. */ | |
350 | /* By design, we should have made this node a leaf to begin with so we | |
351 | * should never reach here. | |
352 | * But since it's so simple to handle this, let's do it just in case we | |
353 | * change this rule. | |
354 | */ | |
355 | lp->skip = 0; | |
356 | } else { | |
357 | lp->skip += p[valid_ptr].skip; | |
358 | } | |
359 | } | |
360 | ||
8629d3fc | 361 | void address_space_dispatch_compact(AddressSpaceDispatch *d) |
b35ba30f | 362 | { |
b35ba30f | 363 | if (d->phys_map.skip) { |
efee678d | 364 | phys_page_compact(&d->phys_map, d->map.nodes); |
b35ba30f MT |
365 | } |
366 | } | |
367 | ||
29cb533d FZ |
368 | static inline bool section_covers_addr(const MemoryRegionSection *section, |
369 | hwaddr addr) | |
370 | { | |
371 | /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means | |
372 | * the section must cover the entire address space. | |
373 | */ | |
258dfaaa | 374 | return int128_gethi(section->size) || |
29cb533d | 375 | range_covers_byte(section->offset_within_address_space, |
258dfaaa | 376 | int128_getlo(section->size), addr); |
29cb533d FZ |
377 | } |
378 | ||
003a0cf2 | 379 | static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr) |
92e873b9 | 380 | { |
003a0cf2 PX |
381 | PhysPageEntry lp = d->phys_map, *p; |
382 | Node *nodes = d->map.nodes; | |
383 | MemoryRegionSection *sections = d->map.sections; | |
97115a8d | 384 | hwaddr index = addr >> TARGET_PAGE_BITS; |
31ab2b4a | 385 | int i; |
f1f6e3b8 | 386 | |
9736e55b | 387 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
c19e8800 | 388 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
9affd6fc | 389 | return §ions[PHYS_SECTION_UNASSIGNED]; |
31ab2b4a | 390 | } |
9affd6fc | 391 | p = nodes[lp.ptr]; |
03f49957 | 392 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
5312bd8b | 393 | } |
b35ba30f | 394 | |
29cb533d | 395 | if (section_covers_addr(§ions[lp.ptr], addr)) { |
b35ba30f MT |
396 | return §ions[lp.ptr]; |
397 | } else { | |
398 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
399 | } | |
f3705d53 AK |
400 | } |
401 | ||
e5548617 BS |
402 | bool memory_region_is_unassigned(MemoryRegion *mr) |
403 | { | |
2a8e7499 | 404 | return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device |
5b6dd868 | 405 | && mr != &io_mem_watch; |
fd6ce8f6 | 406 | } |
149f54b5 | 407 | |
79e2b9ae | 408 | /* Called from RCU critical section */ |
c7086b4a | 409 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, |
90260c6c JK |
410 | hwaddr addr, |
411 | bool resolve_subpage) | |
9f029603 | 412 | { |
729633c2 | 413 | MemoryRegionSection *section = atomic_read(&d->mru_section); |
90260c6c JK |
414 | subpage_t *subpage; |
415 | ||
07c114bb PB |
416 | if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] || |
417 | !section_covers_addr(section, addr)) { | |
003a0cf2 | 418 | section = phys_page_find(d, addr); |
07c114bb | 419 | atomic_set(&d->mru_section, section); |
729633c2 | 420 | } |
90260c6c JK |
421 | if (resolve_subpage && section->mr->subpage) { |
422 | subpage = container_of(section->mr, subpage_t, iomem); | |
53cb28cb | 423 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
90260c6c JK |
424 | } |
425 | return section; | |
9f029603 JK |
426 | } |
427 | ||
79e2b9ae | 428 | /* Called from RCU critical section */ |
90260c6c | 429 | static MemoryRegionSection * |
c7086b4a | 430 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
90260c6c | 431 | hwaddr *plen, bool resolve_subpage) |
149f54b5 PB |
432 | { |
433 | MemoryRegionSection *section; | |
965eb2fc | 434 | MemoryRegion *mr; |
a87f3954 | 435 | Int128 diff; |
149f54b5 | 436 | |
c7086b4a | 437 | section = address_space_lookup_region(d, addr, resolve_subpage); |
149f54b5 PB |
438 | /* Compute offset within MemoryRegionSection */ |
439 | addr -= section->offset_within_address_space; | |
440 | ||
441 | /* Compute offset within MemoryRegion */ | |
442 | *xlat = addr + section->offset_within_region; | |
443 | ||
965eb2fc | 444 | mr = section->mr; |
b242e0e0 PB |
445 | |
446 | /* MMIO registers can be expected to perform full-width accesses based only | |
447 | * on their address, without considering adjacent registers that could | |
448 | * decode to completely different MemoryRegions. When such registers | |
449 | * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO | |
450 | * regions overlap wildly. For this reason we cannot clamp the accesses | |
451 | * here. | |
452 | * | |
453 | * If the length is small (as is the case for address_space_ldl/stl), | |
454 | * everything works fine. If the incoming length is large, however, | |
455 | * the caller really has to do the clamping through memory_access_size. | |
456 | */ | |
965eb2fc | 457 | if (memory_region_is_ram(mr)) { |
e4a511f8 | 458 | diff = int128_sub(section->size, int128_make64(addr)); |
965eb2fc PB |
459 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
460 | } | |
149f54b5 PB |
461 | return section; |
462 | } | |
90260c6c | 463 | |
a411c84b PB |
464 | /** |
465 | * address_space_translate_iommu - translate an address through an IOMMU | |
466 | * memory region and then through the target address space. | |
467 | * | |
468 | * @iommu_mr: the IOMMU memory region that we start the translation from | |
469 | * @addr: the address to be translated through the MMU | |
470 | * @xlat: the translated address offset within the destination memory region. | |
471 | * It cannot be %NULL. | |
472 | * @plen_out: valid read/write length of the translated address. It | |
473 | * cannot be %NULL. | |
474 | * @page_mask_out: page mask for the translated address. This | |
475 | * should only be meaningful for IOMMU translated | |
476 | * addresses, since there may be huge pages that this bit | |
477 | * would tell. It can be %NULL if we don't care about it. | |
478 | * @is_write: whether the translation operation is for write | |
479 | * @is_mmio: whether this can be MMIO, set true if it can | |
480 | * @target_as: the address space targeted by the IOMMU | |
2f7b009c | 481 | * @attrs: transaction attributes |
a411c84b PB |
482 | * |
483 | * This function is called from RCU critical section. It is the common | |
484 | * part of flatview_do_translate and address_space_translate_cached. | |
485 | */ | |
486 | static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr, | |
487 | hwaddr *xlat, | |
488 | hwaddr *plen_out, | |
489 | hwaddr *page_mask_out, | |
490 | bool is_write, | |
491 | bool is_mmio, | |
2f7b009c PM |
492 | AddressSpace **target_as, |
493 | MemTxAttrs attrs) | |
a411c84b PB |
494 | { |
495 | MemoryRegionSection *section; | |
496 | hwaddr page_mask = (hwaddr)-1; | |
497 | ||
498 | do { | |
499 | hwaddr addr = *xlat; | |
500 | IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
501 | IOMMUTLBEntry iotlb = imrc->translate(iommu_mr, addr, is_write ? | |
502 | IOMMU_WO : IOMMU_RO); | |
503 | ||
504 | if (!(iotlb.perm & (1 << is_write))) { | |
505 | goto unassigned; | |
506 | } | |
507 | ||
508 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
509 | | (addr & iotlb.addr_mask)); | |
510 | page_mask &= iotlb.addr_mask; | |
511 | *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1); | |
512 | *target_as = iotlb.target_as; | |
513 | ||
514 | section = address_space_translate_internal( | |
515 | address_space_to_dispatch(iotlb.target_as), addr, xlat, | |
516 | plen_out, is_mmio); | |
517 | ||
518 | iommu_mr = memory_region_get_iommu(section->mr); | |
519 | } while (unlikely(iommu_mr)); | |
520 | ||
521 | if (page_mask_out) { | |
522 | *page_mask_out = page_mask; | |
523 | } | |
524 | return *section; | |
525 | ||
526 | unassigned: | |
527 | return (MemoryRegionSection) { .mr = &io_mem_unassigned }; | |
528 | } | |
529 | ||
d5e5fafd PX |
530 | /** |
531 | * flatview_do_translate - translate an address in FlatView | |
532 | * | |
533 | * @fv: the flat view that we want to translate on | |
534 | * @addr: the address to be translated in above address space | |
535 | * @xlat: the translated address offset within memory region. It | |
536 | * cannot be @NULL. | |
537 | * @plen_out: valid read/write length of the translated address. It | |
538 | * can be @NULL when we don't care about it. | |
539 | * @page_mask_out: page mask for the translated address. This | |
540 | * should only be meaningful for IOMMU translated | |
541 | * addresses, since there may be huge pages that this bit | |
542 | * would tell. It can be @NULL if we don't care about it. | |
543 | * @is_write: whether the translation operation is for write | |
544 | * @is_mmio: whether this can be MMIO, set true if it can | |
ad2804d9 | 545 | * @target_as: the address space targeted by the IOMMU |
49e14aa8 | 546 | * @attrs: memory transaction attributes |
d5e5fafd PX |
547 | * |
548 | * This function is called from RCU critical section | |
549 | */ | |
16620684 AK |
550 | static MemoryRegionSection flatview_do_translate(FlatView *fv, |
551 | hwaddr addr, | |
552 | hwaddr *xlat, | |
d5e5fafd PX |
553 | hwaddr *plen_out, |
554 | hwaddr *page_mask_out, | |
16620684 AK |
555 | bool is_write, |
556 | bool is_mmio, | |
49e14aa8 PM |
557 | AddressSpace **target_as, |
558 | MemTxAttrs attrs) | |
052c8fa9 | 559 | { |
052c8fa9 | 560 | MemoryRegionSection *section; |
3df9d748 | 561 | IOMMUMemoryRegion *iommu_mr; |
d5e5fafd PX |
562 | hwaddr plen = (hwaddr)(-1); |
563 | ||
ad2804d9 PB |
564 | if (!plen_out) { |
565 | plen_out = &plen; | |
d5e5fafd | 566 | } |
052c8fa9 | 567 | |
a411c84b PB |
568 | section = address_space_translate_internal( |
569 | flatview_to_dispatch(fv), addr, xlat, | |
570 | plen_out, is_mmio); | |
052c8fa9 | 571 | |
a411c84b PB |
572 | iommu_mr = memory_region_get_iommu(section->mr); |
573 | if (unlikely(iommu_mr)) { | |
574 | return address_space_translate_iommu(iommu_mr, xlat, | |
575 | plen_out, page_mask_out, | |
576 | is_write, is_mmio, | |
2f7b009c | 577 | target_as, attrs); |
052c8fa9 | 578 | } |
d5e5fafd | 579 | if (page_mask_out) { |
a411c84b PB |
580 | /* Not behind an IOMMU, use default page size. */ |
581 | *page_mask_out = ~TARGET_PAGE_MASK; | |
d5e5fafd PX |
582 | } |
583 | ||
a764040c | 584 | return *section; |
052c8fa9 JW |
585 | } |
586 | ||
587 | /* Called from RCU critical section */ | |
a764040c | 588 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, |
7446eb07 | 589 | bool is_write, MemTxAttrs attrs) |
90260c6c | 590 | { |
a764040c | 591 | MemoryRegionSection section; |
076a93d7 | 592 | hwaddr xlat, page_mask; |
30951157 | 593 | |
076a93d7 PX |
594 | /* |
595 | * This can never be MMIO, and we don't really care about plen, | |
596 | * but page mask. | |
597 | */ | |
598 | section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat, | |
49e14aa8 PM |
599 | NULL, &page_mask, is_write, false, &as, |
600 | attrs); | |
30951157 | 601 | |
a764040c PX |
602 | /* Illegal translation */ |
603 | if (section.mr == &io_mem_unassigned) { | |
604 | goto iotlb_fail; | |
605 | } | |
30951157 | 606 | |
a764040c PX |
607 | /* Convert memory region offset into address space offset */ |
608 | xlat += section.offset_within_address_space - | |
609 | section.offset_within_region; | |
610 | ||
a764040c | 611 | return (IOMMUTLBEntry) { |
e76bb18f | 612 | .target_as = as, |
076a93d7 PX |
613 | .iova = addr & ~page_mask, |
614 | .translated_addr = xlat & ~page_mask, | |
615 | .addr_mask = page_mask, | |
a764040c PX |
616 | /* IOTLBs are for DMAs, and DMA only allows on RAMs. */ |
617 | .perm = IOMMU_RW, | |
618 | }; | |
619 | ||
620 | iotlb_fail: | |
621 | return (IOMMUTLBEntry) {0}; | |
622 | } | |
623 | ||
624 | /* Called from RCU critical section */ | |
16620684 | 625 | MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, |
efa99a2f PM |
626 | hwaddr *plen, bool is_write, |
627 | MemTxAttrs attrs) | |
a764040c PX |
628 | { |
629 | MemoryRegion *mr; | |
630 | MemoryRegionSection section; | |
16620684 | 631 | AddressSpace *as = NULL; |
a764040c PX |
632 | |
633 | /* This can be MMIO, so setup MMIO bit. */ | |
d5e5fafd | 634 | section = flatview_do_translate(fv, addr, xlat, plen, NULL, |
49e14aa8 | 635 | is_write, true, &as, attrs); |
a764040c PX |
636 | mr = section.mr; |
637 | ||
fe680d0d | 638 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { |
a87f3954 | 639 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; |
23820dbf | 640 | *plen = MIN(page, *plen); |
a87f3954 PB |
641 | } |
642 | ||
30951157 | 643 | return mr; |
90260c6c JK |
644 | } |
645 | ||
79e2b9ae | 646 | /* Called from RCU critical section */ |
90260c6c | 647 | MemoryRegionSection * |
d7898cda | 648 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, |
9d82b5a7 | 649 | hwaddr *xlat, hwaddr *plen) |
90260c6c | 650 | { |
30951157 | 651 | MemoryRegionSection *section; |
f35e44e7 | 652 | AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch); |
d7898cda PM |
653 | |
654 | section = address_space_translate_internal(d, addr, xlat, plen, false); | |
30951157 | 655 | |
3df9d748 | 656 | assert(!memory_region_is_iommu(section->mr)); |
30951157 | 657 | return section; |
90260c6c | 658 | } |
5b6dd868 | 659 | #endif |
fd6ce8f6 | 660 | |
b170fce3 | 661 | #if !defined(CONFIG_USER_ONLY) |
5b6dd868 BS |
662 | |
663 | static int cpu_common_post_load(void *opaque, int version_id) | |
fd6ce8f6 | 664 | { |
259186a7 | 665 | CPUState *cpu = opaque; |
a513fe19 | 666 | |
5b6dd868 BS |
667 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
668 | version_id is increased. */ | |
259186a7 | 669 | cpu->interrupt_request &= ~0x01; |
d10eb08f | 670 | tlb_flush(cpu); |
5b6dd868 | 671 | |
15a356c4 PD |
672 | /* loadvm has just updated the content of RAM, bypassing the |
673 | * usual mechanisms that ensure we flush TBs for writes to | |
674 | * memory we've translated code from. So we must flush all TBs, | |
675 | * which will now be stale. | |
676 | */ | |
677 | tb_flush(cpu); | |
678 | ||
5b6dd868 | 679 | return 0; |
a513fe19 | 680 | } |
7501267e | 681 | |
6c3bff0e PD |
682 | static int cpu_common_pre_load(void *opaque) |
683 | { | |
684 | CPUState *cpu = opaque; | |
685 | ||
adee6424 | 686 | cpu->exception_index = -1; |
6c3bff0e PD |
687 | |
688 | return 0; | |
689 | } | |
690 | ||
691 | static bool cpu_common_exception_index_needed(void *opaque) | |
692 | { | |
693 | CPUState *cpu = opaque; | |
694 | ||
adee6424 | 695 | return tcg_enabled() && cpu->exception_index != -1; |
6c3bff0e PD |
696 | } |
697 | ||
698 | static const VMStateDescription vmstate_cpu_common_exception_index = { | |
699 | .name = "cpu_common/exception_index", | |
700 | .version_id = 1, | |
701 | .minimum_version_id = 1, | |
5cd8cada | 702 | .needed = cpu_common_exception_index_needed, |
6c3bff0e PD |
703 | .fields = (VMStateField[]) { |
704 | VMSTATE_INT32(exception_index, CPUState), | |
705 | VMSTATE_END_OF_LIST() | |
706 | } | |
707 | }; | |
708 | ||
bac05aa9 AS |
709 | static bool cpu_common_crash_occurred_needed(void *opaque) |
710 | { | |
711 | CPUState *cpu = opaque; | |
712 | ||
713 | return cpu->crash_occurred; | |
714 | } | |
715 | ||
716 | static const VMStateDescription vmstate_cpu_common_crash_occurred = { | |
717 | .name = "cpu_common/crash_occurred", | |
718 | .version_id = 1, | |
719 | .minimum_version_id = 1, | |
720 | .needed = cpu_common_crash_occurred_needed, | |
721 | .fields = (VMStateField[]) { | |
722 | VMSTATE_BOOL(crash_occurred, CPUState), | |
723 | VMSTATE_END_OF_LIST() | |
724 | } | |
725 | }; | |
726 | ||
1a1562f5 | 727 | const VMStateDescription vmstate_cpu_common = { |
5b6dd868 BS |
728 | .name = "cpu_common", |
729 | .version_id = 1, | |
730 | .minimum_version_id = 1, | |
6c3bff0e | 731 | .pre_load = cpu_common_pre_load, |
5b6dd868 | 732 | .post_load = cpu_common_post_load, |
35d08458 | 733 | .fields = (VMStateField[]) { |
259186a7 AF |
734 | VMSTATE_UINT32(halted, CPUState), |
735 | VMSTATE_UINT32(interrupt_request, CPUState), | |
5b6dd868 | 736 | VMSTATE_END_OF_LIST() |
6c3bff0e | 737 | }, |
5cd8cada JQ |
738 | .subsections = (const VMStateDescription*[]) { |
739 | &vmstate_cpu_common_exception_index, | |
bac05aa9 | 740 | &vmstate_cpu_common_crash_occurred, |
5cd8cada | 741 | NULL |
5b6dd868 BS |
742 | } |
743 | }; | |
1a1562f5 | 744 | |
5b6dd868 | 745 | #endif |
ea041c0e | 746 | |
38d8f5c8 | 747 | CPUState *qemu_get_cpu(int index) |
ea041c0e | 748 | { |
bdc44640 | 749 | CPUState *cpu; |
ea041c0e | 750 | |
bdc44640 | 751 | CPU_FOREACH(cpu) { |
55e5c285 | 752 | if (cpu->cpu_index == index) { |
bdc44640 | 753 | return cpu; |
55e5c285 | 754 | } |
ea041c0e | 755 | } |
5b6dd868 | 756 | |
bdc44640 | 757 | return NULL; |
ea041c0e FB |
758 | } |
759 | ||
09daed84 | 760 | #if !defined(CONFIG_USER_ONLY) |
80ceb07a PX |
761 | void cpu_address_space_init(CPUState *cpu, int asidx, |
762 | const char *prefix, MemoryRegion *mr) | |
09daed84 | 763 | { |
12ebc9a7 | 764 | CPUAddressSpace *newas; |
80ceb07a | 765 | AddressSpace *as = g_new0(AddressSpace, 1); |
87a621d8 | 766 | char *as_name; |
80ceb07a PX |
767 | |
768 | assert(mr); | |
87a621d8 PX |
769 | as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index); |
770 | address_space_init(as, mr, as_name); | |
771 | g_free(as_name); | |
12ebc9a7 PM |
772 | |
773 | /* Target code should have set num_ases before calling us */ | |
774 | assert(asidx < cpu->num_ases); | |
775 | ||
56943e8c PM |
776 | if (asidx == 0) { |
777 | /* address space 0 gets the convenience alias */ | |
778 | cpu->as = as; | |
779 | } | |
780 | ||
12ebc9a7 PM |
781 | /* KVM cannot currently support multiple address spaces. */ |
782 | assert(asidx == 0 || !kvm_enabled()); | |
09daed84 | 783 | |
12ebc9a7 PM |
784 | if (!cpu->cpu_ases) { |
785 | cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases); | |
09daed84 | 786 | } |
32857f4d | 787 | |
12ebc9a7 PM |
788 | newas = &cpu->cpu_ases[asidx]; |
789 | newas->cpu = cpu; | |
790 | newas->as = as; | |
56943e8c | 791 | if (tcg_enabled()) { |
12ebc9a7 PM |
792 | newas->tcg_as_listener.commit = tcg_commit; |
793 | memory_listener_register(&newas->tcg_as_listener, as); | |
56943e8c | 794 | } |
09daed84 | 795 | } |
651a5bc0 PM |
796 | |
797 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) | |
798 | { | |
799 | /* Return the AddressSpace corresponding to the specified index */ | |
800 | return cpu->cpu_ases[asidx].as; | |
801 | } | |
09daed84 EI |
802 | #endif |
803 | ||
7bbc124e | 804 | void cpu_exec_unrealizefn(CPUState *cpu) |
1c59eb39 | 805 | { |
9dfeca7c BR |
806 | CPUClass *cc = CPU_GET_CLASS(cpu); |
807 | ||
267f685b | 808 | cpu_list_remove(cpu); |
9dfeca7c BR |
809 | |
810 | if (cc->vmsd != NULL) { | |
811 | vmstate_unregister(NULL, cc->vmsd, cpu); | |
812 | } | |
813 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | |
814 | vmstate_unregister(NULL, &vmstate_cpu_common, cpu); | |
815 | } | |
1c59eb39 BR |
816 | } |
817 | ||
c7e002c5 FZ |
818 | Property cpu_common_props[] = { |
819 | #ifndef CONFIG_USER_ONLY | |
820 | /* Create a memory property for softmmu CPU object, | |
821 | * so users can wire up its memory. (This can't go in qom/cpu.c | |
822 | * because that file is compiled only once for both user-mode | |
823 | * and system builds.) The default if no link is set up is to use | |
824 | * the system address space. | |
825 | */ | |
826 | DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, | |
827 | MemoryRegion *), | |
828 | #endif | |
829 | DEFINE_PROP_END_OF_LIST(), | |
830 | }; | |
831 | ||
39e329e3 | 832 | void cpu_exec_initfn(CPUState *cpu) |
ea041c0e | 833 | { |
56943e8c | 834 | cpu->as = NULL; |
12ebc9a7 | 835 | cpu->num_ases = 0; |
56943e8c | 836 | |
291135b5 | 837 | #ifndef CONFIG_USER_ONLY |
291135b5 | 838 | cpu->thread_id = qemu_get_thread_id(); |
6731d864 PC |
839 | cpu->memory = system_memory; |
840 | object_ref(OBJECT(cpu->memory)); | |
291135b5 | 841 | #endif |
39e329e3 LV |
842 | } |
843 | ||
ce5b1bbf | 844 | void cpu_exec_realizefn(CPUState *cpu, Error **errp) |
39e329e3 | 845 | { |
55c3ceef | 846 | CPUClass *cc = CPU_GET_CLASS(cpu); |
2dda6354 | 847 | static bool tcg_target_initialized; |
291135b5 | 848 | |
267f685b | 849 | cpu_list_add(cpu); |
1bc7e522 | 850 | |
2dda6354 EC |
851 | if (tcg_enabled() && !tcg_target_initialized) { |
852 | tcg_target_initialized = true; | |
55c3ceef RH |
853 | cc->tcg_initialize(); |
854 | } | |
855 | ||
1bc7e522 | 856 | #ifndef CONFIG_USER_ONLY |
e0d47944 | 857 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { |
741da0d3 | 858 | vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); |
e0d47944 | 859 | } |
b170fce3 | 860 | if (cc->vmsd != NULL) { |
741da0d3 | 861 | vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); |
b170fce3 | 862 | } |
741da0d3 | 863 | #endif |
ea041c0e FB |
864 | } |
865 | ||
2278b939 IM |
866 | const char *parse_cpu_model(const char *cpu_model) |
867 | { | |
868 | ObjectClass *oc; | |
869 | CPUClass *cc; | |
870 | gchar **model_pieces; | |
871 | const char *cpu_type; | |
872 | ||
873 | model_pieces = g_strsplit(cpu_model, ",", 2); | |
874 | ||
875 | oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]); | |
876 | if (oc == NULL) { | |
877 | error_report("unable to find CPU model '%s'", model_pieces[0]); | |
878 | g_strfreev(model_pieces); | |
879 | exit(EXIT_FAILURE); | |
880 | } | |
881 | ||
882 | cpu_type = object_class_get_name(oc); | |
883 | cc = CPU_CLASS(oc); | |
884 | cc->parse_features(cpu_type, model_pieces[1], &error_fatal); | |
885 | g_strfreev(model_pieces); | |
886 | return cpu_type; | |
887 | } | |
888 | ||
406bc339 | 889 | #if defined(CONFIG_USER_ONLY) |
00b941e5 | 890 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
1e7855a5 | 891 | { |
406bc339 PK |
892 | mmap_lock(); |
893 | tb_lock(); | |
894 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
895 | tb_unlock(); | |
896 | mmap_unlock(); | |
897 | } | |
898 | #else | |
899 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | |
900 | { | |
901 | MemTxAttrs attrs; | |
902 | hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); | |
903 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | |
904 | if (phys != -1) { | |
905 | /* Locks grabbed by tb_invalidate_phys_addr */ | |
906 | tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, | |
c874dc4f | 907 | phys | (pc & ~TARGET_PAGE_MASK), attrs); |
406bc339 | 908 | } |
1e7855a5 | 909 | } |
406bc339 | 910 | #endif |
d720b93d | 911 | |
c527ee8f | 912 | #if defined(CONFIG_USER_ONLY) |
75a34036 | 913 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
c527ee8f PB |
914 | |
915 | { | |
916 | } | |
917 | ||
3ee887e8 PM |
918 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
919 | int flags) | |
920 | { | |
921 | return -ENOSYS; | |
922 | } | |
923 | ||
924 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
925 | { | |
926 | } | |
927 | ||
75a34036 | 928 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
c527ee8f PB |
929 | int flags, CPUWatchpoint **watchpoint) |
930 | { | |
931 | return -ENOSYS; | |
932 | } | |
933 | #else | |
6658ffb8 | 934 | /* Add a watchpoint. */ |
75a34036 | 935 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 936 | int flags, CPUWatchpoint **watchpoint) |
6658ffb8 | 937 | { |
c0ce998e | 938 | CPUWatchpoint *wp; |
6658ffb8 | 939 | |
05068c0d | 940 | /* forbid ranges which are empty or run off the end of the address space */ |
07e2863d | 941 | if (len == 0 || (addr + len - 1) < addr) { |
75a34036 AF |
942 | error_report("tried to set invalid watchpoint at %" |
943 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); | |
b4051334 AL |
944 | return -EINVAL; |
945 | } | |
7267c094 | 946 | wp = g_malloc(sizeof(*wp)); |
a1d1bb31 AL |
947 | |
948 | wp->vaddr = addr; | |
05068c0d | 949 | wp->len = len; |
a1d1bb31 AL |
950 | wp->flags = flags; |
951 | ||
2dc9f411 | 952 | /* keep all GDB-injected watchpoints in front */ |
ff4700b0 AF |
953 | if (flags & BP_GDB) { |
954 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); | |
955 | } else { | |
956 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); | |
957 | } | |
6658ffb8 | 958 | |
31b030d4 | 959 | tlb_flush_page(cpu, addr); |
a1d1bb31 AL |
960 | |
961 | if (watchpoint) | |
962 | *watchpoint = wp; | |
963 | return 0; | |
6658ffb8 PB |
964 | } |
965 | ||
a1d1bb31 | 966 | /* Remove a specific watchpoint. */ |
75a34036 | 967 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 968 | int flags) |
6658ffb8 | 969 | { |
a1d1bb31 | 970 | CPUWatchpoint *wp; |
6658ffb8 | 971 | |
ff4700b0 | 972 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 973 | if (addr == wp->vaddr && len == wp->len |
6e140f28 | 974 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
75a34036 | 975 | cpu_watchpoint_remove_by_ref(cpu, wp); |
6658ffb8 PB |
976 | return 0; |
977 | } | |
978 | } | |
a1d1bb31 | 979 | return -ENOENT; |
6658ffb8 PB |
980 | } |
981 | ||
a1d1bb31 | 982 | /* Remove a specific watchpoint by reference. */ |
75a34036 | 983 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) |
a1d1bb31 | 984 | { |
ff4700b0 | 985 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); |
7d03f82f | 986 | |
31b030d4 | 987 | tlb_flush_page(cpu, watchpoint->vaddr); |
a1d1bb31 | 988 | |
7267c094 | 989 | g_free(watchpoint); |
a1d1bb31 AL |
990 | } |
991 | ||
992 | /* Remove all matching watchpoints. */ | |
75a34036 | 993 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 994 | { |
c0ce998e | 995 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 996 | |
ff4700b0 | 997 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { |
75a34036 AF |
998 | if (wp->flags & mask) { |
999 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
1000 | } | |
c0ce998e | 1001 | } |
7d03f82f | 1002 | } |
05068c0d PM |
1003 | |
1004 | /* Return true if this watchpoint address matches the specified | |
1005 | * access (ie the address range covered by the watchpoint overlaps | |
1006 | * partially or completely with the address range covered by the | |
1007 | * access). | |
1008 | */ | |
1009 | static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, | |
1010 | vaddr addr, | |
1011 | vaddr len) | |
1012 | { | |
1013 | /* We know the lengths are non-zero, but a little caution is | |
1014 | * required to avoid errors in the case where the range ends | |
1015 | * exactly at the top of the address space and so addr + len | |
1016 | * wraps round to zero. | |
1017 | */ | |
1018 | vaddr wpend = wp->vaddr + wp->len - 1; | |
1019 | vaddr addrend = addr + len - 1; | |
1020 | ||
1021 | return !(addr > wpend || wp->vaddr > addrend); | |
1022 | } | |
1023 | ||
c527ee8f | 1024 | #endif |
7d03f82f | 1025 | |
a1d1bb31 | 1026 | /* Add a breakpoint. */ |
b3310ab3 | 1027 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, |
a1d1bb31 | 1028 | CPUBreakpoint **breakpoint) |
4c3a88a2 | 1029 | { |
c0ce998e | 1030 | CPUBreakpoint *bp; |
3b46e624 | 1031 | |
7267c094 | 1032 | bp = g_malloc(sizeof(*bp)); |
4c3a88a2 | 1033 | |
a1d1bb31 AL |
1034 | bp->pc = pc; |
1035 | bp->flags = flags; | |
1036 | ||
2dc9f411 | 1037 | /* keep all GDB-injected breakpoints in front */ |
00b941e5 | 1038 | if (flags & BP_GDB) { |
f0c3c505 | 1039 | QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); |
00b941e5 | 1040 | } else { |
f0c3c505 | 1041 | QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); |
00b941e5 | 1042 | } |
3b46e624 | 1043 | |
f0c3c505 | 1044 | breakpoint_invalidate(cpu, pc); |
a1d1bb31 | 1045 | |
00b941e5 | 1046 | if (breakpoint) { |
a1d1bb31 | 1047 | *breakpoint = bp; |
00b941e5 | 1048 | } |
4c3a88a2 | 1049 | return 0; |
4c3a88a2 FB |
1050 | } |
1051 | ||
a1d1bb31 | 1052 | /* Remove a specific breakpoint. */ |
b3310ab3 | 1053 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) |
a1d1bb31 | 1054 | { |
a1d1bb31 AL |
1055 | CPUBreakpoint *bp; |
1056 | ||
f0c3c505 | 1057 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { |
a1d1bb31 | 1058 | if (bp->pc == pc && bp->flags == flags) { |
b3310ab3 | 1059 | cpu_breakpoint_remove_by_ref(cpu, bp); |
a1d1bb31 AL |
1060 | return 0; |
1061 | } | |
7d03f82f | 1062 | } |
a1d1bb31 | 1063 | return -ENOENT; |
7d03f82f EI |
1064 | } |
1065 | ||
a1d1bb31 | 1066 | /* Remove a specific breakpoint by reference. */ |
b3310ab3 | 1067 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) |
4c3a88a2 | 1068 | { |
f0c3c505 AF |
1069 | QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); |
1070 | ||
1071 | breakpoint_invalidate(cpu, breakpoint->pc); | |
a1d1bb31 | 1072 | |
7267c094 | 1073 | g_free(breakpoint); |
a1d1bb31 AL |
1074 | } |
1075 | ||
1076 | /* Remove all matching breakpoints. */ | |
b3310ab3 | 1077 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 1078 | { |
c0ce998e | 1079 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1080 | |
f0c3c505 | 1081 | QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { |
b3310ab3 AF |
1082 | if (bp->flags & mask) { |
1083 | cpu_breakpoint_remove_by_ref(cpu, bp); | |
1084 | } | |
c0ce998e | 1085 | } |
4c3a88a2 FB |
1086 | } |
1087 | ||
c33a346e FB |
1088 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1089 | CPU loop after each instruction */ | |
3825b28f | 1090 | void cpu_single_step(CPUState *cpu, int enabled) |
c33a346e | 1091 | { |
ed2803da AF |
1092 | if (cpu->singlestep_enabled != enabled) { |
1093 | cpu->singlestep_enabled = enabled; | |
1094 | if (kvm_enabled()) { | |
38e478ec | 1095 | kvm_update_guest_debug(cpu, 0); |
ed2803da | 1096 | } else { |
ccbb4d44 | 1097 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 | 1098 | /* XXX: only flush what is necessary */ |
bbd77c18 | 1099 | tb_flush(cpu); |
e22a25c9 | 1100 | } |
c33a346e | 1101 | } |
c33a346e FB |
1102 | } |
1103 | ||
a47dddd7 | 1104 | void cpu_abort(CPUState *cpu, const char *fmt, ...) |
7501267e FB |
1105 | { |
1106 | va_list ap; | |
493ae1f0 | 1107 | va_list ap2; |
7501267e FB |
1108 | |
1109 | va_start(ap, fmt); | |
493ae1f0 | 1110 | va_copy(ap2, ap); |
7501267e FB |
1111 | fprintf(stderr, "qemu: fatal: "); |
1112 | vfprintf(stderr, fmt, ap); | |
1113 | fprintf(stderr, "\n"); | |
878096ee | 1114 | cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
013a2942 | 1115 | if (qemu_log_separate()) { |
1ee73216 | 1116 | qemu_log_lock(); |
93fcfe39 AL |
1117 | qemu_log("qemu: fatal: "); |
1118 | qemu_log_vprintf(fmt, ap2); | |
1119 | qemu_log("\n"); | |
a0762859 | 1120 | log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
31b1a7b4 | 1121 | qemu_log_flush(); |
1ee73216 | 1122 | qemu_log_unlock(); |
93fcfe39 | 1123 | qemu_log_close(); |
924edcae | 1124 | } |
493ae1f0 | 1125 | va_end(ap2); |
f9373291 | 1126 | va_end(ap); |
7615936e | 1127 | replay_finish(); |
fd052bf6 RV |
1128 | #if defined(CONFIG_USER_ONLY) |
1129 | { | |
1130 | struct sigaction act; | |
1131 | sigfillset(&act.sa_mask); | |
1132 | act.sa_handler = SIG_DFL; | |
1133 | sigaction(SIGABRT, &act, NULL); | |
1134 | } | |
1135 | #endif | |
7501267e FB |
1136 | abort(); |
1137 | } | |
1138 | ||
0124311e | 1139 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a | 1140 | /* Called from RCU critical section */ |
041603fe PB |
1141 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
1142 | { | |
1143 | RAMBlock *block; | |
1144 | ||
43771539 | 1145 | block = atomic_rcu_read(&ram_list.mru_block); |
9b8424d5 | 1146 | if (block && addr - block->offset < block->max_length) { |
68851b98 | 1147 | return block; |
041603fe | 1148 | } |
99e15582 | 1149 | RAMBLOCK_FOREACH(block) { |
9b8424d5 | 1150 | if (addr - block->offset < block->max_length) { |
041603fe PB |
1151 | goto found; |
1152 | } | |
1153 | } | |
1154 | ||
1155 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1156 | abort(); | |
1157 | ||
1158 | found: | |
43771539 PB |
1159 | /* It is safe to write mru_block outside the iothread lock. This |
1160 | * is what happens: | |
1161 | * | |
1162 | * mru_block = xxx | |
1163 | * rcu_read_unlock() | |
1164 | * xxx removed from list | |
1165 | * rcu_read_lock() | |
1166 | * read mru_block | |
1167 | * mru_block = NULL; | |
1168 | * call_rcu(reclaim_ramblock, xxx); | |
1169 | * rcu_read_unlock() | |
1170 | * | |
1171 | * atomic_rcu_set is not needed here. The block was already published | |
1172 | * when it was placed into the list. Here we're just making an extra | |
1173 | * copy of the pointer. | |
1174 | */ | |
041603fe PB |
1175 | ram_list.mru_block = block; |
1176 | return block; | |
1177 | } | |
1178 | ||
a2f4d5be | 1179 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) |
d24981d3 | 1180 | { |
9a13565d | 1181 | CPUState *cpu; |
041603fe | 1182 | ram_addr_t start1; |
a2f4d5be JQ |
1183 | RAMBlock *block; |
1184 | ram_addr_t end; | |
1185 | ||
1186 | end = TARGET_PAGE_ALIGN(start + length); | |
1187 | start &= TARGET_PAGE_MASK; | |
d24981d3 | 1188 | |
0dc3f44a | 1189 | rcu_read_lock(); |
041603fe PB |
1190 | block = qemu_get_ram_block(start); |
1191 | assert(block == qemu_get_ram_block(end - 1)); | |
1240be24 | 1192 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); |
9a13565d PC |
1193 | CPU_FOREACH(cpu) { |
1194 | tlb_reset_dirty(cpu, start1, length); | |
1195 | } | |
0dc3f44a | 1196 | rcu_read_unlock(); |
d24981d3 JQ |
1197 | } |
1198 | ||
5579c7f3 | 1199 | /* Note: start and end must be within the same ram block. */ |
03eebc9e SH |
1200 | bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, |
1201 | ram_addr_t length, | |
1202 | unsigned client) | |
1ccde1cb | 1203 | { |
5b82b703 | 1204 | DirtyMemoryBlocks *blocks; |
03eebc9e | 1205 | unsigned long end, page; |
5b82b703 | 1206 | bool dirty = false; |
03eebc9e SH |
1207 | |
1208 | if (length == 0) { | |
1209 | return false; | |
1210 | } | |
f23db169 | 1211 | |
03eebc9e SH |
1212 | end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; |
1213 | page = start >> TARGET_PAGE_BITS; | |
5b82b703 SH |
1214 | |
1215 | rcu_read_lock(); | |
1216 | ||
1217 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1218 | ||
1219 | while (page < end) { | |
1220 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1221 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1222 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1223 | ||
1224 | dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx], | |
1225 | offset, num); | |
1226 | page += num; | |
1227 | } | |
1228 | ||
1229 | rcu_read_unlock(); | |
03eebc9e SH |
1230 | |
1231 | if (dirty && tcg_enabled()) { | |
a2f4d5be | 1232 | tlb_reset_dirty_range_all(start, length); |
5579c7f3 | 1233 | } |
03eebc9e SH |
1234 | |
1235 | return dirty; | |
1ccde1cb FB |
1236 | } |
1237 | ||
8deaf12c GH |
1238 | DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty |
1239 | (ram_addr_t start, ram_addr_t length, unsigned client) | |
1240 | { | |
1241 | DirtyMemoryBlocks *blocks; | |
1242 | unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL); | |
1243 | ram_addr_t first = QEMU_ALIGN_DOWN(start, align); | |
1244 | ram_addr_t last = QEMU_ALIGN_UP(start + length, align); | |
1245 | DirtyBitmapSnapshot *snap; | |
1246 | unsigned long page, end, dest; | |
1247 | ||
1248 | snap = g_malloc0(sizeof(*snap) + | |
1249 | ((last - first) >> (TARGET_PAGE_BITS + 3))); | |
1250 | snap->start = first; | |
1251 | snap->end = last; | |
1252 | ||
1253 | page = first >> TARGET_PAGE_BITS; | |
1254 | end = last >> TARGET_PAGE_BITS; | |
1255 | dest = 0; | |
1256 | ||
1257 | rcu_read_lock(); | |
1258 | ||
1259 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1260 | ||
1261 | while (page < end) { | |
1262 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1263 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1264 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1265 | ||
1266 | assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL))); | |
1267 | assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL))); | |
1268 | offset >>= BITS_PER_LEVEL; | |
1269 | ||
1270 | bitmap_copy_and_clear_atomic(snap->dirty + dest, | |
1271 | blocks->blocks[idx] + offset, | |
1272 | num); | |
1273 | page += num; | |
1274 | dest += num >> BITS_PER_LEVEL; | |
1275 | } | |
1276 | ||
1277 | rcu_read_unlock(); | |
1278 | ||
1279 | if (tcg_enabled()) { | |
1280 | tlb_reset_dirty_range_all(start, length); | |
1281 | } | |
1282 | ||
1283 | return snap; | |
1284 | } | |
1285 | ||
1286 | bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, | |
1287 | ram_addr_t start, | |
1288 | ram_addr_t length) | |
1289 | { | |
1290 | unsigned long page, end; | |
1291 | ||
1292 | assert(start >= snap->start); | |
1293 | assert(start + length <= snap->end); | |
1294 | ||
1295 | end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS; | |
1296 | page = (start - snap->start) >> TARGET_PAGE_BITS; | |
1297 | ||
1298 | while (page < end) { | |
1299 | if (test_bit(page, snap->dirty)) { | |
1300 | return true; | |
1301 | } | |
1302 | page++; | |
1303 | } | |
1304 | return false; | |
1305 | } | |
1306 | ||
79e2b9ae | 1307 | /* Called from RCU critical section */ |
bb0e627a | 1308 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
149f54b5 PB |
1309 | MemoryRegionSection *section, |
1310 | target_ulong vaddr, | |
1311 | hwaddr paddr, hwaddr xlat, | |
1312 | int prot, | |
1313 | target_ulong *address) | |
e5548617 | 1314 | { |
a8170e5e | 1315 | hwaddr iotlb; |
e5548617 BS |
1316 | CPUWatchpoint *wp; |
1317 | ||
cc5bea60 | 1318 | if (memory_region_is_ram(section->mr)) { |
e5548617 | 1319 | /* Normal RAM. */ |
e4e69794 | 1320 | iotlb = memory_region_get_ram_addr(section->mr) + xlat; |
e5548617 | 1321 | if (!section->readonly) { |
b41aac4f | 1322 | iotlb |= PHYS_SECTION_NOTDIRTY; |
e5548617 | 1323 | } else { |
b41aac4f | 1324 | iotlb |= PHYS_SECTION_ROM; |
e5548617 BS |
1325 | } |
1326 | } else { | |
0b8e2c10 PM |
1327 | AddressSpaceDispatch *d; |
1328 | ||
16620684 | 1329 | d = flatview_to_dispatch(section->fv); |
0b8e2c10 | 1330 | iotlb = section - d->map.sections; |
149f54b5 | 1331 | iotlb += xlat; |
e5548617 BS |
1332 | } |
1333 | ||
1334 | /* Make accesses to pages with watchpoints go via the | |
1335 | watchpoint trap routines. */ | |
ff4700b0 | 1336 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 1337 | if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { |
e5548617 BS |
1338 | /* Avoid trapping reads of pages with a write breakpoint. */ |
1339 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
b41aac4f | 1340 | iotlb = PHYS_SECTION_WATCH + paddr; |
e5548617 BS |
1341 | *address |= TLB_MMIO; |
1342 | break; | |
1343 | } | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | return iotlb; | |
1348 | } | |
9fa3e853 FB |
1349 | #endif /* defined(CONFIG_USER_ONLY) */ |
1350 | ||
e2eef170 | 1351 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 1352 | |
c227f099 | 1353 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 1354 | uint16_t section); |
16620684 | 1355 | static subpage_t *subpage_init(FlatView *fv, hwaddr base); |
54688b1e | 1356 | |
06329cce | 1357 | static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) = |
a2b257d6 | 1358 | qemu_anon_ram_alloc; |
91138037 MA |
1359 | |
1360 | /* | |
1361 | * Set a custom physical guest memory alloator. | |
1362 | * Accelerators with unusual needs may need this. Hopefully, we can | |
1363 | * get rid of it eventually. | |
1364 | */ | |
06329cce | 1365 | void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared)) |
91138037 MA |
1366 | { |
1367 | phys_mem_alloc = alloc; | |
1368 | } | |
1369 | ||
53cb28cb MA |
1370 | static uint16_t phys_section_add(PhysPageMap *map, |
1371 | MemoryRegionSection *section) | |
5312bd8b | 1372 | { |
68f3f65b PB |
1373 | /* The physical section number is ORed with a page-aligned |
1374 | * pointer to produce the iotlb entries. Thus it should | |
1375 | * never overflow into the page-aligned value. | |
1376 | */ | |
53cb28cb | 1377 | assert(map->sections_nb < TARGET_PAGE_SIZE); |
68f3f65b | 1378 | |
53cb28cb MA |
1379 | if (map->sections_nb == map->sections_nb_alloc) { |
1380 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
1381 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
1382 | map->sections_nb_alloc); | |
5312bd8b | 1383 | } |
53cb28cb | 1384 | map->sections[map->sections_nb] = *section; |
dfde4e6e | 1385 | memory_region_ref(section->mr); |
53cb28cb | 1386 | return map->sections_nb++; |
5312bd8b AK |
1387 | } |
1388 | ||
058bc4b5 PB |
1389 | static void phys_section_destroy(MemoryRegion *mr) |
1390 | { | |
55b4e80b DS |
1391 | bool have_sub_page = mr->subpage; |
1392 | ||
dfde4e6e PB |
1393 | memory_region_unref(mr); |
1394 | ||
55b4e80b | 1395 | if (have_sub_page) { |
058bc4b5 | 1396 | subpage_t *subpage = container_of(mr, subpage_t, iomem); |
b4fefef9 | 1397 | object_unref(OBJECT(&subpage->iomem)); |
058bc4b5 PB |
1398 | g_free(subpage); |
1399 | } | |
1400 | } | |
1401 | ||
6092666e | 1402 | static void phys_sections_free(PhysPageMap *map) |
5312bd8b | 1403 | { |
9affd6fc PB |
1404 | while (map->sections_nb > 0) { |
1405 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
058bc4b5 PB |
1406 | phys_section_destroy(section->mr); |
1407 | } | |
9affd6fc PB |
1408 | g_free(map->sections); |
1409 | g_free(map->nodes); | |
5312bd8b AK |
1410 | } |
1411 | ||
9950322a | 1412 | static void register_subpage(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1413 | { |
9950322a | 1414 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
0f0cb164 | 1415 | subpage_t *subpage; |
a8170e5e | 1416 | hwaddr base = section->offset_within_address_space |
0f0cb164 | 1417 | & TARGET_PAGE_MASK; |
003a0cf2 | 1418 | MemoryRegionSection *existing = phys_page_find(d, base); |
0f0cb164 AK |
1419 | MemoryRegionSection subsection = { |
1420 | .offset_within_address_space = base, | |
052e87b0 | 1421 | .size = int128_make64(TARGET_PAGE_SIZE), |
0f0cb164 | 1422 | }; |
a8170e5e | 1423 | hwaddr start, end; |
0f0cb164 | 1424 | |
f3705d53 | 1425 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
0f0cb164 | 1426 | |
f3705d53 | 1427 | if (!(existing->mr->subpage)) { |
16620684 AK |
1428 | subpage = subpage_init(fv, base); |
1429 | subsection.fv = fv; | |
0f0cb164 | 1430 | subsection.mr = &subpage->iomem; |
ac1970fb | 1431 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
53cb28cb | 1432 | phys_section_add(&d->map, &subsection)); |
0f0cb164 | 1433 | } else { |
f3705d53 | 1434 | subpage = container_of(existing->mr, subpage_t, iomem); |
0f0cb164 AK |
1435 | } |
1436 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
052e87b0 | 1437 | end = start + int128_get64(section->size) - 1; |
53cb28cb MA |
1438 | subpage_register(subpage, start, end, |
1439 | phys_section_add(&d->map, section)); | |
0f0cb164 AK |
1440 | } |
1441 | ||
1442 | ||
9950322a | 1443 | static void register_multipage(FlatView *fv, |
052e87b0 | 1444 | MemoryRegionSection *section) |
33417e70 | 1445 | { |
9950322a | 1446 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
a8170e5e | 1447 | hwaddr start_addr = section->offset_within_address_space; |
53cb28cb | 1448 | uint16_t section_index = phys_section_add(&d->map, section); |
052e87b0 PB |
1449 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
1450 | TARGET_PAGE_BITS)); | |
dd81124b | 1451 | |
733d5ef5 PB |
1452 | assert(num_pages); |
1453 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
33417e70 FB |
1454 | } |
1455 | ||
8629d3fc | 1456 | void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1457 | { |
99b9cc06 | 1458 | MemoryRegionSection now = *section, remain = *section; |
052e87b0 | 1459 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
0f0cb164 | 1460 | |
733d5ef5 PB |
1461 | if (now.offset_within_address_space & ~TARGET_PAGE_MASK) { |
1462 | uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) | |
1463 | - now.offset_within_address_space; | |
1464 | ||
052e87b0 | 1465 | now.size = int128_min(int128_make64(left), now.size); |
9950322a | 1466 | register_subpage(fv, &now); |
733d5ef5 | 1467 | } else { |
052e87b0 | 1468 | now.size = int128_zero(); |
733d5ef5 | 1469 | } |
052e87b0 PB |
1470 | while (int128_ne(remain.size, now.size)) { |
1471 | remain.size = int128_sub(remain.size, now.size); | |
1472 | remain.offset_within_address_space += int128_get64(now.size); | |
1473 | remain.offset_within_region += int128_get64(now.size); | |
69b67646 | 1474 | now = remain; |
052e87b0 | 1475 | if (int128_lt(remain.size, page_size)) { |
9950322a | 1476 | register_subpage(fv, &now); |
88266249 | 1477 | } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { |
052e87b0 | 1478 | now.size = page_size; |
9950322a | 1479 | register_subpage(fv, &now); |
69b67646 | 1480 | } else { |
052e87b0 | 1481 | now.size = int128_and(now.size, int128_neg(page_size)); |
9950322a | 1482 | register_multipage(fv, &now); |
69b67646 | 1483 | } |
0f0cb164 AK |
1484 | } |
1485 | } | |
1486 | ||
62a2744c SY |
1487 | void qemu_flush_coalesced_mmio_buffer(void) |
1488 | { | |
1489 | if (kvm_enabled()) | |
1490 | kvm_flush_coalesced_mmio_buffer(); | |
1491 | } | |
1492 | ||
b2a8658e UD |
1493 | void qemu_mutex_lock_ramlist(void) |
1494 | { | |
1495 | qemu_mutex_lock(&ram_list.mutex); | |
1496 | } | |
1497 | ||
1498 | void qemu_mutex_unlock_ramlist(void) | |
1499 | { | |
1500 | qemu_mutex_unlock(&ram_list.mutex); | |
1501 | } | |
1502 | ||
be9b23c4 PX |
1503 | void ram_block_dump(Monitor *mon) |
1504 | { | |
1505 | RAMBlock *block; | |
1506 | char *psize; | |
1507 | ||
1508 | rcu_read_lock(); | |
1509 | monitor_printf(mon, "%24s %8s %18s %18s %18s\n", | |
1510 | "Block Name", "PSize", "Offset", "Used", "Total"); | |
1511 | RAMBLOCK_FOREACH(block) { | |
1512 | psize = size_to_str(block->page_size); | |
1513 | monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64 | |
1514 | " 0x%016" PRIx64 "\n", block->idstr, psize, | |
1515 | (uint64_t)block->offset, | |
1516 | (uint64_t)block->used_length, | |
1517 | (uint64_t)block->max_length); | |
1518 | g_free(psize); | |
1519 | } | |
1520 | rcu_read_unlock(); | |
1521 | } | |
1522 | ||
9c607668 AK |
1523 | #ifdef __linux__ |
1524 | /* | |
1525 | * FIXME TOCTTOU: this iterates over memory backends' mem-path, which | |
1526 | * may or may not name the same files / on the same filesystem now as | |
1527 | * when we actually open and map them. Iterate over the file | |
1528 | * descriptors instead, and use qemu_fd_getpagesize(). | |
1529 | */ | |
1530 | static int find_max_supported_pagesize(Object *obj, void *opaque) | |
1531 | { | |
9c607668 AK |
1532 | long *hpsize_min = opaque; |
1533 | ||
1534 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
2b108085 DG |
1535 | long hpsize = host_memory_backend_pagesize(MEMORY_BACKEND(obj)); |
1536 | ||
0de6e2a3 DG |
1537 | if (hpsize < *hpsize_min) { |
1538 | *hpsize_min = hpsize; | |
9c607668 AK |
1539 | } |
1540 | } | |
1541 | ||
1542 | return 0; | |
1543 | } | |
1544 | ||
1545 | long qemu_getrampagesize(void) | |
1546 | { | |
1547 | long hpsize = LONG_MAX; | |
1548 | long mainrampagesize; | |
1549 | Object *memdev_root; | |
1550 | ||
0de6e2a3 | 1551 | mainrampagesize = qemu_mempath_getpagesize(mem_path); |
9c607668 AK |
1552 | |
1553 | /* it's possible we have memory-backend objects with | |
1554 | * hugepage-backed RAM. these may get mapped into system | |
1555 | * address space via -numa parameters or memory hotplug | |
1556 | * hooks. we want to take these into account, but we | |
1557 | * also want to make sure these supported hugepage | |
1558 | * sizes are applicable across the entire range of memory | |
1559 | * we may boot from, so we take the min across all | |
1560 | * backends, and assume normal pages in cases where a | |
1561 | * backend isn't backed by hugepages. | |
1562 | */ | |
1563 | memdev_root = object_resolve_path("/objects", NULL); | |
1564 | if (memdev_root) { | |
1565 | object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize); | |
1566 | } | |
1567 | if (hpsize == LONG_MAX) { | |
1568 | /* No additional memory regions found ==> Report main RAM page size */ | |
1569 | return mainrampagesize; | |
1570 | } | |
1571 | ||
1572 | /* If NUMA is disabled or the NUMA nodes are not backed with a | |
1573 | * memory-backend, then there is at least one node using "normal" RAM, | |
1574 | * so if its page size is smaller we have got to report that size instead. | |
1575 | */ | |
1576 | if (hpsize > mainrampagesize && | |
1577 | (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) { | |
1578 | static bool warned; | |
1579 | if (!warned) { | |
1580 | error_report("Huge page support disabled (n/a for main memory)."); | |
1581 | warned = true; | |
1582 | } | |
1583 | return mainrampagesize; | |
1584 | } | |
1585 | ||
1586 | return hpsize; | |
1587 | } | |
1588 | #else | |
1589 | long qemu_getrampagesize(void) | |
1590 | { | |
1591 | return getpagesize(); | |
1592 | } | |
1593 | #endif | |
1594 | ||
e1e84ba0 | 1595 | #ifdef __linux__ |
d6af99c9 HZ |
1596 | static int64_t get_file_size(int fd) |
1597 | { | |
1598 | int64_t size = lseek(fd, 0, SEEK_END); | |
1599 | if (size < 0) { | |
1600 | return -errno; | |
1601 | } | |
1602 | return size; | |
1603 | } | |
1604 | ||
8d37b030 MAL |
1605 | static int file_ram_open(const char *path, |
1606 | const char *region_name, | |
1607 | bool *created, | |
1608 | Error **errp) | |
c902760f MT |
1609 | { |
1610 | char *filename; | |
8ca761f6 PF |
1611 | char *sanitized_name; |
1612 | char *c; | |
5c3ece79 | 1613 | int fd = -1; |
c902760f | 1614 | |
8d37b030 | 1615 | *created = false; |
fd97fd44 MA |
1616 | for (;;) { |
1617 | fd = open(path, O_RDWR); | |
1618 | if (fd >= 0) { | |
1619 | /* @path names an existing file, use it */ | |
1620 | break; | |
8d31d6b6 | 1621 | } |
fd97fd44 MA |
1622 | if (errno == ENOENT) { |
1623 | /* @path names a file that doesn't exist, create it */ | |
1624 | fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644); | |
1625 | if (fd >= 0) { | |
8d37b030 | 1626 | *created = true; |
fd97fd44 MA |
1627 | break; |
1628 | } | |
1629 | } else if (errno == EISDIR) { | |
1630 | /* @path names a directory, create a file there */ | |
1631 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ | |
8d37b030 | 1632 | sanitized_name = g_strdup(region_name); |
fd97fd44 MA |
1633 | for (c = sanitized_name; *c != '\0'; c++) { |
1634 | if (*c == '/') { | |
1635 | *c = '_'; | |
1636 | } | |
1637 | } | |
8ca761f6 | 1638 | |
fd97fd44 MA |
1639 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, |
1640 | sanitized_name); | |
1641 | g_free(sanitized_name); | |
8d31d6b6 | 1642 | |
fd97fd44 MA |
1643 | fd = mkstemp(filename); |
1644 | if (fd >= 0) { | |
1645 | unlink(filename); | |
1646 | g_free(filename); | |
1647 | break; | |
1648 | } | |
1649 | g_free(filename); | |
8d31d6b6 | 1650 | } |
fd97fd44 MA |
1651 | if (errno != EEXIST && errno != EINTR) { |
1652 | error_setg_errno(errp, errno, | |
1653 | "can't open backing store %s for guest RAM", | |
1654 | path); | |
8d37b030 | 1655 | return -1; |
fd97fd44 MA |
1656 | } |
1657 | /* | |
1658 | * Try again on EINTR and EEXIST. The latter happens when | |
1659 | * something else creates the file between our two open(). | |
1660 | */ | |
8d31d6b6 | 1661 | } |
c902760f | 1662 | |
8d37b030 MAL |
1663 | return fd; |
1664 | } | |
1665 | ||
1666 | static void *file_ram_alloc(RAMBlock *block, | |
1667 | ram_addr_t memory, | |
1668 | int fd, | |
1669 | bool truncate, | |
1670 | Error **errp) | |
1671 | { | |
1672 | void *area; | |
1673 | ||
863e9621 | 1674 | block->page_size = qemu_fd_getpagesize(fd); |
98376843 HZ |
1675 | if (block->mr->align % block->page_size) { |
1676 | error_setg(errp, "alignment 0x%" PRIx64 | |
1677 | " must be multiples of page size 0x%zx", | |
1678 | block->mr->align, block->page_size); | |
1679 | return NULL; | |
1680 | } | |
1681 | block->mr->align = MAX(block->page_size, block->mr->align); | |
8360668e HZ |
1682 | #if defined(__s390x__) |
1683 | if (kvm_enabled()) { | |
1684 | block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN); | |
1685 | } | |
1686 | #endif | |
fd97fd44 | 1687 | |
863e9621 | 1688 | if (memory < block->page_size) { |
fd97fd44 | 1689 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " |
863e9621 DDAG |
1690 | "or larger than page size 0x%zx", |
1691 | memory, block->page_size); | |
8d37b030 | 1692 | return NULL; |
1775f111 HZ |
1693 | } |
1694 | ||
863e9621 | 1695 | memory = ROUND_UP(memory, block->page_size); |
c902760f MT |
1696 | |
1697 | /* | |
1698 | * ftruncate is not supported by hugetlbfs in older | |
1699 | * hosts, so don't bother bailing out on errors. | |
1700 | * If anything goes wrong with it under other filesystems, | |
1701 | * mmap will fail. | |
d6af99c9 HZ |
1702 | * |
1703 | * Do not truncate the non-empty backend file to avoid corrupting | |
1704 | * the existing data in the file. Disabling shrinking is not | |
1705 | * enough. For example, the current vNVDIMM implementation stores | |
1706 | * the guest NVDIMM labels at the end of the backend file. If the | |
1707 | * backend file is later extended, QEMU will not be able to find | |
1708 | * those labels. Therefore, extending the non-empty backend file | |
1709 | * is disabled as well. | |
c902760f | 1710 | */ |
8d37b030 | 1711 | if (truncate && ftruncate(fd, memory)) { |
9742bf26 | 1712 | perror("ftruncate"); |
7f56e740 | 1713 | } |
c902760f | 1714 | |
d2f39add DD |
1715 | area = qemu_ram_mmap(fd, memory, block->mr->align, |
1716 | block->flags & RAM_SHARED); | |
c902760f | 1717 | if (area == MAP_FAILED) { |
7f56e740 | 1718 | error_setg_errno(errp, errno, |
fd97fd44 | 1719 | "unable to map backing store for guest RAM"); |
8d37b030 | 1720 | return NULL; |
c902760f | 1721 | } |
ef36fa14 MT |
1722 | |
1723 | if (mem_prealloc) { | |
1e356fc1 | 1724 | os_mem_prealloc(fd, area, memory, smp_cpus, errp); |
056b68af | 1725 | if (errp && *errp) { |
8d37b030 MAL |
1726 | qemu_ram_munmap(area, memory); |
1727 | return NULL; | |
056b68af | 1728 | } |
ef36fa14 MT |
1729 | } |
1730 | ||
04b16653 | 1731 | block->fd = fd; |
c902760f MT |
1732 | return area; |
1733 | } | |
1734 | #endif | |
1735 | ||
154cc9ea DDAG |
1736 | /* Allocate space within the ram_addr_t space that governs the |
1737 | * dirty bitmaps. | |
1738 | * Called with the ramlist lock held. | |
1739 | */ | |
d17b5288 | 1740 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
1741 | { |
1742 | RAMBlock *block, *next_block; | |
3e837b2c | 1743 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 | 1744 | |
49cd9ac6 SH |
1745 | assert(size != 0); /* it would hand out same offset multiple times */ |
1746 | ||
0dc3f44a | 1747 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { |
04b16653 | 1748 | return 0; |
0d53d9fe | 1749 | } |
04b16653 | 1750 | |
99e15582 | 1751 | RAMBLOCK_FOREACH(block) { |
154cc9ea | 1752 | ram_addr_t candidate, next = RAM_ADDR_MAX; |
04b16653 | 1753 | |
801110ab DDAG |
1754 | /* Align blocks to start on a 'long' in the bitmap |
1755 | * which makes the bitmap sync'ing take the fast path. | |
1756 | */ | |
154cc9ea | 1757 | candidate = block->offset + block->max_length; |
801110ab | 1758 | candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS); |
04b16653 | 1759 | |
154cc9ea DDAG |
1760 | /* Search for the closest following block |
1761 | * and find the gap. | |
1762 | */ | |
99e15582 | 1763 | RAMBLOCK_FOREACH(next_block) { |
154cc9ea | 1764 | if (next_block->offset >= candidate) { |
04b16653 AW |
1765 | next = MIN(next, next_block->offset); |
1766 | } | |
1767 | } | |
154cc9ea DDAG |
1768 | |
1769 | /* If it fits remember our place and remember the size | |
1770 | * of gap, but keep going so that we might find a smaller | |
1771 | * gap to fill so avoiding fragmentation. | |
1772 | */ | |
1773 | if (next - candidate >= size && next - candidate < mingap) { | |
1774 | offset = candidate; | |
1775 | mingap = next - candidate; | |
04b16653 | 1776 | } |
154cc9ea DDAG |
1777 | |
1778 | trace_find_ram_offset_loop(size, candidate, offset, next, mingap); | |
04b16653 | 1779 | } |
3e837b2c AW |
1780 | |
1781 | if (offset == RAM_ADDR_MAX) { | |
1782 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1783 | (uint64_t)size); | |
1784 | abort(); | |
1785 | } | |
1786 | ||
154cc9ea DDAG |
1787 | trace_find_ram_offset(size, offset); |
1788 | ||
04b16653 AW |
1789 | return offset; |
1790 | } | |
1791 | ||
b8c48993 | 1792 | unsigned long last_ram_page(void) |
d17b5288 AW |
1793 | { |
1794 | RAMBlock *block; | |
1795 | ram_addr_t last = 0; | |
1796 | ||
0dc3f44a | 1797 | rcu_read_lock(); |
99e15582 | 1798 | RAMBLOCK_FOREACH(block) { |
62be4e3a | 1799 | last = MAX(last, block->offset + block->max_length); |
0d53d9fe | 1800 | } |
0dc3f44a | 1801 | rcu_read_unlock(); |
b8c48993 | 1802 | return last >> TARGET_PAGE_BITS; |
d17b5288 AW |
1803 | } |
1804 | ||
ddb97f1d JB |
1805 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
1806 | { | |
1807 | int ret; | |
ddb97f1d JB |
1808 | |
1809 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
47c8ca53 | 1810 | if (!machine_dump_guest_core(current_machine)) { |
ddb97f1d JB |
1811 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
1812 | if (ret) { | |
1813 | perror("qemu_madvise"); | |
1814 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1815 | "but dump_guest_core=off specified\n"); | |
1816 | } | |
1817 | } | |
1818 | } | |
1819 | ||
422148d3 DDAG |
1820 | const char *qemu_ram_get_idstr(RAMBlock *rb) |
1821 | { | |
1822 | return rb->idstr; | |
1823 | } | |
1824 | ||
463a4ac2 DDAG |
1825 | bool qemu_ram_is_shared(RAMBlock *rb) |
1826 | { | |
1827 | return rb->flags & RAM_SHARED; | |
1828 | } | |
1829 | ||
2ce16640 DDAG |
1830 | /* Note: Only set at the start of postcopy */ |
1831 | bool qemu_ram_is_uf_zeroable(RAMBlock *rb) | |
1832 | { | |
1833 | return rb->flags & RAM_UF_ZEROPAGE; | |
1834 | } | |
1835 | ||
1836 | void qemu_ram_set_uf_zeroable(RAMBlock *rb) | |
1837 | { | |
1838 | rb->flags |= RAM_UF_ZEROPAGE; | |
1839 | } | |
1840 | ||
ae3a7047 | 1841 | /* Called with iothread lock held. */ |
fa53a0e5 | 1842 | void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev) |
20cfe881 | 1843 | { |
fa53a0e5 | 1844 | RAMBlock *block; |
20cfe881 | 1845 | |
c5705a77 AK |
1846 | assert(new_block); |
1847 | assert(!new_block->idstr[0]); | |
84b89d78 | 1848 | |
09e5ab63 AL |
1849 | if (dev) { |
1850 | char *id = qdev_get_dev_path(dev); | |
84b89d78 CM |
1851 | if (id) { |
1852 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 1853 | g_free(id); |
84b89d78 CM |
1854 | } |
1855 | } | |
1856 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
1857 | ||
ab0a9956 | 1858 | rcu_read_lock(); |
99e15582 | 1859 | RAMBLOCK_FOREACH(block) { |
fa53a0e5 GA |
1860 | if (block != new_block && |
1861 | !strcmp(block->idstr, new_block->idstr)) { | |
84b89d78 CM |
1862 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
1863 | new_block->idstr); | |
1864 | abort(); | |
1865 | } | |
1866 | } | |
0dc3f44a | 1867 | rcu_read_unlock(); |
c5705a77 AK |
1868 | } |
1869 | ||
ae3a7047 | 1870 | /* Called with iothread lock held. */ |
fa53a0e5 | 1871 | void qemu_ram_unset_idstr(RAMBlock *block) |
20cfe881 | 1872 | { |
ae3a7047 MD |
1873 | /* FIXME: arch_init.c assumes that this is not called throughout |
1874 | * migration. Ignore the problem since hot-unplug during migration | |
1875 | * does not work anyway. | |
1876 | */ | |
20cfe881 HT |
1877 | if (block) { |
1878 | memset(block->idstr, 0, sizeof(block->idstr)); | |
1879 | } | |
1880 | } | |
1881 | ||
863e9621 DDAG |
1882 | size_t qemu_ram_pagesize(RAMBlock *rb) |
1883 | { | |
1884 | return rb->page_size; | |
1885 | } | |
1886 | ||
67f11b5c DDAG |
1887 | /* Returns the largest size of page in use */ |
1888 | size_t qemu_ram_pagesize_largest(void) | |
1889 | { | |
1890 | RAMBlock *block; | |
1891 | size_t largest = 0; | |
1892 | ||
99e15582 | 1893 | RAMBLOCK_FOREACH(block) { |
67f11b5c DDAG |
1894 | largest = MAX(largest, qemu_ram_pagesize(block)); |
1895 | } | |
1896 | ||
1897 | return largest; | |
1898 | } | |
1899 | ||
8490fc78 LC |
1900 | static int memory_try_enable_merging(void *addr, size_t len) |
1901 | { | |
75cc7f01 | 1902 | if (!machine_mem_merge(current_machine)) { |
8490fc78 LC |
1903 | /* disabled by the user */ |
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
1908 | } | |
1909 | ||
62be4e3a MT |
1910 | /* Only legal before guest might have detected the memory size: e.g. on |
1911 | * incoming migration, or right after reset. | |
1912 | * | |
1913 | * As memory core doesn't know how is memory accessed, it is up to | |
1914 | * resize callback to update device state and/or add assertions to detect | |
1915 | * misuse, if necessary. | |
1916 | */ | |
fa53a0e5 | 1917 | int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) |
62be4e3a | 1918 | { |
62be4e3a MT |
1919 | assert(block); |
1920 | ||
4ed023ce | 1921 | newsize = HOST_PAGE_ALIGN(newsize); |
129ddaf3 | 1922 | |
62be4e3a MT |
1923 | if (block->used_length == newsize) { |
1924 | return 0; | |
1925 | } | |
1926 | ||
1927 | if (!(block->flags & RAM_RESIZEABLE)) { | |
1928 | error_setg_errno(errp, EINVAL, | |
1929 | "Length mismatch: %s: 0x" RAM_ADDR_FMT | |
1930 | " in != 0x" RAM_ADDR_FMT, block->idstr, | |
1931 | newsize, block->used_length); | |
1932 | return -EINVAL; | |
1933 | } | |
1934 | ||
1935 | if (block->max_length < newsize) { | |
1936 | error_setg_errno(errp, EINVAL, | |
1937 | "Length too large: %s: 0x" RAM_ADDR_FMT | |
1938 | " > 0x" RAM_ADDR_FMT, block->idstr, | |
1939 | newsize, block->max_length); | |
1940 | return -EINVAL; | |
1941 | } | |
1942 | ||
1943 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); | |
1944 | block->used_length = newsize; | |
58d2707e PB |
1945 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length, |
1946 | DIRTY_CLIENTS_ALL); | |
62be4e3a MT |
1947 | memory_region_set_size(block->mr, newsize); |
1948 | if (block->resized) { | |
1949 | block->resized(block->idstr, newsize, block->host); | |
1950 | } | |
1951 | return 0; | |
1952 | } | |
1953 | ||
5b82b703 SH |
1954 | /* Called with ram_list.mutex held */ |
1955 | static void dirty_memory_extend(ram_addr_t old_ram_size, | |
1956 | ram_addr_t new_ram_size) | |
1957 | { | |
1958 | ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size, | |
1959 | DIRTY_MEMORY_BLOCK_SIZE); | |
1960 | ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size, | |
1961 | DIRTY_MEMORY_BLOCK_SIZE); | |
1962 | int i; | |
1963 | ||
1964 | /* Only need to extend if block count increased */ | |
1965 | if (new_num_blocks <= old_num_blocks) { | |
1966 | return; | |
1967 | } | |
1968 | ||
1969 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { | |
1970 | DirtyMemoryBlocks *old_blocks; | |
1971 | DirtyMemoryBlocks *new_blocks; | |
1972 | int j; | |
1973 | ||
1974 | old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]); | |
1975 | new_blocks = g_malloc(sizeof(*new_blocks) + | |
1976 | sizeof(new_blocks->blocks[0]) * new_num_blocks); | |
1977 | ||
1978 | if (old_num_blocks) { | |
1979 | memcpy(new_blocks->blocks, old_blocks->blocks, | |
1980 | old_num_blocks * sizeof(old_blocks->blocks[0])); | |
1981 | } | |
1982 | ||
1983 | for (j = old_num_blocks; j < new_num_blocks; j++) { | |
1984 | new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE); | |
1985 | } | |
1986 | ||
1987 | atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks); | |
1988 | ||
1989 | if (old_blocks) { | |
1990 | g_free_rcu(old_blocks, rcu); | |
1991 | } | |
1992 | } | |
1993 | } | |
1994 | ||
06329cce | 1995 | static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared) |
c5705a77 | 1996 | { |
e1c57ab8 | 1997 | RAMBlock *block; |
0d53d9fe | 1998 | RAMBlock *last_block = NULL; |
2152f5ca | 1999 | ram_addr_t old_ram_size, new_ram_size; |
37aa7a0e | 2000 | Error *err = NULL; |
2152f5ca | 2001 | |
b8c48993 | 2002 | old_ram_size = last_ram_page(); |
c5705a77 | 2003 | |
b2a8658e | 2004 | qemu_mutex_lock_ramlist(); |
9b8424d5 | 2005 | new_block->offset = find_ram_offset(new_block->max_length); |
e1c57ab8 PB |
2006 | |
2007 | if (!new_block->host) { | |
2008 | if (xen_enabled()) { | |
9b8424d5 | 2009 | xen_ram_alloc(new_block->offset, new_block->max_length, |
37aa7a0e MA |
2010 | new_block->mr, &err); |
2011 | if (err) { | |
2012 | error_propagate(errp, err); | |
2013 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 2014 | return; |
37aa7a0e | 2015 | } |
e1c57ab8 | 2016 | } else { |
9b8424d5 | 2017 | new_block->host = phys_mem_alloc(new_block->max_length, |
06329cce | 2018 | &new_block->mr->align, shared); |
39228250 | 2019 | if (!new_block->host) { |
ef701d7b HT |
2020 | error_setg_errno(errp, errno, |
2021 | "cannot set up guest memory '%s'", | |
2022 | memory_region_name(new_block->mr)); | |
2023 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 2024 | return; |
39228250 | 2025 | } |
9b8424d5 | 2026 | memory_try_enable_merging(new_block->host, new_block->max_length); |
6977dfe6 | 2027 | } |
c902760f | 2028 | } |
94a6b54f | 2029 | |
dd631697 LZ |
2030 | new_ram_size = MAX(old_ram_size, |
2031 | (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS); | |
2032 | if (new_ram_size > old_ram_size) { | |
5b82b703 | 2033 | dirty_memory_extend(old_ram_size, new_ram_size); |
dd631697 | 2034 | } |
0d53d9fe MD |
2035 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, |
2036 | * QLIST (which has an RCU-friendly variant) does not have insertion at | |
2037 | * tail, so save the last element in last_block. | |
2038 | */ | |
99e15582 | 2039 | RAMBLOCK_FOREACH(block) { |
0d53d9fe | 2040 | last_block = block; |
9b8424d5 | 2041 | if (block->max_length < new_block->max_length) { |
abb26d63 PB |
2042 | break; |
2043 | } | |
2044 | } | |
2045 | if (block) { | |
0dc3f44a | 2046 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); |
0d53d9fe | 2047 | } else if (last_block) { |
0dc3f44a | 2048 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); |
0d53d9fe | 2049 | } else { /* list is empty */ |
0dc3f44a | 2050 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); |
abb26d63 | 2051 | } |
0d6d3c87 | 2052 | ram_list.mru_block = NULL; |
94a6b54f | 2053 | |
0dc3f44a MD |
2054 | /* Write list before version */ |
2055 | smp_wmb(); | |
f798b07f | 2056 | ram_list.version++; |
b2a8658e | 2057 | qemu_mutex_unlock_ramlist(); |
f798b07f | 2058 | |
9b8424d5 | 2059 | cpu_physical_memory_set_dirty_range(new_block->offset, |
58d2707e PB |
2060 | new_block->used_length, |
2061 | DIRTY_CLIENTS_ALL); | |
94a6b54f | 2062 | |
a904c911 PB |
2063 | if (new_block->host) { |
2064 | qemu_ram_setup_dump(new_block->host, new_block->max_length); | |
2065 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); | |
c2cd627d | 2066 | /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */ |
a904c911 | 2067 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK); |
0987d735 | 2068 | ram_block_notify_add(new_block->host, new_block->max_length); |
e1c57ab8 | 2069 | } |
94a6b54f | 2070 | } |
e9a1ab19 | 2071 | |
0b183fc8 | 2072 | #ifdef __linux__ |
38b3362d MAL |
2073 | RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr, |
2074 | bool share, int fd, | |
2075 | Error **errp) | |
e1c57ab8 PB |
2076 | { |
2077 | RAMBlock *new_block; | |
ef701d7b | 2078 | Error *local_err = NULL; |
8d37b030 | 2079 | int64_t file_size; |
e1c57ab8 PB |
2080 | |
2081 | if (xen_enabled()) { | |
7f56e740 | 2082 | error_setg(errp, "-mem-path not supported with Xen"); |
528f46af | 2083 | return NULL; |
e1c57ab8 PB |
2084 | } |
2085 | ||
e45e7ae2 MAL |
2086 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
2087 | error_setg(errp, | |
2088 | "host lacks kvm mmu notifiers, -mem-path unsupported"); | |
2089 | return NULL; | |
2090 | } | |
2091 | ||
e1c57ab8 PB |
2092 | if (phys_mem_alloc != qemu_anon_ram_alloc) { |
2093 | /* | |
2094 | * file_ram_alloc() needs to allocate just like | |
2095 | * phys_mem_alloc, but we haven't bothered to provide | |
2096 | * a hook there. | |
2097 | */ | |
7f56e740 PB |
2098 | error_setg(errp, |
2099 | "-mem-path not supported with this accelerator"); | |
528f46af | 2100 | return NULL; |
e1c57ab8 PB |
2101 | } |
2102 | ||
4ed023ce | 2103 | size = HOST_PAGE_ALIGN(size); |
8d37b030 MAL |
2104 | file_size = get_file_size(fd); |
2105 | if (file_size > 0 && file_size < size) { | |
2106 | error_setg(errp, "backing store %s size 0x%" PRIx64 | |
2107 | " does not match 'size' option 0x" RAM_ADDR_FMT, | |
2108 | mem_path, file_size, size); | |
8d37b030 MAL |
2109 | return NULL; |
2110 | } | |
2111 | ||
e1c57ab8 PB |
2112 | new_block = g_malloc0(sizeof(*new_block)); |
2113 | new_block->mr = mr; | |
9b8424d5 MT |
2114 | new_block->used_length = size; |
2115 | new_block->max_length = size; | |
dbcb8981 | 2116 | new_block->flags = share ? RAM_SHARED : 0; |
8d37b030 | 2117 | new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp); |
7f56e740 PB |
2118 | if (!new_block->host) { |
2119 | g_free(new_block); | |
528f46af | 2120 | return NULL; |
7f56e740 PB |
2121 | } |
2122 | ||
06329cce | 2123 | ram_block_add(new_block, &local_err, share); |
ef701d7b HT |
2124 | if (local_err) { |
2125 | g_free(new_block); | |
2126 | error_propagate(errp, local_err); | |
528f46af | 2127 | return NULL; |
ef701d7b | 2128 | } |
528f46af | 2129 | return new_block; |
38b3362d MAL |
2130 | |
2131 | } | |
2132 | ||
2133 | ||
2134 | RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, | |
2135 | bool share, const char *mem_path, | |
2136 | Error **errp) | |
2137 | { | |
2138 | int fd; | |
2139 | bool created; | |
2140 | RAMBlock *block; | |
2141 | ||
2142 | fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp); | |
2143 | if (fd < 0) { | |
2144 | return NULL; | |
2145 | } | |
2146 | ||
2147 | block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp); | |
2148 | if (!block) { | |
2149 | if (created) { | |
2150 | unlink(mem_path); | |
2151 | } | |
2152 | close(fd); | |
2153 | return NULL; | |
2154 | } | |
2155 | ||
2156 | return block; | |
e1c57ab8 | 2157 | } |
0b183fc8 | 2158 | #endif |
e1c57ab8 | 2159 | |
62be4e3a | 2160 | static |
528f46af FZ |
2161 | RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, |
2162 | void (*resized)(const char*, | |
2163 | uint64_t length, | |
2164 | void *host), | |
06329cce | 2165 | void *host, bool resizeable, bool share, |
528f46af | 2166 | MemoryRegion *mr, Error **errp) |
e1c57ab8 PB |
2167 | { |
2168 | RAMBlock *new_block; | |
ef701d7b | 2169 | Error *local_err = NULL; |
e1c57ab8 | 2170 | |
4ed023ce DDAG |
2171 | size = HOST_PAGE_ALIGN(size); |
2172 | max_size = HOST_PAGE_ALIGN(max_size); | |
e1c57ab8 PB |
2173 | new_block = g_malloc0(sizeof(*new_block)); |
2174 | new_block->mr = mr; | |
62be4e3a | 2175 | new_block->resized = resized; |
9b8424d5 MT |
2176 | new_block->used_length = size; |
2177 | new_block->max_length = max_size; | |
62be4e3a | 2178 | assert(max_size >= size); |
e1c57ab8 | 2179 | new_block->fd = -1; |
863e9621 | 2180 | new_block->page_size = getpagesize(); |
e1c57ab8 PB |
2181 | new_block->host = host; |
2182 | if (host) { | |
7bd4f430 | 2183 | new_block->flags |= RAM_PREALLOC; |
e1c57ab8 | 2184 | } |
62be4e3a MT |
2185 | if (resizeable) { |
2186 | new_block->flags |= RAM_RESIZEABLE; | |
2187 | } | |
06329cce | 2188 | ram_block_add(new_block, &local_err, share); |
ef701d7b HT |
2189 | if (local_err) { |
2190 | g_free(new_block); | |
2191 | error_propagate(errp, local_err); | |
528f46af | 2192 | return NULL; |
ef701d7b | 2193 | } |
528f46af | 2194 | return new_block; |
e1c57ab8 PB |
2195 | } |
2196 | ||
528f46af | 2197 | RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
62be4e3a MT |
2198 | MemoryRegion *mr, Error **errp) |
2199 | { | |
06329cce MA |
2200 | return qemu_ram_alloc_internal(size, size, NULL, host, false, |
2201 | false, mr, errp); | |
62be4e3a MT |
2202 | } |
2203 | ||
06329cce MA |
2204 | RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share, |
2205 | MemoryRegion *mr, Error **errp) | |
6977dfe6 | 2206 | { |
06329cce MA |
2207 | return qemu_ram_alloc_internal(size, size, NULL, NULL, false, |
2208 | share, mr, errp); | |
62be4e3a MT |
2209 | } |
2210 | ||
528f46af | 2211 | RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, |
62be4e3a MT |
2212 | void (*resized)(const char*, |
2213 | uint64_t length, | |
2214 | void *host), | |
2215 | MemoryRegion *mr, Error **errp) | |
2216 | { | |
06329cce MA |
2217 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, |
2218 | false, mr, errp); | |
6977dfe6 YT |
2219 | } |
2220 | ||
43771539 PB |
2221 | static void reclaim_ramblock(RAMBlock *block) |
2222 | { | |
2223 | if (block->flags & RAM_PREALLOC) { | |
2224 | ; | |
2225 | } else if (xen_enabled()) { | |
2226 | xen_invalidate_map_cache_entry(block->host); | |
2227 | #ifndef _WIN32 | |
2228 | } else if (block->fd >= 0) { | |
2f3a2bb1 | 2229 | qemu_ram_munmap(block->host, block->max_length); |
43771539 PB |
2230 | close(block->fd); |
2231 | #endif | |
2232 | } else { | |
2233 | qemu_anon_ram_free(block->host, block->max_length); | |
2234 | } | |
2235 | g_free(block); | |
2236 | } | |
2237 | ||
f1060c55 | 2238 | void qemu_ram_free(RAMBlock *block) |
e9a1ab19 | 2239 | { |
85bc2a15 MAL |
2240 | if (!block) { |
2241 | return; | |
2242 | } | |
2243 | ||
0987d735 PB |
2244 | if (block->host) { |
2245 | ram_block_notify_remove(block->host, block->max_length); | |
2246 | } | |
2247 | ||
b2a8658e | 2248 | qemu_mutex_lock_ramlist(); |
f1060c55 FZ |
2249 | QLIST_REMOVE_RCU(block, next); |
2250 | ram_list.mru_block = NULL; | |
2251 | /* Write list before version */ | |
2252 | smp_wmb(); | |
2253 | ram_list.version++; | |
2254 | call_rcu(block, reclaim_ramblock, rcu); | |
b2a8658e | 2255 | qemu_mutex_unlock_ramlist(); |
e9a1ab19 FB |
2256 | } |
2257 | ||
cd19cfa2 HY |
2258 | #ifndef _WIN32 |
2259 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
2260 | { | |
2261 | RAMBlock *block; | |
2262 | ram_addr_t offset; | |
2263 | int flags; | |
2264 | void *area, *vaddr; | |
2265 | ||
99e15582 | 2266 | RAMBLOCK_FOREACH(block) { |
cd19cfa2 | 2267 | offset = addr - block->offset; |
9b8424d5 | 2268 | if (offset < block->max_length) { |
1240be24 | 2269 | vaddr = ramblock_ptr(block, offset); |
7bd4f430 | 2270 | if (block->flags & RAM_PREALLOC) { |
cd19cfa2 | 2271 | ; |
dfeaf2ab MA |
2272 | } else if (xen_enabled()) { |
2273 | abort(); | |
cd19cfa2 HY |
2274 | } else { |
2275 | flags = MAP_FIXED; | |
3435f395 | 2276 | if (block->fd >= 0) { |
dbcb8981 PB |
2277 | flags |= (block->flags & RAM_SHARED ? |
2278 | MAP_SHARED : MAP_PRIVATE); | |
3435f395 MA |
2279 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
2280 | flags, block->fd, offset); | |
cd19cfa2 | 2281 | } else { |
2eb9fbaa MA |
2282 | /* |
2283 | * Remap needs to match alloc. Accelerators that | |
2284 | * set phys_mem_alloc never remap. If they did, | |
2285 | * we'd need a remap hook here. | |
2286 | */ | |
2287 | assert(phys_mem_alloc == qemu_anon_ram_alloc); | |
2288 | ||
cd19cfa2 HY |
2289 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
2290 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2291 | flags, -1, 0); | |
cd19cfa2 HY |
2292 | } |
2293 | if (area != vaddr) { | |
493d89bf AF |
2294 | error_report("Could not remap addr: " |
2295 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "", | |
2296 | length, addr); | |
cd19cfa2 HY |
2297 | exit(1); |
2298 | } | |
8490fc78 | 2299 | memory_try_enable_merging(vaddr, length); |
ddb97f1d | 2300 | qemu_ram_setup_dump(vaddr, length); |
cd19cfa2 | 2301 | } |
cd19cfa2 HY |
2302 | } |
2303 | } | |
2304 | } | |
2305 | #endif /* !_WIN32 */ | |
2306 | ||
1b5ec234 | 2307 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
ae3a7047 MD |
2308 | * This should not be used for general purpose DMA. Use address_space_map |
2309 | * or address_space_rw instead. For local memory (e.g. video ram) that the | |
2310 | * device owns, use memory_region_get_ram_ptr. | |
0dc3f44a | 2311 | * |
49b24afc | 2312 | * Called within RCU critical section. |
1b5ec234 | 2313 | */ |
0878d0e1 | 2314 | void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) |
1b5ec234 | 2315 | { |
3655cb9c GA |
2316 | RAMBlock *block = ram_block; |
2317 | ||
2318 | if (block == NULL) { | |
2319 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2320 | addr -= block->offset; |
3655cb9c | 2321 | } |
ae3a7047 MD |
2322 | |
2323 | if (xen_enabled() && block->host == NULL) { | |
0d6d3c87 PB |
2324 | /* We need to check if the requested address is in the RAM |
2325 | * because we don't want to map the entire memory in QEMU. | |
2326 | * In that case just map until the end of the page. | |
2327 | */ | |
2328 | if (block->offset == 0) { | |
1ff7c598 | 2329 | return xen_map_cache(addr, 0, 0, false); |
0d6d3c87 | 2330 | } |
ae3a7047 | 2331 | |
1ff7c598 | 2332 | block->host = xen_map_cache(block->offset, block->max_length, 1, false); |
0d6d3c87 | 2333 | } |
0878d0e1 | 2334 | return ramblock_ptr(block, addr); |
dc828ca1 PB |
2335 | } |
2336 | ||
0878d0e1 | 2337 | /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr |
ae3a7047 | 2338 | * but takes a size argument. |
0dc3f44a | 2339 | * |
e81bcda5 | 2340 | * Called within RCU critical section. |
ae3a7047 | 2341 | */ |
3655cb9c | 2342 | static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr, |
f5aa69bd | 2343 | hwaddr *size, bool lock) |
38bee5dc | 2344 | { |
3655cb9c | 2345 | RAMBlock *block = ram_block; |
8ab934f9 SS |
2346 | if (*size == 0) { |
2347 | return NULL; | |
2348 | } | |
e81bcda5 | 2349 | |
3655cb9c GA |
2350 | if (block == NULL) { |
2351 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2352 | addr -= block->offset; |
3655cb9c | 2353 | } |
0878d0e1 | 2354 | *size = MIN(*size, block->max_length - addr); |
e81bcda5 PB |
2355 | |
2356 | if (xen_enabled() && block->host == NULL) { | |
2357 | /* We need to check if the requested address is in the RAM | |
2358 | * because we don't want to map the entire memory in QEMU. | |
2359 | * In that case just map the requested area. | |
2360 | */ | |
2361 | if (block->offset == 0) { | |
f5aa69bd | 2362 | return xen_map_cache(addr, *size, lock, lock); |
38bee5dc SS |
2363 | } |
2364 | ||
f5aa69bd | 2365 | block->host = xen_map_cache(block->offset, block->max_length, 1, lock); |
38bee5dc | 2366 | } |
e81bcda5 | 2367 | |
0878d0e1 | 2368 | return ramblock_ptr(block, addr); |
38bee5dc SS |
2369 | } |
2370 | ||
f90bb71b DDAG |
2371 | /* Return the offset of a hostpointer within a ramblock */ |
2372 | ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host) | |
2373 | { | |
2374 | ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host; | |
2375 | assert((uintptr_t)host >= (uintptr_t)rb->host); | |
2376 | assert(res < rb->max_length); | |
2377 | ||
2378 | return res; | |
2379 | } | |
2380 | ||
422148d3 DDAG |
2381 | /* |
2382 | * Translates a host ptr back to a RAMBlock, a ram_addr and an offset | |
2383 | * in that RAMBlock. | |
2384 | * | |
2385 | * ptr: Host pointer to look up | |
2386 | * round_offset: If true round the result offset down to a page boundary | |
2387 | * *ram_addr: set to result ram_addr | |
2388 | * *offset: set to result offset within the RAMBlock | |
2389 | * | |
2390 | * Returns: RAMBlock (or NULL if not found) | |
ae3a7047 MD |
2391 | * |
2392 | * By the time this function returns, the returned pointer is not protected | |
2393 | * by RCU anymore. If the caller is not within an RCU critical section and | |
2394 | * does not hold the iothread lock, it must have other means of protecting the | |
2395 | * pointer, such as a reference to the region that includes the incoming | |
2396 | * ram_addr_t. | |
2397 | */ | |
422148d3 | 2398 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
422148d3 | 2399 | ram_addr_t *offset) |
5579c7f3 | 2400 | { |
94a6b54f PB |
2401 | RAMBlock *block; |
2402 | uint8_t *host = ptr; | |
2403 | ||
868bb33f | 2404 | if (xen_enabled()) { |
f615f396 | 2405 | ram_addr_t ram_addr; |
0dc3f44a | 2406 | rcu_read_lock(); |
f615f396 PB |
2407 | ram_addr = xen_ram_addr_from_mapcache(ptr); |
2408 | block = qemu_get_ram_block(ram_addr); | |
422148d3 | 2409 | if (block) { |
d6b6aec4 | 2410 | *offset = ram_addr - block->offset; |
422148d3 | 2411 | } |
0dc3f44a | 2412 | rcu_read_unlock(); |
422148d3 | 2413 | return block; |
712c2b41 SS |
2414 | } |
2415 | ||
0dc3f44a MD |
2416 | rcu_read_lock(); |
2417 | block = atomic_rcu_read(&ram_list.mru_block); | |
9b8424d5 | 2418 | if (block && block->host && host - block->host < block->max_length) { |
23887b79 PB |
2419 | goto found; |
2420 | } | |
2421 | ||
99e15582 | 2422 | RAMBLOCK_FOREACH(block) { |
432d268c JN |
2423 | /* This case append when the block is not mapped. */ |
2424 | if (block->host == NULL) { | |
2425 | continue; | |
2426 | } | |
9b8424d5 | 2427 | if (host - block->host < block->max_length) { |
23887b79 | 2428 | goto found; |
f471a17e | 2429 | } |
94a6b54f | 2430 | } |
432d268c | 2431 | |
0dc3f44a | 2432 | rcu_read_unlock(); |
1b5ec234 | 2433 | return NULL; |
23887b79 PB |
2434 | |
2435 | found: | |
422148d3 DDAG |
2436 | *offset = (host - block->host); |
2437 | if (round_offset) { | |
2438 | *offset &= TARGET_PAGE_MASK; | |
2439 | } | |
0dc3f44a | 2440 | rcu_read_unlock(); |
422148d3 DDAG |
2441 | return block; |
2442 | } | |
2443 | ||
e3dd7493 DDAG |
2444 | /* |
2445 | * Finds the named RAMBlock | |
2446 | * | |
2447 | * name: The name of RAMBlock to find | |
2448 | * | |
2449 | * Returns: RAMBlock (or NULL if not found) | |
2450 | */ | |
2451 | RAMBlock *qemu_ram_block_by_name(const char *name) | |
2452 | { | |
2453 | RAMBlock *block; | |
2454 | ||
99e15582 | 2455 | RAMBLOCK_FOREACH(block) { |
e3dd7493 DDAG |
2456 | if (!strcmp(name, block->idstr)) { |
2457 | return block; | |
2458 | } | |
2459 | } | |
2460 | ||
2461 | return NULL; | |
2462 | } | |
2463 | ||
422148d3 DDAG |
2464 | /* Some of the softmmu routines need to translate from a host pointer |
2465 | (typically a TLB entry) back to a ram offset. */ | |
07bdaa41 | 2466 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
422148d3 DDAG |
2467 | { |
2468 | RAMBlock *block; | |
f615f396 | 2469 | ram_addr_t offset; |
422148d3 | 2470 | |
f615f396 | 2471 | block = qemu_ram_block_from_host(ptr, false, &offset); |
422148d3 | 2472 | if (!block) { |
07bdaa41 | 2473 | return RAM_ADDR_INVALID; |
422148d3 DDAG |
2474 | } |
2475 | ||
07bdaa41 | 2476 | return block->offset + offset; |
e890261f | 2477 | } |
f471a17e | 2478 | |
27266271 PM |
2479 | /* Called within RCU critical section. */ |
2480 | void memory_notdirty_write_prepare(NotDirtyInfo *ndi, | |
2481 | CPUState *cpu, | |
2482 | vaddr mem_vaddr, | |
2483 | ram_addr_t ram_addr, | |
2484 | unsigned size) | |
2485 | { | |
2486 | ndi->cpu = cpu; | |
2487 | ndi->ram_addr = ram_addr; | |
2488 | ndi->mem_vaddr = mem_vaddr; | |
2489 | ndi->size = size; | |
2490 | ndi->locked = false; | |
ba051fb5 | 2491 | |
5aa1ef71 | 2492 | assert(tcg_enabled()); |
52159192 | 2493 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { |
27266271 | 2494 | ndi->locked = true; |
ba051fb5 | 2495 | tb_lock(); |
0e0df1e2 | 2496 | tb_invalidate_phys_page_fast(ram_addr, size); |
3a7d929e | 2497 | } |
27266271 PM |
2498 | } |
2499 | ||
2500 | /* Called within RCU critical section. */ | |
2501 | void memory_notdirty_write_complete(NotDirtyInfo *ndi) | |
2502 | { | |
2503 | if (ndi->locked) { | |
2504 | tb_unlock(); | |
2505 | } | |
2506 | ||
2507 | /* Set both VGA and migration bits for simplicity and to remove | |
2508 | * the notdirty callback faster. | |
2509 | */ | |
2510 | cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size, | |
2511 | DIRTY_CLIENTS_NOCODE); | |
2512 | /* we remove the notdirty callback only if the code has been | |
2513 | flushed */ | |
2514 | if (!cpu_physical_memory_is_clean(ndi->ram_addr)) { | |
2515 | tlb_set_dirty(ndi->cpu, ndi->mem_vaddr); | |
2516 | } | |
2517 | } | |
2518 | ||
2519 | /* Called within RCU critical section. */ | |
2520 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, | |
2521 | uint64_t val, unsigned size) | |
2522 | { | |
2523 | NotDirtyInfo ndi; | |
2524 | ||
2525 | memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr, | |
2526 | ram_addr, size); | |
2527 | ||
0e0df1e2 AK |
2528 | switch (size) { |
2529 | case 1: | |
0878d0e1 | 2530 | stb_p(qemu_map_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2531 | break; |
2532 | case 2: | |
0878d0e1 | 2533 | stw_p(qemu_map_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2534 | break; |
2535 | case 4: | |
0878d0e1 | 2536 | stl_p(qemu_map_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 | 2537 | break; |
ad52878f AB |
2538 | case 8: |
2539 | stq_p(qemu_map_ram_ptr(NULL, ram_addr), val); | |
2540 | break; | |
0e0df1e2 AK |
2541 | default: |
2542 | abort(); | |
3a7d929e | 2543 | } |
27266271 | 2544 | memory_notdirty_write_complete(&ndi); |
9fa3e853 FB |
2545 | } |
2546 | ||
b018ddf6 | 2547 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
2548 | unsigned size, bool is_write, |
2549 | MemTxAttrs attrs) | |
b018ddf6 PB |
2550 | { |
2551 | return is_write; | |
2552 | } | |
2553 | ||
0e0df1e2 | 2554 | static const MemoryRegionOps notdirty_mem_ops = { |
0e0df1e2 | 2555 | .write = notdirty_mem_write, |
b018ddf6 | 2556 | .valid.accepts = notdirty_mem_accepts, |
0e0df1e2 | 2557 | .endianness = DEVICE_NATIVE_ENDIAN, |
ad52878f AB |
2558 | .valid = { |
2559 | .min_access_size = 1, | |
2560 | .max_access_size = 8, | |
2561 | .unaligned = false, | |
2562 | }, | |
2563 | .impl = { | |
2564 | .min_access_size = 1, | |
2565 | .max_access_size = 8, | |
2566 | .unaligned = false, | |
2567 | }, | |
1ccde1cb FB |
2568 | }; |
2569 | ||
0f459d16 | 2570 | /* Generate a debug exception if a watchpoint has been hit. */ |
66b9b43c | 2571 | static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) |
0f459d16 | 2572 | { |
93afeade | 2573 | CPUState *cpu = current_cpu; |
568496c0 | 2574 | CPUClass *cc = CPU_GET_CLASS(cpu); |
0f459d16 | 2575 | target_ulong vaddr; |
a1d1bb31 | 2576 | CPUWatchpoint *wp; |
0f459d16 | 2577 | |
5aa1ef71 | 2578 | assert(tcg_enabled()); |
ff4700b0 | 2579 | if (cpu->watchpoint_hit) { |
06d55cc1 AL |
2580 | /* We re-entered the check after replacing the TB. Now raise |
2581 | * the debug interrupt so that is will trigger after the | |
2582 | * current instruction. */ | |
93afeade | 2583 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); |
06d55cc1 AL |
2584 | return; |
2585 | } | |
93afeade | 2586 | vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
40612000 | 2587 | vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len); |
ff4700b0 | 2588 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d PM |
2589 | if (cpu_watchpoint_address_matches(wp, vaddr, len) |
2590 | && (wp->flags & flags)) { | |
08225676 PM |
2591 | if (flags == BP_MEM_READ) { |
2592 | wp->flags |= BP_WATCHPOINT_HIT_READ; | |
2593 | } else { | |
2594 | wp->flags |= BP_WATCHPOINT_HIT_WRITE; | |
2595 | } | |
2596 | wp->hitaddr = vaddr; | |
66b9b43c | 2597 | wp->hitattrs = attrs; |
ff4700b0 | 2598 | if (!cpu->watchpoint_hit) { |
568496c0 SF |
2599 | if (wp->flags & BP_CPU && |
2600 | !cc->debug_check_watchpoint(cpu, wp)) { | |
2601 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
2602 | continue; | |
2603 | } | |
ff4700b0 | 2604 | cpu->watchpoint_hit = wp; |
a5e99826 | 2605 | |
8d04fb55 JK |
2606 | /* Both tb_lock and iothread_mutex will be reset when |
2607 | * cpu_loop_exit or cpu_loop_exit_noexc longjmp | |
2608 | * back into the cpu_exec main loop. | |
a5e99826 FK |
2609 | */ |
2610 | tb_lock(); | |
239c51a5 | 2611 | tb_check_watchpoint(cpu); |
6e140f28 | 2612 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
27103424 | 2613 | cpu->exception_index = EXCP_DEBUG; |
5638d180 | 2614 | cpu_loop_exit(cpu); |
6e140f28 | 2615 | } else { |
9b990ee5 RH |
2616 | /* Force execution of one insn next time. */ |
2617 | cpu->cflags_next_tb = 1 | curr_cflags(); | |
6886b980 | 2618 | cpu_loop_exit_noexc(cpu); |
6e140f28 | 2619 | } |
06d55cc1 | 2620 | } |
6e140f28 AL |
2621 | } else { |
2622 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
2623 | } |
2624 | } | |
2625 | } | |
2626 | ||
6658ffb8 PB |
2627 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
2628 | so these check for a hit then pass through to the normal out-of-line | |
2629 | phys routines. */ | |
66b9b43c PM |
2630 | static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata, |
2631 | unsigned size, MemTxAttrs attrs) | |
6658ffb8 | 2632 | { |
66b9b43c PM |
2633 | MemTxResult res; |
2634 | uint64_t data; | |
79ed0416 PM |
2635 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2636 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2637 | |
2638 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ); | |
1ec9b909 | 2639 | switch (size) { |
66b9b43c | 2640 | case 1: |
79ed0416 | 2641 | data = address_space_ldub(as, addr, attrs, &res); |
66b9b43c PM |
2642 | break; |
2643 | case 2: | |
79ed0416 | 2644 | data = address_space_lduw(as, addr, attrs, &res); |
66b9b43c PM |
2645 | break; |
2646 | case 4: | |
79ed0416 | 2647 | data = address_space_ldl(as, addr, attrs, &res); |
66b9b43c | 2648 | break; |
306526b5 PB |
2649 | case 8: |
2650 | data = address_space_ldq(as, addr, attrs, &res); | |
2651 | break; | |
1ec9b909 AK |
2652 | default: abort(); |
2653 | } | |
66b9b43c PM |
2654 | *pdata = data; |
2655 | return res; | |
6658ffb8 PB |
2656 | } |
2657 | ||
66b9b43c PM |
2658 | static MemTxResult watch_mem_write(void *opaque, hwaddr addr, |
2659 | uint64_t val, unsigned size, | |
2660 | MemTxAttrs attrs) | |
6658ffb8 | 2661 | { |
66b9b43c | 2662 | MemTxResult res; |
79ed0416 PM |
2663 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2664 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2665 | |
2666 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE); | |
1ec9b909 | 2667 | switch (size) { |
67364150 | 2668 | case 1: |
79ed0416 | 2669 | address_space_stb(as, addr, val, attrs, &res); |
67364150 MF |
2670 | break; |
2671 | case 2: | |
79ed0416 | 2672 | address_space_stw(as, addr, val, attrs, &res); |
67364150 MF |
2673 | break; |
2674 | case 4: | |
79ed0416 | 2675 | address_space_stl(as, addr, val, attrs, &res); |
67364150 | 2676 | break; |
306526b5 PB |
2677 | case 8: |
2678 | address_space_stq(as, addr, val, attrs, &res); | |
2679 | break; | |
1ec9b909 AK |
2680 | default: abort(); |
2681 | } | |
66b9b43c | 2682 | return res; |
6658ffb8 PB |
2683 | } |
2684 | ||
1ec9b909 | 2685 | static const MemoryRegionOps watch_mem_ops = { |
66b9b43c PM |
2686 | .read_with_attrs = watch_mem_read, |
2687 | .write_with_attrs = watch_mem_write, | |
1ec9b909 | 2688 | .endianness = DEVICE_NATIVE_ENDIAN, |
306526b5 PB |
2689 | .valid = { |
2690 | .min_access_size = 1, | |
2691 | .max_access_size = 8, | |
2692 | .unaligned = false, | |
2693 | }, | |
2694 | .impl = { | |
2695 | .min_access_size = 1, | |
2696 | .max_access_size = 8, | |
2697 | .unaligned = false, | |
2698 | }, | |
6658ffb8 | 2699 | }; |
6658ffb8 | 2700 | |
b2a44fca PB |
2701 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, |
2702 | MemTxAttrs attrs, uint8_t *buf, int len); | |
16620684 AK |
2703 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
2704 | const uint8_t *buf, int len); | |
2705 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | |
eace72b7 | 2706 | bool is_write, MemTxAttrs attrs); |
16620684 | 2707 | |
f25a49e0 PM |
2708 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, |
2709 | unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2710 | { |
acc9d80b | 2711 | subpage_t *subpage = opaque; |
ff6cff75 | 2712 | uint8_t buf[8]; |
5c9eb028 | 2713 | MemTxResult res; |
791af8c8 | 2714 | |
db7b5426 | 2715 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2716 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, |
acc9d80b | 2717 | subpage, len, addr); |
db7b5426 | 2718 | #endif |
16620684 | 2719 | res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); |
5c9eb028 PM |
2720 | if (res) { |
2721 | return res; | |
f25a49e0 | 2722 | } |
acc9d80b JK |
2723 | switch (len) { |
2724 | case 1: | |
f25a49e0 PM |
2725 | *data = ldub_p(buf); |
2726 | return MEMTX_OK; | |
acc9d80b | 2727 | case 2: |
f25a49e0 PM |
2728 | *data = lduw_p(buf); |
2729 | return MEMTX_OK; | |
acc9d80b | 2730 | case 4: |
f25a49e0 PM |
2731 | *data = ldl_p(buf); |
2732 | return MEMTX_OK; | |
ff6cff75 | 2733 | case 8: |
f25a49e0 PM |
2734 | *data = ldq_p(buf); |
2735 | return MEMTX_OK; | |
acc9d80b JK |
2736 | default: |
2737 | abort(); | |
2738 | } | |
db7b5426 BS |
2739 | } |
2740 | ||
f25a49e0 PM |
2741 | static MemTxResult subpage_write(void *opaque, hwaddr addr, |
2742 | uint64_t value, unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2743 | { |
acc9d80b | 2744 | subpage_t *subpage = opaque; |
ff6cff75 | 2745 | uint8_t buf[8]; |
acc9d80b | 2746 | |
db7b5426 | 2747 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2748 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx |
acc9d80b JK |
2749 | " value %"PRIx64"\n", |
2750 | __func__, subpage, len, addr, value); | |
db7b5426 | 2751 | #endif |
acc9d80b JK |
2752 | switch (len) { |
2753 | case 1: | |
2754 | stb_p(buf, value); | |
2755 | break; | |
2756 | case 2: | |
2757 | stw_p(buf, value); | |
2758 | break; | |
2759 | case 4: | |
2760 | stl_p(buf, value); | |
2761 | break; | |
ff6cff75 PB |
2762 | case 8: |
2763 | stq_p(buf, value); | |
2764 | break; | |
acc9d80b JK |
2765 | default: |
2766 | abort(); | |
2767 | } | |
16620684 | 2768 | return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); |
db7b5426 BS |
2769 | } |
2770 | ||
c353e4cc | 2771 | static bool subpage_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
2772 | unsigned len, bool is_write, |
2773 | MemTxAttrs attrs) | |
c353e4cc | 2774 | { |
acc9d80b | 2775 | subpage_t *subpage = opaque; |
c353e4cc | 2776 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2777 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", |
acc9d80b | 2778 | __func__, subpage, is_write ? 'w' : 'r', len, addr); |
c353e4cc PB |
2779 | #endif |
2780 | ||
16620684 | 2781 | return flatview_access_valid(subpage->fv, addr + subpage->base, |
eace72b7 | 2782 | len, is_write, attrs); |
c353e4cc PB |
2783 | } |
2784 | ||
70c68e44 | 2785 | static const MemoryRegionOps subpage_ops = { |
f25a49e0 PM |
2786 | .read_with_attrs = subpage_read, |
2787 | .write_with_attrs = subpage_write, | |
ff6cff75 PB |
2788 | .impl.min_access_size = 1, |
2789 | .impl.max_access_size = 8, | |
2790 | .valid.min_access_size = 1, | |
2791 | .valid.max_access_size = 8, | |
c353e4cc | 2792 | .valid.accepts = subpage_accepts, |
70c68e44 | 2793 | .endianness = DEVICE_NATIVE_ENDIAN, |
db7b5426 BS |
2794 | }; |
2795 | ||
c227f099 | 2796 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 2797 | uint16_t section) |
db7b5426 BS |
2798 | { |
2799 | int idx, eidx; | |
2800 | ||
2801 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2802 | return -1; | |
2803 | idx = SUBPAGE_IDX(start); | |
2804 | eidx = SUBPAGE_IDX(end); | |
2805 | #if defined(DEBUG_SUBPAGE) | |
016e9d62 AK |
2806 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", |
2807 | __func__, mmio, start, end, idx, eidx, section); | |
db7b5426 | 2808 | #endif |
db7b5426 | 2809 | for (; idx <= eidx; idx++) { |
5312bd8b | 2810 | mmio->sub_section[idx] = section; |
db7b5426 BS |
2811 | } |
2812 | ||
2813 | return 0; | |
2814 | } | |
2815 | ||
16620684 | 2816 | static subpage_t *subpage_init(FlatView *fv, hwaddr base) |
db7b5426 | 2817 | { |
c227f099 | 2818 | subpage_t *mmio; |
db7b5426 | 2819 | |
2615fabd | 2820 | mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t)); |
16620684 | 2821 | mmio->fv = fv; |
1eec614b | 2822 | mmio->base = base; |
2c9b15ca | 2823 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
b4fefef9 | 2824 | NULL, TARGET_PAGE_SIZE); |
b3b00c78 | 2825 | mmio->iomem.subpage = true; |
db7b5426 | 2826 | #if defined(DEBUG_SUBPAGE) |
016e9d62 AK |
2827 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, |
2828 | mmio, base, TARGET_PAGE_SIZE); | |
db7b5426 | 2829 | #endif |
b41aac4f | 2830 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); |
db7b5426 BS |
2831 | |
2832 | return mmio; | |
2833 | } | |
2834 | ||
16620684 | 2835 | static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) |
5312bd8b | 2836 | { |
16620684 | 2837 | assert(fv); |
5312bd8b | 2838 | MemoryRegionSection section = { |
16620684 | 2839 | .fv = fv, |
5312bd8b AK |
2840 | .mr = mr, |
2841 | .offset_within_address_space = 0, | |
2842 | .offset_within_region = 0, | |
052e87b0 | 2843 | .size = int128_2_64(), |
5312bd8b AK |
2844 | }; |
2845 | ||
53cb28cb | 2846 | return phys_section_add(map, §ion); |
5312bd8b AK |
2847 | } |
2848 | ||
8af36743 PM |
2849 | static void readonly_mem_write(void *opaque, hwaddr addr, |
2850 | uint64_t val, unsigned size) | |
2851 | { | |
2852 | /* Ignore any write to ROM. */ | |
2853 | } | |
2854 | ||
2855 | static bool readonly_mem_accepts(void *opaque, hwaddr addr, | |
8372d383 PM |
2856 | unsigned size, bool is_write, |
2857 | MemTxAttrs attrs) | |
8af36743 PM |
2858 | { |
2859 | return is_write; | |
2860 | } | |
2861 | ||
2862 | /* This will only be used for writes, because reads are special cased | |
2863 | * to directly access the underlying host ram. | |
2864 | */ | |
2865 | static const MemoryRegionOps readonly_mem_ops = { | |
2866 | .write = readonly_mem_write, | |
2867 | .valid.accepts = readonly_mem_accepts, | |
2868 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2869 | .valid = { | |
2870 | .min_access_size = 1, | |
2871 | .max_access_size = 8, | |
2872 | .unaligned = false, | |
2873 | }, | |
2874 | .impl = { | |
2875 | .min_access_size = 1, | |
2876 | .max_access_size = 8, | |
2877 | .unaligned = false, | |
2878 | }, | |
2879 | }; | |
2880 | ||
a54c87b6 | 2881 | MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs) |
aa102231 | 2882 | { |
a54c87b6 PM |
2883 | int asidx = cpu_asidx_from_attrs(cpu, attrs); |
2884 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | |
32857f4d | 2885 | AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch); |
79e2b9ae | 2886 | MemoryRegionSection *sections = d->map.sections; |
9d82b5a7 PB |
2887 | |
2888 | return sections[index & ~TARGET_PAGE_MASK].mr; | |
aa102231 AK |
2889 | } |
2890 | ||
e9179ce1 AK |
2891 | static void io_mem_init(void) |
2892 | { | |
8af36743 PM |
2893 | memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops, |
2894 | NULL, NULL, UINT64_MAX); | |
2c9b15ca | 2895 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, |
1f6245e5 | 2896 | NULL, UINT64_MAX); |
8d04fb55 JK |
2897 | |
2898 | /* io_mem_notdirty calls tb_invalidate_phys_page_fast, | |
2899 | * which can be called without the iothread mutex. | |
2900 | */ | |
2c9b15ca | 2901 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, |
1f6245e5 | 2902 | NULL, UINT64_MAX); |
8d04fb55 JK |
2903 | memory_region_clear_global_locking(&io_mem_notdirty); |
2904 | ||
2c9b15ca | 2905 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, |
1f6245e5 | 2906 | NULL, UINT64_MAX); |
e9179ce1 AK |
2907 | } |
2908 | ||
8629d3fc | 2909 | AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) |
00752703 | 2910 | { |
53cb28cb MA |
2911 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); |
2912 | uint16_t n; | |
2913 | ||
16620684 | 2914 | n = dummy_section(&d->map, fv, &io_mem_unassigned); |
53cb28cb | 2915 | assert(n == PHYS_SECTION_UNASSIGNED); |
16620684 | 2916 | n = dummy_section(&d->map, fv, &io_mem_notdirty); |
53cb28cb | 2917 | assert(n == PHYS_SECTION_NOTDIRTY); |
16620684 | 2918 | n = dummy_section(&d->map, fv, &io_mem_rom); |
53cb28cb | 2919 | assert(n == PHYS_SECTION_ROM); |
16620684 | 2920 | n = dummy_section(&d->map, fv, &io_mem_watch); |
53cb28cb | 2921 | assert(n == PHYS_SECTION_WATCH); |
00752703 | 2922 | |
9736e55b | 2923 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; |
66a6df1d AK |
2924 | |
2925 | return d; | |
00752703 PB |
2926 | } |
2927 | ||
66a6df1d | 2928 | void address_space_dispatch_free(AddressSpaceDispatch *d) |
79e2b9ae PB |
2929 | { |
2930 | phys_sections_free(&d->map); | |
2931 | g_free(d); | |
2932 | } | |
2933 | ||
1d71148e | 2934 | static void tcg_commit(MemoryListener *listener) |
50c1e149 | 2935 | { |
32857f4d PM |
2936 | CPUAddressSpace *cpuas; |
2937 | AddressSpaceDispatch *d; | |
117712c3 AK |
2938 | |
2939 | /* since each CPU stores ram addresses in its TLB cache, we must | |
2940 | reset the modified entries */ | |
32857f4d PM |
2941 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); |
2942 | cpu_reloading_memory_map(); | |
2943 | /* The CPU and TLB are protected by the iothread lock. | |
2944 | * We reload the dispatch pointer now because cpu_reloading_memory_map() | |
2945 | * may have split the RCU critical section. | |
2946 | */ | |
66a6df1d | 2947 | d = address_space_to_dispatch(cpuas->as); |
f35e44e7 | 2948 | atomic_rcu_set(&cpuas->memory_dispatch, d); |
d10eb08f | 2949 | tlb_flush(cpuas->cpu); |
50c1e149 AK |
2950 | } |
2951 | ||
62152b8a AK |
2952 | static void memory_map_init(void) |
2953 | { | |
7267c094 | 2954 | system_memory = g_malloc(sizeof(*system_memory)); |
03f49957 | 2955 | |
57271d63 | 2956 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
7dca8043 | 2957 | address_space_init(&address_space_memory, system_memory, "memory"); |
309cb471 | 2958 | |
7267c094 | 2959 | system_io = g_malloc(sizeof(*system_io)); |
3bb28b72 JK |
2960 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
2961 | 65536); | |
7dca8043 | 2962 | address_space_init(&address_space_io, system_io, "I/O"); |
62152b8a AK |
2963 | } |
2964 | ||
2965 | MemoryRegion *get_system_memory(void) | |
2966 | { | |
2967 | return system_memory; | |
2968 | } | |
2969 | ||
309cb471 AK |
2970 | MemoryRegion *get_system_io(void) |
2971 | { | |
2972 | return system_io; | |
2973 | } | |
2974 | ||
e2eef170 PB |
2975 | #endif /* !defined(CONFIG_USER_ONLY) */ |
2976 | ||
13eb76e0 FB |
2977 | /* physical memory access (slow version, mainly for debug) */ |
2978 | #if defined(CONFIG_USER_ONLY) | |
f17ec444 | 2979 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
a68fe89c | 2980 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
2981 | { |
2982 | int l, flags; | |
2983 | target_ulong page; | |
53a5960a | 2984 | void * p; |
13eb76e0 FB |
2985 | |
2986 | while (len > 0) { | |
2987 | page = addr & TARGET_PAGE_MASK; | |
2988 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2989 | if (l > len) | |
2990 | l = len; | |
2991 | flags = page_get_flags(page); | |
2992 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 2993 | return -1; |
13eb76e0 FB |
2994 | if (is_write) { |
2995 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 2996 | return -1; |
579a97f7 | 2997 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2998 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 2999 | return -1; |
72fb7daa AJ |
3000 | memcpy(p, buf, l); |
3001 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3002 | } else { |
3003 | if (!(flags & PAGE_READ)) | |
a68fe89c | 3004 | return -1; |
579a97f7 | 3005 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3006 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 3007 | return -1; |
72fb7daa | 3008 | memcpy(buf, p, l); |
5b257578 | 3009 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3010 | } |
3011 | len -= l; | |
3012 | buf += l; | |
3013 | addr += l; | |
3014 | } | |
a68fe89c | 3015 | return 0; |
13eb76e0 | 3016 | } |
8df1cd07 | 3017 | |
13eb76e0 | 3018 | #else |
51d7a9eb | 3019 | |
845b6214 | 3020 | static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, |
a8170e5e | 3021 | hwaddr length) |
51d7a9eb | 3022 | { |
e87f7778 | 3023 | uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
0878d0e1 PB |
3024 | addr += memory_region_get_ram_addr(mr); |
3025 | ||
e87f7778 PB |
3026 | /* No early return if dirty_log_mask is or becomes 0, because |
3027 | * cpu_physical_memory_set_dirty_range will still call | |
3028 | * xen_modified_memory. | |
3029 | */ | |
3030 | if (dirty_log_mask) { | |
3031 | dirty_log_mask = | |
3032 | cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); | |
3033 | } | |
3034 | if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { | |
5aa1ef71 | 3035 | assert(tcg_enabled()); |
ba051fb5 | 3036 | tb_lock(); |
e87f7778 | 3037 | tb_invalidate_phys_range(addr, addr + length); |
ba051fb5 | 3038 | tb_unlock(); |
e87f7778 | 3039 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); |
51d7a9eb | 3040 | } |
e87f7778 | 3041 | cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); |
51d7a9eb AP |
3042 | } |
3043 | ||
23326164 | 3044 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
82f2563f | 3045 | { |
e1622f4b | 3046 | unsigned access_size_max = mr->ops->valid.max_access_size; |
23326164 RH |
3047 | |
3048 | /* Regions are assumed to support 1-4 byte accesses unless | |
3049 | otherwise specified. */ | |
23326164 RH |
3050 | if (access_size_max == 0) { |
3051 | access_size_max = 4; | |
3052 | } | |
3053 | ||
3054 | /* Bound the maximum access by the alignment of the address. */ | |
3055 | if (!mr->ops->impl.unaligned) { | |
3056 | unsigned align_size_max = addr & -addr; | |
3057 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
3058 | access_size_max = align_size_max; | |
3059 | } | |
82f2563f | 3060 | } |
23326164 RH |
3061 | |
3062 | /* Don't attempt accesses larger than the maximum. */ | |
3063 | if (l > access_size_max) { | |
3064 | l = access_size_max; | |
82f2563f | 3065 | } |
6554f5c0 | 3066 | l = pow2floor(l); |
23326164 RH |
3067 | |
3068 | return l; | |
82f2563f PB |
3069 | } |
3070 | ||
4840f10e | 3071 | static bool prepare_mmio_access(MemoryRegion *mr) |
125b3806 | 3072 | { |
4840f10e JK |
3073 | bool unlocked = !qemu_mutex_iothread_locked(); |
3074 | bool release_lock = false; | |
3075 | ||
3076 | if (unlocked && mr->global_locking) { | |
3077 | qemu_mutex_lock_iothread(); | |
3078 | unlocked = false; | |
3079 | release_lock = true; | |
3080 | } | |
125b3806 | 3081 | if (mr->flush_coalesced_mmio) { |
4840f10e JK |
3082 | if (unlocked) { |
3083 | qemu_mutex_lock_iothread(); | |
3084 | } | |
125b3806 | 3085 | qemu_flush_coalesced_mmio_buffer(); |
4840f10e JK |
3086 | if (unlocked) { |
3087 | qemu_mutex_unlock_iothread(); | |
3088 | } | |
125b3806 | 3089 | } |
4840f10e JK |
3090 | |
3091 | return release_lock; | |
125b3806 PB |
3092 | } |
3093 | ||
a203ac70 | 3094 | /* Called within RCU critical section. */ |
16620684 AK |
3095 | static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, |
3096 | MemTxAttrs attrs, | |
3097 | const uint8_t *buf, | |
3098 | int len, hwaddr addr1, | |
3099 | hwaddr l, MemoryRegion *mr) | |
13eb76e0 | 3100 | { |
13eb76e0 | 3101 | uint8_t *ptr; |
791af8c8 | 3102 | uint64_t val; |
3b643495 | 3103 | MemTxResult result = MEMTX_OK; |
4840f10e | 3104 | bool release_lock = false; |
3b46e624 | 3105 | |
a203ac70 | 3106 | for (;;) { |
eb7eeb88 PB |
3107 | if (!memory_access_is_direct(mr, true)) { |
3108 | release_lock |= prepare_mmio_access(mr); | |
3109 | l = memory_access_size(mr, l, addr1); | |
3110 | /* XXX: could force current_cpu to NULL to avoid | |
3111 | potential bugs */ | |
3112 | switch (l) { | |
3113 | case 8: | |
3114 | /* 64 bit write access */ | |
3115 | val = ldq_p(buf); | |
3116 | result |= memory_region_dispatch_write(mr, addr1, val, 8, | |
3117 | attrs); | |
3118 | break; | |
3119 | case 4: | |
3120 | /* 32 bit write access */ | |
6da67de6 | 3121 | val = (uint32_t)ldl_p(buf); |
eb7eeb88 PB |
3122 | result |= memory_region_dispatch_write(mr, addr1, val, 4, |
3123 | attrs); | |
3124 | break; | |
3125 | case 2: | |
3126 | /* 16 bit write access */ | |
3127 | val = lduw_p(buf); | |
3128 | result |= memory_region_dispatch_write(mr, addr1, val, 2, | |
3129 | attrs); | |
3130 | break; | |
3131 | case 1: | |
3132 | /* 8 bit write access */ | |
3133 | val = ldub_p(buf); | |
3134 | result |= memory_region_dispatch_write(mr, addr1, val, 1, | |
3135 | attrs); | |
3136 | break; | |
3137 | default: | |
3138 | abort(); | |
13eb76e0 FB |
3139 | } |
3140 | } else { | |
eb7eeb88 | 3141 | /* RAM case */ |
f5aa69bd | 3142 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
eb7eeb88 PB |
3143 | memcpy(ptr, buf, l); |
3144 | invalidate_and_set_dirty(mr, addr1, l); | |
13eb76e0 | 3145 | } |
4840f10e JK |
3146 | |
3147 | if (release_lock) { | |
3148 | qemu_mutex_unlock_iothread(); | |
3149 | release_lock = false; | |
3150 | } | |
3151 | ||
13eb76e0 FB |
3152 | len -= l; |
3153 | buf += l; | |
3154 | addr += l; | |
a203ac70 PB |
3155 | |
3156 | if (!len) { | |
3157 | break; | |
3158 | } | |
3159 | ||
3160 | l = len; | |
efa99a2f | 3161 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); |
13eb76e0 | 3162 | } |
fd8aaa76 | 3163 | |
3b643495 | 3164 | return result; |
13eb76e0 | 3165 | } |
8df1cd07 | 3166 | |
4c6ebbb3 | 3167 | /* Called from RCU critical section. */ |
16620684 AK |
3168 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
3169 | const uint8_t *buf, int len) | |
ac1970fb | 3170 | { |
eb7eeb88 | 3171 | hwaddr l; |
eb7eeb88 PB |
3172 | hwaddr addr1; |
3173 | MemoryRegion *mr; | |
3174 | MemTxResult result = MEMTX_OK; | |
eb7eeb88 | 3175 | |
4c6ebbb3 | 3176 | l = len; |
efa99a2f | 3177 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); |
4c6ebbb3 PB |
3178 | result = flatview_write_continue(fv, addr, attrs, buf, len, |
3179 | addr1, l, mr); | |
a203ac70 PB |
3180 | |
3181 | return result; | |
3182 | } | |
3183 | ||
3184 | /* Called within RCU critical section. */ | |
16620684 AK |
3185 | MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, |
3186 | MemTxAttrs attrs, uint8_t *buf, | |
3187 | int len, hwaddr addr1, hwaddr l, | |
3188 | MemoryRegion *mr) | |
a203ac70 PB |
3189 | { |
3190 | uint8_t *ptr; | |
3191 | uint64_t val; | |
3192 | MemTxResult result = MEMTX_OK; | |
3193 | bool release_lock = false; | |
eb7eeb88 | 3194 | |
a203ac70 | 3195 | for (;;) { |
eb7eeb88 PB |
3196 | if (!memory_access_is_direct(mr, false)) { |
3197 | /* I/O case */ | |
3198 | release_lock |= prepare_mmio_access(mr); | |
3199 | l = memory_access_size(mr, l, addr1); | |
3200 | switch (l) { | |
3201 | case 8: | |
3202 | /* 64 bit read access */ | |
3203 | result |= memory_region_dispatch_read(mr, addr1, &val, 8, | |
3204 | attrs); | |
3205 | stq_p(buf, val); | |
3206 | break; | |
3207 | case 4: | |
3208 | /* 32 bit read access */ | |
3209 | result |= memory_region_dispatch_read(mr, addr1, &val, 4, | |
3210 | attrs); | |
3211 | stl_p(buf, val); | |
3212 | break; | |
3213 | case 2: | |
3214 | /* 16 bit read access */ | |
3215 | result |= memory_region_dispatch_read(mr, addr1, &val, 2, | |
3216 | attrs); | |
3217 | stw_p(buf, val); | |
3218 | break; | |
3219 | case 1: | |
3220 | /* 8 bit read access */ | |
3221 | result |= memory_region_dispatch_read(mr, addr1, &val, 1, | |
3222 | attrs); | |
3223 | stb_p(buf, val); | |
3224 | break; | |
3225 | default: | |
3226 | abort(); | |
3227 | } | |
3228 | } else { | |
3229 | /* RAM case */ | |
f5aa69bd | 3230 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
eb7eeb88 PB |
3231 | memcpy(buf, ptr, l); |
3232 | } | |
3233 | ||
3234 | if (release_lock) { | |
3235 | qemu_mutex_unlock_iothread(); | |
3236 | release_lock = false; | |
3237 | } | |
3238 | ||
3239 | len -= l; | |
3240 | buf += l; | |
3241 | addr += l; | |
a203ac70 PB |
3242 | |
3243 | if (!len) { | |
3244 | break; | |
3245 | } | |
3246 | ||
3247 | l = len; | |
efa99a2f | 3248 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); |
a203ac70 PB |
3249 | } |
3250 | ||
3251 | return result; | |
3252 | } | |
3253 | ||
b2a44fca PB |
3254 | /* Called from RCU critical section. */ |
3255 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, | |
3256 | MemTxAttrs attrs, uint8_t *buf, int len) | |
a203ac70 PB |
3257 | { |
3258 | hwaddr l; | |
3259 | hwaddr addr1; | |
3260 | MemoryRegion *mr; | |
eb7eeb88 | 3261 | |
b2a44fca | 3262 | l = len; |
efa99a2f | 3263 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); |
b2a44fca PB |
3264 | return flatview_read_continue(fv, addr, attrs, buf, len, |
3265 | addr1, l, mr); | |
ac1970fb AK |
3266 | } |
3267 | ||
b2a44fca PB |
3268 | MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, |
3269 | MemTxAttrs attrs, uint8_t *buf, int len) | |
3270 | { | |
3271 | MemTxResult result = MEMTX_OK; | |
3272 | FlatView *fv; | |
3273 | ||
3274 | if (len > 0) { | |
3275 | rcu_read_lock(); | |
3276 | fv = address_space_to_flatview(as); | |
3277 | result = flatview_read(fv, addr, attrs, buf, len); | |
3278 | rcu_read_unlock(); | |
3279 | } | |
3280 | ||
3281 | return result; | |
3282 | } | |
3283 | ||
4c6ebbb3 PB |
3284 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, |
3285 | MemTxAttrs attrs, | |
3286 | const uint8_t *buf, int len) | |
3287 | { | |
3288 | MemTxResult result = MEMTX_OK; | |
3289 | FlatView *fv; | |
3290 | ||
3291 | if (len > 0) { | |
3292 | rcu_read_lock(); | |
3293 | fv = address_space_to_flatview(as); | |
3294 | result = flatview_write(fv, addr, attrs, buf, len); | |
3295 | rcu_read_unlock(); | |
3296 | } | |
3297 | ||
3298 | return result; | |
3299 | } | |
3300 | ||
db84fd97 PB |
3301 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, |
3302 | uint8_t *buf, int len, bool is_write) | |
3303 | { | |
3304 | if (is_write) { | |
3305 | return address_space_write(as, addr, attrs, buf, len); | |
3306 | } else { | |
3307 | return address_space_read_full(as, addr, attrs, buf, len); | |
3308 | } | |
3309 | } | |
3310 | ||
a8170e5e | 3311 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
ac1970fb AK |
3312 | int len, int is_write) |
3313 | { | |
5c9eb028 PM |
3314 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, |
3315 | buf, len, is_write); | |
ac1970fb AK |
3316 | } |
3317 | ||
582b55a9 AG |
3318 | enum write_rom_type { |
3319 | WRITE_DATA, | |
3320 | FLUSH_CACHE, | |
3321 | }; | |
3322 | ||
2a221651 | 3323 | static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, |
582b55a9 | 3324 | hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) |
d0ecd2aa | 3325 | { |
149f54b5 | 3326 | hwaddr l; |
d0ecd2aa | 3327 | uint8_t *ptr; |
149f54b5 | 3328 | hwaddr addr1; |
5c8a00ce | 3329 | MemoryRegion *mr; |
3b46e624 | 3330 | |
41063e1e | 3331 | rcu_read_lock(); |
d0ecd2aa | 3332 | while (len > 0) { |
149f54b5 | 3333 | l = len; |
bc6b1cec PM |
3334 | mr = address_space_translate(as, addr, &addr1, &l, true, |
3335 | MEMTXATTRS_UNSPECIFIED); | |
3b46e624 | 3336 | |
5c8a00ce PB |
3337 | if (!(memory_region_is_ram(mr) || |
3338 | memory_region_is_romd(mr))) { | |
b242e0e0 | 3339 | l = memory_access_size(mr, l, addr1); |
d0ecd2aa | 3340 | } else { |
d0ecd2aa | 3341 | /* ROM/RAM case */ |
0878d0e1 | 3342 | ptr = qemu_map_ram_ptr(mr->ram_block, addr1); |
582b55a9 AG |
3343 | switch (type) { |
3344 | case WRITE_DATA: | |
3345 | memcpy(ptr, buf, l); | |
845b6214 | 3346 | invalidate_and_set_dirty(mr, addr1, l); |
582b55a9 AG |
3347 | break; |
3348 | case FLUSH_CACHE: | |
3349 | flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); | |
3350 | break; | |
3351 | } | |
d0ecd2aa FB |
3352 | } |
3353 | len -= l; | |
3354 | buf += l; | |
3355 | addr += l; | |
3356 | } | |
41063e1e | 3357 | rcu_read_unlock(); |
d0ecd2aa FB |
3358 | } |
3359 | ||
582b55a9 | 3360 | /* used for ROM loading : can write in RAM and ROM */ |
2a221651 | 3361 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, |
582b55a9 AG |
3362 | const uint8_t *buf, int len) |
3363 | { | |
2a221651 | 3364 | cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA); |
582b55a9 AG |
3365 | } |
3366 | ||
3367 | void cpu_flush_icache_range(hwaddr start, int len) | |
3368 | { | |
3369 | /* | |
3370 | * This function should do the same thing as an icache flush that was | |
3371 | * triggered from within the guest. For TCG we are always cache coherent, | |
3372 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
3373 | * the host's instruction cache at least. | |
3374 | */ | |
3375 | if (tcg_enabled()) { | |
3376 | return; | |
3377 | } | |
3378 | ||
2a221651 EI |
3379 | cpu_physical_memory_write_rom_internal(&address_space_memory, |
3380 | start, NULL, len, FLUSH_CACHE); | |
582b55a9 AG |
3381 | } |
3382 | ||
6d16c2f8 | 3383 | typedef struct { |
d3e71559 | 3384 | MemoryRegion *mr; |
6d16c2f8 | 3385 | void *buffer; |
a8170e5e AK |
3386 | hwaddr addr; |
3387 | hwaddr len; | |
c2cba0ff | 3388 | bool in_use; |
6d16c2f8 AL |
3389 | } BounceBuffer; |
3390 | ||
3391 | static BounceBuffer bounce; | |
3392 | ||
ba223c29 | 3393 | typedef struct MapClient { |
e95205e1 | 3394 | QEMUBH *bh; |
72cf2d4f | 3395 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3396 | } MapClient; |
3397 | ||
38e047b5 | 3398 | QemuMutex map_client_list_lock; |
72cf2d4f BS |
3399 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3400 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 | 3401 | |
e95205e1 FZ |
3402 | static void cpu_unregister_map_client_do(MapClient *client) |
3403 | { | |
3404 | QLIST_REMOVE(client, link); | |
3405 | g_free(client); | |
3406 | } | |
3407 | ||
33b6c2ed FZ |
3408 | static void cpu_notify_map_clients_locked(void) |
3409 | { | |
3410 | MapClient *client; | |
3411 | ||
3412 | while (!QLIST_EMPTY(&map_client_list)) { | |
3413 | client = QLIST_FIRST(&map_client_list); | |
e95205e1 FZ |
3414 | qemu_bh_schedule(client->bh); |
3415 | cpu_unregister_map_client_do(client); | |
33b6c2ed FZ |
3416 | } |
3417 | } | |
3418 | ||
e95205e1 | 3419 | void cpu_register_map_client(QEMUBH *bh) |
ba223c29 | 3420 | { |
7267c094 | 3421 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 | 3422 | |
38e047b5 | 3423 | qemu_mutex_lock(&map_client_list_lock); |
e95205e1 | 3424 | client->bh = bh; |
72cf2d4f | 3425 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
33b6c2ed FZ |
3426 | if (!atomic_read(&bounce.in_use)) { |
3427 | cpu_notify_map_clients_locked(); | |
3428 | } | |
38e047b5 | 3429 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3430 | } |
3431 | ||
38e047b5 | 3432 | void cpu_exec_init_all(void) |
ba223c29 | 3433 | { |
38e047b5 | 3434 | qemu_mutex_init(&ram_list.mutex); |
20bccb82 PM |
3435 | /* The data structures we set up here depend on knowing the page size, |
3436 | * so no more changes can be made after this point. | |
3437 | * In an ideal world, nothing we did before we had finished the | |
3438 | * machine setup would care about the target page size, and we could | |
3439 | * do this much later, rather than requiring board models to state | |
3440 | * up front what their requirements are. | |
3441 | */ | |
3442 | finalize_target_page_bits(); | |
38e047b5 | 3443 | io_mem_init(); |
680a4783 | 3444 | memory_map_init(); |
38e047b5 | 3445 | qemu_mutex_init(&map_client_list_lock); |
ba223c29 AL |
3446 | } |
3447 | ||
e95205e1 | 3448 | void cpu_unregister_map_client(QEMUBH *bh) |
ba223c29 AL |
3449 | { |
3450 | MapClient *client; | |
3451 | ||
e95205e1 FZ |
3452 | qemu_mutex_lock(&map_client_list_lock); |
3453 | QLIST_FOREACH(client, &map_client_list, link) { | |
3454 | if (client->bh == bh) { | |
3455 | cpu_unregister_map_client_do(client); | |
3456 | break; | |
3457 | } | |
ba223c29 | 3458 | } |
e95205e1 | 3459 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3460 | } |
3461 | ||
3462 | static void cpu_notify_map_clients(void) | |
3463 | { | |
38e047b5 | 3464 | qemu_mutex_lock(&map_client_list_lock); |
33b6c2ed | 3465 | cpu_notify_map_clients_locked(); |
38e047b5 | 3466 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3467 | } |
3468 | ||
16620684 | 3469 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, |
eace72b7 | 3470 | bool is_write, MemTxAttrs attrs) |
51644ab7 | 3471 | { |
5c8a00ce | 3472 | MemoryRegion *mr; |
51644ab7 PB |
3473 | hwaddr l, xlat; |
3474 | ||
3475 | while (len > 0) { | |
3476 | l = len; | |
efa99a2f | 3477 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); |
5c8a00ce PB |
3478 | if (!memory_access_is_direct(mr, is_write)) { |
3479 | l = memory_access_size(mr, l, addr); | |
eace72b7 | 3480 | if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) { |
51644ab7 PB |
3481 | return false; |
3482 | } | |
3483 | } | |
3484 | ||
3485 | len -= l; | |
3486 | addr += l; | |
3487 | } | |
3488 | return true; | |
3489 | } | |
3490 | ||
16620684 | 3491 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, |
fddffa42 PM |
3492 | int len, bool is_write, |
3493 | MemTxAttrs attrs) | |
16620684 | 3494 | { |
11e732a5 PB |
3495 | FlatView *fv; |
3496 | bool result; | |
3497 | ||
3498 | rcu_read_lock(); | |
3499 | fv = address_space_to_flatview(as); | |
eace72b7 | 3500 | result = flatview_access_valid(fv, addr, len, is_write, attrs); |
11e732a5 PB |
3501 | rcu_read_unlock(); |
3502 | return result; | |
16620684 AK |
3503 | } |
3504 | ||
715c31ec | 3505 | static hwaddr |
16620684 | 3506 | flatview_extend_translation(FlatView *fv, hwaddr addr, |
53d0790d PM |
3507 | hwaddr target_len, |
3508 | MemoryRegion *mr, hwaddr base, hwaddr len, | |
3509 | bool is_write, MemTxAttrs attrs) | |
715c31ec PB |
3510 | { |
3511 | hwaddr done = 0; | |
3512 | hwaddr xlat; | |
3513 | MemoryRegion *this_mr; | |
3514 | ||
3515 | for (;;) { | |
3516 | target_len -= len; | |
3517 | addr += len; | |
3518 | done += len; | |
3519 | if (target_len == 0) { | |
3520 | return done; | |
3521 | } | |
3522 | ||
3523 | len = target_len; | |
16620684 | 3524 | this_mr = flatview_translate(fv, addr, &xlat, |
efa99a2f | 3525 | &len, is_write, attrs); |
715c31ec PB |
3526 | if (this_mr != mr || xlat != base + done) { |
3527 | return done; | |
3528 | } | |
3529 | } | |
3530 | } | |
3531 | ||
6d16c2f8 AL |
3532 | /* Map a physical memory region into a host virtual address. |
3533 | * May map a subset of the requested range, given by and returned in *plen. | |
3534 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3535 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3536 | * Use cpu_register_map_client() to know when retrying the map operation is |
3537 | * likely to succeed. | |
6d16c2f8 | 3538 | */ |
ac1970fb | 3539 | void *address_space_map(AddressSpace *as, |
a8170e5e AK |
3540 | hwaddr addr, |
3541 | hwaddr *plen, | |
f26404fb PM |
3542 | bool is_write, |
3543 | MemTxAttrs attrs) | |
6d16c2f8 | 3544 | { |
a8170e5e | 3545 | hwaddr len = *plen; |
715c31ec PB |
3546 | hwaddr l, xlat; |
3547 | MemoryRegion *mr; | |
e81bcda5 | 3548 | void *ptr; |
ad0c60fa | 3549 | FlatView *fv; |
6d16c2f8 | 3550 | |
e3127ae0 PB |
3551 | if (len == 0) { |
3552 | return NULL; | |
3553 | } | |
38bee5dc | 3554 | |
e3127ae0 | 3555 | l = len; |
41063e1e | 3556 | rcu_read_lock(); |
ad0c60fa | 3557 | fv = address_space_to_flatview(as); |
efa99a2f | 3558 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); |
41063e1e | 3559 | |
e3127ae0 | 3560 | if (!memory_access_is_direct(mr, is_write)) { |
c2cba0ff | 3561 | if (atomic_xchg(&bounce.in_use, true)) { |
41063e1e | 3562 | rcu_read_unlock(); |
e3127ae0 | 3563 | return NULL; |
6d16c2f8 | 3564 | } |
e85d9db5 KW |
3565 | /* Avoid unbounded allocations */ |
3566 | l = MIN(l, TARGET_PAGE_SIZE); | |
3567 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
e3127ae0 PB |
3568 | bounce.addr = addr; |
3569 | bounce.len = l; | |
d3e71559 PB |
3570 | |
3571 | memory_region_ref(mr); | |
3572 | bounce.mr = mr; | |
e3127ae0 | 3573 | if (!is_write) { |
16620684 | 3574 | flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED, |
5c9eb028 | 3575 | bounce.buffer, l); |
8ab934f9 | 3576 | } |
6d16c2f8 | 3577 | |
41063e1e | 3578 | rcu_read_unlock(); |
e3127ae0 PB |
3579 | *plen = l; |
3580 | return bounce.buffer; | |
3581 | } | |
3582 | ||
e3127ae0 | 3583 | |
d3e71559 | 3584 | memory_region_ref(mr); |
16620684 | 3585 | *plen = flatview_extend_translation(fv, addr, len, mr, xlat, |
53d0790d | 3586 | l, is_write, attrs); |
f5aa69bd | 3587 | ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); |
e81bcda5 PB |
3588 | rcu_read_unlock(); |
3589 | ||
3590 | return ptr; | |
6d16c2f8 AL |
3591 | } |
3592 | ||
ac1970fb | 3593 | /* Unmaps a memory region previously mapped by address_space_map(). |
6d16c2f8 AL |
3594 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
3595 | * the amount of memory that was actually read or written by the caller. | |
3596 | */ | |
a8170e5e AK |
3597 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
3598 | int is_write, hwaddr access_len) | |
6d16c2f8 AL |
3599 | { |
3600 | if (buffer != bounce.buffer) { | |
d3e71559 PB |
3601 | MemoryRegion *mr; |
3602 | ram_addr_t addr1; | |
3603 | ||
07bdaa41 | 3604 | mr = memory_region_from_host(buffer, &addr1); |
d3e71559 | 3605 | assert(mr != NULL); |
6d16c2f8 | 3606 | if (is_write) { |
845b6214 | 3607 | invalidate_and_set_dirty(mr, addr1, access_len); |
6d16c2f8 | 3608 | } |
868bb33f | 3609 | if (xen_enabled()) { |
e41d7c69 | 3610 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 3611 | } |
d3e71559 | 3612 | memory_region_unref(mr); |
6d16c2f8 AL |
3613 | return; |
3614 | } | |
3615 | if (is_write) { | |
5c9eb028 PM |
3616 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, |
3617 | bounce.buffer, access_len); | |
6d16c2f8 | 3618 | } |
f8a83245 | 3619 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3620 | bounce.buffer = NULL; |
d3e71559 | 3621 | memory_region_unref(bounce.mr); |
c2cba0ff | 3622 | atomic_mb_set(&bounce.in_use, false); |
ba223c29 | 3623 | cpu_notify_map_clients(); |
6d16c2f8 | 3624 | } |
d0ecd2aa | 3625 | |
a8170e5e AK |
3626 | void *cpu_physical_memory_map(hwaddr addr, |
3627 | hwaddr *plen, | |
ac1970fb AK |
3628 | int is_write) |
3629 | { | |
f26404fb PM |
3630 | return address_space_map(&address_space_memory, addr, plen, is_write, |
3631 | MEMTXATTRS_UNSPECIFIED); | |
ac1970fb AK |
3632 | } |
3633 | ||
a8170e5e AK |
3634 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
3635 | int is_write, hwaddr access_len) | |
ac1970fb AK |
3636 | { |
3637 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
3638 | } | |
3639 | ||
0ce265ff PB |
3640 | #define ARG1_DECL AddressSpace *as |
3641 | #define ARG1 as | |
3642 | #define SUFFIX | |
3643 | #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) | |
3644 | #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write) | |
3645 | #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs) | |
3646 | #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len) | |
3647 | #define RCU_READ_LOCK(...) rcu_read_lock() | |
3648 | #define RCU_READ_UNLOCK(...) rcu_read_unlock() | |
3649 | #include "memory_ldst.inc.c" | |
1e78bcc1 | 3650 | |
1f4e496e PB |
3651 | int64_t address_space_cache_init(MemoryRegionCache *cache, |
3652 | AddressSpace *as, | |
3653 | hwaddr addr, | |
3654 | hwaddr len, | |
3655 | bool is_write) | |
3656 | { | |
48564041 PB |
3657 | AddressSpaceDispatch *d; |
3658 | hwaddr l; | |
3659 | MemoryRegion *mr; | |
3660 | ||
3661 | assert(len > 0); | |
3662 | ||
3663 | l = len; | |
3664 | cache->fv = address_space_get_flatview(as); | |
3665 | d = flatview_to_dispatch(cache->fv); | |
3666 | cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true); | |
3667 | ||
3668 | mr = cache->mrs.mr; | |
3669 | memory_region_ref(mr); | |
3670 | if (memory_access_is_direct(mr, is_write)) { | |
53d0790d PM |
3671 | /* We don't care about the memory attributes here as we're only |
3672 | * doing this if we found actual RAM, which behaves the same | |
3673 | * regardless of attributes; so UNSPECIFIED is fine. | |
3674 | */ | |
48564041 | 3675 | l = flatview_extend_translation(cache->fv, addr, len, mr, |
53d0790d PM |
3676 | cache->xlat, l, is_write, |
3677 | MEMTXATTRS_UNSPECIFIED); | |
48564041 PB |
3678 | cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true); |
3679 | } else { | |
3680 | cache->ptr = NULL; | |
3681 | } | |
3682 | ||
3683 | cache->len = l; | |
3684 | cache->is_write = is_write; | |
3685 | return l; | |
1f4e496e PB |
3686 | } |
3687 | ||
3688 | void address_space_cache_invalidate(MemoryRegionCache *cache, | |
3689 | hwaddr addr, | |
3690 | hwaddr access_len) | |
3691 | { | |
48564041 PB |
3692 | assert(cache->is_write); |
3693 | if (likely(cache->ptr)) { | |
3694 | invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len); | |
3695 | } | |
1f4e496e PB |
3696 | } |
3697 | ||
3698 | void address_space_cache_destroy(MemoryRegionCache *cache) | |
3699 | { | |
48564041 PB |
3700 | if (!cache->mrs.mr) { |
3701 | return; | |
3702 | } | |
3703 | ||
3704 | if (xen_enabled()) { | |
3705 | xen_invalidate_map_cache_entry(cache->ptr); | |
3706 | } | |
3707 | memory_region_unref(cache->mrs.mr); | |
3708 | flatview_unref(cache->fv); | |
3709 | cache->mrs.mr = NULL; | |
3710 | cache->fv = NULL; | |
3711 | } | |
3712 | ||
3713 | /* Called from RCU critical section. This function has the same | |
3714 | * semantics as address_space_translate, but it only works on a | |
3715 | * predefined range of a MemoryRegion that was mapped with | |
3716 | * address_space_cache_init. | |
3717 | */ | |
3718 | static inline MemoryRegion *address_space_translate_cached( | |
3719 | MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat, | |
bc6b1cec | 3720 | hwaddr *plen, bool is_write, MemTxAttrs attrs) |
48564041 PB |
3721 | { |
3722 | MemoryRegionSection section; | |
3723 | MemoryRegion *mr; | |
3724 | IOMMUMemoryRegion *iommu_mr; | |
3725 | AddressSpace *target_as; | |
3726 | ||
3727 | assert(!cache->ptr); | |
3728 | *xlat = addr + cache->xlat; | |
3729 | ||
3730 | mr = cache->mrs.mr; | |
3731 | iommu_mr = memory_region_get_iommu(mr); | |
3732 | if (!iommu_mr) { | |
3733 | /* MMIO region. */ | |
3734 | return mr; | |
3735 | } | |
3736 | ||
3737 | section = address_space_translate_iommu(iommu_mr, xlat, plen, | |
3738 | NULL, is_write, true, | |
2f7b009c | 3739 | &target_as, attrs); |
48564041 PB |
3740 | return section.mr; |
3741 | } | |
3742 | ||
3743 | /* Called from RCU critical section. address_space_read_cached uses this | |
3744 | * out of line function when the target is an MMIO or IOMMU region. | |
3745 | */ | |
3746 | void | |
3747 | address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr, | |
3748 | void *buf, int len) | |
3749 | { | |
3750 | hwaddr addr1, l; | |
3751 | MemoryRegion *mr; | |
3752 | ||
3753 | l = len; | |
bc6b1cec PM |
3754 | mr = address_space_translate_cached(cache, addr, &addr1, &l, false, |
3755 | MEMTXATTRS_UNSPECIFIED); | |
48564041 PB |
3756 | flatview_read_continue(cache->fv, |
3757 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3758 | addr1, l, mr); | |
3759 | } | |
3760 | ||
3761 | /* Called from RCU critical section. address_space_write_cached uses this | |
3762 | * out of line function when the target is an MMIO or IOMMU region. | |
3763 | */ | |
3764 | void | |
3765 | address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, | |
3766 | const void *buf, int len) | |
3767 | { | |
3768 | hwaddr addr1, l; | |
3769 | MemoryRegion *mr; | |
3770 | ||
3771 | l = len; | |
bc6b1cec PM |
3772 | mr = address_space_translate_cached(cache, addr, &addr1, &l, true, |
3773 | MEMTXATTRS_UNSPECIFIED); | |
48564041 PB |
3774 | flatview_write_continue(cache->fv, |
3775 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3776 | addr1, l, mr); | |
1f4e496e PB |
3777 | } |
3778 | ||
3779 | #define ARG1_DECL MemoryRegionCache *cache | |
3780 | #define ARG1 cache | |
48564041 PB |
3781 | #define SUFFIX _cached_slow |
3782 | #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__) | |
3783 | #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write) | |
3784 | #define MAP_RAM(mr, ofs) (cache->ptr + (ofs - cache->xlat)) | |
90c4fe5f | 3785 | #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len) |
48564041 PB |
3786 | #define RCU_READ_LOCK() ((void)0) |
3787 | #define RCU_READ_UNLOCK() ((void)0) | |
1f4e496e PB |
3788 | #include "memory_ldst.inc.c" |
3789 | ||
5e2972fd | 3790 | /* virtual memory access for debug (includes writing to ROM) */ |
f17ec444 | 3791 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
b448f2f3 | 3792 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3793 | { |
3794 | int l; | |
a8170e5e | 3795 | hwaddr phys_addr; |
9b3c35e0 | 3796 | target_ulong page; |
13eb76e0 | 3797 | |
79ca7a1b | 3798 | cpu_synchronize_state(cpu); |
13eb76e0 | 3799 | while (len > 0) { |
5232e4c7 PM |
3800 | int asidx; |
3801 | MemTxAttrs attrs; | |
3802 | ||
13eb76e0 | 3803 | page = addr & TARGET_PAGE_MASK; |
5232e4c7 PM |
3804 | phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); |
3805 | asidx = cpu_asidx_from_attrs(cpu, attrs); | |
13eb76e0 FB |
3806 | /* if no physical page mapped, return an error */ |
3807 | if (phys_addr == -1) | |
3808 | return -1; | |
3809 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3810 | if (l > len) | |
3811 | l = len; | |
5e2972fd | 3812 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
2e38847b | 3813 | if (is_write) { |
5232e4c7 PM |
3814 | cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as, |
3815 | phys_addr, buf, l); | |
2e38847b | 3816 | } else { |
5232e4c7 PM |
3817 | address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, |
3818 | MEMTXATTRS_UNSPECIFIED, | |
5c9eb028 | 3819 | buf, l, 0); |
2e38847b | 3820 | } |
13eb76e0 FB |
3821 | len -= l; |
3822 | buf += l; | |
3823 | addr += l; | |
3824 | } | |
3825 | return 0; | |
3826 | } | |
038629a6 DDAG |
3827 | |
3828 | /* | |
3829 | * Allows code that needs to deal with migration bitmaps etc to still be built | |
3830 | * target independent. | |
3831 | */ | |
20afaed9 | 3832 | size_t qemu_target_page_size(void) |
038629a6 | 3833 | { |
20afaed9 | 3834 | return TARGET_PAGE_SIZE; |
038629a6 DDAG |
3835 | } |
3836 | ||
46d702b1 JQ |
3837 | int qemu_target_page_bits(void) |
3838 | { | |
3839 | return TARGET_PAGE_BITS; | |
3840 | } | |
3841 | ||
3842 | int qemu_target_page_bits_min(void) | |
3843 | { | |
3844 | return TARGET_PAGE_BITS_MIN; | |
3845 | } | |
a68fe89c | 3846 | #endif |
13eb76e0 | 3847 | |
8e4a424b BS |
3848 | /* |
3849 | * A helper function for the _utterly broken_ virtio device model to find out if | |
3850 | * it's running on a big endian machine. Don't do this at home kids! | |
3851 | */ | |
98ed8ecf GK |
3852 | bool target_words_bigendian(void); |
3853 | bool target_words_bigendian(void) | |
8e4a424b BS |
3854 | { |
3855 | #if defined(TARGET_WORDS_BIGENDIAN) | |
3856 | return true; | |
3857 | #else | |
3858 | return false; | |
3859 | #endif | |
3860 | } | |
3861 | ||
76f35538 | 3862 | #ifndef CONFIG_USER_ONLY |
a8170e5e | 3863 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
76f35538 | 3864 | { |
5c8a00ce | 3865 | MemoryRegion*mr; |
149f54b5 | 3866 | hwaddr l = 1; |
41063e1e | 3867 | bool res; |
76f35538 | 3868 | |
41063e1e | 3869 | rcu_read_lock(); |
5c8a00ce | 3870 | mr = address_space_translate(&address_space_memory, |
bc6b1cec PM |
3871 | phys_addr, &phys_addr, &l, false, |
3872 | MEMTXATTRS_UNSPECIFIED); | |
76f35538 | 3873 | |
41063e1e PB |
3874 | res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); |
3875 | rcu_read_unlock(); | |
3876 | return res; | |
76f35538 | 3877 | } |
bd2fa51f | 3878 | |
e3807054 | 3879 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) |
bd2fa51f MH |
3880 | { |
3881 | RAMBlock *block; | |
e3807054 | 3882 | int ret = 0; |
bd2fa51f | 3883 | |
0dc3f44a | 3884 | rcu_read_lock(); |
99e15582 | 3885 | RAMBLOCK_FOREACH(block) { |
e3807054 DDAG |
3886 | ret = func(block->idstr, block->host, block->offset, |
3887 | block->used_length, opaque); | |
3888 | if (ret) { | |
3889 | break; | |
3890 | } | |
bd2fa51f | 3891 | } |
0dc3f44a | 3892 | rcu_read_unlock(); |
e3807054 | 3893 | return ret; |
bd2fa51f | 3894 | } |
d3a5038c DDAG |
3895 | |
3896 | /* | |
3897 | * Unmap pages of memory from start to start+length such that | |
3898 | * they a) read as 0, b) Trigger whatever fault mechanism | |
3899 | * the OS provides for postcopy. | |
3900 | * The pages must be unmapped by the end of the function. | |
3901 | * Returns: 0 on success, none-0 on failure | |
3902 | * | |
3903 | */ | |
3904 | int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length) | |
3905 | { | |
3906 | int ret = -1; | |
3907 | ||
3908 | uint8_t *host_startaddr = rb->host + start; | |
3909 | ||
3910 | if ((uintptr_t)host_startaddr & (rb->page_size - 1)) { | |
3911 | error_report("ram_block_discard_range: Unaligned start address: %p", | |
3912 | host_startaddr); | |
3913 | goto err; | |
3914 | } | |
3915 | ||
3916 | if ((start + length) <= rb->used_length) { | |
db144f70 | 3917 | bool need_madvise, need_fallocate; |
d3a5038c DDAG |
3918 | uint8_t *host_endaddr = host_startaddr + length; |
3919 | if ((uintptr_t)host_endaddr & (rb->page_size - 1)) { | |
3920 | error_report("ram_block_discard_range: Unaligned end address: %p", | |
3921 | host_endaddr); | |
3922 | goto err; | |
3923 | } | |
3924 | ||
3925 | errno = ENOTSUP; /* If we are missing MADVISE etc */ | |
3926 | ||
db144f70 DDAG |
3927 | /* The logic here is messy; |
3928 | * madvise DONTNEED fails for hugepages | |
3929 | * fallocate works on hugepages and shmem | |
3930 | */ | |
3931 | need_madvise = (rb->page_size == qemu_host_page_size); | |
3932 | need_fallocate = rb->fd != -1; | |
3933 | if (need_fallocate) { | |
3934 | /* For a file, this causes the area of the file to be zero'd | |
3935 | * if read, and for hugetlbfs also causes it to be unmapped | |
3936 | * so a userfault will trigger. | |
e2fa71f5 DDAG |
3937 | */ |
3938 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
3939 | ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, | |
3940 | start, length); | |
db144f70 DDAG |
3941 | if (ret) { |
3942 | ret = -errno; | |
3943 | error_report("ram_block_discard_range: Failed to fallocate " | |
3944 | "%s:%" PRIx64 " +%zx (%d)", | |
3945 | rb->idstr, start, length, ret); | |
3946 | goto err; | |
3947 | } | |
3948 | #else | |
3949 | ret = -ENOSYS; | |
3950 | error_report("ram_block_discard_range: fallocate not available/file" | |
3951 | "%s:%" PRIx64 " +%zx (%d)", | |
3952 | rb->idstr, start, length, ret); | |
3953 | goto err; | |
e2fa71f5 DDAG |
3954 | #endif |
3955 | } | |
db144f70 DDAG |
3956 | if (need_madvise) { |
3957 | /* For normal RAM this causes it to be unmapped, | |
3958 | * for shared memory it causes the local mapping to disappear | |
3959 | * and to fall back on the file contents (which we just | |
3960 | * fallocate'd away). | |
3961 | */ | |
3962 | #if defined(CONFIG_MADVISE) | |
3963 | ret = madvise(host_startaddr, length, MADV_DONTNEED); | |
3964 | if (ret) { | |
3965 | ret = -errno; | |
3966 | error_report("ram_block_discard_range: Failed to discard range " | |
3967 | "%s:%" PRIx64 " +%zx (%d)", | |
3968 | rb->idstr, start, length, ret); | |
3969 | goto err; | |
3970 | } | |
3971 | #else | |
3972 | ret = -ENOSYS; | |
3973 | error_report("ram_block_discard_range: MADVISE not available" | |
d3a5038c DDAG |
3974 | "%s:%" PRIx64 " +%zx (%d)", |
3975 | rb->idstr, start, length, ret); | |
db144f70 DDAG |
3976 | goto err; |
3977 | #endif | |
d3a5038c | 3978 | } |
db144f70 DDAG |
3979 | trace_ram_block_discard_range(rb->idstr, host_startaddr, length, |
3980 | need_madvise, need_fallocate, ret); | |
d3a5038c DDAG |
3981 | } else { |
3982 | error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64 | |
3983 | "/%zx/" RAM_ADDR_FMT")", | |
3984 | rb->idstr, start, length, rb->used_length); | |
3985 | } | |
3986 | ||
3987 | err: | |
3988 | return ret; | |
3989 | } | |
3990 | ||
ec3f8c99 | 3991 | #endif |
a0be0c58 YZ |
3992 | |
3993 | void page_size_init(void) | |
3994 | { | |
3995 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
3996 | TARGET_PAGE_SIZE */ | |
a0be0c58 YZ |
3997 | if (qemu_host_page_size == 0) { |
3998 | qemu_host_page_size = qemu_real_host_page_size; | |
3999 | } | |
4000 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
4001 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
4002 | } | |
4003 | qemu_host_page_mask = -(intptr_t)qemu_host_page_size; | |
4004 | } | |
5e8fd947 AK |
4005 | |
4006 | #if !defined(CONFIG_USER_ONLY) | |
4007 | ||
4008 | static void mtree_print_phys_entries(fprintf_function mon, void *f, | |
4009 | int start, int end, int skip, int ptr) | |
4010 | { | |
4011 | if (start == end - 1) { | |
4012 | mon(f, "\t%3d ", start); | |
4013 | } else { | |
4014 | mon(f, "\t%3d..%-3d ", start, end - 1); | |
4015 | } | |
4016 | mon(f, " skip=%d ", skip); | |
4017 | if (ptr == PHYS_MAP_NODE_NIL) { | |
4018 | mon(f, " ptr=NIL"); | |
4019 | } else if (!skip) { | |
4020 | mon(f, " ptr=#%d", ptr); | |
4021 | } else { | |
4022 | mon(f, " ptr=[%d]", ptr); | |
4023 | } | |
4024 | mon(f, "\n"); | |
4025 | } | |
4026 | ||
4027 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ | |
4028 | int128_sub((size), int128_one())) : 0) | |
4029 | ||
4030 | void mtree_print_dispatch(fprintf_function mon, void *f, | |
4031 | AddressSpaceDispatch *d, MemoryRegion *root) | |
4032 | { | |
4033 | int i; | |
4034 | ||
4035 | mon(f, " Dispatch\n"); | |
4036 | mon(f, " Physical sections\n"); | |
4037 | ||
4038 | for (i = 0; i < d->map.sections_nb; ++i) { | |
4039 | MemoryRegionSection *s = d->map.sections + i; | |
4040 | const char *names[] = { " [unassigned]", " [not dirty]", | |
4041 | " [ROM]", " [watch]" }; | |
4042 | ||
4043 | mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s", | |
4044 | i, | |
4045 | s->offset_within_address_space, | |
4046 | s->offset_within_address_space + MR_SIZE(s->mr->size), | |
4047 | s->mr->name ? s->mr->name : "(noname)", | |
4048 | i < ARRAY_SIZE(names) ? names[i] : "", | |
4049 | s->mr == root ? " [ROOT]" : "", | |
4050 | s == d->mru_section ? " [MRU]" : "", | |
4051 | s->mr->is_iommu ? " [iommu]" : ""); | |
4052 | ||
4053 | if (s->mr->alias) { | |
4054 | mon(f, " alias=%s", s->mr->alias->name ? | |
4055 | s->mr->alias->name : "noname"); | |
4056 | } | |
4057 | mon(f, "\n"); | |
4058 | } | |
4059 | ||
4060 | mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n", | |
4061 | P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip); | |
4062 | for (i = 0; i < d->map.nodes_nb; ++i) { | |
4063 | int j, jprev; | |
4064 | PhysPageEntry prev; | |
4065 | Node *n = d->map.nodes + i; | |
4066 | ||
4067 | mon(f, " [%d]\n", i); | |
4068 | ||
4069 | for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) { | |
4070 | PhysPageEntry *pe = *n + j; | |
4071 | ||
4072 | if (pe->ptr == prev.ptr && pe->skip == prev.skip) { | |
4073 | continue; | |
4074 | } | |
4075 | ||
4076 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
4077 | ||
4078 | jprev = j; | |
4079 | prev = *pe; | |
4080 | } | |
4081 | ||
4082 | if (jprev != ARRAY_SIZE(*n)) { | |
4083 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
4084 | } | |
4085 | } | |
4086 | } | |
4087 | ||
4088 | #endif |