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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 FB |
26 | #include <stdlib.h> |
27 | #include <stdio.h> | |
28 | #include <stdarg.h> | |
29 | #include <string.h> | |
30 | #include <errno.h> | |
31 | #include <unistd.h> | |
32 | #include <inttypes.h> | |
33 | ||
6180a181 FB |
34 | #include "cpu.h" |
35 | #include "exec-all.h" | |
ca10f867 | 36 | #include "qemu-common.h" |
b67d9a52 | 37 | #include "tcg.h" |
b3c7724c | 38 | #include "hw/hw.h" |
74576198 | 39 | #include "osdep.h" |
7ba1e619 | 40 | #include "kvm.h" |
53a5960a PB |
41 | #if defined(CONFIG_USER_ONLY) |
42 | #include <qemu.h> | |
fd052bf6 | 43 | #include <signal.h> |
53a5960a | 44 | #endif |
54936004 | 45 | |
fd6ce8f6 | 46 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 47 | //#define DEBUG_FLUSH |
9fa3e853 | 48 | //#define DEBUG_TLB |
67d3b957 | 49 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
50 | |
51 | /* make various TB consistency checks */ | |
5fafdf24 TS |
52 | //#define DEBUG_TB_CHECK |
53 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 54 | |
1196be37 | 55 | //#define DEBUG_IOPORT |
db7b5426 | 56 | //#define DEBUG_SUBPAGE |
1196be37 | 57 | |
99773bd4 PB |
58 | #if !defined(CONFIG_USER_ONLY) |
59 | /* TB consistency checks only implemented for usermode emulation. */ | |
60 | #undef DEBUG_TB_CHECK | |
61 | #endif | |
62 | ||
9fa3e853 FB |
63 | #define SMC_BITMAP_USE_THRESHOLD 10 |
64 | ||
108c49b8 FB |
65 | #if defined(TARGET_SPARC64) |
66 | #define TARGET_PHYS_ADDR_SPACE_BITS 41 | |
5dcb6b91 BS |
67 | #elif defined(TARGET_SPARC) |
68 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
bedb69ea JM |
69 | #elif defined(TARGET_ALPHA) |
70 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
71 | #define TARGET_VIRT_ADDR_SPACE_BITS 42 | |
108c49b8 FB |
72 | #elif defined(TARGET_PPC64) |
73 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
4a1418e0 | 74 | #elif defined(TARGET_X86_64) |
00f82b8a | 75 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 |
4a1418e0 | 76 | #elif defined(TARGET_I386) |
00f82b8a | 77 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
108c49b8 | 78 | #else |
108c49b8 FB |
79 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
80 | #endif | |
81 | ||
bdaf78e0 | 82 | static TranslationBlock *tbs; |
26a5f13b | 83 | int code_gen_max_blocks; |
9fa3e853 | 84 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 85 | static int nb_tbs; |
eb51d102 | 86 | /* any access to the tbs or the page table must use this lock */ |
c227f099 | 87 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
fd6ce8f6 | 88 | |
141ac468 BS |
89 | #if defined(__arm__) || defined(__sparc_v9__) |
90 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
91 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
92 | section close to code segment. */ |
93 | #define code_gen_section \ | |
94 | __attribute__((__section__(".gen_code"))) \ | |
95 | __attribute__((aligned (32))) | |
f8e2af11 SW |
96 | #elif defined(_WIN32) |
97 | /* Maximum alignment for Win32 is 16. */ | |
98 | #define code_gen_section \ | |
99 | __attribute__((aligned (16))) | |
d03d860b BS |
100 | #else |
101 | #define code_gen_section \ | |
102 | __attribute__((aligned (32))) | |
103 | #endif | |
104 | ||
105 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
106 | static uint8_t *code_gen_buffer; |
107 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 108 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 109 | static unsigned long code_gen_buffer_max_size; |
fd6ce8f6 FB |
110 | uint8_t *code_gen_ptr; |
111 | ||
e2eef170 | 112 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 113 | int phys_ram_fd; |
1ccde1cb | 114 | uint8_t *phys_ram_dirty; |
74576198 | 115 | static int in_migration; |
94a6b54f PB |
116 | |
117 | typedef struct RAMBlock { | |
118 | uint8_t *host; | |
c227f099 AL |
119 | ram_addr_t offset; |
120 | ram_addr_t length; | |
94a6b54f PB |
121 | struct RAMBlock *next; |
122 | } RAMBlock; | |
123 | ||
124 | static RAMBlock *ram_blocks; | |
125 | /* TODO: When we implement (and use) ram deallocation (e.g. for hotplug) | |
ccbb4d44 | 126 | then we can no longer assume contiguous ram offsets, and external uses |
94a6b54f | 127 | of this variable will break. */ |
c227f099 | 128 | ram_addr_t last_ram_offset; |
e2eef170 | 129 | #endif |
9fa3e853 | 130 | |
6a00d601 FB |
131 | CPUState *first_cpu; |
132 | /* current CPU in the current thread. It is only valid inside | |
133 | cpu_exec() */ | |
5fafdf24 | 134 | CPUState *cpu_single_env; |
2e70f6ef | 135 | /* 0 = Do not count executed instructions. |
bf20dc07 | 136 | 1 = Precise instruction counting. |
2e70f6ef PB |
137 | 2 = Adaptive rate instruction counting. */ |
138 | int use_icount = 0; | |
139 | /* Current instruction counter. While executing translated code this may | |
140 | include some instructions that have not yet been executed. */ | |
141 | int64_t qemu_icount; | |
6a00d601 | 142 | |
54936004 | 143 | typedef struct PageDesc { |
92e873b9 | 144 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 145 | TranslationBlock *first_tb; |
9fa3e853 FB |
146 | /* in order to optimize self modifying code, we count the number |
147 | of lookups we do to a given page to use a bitmap */ | |
148 | unsigned int code_write_count; | |
149 | uint8_t *code_bitmap; | |
150 | #if defined(CONFIG_USER_ONLY) | |
151 | unsigned long flags; | |
152 | #endif | |
54936004 FB |
153 | } PageDesc; |
154 | ||
92e873b9 | 155 | typedef struct PhysPageDesc { |
0f459d16 | 156 | /* offset in host memory of the page + io_index in the low bits */ |
c227f099 AL |
157 | ram_addr_t phys_offset; |
158 | ram_addr_t region_offset; | |
92e873b9 FB |
159 | } PhysPageDesc; |
160 | ||
54936004 | 161 | #define L2_BITS 10 |
bedb69ea JM |
162 | #if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS) |
163 | /* XXX: this is a temporary hack for alpha target. | |
164 | * In the future, this is to be replaced by a multi-level table | |
165 | * to actually be able to handle the complete 64 bits address space. | |
166 | */ | |
167 | #define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS) | |
168 | #else | |
03875444 | 169 | #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS) |
bedb69ea | 170 | #endif |
54936004 FB |
171 | |
172 | #define L1_SIZE (1 << L1_BITS) | |
173 | #define L2_SIZE (1 << L2_BITS) | |
174 | ||
83fb7adf FB |
175 | unsigned long qemu_real_host_page_size; |
176 | unsigned long qemu_host_page_bits; | |
177 | unsigned long qemu_host_page_size; | |
178 | unsigned long qemu_host_page_mask; | |
54936004 | 179 | |
92e873b9 | 180 | /* XXX: for system emulation, it could just be an array */ |
54936004 FB |
181 | static PageDesc *l1_map[L1_SIZE]; |
182 | ||
e2eef170 | 183 | #if !defined(CONFIG_USER_ONLY) |
6d9a1304 PB |
184 | static PhysPageDesc **l1_phys_map; |
185 | ||
e2eef170 PB |
186 | static void io_mem_init(void); |
187 | ||
33417e70 | 188 | /* io memory support */ |
33417e70 FB |
189 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
190 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 191 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
511d2b14 | 192 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
6658ffb8 PB |
193 | static int io_mem_watch; |
194 | #endif | |
33417e70 | 195 | |
34865134 | 196 | /* log support */ |
1e8b27ca JR |
197 | #ifdef WIN32 |
198 | static const char *logfilename = "qemu.log"; | |
199 | #else | |
d9b630fd | 200 | static const char *logfilename = "/tmp/qemu.log"; |
1e8b27ca | 201 | #endif |
34865134 FB |
202 | FILE *logfile; |
203 | int loglevel; | |
e735b91c | 204 | static int log_append = 0; |
34865134 | 205 | |
e3db7226 FB |
206 | /* statistics */ |
207 | static int tlb_flush_count; | |
208 | static int tb_flush_count; | |
209 | static int tb_phys_invalidate_count; | |
210 | ||
7cb69cae FB |
211 | #ifdef _WIN32 |
212 | static void map_exec(void *addr, long size) | |
213 | { | |
214 | DWORD old_protect; | |
215 | VirtualProtect(addr, size, | |
216 | PAGE_EXECUTE_READWRITE, &old_protect); | |
217 | ||
218 | } | |
219 | #else | |
220 | static void map_exec(void *addr, long size) | |
221 | { | |
4369415f | 222 | unsigned long start, end, page_size; |
7cb69cae | 223 | |
4369415f | 224 | page_size = getpagesize(); |
7cb69cae | 225 | start = (unsigned long)addr; |
4369415f | 226 | start &= ~(page_size - 1); |
7cb69cae FB |
227 | |
228 | end = (unsigned long)addr + size; | |
4369415f FB |
229 | end += page_size - 1; |
230 | end &= ~(page_size - 1); | |
7cb69cae FB |
231 | |
232 | mprotect((void *)start, end - start, | |
233 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
234 | } | |
235 | #endif | |
236 | ||
b346ff46 | 237 | static void page_init(void) |
54936004 | 238 | { |
83fb7adf | 239 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 240 | TARGET_PAGE_SIZE */ |
c2b48b69 AL |
241 | #ifdef _WIN32 |
242 | { | |
243 | SYSTEM_INFO system_info; | |
244 | ||
245 | GetSystemInfo(&system_info); | |
246 | qemu_real_host_page_size = system_info.dwPageSize; | |
247 | } | |
248 | #else | |
249 | qemu_real_host_page_size = getpagesize(); | |
250 | #endif | |
83fb7adf FB |
251 | if (qemu_host_page_size == 0) |
252 | qemu_host_page_size = qemu_real_host_page_size; | |
253 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
254 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
255 | qemu_host_page_bits = 0; | |
256 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
257 | qemu_host_page_bits++; | |
258 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
6d9a1304 | 259 | #if !defined(CONFIG_USER_ONLY) |
108c49b8 FB |
260 | l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *)); |
261 | memset(l1_phys_map, 0, L1_SIZE * sizeof(void *)); | |
6d9a1304 | 262 | #endif |
50a9569b AZ |
263 | |
264 | #if !defined(_WIN32) && defined(CONFIG_USER_ONLY) | |
265 | { | |
266 | long long startaddr, endaddr; | |
267 | FILE *f; | |
268 | int n; | |
269 | ||
c8a706fe | 270 | mmap_lock(); |
0776590d | 271 | last_brk = (unsigned long)sbrk(0); |
50a9569b AZ |
272 | f = fopen("/proc/self/maps", "r"); |
273 | if (f) { | |
274 | do { | |
275 | n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr); | |
276 | if (n == 2) { | |
e0b8d65a BS |
277 | startaddr = MIN(startaddr, |
278 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
279 | endaddr = MIN(endaddr, | |
280 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
b5fc909e | 281 | page_set_flags(startaddr & TARGET_PAGE_MASK, |
50a9569b AZ |
282 | TARGET_PAGE_ALIGN(endaddr), |
283 | PAGE_RESERVED); | |
284 | } | |
285 | } while (!feof(f)); | |
286 | fclose(f); | |
287 | } | |
c8a706fe | 288 | mmap_unlock(); |
50a9569b AZ |
289 | } |
290 | #endif | |
54936004 FB |
291 | } |
292 | ||
434929bf | 293 | static inline PageDesc **page_l1_map(target_ulong index) |
54936004 | 294 | { |
17e2377a PB |
295 | #if TARGET_LONG_BITS > 32 |
296 | /* Host memory outside guest VM. For 32-bit targets we have already | |
297 | excluded high addresses. */ | |
d8173e0f | 298 | if (index > ((target_ulong)L2_SIZE * L1_SIZE)) |
17e2377a PB |
299 | return NULL; |
300 | #endif | |
434929bf AL |
301 | return &l1_map[index >> L2_BITS]; |
302 | } | |
303 | ||
304 | static inline PageDesc *page_find_alloc(target_ulong index) | |
305 | { | |
306 | PageDesc **lp, *p; | |
307 | lp = page_l1_map(index); | |
308 | if (!lp) | |
309 | return NULL; | |
310 | ||
54936004 FB |
311 | p = *lp; |
312 | if (!p) { | |
313 | /* allocate if not found */ | |
17e2377a | 314 | #if defined(CONFIG_USER_ONLY) |
17e2377a PB |
315 | size_t len = sizeof(PageDesc) * L2_SIZE; |
316 | /* Don't use qemu_malloc because it may recurse. */ | |
660f11be | 317 | p = mmap(NULL, len, PROT_READ | PROT_WRITE, |
17e2377a | 318 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); |
54936004 | 319 | *lp = p; |
fb1c2cd7 AJ |
320 | if (h2g_valid(p)) { |
321 | unsigned long addr = h2g(p); | |
17e2377a PB |
322 | page_set_flags(addr & TARGET_PAGE_MASK, |
323 | TARGET_PAGE_ALIGN(addr + len), | |
324 | PAGE_RESERVED); | |
325 | } | |
326 | #else | |
327 | p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE); | |
328 | *lp = p; | |
329 | #endif | |
54936004 FB |
330 | } |
331 | return p + (index & (L2_SIZE - 1)); | |
332 | } | |
333 | ||
00f82b8a | 334 | static inline PageDesc *page_find(target_ulong index) |
54936004 | 335 | { |
434929bf AL |
336 | PageDesc **lp, *p; |
337 | lp = page_l1_map(index); | |
338 | if (!lp) | |
339 | return NULL; | |
54936004 | 340 | |
434929bf | 341 | p = *lp; |
660f11be BS |
342 | if (!p) { |
343 | return NULL; | |
344 | } | |
fd6ce8f6 FB |
345 | return p + (index & (L2_SIZE - 1)); |
346 | } | |
347 | ||
6d9a1304 | 348 | #if !defined(CONFIG_USER_ONLY) |
c227f099 | 349 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 350 | { |
108c49b8 | 351 | void **lp, **p; |
e3f4e2a4 | 352 | PhysPageDesc *pd; |
92e873b9 | 353 | |
108c49b8 FB |
354 | p = (void **)l1_phys_map; |
355 | #if TARGET_PHYS_ADDR_SPACE_BITS > 32 | |
356 | ||
357 | #if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS) | |
358 | #error unsupported TARGET_PHYS_ADDR_SPACE_BITS | |
359 | #endif | |
360 | lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1)); | |
92e873b9 FB |
361 | p = *lp; |
362 | if (!p) { | |
363 | /* allocate if not found */ | |
108c49b8 FB |
364 | if (!alloc) |
365 | return NULL; | |
366 | p = qemu_vmalloc(sizeof(void *) * L1_SIZE); | |
367 | memset(p, 0, sizeof(void *) * L1_SIZE); | |
368 | *lp = p; | |
369 | } | |
370 | #endif | |
371 | lp = p + ((index >> L2_BITS) & (L1_SIZE - 1)); | |
e3f4e2a4 PB |
372 | pd = *lp; |
373 | if (!pd) { | |
374 | int i; | |
108c49b8 FB |
375 | /* allocate if not found */ |
376 | if (!alloc) | |
377 | return NULL; | |
e3f4e2a4 PB |
378 | pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE); |
379 | *lp = pd; | |
67c4d23c | 380 | for (i = 0; i < L2_SIZE; i++) { |
e3f4e2a4 | 381 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
67c4d23c PB |
382 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; |
383 | } | |
92e873b9 | 384 | } |
e3f4e2a4 | 385 | return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1)); |
92e873b9 FB |
386 | } |
387 | ||
c227f099 | 388 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 389 | { |
108c49b8 | 390 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
391 | } |
392 | ||
c227f099 AL |
393 | static void tlb_protect_code(ram_addr_t ram_addr); |
394 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
3a7d929e | 395 | target_ulong vaddr); |
c8a706fe PB |
396 | #define mmap_lock() do { } while(0) |
397 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 398 | #endif |
fd6ce8f6 | 399 | |
4369415f FB |
400 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
401 | ||
402 | #if defined(CONFIG_USER_ONLY) | |
ccbb4d44 | 403 | /* Currently it is not recommended to allocate big chunks of data in |
4369415f FB |
404 | user mode. It will change when a dedicated libc will be used */ |
405 | #define USE_STATIC_CODE_GEN_BUFFER | |
406 | #endif | |
407 | ||
408 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
409 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]; | |
410 | #endif | |
411 | ||
8fcd3692 | 412 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 413 | { |
4369415f FB |
414 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
415 | code_gen_buffer = static_code_gen_buffer; | |
416 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
417 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
418 | #else | |
26a5f13b FB |
419 | code_gen_buffer_size = tb_size; |
420 | if (code_gen_buffer_size == 0) { | |
4369415f FB |
421 | #if defined(CONFIG_USER_ONLY) |
422 | /* in user mode, phys_ram_size is not meaningful */ | |
423 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
424 | #else | |
ccbb4d44 | 425 | /* XXX: needs adjustments */ |
94a6b54f | 426 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
4369415f | 427 | #endif |
26a5f13b FB |
428 | } |
429 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
430 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
431 | /* The code gen buffer location may have constraints depending on | |
432 | the host cpu and OS */ | |
433 | #if defined(__linux__) | |
434 | { | |
435 | int flags; | |
141ac468 BS |
436 | void *start = NULL; |
437 | ||
26a5f13b FB |
438 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
439 | #if defined(__x86_64__) | |
440 | flags |= MAP_32BIT; | |
441 | /* Cannot map more than that */ | |
442 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
443 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
444 | #elif defined(__sparc_v9__) |
445 | // Map the buffer below 2G, so we can use direct calls and branches | |
446 | flags |= MAP_FIXED; | |
447 | start = (void *) 0x60000000UL; | |
448 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
449 | code_gen_buffer_size = (512 * 1024 * 1024); | |
1cb0661e | 450 | #elif defined(__arm__) |
63d41246 | 451 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
1cb0661e AZ |
452 | flags |= MAP_FIXED; |
453 | start = (void *) 0x01000000UL; | |
454 | if (code_gen_buffer_size > 16 * 1024 * 1024) | |
455 | code_gen_buffer_size = 16 * 1024 * 1024; | |
26a5f13b | 456 | #endif |
141ac468 BS |
457 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
458 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
459 | flags, -1, 0); |
460 | if (code_gen_buffer == MAP_FAILED) { | |
461 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
462 | exit(1); | |
463 | } | |
464 | } | |
a167ba50 | 465 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
06e67a82 AL |
466 | { |
467 | int flags; | |
468 | void *addr = NULL; | |
469 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
470 | #if defined(__x86_64__) | |
471 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
472 | * 0x40000000 is free */ | |
473 | flags |= MAP_FIXED; | |
474 | addr = (void *)0x40000000; | |
475 | /* Cannot map more than that */ | |
476 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
477 | code_gen_buffer_size = (800 * 1024 * 1024); | |
478 | #endif | |
479 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
480 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
481 | flags, -1, 0); | |
482 | if (code_gen_buffer == MAP_FAILED) { | |
483 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
484 | exit(1); | |
485 | } | |
486 | } | |
26a5f13b FB |
487 | #else |
488 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
26a5f13b FB |
489 | map_exec(code_gen_buffer, code_gen_buffer_size); |
490 | #endif | |
4369415f | 491 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b FB |
492 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
493 | code_gen_buffer_max_size = code_gen_buffer_size - | |
494 | code_gen_max_block_size(); | |
495 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; | |
496 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
497 | } | |
498 | ||
499 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
500 | (in bytes) allocated to the translation buffer. Zero means default | |
501 | size. */ | |
502 | void cpu_exec_init_all(unsigned long tb_size) | |
503 | { | |
26a5f13b FB |
504 | cpu_gen_init(); |
505 | code_gen_alloc(tb_size); | |
506 | code_gen_ptr = code_gen_buffer; | |
4369415f | 507 | page_init(); |
e2eef170 | 508 | #if !defined(CONFIG_USER_ONLY) |
26a5f13b | 509 | io_mem_init(); |
e2eef170 | 510 | #endif |
26a5f13b FB |
511 | } |
512 | ||
9656f324 PB |
513 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
514 | ||
d4bfa4d7 | 515 | static void cpu_common_pre_save(void *opaque) |
9656f324 | 516 | { |
d4bfa4d7 | 517 | CPUState *env = opaque; |
9656f324 | 518 | |
4c0960c0 | 519 | cpu_synchronize_state(env); |
9656f324 PB |
520 | } |
521 | ||
e7f4eff7 | 522 | static int cpu_common_pre_load(void *opaque) |
9656f324 PB |
523 | { |
524 | CPUState *env = opaque; | |
525 | ||
4c0960c0 | 526 | cpu_synchronize_state(env); |
e7f4eff7 JQ |
527 | return 0; |
528 | } | |
529 | ||
e59fb374 | 530 | static int cpu_common_post_load(void *opaque, int version_id) |
e7f4eff7 JQ |
531 | { |
532 | CPUState *env = opaque; | |
9656f324 | 533 | |
3098dba0 AJ |
534 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
535 | version_id is increased. */ | |
536 | env->interrupt_request &= ~0x01; | |
9656f324 PB |
537 | tlb_flush(env, 1); |
538 | ||
539 | return 0; | |
540 | } | |
e7f4eff7 JQ |
541 | |
542 | static const VMStateDescription vmstate_cpu_common = { | |
543 | .name = "cpu_common", | |
544 | .version_id = 1, | |
545 | .minimum_version_id = 1, | |
546 | .minimum_version_id_old = 1, | |
547 | .pre_save = cpu_common_pre_save, | |
548 | .pre_load = cpu_common_pre_load, | |
549 | .post_load = cpu_common_post_load, | |
550 | .fields = (VMStateField []) { | |
551 | VMSTATE_UINT32(halted, CPUState), | |
552 | VMSTATE_UINT32(interrupt_request, CPUState), | |
553 | VMSTATE_END_OF_LIST() | |
554 | } | |
555 | }; | |
9656f324 PB |
556 | #endif |
557 | ||
950f1472 GC |
558 | CPUState *qemu_get_cpu(int cpu) |
559 | { | |
560 | CPUState *env = first_cpu; | |
561 | ||
562 | while (env) { | |
563 | if (env->cpu_index == cpu) | |
564 | break; | |
565 | env = env->next_cpu; | |
566 | } | |
567 | ||
568 | return env; | |
569 | } | |
570 | ||
6a00d601 | 571 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 572 | { |
6a00d601 FB |
573 | CPUState **penv; |
574 | int cpu_index; | |
575 | ||
c2764719 PB |
576 | #if defined(CONFIG_USER_ONLY) |
577 | cpu_list_lock(); | |
578 | #endif | |
6a00d601 FB |
579 | env->next_cpu = NULL; |
580 | penv = &first_cpu; | |
581 | cpu_index = 0; | |
582 | while (*penv != NULL) { | |
1e9fa730 | 583 | penv = &(*penv)->next_cpu; |
6a00d601 FB |
584 | cpu_index++; |
585 | } | |
586 | env->cpu_index = cpu_index; | |
268a362c | 587 | env->numa_node = 0; |
72cf2d4f BS |
588 | QTAILQ_INIT(&env->breakpoints); |
589 | QTAILQ_INIT(&env->watchpoints); | |
6a00d601 | 590 | *penv = env; |
c2764719 PB |
591 | #if defined(CONFIG_USER_ONLY) |
592 | cpu_list_unlock(); | |
593 | #endif | |
b3c7724c | 594 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
e7f4eff7 | 595 | vmstate_register(cpu_index, &vmstate_cpu_common, env); |
b3c7724c PB |
596 | register_savevm("cpu", cpu_index, CPU_SAVE_VERSION, |
597 | cpu_save, cpu_load, env); | |
598 | #endif | |
fd6ce8f6 FB |
599 | } |
600 | ||
9fa3e853 FB |
601 | static inline void invalidate_page_bitmap(PageDesc *p) |
602 | { | |
603 | if (p->code_bitmap) { | |
59817ccb | 604 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
605 | p->code_bitmap = NULL; |
606 | } | |
607 | p->code_write_count = 0; | |
608 | } | |
609 | ||
fd6ce8f6 FB |
610 | /* set to NULL all the 'first_tb' fields in all PageDescs */ |
611 | static void page_flush_tb(void) | |
612 | { | |
613 | int i, j; | |
614 | PageDesc *p; | |
615 | ||
616 | for(i = 0; i < L1_SIZE; i++) { | |
617 | p = l1_map[i]; | |
618 | if (p) { | |
9fa3e853 FB |
619 | for(j = 0; j < L2_SIZE; j++) { |
620 | p->first_tb = NULL; | |
621 | invalidate_page_bitmap(p); | |
622 | p++; | |
623 | } | |
fd6ce8f6 FB |
624 | } |
625 | } | |
626 | } | |
627 | ||
628 | /* flush all the translation blocks */ | |
d4e8164f | 629 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 630 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 631 | { |
6a00d601 | 632 | CPUState *env; |
0124311e | 633 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
634 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
635 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
636 | nb_tbs, nb_tbs > 0 ? | |
637 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 638 | #endif |
26a5f13b | 639 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
640 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
641 | ||
fd6ce8f6 | 642 | nb_tbs = 0; |
3b46e624 | 643 | |
6a00d601 FB |
644 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
645 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
646 | } | |
9fa3e853 | 647 | |
8a8a608f | 648 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 649 | page_flush_tb(); |
9fa3e853 | 650 | |
fd6ce8f6 | 651 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
652 | /* XXX: flush processor icache at this point if cache flush is |
653 | expensive */ | |
e3db7226 | 654 | tb_flush_count++; |
fd6ce8f6 FB |
655 | } |
656 | ||
657 | #ifdef DEBUG_TB_CHECK | |
658 | ||
bc98a7ef | 659 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
660 | { |
661 | TranslationBlock *tb; | |
662 | int i; | |
663 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
664 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
665 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
666 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
667 | address >= tb->pc + tb->size)) { | |
0bf9e31a BS |
668 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
669 | " PC=%08lx size=%04x\n", | |
99773bd4 | 670 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
671 | } |
672 | } | |
673 | } | |
674 | } | |
675 | ||
676 | /* verify that all the pages have correct rights for code */ | |
677 | static void tb_page_check(void) | |
678 | { | |
679 | TranslationBlock *tb; | |
680 | int i, flags1, flags2; | |
3b46e624 | 681 | |
99773bd4 PB |
682 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
683 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
684 | flags1 = page_get_flags(tb->pc); |
685 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
686 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
687 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 688 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
689 | } |
690 | } | |
691 | } | |
692 | } | |
693 | ||
694 | #endif | |
695 | ||
696 | /* invalidate one TB */ | |
697 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
698 | int next_offset) | |
699 | { | |
700 | TranslationBlock *tb1; | |
701 | for(;;) { | |
702 | tb1 = *ptb; | |
703 | if (tb1 == tb) { | |
704 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
705 | break; | |
706 | } | |
707 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
708 | } | |
709 | } | |
710 | ||
9fa3e853 FB |
711 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
712 | { | |
713 | TranslationBlock *tb1; | |
714 | unsigned int n1; | |
715 | ||
716 | for(;;) { | |
717 | tb1 = *ptb; | |
718 | n1 = (long)tb1 & 3; | |
719 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
720 | if (tb1 == tb) { | |
721 | *ptb = tb1->page_next[n1]; | |
722 | break; | |
723 | } | |
724 | ptb = &tb1->page_next[n1]; | |
725 | } | |
726 | } | |
727 | ||
d4e8164f FB |
728 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
729 | { | |
730 | TranslationBlock *tb1, **ptb; | |
731 | unsigned int n1; | |
732 | ||
733 | ptb = &tb->jmp_next[n]; | |
734 | tb1 = *ptb; | |
735 | if (tb1) { | |
736 | /* find tb(n) in circular list */ | |
737 | for(;;) { | |
738 | tb1 = *ptb; | |
739 | n1 = (long)tb1 & 3; | |
740 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
741 | if (n1 == n && tb1 == tb) | |
742 | break; | |
743 | if (n1 == 2) { | |
744 | ptb = &tb1->jmp_first; | |
745 | } else { | |
746 | ptb = &tb1->jmp_next[n1]; | |
747 | } | |
748 | } | |
749 | /* now we can suppress tb(n) from the list */ | |
750 | *ptb = tb->jmp_next[n]; | |
751 | ||
752 | tb->jmp_next[n] = NULL; | |
753 | } | |
754 | } | |
755 | ||
756 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
757 | another TB */ | |
758 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
759 | { | |
760 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
761 | } | |
762 | ||
2e70f6ef | 763 | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr) |
fd6ce8f6 | 764 | { |
6a00d601 | 765 | CPUState *env; |
8a40a180 | 766 | PageDesc *p; |
d4e8164f | 767 | unsigned int h, n1; |
c227f099 | 768 | target_phys_addr_t phys_pc; |
8a40a180 | 769 | TranslationBlock *tb1, *tb2; |
3b46e624 | 770 | |
8a40a180 FB |
771 | /* remove the TB from the hash list */ |
772 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
773 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 774 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
775 | offsetof(TranslationBlock, phys_hash_next)); |
776 | ||
777 | /* remove the TB from the page list */ | |
778 | if (tb->page_addr[0] != page_addr) { | |
779 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
780 | tb_page_remove(&p->first_tb, tb); | |
781 | invalidate_page_bitmap(p); | |
782 | } | |
783 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
784 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
785 | tb_page_remove(&p->first_tb, tb); | |
786 | invalidate_page_bitmap(p); | |
787 | } | |
788 | ||
36bdbe54 | 789 | tb_invalidated_flag = 1; |
59817ccb | 790 | |
fd6ce8f6 | 791 | /* remove the TB from the hash list */ |
8a40a180 | 792 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
793 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
794 | if (env->tb_jmp_cache[h] == tb) | |
795 | env->tb_jmp_cache[h] = NULL; | |
796 | } | |
d4e8164f FB |
797 | |
798 | /* suppress this TB from the two jump lists */ | |
799 | tb_jmp_remove(tb, 0); | |
800 | tb_jmp_remove(tb, 1); | |
801 | ||
802 | /* suppress any remaining jumps to this TB */ | |
803 | tb1 = tb->jmp_first; | |
804 | for(;;) { | |
805 | n1 = (long)tb1 & 3; | |
806 | if (n1 == 2) | |
807 | break; | |
808 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
809 | tb2 = tb1->jmp_next[n1]; | |
810 | tb_reset_jump(tb1, n1); | |
811 | tb1->jmp_next[n1] = NULL; | |
812 | tb1 = tb2; | |
813 | } | |
814 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 815 | |
e3db7226 | 816 | tb_phys_invalidate_count++; |
9fa3e853 FB |
817 | } |
818 | ||
819 | static inline void set_bits(uint8_t *tab, int start, int len) | |
820 | { | |
821 | int end, mask, end1; | |
822 | ||
823 | end = start + len; | |
824 | tab += start >> 3; | |
825 | mask = 0xff << (start & 7); | |
826 | if ((start & ~7) == (end & ~7)) { | |
827 | if (start < end) { | |
828 | mask &= ~(0xff << (end & 7)); | |
829 | *tab |= mask; | |
830 | } | |
831 | } else { | |
832 | *tab++ |= mask; | |
833 | start = (start + 8) & ~7; | |
834 | end1 = end & ~7; | |
835 | while (start < end1) { | |
836 | *tab++ = 0xff; | |
837 | start += 8; | |
838 | } | |
839 | if (start < end) { | |
840 | mask = ~(0xff << (end & 7)); | |
841 | *tab |= mask; | |
842 | } | |
843 | } | |
844 | } | |
845 | ||
846 | static void build_page_bitmap(PageDesc *p) | |
847 | { | |
848 | int n, tb_start, tb_end; | |
849 | TranslationBlock *tb; | |
3b46e624 | 850 | |
b2a7081a | 851 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
852 | |
853 | tb = p->first_tb; | |
854 | while (tb != NULL) { | |
855 | n = (long)tb & 3; | |
856 | tb = (TranslationBlock *)((long)tb & ~3); | |
857 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
858 | if (n == 0) { | |
859 | /* NOTE: tb_end may be after the end of the page, but | |
860 | it is not a problem */ | |
861 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
862 | tb_end = tb_start + tb->size; | |
863 | if (tb_end > TARGET_PAGE_SIZE) | |
864 | tb_end = TARGET_PAGE_SIZE; | |
865 | } else { | |
866 | tb_start = 0; | |
867 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
868 | } | |
869 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
870 | tb = tb->page_next[n]; | |
871 | } | |
872 | } | |
873 | ||
2e70f6ef PB |
874 | TranslationBlock *tb_gen_code(CPUState *env, |
875 | target_ulong pc, target_ulong cs_base, | |
876 | int flags, int cflags) | |
d720b93d FB |
877 | { |
878 | TranslationBlock *tb; | |
879 | uint8_t *tc_ptr; | |
880 | target_ulong phys_pc, phys_page2, virt_page2; | |
881 | int code_gen_size; | |
882 | ||
c27004ec FB |
883 | phys_pc = get_phys_addr_code(env, pc); |
884 | tb = tb_alloc(pc); | |
d720b93d FB |
885 | if (!tb) { |
886 | /* flush must be done */ | |
887 | tb_flush(env); | |
888 | /* cannot fail at this point */ | |
c27004ec | 889 | tb = tb_alloc(pc); |
2e70f6ef PB |
890 | /* Don't forget to invalidate previous TB info. */ |
891 | tb_invalidated_flag = 1; | |
d720b93d FB |
892 | } |
893 | tc_ptr = code_gen_ptr; | |
894 | tb->tc_ptr = tc_ptr; | |
895 | tb->cs_base = cs_base; | |
896 | tb->flags = flags; | |
897 | tb->cflags = cflags; | |
d07bde88 | 898 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 899 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 900 | |
d720b93d | 901 | /* check next page if needed */ |
c27004ec | 902 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 903 | phys_page2 = -1; |
c27004ec | 904 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
d720b93d FB |
905 | phys_page2 = get_phys_addr_code(env, virt_page2); |
906 | } | |
907 | tb_link_phys(tb, phys_pc, phys_page2); | |
2e70f6ef | 908 | return tb; |
d720b93d | 909 | } |
3b46e624 | 910 | |
9fa3e853 FB |
911 | /* invalidate all TBs which intersect with the target physical page |
912 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
913 | the same physical page. 'is_cpu_write_access' should be true if called |
914 | from a real cpu write access: the virtual CPU will exit the current | |
915 | TB if code is modified inside this TB. */ | |
c227f099 | 916 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
d720b93d FB |
917 | int is_cpu_write_access) |
918 | { | |
6b917547 | 919 | TranslationBlock *tb, *tb_next, *saved_tb; |
d720b93d | 920 | CPUState *env = cpu_single_env; |
9fa3e853 | 921 | target_ulong tb_start, tb_end; |
6b917547 AL |
922 | PageDesc *p; |
923 | int n; | |
924 | #ifdef TARGET_HAS_PRECISE_SMC | |
925 | int current_tb_not_found = is_cpu_write_access; | |
926 | TranslationBlock *current_tb = NULL; | |
927 | int current_tb_modified = 0; | |
928 | target_ulong current_pc = 0; | |
929 | target_ulong current_cs_base = 0; | |
930 | int current_flags = 0; | |
931 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
932 | |
933 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 934 | if (!p) |
9fa3e853 | 935 | return; |
5fafdf24 | 936 | if (!p->code_bitmap && |
d720b93d FB |
937 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
938 | is_cpu_write_access) { | |
9fa3e853 FB |
939 | /* build code bitmap */ |
940 | build_page_bitmap(p); | |
941 | } | |
942 | ||
943 | /* we remove all the TBs in the range [start, end[ */ | |
944 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
945 | tb = p->first_tb; | |
946 | while (tb != NULL) { | |
947 | n = (long)tb & 3; | |
948 | tb = (TranslationBlock *)((long)tb & ~3); | |
949 | tb_next = tb->page_next[n]; | |
950 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
951 | if (n == 0) { | |
952 | /* NOTE: tb_end may be after the end of the page, but | |
953 | it is not a problem */ | |
954 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
955 | tb_end = tb_start + tb->size; | |
956 | } else { | |
957 | tb_start = tb->page_addr[1]; | |
958 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
959 | } | |
960 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
961 | #ifdef TARGET_HAS_PRECISE_SMC |
962 | if (current_tb_not_found) { | |
963 | current_tb_not_found = 0; | |
964 | current_tb = NULL; | |
2e70f6ef | 965 | if (env->mem_io_pc) { |
d720b93d | 966 | /* now we have a real cpu fault */ |
2e70f6ef | 967 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
968 | } |
969 | } | |
970 | if (current_tb == tb && | |
2e70f6ef | 971 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
972 | /* If we are modifying the current TB, we must stop |
973 | its execution. We could be more precise by checking | |
974 | that the modification is after the current PC, but it | |
975 | would require a specialized function to partially | |
976 | restore the CPU state */ | |
3b46e624 | 977 | |
d720b93d | 978 | current_tb_modified = 1; |
5fafdf24 | 979 | cpu_restore_state(current_tb, env, |
2e70f6ef | 980 | env->mem_io_pc, NULL); |
6b917547 AL |
981 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
982 | ¤t_flags); | |
d720b93d FB |
983 | } |
984 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
985 | /* we need to do that to handle the case where a signal |
986 | occurs while doing tb_phys_invalidate() */ | |
987 | saved_tb = NULL; | |
988 | if (env) { | |
989 | saved_tb = env->current_tb; | |
990 | env->current_tb = NULL; | |
991 | } | |
9fa3e853 | 992 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
993 | if (env) { |
994 | env->current_tb = saved_tb; | |
995 | if (env->interrupt_request && env->current_tb) | |
996 | cpu_interrupt(env, env->interrupt_request); | |
997 | } | |
9fa3e853 FB |
998 | } |
999 | tb = tb_next; | |
1000 | } | |
1001 | #if !defined(CONFIG_USER_ONLY) | |
1002 | /* if no code remaining, no need to continue to use slow writes */ | |
1003 | if (!p->first_tb) { | |
1004 | invalidate_page_bitmap(p); | |
d720b93d | 1005 | if (is_cpu_write_access) { |
2e70f6ef | 1006 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
1007 | } |
1008 | } | |
1009 | #endif | |
1010 | #ifdef TARGET_HAS_PRECISE_SMC | |
1011 | if (current_tb_modified) { | |
1012 | /* we generate a block containing just the instruction | |
1013 | modifying the memory. It will ensure that it cannot modify | |
1014 | itself */ | |
ea1c1802 | 1015 | env->current_tb = NULL; |
2e70f6ef | 1016 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 1017 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 1018 | } |
fd6ce8f6 | 1019 | #endif |
9fa3e853 | 1020 | } |
fd6ce8f6 | 1021 | |
9fa3e853 | 1022 | /* len must be <= 8 and start must be a multiple of len */ |
c227f099 | 1023 | static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len) |
9fa3e853 FB |
1024 | { |
1025 | PageDesc *p; | |
1026 | int offset, b; | |
59817ccb | 1027 | #if 0 |
a4193c8a | 1028 | if (1) { |
93fcfe39 AL |
1029 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
1030 | cpu_single_env->mem_io_vaddr, len, | |
1031 | cpu_single_env->eip, | |
1032 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
59817ccb FB |
1033 | } |
1034 | #endif | |
9fa3e853 | 1035 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1036 | if (!p) |
9fa3e853 FB |
1037 | return; |
1038 | if (p->code_bitmap) { | |
1039 | offset = start & ~TARGET_PAGE_MASK; | |
1040 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1041 | if (b & ((1 << len) - 1)) | |
1042 | goto do_invalidate; | |
1043 | } else { | |
1044 | do_invalidate: | |
d720b93d | 1045 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1046 | } |
1047 | } | |
1048 | ||
9fa3e853 | 1049 | #if !defined(CONFIG_SOFTMMU) |
c227f099 | 1050 | static void tb_invalidate_phys_page(target_phys_addr_t addr, |
d720b93d | 1051 | unsigned long pc, void *puc) |
9fa3e853 | 1052 | { |
6b917547 | 1053 | TranslationBlock *tb; |
9fa3e853 | 1054 | PageDesc *p; |
6b917547 | 1055 | int n; |
d720b93d | 1056 | #ifdef TARGET_HAS_PRECISE_SMC |
6b917547 | 1057 | TranslationBlock *current_tb = NULL; |
d720b93d | 1058 | CPUState *env = cpu_single_env; |
6b917547 AL |
1059 | int current_tb_modified = 0; |
1060 | target_ulong current_pc = 0; | |
1061 | target_ulong current_cs_base = 0; | |
1062 | int current_flags = 0; | |
d720b93d | 1063 | #endif |
9fa3e853 FB |
1064 | |
1065 | addr &= TARGET_PAGE_MASK; | |
1066 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1067 | if (!p) |
9fa3e853 FB |
1068 | return; |
1069 | tb = p->first_tb; | |
d720b93d FB |
1070 | #ifdef TARGET_HAS_PRECISE_SMC |
1071 | if (tb && pc != 0) { | |
1072 | current_tb = tb_find_pc(pc); | |
1073 | } | |
1074 | #endif | |
9fa3e853 FB |
1075 | while (tb != NULL) { |
1076 | n = (long)tb & 3; | |
1077 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1078 | #ifdef TARGET_HAS_PRECISE_SMC |
1079 | if (current_tb == tb && | |
2e70f6ef | 1080 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1081 | /* If we are modifying the current TB, we must stop |
1082 | its execution. We could be more precise by checking | |
1083 | that the modification is after the current PC, but it | |
1084 | would require a specialized function to partially | |
1085 | restore the CPU state */ | |
3b46e624 | 1086 | |
d720b93d FB |
1087 | current_tb_modified = 1; |
1088 | cpu_restore_state(current_tb, env, pc, puc); | |
6b917547 AL |
1089 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1090 | ¤t_flags); | |
d720b93d FB |
1091 | } |
1092 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1093 | tb_phys_invalidate(tb, addr); |
1094 | tb = tb->page_next[n]; | |
1095 | } | |
fd6ce8f6 | 1096 | p->first_tb = NULL; |
d720b93d FB |
1097 | #ifdef TARGET_HAS_PRECISE_SMC |
1098 | if (current_tb_modified) { | |
1099 | /* we generate a block containing just the instruction | |
1100 | modifying the memory. It will ensure that it cannot modify | |
1101 | itself */ | |
ea1c1802 | 1102 | env->current_tb = NULL; |
2e70f6ef | 1103 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1104 | cpu_resume_from_signal(env, puc); |
1105 | } | |
1106 | #endif | |
fd6ce8f6 | 1107 | } |
9fa3e853 | 1108 | #endif |
fd6ce8f6 FB |
1109 | |
1110 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1111 | static inline void tb_alloc_page(TranslationBlock *tb, |
53a5960a | 1112 | unsigned int n, target_ulong page_addr) |
fd6ce8f6 FB |
1113 | { |
1114 | PageDesc *p; | |
9fa3e853 FB |
1115 | TranslationBlock *last_first_tb; |
1116 | ||
1117 | tb->page_addr[n] = page_addr; | |
3a7d929e | 1118 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
1119 | tb->page_next[n] = p->first_tb; |
1120 | last_first_tb = p->first_tb; | |
1121 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1122 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1123 | |
107db443 | 1124 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1125 | |
9fa3e853 | 1126 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1127 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1128 | target_ulong addr; |
1129 | PageDesc *p2; | |
9fa3e853 FB |
1130 | int prot; |
1131 | ||
fd6ce8f6 FB |
1132 | /* force the host page as non writable (writes will have a |
1133 | page fault + mprotect overhead) */ | |
53a5960a | 1134 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1135 | prot = 0; |
53a5960a PB |
1136 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1137 | addr += TARGET_PAGE_SIZE) { | |
1138 | ||
1139 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1140 | if (!p2) | |
1141 | continue; | |
1142 | prot |= p2->flags; | |
1143 | p2->flags &= ~PAGE_WRITE; | |
1144 | page_get_flags(addr); | |
1145 | } | |
5fafdf24 | 1146 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1147 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1148 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1149 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1150 | page_addr); |
fd6ce8f6 | 1151 | #endif |
fd6ce8f6 | 1152 | } |
9fa3e853 FB |
1153 | #else |
1154 | /* if some code is already present, then the pages are already | |
1155 | protected. So we handle the case where only the first TB is | |
1156 | allocated in a physical page */ | |
1157 | if (!last_first_tb) { | |
6a00d601 | 1158 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1159 | } |
1160 | #endif | |
d720b93d FB |
1161 | |
1162 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1163 | } |
1164 | ||
1165 | /* Allocate a new translation block. Flush the translation buffer if | |
1166 | too many translation blocks or too much generated code. */ | |
c27004ec | 1167 | TranslationBlock *tb_alloc(target_ulong pc) |
fd6ce8f6 FB |
1168 | { |
1169 | TranslationBlock *tb; | |
fd6ce8f6 | 1170 | |
26a5f13b FB |
1171 | if (nb_tbs >= code_gen_max_blocks || |
1172 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
d4e8164f | 1173 | return NULL; |
fd6ce8f6 FB |
1174 | tb = &tbs[nb_tbs++]; |
1175 | tb->pc = pc; | |
b448f2f3 | 1176 | tb->cflags = 0; |
d4e8164f FB |
1177 | return tb; |
1178 | } | |
1179 | ||
2e70f6ef PB |
1180 | void tb_free(TranslationBlock *tb) |
1181 | { | |
bf20dc07 | 1182 | /* In practice this is mostly used for single use temporary TB |
2e70f6ef PB |
1183 | Ignore the hard cases and just back up if this TB happens to |
1184 | be the last one generated. */ | |
1185 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
1186 | code_gen_ptr = tb->tc_ptr; | |
1187 | nb_tbs--; | |
1188 | } | |
1189 | } | |
1190 | ||
9fa3e853 FB |
1191 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1192 | (-1) to indicate that only one page contains the TB. */ | |
5fafdf24 | 1193 | void tb_link_phys(TranslationBlock *tb, |
9fa3e853 | 1194 | target_ulong phys_pc, target_ulong phys_page2) |
d4e8164f | 1195 | { |
9fa3e853 FB |
1196 | unsigned int h; |
1197 | TranslationBlock **ptb; | |
1198 | ||
c8a706fe PB |
1199 | /* Grab the mmap lock to stop another thread invalidating this TB |
1200 | before we are done. */ | |
1201 | mmap_lock(); | |
9fa3e853 FB |
1202 | /* add in the physical hash table */ |
1203 | h = tb_phys_hash_func(phys_pc); | |
1204 | ptb = &tb_phys_hash[h]; | |
1205 | tb->phys_hash_next = *ptb; | |
1206 | *ptb = tb; | |
fd6ce8f6 FB |
1207 | |
1208 | /* add in the page list */ | |
9fa3e853 FB |
1209 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1210 | if (phys_page2 != -1) | |
1211 | tb_alloc_page(tb, 1, phys_page2); | |
1212 | else | |
1213 | tb->page_addr[1] = -1; | |
9fa3e853 | 1214 | |
d4e8164f FB |
1215 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1216 | tb->jmp_next[0] = NULL; | |
1217 | tb->jmp_next[1] = NULL; | |
1218 | ||
1219 | /* init original jump addresses */ | |
1220 | if (tb->tb_next_offset[0] != 0xffff) | |
1221 | tb_reset_jump(tb, 0); | |
1222 | if (tb->tb_next_offset[1] != 0xffff) | |
1223 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1224 | |
1225 | #ifdef DEBUG_TB_CHECK | |
1226 | tb_page_check(); | |
1227 | #endif | |
c8a706fe | 1228 | mmap_unlock(); |
fd6ce8f6 FB |
1229 | } |
1230 | ||
9fa3e853 FB |
1231 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1232 | tb[1].tc_ptr. Return NULL if not found */ | |
1233 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1234 | { |
9fa3e853 FB |
1235 | int m_min, m_max, m; |
1236 | unsigned long v; | |
1237 | TranslationBlock *tb; | |
a513fe19 FB |
1238 | |
1239 | if (nb_tbs <= 0) | |
1240 | return NULL; | |
1241 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1242 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1243 | return NULL; | |
1244 | /* binary search (cf Knuth) */ | |
1245 | m_min = 0; | |
1246 | m_max = nb_tbs - 1; | |
1247 | while (m_min <= m_max) { | |
1248 | m = (m_min + m_max) >> 1; | |
1249 | tb = &tbs[m]; | |
1250 | v = (unsigned long)tb->tc_ptr; | |
1251 | if (v == tc_ptr) | |
1252 | return tb; | |
1253 | else if (tc_ptr < v) { | |
1254 | m_max = m - 1; | |
1255 | } else { | |
1256 | m_min = m + 1; | |
1257 | } | |
5fafdf24 | 1258 | } |
a513fe19 FB |
1259 | return &tbs[m_max]; |
1260 | } | |
7501267e | 1261 | |
ea041c0e FB |
1262 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1263 | ||
1264 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1265 | { | |
1266 | TranslationBlock *tb1, *tb_next, **ptb; | |
1267 | unsigned int n1; | |
1268 | ||
1269 | tb1 = tb->jmp_next[n]; | |
1270 | if (tb1 != NULL) { | |
1271 | /* find head of list */ | |
1272 | for(;;) { | |
1273 | n1 = (long)tb1 & 3; | |
1274 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1275 | if (n1 == 2) | |
1276 | break; | |
1277 | tb1 = tb1->jmp_next[n1]; | |
1278 | } | |
1279 | /* we are now sure now that tb jumps to tb1 */ | |
1280 | tb_next = tb1; | |
1281 | ||
1282 | /* remove tb from the jmp_first list */ | |
1283 | ptb = &tb_next->jmp_first; | |
1284 | for(;;) { | |
1285 | tb1 = *ptb; | |
1286 | n1 = (long)tb1 & 3; | |
1287 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1288 | if (n1 == n && tb1 == tb) | |
1289 | break; | |
1290 | ptb = &tb1->jmp_next[n1]; | |
1291 | } | |
1292 | *ptb = tb->jmp_next[n]; | |
1293 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1294 | |
ea041c0e FB |
1295 | /* suppress the jump to next tb in generated code */ |
1296 | tb_reset_jump(tb, n); | |
1297 | ||
0124311e | 1298 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1299 | tb_reset_jump_recursive(tb_next); |
1300 | } | |
1301 | } | |
1302 | ||
1303 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1304 | { | |
1305 | tb_reset_jump_recursive2(tb, 0); | |
1306 | tb_reset_jump_recursive2(tb, 1); | |
1307 | } | |
1308 | ||
1fddef4b | 1309 | #if defined(TARGET_HAS_ICE) |
94df27fd PB |
1310 | #if defined(CONFIG_USER_ONLY) |
1311 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) | |
1312 | { | |
1313 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
1314 | } | |
1315 | #else | |
d720b93d FB |
1316 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1317 | { | |
c227f099 | 1318 | target_phys_addr_t addr; |
9b3c35e0 | 1319 | target_ulong pd; |
c227f099 | 1320 | ram_addr_t ram_addr; |
c2f07f81 | 1321 | PhysPageDesc *p; |
d720b93d | 1322 | |
c2f07f81 PB |
1323 | addr = cpu_get_phys_page_debug(env, pc); |
1324 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1325 | if (!p) { | |
1326 | pd = IO_MEM_UNASSIGNED; | |
1327 | } else { | |
1328 | pd = p->phys_offset; | |
1329 | } | |
1330 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1331 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1332 | } |
c27004ec | 1333 | #endif |
94df27fd | 1334 | #endif /* TARGET_HAS_ICE */ |
d720b93d | 1335 | |
6658ffb8 | 1336 | /* Add a watchpoint. */ |
a1d1bb31 AL |
1337 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
1338 | int flags, CPUWatchpoint **watchpoint) | |
6658ffb8 | 1339 | { |
b4051334 | 1340 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 1341 | CPUWatchpoint *wp; |
6658ffb8 | 1342 | |
b4051334 AL |
1343 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
1344 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1345 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1346 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1347 | return -EINVAL; | |
1348 | } | |
a1d1bb31 | 1349 | wp = qemu_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1350 | |
1351 | wp->vaddr = addr; | |
b4051334 | 1352 | wp->len_mask = len_mask; |
a1d1bb31 AL |
1353 | wp->flags = flags; |
1354 | ||
2dc9f411 | 1355 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 1356 | if (flags & BP_GDB) |
72cf2d4f | 1357 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 1358 | else |
72cf2d4f | 1359 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 1360 | |
6658ffb8 | 1361 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
1362 | |
1363 | if (watchpoint) | |
1364 | *watchpoint = wp; | |
1365 | return 0; | |
6658ffb8 PB |
1366 | } |
1367 | ||
a1d1bb31 AL |
1368 | /* Remove a specific watchpoint. */ |
1369 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1370 | int flags) | |
6658ffb8 | 1371 | { |
b4051334 | 1372 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 1373 | CPUWatchpoint *wp; |
6658ffb8 | 1374 | |
72cf2d4f | 1375 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 1376 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 1377 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 1378 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
1379 | return 0; |
1380 | } | |
1381 | } | |
a1d1bb31 | 1382 | return -ENOENT; |
6658ffb8 PB |
1383 | } |
1384 | ||
a1d1bb31 AL |
1385 | /* Remove a specific watchpoint by reference. */ |
1386 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1387 | { | |
72cf2d4f | 1388 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 1389 | |
a1d1bb31 AL |
1390 | tlb_flush_page(env, watchpoint->vaddr); |
1391 | ||
1392 | qemu_free(watchpoint); | |
1393 | } | |
1394 | ||
1395 | /* Remove all matching watchpoints. */ | |
1396 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1397 | { | |
c0ce998e | 1398 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1399 | |
72cf2d4f | 1400 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
1401 | if (wp->flags & mask) |
1402 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 1403 | } |
7d03f82f EI |
1404 | } |
1405 | ||
a1d1bb31 AL |
1406 | /* Add a breakpoint. */ |
1407 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1408 | CPUBreakpoint **breakpoint) | |
4c3a88a2 | 1409 | { |
1fddef4b | 1410 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1411 | CPUBreakpoint *bp; |
3b46e624 | 1412 | |
a1d1bb31 | 1413 | bp = qemu_malloc(sizeof(*bp)); |
4c3a88a2 | 1414 | |
a1d1bb31 AL |
1415 | bp->pc = pc; |
1416 | bp->flags = flags; | |
1417 | ||
2dc9f411 | 1418 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e | 1419 | if (flags & BP_GDB) |
72cf2d4f | 1420 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
c0ce998e | 1421 | else |
72cf2d4f | 1422 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
3b46e624 | 1423 | |
d720b93d | 1424 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
1425 | |
1426 | if (breakpoint) | |
1427 | *breakpoint = bp; | |
4c3a88a2 FB |
1428 | return 0; |
1429 | #else | |
a1d1bb31 | 1430 | return -ENOSYS; |
4c3a88a2 FB |
1431 | #endif |
1432 | } | |
1433 | ||
a1d1bb31 AL |
1434 | /* Remove a specific breakpoint. */ |
1435 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1436 | { | |
7d03f82f | 1437 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
1438 | CPUBreakpoint *bp; |
1439 | ||
72cf2d4f | 1440 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
1441 | if (bp->pc == pc && bp->flags == flags) { |
1442 | cpu_breakpoint_remove_by_ref(env, bp); | |
1443 | return 0; | |
1444 | } | |
7d03f82f | 1445 | } |
a1d1bb31 AL |
1446 | return -ENOENT; |
1447 | #else | |
1448 | return -ENOSYS; | |
7d03f82f EI |
1449 | #endif |
1450 | } | |
1451 | ||
a1d1bb31 AL |
1452 | /* Remove a specific breakpoint by reference. */ |
1453 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
4c3a88a2 | 1454 | { |
1fddef4b | 1455 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1456 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 1457 | |
a1d1bb31 AL |
1458 | breakpoint_invalidate(env, breakpoint->pc); |
1459 | ||
1460 | qemu_free(breakpoint); | |
1461 | #endif | |
1462 | } | |
1463 | ||
1464 | /* Remove all matching breakpoints. */ | |
1465 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1466 | { | |
1467 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 1468 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1469 | |
72cf2d4f | 1470 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
1471 | if (bp->flags & mask) |
1472 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 1473 | } |
4c3a88a2 FB |
1474 | #endif |
1475 | } | |
1476 | ||
c33a346e FB |
1477 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1478 | CPU loop after each instruction */ | |
1479 | void cpu_single_step(CPUState *env, int enabled) | |
1480 | { | |
1fddef4b | 1481 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1482 | if (env->singlestep_enabled != enabled) { |
1483 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
1484 | if (kvm_enabled()) |
1485 | kvm_update_guest_debug(env, 0); | |
1486 | else { | |
ccbb4d44 | 1487 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
1488 | /* XXX: only flush what is necessary */ |
1489 | tb_flush(env); | |
1490 | } | |
c33a346e FB |
1491 | } |
1492 | #endif | |
1493 | } | |
1494 | ||
34865134 FB |
1495 | /* enable or disable low levels log */ |
1496 | void cpu_set_log(int log_flags) | |
1497 | { | |
1498 | loglevel = log_flags; | |
1499 | if (loglevel && !logfile) { | |
11fcfab4 | 1500 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1501 | if (!logfile) { |
1502 | perror(logfilename); | |
1503 | _exit(1); | |
1504 | } | |
9fa3e853 FB |
1505 | #if !defined(CONFIG_SOFTMMU) |
1506 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1507 | { | |
b55266b5 | 1508 | static char logfile_buf[4096]; |
9fa3e853 FB |
1509 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1510 | } | |
bf65f53f FN |
1511 | #elif !defined(_WIN32) |
1512 | /* Win32 doesn't support line-buffering and requires size >= 2 */ | |
34865134 | 1513 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1514 | #endif |
e735b91c PB |
1515 | log_append = 1; |
1516 | } | |
1517 | if (!loglevel && logfile) { | |
1518 | fclose(logfile); | |
1519 | logfile = NULL; | |
34865134 FB |
1520 | } |
1521 | } | |
1522 | ||
1523 | void cpu_set_log_filename(const char *filename) | |
1524 | { | |
1525 | logfilename = strdup(filename); | |
e735b91c PB |
1526 | if (logfile) { |
1527 | fclose(logfile); | |
1528 | logfile = NULL; | |
1529 | } | |
1530 | cpu_set_log(loglevel); | |
34865134 | 1531 | } |
c33a346e | 1532 | |
3098dba0 | 1533 | static void cpu_unlink_tb(CPUState *env) |
ea041c0e | 1534 | { |
3098dba0 AJ |
1535 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
1536 | problem and hope the cpu will stop of its own accord. For userspace | |
1537 | emulation this often isn't actually as bad as it sounds. Often | |
1538 | signals are used primarily to interrupt blocking syscalls. */ | |
ea041c0e | 1539 | TranslationBlock *tb; |
c227f099 | 1540 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1541 | |
cab1b4bd | 1542 | spin_lock(&interrupt_lock); |
3098dba0 AJ |
1543 | tb = env->current_tb; |
1544 | /* if the cpu is currently executing code, we must unlink it and | |
1545 | all the potentially executing TB */ | |
f76cfe56 | 1546 | if (tb) { |
3098dba0 AJ |
1547 | env->current_tb = NULL; |
1548 | tb_reset_jump_recursive(tb); | |
be214e6c | 1549 | } |
cab1b4bd | 1550 | spin_unlock(&interrupt_lock); |
3098dba0 AJ |
1551 | } |
1552 | ||
1553 | /* mask must never be zero, except for A20 change call */ | |
1554 | void cpu_interrupt(CPUState *env, int mask) | |
1555 | { | |
1556 | int old_mask; | |
be214e6c | 1557 | |
2e70f6ef | 1558 | old_mask = env->interrupt_request; |
68a79315 | 1559 | env->interrupt_request |= mask; |
3098dba0 | 1560 | |
8edac960 AL |
1561 | #ifndef CONFIG_USER_ONLY |
1562 | /* | |
1563 | * If called from iothread context, wake the target cpu in | |
1564 | * case its halted. | |
1565 | */ | |
1566 | if (!qemu_cpu_self(env)) { | |
1567 | qemu_cpu_kick(env); | |
1568 | return; | |
1569 | } | |
1570 | #endif | |
1571 | ||
2e70f6ef | 1572 | if (use_icount) { |
266910c4 | 1573 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef | 1574 | #ifndef CONFIG_USER_ONLY |
2e70f6ef | 1575 | if (!can_do_io(env) |
be214e6c | 1576 | && (mask & ~old_mask) != 0) { |
2e70f6ef PB |
1577 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
1578 | } | |
1579 | #endif | |
1580 | } else { | |
3098dba0 | 1581 | cpu_unlink_tb(env); |
ea041c0e FB |
1582 | } |
1583 | } | |
1584 | ||
b54ad049 FB |
1585 | void cpu_reset_interrupt(CPUState *env, int mask) |
1586 | { | |
1587 | env->interrupt_request &= ~mask; | |
1588 | } | |
1589 | ||
3098dba0 AJ |
1590 | void cpu_exit(CPUState *env) |
1591 | { | |
1592 | env->exit_request = 1; | |
1593 | cpu_unlink_tb(env); | |
1594 | } | |
1595 | ||
c7cd6a37 | 1596 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1597 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1598 | "show generated host assembly code for each compiled TB" }, |
1599 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1600 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1601 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1602 | "show micro ops for each compiled TB" }, |
f193c797 | 1603 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1604 | "show micro ops " |
1605 | #ifdef TARGET_I386 | |
1606 | "before eflags optimization and " | |
f193c797 | 1607 | #endif |
e01a1157 | 1608 | "after liveness analysis" }, |
f193c797 FB |
1609 | { CPU_LOG_INT, "int", |
1610 | "show interrupts/exceptions in short format" }, | |
1611 | { CPU_LOG_EXEC, "exec", | |
1612 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1613 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1614 | "show CPU state before block translation" }, |
f193c797 FB |
1615 | #ifdef TARGET_I386 |
1616 | { CPU_LOG_PCALL, "pcall", | |
1617 | "show protected mode far calls/returns/exceptions" }, | |
eca1bdf4 AL |
1618 | { CPU_LOG_RESET, "cpu_reset", |
1619 | "show CPU state before CPU resets" }, | |
f193c797 | 1620 | #endif |
8e3a9fd2 | 1621 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1622 | { CPU_LOG_IOPORT, "ioport", |
1623 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1624 | #endif |
f193c797 FB |
1625 | { 0, NULL, NULL }, |
1626 | }; | |
1627 | ||
f6f3fbca MT |
1628 | #ifndef CONFIG_USER_ONLY |
1629 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list | |
1630 | = QLIST_HEAD_INITIALIZER(memory_client_list); | |
1631 | ||
1632 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, | |
1633 | ram_addr_t size, | |
1634 | ram_addr_t phys_offset) | |
1635 | { | |
1636 | CPUPhysMemoryClient *client; | |
1637 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1638 | client->set_memory(client, start_addr, size, phys_offset); | |
1639 | } | |
1640 | } | |
1641 | ||
1642 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, | |
1643 | target_phys_addr_t end) | |
1644 | { | |
1645 | CPUPhysMemoryClient *client; | |
1646 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1647 | int r = client->sync_dirty_bitmap(client, start, end); | |
1648 | if (r < 0) | |
1649 | return r; | |
1650 | } | |
1651 | return 0; | |
1652 | } | |
1653 | ||
1654 | static int cpu_notify_migration_log(int enable) | |
1655 | { | |
1656 | CPUPhysMemoryClient *client; | |
1657 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1658 | int r = client->migration_log(client, enable); | |
1659 | if (r < 0) | |
1660 | return r; | |
1661 | } | |
1662 | return 0; | |
1663 | } | |
1664 | ||
1665 | static void phys_page_for_each_in_l1_map(PhysPageDesc **phys_map, | |
1666 | CPUPhysMemoryClient *client) | |
1667 | { | |
1668 | PhysPageDesc *pd; | |
1669 | int l1, l2; | |
1670 | ||
1671 | for (l1 = 0; l1 < L1_SIZE; ++l1) { | |
1672 | pd = phys_map[l1]; | |
1673 | if (!pd) { | |
1674 | continue; | |
1675 | } | |
1676 | for (l2 = 0; l2 < L2_SIZE; ++l2) { | |
1677 | if (pd[l2].phys_offset == IO_MEM_UNASSIGNED) { | |
1678 | continue; | |
1679 | } | |
1680 | client->set_memory(client, pd[l2].region_offset, | |
1681 | TARGET_PAGE_SIZE, pd[l2].phys_offset); | |
1682 | } | |
1683 | } | |
1684 | } | |
1685 | ||
1686 | static void phys_page_for_each(CPUPhysMemoryClient *client) | |
1687 | { | |
1688 | #if TARGET_PHYS_ADDR_SPACE_BITS > 32 | |
1689 | ||
1690 | #if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS) | |
1691 | #error unsupported TARGET_PHYS_ADDR_SPACE_BITS | |
1692 | #endif | |
1693 | void **phys_map = (void **)l1_phys_map; | |
1694 | int l1; | |
1695 | if (!l1_phys_map) { | |
1696 | return; | |
1697 | } | |
1698 | for (l1 = 0; l1 < L1_SIZE; ++l1) { | |
1699 | if (phys_map[l1]) { | |
1700 | phys_page_for_each_in_l1_map(phys_map[l1], client); | |
1701 | } | |
1702 | } | |
1703 | #else | |
1704 | if (!l1_phys_map) { | |
1705 | return; | |
1706 | } | |
1707 | phys_page_for_each_in_l1_map(l1_phys_map, client); | |
1708 | #endif | |
1709 | } | |
1710 | ||
1711 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) | |
1712 | { | |
1713 | QLIST_INSERT_HEAD(&memory_client_list, client, list); | |
1714 | phys_page_for_each(client); | |
1715 | } | |
1716 | ||
1717 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) | |
1718 | { | |
1719 | QLIST_REMOVE(client, list); | |
1720 | } | |
1721 | #endif | |
1722 | ||
f193c797 FB |
1723 | static int cmp1(const char *s1, int n, const char *s2) |
1724 | { | |
1725 | if (strlen(s2) != n) | |
1726 | return 0; | |
1727 | return memcmp(s1, s2, n) == 0; | |
1728 | } | |
3b46e624 | 1729 | |
f193c797 FB |
1730 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1731 | int cpu_str_to_log_mask(const char *str) | |
1732 | { | |
c7cd6a37 | 1733 | const CPULogItem *item; |
f193c797 FB |
1734 | int mask; |
1735 | const char *p, *p1; | |
1736 | ||
1737 | p = str; | |
1738 | mask = 0; | |
1739 | for(;;) { | |
1740 | p1 = strchr(p, ','); | |
1741 | if (!p1) | |
1742 | p1 = p + strlen(p); | |
8e3a9fd2 FB |
1743 | if(cmp1(p,p1-p,"all")) { |
1744 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1745 | mask |= item->mask; | |
1746 | } | |
1747 | } else { | |
f193c797 FB |
1748 | for(item = cpu_log_items; item->mask != 0; item++) { |
1749 | if (cmp1(p, p1 - p, item->name)) | |
1750 | goto found; | |
1751 | } | |
1752 | return 0; | |
8e3a9fd2 | 1753 | } |
f193c797 FB |
1754 | found: |
1755 | mask |= item->mask; | |
1756 | if (*p1 != ',') | |
1757 | break; | |
1758 | p = p1 + 1; | |
1759 | } | |
1760 | return mask; | |
1761 | } | |
ea041c0e | 1762 | |
7501267e FB |
1763 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1764 | { | |
1765 | va_list ap; | |
493ae1f0 | 1766 | va_list ap2; |
7501267e FB |
1767 | |
1768 | va_start(ap, fmt); | |
493ae1f0 | 1769 | va_copy(ap2, ap); |
7501267e FB |
1770 | fprintf(stderr, "qemu: fatal: "); |
1771 | vfprintf(stderr, fmt, ap); | |
1772 | fprintf(stderr, "\n"); | |
1773 | #ifdef TARGET_I386 | |
7fe48483 FB |
1774 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1775 | #else | |
1776 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1777 | #endif |
93fcfe39 AL |
1778 | if (qemu_log_enabled()) { |
1779 | qemu_log("qemu: fatal: "); | |
1780 | qemu_log_vprintf(fmt, ap2); | |
1781 | qemu_log("\n"); | |
f9373291 | 1782 | #ifdef TARGET_I386 |
93fcfe39 | 1783 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
f9373291 | 1784 | #else |
93fcfe39 | 1785 | log_cpu_state(env, 0); |
f9373291 | 1786 | #endif |
31b1a7b4 | 1787 | qemu_log_flush(); |
93fcfe39 | 1788 | qemu_log_close(); |
924edcae | 1789 | } |
493ae1f0 | 1790 | va_end(ap2); |
f9373291 | 1791 | va_end(ap); |
fd052bf6 RV |
1792 | #if defined(CONFIG_USER_ONLY) |
1793 | { | |
1794 | struct sigaction act; | |
1795 | sigfillset(&act.sa_mask); | |
1796 | act.sa_handler = SIG_DFL; | |
1797 | sigaction(SIGABRT, &act, NULL); | |
1798 | } | |
1799 | #endif | |
7501267e FB |
1800 | abort(); |
1801 | } | |
1802 | ||
c5be9f08 TS |
1803 | CPUState *cpu_copy(CPUState *env) |
1804 | { | |
01ba9816 | 1805 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1806 | CPUState *next_cpu = new_env->next_cpu; |
1807 | int cpu_index = new_env->cpu_index; | |
5a38f081 AL |
1808 | #if defined(TARGET_HAS_ICE) |
1809 | CPUBreakpoint *bp; | |
1810 | CPUWatchpoint *wp; | |
1811 | #endif | |
1812 | ||
c5be9f08 | 1813 | memcpy(new_env, env, sizeof(CPUState)); |
5a38f081 AL |
1814 | |
1815 | /* Preserve chaining and index. */ | |
c5be9f08 TS |
1816 | new_env->next_cpu = next_cpu; |
1817 | new_env->cpu_index = cpu_index; | |
5a38f081 AL |
1818 | |
1819 | /* Clone all break/watchpoints. | |
1820 | Note: Once we support ptrace with hw-debug register access, make sure | |
1821 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
72cf2d4f BS |
1822 | QTAILQ_INIT(&env->breakpoints); |
1823 | QTAILQ_INIT(&env->watchpoints); | |
5a38f081 | 1824 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1825 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5a38f081 AL |
1826 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
1827 | } | |
72cf2d4f | 1828 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
5a38f081 AL |
1829 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
1830 | wp->flags, NULL); | |
1831 | } | |
1832 | #endif | |
1833 | ||
c5be9f08 TS |
1834 | return new_env; |
1835 | } | |
1836 | ||
0124311e FB |
1837 | #if !defined(CONFIG_USER_ONLY) |
1838 | ||
5c751e99 EI |
1839 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1840 | { | |
1841 | unsigned int i; | |
1842 | ||
1843 | /* Discard jump cache entries for any tb which might potentially | |
1844 | overlap the flushed page. */ | |
1845 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1846 | memset (&env->tb_jmp_cache[i], 0, | |
1847 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1848 | ||
1849 | i = tb_jmp_cache_hash_page(addr); | |
1850 | memset (&env->tb_jmp_cache[i], 0, | |
1851 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1852 | } | |
1853 | ||
08738984 IK |
1854 | static CPUTLBEntry s_cputlb_empty_entry = { |
1855 | .addr_read = -1, | |
1856 | .addr_write = -1, | |
1857 | .addr_code = -1, | |
1858 | .addend = -1, | |
1859 | }; | |
1860 | ||
ee8b7021 FB |
1861 | /* NOTE: if flush_global is true, also flush global entries (not |
1862 | implemented yet) */ | |
1863 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1864 | { |
33417e70 | 1865 | int i; |
0124311e | 1866 | |
9fa3e853 FB |
1867 | #if defined(DEBUG_TLB) |
1868 | printf("tlb_flush:\n"); | |
1869 | #endif | |
0124311e FB |
1870 | /* must reset current TB so that interrupts cannot modify the |
1871 | links while we are modifying them */ | |
1872 | env->current_tb = NULL; | |
1873 | ||
33417e70 | 1874 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
cfde4bd9 IY |
1875 | int mmu_idx; |
1876 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
08738984 | 1877 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
cfde4bd9 | 1878 | } |
33417e70 | 1879 | } |
9fa3e853 | 1880 | |
8a40a180 | 1881 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1882 | |
e3db7226 | 1883 | tlb_flush_count++; |
33417e70 FB |
1884 | } |
1885 | ||
274da6b2 | 1886 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1887 | { |
5fafdf24 | 1888 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 1889 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1890 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 1891 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1892 | addr == (tlb_entry->addr_code & |
84b7b8e7 | 1893 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
08738984 | 1894 | *tlb_entry = s_cputlb_empty_entry; |
84b7b8e7 | 1895 | } |
61382a50 FB |
1896 | } |
1897 | ||
2e12669a | 1898 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 1899 | { |
8a40a180 | 1900 | int i; |
cfde4bd9 | 1901 | int mmu_idx; |
0124311e | 1902 | |
9fa3e853 | 1903 | #if defined(DEBUG_TLB) |
108c49b8 | 1904 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 1905 | #endif |
0124311e FB |
1906 | /* must reset current TB so that interrupts cannot modify the |
1907 | links while we are modifying them */ | |
1908 | env->current_tb = NULL; | |
61382a50 FB |
1909 | |
1910 | addr &= TARGET_PAGE_MASK; | |
1911 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
cfde4bd9 IY |
1912 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
1913 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); | |
0124311e | 1914 | |
5c751e99 | 1915 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 FB |
1916 | } |
1917 | ||
9fa3e853 FB |
1918 | /* update the TLBs so that writes to code in the virtual page 'addr' |
1919 | can be detected */ | |
c227f099 | 1920 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 1921 | { |
5fafdf24 | 1922 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
1923 | ram_addr + TARGET_PAGE_SIZE, |
1924 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
1925 | } |
1926 | ||
9fa3e853 | 1927 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 1928 | tested for self modifying code */ |
c227f099 | 1929 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 1930 | target_ulong vaddr) |
9fa3e853 | 1931 | { |
3a7d929e | 1932 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG; |
1ccde1cb FB |
1933 | } |
1934 | ||
5fafdf24 | 1935 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
1936 | unsigned long start, unsigned long length) |
1937 | { | |
1938 | unsigned long addr; | |
84b7b8e7 FB |
1939 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
1940 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 1941 | if ((addr - start) < length) { |
0f459d16 | 1942 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
1943 | } |
1944 | } | |
1945 | } | |
1946 | ||
5579c7f3 | 1947 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 1948 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 1949 | int dirty_flags) |
1ccde1cb FB |
1950 | { |
1951 | CPUState *env; | |
4f2ac237 | 1952 | unsigned long length, start1; |
0a962c02 FB |
1953 | int i, mask, len; |
1954 | uint8_t *p; | |
1ccde1cb FB |
1955 | |
1956 | start &= TARGET_PAGE_MASK; | |
1957 | end = TARGET_PAGE_ALIGN(end); | |
1958 | ||
1959 | length = end - start; | |
1960 | if (length == 0) | |
1961 | return; | |
0a962c02 | 1962 | len = length >> TARGET_PAGE_BITS; |
f23db169 FB |
1963 | mask = ~dirty_flags; |
1964 | p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); | |
1965 | for(i = 0; i < len; i++) | |
1966 | p[i] &= mask; | |
1967 | ||
1ccde1cb FB |
1968 | /* we modify the TLB cache so that the dirty bit will be set again |
1969 | when accessing the range */ | |
5579c7f3 PB |
1970 | start1 = (unsigned long)qemu_get_ram_ptr(start); |
1971 | /* Chek that we don't span multiple blocks - this breaks the | |
1972 | address comparisons below. */ | |
1973 | if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1 | |
1974 | != (end - 1) - start) { | |
1975 | abort(); | |
1976 | } | |
1977 | ||
6a00d601 | 1978 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
cfde4bd9 IY |
1979 | int mmu_idx; |
1980 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
1981 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1982 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], | |
1983 | start1, length); | |
1984 | } | |
6a00d601 | 1985 | } |
1ccde1cb FB |
1986 | } |
1987 | ||
74576198 AL |
1988 | int cpu_physical_memory_set_dirty_tracking(int enable) |
1989 | { | |
f6f3fbca | 1990 | int ret = 0; |
74576198 | 1991 | in_migration = enable; |
f6f3fbca MT |
1992 | ret = cpu_notify_migration_log(!!enable); |
1993 | return ret; | |
74576198 AL |
1994 | } |
1995 | ||
1996 | int cpu_physical_memory_get_dirty_tracking(void) | |
1997 | { | |
1998 | return in_migration; | |
1999 | } | |
2000 | ||
c227f099 AL |
2001 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
2002 | target_phys_addr_t end_addr) | |
2bec46dc | 2003 | { |
7b8f3b78 | 2004 | int ret; |
151f7749 | 2005 | |
f6f3fbca | 2006 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); |
151f7749 | 2007 | return ret; |
2bec46dc AL |
2008 | } |
2009 | ||
3a7d929e FB |
2010 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
2011 | { | |
c227f099 | 2012 | ram_addr_t ram_addr; |
5579c7f3 | 2013 | void *p; |
3a7d929e | 2014 | |
84b7b8e7 | 2015 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5579c7f3 PB |
2016 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
2017 | + tlb_entry->addend); | |
2018 | ram_addr = qemu_ram_addr_from_host(p); | |
3a7d929e | 2019 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
0f459d16 | 2020 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
2021 | } |
2022 | } | |
2023 | } | |
2024 | ||
2025 | /* update the TLB according to the current state of the dirty bits */ | |
2026 | void cpu_tlb_update_dirty(CPUState *env) | |
2027 | { | |
2028 | int i; | |
cfde4bd9 IY |
2029 | int mmu_idx; |
2030 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2031 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2032 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); | |
2033 | } | |
3a7d929e FB |
2034 | } |
2035 | ||
0f459d16 | 2036 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 2037 | { |
0f459d16 PB |
2038 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
2039 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
2040 | } |
2041 | ||
0f459d16 PB |
2042 | /* update the TLB corresponding to virtual page vaddr |
2043 | so that it is no longer dirty */ | |
2044 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 2045 | { |
1ccde1cb | 2046 | int i; |
cfde4bd9 | 2047 | int mmu_idx; |
1ccde1cb | 2048 | |
0f459d16 | 2049 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 2050 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
cfde4bd9 IY |
2051 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2052 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); | |
9fa3e853 FB |
2053 | } |
2054 | ||
59817ccb FB |
2055 | /* add a new TLB entry. At most one entry for a given virtual address |
2056 | is permitted. Return 0 if OK or 2 if the page could not be mapped | |
2057 | (can only happen in non SOFTMMU mode for I/O pages or pages | |
2058 | conflicting with the host address space). */ | |
5fafdf24 | 2059 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
c227f099 | 2060 | target_phys_addr_t paddr, int prot, |
6ebbf390 | 2061 | int mmu_idx, int is_softmmu) |
9fa3e853 | 2062 | { |
92e873b9 | 2063 | PhysPageDesc *p; |
4f2ac237 | 2064 | unsigned long pd; |
9fa3e853 | 2065 | unsigned int index; |
4f2ac237 | 2066 | target_ulong address; |
0f459d16 | 2067 | target_ulong code_address; |
c227f099 | 2068 | target_phys_addr_t addend; |
9fa3e853 | 2069 | int ret; |
84b7b8e7 | 2070 | CPUTLBEntry *te; |
a1d1bb31 | 2071 | CPUWatchpoint *wp; |
c227f099 | 2072 | target_phys_addr_t iotlb; |
9fa3e853 | 2073 | |
92e873b9 | 2074 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
2075 | if (!p) { |
2076 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
2077 | } else { |
2078 | pd = p->phys_offset; | |
9fa3e853 FB |
2079 | } |
2080 | #if defined(DEBUG_TLB) | |
6ebbf390 JM |
2081 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n", |
2082 | vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd); | |
9fa3e853 FB |
2083 | #endif |
2084 | ||
2085 | ret = 0; | |
0f459d16 PB |
2086 | address = vaddr; |
2087 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
2088 | /* IO memory case (romd handled later) */ | |
2089 | address |= TLB_MMIO; | |
2090 | } | |
5579c7f3 | 2091 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
0f459d16 PB |
2092 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
2093 | /* Normal RAM. */ | |
2094 | iotlb = pd & TARGET_PAGE_MASK; | |
2095 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
2096 | iotlb |= IO_MEM_NOTDIRTY; | |
2097 | else | |
2098 | iotlb |= IO_MEM_ROM; | |
2099 | } else { | |
ccbb4d44 | 2100 | /* IO handlers are currently passed a physical address. |
0f459d16 PB |
2101 | It would be nice to pass an offset from the base address |
2102 | of that region. This would avoid having to special case RAM, | |
2103 | and avoid full address decoding in every device. | |
2104 | We can't use the high bits of pd for this because | |
2105 | IO_MEM_ROMD uses these as a ram address. */ | |
8da3ff18 PB |
2106 | iotlb = (pd & ~TARGET_PAGE_MASK); |
2107 | if (p) { | |
8da3ff18 PB |
2108 | iotlb += p->region_offset; |
2109 | } else { | |
2110 | iotlb += paddr; | |
2111 | } | |
0f459d16 PB |
2112 | } |
2113 | ||
2114 | code_address = address; | |
2115 | /* Make accesses to pages with watchpoints go via the | |
2116 | watchpoint trap routines. */ | |
72cf2d4f | 2117 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
a1d1bb31 | 2118 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
0f459d16 PB |
2119 | iotlb = io_mem_watch + paddr; |
2120 | /* TODO: The memory case can be optimized by not trapping | |
2121 | reads of pages with a write breakpoint. */ | |
2122 | address |= TLB_MMIO; | |
6658ffb8 | 2123 | } |
0f459d16 | 2124 | } |
d79acba4 | 2125 | |
0f459d16 PB |
2126 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
2127 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2128 | te = &env->tlb_table[mmu_idx][index]; | |
2129 | te->addend = addend - vaddr; | |
2130 | if (prot & PAGE_READ) { | |
2131 | te->addr_read = address; | |
2132 | } else { | |
2133 | te->addr_read = -1; | |
2134 | } | |
5c751e99 | 2135 | |
0f459d16 PB |
2136 | if (prot & PAGE_EXEC) { |
2137 | te->addr_code = code_address; | |
2138 | } else { | |
2139 | te->addr_code = -1; | |
2140 | } | |
2141 | if (prot & PAGE_WRITE) { | |
2142 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
2143 | (pd & IO_MEM_ROMD)) { | |
2144 | /* Write access calls the I/O callback. */ | |
2145 | te->addr_write = address | TLB_MMIO; | |
2146 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
2147 | !cpu_physical_memory_is_dirty(pd)) { | |
2148 | te->addr_write = address | TLB_NOTDIRTY; | |
9fa3e853 | 2149 | } else { |
0f459d16 | 2150 | te->addr_write = address; |
9fa3e853 | 2151 | } |
0f459d16 PB |
2152 | } else { |
2153 | te->addr_write = -1; | |
9fa3e853 | 2154 | } |
9fa3e853 FB |
2155 | return ret; |
2156 | } | |
2157 | ||
0124311e FB |
2158 | #else |
2159 | ||
ee8b7021 | 2160 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
2161 | { |
2162 | } | |
2163 | ||
2e12669a | 2164 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
2165 | { |
2166 | } | |
2167 | ||
5fafdf24 | 2168 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
c227f099 | 2169 | target_phys_addr_t paddr, int prot, |
6ebbf390 | 2170 | int mmu_idx, int is_softmmu) |
9fa3e853 FB |
2171 | { |
2172 | return 0; | |
2173 | } | |
0124311e | 2174 | |
edf8e2af MW |
2175 | /* |
2176 | * Walks guest process memory "regions" one by one | |
2177 | * and calls callback function 'fn' for each region. | |
2178 | */ | |
2179 | int walk_memory_regions(void *priv, | |
2180 | int (*fn)(void *, unsigned long, unsigned long, unsigned long)) | |
33417e70 | 2181 | { |
9fa3e853 | 2182 | unsigned long start, end; |
edf8e2af | 2183 | PageDesc *p = NULL; |
9fa3e853 | 2184 | int i, j, prot, prot1; |
edf8e2af | 2185 | int rc = 0; |
33417e70 | 2186 | |
edf8e2af | 2187 | start = end = -1; |
9fa3e853 | 2188 | prot = 0; |
edf8e2af MW |
2189 | |
2190 | for (i = 0; i <= L1_SIZE; i++) { | |
2191 | p = (i < L1_SIZE) ? l1_map[i] : NULL; | |
2192 | for (j = 0; j < L2_SIZE; j++) { | |
2193 | prot1 = (p == NULL) ? 0 : p[j].flags; | |
2194 | /* | |
2195 | * "region" is one continuous chunk of memory | |
2196 | * that has same protection flags set. | |
2197 | */ | |
9fa3e853 FB |
2198 | if (prot1 != prot) { |
2199 | end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS); | |
2200 | if (start != -1) { | |
edf8e2af MW |
2201 | rc = (*fn)(priv, start, end, prot); |
2202 | /* callback can stop iteration by returning != 0 */ | |
2203 | if (rc != 0) | |
2204 | return (rc); | |
9fa3e853 FB |
2205 | } |
2206 | if (prot1 != 0) | |
2207 | start = end; | |
2208 | else | |
2209 | start = -1; | |
2210 | prot = prot1; | |
2211 | } | |
edf8e2af | 2212 | if (p == NULL) |
9fa3e853 FB |
2213 | break; |
2214 | } | |
33417e70 | 2215 | } |
edf8e2af MW |
2216 | return (rc); |
2217 | } | |
2218 | ||
2219 | static int dump_region(void *priv, unsigned long start, | |
2220 | unsigned long end, unsigned long prot) | |
2221 | { | |
2222 | FILE *f = (FILE *)priv; | |
2223 | ||
2224 | (void) fprintf(f, "%08lx-%08lx %08lx %c%c%c\n", | |
2225 | start, end, end - start, | |
2226 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2227 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2228 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2229 | ||
2230 | return (0); | |
2231 | } | |
2232 | ||
2233 | /* dump memory mappings */ | |
2234 | void page_dump(FILE *f) | |
2235 | { | |
2236 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2237 | "start", "end", "size", "prot"); | |
2238 | walk_memory_regions(f, dump_region); | |
33417e70 FB |
2239 | } |
2240 | ||
53a5960a | 2241 | int page_get_flags(target_ulong address) |
33417e70 | 2242 | { |
9fa3e853 FB |
2243 | PageDesc *p; |
2244 | ||
2245 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2246 | if (!p) |
9fa3e853 FB |
2247 | return 0; |
2248 | return p->flags; | |
2249 | } | |
2250 | ||
2251 | /* modify the flags of a page and invalidate the code if | |
ccbb4d44 | 2252 | necessary. The flag PAGE_WRITE_ORG is positioned automatically |
9fa3e853 | 2253 | depending on PAGE_WRITE */ |
53a5960a | 2254 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 FB |
2255 | { |
2256 | PageDesc *p; | |
53a5960a | 2257 | target_ulong addr; |
9fa3e853 | 2258 | |
c8a706fe | 2259 | /* mmap_lock should already be held. */ |
9fa3e853 FB |
2260 | start = start & TARGET_PAGE_MASK; |
2261 | end = TARGET_PAGE_ALIGN(end); | |
2262 | if (flags & PAGE_WRITE) | |
2263 | flags |= PAGE_WRITE_ORG; | |
9fa3e853 FB |
2264 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
2265 | p = page_find_alloc(addr >> TARGET_PAGE_BITS); | |
17e2377a PB |
2266 | /* We may be called for host regions that are outside guest |
2267 | address space. */ | |
2268 | if (!p) | |
2269 | return; | |
9fa3e853 FB |
2270 | /* if the write protection is set, then we invalidate the code |
2271 | inside */ | |
5fafdf24 | 2272 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2273 | (flags & PAGE_WRITE) && |
2274 | p->first_tb) { | |
d720b93d | 2275 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2276 | } |
2277 | p->flags = flags; | |
2278 | } | |
33417e70 FB |
2279 | } |
2280 | ||
3d97b40b TS |
2281 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2282 | { | |
2283 | PageDesc *p; | |
2284 | target_ulong end; | |
2285 | target_ulong addr; | |
2286 | ||
55f280c9 AZ |
2287 | if (start + len < start) |
2288 | /* we've wrapped around */ | |
2289 | return -1; | |
2290 | ||
3d97b40b TS |
2291 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2292 | start = start & TARGET_PAGE_MASK; | |
2293 | ||
3d97b40b TS |
2294 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
2295 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2296 | if( !p ) | |
2297 | return -1; | |
2298 | if( !(p->flags & PAGE_VALID) ) | |
2299 | return -1; | |
2300 | ||
dae3270c | 2301 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2302 | return -1; |
dae3270c FB |
2303 | if (flags & PAGE_WRITE) { |
2304 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2305 | return -1; | |
2306 | /* unprotect the page if it was put read-only because it | |
2307 | contains translated code */ | |
2308 | if (!(p->flags & PAGE_WRITE)) { | |
2309 | if (!page_unprotect(addr, 0, NULL)) | |
2310 | return -1; | |
2311 | } | |
2312 | return 0; | |
2313 | } | |
3d97b40b TS |
2314 | } |
2315 | return 0; | |
2316 | } | |
2317 | ||
9fa3e853 | 2318 | /* called from signal handler: invalidate the code and unprotect the |
ccbb4d44 | 2319 | page. Return TRUE if the fault was successfully handled. */ |
53a5960a | 2320 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 FB |
2321 | { |
2322 | unsigned int page_index, prot, pindex; | |
2323 | PageDesc *p, *p1; | |
53a5960a | 2324 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2325 | |
c8a706fe PB |
2326 | /* Technically this isn't safe inside a signal handler. However we |
2327 | know this only ever happens in a synchronous SEGV handler, so in | |
2328 | practice it seems to be ok. */ | |
2329 | mmap_lock(); | |
2330 | ||
83fb7adf | 2331 | host_start = address & qemu_host_page_mask; |
9fa3e853 FB |
2332 | page_index = host_start >> TARGET_PAGE_BITS; |
2333 | p1 = page_find(page_index); | |
c8a706fe PB |
2334 | if (!p1) { |
2335 | mmap_unlock(); | |
9fa3e853 | 2336 | return 0; |
c8a706fe | 2337 | } |
83fb7adf | 2338 | host_end = host_start + qemu_host_page_size; |
9fa3e853 FB |
2339 | p = p1; |
2340 | prot = 0; | |
2341 | for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) { | |
2342 | prot |= p->flags; | |
2343 | p++; | |
2344 | } | |
2345 | /* if the page was really writable, then we change its | |
2346 | protection back to writable */ | |
2347 | if (prot & PAGE_WRITE_ORG) { | |
2348 | pindex = (address - host_start) >> TARGET_PAGE_BITS; | |
2349 | if (!(p1[pindex].flags & PAGE_WRITE)) { | |
5fafdf24 | 2350 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
9fa3e853 FB |
2351 | (prot & PAGE_BITS) | PAGE_WRITE); |
2352 | p1[pindex].flags |= PAGE_WRITE; | |
2353 | /* and since the content will be modified, we must invalidate | |
2354 | the corresponding translated code. */ | |
d720b93d | 2355 | tb_invalidate_phys_page(address, pc, puc); |
9fa3e853 FB |
2356 | #ifdef DEBUG_TB_CHECK |
2357 | tb_invalidate_check(address); | |
2358 | #endif | |
c8a706fe | 2359 | mmap_unlock(); |
9fa3e853 FB |
2360 | return 1; |
2361 | } | |
2362 | } | |
c8a706fe | 2363 | mmap_unlock(); |
9fa3e853 FB |
2364 | return 0; |
2365 | } | |
2366 | ||
6a00d601 FB |
2367 | static inline void tlb_set_dirty(CPUState *env, |
2368 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2369 | { |
2370 | } | |
9fa3e853 FB |
2371 | #endif /* defined(CONFIG_USER_ONLY) */ |
2372 | ||
e2eef170 | 2373 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 2374 | |
c04b2b78 PB |
2375 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
2376 | typedef struct subpage_t { | |
2377 | target_phys_addr_t base; | |
2378 | CPUReadMemoryFunc * const *mem_read[TARGET_PAGE_SIZE][4]; | |
2379 | CPUWriteMemoryFunc * const *mem_write[TARGET_PAGE_SIZE][4]; | |
2380 | void *opaque[TARGET_PAGE_SIZE][2][4]; | |
2381 | ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4]; | |
2382 | } subpage_t; | |
2383 | ||
c227f099 AL |
2384 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
2385 | ram_addr_t memory, ram_addr_t region_offset); | |
2386 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, | |
2387 | ram_addr_t orig_memory, ram_addr_t region_offset); | |
db7b5426 BS |
2388 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2389 | need_subpage) \ | |
2390 | do { \ | |
2391 | if (addr > start_addr) \ | |
2392 | start_addr2 = 0; \ | |
2393 | else { \ | |
2394 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2395 | if (start_addr2 > 0) \ | |
2396 | need_subpage = 1; \ | |
2397 | } \ | |
2398 | \ | |
49e9fba2 | 2399 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2400 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2401 | else { \ | |
2402 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2403 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2404 | need_subpage = 1; \ | |
2405 | } \ | |
2406 | } while (0) | |
2407 | ||
8f2498f9 MT |
2408 | /* register physical memory. |
2409 | For RAM, 'size' must be a multiple of the target page size. | |
2410 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
8da3ff18 PB |
2411 | io memory page. The address used when calling the IO function is |
2412 | the offset from the start of the region, plus region_offset. Both | |
ccbb4d44 | 2413 | start_addr and region_offset are rounded down to a page boundary |
8da3ff18 PB |
2414 | before calculating this offset. This should not be a problem unless |
2415 | the low bits of start_addr and region_offset differ. */ | |
c227f099 AL |
2416 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
2417 | ram_addr_t size, | |
2418 | ram_addr_t phys_offset, | |
2419 | ram_addr_t region_offset) | |
33417e70 | 2420 | { |
c227f099 | 2421 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2422 | PhysPageDesc *p; |
9d42037b | 2423 | CPUState *env; |
c227f099 | 2424 | ram_addr_t orig_size = size; |
db7b5426 | 2425 | void *subpage; |
33417e70 | 2426 | |
f6f3fbca MT |
2427 | cpu_notify_set_memory(start_addr, size, phys_offset); |
2428 | ||
67c4d23c PB |
2429 | if (phys_offset == IO_MEM_UNASSIGNED) { |
2430 | region_offset = start_addr; | |
2431 | } | |
8da3ff18 | 2432 | region_offset &= TARGET_PAGE_MASK; |
5fd386f6 | 2433 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
c227f099 | 2434 | end_addr = start_addr + (target_phys_addr_t)size; |
49e9fba2 | 2435 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { |
db7b5426 BS |
2436 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2437 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
c227f099 AL |
2438 | ram_addr_t orig_memory = p->phys_offset; |
2439 | target_phys_addr_t start_addr2, end_addr2; | |
db7b5426 BS |
2440 | int need_subpage = 0; |
2441 | ||
2442 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2443 | need_subpage); | |
4254fab8 | 2444 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 BS |
2445 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2446 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
8da3ff18 PB |
2447 | &p->phys_offset, orig_memory, |
2448 | p->region_offset); | |
db7b5426 BS |
2449 | } else { |
2450 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2451 | >> IO_MEM_SHIFT]; | |
2452 | } | |
8da3ff18 PB |
2453 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
2454 | region_offset); | |
2455 | p->region_offset = 0; | |
db7b5426 BS |
2456 | } else { |
2457 | p->phys_offset = phys_offset; | |
2458 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2459 | (phys_offset & IO_MEM_ROMD)) | |
2460 | phys_offset += TARGET_PAGE_SIZE; | |
2461 | } | |
2462 | } else { | |
2463 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2464 | p->phys_offset = phys_offset; | |
8da3ff18 | 2465 | p->region_offset = region_offset; |
db7b5426 | 2466 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
8da3ff18 | 2467 | (phys_offset & IO_MEM_ROMD)) { |
db7b5426 | 2468 | phys_offset += TARGET_PAGE_SIZE; |
0e8f0967 | 2469 | } else { |
c227f099 | 2470 | target_phys_addr_t start_addr2, end_addr2; |
db7b5426 BS |
2471 | int need_subpage = 0; |
2472 | ||
2473 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2474 | end_addr2, need_subpage); | |
2475 | ||
4254fab8 | 2476 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 | 2477 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
8da3ff18 | 2478 | &p->phys_offset, IO_MEM_UNASSIGNED, |
67c4d23c | 2479 | addr & TARGET_PAGE_MASK); |
db7b5426 | 2480 | subpage_register(subpage, start_addr2, end_addr2, |
8da3ff18 PB |
2481 | phys_offset, region_offset); |
2482 | p->region_offset = 0; | |
db7b5426 BS |
2483 | } |
2484 | } | |
2485 | } | |
8da3ff18 | 2486 | region_offset += TARGET_PAGE_SIZE; |
33417e70 | 2487 | } |
3b46e624 | 2488 | |
9d42037b FB |
2489 | /* since each CPU stores ram addresses in its TLB cache, we must |
2490 | reset the modified entries */ | |
2491 | /* XXX: slow ! */ | |
2492 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2493 | tlb_flush(env, 1); | |
2494 | } | |
33417e70 FB |
2495 | } |
2496 | ||
ba863458 | 2497 | /* XXX: temporary until new memory mapping API */ |
c227f099 | 2498 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2499 | { |
2500 | PhysPageDesc *p; | |
2501 | ||
2502 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2503 | if (!p) | |
2504 | return IO_MEM_UNASSIGNED; | |
2505 | return p->phys_offset; | |
2506 | } | |
2507 | ||
c227f099 | 2508 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2509 | { |
2510 | if (kvm_enabled()) | |
2511 | kvm_coalesce_mmio_region(addr, size); | |
2512 | } | |
2513 | ||
c227f099 | 2514 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2515 | { |
2516 | if (kvm_enabled()) | |
2517 | kvm_uncoalesce_mmio_region(addr, size); | |
2518 | } | |
2519 | ||
62a2744c SY |
2520 | void qemu_flush_coalesced_mmio_buffer(void) |
2521 | { | |
2522 | if (kvm_enabled()) | |
2523 | kvm_flush_coalesced_mmio_buffer(); | |
2524 | } | |
2525 | ||
c227f099 | 2526 | ram_addr_t qemu_ram_alloc(ram_addr_t size) |
94a6b54f PB |
2527 | { |
2528 | RAMBlock *new_block; | |
2529 | ||
94a6b54f PB |
2530 | size = TARGET_PAGE_ALIGN(size); |
2531 | new_block = qemu_malloc(sizeof(*new_block)); | |
2532 | ||
6b02494d AG |
2533 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
2534 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */ | |
2535 | new_block->host = mmap((void*)0x1000000, size, PROT_EXEC|PROT_READ|PROT_WRITE, | |
2536 | MAP_SHARED | MAP_ANONYMOUS, -1, 0); | |
2537 | #else | |
94a6b54f | 2538 | new_block->host = qemu_vmalloc(size); |
6b02494d | 2539 | #endif |
ccb167e9 IE |
2540 | #ifdef MADV_MERGEABLE |
2541 | madvise(new_block->host, size, MADV_MERGEABLE); | |
2542 | #endif | |
94a6b54f PB |
2543 | new_block->offset = last_ram_offset; |
2544 | new_block->length = size; | |
2545 | ||
2546 | new_block->next = ram_blocks; | |
2547 | ram_blocks = new_block; | |
2548 | ||
2549 | phys_ram_dirty = qemu_realloc(phys_ram_dirty, | |
2550 | (last_ram_offset + size) >> TARGET_PAGE_BITS); | |
2551 | memset(phys_ram_dirty + (last_ram_offset >> TARGET_PAGE_BITS), | |
2552 | 0xff, size >> TARGET_PAGE_BITS); | |
2553 | ||
2554 | last_ram_offset += size; | |
2555 | ||
6f0437e8 JK |
2556 | if (kvm_enabled()) |
2557 | kvm_setup_guest_memory(new_block->host, size); | |
2558 | ||
94a6b54f PB |
2559 | return new_block->offset; |
2560 | } | |
e9a1ab19 | 2561 | |
c227f099 | 2562 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 2563 | { |
94a6b54f | 2564 | /* TODO: implement this. */ |
e9a1ab19 FB |
2565 | } |
2566 | ||
dc828ca1 | 2567 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
5579c7f3 PB |
2568 | With the exception of the softmmu code in this file, this should |
2569 | only be used for local memory (e.g. video ram) that the device owns, | |
2570 | and knows it isn't going to access beyond the end of the block. | |
2571 | ||
2572 | It should not be used for general purpose DMA. | |
2573 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
2574 | */ | |
c227f099 | 2575 | void *qemu_get_ram_ptr(ram_addr_t addr) |
dc828ca1 | 2576 | { |
94a6b54f PB |
2577 | RAMBlock *prev; |
2578 | RAMBlock **prevp; | |
2579 | RAMBlock *block; | |
2580 | ||
94a6b54f PB |
2581 | prev = NULL; |
2582 | prevp = &ram_blocks; | |
2583 | block = ram_blocks; | |
2584 | while (block && (block->offset > addr | |
2585 | || block->offset + block->length <= addr)) { | |
2586 | if (prev) | |
2587 | prevp = &prev->next; | |
2588 | prev = block; | |
2589 | block = block->next; | |
2590 | } | |
2591 | if (!block) { | |
2592 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
2593 | abort(); | |
2594 | } | |
2595 | /* Move this entry to to start of the list. */ | |
2596 | if (prev) { | |
2597 | prev->next = block->next; | |
2598 | block->next = *prevp; | |
2599 | *prevp = block; | |
2600 | } | |
2601 | return block->host + (addr - block->offset); | |
dc828ca1 PB |
2602 | } |
2603 | ||
5579c7f3 PB |
2604 | /* Some of the softmmu routines need to translate from a host pointer |
2605 | (typically a TLB entry) back to a ram offset. */ | |
c227f099 | 2606 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
5579c7f3 | 2607 | { |
94a6b54f | 2608 | RAMBlock *prev; |
94a6b54f PB |
2609 | RAMBlock *block; |
2610 | uint8_t *host = ptr; | |
2611 | ||
94a6b54f | 2612 | prev = NULL; |
94a6b54f PB |
2613 | block = ram_blocks; |
2614 | while (block && (block->host > host | |
2615 | || block->host + block->length <= host)) { | |
94a6b54f PB |
2616 | prev = block; |
2617 | block = block->next; | |
2618 | } | |
2619 | if (!block) { | |
2620 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
2621 | abort(); | |
2622 | } | |
2623 | return block->offset + (host - block->host); | |
5579c7f3 PB |
2624 | } |
2625 | ||
c227f099 | 2626 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 2627 | { |
67d3b957 | 2628 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2629 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 | 2630 | #endif |
faed1c2a | 2631 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2632 | do_unassigned_access(addr, 0, 0, 0, 1); |
2633 | #endif | |
2634 | return 0; | |
2635 | } | |
2636 | ||
c227f099 | 2637 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2638 | { |
2639 | #ifdef DEBUG_UNASSIGNED | |
2640 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2641 | #endif | |
faed1c2a | 2642 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2643 | do_unassigned_access(addr, 0, 0, 0, 2); |
2644 | #endif | |
2645 | return 0; | |
2646 | } | |
2647 | ||
c227f099 | 2648 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2649 | { |
2650 | #ifdef DEBUG_UNASSIGNED | |
2651 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2652 | #endif | |
faed1c2a | 2653 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 2654 | do_unassigned_access(addr, 0, 0, 0, 4); |
67d3b957 | 2655 | #endif |
33417e70 FB |
2656 | return 0; |
2657 | } | |
2658 | ||
c227f099 | 2659 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 2660 | { |
67d3b957 | 2661 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2662 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 2663 | #endif |
faed1c2a | 2664 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2665 | do_unassigned_access(addr, 1, 0, 0, 1); |
2666 | #endif | |
2667 | } | |
2668 | ||
c227f099 | 2669 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
2670 | { |
2671 | #ifdef DEBUG_UNASSIGNED | |
2672 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2673 | #endif | |
faed1c2a | 2674 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2675 | do_unassigned_access(addr, 1, 0, 0, 2); |
2676 | #endif | |
2677 | } | |
2678 | ||
c227f099 | 2679 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
2680 | { |
2681 | #ifdef DEBUG_UNASSIGNED | |
2682 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2683 | #endif | |
faed1c2a | 2684 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 2685 | do_unassigned_access(addr, 1, 0, 0, 4); |
b4f0a316 | 2686 | #endif |
33417e70 FB |
2687 | } |
2688 | ||
d60efc6b | 2689 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
33417e70 | 2690 | unassigned_mem_readb, |
e18231a3 BS |
2691 | unassigned_mem_readw, |
2692 | unassigned_mem_readl, | |
33417e70 FB |
2693 | }; |
2694 | ||
d60efc6b | 2695 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
33417e70 | 2696 | unassigned_mem_writeb, |
e18231a3 BS |
2697 | unassigned_mem_writew, |
2698 | unassigned_mem_writel, | |
33417e70 FB |
2699 | }; |
2700 | ||
c227f099 | 2701 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2702 | uint32_t val) |
9fa3e853 | 2703 | { |
3a7d929e | 2704 | int dirty_flags; |
3a7d929e FB |
2705 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2706 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2707 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2708 | tb_invalidate_phys_page_fast(ram_addr, 1); |
2709 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2710 | #endif |
3a7d929e | 2711 | } |
5579c7f3 | 2712 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 FB |
2713 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2714 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2715 | /* we remove the notdirty callback only if the code has been | |
2716 | flushed */ | |
2717 | if (dirty_flags == 0xff) | |
2e70f6ef | 2718 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2719 | } |
2720 | ||
c227f099 | 2721 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2722 | uint32_t val) |
9fa3e853 | 2723 | { |
3a7d929e | 2724 | int dirty_flags; |
3a7d929e FB |
2725 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2726 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2727 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2728 | tb_invalidate_phys_page_fast(ram_addr, 2); |
2729 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2730 | #endif |
3a7d929e | 2731 | } |
5579c7f3 | 2732 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 FB |
2733 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2734 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2735 | /* we remove the notdirty callback only if the code has been | |
2736 | flushed */ | |
2737 | if (dirty_flags == 0xff) | |
2e70f6ef | 2738 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2739 | } |
2740 | ||
c227f099 | 2741 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2742 | uint32_t val) |
9fa3e853 | 2743 | { |
3a7d929e | 2744 | int dirty_flags; |
3a7d929e FB |
2745 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2746 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2747 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2748 | tb_invalidate_phys_page_fast(ram_addr, 4); |
2749 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2750 | #endif |
3a7d929e | 2751 | } |
5579c7f3 | 2752 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 FB |
2753 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2754 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2755 | /* we remove the notdirty callback only if the code has been | |
2756 | flushed */ | |
2757 | if (dirty_flags == 0xff) | |
2e70f6ef | 2758 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2759 | } |
2760 | ||
d60efc6b | 2761 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
9fa3e853 FB |
2762 | NULL, /* never used */ |
2763 | NULL, /* never used */ | |
2764 | NULL, /* never used */ | |
2765 | }; | |
2766 | ||
d60efc6b | 2767 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
1ccde1cb FB |
2768 | notdirty_mem_writeb, |
2769 | notdirty_mem_writew, | |
2770 | notdirty_mem_writel, | |
2771 | }; | |
2772 | ||
0f459d16 | 2773 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 2774 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 PB |
2775 | { |
2776 | CPUState *env = cpu_single_env; | |
06d55cc1 AL |
2777 | target_ulong pc, cs_base; |
2778 | TranslationBlock *tb; | |
0f459d16 | 2779 | target_ulong vaddr; |
a1d1bb31 | 2780 | CPUWatchpoint *wp; |
06d55cc1 | 2781 | int cpu_flags; |
0f459d16 | 2782 | |
06d55cc1 AL |
2783 | if (env->watchpoint_hit) { |
2784 | /* We re-entered the check after replacing the TB. Now raise | |
2785 | * the debug interrupt so that is will trigger after the | |
2786 | * current instruction. */ | |
2787 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
2788 | return; | |
2789 | } | |
2e70f6ef | 2790 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 2791 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
2792 | if ((vaddr == (wp->vaddr & len_mask) || |
2793 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
2794 | wp->flags |= BP_WATCHPOINT_HIT; |
2795 | if (!env->watchpoint_hit) { | |
2796 | env->watchpoint_hit = wp; | |
2797 | tb = tb_find_pc(env->mem_io_pc); | |
2798 | if (!tb) { | |
2799 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
2800 | "pc=%p", (void *)env->mem_io_pc); | |
2801 | } | |
2802 | cpu_restore_state(tb, env, env->mem_io_pc, NULL); | |
2803 | tb_phys_invalidate(tb, -1); | |
2804 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
2805 | env->exception_index = EXCP_DEBUG; | |
2806 | } else { | |
2807 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
2808 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
2809 | } | |
2810 | cpu_resume_from_signal(env, NULL); | |
06d55cc1 | 2811 | } |
6e140f28 AL |
2812 | } else { |
2813 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
2814 | } |
2815 | } | |
2816 | } | |
2817 | ||
6658ffb8 PB |
2818 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
2819 | so these check for a hit then pass through to the normal out-of-line | |
2820 | phys routines. */ | |
c227f099 | 2821 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 2822 | { |
b4051334 | 2823 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
6658ffb8 PB |
2824 | return ldub_phys(addr); |
2825 | } | |
2826 | ||
c227f099 | 2827 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 2828 | { |
b4051334 | 2829 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
6658ffb8 PB |
2830 | return lduw_phys(addr); |
2831 | } | |
2832 | ||
c227f099 | 2833 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 2834 | { |
b4051334 | 2835 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
6658ffb8 PB |
2836 | return ldl_phys(addr); |
2837 | } | |
2838 | ||
c227f099 | 2839 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
2840 | uint32_t val) |
2841 | { | |
b4051334 | 2842 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
6658ffb8 PB |
2843 | stb_phys(addr, val); |
2844 | } | |
2845 | ||
c227f099 | 2846 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
2847 | uint32_t val) |
2848 | { | |
b4051334 | 2849 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
6658ffb8 PB |
2850 | stw_phys(addr, val); |
2851 | } | |
2852 | ||
c227f099 | 2853 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
2854 | uint32_t val) |
2855 | { | |
b4051334 | 2856 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
6658ffb8 PB |
2857 | stl_phys(addr, val); |
2858 | } | |
2859 | ||
d60efc6b | 2860 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
6658ffb8 PB |
2861 | watch_mem_readb, |
2862 | watch_mem_readw, | |
2863 | watch_mem_readl, | |
2864 | }; | |
2865 | ||
d60efc6b | 2866 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
6658ffb8 PB |
2867 | watch_mem_writeb, |
2868 | watch_mem_writew, | |
2869 | watch_mem_writel, | |
2870 | }; | |
6658ffb8 | 2871 | |
c227f099 | 2872 | static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr, |
db7b5426 BS |
2873 | unsigned int len) |
2874 | { | |
db7b5426 BS |
2875 | uint32_t ret; |
2876 | unsigned int idx; | |
2877 | ||
8da3ff18 | 2878 | idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
2879 | #if defined(DEBUG_SUBPAGE) |
2880 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
2881 | mmio, len, addr, idx); | |
2882 | #endif | |
8da3ff18 PB |
2883 | ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], |
2884 | addr + mmio->region_offset[idx][0][len]); | |
db7b5426 BS |
2885 | |
2886 | return ret; | |
2887 | } | |
2888 | ||
c227f099 | 2889 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
db7b5426 BS |
2890 | uint32_t value, unsigned int len) |
2891 | { | |
db7b5426 BS |
2892 | unsigned int idx; |
2893 | ||
8da3ff18 | 2894 | idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
2895 | #if defined(DEBUG_SUBPAGE) |
2896 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__, | |
2897 | mmio, len, addr, idx, value); | |
2898 | #endif | |
8da3ff18 PB |
2899 | (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], |
2900 | addr + mmio->region_offset[idx][1][len], | |
2901 | value); | |
db7b5426 BS |
2902 | } |
2903 | ||
c227f099 | 2904 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
db7b5426 BS |
2905 | { |
2906 | #if defined(DEBUG_SUBPAGE) | |
2907 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2908 | #endif | |
2909 | ||
2910 | return subpage_readlen(opaque, addr, 0); | |
2911 | } | |
2912 | ||
c227f099 | 2913 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
2914 | uint32_t value) |
2915 | { | |
2916 | #if defined(DEBUG_SUBPAGE) | |
2917 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2918 | #endif | |
2919 | subpage_writelen(opaque, addr, value, 0); | |
2920 | } | |
2921 | ||
c227f099 | 2922 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
db7b5426 BS |
2923 | { |
2924 | #if defined(DEBUG_SUBPAGE) | |
2925 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2926 | #endif | |
2927 | ||
2928 | return subpage_readlen(opaque, addr, 1); | |
2929 | } | |
2930 | ||
c227f099 | 2931 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
2932 | uint32_t value) |
2933 | { | |
2934 | #if defined(DEBUG_SUBPAGE) | |
2935 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2936 | #endif | |
2937 | subpage_writelen(opaque, addr, value, 1); | |
2938 | } | |
2939 | ||
c227f099 | 2940 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
db7b5426 BS |
2941 | { |
2942 | #if defined(DEBUG_SUBPAGE) | |
2943 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2944 | #endif | |
2945 | ||
2946 | return subpage_readlen(opaque, addr, 2); | |
2947 | } | |
2948 | ||
2949 | static void subpage_writel (void *opaque, | |
c227f099 | 2950 | target_phys_addr_t addr, uint32_t value) |
db7b5426 BS |
2951 | { |
2952 | #if defined(DEBUG_SUBPAGE) | |
2953 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2954 | #endif | |
2955 | subpage_writelen(opaque, addr, value, 2); | |
2956 | } | |
2957 | ||
d60efc6b | 2958 | static CPUReadMemoryFunc * const subpage_read[] = { |
db7b5426 BS |
2959 | &subpage_readb, |
2960 | &subpage_readw, | |
2961 | &subpage_readl, | |
2962 | }; | |
2963 | ||
d60efc6b | 2964 | static CPUWriteMemoryFunc * const subpage_write[] = { |
db7b5426 BS |
2965 | &subpage_writeb, |
2966 | &subpage_writew, | |
2967 | &subpage_writel, | |
2968 | }; | |
2969 | ||
c227f099 AL |
2970 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
2971 | ram_addr_t memory, ram_addr_t region_offset) | |
db7b5426 BS |
2972 | { |
2973 | int idx, eidx; | |
4254fab8 | 2974 | unsigned int i; |
db7b5426 BS |
2975 | |
2976 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2977 | return -1; | |
2978 | idx = SUBPAGE_IDX(start); | |
2979 | eidx = SUBPAGE_IDX(end); | |
2980 | #if defined(DEBUG_SUBPAGE) | |
0bf9e31a | 2981 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
db7b5426 BS |
2982 | mmio, start, end, idx, eidx, memory); |
2983 | #endif | |
2984 | memory >>= IO_MEM_SHIFT; | |
2985 | for (; idx <= eidx; idx++) { | |
4254fab8 | 2986 | for (i = 0; i < 4; i++) { |
3ee89922 BS |
2987 | if (io_mem_read[memory][i]) { |
2988 | mmio->mem_read[idx][i] = &io_mem_read[memory][i]; | |
2989 | mmio->opaque[idx][0][i] = io_mem_opaque[memory]; | |
8da3ff18 | 2990 | mmio->region_offset[idx][0][i] = region_offset; |
3ee89922 BS |
2991 | } |
2992 | if (io_mem_write[memory][i]) { | |
2993 | mmio->mem_write[idx][i] = &io_mem_write[memory][i]; | |
2994 | mmio->opaque[idx][1][i] = io_mem_opaque[memory]; | |
8da3ff18 | 2995 | mmio->region_offset[idx][1][i] = region_offset; |
3ee89922 | 2996 | } |
4254fab8 | 2997 | } |
db7b5426 BS |
2998 | } |
2999 | ||
3000 | return 0; | |
3001 | } | |
3002 | ||
c227f099 AL |
3003 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
3004 | ram_addr_t orig_memory, ram_addr_t region_offset) | |
db7b5426 | 3005 | { |
c227f099 | 3006 | subpage_t *mmio; |
db7b5426 BS |
3007 | int subpage_memory; |
3008 | ||
c227f099 | 3009 | mmio = qemu_mallocz(sizeof(subpage_t)); |
1eec614b AL |
3010 | |
3011 | mmio->base = base; | |
1eed09cb | 3012 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio); |
db7b5426 | 3013 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
3014 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
3015 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 3016 | #endif |
1eec614b AL |
3017 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
3018 | subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory, | |
8da3ff18 | 3019 | region_offset); |
db7b5426 BS |
3020 | |
3021 | return mmio; | |
3022 | } | |
3023 | ||
88715657 AL |
3024 | static int get_free_io_mem_idx(void) |
3025 | { | |
3026 | int i; | |
3027 | ||
3028 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
3029 | if (!io_mem_used[i]) { | |
3030 | io_mem_used[i] = 1; | |
3031 | return i; | |
3032 | } | |
c6703b47 | 3033 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
88715657 AL |
3034 | return -1; |
3035 | } | |
3036 | ||
33417e70 FB |
3037 | /* mem_read and mem_write are arrays of functions containing the |
3038 | function to access byte (index 0), word (index 1) and dword (index | |
0b4e6e3e | 3039 | 2). Functions can be omitted with a NULL function pointer. |
3ee89922 | 3040 | If io_index is non zero, the corresponding io zone is |
4254fab8 BS |
3041 | modified. If it is zero, a new io zone is allocated. The return |
3042 | value can be used with cpu_register_physical_memory(). (-1) is | |
3043 | returned if error. */ | |
1eed09cb | 3044 | static int cpu_register_io_memory_fixed(int io_index, |
d60efc6b BS |
3045 | CPUReadMemoryFunc * const *mem_read, |
3046 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb | 3047 | void *opaque) |
33417e70 | 3048 | { |
4254fab8 | 3049 | int i, subwidth = 0; |
33417e70 FB |
3050 | |
3051 | if (io_index <= 0) { | |
88715657 AL |
3052 | io_index = get_free_io_mem_idx(); |
3053 | if (io_index == -1) | |
3054 | return io_index; | |
33417e70 | 3055 | } else { |
1eed09cb | 3056 | io_index >>= IO_MEM_SHIFT; |
33417e70 FB |
3057 | if (io_index >= IO_MEM_NB_ENTRIES) |
3058 | return -1; | |
3059 | } | |
b5ff1b31 | 3060 | |
33417e70 | 3061 | for(i = 0;i < 3; i++) { |
4254fab8 BS |
3062 | if (!mem_read[i] || !mem_write[i]) |
3063 | subwidth = IO_MEM_SUBWIDTH; | |
33417e70 FB |
3064 | io_mem_read[io_index][i] = mem_read[i]; |
3065 | io_mem_write[io_index][i] = mem_write[i]; | |
3066 | } | |
a4193c8a | 3067 | io_mem_opaque[io_index] = opaque; |
4254fab8 | 3068 | return (io_index << IO_MEM_SHIFT) | subwidth; |
33417e70 | 3069 | } |
61382a50 | 3070 | |
d60efc6b BS |
3071 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
3072 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb AK |
3073 | void *opaque) |
3074 | { | |
3075 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque); | |
3076 | } | |
3077 | ||
88715657 AL |
3078 | void cpu_unregister_io_memory(int io_table_address) |
3079 | { | |
3080 | int i; | |
3081 | int io_index = io_table_address >> IO_MEM_SHIFT; | |
3082 | ||
3083 | for (i=0;i < 3; i++) { | |
3084 | io_mem_read[io_index][i] = unassigned_mem_read[i]; | |
3085 | io_mem_write[io_index][i] = unassigned_mem_write[i]; | |
3086 | } | |
3087 | io_mem_opaque[io_index] = NULL; | |
3088 | io_mem_used[io_index] = 0; | |
3089 | } | |
3090 | ||
e9179ce1 AK |
3091 | static void io_mem_init(void) |
3092 | { | |
3093 | int i; | |
3094 | ||
3095 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL); | |
3096 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL); | |
3097 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL); | |
3098 | for (i=0; i<5; i++) | |
3099 | io_mem_used[i] = 1; | |
3100 | ||
3101 | io_mem_watch = cpu_register_io_memory(watch_mem_read, | |
3102 | watch_mem_write, NULL); | |
e9179ce1 AK |
3103 | } |
3104 | ||
e2eef170 PB |
3105 | #endif /* !defined(CONFIG_USER_ONLY) */ |
3106 | ||
13eb76e0 FB |
3107 | /* physical memory access (slow version, mainly for debug) */ |
3108 | #if defined(CONFIG_USER_ONLY) | |
a68fe89c PB |
3109 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
3110 | uint8_t *buf, int len, int is_write) | |
13eb76e0 FB |
3111 | { |
3112 | int l, flags; | |
3113 | target_ulong page; | |
53a5960a | 3114 | void * p; |
13eb76e0 FB |
3115 | |
3116 | while (len > 0) { | |
3117 | page = addr & TARGET_PAGE_MASK; | |
3118 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3119 | if (l > len) | |
3120 | l = len; | |
3121 | flags = page_get_flags(page); | |
3122 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 3123 | return -1; |
13eb76e0 FB |
3124 | if (is_write) { |
3125 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 3126 | return -1; |
579a97f7 | 3127 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3128 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 3129 | return -1; |
72fb7daa AJ |
3130 | memcpy(p, buf, l); |
3131 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3132 | } else { |
3133 | if (!(flags & PAGE_READ)) | |
a68fe89c | 3134 | return -1; |
579a97f7 | 3135 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3136 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 3137 | return -1; |
72fb7daa | 3138 | memcpy(buf, p, l); |
5b257578 | 3139 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3140 | } |
3141 | len -= l; | |
3142 | buf += l; | |
3143 | addr += l; | |
3144 | } | |
a68fe89c | 3145 | return 0; |
13eb76e0 | 3146 | } |
8df1cd07 | 3147 | |
13eb76e0 | 3148 | #else |
c227f099 | 3149 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3150 | int len, int is_write) |
3151 | { | |
3152 | int l, io_index; | |
3153 | uint8_t *ptr; | |
3154 | uint32_t val; | |
c227f099 | 3155 | target_phys_addr_t page; |
2e12669a | 3156 | unsigned long pd; |
92e873b9 | 3157 | PhysPageDesc *p; |
3b46e624 | 3158 | |
13eb76e0 FB |
3159 | while (len > 0) { |
3160 | page = addr & TARGET_PAGE_MASK; | |
3161 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3162 | if (l > len) | |
3163 | l = len; | |
92e873b9 | 3164 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
3165 | if (!p) { |
3166 | pd = IO_MEM_UNASSIGNED; | |
3167 | } else { | |
3168 | pd = p->phys_offset; | |
3169 | } | |
3b46e624 | 3170 | |
13eb76e0 | 3171 | if (is_write) { |
3a7d929e | 3172 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
c227f099 | 3173 | target_phys_addr_t addr1 = addr; |
13eb76e0 | 3174 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 | 3175 | if (p) |
6c2934db | 3176 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
6a00d601 FB |
3177 | /* XXX: could force cpu_single_env to NULL to avoid |
3178 | potential bugs */ | |
6c2934db | 3179 | if (l >= 4 && ((addr1 & 3) == 0)) { |
1c213d19 | 3180 | /* 32 bit write access */ |
c27004ec | 3181 | val = ldl_p(buf); |
6c2934db | 3182 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
13eb76e0 | 3183 | l = 4; |
6c2934db | 3184 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
1c213d19 | 3185 | /* 16 bit write access */ |
c27004ec | 3186 | val = lduw_p(buf); |
6c2934db | 3187 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3188 | l = 2; |
3189 | } else { | |
1c213d19 | 3190 | /* 8 bit write access */ |
c27004ec | 3191 | val = ldub_p(buf); |
6c2934db | 3192 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3193 | l = 1; |
3194 | } | |
3195 | } else { | |
b448f2f3 FB |
3196 | unsigned long addr1; |
3197 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 3198 | /* RAM case */ |
5579c7f3 | 3199 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 3200 | memcpy(ptr, buf, l); |
3a7d929e FB |
3201 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3202 | /* invalidate code */ | |
3203 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3204 | /* set dirty bit */ | |
5fafdf24 | 3205 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
f23db169 | 3206 | (0xff & ~CODE_DIRTY_FLAG); |
3a7d929e | 3207 | } |
13eb76e0 FB |
3208 | } |
3209 | } else { | |
5fafdf24 | 3210 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3211 | !(pd & IO_MEM_ROMD)) { |
c227f099 | 3212 | target_phys_addr_t addr1 = addr; |
13eb76e0 FB |
3213 | /* I/O case */ |
3214 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 | 3215 | if (p) |
6c2934db AJ |
3216 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
3217 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
13eb76e0 | 3218 | /* 32 bit read access */ |
6c2934db | 3219 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
c27004ec | 3220 | stl_p(buf, val); |
13eb76e0 | 3221 | l = 4; |
6c2934db | 3222 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
13eb76e0 | 3223 | /* 16 bit read access */ |
6c2934db | 3224 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
c27004ec | 3225 | stw_p(buf, val); |
13eb76e0 FB |
3226 | l = 2; |
3227 | } else { | |
1c213d19 | 3228 | /* 8 bit read access */ |
6c2934db | 3229 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
c27004ec | 3230 | stb_p(buf, val); |
13eb76e0 FB |
3231 | l = 1; |
3232 | } | |
3233 | } else { | |
3234 | /* RAM case */ | |
5579c7f3 | 3235 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
13eb76e0 FB |
3236 | (addr & ~TARGET_PAGE_MASK); |
3237 | memcpy(buf, ptr, l); | |
3238 | } | |
3239 | } | |
3240 | len -= l; | |
3241 | buf += l; | |
3242 | addr += l; | |
3243 | } | |
3244 | } | |
8df1cd07 | 3245 | |
d0ecd2aa | 3246 | /* used for ROM loading : can write in RAM and ROM */ |
c227f099 | 3247 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
3248 | const uint8_t *buf, int len) |
3249 | { | |
3250 | int l; | |
3251 | uint8_t *ptr; | |
c227f099 | 3252 | target_phys_addr_t page; |
d0ecd2aa FB |
3253 | unsigned long pd; |
3254 | PhysPageDesc *p; | |
3b46e624 | 3255 | |
d0ecd2aa FB |
3256 | while (len > 0) { |
3257 | page = addr & TARGET_PAGE_MASK; | |
3258 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3259 | if (l > len) | |
3260 | l = len; | |
3261 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3262 | if (!p) { | |
3263 | pd = IO_MEM_UNASSIGNED; | |
3264 | } else { | |
3265 | pd = p->phys_offset; | |
3266 | } | |
3b46e624 | 3267 | |
d0ecd2aa | 3268 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
3269 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
3270 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
3271 | /* do nothing */ |
3272 | } else { | |
3273 | unsigned long addr1; | |
3274 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3275 | /* ROM/RAM case */ | |
5579c7f3 | 3276 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa FB |
3277 | memcpy(ptr, buf, l); |
3278 | } | |
3279 | len -= l; | |
3280 | buf += l; | |
3281 | addr += l; | |
3282 | } | |
3283 | } | |
3284 | ||
6d16c2f8 AL |
3285 | typedef struct { |
3286 | void *buffer; | |
c227f099 AL |
3287 | target_phys_addr_t addr; |
3288 | target_phys_addr_t len; | |
6d16c2f8 AL |
3289 | } BounceBuffer; |
3290 | ||
3291 | static BounceBuffer bounce; | |
3292 | ||
ba223c29 AL |
3293 | typedef struct MapClient { |
3294 | void *opaque; | |
3295 | void (*callback)(void *opaque); | |
72cf2d4f | 3296 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3297 | } MapClient; |
3298 | ||
72cf2d4f BS |
3299 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3300 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
3301 | |
3302 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
3303 | { | |
3304 | MapClient *client = qemu_malloc(sizeof(*client)); | |
3305 | ||
3306 | client->opaque = opaque; | |
3307 | client->callback = callback; | |
72cf2d4f | 3308 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
3309 | return client; |
3310 | } | |
3311 | ||
3312 | void cpu_unregister_map_client(void *_client) | |
3313 | { | |
3314 | MapClient *client = (MapClient *)_client; | |
3315 | ||
72cf2d4f | 3316 | QLIST_REMOVE(client, link); |
34d5e948 | 3317 | qemu_free(client); |
ba223c29 AL |
3318 | } |
3319 | ||
3320 | static void cpu_notify_map_clients(void) | |
3321 | { | |
3322 | MapClient *client; | |
3323 | ||
72cf2d4f BS |
3324 | while (!QLIST_EMPTY(&map_client_list)) { |
3325 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 3326 | client->callback(client->opaque); |
34d5e948 | 3327 | cpu_unregister_map_client(client); |
ba223c29 AL |
3328 | } |
3329 | } | |
3330 | ||
6d16c2f8 AL |
3331 | /* Map a physical memory region into a host virtual address. |
3332 | * May map a subset of the requested range, given by and returned in *plen. | |
3333 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3334 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3335 | * Use cpu_register_map_client() to know when retrying the map operation is |
3336 | * likely to succeed. | |
6d16c2f8 | 3337 | */ |
c227f099 AL |
3338 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
3339 | target_phys_addr_t *plen, | |
6d16c2f8 AL |
3340 | int is_write) |
3341 | { | |
c227f099 AL |
3342 | target_phys_addr_t len = *plen; |
3343 | target_phys_addr_t done = 0; | |
6d16c2f8 AL |
3344 | int l; |
3345 | uint8_t *ret = NULL; | |
3346 | uint8_t *ptr; | |
c227f099 | 3347 | target_phys_addr_t page; |
6d16c2f8 AL |
3348 | unsigned long pd; |
3349 | PhysPageDesc *p; | |
3350 | unsigned long addr1; | |
3351 | ||
3352 | while (len > 0) { | |
3353 | page = addr & TARGET_PAGE_MASK; | |
3354 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3355 | if (l > len) | |
3356 | l = len; | |
3357 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3358 | if (!p) { | |
3359 | pd = IO_MEM_UNASSIGNED; | |
3360 | } else { | |
3361 | pd = p->phys_offset; | |
3362 | } | |
3363 | ||
3364 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3365 | if (done || bounce.buffer) { | |
3366 | break; | |
3367 | } | |
3368 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
3369 | bounce.addr = addr; | |
3370 | bounce.len = l; | |
3371 | if (!is_write) { | |
3372 | cpu_physical_memory_rw(addr, bounce.buffer, l, 0); | |
3373 | } | |
3374 | ptr = bounce.buffer; | |
3375 | } else { | |
3376 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
5579c7f3 | 3377 | ptr = qemu_get_ram_ptr(addr1); |
6d16c2f8 AL |
3378 | } |
3379 | if (!done) { | |
3380 | ret = ptr; | |
3381 | } else if (ret + done != ptr) { | |
3382 | break; | |
3383 | } | |
3384 | ||
3385 | len -= l; | |
3386 | addr += l; | |
3387 | done += l; | |
3388 | } | |
3389 | *plen = done; | |
3390 | return ret; | |
3391 | } | |
3392 | ||
3393 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
3394 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
3395 | * the amount of memory that was actually read or written by the caller. | |
3396 | */ | |
c227f099 AL |
3397 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
3398 | int is_write, target_phys_addr_t access_len) | |
6d16c2f8 AL |
3399 | { |
3400 | if (buffer != bounce.buffer) { | |
3401 | if (is_write) { | |
c227f099 | 3402 | ram_addr_t addr1 = qemu_ram_addr_from_host(buffer); |
6d16c2f8 AL |
3403 | while (access_len) { |
3404 | unsigned l; | |
3405 | l = TARGET_PAGE_SIZE; | |
3406 | if (l > access_len) | |
3407 | l = access_len; | |
3408 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3409 | /* invalidate code */ | |
3410 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3411 | /* set dirty bit */ | |
3412 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= | |
3413 | (0xff & ~CODE_DIRTY_FLAG); | |
3414 | } | |
3415 | addr1 += l; | |
3416 | access_len -= l; | |
3417 | } | |
3418 | } | |
3419 | return; | |
3420 | } | |
3421 | if (is_write) { | |
3422 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
3423 | } | |
f8a83245 | 3424 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3425 | bounce.buffer = NULL; |
ba223c29 | 3426 | cpu_notify_map_clients(); |
6d16c2f8 | 3427 | } |
d0ecd2aa | 3428 | |
8df1cd07 | 3429 | /* warning: addr must be aligned */ |
c227f099 | 3430 | uint32_t ldl_phys(target_phys_addr_t addr) |
8df1cd07 FB |
3431 | { |
3432 | int io_index; | |
3433 | uint8_t *ptr; | |
3434 | uint32_t val; | |
3435 | unsigned long pd; | |
3436 | PhysPageDesc *p; | |
3437 | ||
3438 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3439 | if (!p) { | |
3440 | pd = IO_MEM_UNASSIGNED; | |
3441 | } else { | |
3442 | pd = p->phys_offset; | |
3443 | } | |
3b46e624 | 3444 | |
5fafdf24 | 3445 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3446 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
3447 | /* I/O case */ |
3448 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3449 | if (p) |
3450 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3451 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
3452 | } else { | |
3453 | /* RAM case */ | |
5579c7f3 | 3454 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
3455 | (addr & ~TARGET_PAGE_MASK); |
3456 | val = ldl_p(ptr); | |
3457 | } | |
3458 | return val; | |
3459 | } | |
3460 | ||
84b7b8e7 | 3461 | /* warning: addr must be aligned */ |
c227f099 | 3462 | uint64_t ldq_phys(target_phys_addr_t addr) |
84b7b8e7 FB |
3463 | { |
3464 | int io_index; | |
3465 | uint8_t *ptr; | |
3466 | uint64_t val; | |
3467 | unsigned long pd; | |
3468 | PhysPageDesc *p; | |
3469 | ||
3470 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3471 | if (!p) { | |
3472 | pd = IO_MEM_UNASSIGNED; | |
3473 | } else { | |
3474 | pd = p->phys_offset; | |
3475 | } | |
3b46e624 | 3476 | |
2a4188a3 FB |
3477 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
3478 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
3479 | /* I/O case */ |
3480 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3481 | if (p) |
3482 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
84b7b8e7 FB |
3483 | #ifdef TARGET_WORDS_BIGENDIAN |
3484 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
3485 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
3486 | #else | |
3487 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
3488 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
3489 | #endif | |
3490 | } else { | |
3491 | /* RAM case */ | |
5579c7f3 | 3492 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
3493 | (addr & ~TARGET_PAGE_MASK); |
3494 | val = ldq_p(ptr); | |
3495 | } | |
3496 | return val; | |
3497 | } | |
3498 | ||
aab33094 | 3499 | /* XXX: optimize */ |
c227f099 | 3500 | uint32_t ldub_phys(target_phys_addr_t addr) |
aab33094 FB |
3501 | { |
3502 | uint8_t val; | |
3503 | cpu_physical_memory_read(addr, &val, 1); | |
3504 | return val; | |
3505 | } | |
3506 | ||
3507 | /* XXX: optimize */ | |
c227f099 | 3508 | uint32_t lduw_phys(target_phys_addr_t addr) |
aab33094 FB |
3509 | { |
3510 | uint16_t val; | |
3511 | cpu_physical_memory_read(addr, (uint8_t *)&val, 2); | |
3512 | return tswap16(val); | |
3513 | } | |
3514 | ||
8df1cd07 FB |
3515 | /* warning: addr must be aligned. The ram page is not masked as dirty |
3516 | and the code inside is not invalidated. It is useful if the dirty | |
3517 | bits are used to track modified PTEs */ | |
c227f099 | 3518 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3519 | { |
3520 | int io_index; | |
3521 | uint8_t *ptr; | |
3522 | unsigned long pd; | |
3523 | PhysPageDesc *p; | |
3524 | ||
3525 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3526 | if (!p) { | |
3527 | pd = IO_MEM_UNASSIGNED; | |
3528 | } else { | |
3529 | pd = p->phys_offset; | |
3530 | } | |
3b46e624 | 3531 | |
3a7d929e | 3532 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3533 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3534 | if (p) |
3535 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3536 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3537 | } else { | |
74576198 | 3538 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
5579c7f3 | 3539 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3540 | stl_p(ptr, val); |
74576198 AL |
3541 | |
3542 | if (unlikely(in_migration)) { | |
3543 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3544 | /* invalidate code */ | |
3545 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3546 | /* set dirty bit */ | |
3547 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= | |
3548 | (0xff & ~CODE_DIRTY_FLAG); | |
3549 | } | |
3550 | } | |
8df1cd07 FB |
3551 | } |
3552 | } | |
3553 | ||
c227f099 | 3554 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
bc98a7ef JM |
3555 | { |
3556 | int io_index; | |
3557 | uint8_t *ptr; | |
3558 | unsigned long pd; | |
3559 | PhysPageDesc *p; | |
3560 | ||
3561 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3562 | if (!p) { | |
3563 | pd = IO_MEM_UNASSIGNED; | |
3564 | } else { | |
3565 | pd = p->phys_offset; | |
3566 | } | |
3b46e624 | 3567 | |
bc98a7ef JM |
3568 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
3569 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3570 | if (p) |
3571 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
bc98a7ef JM |
3572 | #ifdef TARGET_WORDS_BIGENDIAN |
3573 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
3574 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
3575 | #else | |
3576 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
3577 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
3578 | #endif | |
3579 | } else { | |
5579c7f3 | 3580 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
3581 | (addr & ~TARGET_PAGE_MASK); |
3582 | stq_p(ptr, val); | |
3583 | } | |
3584 | } | |
3585 | ||
8df1cd07 | 3586 | /* warning: addr must be aligned */ |
c227f099 | 3587 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3588 | { |
3589 | int io_index; | |
3590 | uint8_t *ptr; | |
3591 | unsigned long pd; | |
3592 | PhysPageDesc *p; | |
3593 | ||
3594 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3595 | if (!p) { | |
3596 | pd = IO_MEM_UNASSIGNED; | |
3597 | } else { | |
3598 | pd = p->phys_offset; | |
3599 | } | |
3b46e624 | 3600 | |
3a7d929e | 3601 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3602 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3603 | if (p) |
3604 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3605 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3606 | } else { | |
3607 | unsigned long addr1; | |
3608 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3609 | /* RAM case */ | |
5579c7f3 | 3610 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3611 | stl_p(ptr, val); |
3a7d929e FB |
3612 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3613 | /* invalidate code */ | |
3614 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3615 | /* set dirty bit */ | |
f23db169 FB |
3616 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
3617 | (0xff & ~CODE_DIRTY_FLAG); | |
3a7d929e | 3618 | } |
8df1cd07 FB |
3619 | } |
3620 | } | |
3621 | ||
aab33094 | 3622 | /* XXX: optimize */ |
c227f099 | 3623 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
3624 | { |
3625 | uint8_t v = val; | |
3626 | cpu_physical_memory_write(addr, &v, 1); | |
3627 | } | |
3628 | ||
3629 | /* XXX: optimize */ | |
c227f099 | 3630 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
3631 | { |
3632 | uint16_t v = tswap16(val); | |
3633 | cpu_physical_memory_write(addr, (const uint8_t *)&v, 2); | |
3634 | } | |
3635 | ||
3636 | /* XXX: optimize */ | |
c227f099 | 3637 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
aab33094 FB |
3638 | { |
3639 | val = tswap64(val); | |
3640 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); | |
3641 | } | |
3642 | ||
5e2972fd | 3643 | /* virtual memory access for debug (includes writing to ROM) */ |
5fafdf24 | 3644 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 3645 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3646 | { |
3647 | int l; | |
c227f099 | 3648 | target_phys_addr_t phys_addr; |
9b3c35e0 | 3649 | target_ulong page; |
13eb76e0 FB |
3650 | |
3651 | while (len > 0) { | |
3652 | page = addr & TARGET_PAGE_MASK; | |
3653 | phys_addr = cpu_get_phys_page_debug(env, page); | |
3654 | /* if no physical page mapped, return an error */ | |
3655 | if (phys_addr == -1) | |
3656 | return -1; | |
3657 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3658 | if (l > len) | |
3659 | l = len; | |
5e2972fd | 3660 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
5e2972fd AL |
3661 | if (is_write) |
3662 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
3663 | else | |
5e2972fd | 3664 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
13eb76e0 FB |
3665 | len -= l; |
3666 | buf += l; | |
3667 | addr += l; | |
3668 | } | |
3669 | return 0; | |
3670 | } | |
a68fe89c | 3671 | #endif |
13eb76e0 | 3672 | |
2e70f6ef PB |
3673 | /* in deterministic execution mode, instructions doing device I/Os |
3674 | must be at the end of the TB */ | |
3675 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
3676 | { | |
3677 | TranslationBlock *tb; | |
3678 | uint32_t n, cflags; | |
3679 | target_ulong pc, cs_base; | |
3680 | uint64_t flags; | |
3681 | ||
3682 | tb = tb_find_pc((unsigned long)retaddr); | |
3683 | if (!tb) { | |
3684 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
3685 | retaddr); | |
3686 | } | |
3687 | n = env->icount_decr.u16.low + tb->icount; | |
3688 | cpu_restore_state(tb, env, (unsigned long)retaddr, NULL); | |
3689 | /* Calculate how many instructions had been executed before the fault | |
bf20dc07 | 3690 | occurred. */ |
2e70f6ef PB |
3691 | n = n - env->icount_decr.u16.low; |
3692 | /* Generate a new TB ending on the I/O insn. */ | |
3693 | n++; | |
3694 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
3695 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 3696 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
3697 | branch. */ |
3698 | #if defined(TARGET_MIPS) | |
3699 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
3700 | env->active_tc.PC -= 4; | |
3701 | env->icount_decr.u16.low++; | |
3702 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
3703 | } | |
3704 | #elif defined(TARGET_SH4) | |
3705 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
3706 | && n > 1) { | |
3707 | env->pc -= 2; | |
3708 | env->icount_decr.u16.low++; | |
3709 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
3710 | } | |
3711 | #endif | |
3712 | /* This should never happen. */ | |
3713 | if (n > CF_COUNT_MASK) | |
3714 | cpu_abort(env, "TB too big during recompile"); | |
3715 | ||
3716 | cflags = n | CF_LAST_IO; | |
3717 | pc = tb->pc; | |
3718 | cs_base = tb->cs_base; | |
3719 | flags = tb->flags; | |
3720 | tb_phys_invalidate(tb, -1); | |
3721 | /* FIXME: In theory this could raise an exception. In practice | |
3722 | we have already translated the block once so it's probably ok. */ | |
3723 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 3724 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
3725 | the first in the TB) then we end up generating a whole new TB and |
3726 | repeating the fault, which is horribly inefficient. | |
3727 | Better would be to execute just this insn uncached, or generate a | |
3728 | second new TB. */ | |
3729 | cpu_resume_from_signal(env, NULL); | |
3730 | } | |
3731 | ||
e3db7226 FB |
3732 | void dump_exec_info(FILE *f, |
3733 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
3734 | { | |
3735 | int i, target_code_size, max_target_code_size; | |
3736 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
3737 | TranslationBlock *tb; | |
3b46e624 | 3738 | |
e3db7226 FB |
3739 | target_code_size = 0; |
3740 | max_target_code_size = 0; | |
3741 | cross_page = 0; | |
3742 | direct_jmp_count = 0; | |
3743 | direct_jmp2_count = 0; | |
3744 | for(i = 0; i < nb_tbs; i++) { | |
3745 | tb = &tbs[i]; | |
3746 | target_code_size += tb->size; | |
3747 | if (tb->size > max_target_code_size) | |
3748 | max_target_code_size = tb->size; | |
3749 | if (tb->page_addr[1] != -1) | |
3750 | cross_page++; | |
3751 | if (tb->tb_next_offset[0] != 0xffff) { | |
3752 | direct_jmp_count++; | |
3753 | if (tb->tb_next_offset[1] != 0xffff) { | |
3754 | direct_jmp2_count++; | |
3755 | } | |
3756 | } | |
3757 | } | |
3758 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 3759 | cpu_fprintf(f, "Translation buffer state:\n"); |
26a5f13b FB |
3760 | cpu_fprintf(f, "gen code size %ld/%ld\n", |
3761 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); | |
3762 | cpu_fprintf(f, "TB count %d/%d\n", | |
3763 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 3764 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
3765 | nb_tbs ? target_code_size / nb_tbs : 0, |
3766 | max_target_code_size); | |
5fafdf24 | 3767 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
3768 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
3769 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
3770 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
3771 | cross_page, | |
e3db7226 FB |
3772 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
3773 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 3774 | direct_jmp_count, |
e3db7226 FB |
3775 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
3776 | direct_jmp2_count, | |
3777 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 3778 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
3779 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
3780 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
3781 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 3782 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
3783 | } |
3784 | ||
5fafdf24 | 3785 | #if !defined(CONFIG_USER_ONLY) |
61382a50 FB |
3786 | |
3787 | #define MMUSUFFIX _cmmu | |
3788 | #define GETPC() NULL | |
3789 | #define env cpu_single_env | |
b769d8fe | 3790 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
3791 | |
3792 | #define SHIFT 0 | |
3793 | #include "softmmu_template.h" | |
3794 | ||
3795 | #define SHIFT 1 | |
3796 | #include "softmmu_template.h" | |
3797 | ||
3798 | #define SHIFT 2 | |
3799 | #include "softmmu_template.h" | |
3800 | ||
3801 | #define SHIFT 3 | |
3802 | #include "softmmu_template.h" | |
3803 | ||
3804 | #undef env | |
3805 | ||
3806 | #endif |