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f25c0ae1 CLG |
1 | /* |
2 | * ASPEED SoC 2600 family | |
3 | * | |
4 | * Copyright (c) 2016-2019, IBM Corporation. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qapi/error.h" | |
f25c0ae1 CLG |
12 | #include "hw/misc/unimp.h" |
13 | #include "hw/arm/aspeed_soc.h" | |
f25c0ae1 CLG |
14 | #include "qemu/module.h" |
15 | #include "qemu/error-report.h" | |
16 | #include "hw/i2c/aspeed_i2c.h" | |
17 | #include "net/net.h" | |
18 | #include "sysemu/sysemu.h" | |
19 | ||
20 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
d9e9cd59 | 21 | #define ASPEED_SOC_DPMCU_SIZE 0x00040000 |
f25c0ae1 CLG |
22 | |
23 | static const hwaddr aspeed_soc_ast2600_memmap[] = { | |
5aa281d7 | 24 | [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, |
347df6f8 | 25 | [ASPEED_DEV_SRAM] = 0x10000000, |
d9e9cd59 | 26 | [ASPEED_DEV_DPMCU] = 0x18000000, |
f25c0ae1 | 27 | /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ |
347df6f8 EH |
28 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
29 | [ASPEED_DEV_PWM] = 0x1E610000, | |
30 | [ASPEED_DEV_FMC] = 0x1E620000, | |
31 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
08048cbd | 32 | [ASPEED_DEV_SPI2] = 0x1E631000, |
347df6f8 EH |
33 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, |
34 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
35 | [ASPEED_DEV_MII1] = 0x1E650000, | |
36 | [ASPEED_DEV_MII2] = 0x1E650008, | |
37 | [ASPEED_DEV_MII3] = 0x1E650010, | |
38 | [ASPEED_DEV_MII4] = 0x1E650018, | |
39 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
40 | [ASPEED_DEV_ETH3] = 0x1E670000, | |
41 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
42 | [ASPEED_DEV_ETH4] = 0x1E690000, | |
43 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
a3888d75 | 44 | [ASPEED_DEV_HACE] = 0x1E6D0000, |
347df6f8 EH |
45 | [ASPEED_DEV_SDMC] = 0x1E6E0000, |
46 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
47 | [ASPEED_DEV_XDMA] = 0x1E6E7000, | |
48 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
d9e9cd59 | 49 | [ASPEED_DEV_DP] = 0x1E6EB000, |
e1acf581 | 50 | [ASPEED_DEV_SBC] = 0x1E6F2000, |
fe31a2ec | 51 | [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, |
347df6f8 EH |
52 | [ASPEED_DEV_VIDEO] = 0x1E700000, |
53 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
54 | [ASPEED_DEV_EMMC] = 0x1E750000, | |
55 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
56 | [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, | |
57 | [ASPEED_DEV_RTC] = 0x1E781000, | |
58 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
59 | [ASPEED_DEV_WDT] = 0x1E785000, | |
60 | [ASPEED_DEV_LPC] = 0x1E789000, | |
61 | [ASPEED_DEV_IBT] = 0x1E789140, | |
62 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
55c57023 | 63 | [ASPEED_DEV_PECI] = 0x1E78B000, |
347df6f8 | 64 | [ASPEED_DEV_UART1] = 0x1E783000, |
ab5e8605 PD |
65 | [ASPEED_DEV_UART2] = 0x1E78D000, |
66 | [ASPEED_DEV_UART3] = 0x1E78E000, | |
67 | [ASPEED_DEV_UART4] = 0x1E78F000, | |
347df6f8 | 68 | [ASPEED_DEV_UART5] = 0x1E784000, |
ab5e8605 PD |
69 | [ASPEED_DEV_UART6] = 0x1E790000, |
70 | [ASPEED_DEV_UART7] = 0x1E790100, | |
71 | [ASPEED_DEV_UART8] = 0x1E790200, | |
72 | [ASPEED_DEV_UART9] = 0x1E790300, | |
73 | [ASPEED_DEV_UART10] = 0x1E790400, | |
74 | [ASPEED_DEV_UART11] = 0x1E790500, | |
75 | [ASPEED_DEV_UART12] = 0x1E790600, | |
76 | [ASPEED_DEV_UART13] = 0x1E790700, | |
347df6f8 | 77 | [ASPEED_DEV_VUART] = 0x1E787000, |
3222165d | 78 | [ASPEED_DEV_I3C] = 0x1E7A0000, |
347df6f8 | 79 | [ASPEED_DEV_SDRAM] = 0x80000000, |
f25c0ae1 CLG |
80 | }; |
81 | ||
82 | #define ASPEED_A7MPCORE_ADDR 0x40460000 | |
83 | ||
b151de69 | 84 | #define AST2600_MAX_IRQ 197 |
f25c0ae1 | 85 | |
a29e3e12 | 86 | /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ |
f25c0ae1 | 87 | static const int aspeed_soc_ast2600_irqmap[] = { |
347df6f8 EH |
88 | [ASPEED_DEV_UART1] = 47, |
89 | [ASPEED_DEV_UART2] = 48, | |
90 | [ASPEED_DEV_UART3] = 49, | |
91 | [ASPEED_DEV_UART4] = 50, | |
92 | [ASPEED_DEV_UART5] = 8, | |
ab5e8605 PD |
93 | [ASPEED_DEV_UART6] = 57, |
94 | [ASPEED_DEV_UART7] = 58, | |
95 | [ASPEED_DEV_UART8] = 59, | |
96 | [ASPEED_DEV_UART9] = 60, | |
97 | [ASPEED_DEV_UART10] = 61, | |
98 | [ASPEED_DEV_UART11] = 62, | |
99 | [ASPEED_DEV_UART12] = 63, | |
100 | [ASPEED_DEV_UART13] = 64, | |
347df6f8 EH |
101 | [ASPEED_DEV_VUART] = 8, |
102 | [ASPEED_DEV_FMC] = 39, | |
103 | [ASPEED_DEV_SDMC] = 0, | |
104 | [ASPEED_DEV_SCU] = 12, | |
105 | [ASPEED_DEV_ADC] = 78, | |
106 | [ASPEED_DEV_XDMA] = 6, | |
107 | [ASPEED_DEV_SDHCI] = 43, | |
108 | [ASPEED_DEV_EHCI1] = 5, | |
109 | [ASPEED_DEV_EHCI2] = 9, | |
110 | [ASPEED_DEV_EMMC] = 15, | |
111 | [ASPEED_DEV_GPIO] = 40, | |
112 | [ASPEED_DEV_GPIO_1_8V] = 11, | |
113 | [ASPEED_DEV_RTC] = 13, | |
114 | [ASPEED_DEV_TIMER1] = 16, | |
115 | [ASPEED_DEV_TIMER2] = 17, | |
116 | [ASPEED_DEV_TIMER3] = 18, | |
117 | [ASPEED_DEV_TIMER4] = 19, | |
118 | [ASPEED_DEV_TIMER5] = 20, | |
119 | [ASPEED_DEV_TIMER6] = 21, | |
120 | [ASPEED_DEV_TIMER7] = 22, | |
121 | [ASPEED_DEV_TIMER8] = 23, | |
122 | [ASPEED_DEV_WDT] = 24, | |
123 | [ASPEED_DEV_PWM] = 44, | |
124 | [ASPEED_DEV_LPC] = 35, | |
6820588e | 125 | [ASPEED_DEV_IBT] = 143, |
347df6f8 | 126 | [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ |
55c57023 | 127 | [ASPEED_DEV_PECI] = 38, |
347df6f8 EH |
128 | [ASPEED_DEV_ETH1] = 2, |
129 | [ASPEED_DEV_ETH2] = 3, | |
a3888d75 | 130 | [ASPEED_DEV_HACE] = 4, |
347df6f8 EH |
131 | [ASPEED_DEV_ETH3] = 32, |
132 | [ASPEED_DEV_ETH4] = 33, | |
c59f781e | 133 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ |
d9e9cd59 | 134 | [ASPEED_DEV_DP] = 62, |
3222165d | 135 | [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ |
f25c0ae1 CLG |
136 | }; |
137 | ||
699db715 | 138 | static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) |
f25c0ae1 CLG |
139 | { |
140 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
141 | ||
699db715 | 142 | return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]); |
f25c0ae1 CLG |
143 | } |
144 | ||
145 | static void aspeed_soc_ast2600_init(Object *obj) | |
146 | { | |
147 | AspeedSoCState *s = ASPEED_SOC(obj); | |
148 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
149 | int i; | |
150 | char socname[8]; | |
151 | char typename[64]; | |
152 | ||
153 | if (sscanf(sc->name, "%7s", socname) != 1) { | |
154 | g_assert_not_reached(); | |
155 | } | |
156 | ||
157 | for (i = 0; i < sc->num_cpus; i++) { | |
9fc7fc4d | 158 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
f25c0ae1 CLG |
159 | } |
160 | ||
161 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | |
db873cc5 | 162 | object_initialize_child(obj, "scu", &s->scu, typename); |
f25c0ae1 CLG |
163 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
164 | sc->silicon_rev); | |
165 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | |
d2623129 | 166 | "hw-strap1"); |
f25c0ae1 | 167 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 168 | "hw-strap2"); |
f25c0ae1 | 169 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 170 | "hw-prot-key"); |
f25c0ae1 | 171 | |
db873cc5 MA |
172 | object_initialize_child(obj, "a7mpcore", &s->a7mpcore, |
173 | TYPE_A15MPCORE_PRIV); | |
f25c0ae1 | 174 | |
db873cc5 | 175 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
f25c0ae1 CLG |
176 | |
177 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | |
db873cc5 | 178 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
f25c0ae1 | 179 | |
199fd623 AJ |
180 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); |
181 | object_initialize_child(obj, "adc", &s->adc, typename); | |
182 | ||
f25c0ae1 | 183 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 184 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
f25c0ae1 | 185 | |
55c57023 PD |
186 | object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); |
187 | ||
f25c0ae1 | 188 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
db873cc5 | 189 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
f25c0ae1 CLG |
190 | |
191 | for (i = 0; i < sc->spis_num; i++) { | |
192 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | |
db873cc5 | 193 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
f25c0ae1 CLG |
194 | } |
195 | ||
917940ce | 196 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
197 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
198 | TYPE_PLATFORM_EHCI); | |
917940ce GR |
199 | } |
200 | ||
f25c0ae1 | 201 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 202 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
f25c0ae1 | 203 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 204 | "ram-size"); |
f25c0ae1 CLG |
205 | |
206 | for (i = 0; i < sc->wdts_num; i++) { | |
207 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | |
db873cc5 | 208 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f25c0ae1 CLG |
209 | } |
210 | ||
d300db02 | 211 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
212 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
213 | TYPE_FTGMAC100); | |
289251b0 | 214 | |
db873cc5 | 215 | object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); |
f25c0ae1 CLG |
216 | } |
217 | ||
d2b3eaef PD |
218 | for (i = 0; i < sc->uarts_num; i++) { |
219 | object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); | |
220 | } | |
221 | ||
8efbee28 CLG |
222 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
223 | object_initialize_child(obj, "xdma", &s->xdma, typename); | |
f25c0ae1 CLG |
224 | |
225 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | |
db873cc5 | 226 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
f25c0ae1 CLG |
227 | |
228 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); | |
db873cc5 | 229 | object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); |
f25c0ae1 | 230 | |
db873cc5 MA |
231 | object_initialize_child(obj, "sd-controller", &s->sdhci, |
232 | TYPE_ASPEED_SDHCI); | |
f25c0ae1 | 233 | |
5325cc34 | 234 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 235 | |
f25c0ae1 CLG |
236 | /* Init sd card slot class here so that they're under the correct parent */ |
237 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
238 | object_initialize_child(obj, "sd-controller.sdhci[*]", |
239 | &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); | |
f25c0ae1 | 240 | } |
a29e3e12 | 241 | |
db873cc5 MA |
242 | object_initialize_child(obj, "emmc-controller", &s->emmc, |
243 | TYPE_ASPEED_SDHCI); | |
a29e3e12 | 244 | |
5325cc34 | 245 | object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
a29e3e12 | 246 | |
7089e0cc MA |
247 | object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], |
248 | TYPE_SYSBUS_SDHCI); | |
2ecf1726 CLG |
249 | |
250 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
251 | |
252 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
253 | object_initialize_child(obj, "hace", &s->hace, typename); | |
3222165d TL |
254 | |
255 | object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); | |
e1acf581 JS |
256 | |
257 | object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); | |
80beb085 PD |
258 | |
259 | object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); | |
260 | object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); | |
261 | object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); | |
262 | object_initialize_child(obj, "emmc-boot-controller", | |
263 | &s->emmc_boot_controller, | |
264 | TYPE_UNIMPLEMENTED_DEVICE); | |
f25c0ae1 CLG |
265 | } |
266 | ||
267 | /* | |
268 | * ASPEED ast2600 has 0xf as cluster ID | |
269 | * | |
932a8d1f | 270 | * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register |
f25c0ae1 CLG |
271 | */ |
272 | static uint64_t aspeed_calc_affinity(int cpu) | |
273 | { | |
274 | return (0xf << ARM_AFF1_SHIFT) | cpu; | |
275 | } | |
276 | ||
277 | static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | |
278 | { | |
279 | int i; | |
280 | AspeedSoCState *s = ASPEED_SOC(dev); | |
281 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
123327d1 | 282 | Error *err = NULL; |
f25c0ae1 | 283 | qemu_irq irq; |
72a7c473 | 284 | g_autofree char *sram_name = NULL; |
f25c0ae1 | 285 | |
5aa281d7 CLG |
286 | /* Default boot region (SPI memory or ROMs) */ |
287 | memory_region_init(&s->spi_boot_container, OBJECT(s), | |
288 | "aspeed.spi_boot_container", 0x10000000); | |
289 | memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], | |
290 | &s->spi_boot_container); | |
291 | ||
f25c0ae1 | 292 | /* IO space */ |
80beb085 PD |
293 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", |
294 | sc->memmap[ASPEED_DEV_IOMEM], | |
295 | ASPEED_SOC_IOMEM_SIZE); | |
f25c0ae1 | 296 | |
514bcf6f | 297 | /* Video engine stub */ |
80beb085 PD |
298 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", |
299 | sc->memmap[ASPEED_DEV_VIDEO], 0x1000); | |
514bcf6f | 300 | |
fe31a2ec | 301 | /* eMMC Boot Controller stub */ |
80beb085 PD |
302 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), |
303 | "aspeed.emmc-boot-controller", | |
304 | sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); | |
fe31a2ec | 305 | |
f25c0ae1 | 306 | /* CPU */ |
b7f1a0cb | 307 | for (i = 0; i < sc->num_cpus; i++) { |
b7f1a0cb | 308 | if (sc->num_cpus > 1) { |
5325cc34 MA |
309 | object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", |
310 | ASPEED_A7MPCORE_ADDR, &error_abort); | |
f25c0ae1 | 311 | } |
5325cc34 MA |
312 | object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", |
313 | aspeed_calc_affinity(i), &error_abort); | |
f25c0ae1 | 314 | |
5325cc34 | 315 | object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, |
058d0955 | 316 | &error_abort); |
e5c1b489 CLG |
317 | object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false, |
318 | &error_abort); | |
42bea956 CLG |
319 | object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false, |
320 | &error_abort); | |
e37976d7 | 321 | object_property_set_link(OBJECT(&s->cpu[i]), "memory", |
4dd9d554 | 322 | OBJECT(s->memory), &error_abort); |
058d0955 | 323 | |
668f62ec | 324 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
f25c0ae1 CLG |
325 | return; |
326 | } | |
327 | } | |
328 | ||
329 | /* A7MPCORE */ | |
5325cc34 | 330 | object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, |
f25c0ae1 | 331 | &error_abort); |
5325cc34 | 332 | object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", |
957ad79f | 333 | ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), |
5325cc34 | 334 | &error_abort); |
f25c0ae1 | 335 | |
db873cc5 | 336 | sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); |
5bfcbda7 | 337 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); |
f25c0ae1 | 338 | |
b7f1a0cb | 339 | for (i = 0; i < sc->num_cpus; i++) { |
f25c0ae1 | 340 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); |
85f0e0c3 | 341 | DeviceState *d = DEVICE(&s->cpu[i]); |
f25c0ae1 CLG |
342 | |
343 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | |
344 | sysbus_connect_irq(sbd, i, irq); | |
345 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | |
b7f1a0cb | 346 | sysbus_connect_irq(sbd, i + sc->num_cpus, irq); |
f25c0ae1 | 347 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
b7f1a0cb | 348 | sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); |
f25c0ae1 | 349 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); |
b7f1a0cb | 350 | sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); |
f25c0ae1 CLG |
351 | } |
352 | ||
353 | /* SRAM */ | |
72a7c473 PD |
354 | sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index); |
355 | memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); | |
f25c0ae1 CLG |
356 | if (err) { |
357 | error_propagate(errp, err); | |
358 | return; | |
359 | } | |
4dd9d554 | 360 | memory_region_add_subregion(s->memory, |
347df6f8 | 361 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
f25c0ae1 | 362 | |
d9e9cd59 | 363 | /* DPMCU */ |
80beb085 PD |
364 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", |
365 | sc->memmap[ASPEED_DEV_DPMCU], | |
366 | ASPEED_SOC_DPMCU_SIZE); | |
d9e9cd59 | 367 | |
f25c0ae1 | 368 | /* SCU */ |
668f62ec | 369 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
f25c0ae1 CLG |
370 | return; |
371 | } | |
5bfcbda7 | 372 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
f25c0ae1 CLG |
373 | |
374 | /* RTC */ | |
668f62ec | 375 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
f25c0ae1 CLG |
376 | return; |
377 | } | |
5bfcbda7 | 378 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
f25c0ae1 | 379 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 380 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
f25c0ae1 CLG |
381 | |
382 | /* Timer */ | |
5325cc34 MA |
383 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
384 | &error_abort); | |
668f62ec | 385 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
f25c0ae1 CLG |
386 | return; |
387 | } | |
5bfcbda7 | 388 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, |
347df6f8 | 389 | sc->memmap[ASPEED_DEV_TIMER1]); |
f25c0ae1 | 390 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
e8874c06 | 391 | irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
f25c0ae1 CLG |
392 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
393 | } | |
394 | ||
199fd623 AJ |
395 | /* ADC */ |
396 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
397 | return; | |
398 | } | |
5bfcbda7 | 399 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); |
199fd623 AJ |
400 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, |
401 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
402 | ||
470253b6 | 403 | /* UART */ |
d2b3eaef PD |
404 | if (!aspeed_soc_uart_realize(s, errp)) { |
405 | return; | |
406 | } | |
f25c0ae1 CLG |
407 | |
408 | /* I2C */ | |
5325cc34 | 409 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 410 | &error_abort); |
668f62ec | 411 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
f25c0ae1 CLG |
412 | return; |
413 | } | |
5bfcbda7 | 414 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
f25c0ae1 | 415 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { |
e8874c06 CLG |
416 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), |
417 | sc->irqmap[ASPEED_DEV_I2C] + i); | |
60261038 CLG |
418 | /* The AST2600 I2C controller has one IRQ per bus. */ |
419 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); | |
f25c0ae1 CLG |
420 | } |
421 | ||
55c57023 PD |
422 | /* PECI */ |
423 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { | |
424 | return; | |
425 | } | |
426 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, | |
427 | sc->memmap[ASPEED_DEV_PECI]); | |
428 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, | |
429 | aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); | |
430 | ||
f25c0ae1 | 431 | /* FMC, The number of CS is set at the board level */ |
5325cc34 | 432 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 433 | &error_abort); |
668f62ec | 434 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
f25c0ae1 CLG |
435 | return; |
436 | } | |
5bfcbda7 PD |
437 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
438 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, | |
30b6852c | 439 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
f25c0ae1 | 440 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
347df6f8 | 441 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
f25c0ae1 | 442 | |
5aa281d7 CLG |
443 | /* Set up an alias on the FMC CE0 region (boot default) */ |
444 | MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; | |
445 | memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", | |
446 | fmc0_mmio, 0, memory_region_size(fmc0_mmio)); | |
447 | memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); | |
448 | ||
f25c0ae1 CLG |
449 | /* SPI */ |
450 | for (i = 0; i < sc->spis_num; i++) { | |
5325cc34 MA |
451 | object_property_set_link(OBJECT(&s->spi[i]), "dram", |
452 | OBJECT(s->dram_mr), &error_abort); | |
668f62ec | 453 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
f25c0ae1 CLG |
454 | return; |
455 | } | |
5bfcbda7 | 456 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, |
347df6f8 | 457 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
5bfcbda7 | 458 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, |
30b6852c | 459 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
f25c0ae1 CLG |
460 | } |
461 | ||
917940ce GR |
462 | /* EHCI */ |
463 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 464 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
917940ce GR |
465 | return; |
466 | } | |
5bfcbda7 | 467 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 468 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
917940ce | 469 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 470 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
917940ce GR |
471 | } |
472 | ||
f25c0ae1 | 473 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 474 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
f25c0ae1 CLG |
475 | return; |
476 | } | |
5bfcbda7 PD |
477 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, |
478 | sc->memmap[ASPEED_DEV_SDMC]); | |
f25c0ae1 CLG |
479 | |
480 | /* Watch dog */ | |
481 | for (i = 0; i < sc->wdts_num; i++) { | |
482 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | |
6fdb4381 | 483 | hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; |
f25c0ae1 | 484 | |
5325cc34 MA |
485 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
486 | &error_abort); | |
668f62ec | 487 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f25c0ae1 CLG |
488 | return; |
489 | } | |
6fdb4381 | 490 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); |
f25c0ae1 CLG |
491 | } |
492 | ||
346160cb CLG |
493 | /* RAM */ |
494 | if (!aspeed_soc_dram_init(s, errp)) { | |
495 | return; | |
496 | } | |
497 | ||
f25c0ae1 | 498 | /* Net */ |
d3bad7e7 | 499 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 500 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 501 | &error_abort); |
668f62ec | 502 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 503 | return; |
f25c0ae1 | 504 | } |
5bfcbda7 | 505 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 506 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
f25c0ae1 | 507 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 508 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
289251b0 | 509 | |
5325cc34 MA |
510 | object_property_set_link(OBJECT(&s->mii[i]), "nic", |
511 | OBJECT(&s->ftgmac100[i]), &error_abort); | |
668f62ec | 512 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { |
289251b0 CLG |
513 | return; |
514 | } | |
515 | ||
5bfcbda7 | 516 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, |
347df6f8 | 517 | sc->memmap[ASPEED_DEV_MII1 + i]); |
f25c0ae1 CLG |
518 | } |
519 | ||
520 | /* XDMA */ | |
668f62ec | 521 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
f25c0ae1 CLG |
522 | return; |
523 | } | |
5bfcbda7 | 524 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 525 | sc->memmap[ASPEED_DEV_XDMA]); |
f25c0ae1 | 526 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 527 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
f25c0ae1 CLG |
528 | |
529 | /* GPIO */ | |
668f62ec | 530 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
f25c0ae1 CLG |
531 | return; |
532 | } | |
5bfcbda7 | 533 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); |
f25c0ae1 | 534 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 535 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
f25c0ae1 | 536 | |
668f62ec | 537 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { |
f25c0ae1 CLG |
538 | return; |
539 | } | |
5bfcbda7 | 540 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
347df6f8 | 541 | sc->memmap[ASPEED_DEV_GPIO_1_8V]); |
f25c0ae1 | 542 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
347df6f8 | 543 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); |
f25c0ae1 CLG |
544 | |
545 | /* SDHCI */ | |
668f62ec | 546 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
f25c0ae1 CLG |
547 | return; |
548 | } | |
5bfcbda7 | 549 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 550 | sc->memmap[ASPEED_DEV_SDHCI]); |
f25c0ae1 | 551 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 552 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
a29e3e12 AJ |
553 | |
554 | /* eMMC */ | |
668f62ec | 555 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { |
a29e3e12 AJ |
556 | return; |
557 | } | |
5bfcbda7 PD |
558 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, |
559 | sc->memmap[ASPEED_DEV_EMMC]); | |
a29e3e12 | 560 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, |
347df6f8 | 561 | aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); |
2ecf1726 CLG |
562 | |
563 | /* LPC */ | |
564 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
565 | return; | |
566 | } | |
5bfcbda7 | 567 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); |
c59f781e AJ |
568 | |
569 | /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ | |
2ecf1726 CLG |
570 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
571 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
572 | |
573 | /* | |
574 | * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. | |
575 | * | |
576 | * LPC subdevice IRQ sources are offset from 1 because the LPC model caters | |
577 | * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ | |
578 | * shared across the subdevices, and the shared IRQ output to the VIC is at | |
579 | * offset 0. | |
580 | */ | |
581 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
582 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
583 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); | |
584 | ||
585 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
586 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
587 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); | |
588 | ||
589 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
590 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
591 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); | |
592 | ||
593 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
594 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
595 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | |
a3888d75 JS |
596 | |
597 | /* HACE */ | |
598 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
599 | &error_abort); | |
600 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
601 | return; | |
602 | } | |
5bfcbda7 PD |
603 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, |
604 | sc->memmap[ASPEED_DEV_HACE]); | |
a3888d75 JS |
605 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, |
606 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
3222165d TL |
607 | |
608 | /* I3C */ | |
609 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { | |
610 | return; | |
611 | } | |
5bfcbda7 | 612 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); |
3222165d | 613 | for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { |
e8874c06 CLG |
614 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), |
615 | sc->irqmap[ASPEED_DEV_I3C] + i); | |
3222165d TL |
616 | /* The AST2600 I3C controller has one IRQ per bus. */ |
617 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); | |
618 | } | |
e1acf581 JS |
619 | |
620 | /* Secure Boot Controller */ | |
621 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { | |
622 | return; | |
623 | } | |
5bfcbda7 | 624 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); |
f25c0ae1 CLG |
625 | } |
626 | ||
627 | static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | |
628 | { | |
629 | DeviceClass *dc = DEVICE_CLASS(oc); | |
630 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
631 | ||
632 | dc->realize = aspeed_soc_ast2600_realize; | |
633 | ||
c5811bb3 | 634 | sc->name = "ast2600-a3"; |
f25c0ae1 | 635 | sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); |
c5811bb3 | 636 | sc->silicon_rev = AST2600_A3_SILICON_REV; |
e01b4d5b | 637 | sc->sram_size = 0x16400; |
f25c0ae1 | 638 | sc->spis_num = 2; |
917940ce | 639 | sc->ehcis_num = 2; |
f25c0ae1 | 640 | sc->wdts_num = 4; |
d300db02 | 641 | sc->macs_num = 4; |
c5e1bdb9 | 642 | sc->uarts_num = 13; |
f25c0ae1 CLG |
643 | sc->irqmap = aspeed_soc_ast2600_irqmap; |
644 | sc->memmap = aspeed_soc_ast2600_memmap; | |
645 | sc->num_cpus = 2; | |
699db715 | 646 | sc->get_irq = aspeed_soc_ast2600_get_irq; |
f25c0ae1 CLG |
647 | } |
648 | ||
4fc5e806 PMD |
649 | static const TypeInfo aspeed_soc_ast2600_types[] = { |
650 | { | |
651 | .name = TYPE_ASPEED2600_SOC, | |
652 | .parent = TYPE_ASPEED_SOC, | |
653 | .instance_size = sizeof(Aspeed2600SoCState), | |
654 | .abstract = true, | |
655 | }, { | |
656 | .name = "ast2600-a3", | |
657 | .parent = TYPE_ASPEED2600_SOC, | |
658 | .instance_init = aspeed_soc_ast2600_init, | |
659 | .class_init = aspeed_soc_ast2600_class_init, | |
660 | }, | |
f25c0ae1 CLG |
661 | }; |
662 | ||
4fc5e806 | 663 | DEFINE_TYPES(aspeed_soc_ast2600_types) |