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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
18e08a55 | 26 | #include "apb_pci.h" |
87ecb68b PB |
27 | #include "pc.h" |
28 | #include "nvram.h" | |
29 | #include "fdc.h" | |
30 | #include "net.h" | |
31 | #include "qemu-timer.h" | |
32 | #include "sysemu.h" | |
33 | #include "boards.h" | |
d2c63fc1 | 34 | #include "firmware_abi.h" |
3cce6243 | 35 | #include "fw_cfg.h" |
1baffa46 | 36 | #include "sysbus.h" |
977e1244 | 37 | #include "ide.h" |
ca20cf32 BS |
38 | #include "loader.h" |
39 | #include "elf.h" | |
2446333c | 40 | #include "blockdev.h" |
39186d8a | 41 | #include "exec-memory.h" |
c1195d16 | 42 | #include "vga-pci.h" |
3475187d | 43 | |
9d926598 | 44 | //#define DEBUG_IRQ |
b430a225 | 45 | //#define DEBUG_EBUS |
8f4efc55 | 46 | //#define DEBUG_TIMER |
9d926598 BS |
47 | |
48 | #ifdef DEBUG_IRQ | |
b430a225 | 49 | #define CPUIRQ_DPRINTF(fmt, ...) \ |
001faf32 | 50 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
9d926598 | 51 | #else |
b430a225 BS |
52 | #define CPUIRQ_DPRINTF(fmt, ...) |
53 | #endif | |
54 | ||
55 | #ifdef DEBUG_EBUS | |
56 | #define EBUS_DPRINTF(fmt, ...) \ | |
57 | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) | |
58 | #else | |
59 | #define EBUS_DPRINTF(fmt, ...) | |
9d926598 BS |
60 | #endif |
61 | ||
8f4efc55 IK |
62 | #ifdef DEBUG_TIMER |
63 | #define TIMER_DPRINTF(fmt, ...) \ | |
64 | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) | |
65 | #else | |
66 | #define TIMER_DPRINTF(fmt, ...) | |
67 | #endif | |
68 | ||
83469015 FB |
69 | #define KERNEL_LOAD_ADDR 0x00404000 |
70 | #define CMDLINE_ADDR 0x003ff000 | |
ac2e9d66 | 71 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 72 | #define PROM_VADDR 0x000ffd00000ULL |
83469015 | 73 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e | 74 | #define APB_MEM_BASE 0x1ff00000000ULL |
d63baf92 | 75 | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
f930d07e | 76 | #define PROM_FILENAME "openbios-sparc64" |
83469015 | 77 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 78 | #define MAX_IDE_BUS 2 |
3cce6243 | 79 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
80 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
81 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
82 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 83 | |
361dea40 | 84 | #define IVEC_MAX 0x30 |
9d926598 | 85 | |
8fa211e8 BS |
86 | #define TICK_MAX 0x7fffffffffffffffULL |
87 | ||
c7ba218d BS |
88 | struct hwdef { |
89 | const char * const default_cpu_model; | |
905fdcb5 | 90 | uint16_t machine_id; |
e87231d4 BS |
91 | uint64_t prom_addr; |
92 | uint64_t console_serial_base; | |
c7ba218d BS |
93 | }; |
94 | ||
c5e6fb7e AK |
95 | typedef struct EbusState { |
96 | PCIDevice pci_dev; | |
97 | MemoryRegion bar0; | |
98 | MemoryRegion bar1; | |
99 | } EbusState; | |
100 | ||
3475187d FB |
101 | int DMA_get_channel_mode (int nchan) |
102 | { | |
103 | return 0; | |
104 | } | |
105 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
106 | { | |
107 | return 0; | |
108 | } | |
109 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
110 | { | |
111 | return 0; | |
112 | } | |
113 | void DMA_hold_DREQ (int nchan) {} | |
114 | void DMA_release_DREQ (int nchan) {} | |
115 | void DMA_schedule(int nchan) {} | |
4556bd8b BS |
116 | |
117 | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) | |
118 | { | |
119 | } | |
120 | ||
3475187d FB |
121 | void DMA_register_channel (int nchan, |
122 | DMA_transfer_handler transfer_handler, | |
123 | void *opaque) | |
124 | { | |
125 | } | |
126 | ||
513f789f | 127 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
81864572 | 128 | { |
513f789f | 129 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
130 | return 0; |
131 | } | |
132 | ||
43a34704 BS |
133 | static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size, |
134 | const char *arch, ram_addr_t RAM_size, | |
135 | const char *boot_devices, | |
136 | uint32_t kernel_image, uint32_t kernel_size, | |
137 | const char *cmdline, | |
138 | uint32_t initrd_image, uint32_t initrd_size, | |
139 | uint32_t NVRAM_image, | |
140 | int width, int height, int depth, | |
141 | const uint8_t *macaddr) | |
83469015 | 142 | { |
66508601 BS |
143 | unsigned int i; |
144 | uint32_t start, end; | |
d2c63fc1 | 145 | uint8_t image[0x1ff0]; |
d2c63fc1 BS |
146 | struct OpenBIOS_nvpart_v1 *part_header; |
147 | ||
148 | memset(image, '\0', sizeof(image)); | |
149 | ||
513f789f | 150 | start = 0; |
83469015 | 151 | |
66508601 BS |
152 | // OpenBIOS nvram variables |
153 | // Variable partition | |
d2c63fc1 BS |
154 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
155 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 156 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 157 | |
d2c63fc1 | 158 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 159 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
160 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
161 | ||
162 | // End marker | |
163 | image[end++] = '\0'; | |
66508601 | 164 | |
66508601 | 165 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 166 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
167 | |
168 | // free partition | |
169 | start = end; | |
d2c63fc1 BS |
170 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
171 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 172 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
173 | |
174 | end = 0x1fd0; | |
d2c63fc1 BS |
175 | OpenBIOS_finish_partition(part_header, end - start); |
176 | ||
0d31cb99 BS |
177 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
178 | ||
d2c63fc1 BS |
179 | for (i = 0; i < sizeof(image); i++) |
180 | m48t59_write(nvram, i, image[i]); | |
66508601 | 181 | |
83469015 | 182 | return 0; |
3475187d | 183 | } |
5f2bf0fe BS |
184 | |
185 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
186 | const char *initrd_filename, | |
187 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
188 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
189 | uint64_t *kernel_entry) | |
636aa70a BS |
190 | { |
191 | int linux_boot; | |
192 | unsigned int i; | |
193 | long kernel_size; | |
6908d9ce | 194 | uint8_t *ptr; |
5f2bf0fe | 195 | uint64_t kernel_top; |
636aa70a BS |
196 | |
197 | linux_boot = (kernel_filename != NULL); | |
198 | ||
199 | kernel_size = 0; | |
200 | if (linux_boot) { | |
ca20cf32 BS |
201 | int bswap_needed; |
202 | ||
203 | #ifdef BSWAP_NEEDED | |
204 | bswap_needed = 1; | |
205 | #else | |
206 | bswap_needed = 0; | |
207 | #endif | |
5f2bf0fe BS |
208 | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
209 | kernel_addr, &kernel_top, 1, ELF_MACHINE, 0); | |
210 | if (kernel_size < 0) { | |
211 | *kernel_addr = KERNEL_LOAD_ADDR; | |
212 | *kernel_entry = KERNEL_LOAD_ADDR; | |
636aa70a | 213 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
214 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
215 | TARGET_PAGE_SIZE); | |
5f2bf0fe BS |
216 | } |
217 | if (kernel_size < 0) { | |
636aa70a BS |
218 | kernel_size = load_image_targphys(kernel_filename, |
219 | KERNEL_LOAD_ADDR, | |
220 | RAM_size - KERNEL_LOAD_ADDR); | |
5f2bf0fe | 221 | } |
636aa70a BS |
222 | if (kernel_size < 0) { |
223 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
224 | kernel_filename); | |
225 | exit(1); | |
226 | } | |
5f2bf0fe | 227 | /* load initrd above kernel */ |
636aa70a BS |
228 | *initrd_size = 0; |
229 | if (initrd_filename) { | |
5f2bf0fe BS |
230 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
231 | ||
636aa70a | 232 | *initrd_size = load_image_targphys(initrd_filename, |
5f2bf0fe BS |
233 | *initrd_addr, |
234 | RAM_size - *initrd_addr); | |
235 | if ((int)*initrd_size < 0) { | |
636aa70a BS |
236 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
237 | initrd_filename); | |
238 | exit(1); | |
239 | } | |
240 | } | |
241 | if (*initrd_size > 0) { | |
242 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
5f2bf0fe | 243 | ptr = rom_ptr(*kernel_addr + i); |
6908d9ce | 244 | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
5f2bf0fe | 245 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); |
6908d9ce | 246 | stl_p(ptr + 28, *initrd_size); |
636aa70a BS |
247 | break; |
248 | } | |
249 | } | |
250 | } | |
251 | } | |
252 | return kernel_size; | |
253 | } | |
3475187d | 254 | |
98cec4a2 | 255 | void cpu_check_irqs(CPUSPARCState *env) |
9d926598 | 256 | { |
d532b26c IK |
257 | uint32_t pil = env->pil_in | |
258 | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); | |
259 | ||
a7be9bad AT |
260 | /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ |
261 | if (env->ivec_status & 0x20) { | |
262 | return; | |
263 | } | |
d532b26c IK |
264 | /* check if TM or SM in SOFTINT are set |
265 | setting these also causes interrupt 14 */ | |
266 | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { | |
267 | pil |= 1 << 14; | |
268 | } | |
269 | ||
9f94778c AT |
270 | /* The bit corresponding to psrpil is (1<< psrpil), the next bit |
271 | is (2 << psrpil). */ | |
272 | if (pil < (2 << env->psrpil)){ | |
d532b26c IK |
273 | if (env->interrupt_request & CPU_INTERRUPT_HARD) { |
274 | CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", | |
275 | env->interrupt_index); | |
276 | env->interrupt_index = 0; | |
277 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
278 | } | |
279 | return; | |
280 | } | |
281 | ||
282 | if (cpu_interrupts_enabled(env)) { | |
9d926598 | 283 | |
9d926598 BS |
284 | unsigned int i; |
285 | ||
d532b26c | 286 | for (i = 15; i > env->psrpil; i--) { |
9d926598 BS |
287 | if (pil & (1 << i)) { |
288 | int old_interrupt = env->interrupt_index; | |
d532b26c IK |
289 | int new_interrupt = TT_EXTINT | i; |
290 | ||
a7be9bad AT |
291 | if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt |
292 | && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { | |
d532b26c IK |
293 | CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " |
294 | "current %x >= pending %x\n", | |
295 | env->tl, cpu_tsptr(env)->tt, new_interrupt); | |
296 | } else if (old_interrupt != new_interrupt) { | |
297 | env->interrupt_index = new_interrupt; | |
298 | CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, | |
299 | old_interrupt, new_interrupt); | |
9d926598 BS |
300 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
301 | } | |
302 | break; | |
303 | } | |
304 | } | |
9f94778c | 305 | } else if (env->interrupt_request & CPU_INTERRUPT_HARD) { |
d532b26c IK |
306 | CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " |
307 | "current interrupt %x\n", | |
308 | pil, env->pil_in, env->softint, env->interrupt_index); | |
9f94778c AT |
309 | env->interrupt_index = 0; |
310 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
9d926598 BS |
311 | } |
312 | } | |
313 | ||
98cec4a2 | 314 | static void cpu_kick_irq(CPUSPARCState *env) |
8f4efc55 IK |
315 | { |
316 | env->halted = 0; | |
317 | cpu_check_irqs(env); | |
94ad5b00 | 318 | qemu_cpu_kick(env); |
8f4efc55 IK |
319 | } |
320 | ||
361dea40 | 321 | static void cpu_set_ivec_irq(void *opaque, int irq, int level) |
9d926598 | 322 | { |
98cec4a2 | 323 | CPUSPARCState *env = opaque; |
9d926598 BS |
324 | |
325 | if (level) { | |
23cf96e1 AT |
326 | if (!(env->ivec_status & 0x20)) { |
327 | CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); | |
328 | env->halted = 0; | |
329 | env->interrupt_index = TT_IVEC; | |
330 | env->ivec_status |= 0x20; | |
331 | env->ivec_data[0] = (0x1f << 6) | irq; | |
332 | env->ivec_data[1] = 0; | |
333 | env->ivec_data[2] = 0; | |
334 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
335 | } | |
336 | } else { | |
337 | if (env->ivec_status & 0x20) { | |
338 | CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); | |
339 | env->ivec_status &= ~0x20; | |
340 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
341 | } | |
9d926598 BS |
342 | } |
343 | } | |
344 | ||
e87231d4 | 345 | typedef struct ResetData { |
403d7a2d | 346 | SPARCCPU *cpu; |
44a99354 | 347 | uint64_t prom_addr; |
e87231d4 BS |
348 | } ResetData; |
349 | ||
8f4efc55 IK |
350 | void cpu_put_timer(QEMUFile *f, CPUTimer *s) |
351 | { | |
352 | qemu_put_be32s(f, &s->frequency); | |
353 | qemu_put_be32s(f, &s->disabled); | |
354 | qemu_put_be64s(f, &s->disabled_mask); | |
355 | qemu_put_sbe64s(f, &s->clock_offset); | |
356 | ||
357 | qemu_put_timer(f, s->qtimer); | |
358 | } | |
359 | ||
360 | void cpu_get_timer(QEMUFile *f, CPUTimer *s) | |
361 | { | |
362 | qemu_get_be32s(f, &s->frequency); | |
363 | qemu_get_be32s(f, &s->disabled); | |
364 | qemu_get_be64s(f, &s->disabled_mask); | |
365 | qemu_get_sbe64s(f, &s->clock_offset); | |
366 | ||
367 | qemu_get_timer(f, s->qtimer); | |
368 | } | |
369 | ||
98cec4a2 | 370 | static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env, |
8f4efc55 IK |
371 | QEMUBHFunc *cb, uint32_t frequency, |
372 | uint64_t disabled_mask) | |
373 | { | |
7267c094 | 374 | CPUTimer *timer = g_malloc0(sizeof (CPUTimer)); |
8f4efc55 IK |
375 | |
376 | timer->name = name; | |
377 | timer->frequency = frequency; | |
378 | timer->disabled_mask = disabled_mask; | |
379 | ||
380 | timer->disabled = 1; | |
74475455 | 381 | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
8f4efc55 | 382 | |
74475455 | 383 | timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env); |
8f4efc55 IK |
384 | |
385 | return timer; | |
386 | } | |
387 | ||
388 | static void cpu_timer_reset(CPUTimer *timer) | |
389 | { | |
390 | timer->disabled = 1; | |
74475455 | 391 | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
8f4efc55 IK |
392 | |
393 | qemu_del_timer(timer->qtimer); | |
394 | } | |
395 | ||
c68ea704 FB |
396 | static void main_cpu_reset(void *opaque) |
397 | { | |
e87231d4 | 398 | ResetData *s = (ResetData *)opaque; |
403d7a2d | 399 | CPUSPARCState *env = &s->cpu->env; |
44a99354 | 400 | static unsigned int nr_resets; |
20c9f095 | 401 | |
403d7a2d | 402 | cpu_reset(CPU(s->cpu)); |
8f4efc55 IK |
403 | |
404 | cpu_timer_reset(env->tick); | |
405 | cpu_timer_reset(env->stick); | |
406 | cpu_timer_reset(env->hstick); | |
407 | ||
e87231d4 BS |
408 | env->gregs[1] = 0; // Memory start |
409 | env->gregs[2] = ram_size; // Memory size | |
410 | env->gregs[3] = 0; // Machine description XXX | |
44a99354 BS |
411 | if (nr_resets++ == 0) { |
412 | /* Power on reset */ | |
413 | env->pc = s->prom_addr + 0x20ULL; | |
414 | } else { | |
415 | env->pc = s->prom_addr + 0x40ULL; | |
416 | } | |
e87231d4 | 417 | env->npc = env->pc + 4; |
20c9f095 BS |
418 | } |
419 | ||
22548760 | 420 | static void tick_irq(void *opaque) |
20c9f095 | 421 | { |
98cec4a2 | 422 | CPUSPARCState *env = opaque; |
20c9f095 | 423 | |
8f4efc55 IK |
424 | CPUTimer* timer = env->tick; |
425 | ||
426 | if (timer->disabled) { | |
427 | CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); | |
428 | return; | |
429 | } else { | |
430 | CPUIRQ_DPRINTF("tick: fire\n"); | |
8fa211e8 | 431 | } |
8f4efc55 IK |
432 | |
433 | env->softint |= SOFTINT_TIMER; | |
434 | cpu_kick_irq(env); | |
20c9f095 BS |
435 | } |
436 | ||
22548760 | 437 | static void stick_irq(void *opaque) |
20c9f095 | 438 | { |
98cec4a2 | 439 | CPUSPARCState *env = opaque; |
20c9f095 | 440 | |
8f4efc55 IK |
441 | CPUTimer* timer = env->stick; |
442 | ||
443 | if (timer->disabled) { | |
444 | CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); | |
445 | return; | |
446 | } else { | |
447 | CPUIRQ_DPRINTF("stick: fire\n"); | |
8fa211e8 | 448 | } |
8f4efc55 IK |
449 | |
450 | env->softint |= SOFTINT_STIMER; | |
451 | cpu_kick_irq(env); | |
20c9f095 BS |
452 | } |
453 | ||
22548760 | 454 | static void hstick_irq(void *opaque) |
20c9f095 | 455 | { |
98cec4a2 | 456 | CPUSPARCState *env = opaque; |
20c9f095 | 457 | |
8f4efc55 IK |
458 | CPUTimer* timer = env->hstick; |
459 | ||
460 | if (timer->disabled) { | |
461 | CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); | |
462 | return; | |
463 | } else { | |
464 | CPUIRQ_DPRINTF("hstick: fire\n"); | |
8fa211e8 | 465 | } |
8f4efc55 IK |
466 | |
467 | env->softint |= SOFTINT_STIMER; | |
468 | cpu_kick_irq(env); | |
469 | } | |
470 | ||
471 | static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) | |
472 | { | |
473 | return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency); | |
474 | } | |
475 | ||
476 | static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) | |
477 | { | |
478 | return muldiv64(timer_ticks, frequency, get_ticks_per_sec()); | |
c68ea704 FB |
479 | } |
480 | ||
8f4efc55 | 481 | void cpu_tick_set_count(CPUTimer *timer, uint64_t count) |
f4b1a842 | 482 | { |
8f4efc55 IK |
483 | uint64_t real_count = count & ~timer->disabled_mask; |
484 | uint64_t disabled_bit = count & timer->disabled_mask; | |
485 | ||
74475455 | 486 | int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) - |
8f4efc55 IK |
487 | cpu_to_timer_ticks(real_count, timer->frequency); |
488 | ||
489 | TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n", | |
490 | timer->name, real_count, | |
491 | timer->disabled?"disabled":"enabled", timer); | |
492 | ||
493 | timer->disabled = disabled_bit ? 1 : 0; | |
494 | timer->clock_offset = vm_clock_offset; | |
f4b1a842 BS |
495 | } |
496 | ||
8f4efc55 | 497 | uint64_t cpu_tick_get_count(CPUTimer *timer) |
f4b1a842 | 498 | { |
8f4efc55 | 499 | uint64_t real_count = timer_to_cpu_ticks( |
74475455 | 500 | qemu_get_clock_ns(vm_clock) - timer->clock_offset, |
8f4efc55 IK |
501 | timer->frequency); |
502 | ||
503 | TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n", | |
504 | timer->name, real_count, | |
505 | timer->disabled?"disabled":"enabled", timer); | |
506 | ||
507 | if (timer->disabled) | |
508 | real_count |= timer->disabled_mask; | |
509 | ||
510 | return real_count; | |
f4b1a842 BS |
511 | } |
512 | ||
8f4efc55 | 513 | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) |
f4b1a842 | 514 | { |
74475455 | 515 | int64_t now = qemu_get_clock_ns(vm_clock); |
8f4efc55 IK |
516 | |
517 | uint64_t real_limit = limit & ~timer->disabled_mask; | |
518 | timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; | |
519 | ||
520 | int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + | |
521 | timer->clock_offset; | |
522 | ||
523 | if (expires < now) { | |
524 | expires = now + 1; | |
525 | } | |
526 | ||
527 | TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " | |
528 | "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", | |
529 | timer->name, real_limit, | |
530 | timer->disabled?"disabled":"enabled", | |
531 | timer, limit, | |
532 | timer_to_cpu_ticks(now - timer->clock_offset, | |
533 | timer->frequency), | |
534 | timer_to_cpu_ticks(expires - now, timer->frequency)); | |
535 | ||
536 | if (!real_limit) { | |
537 | TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", | |
538 | timer->name); | |
539 | qemu_del_timer(timer->qtimer); | |
540 | } else if (timer->disabled) { | |
541 | qemu_del_timer(timer->qtimer); | |
542 | } else { | |
543 | qemu_mod_timer(timer->qtimer, expires); | |
544 | } | |
f4b1a842 BS |
545 | } |
546 | ||
361dea40 | 547 | static void isa_irq_handler(void *opaque, int n, int level) |
1387fe4a | 548 | { |
361dea40 BS |
549 | static const int isa_irq_to_ivec[16] = { |
550 | [1] = 0x29, /* keyboard */ | |
551 | [4] = 0x2b, /* serial */ | |
552 | [6] = 0x27, /* floppy */ | |
553 | [7] = 0x22, /* parallel */ | |
554 | [12] = 0x2a, /* mouse */ | |
555 | }; | |
556 | qemu_irq *irqs = opaque; | |
557 | int ivec; | |
558 | ||
559 | assert(n < 16); | |
560 | ivec = isa_irq_to_ivec[n]; | |
561 | EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); | |
562 | if (ivec) { | |
563 | qemu_set_irq(irqs[ivec], level); | |
564 | } | |
1387fe4a BS |
565 | } |
566 | ||
c190ea07 | 567 | /* EBUS (Eight bit bus) bridge */ |
48a18b3c | 568 | static ISABus * |
361dea40 | 569 | pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs) |
c190ea07 | 570 | { |
1387fe4a | 571 | qemu_irq *isa_irq; |
ab953e28 | 572 | PCIDevice *pci_dev; |
48a18b3c | 573 | ISABus *isa_bus; |
1387fe4a | 574 | |
ab953e28 HP |
575 | pci_dev = pci_create_simple(bus, devfn, "ebus"); |
576 | isa_bus = DO_UPCAST(ISABus, qbus, | |
577 | qdev_get_child_bus(&pci_dev->qdev, "isa.0")); | |
361dea40 | 578 | isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); |
48a18b3c HP |
579 | isa_bus_irqs(isa_bus, isa_irq); |
580 | return isa_bus; | |
53e3c4f9 | 581 | } |
c190ea07 | 582 | |
81a322d4 | 583 | static int |
c5e6fb7e | 584 | pci_ebus_init1(PCIDevice *pci_dev) |
53e3c4f9 | 585 | { |
c5e6fb7e AK |
586 | EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); |
587 | ||
c2d0d012 | 588 | isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev)); |
c5e6fb7e AK |
589 | |
590 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem | |
591 | pci_dev->config[0x05] = 0x00; | |
592 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
593 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
594 | pci_dev->config[0x09] = 0x00; // programming i/f | |
595 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
596 | ||
597 | isa_mmio_setup(&s->bar0, 0x1000000); | |
e824b2cc | 598 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
c5e6fb7e | 599 | isa_mmio_setup(&s->bar1, 0x800000); |
e824b2cc | 600 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1); |
81a322d4 | 601 | return 0; |
c190ea07 BS |
602 | } |
603 | ||
40021f08 AL |
604 | static void ebus_class_init(ObjectClass *klass, void *data) |
605 | { | |
606 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
607 | ||
608 | k->init = pci_ebus_init1; | |
609 | k->vendor_id = PCI_VENDOR_ID_SUN; | |
610 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
611 | k->revision = 0x01; | |
612 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
613 | } | |
614 | ||
39bffca2 AL |
615 | static TypeInfo ebus_info = { |
616 | .name = "ebus", | |
617 | .parent = TYPE_PCI_DEVICE, | |
618 | .instance_size = sizeof(EbusState), | |
619 | .class_init = ebus_class_init, | |
53e3c4f9 BS |
620 | }; |
621 | ||
d4edce38 AK |
622 | typedef struct PROMState { |
623 | SysBusDevice busdev; | |
624 | MemoryRegion prom; | |
625 | } PROMState; | |
626 | ||
409dbce5 AJ |
627 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
628 | { | |
629 | target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque; | |
630 | return addr + *base_addr - PROM_VADDR; | |
631 | } | |
632 | ||
1baffa46 | 633 | /* Boot PROM (OpenBIOS) */ |
c227f099 | 634 | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
1baffa46 BS |
635 | { |
636 | DeviceState *dev; | |
637 | SysBusDevice *s; | |
638 | char *filename; | |
639 | int ret; | |
640 | ||
641 | dev = qdev_create(NULL, "openprom"); | |
e23a1b33 | 642 | qdev_init_nofail(dev); |
1baffa46 BS |
643 | s = sysbus_from_qdev(dev); |
644 | ||
645 | sysbus_mmio_map(s, 0, addr); | |
646 | ||
647 | /* load boot prom */ | |
648 | if (bios_name == NULL) { | |
649 | bios_name = PROM_FILENAME; | |
650 | } | |
651 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
652 | if (filename) { | |
409dbce5 AJ |
653 | ret = load_elf(filename, translate_prom_address, &addr, |
654 | NULL, NULL, NULL, 1, ELF_MACHINE, 0); | |
1baffa46 BS |
655 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
656 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
657 | } | |
7267c094 | 658 | g_free(filename); |
1baffa46 BS |
659 | } else { |
660 | ret = -1; | |
661 | } | |
662 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
663 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
664 | exit(1); | |
665 | } | |
666 | } | |
667 | ||
81a322d4 | 668 | static int prom_init1(SysBusDevice *dev) |
1baffa46 | 669 | { |
d4edce38 | 670 | PROMState *s = FROM_SYSBUS(PROMState, dev); |
1baffa46 | 671 | |
c5705a77 AK |
672 | memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX); |
673 | vmstate_register_ram_global(&s->prom); | |
d4edce38 | 674 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 675 | sysbus_init_mmio(dev, &s->prom); |
81a322d4 | 676 | return 0; |
1baffa46 BS |
677 | } |
678 | ||
999e12bb AL |
679 | static Property prom_properties[] = { |
680 | {/* end of property list */}, | |
681 | }; | |
682 | ||
683 | static void prom_class_init(ObjectClass *klass, void *data) | |
684 | { | |
39bffca2 | 685 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
686 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
687 | ||
688 | k->init = prom_init1; | |
39bffca2 | 689 | dc->props = prom_properties; |
999e12bb AL |
690 | } |
691 | ||
39bffca2 AL |
692 | static TypeInfo prom_info = { |
693 | .name = "openprom", | |
694 | .parent = TYPE_SYS_BUS_DEVICE, | |
695 | .instance_size = sizeof(PROMState), | |
696 | .class_init = prom_class_init, | |
1baffa46 BS |
697 | }; |
698 | ||
bda42033 BS |
699 | |
700 | typedef struct RamDevice | |
701 | { | |
702 | SysBusDevice busdev; | |
d4edce38 | 703 | MemoryRegion ram; |
04843626 | 704 | uint64_t size; |
bda42033 BS |
705 | } RamDevice; |
706 | ||
707 | /* System RAM */ | |
81a322d4 | 708 | static int ram_init1(SysBusDevice *dev) |
bda42033 | 709 | { |
bda42033 BS |
710 | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
711 | ||
c5705a77 AK |
712 | memory_region_init_ram(&d->ram, "sun4u.ram", d->size); |
713 | vmstate_register_ram_global(&d->ram); | |
750ecd44 | 714 | sysbus_init_mmio(dev, &d->ram); |
81a322d4 | 715 | return 0; |
bda42033 BS |
716 | } |
717 | ||
c227f099 | 718 | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) |
bda42033 BS |
719 | { |
720 | DeviceState *dev; | |
721 | SysBusDevice *s; | |
722 | RamDevice *d; | |
723 | ||
724 | /* allocate RAM */ | |
725 | dev = qdev_create(NULL, "memory"); | |
726 | s = sysbus_from_qdev(dev); | |
727 | ||
728 | d = FROM_SYSBUS(RamDevice, s); | |
729 | d->size = RAM_size; | |
e23a1b33 | 730 | qdev_init_nofail(dev); |
bda42033 BS |
731 | |
732 | sysbus_mmio_map(s, 0, addr); | |
733 | } | |
734 | ||
999e12bb AL |
735 | static Property ram_properties[] = { |
736 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
737 | DEFINE_PROP_END_OF_LIST(), | |
738 | }; | |
739 | ||
740 | static void ram_class_init(ObjectClass *klass, void *data) | |
741 | { | |
39bffca2 | 742 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
743 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
744 | ||
745 | k->init = ram_init1; | |
39bffca2 | 746 | dc->props = ram_properties; |
999e12bb AL |
747 | } |
748 | ||
39bffca2 AL |
749 | static TypeInfo ram_info = { |
750 | .name = "memory", | |
751 | .parent = TYPE_SYS_BUS_DEVICE, | |
752 | .instance_size = sizeof(RamDevice), | |
753 | .class_init = ram_class_init, | |
bda42033 BS |
754 | }; |
755 | ||
f9d1465f | 756 | static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
3475187d | 757 | { |
8ebdf9dc | 758 | SPARCCPU *cpu; |
98cec4a2 | 759 | CPUSPARCState *env; |
e87231d4 | 760 | ResetData *reset_info; |
3475187d | 761 | |
8f4efc55 IK |
762 | uint32_t tick_frequency = 100*1000000; |
763 | uint32_t stick_frequency = 100*1000000; | |
764 | uint32_t hstick_frequency = 100*1000000; | |
765 | ||
8ebdf9dc | 766 | if (cpu_model == NULL) { |
c7ba218d | 767 | cpu_model = hwdef->default_cpu_model; |
8ebdf9dc AF |
768 | } |
769 | cpu = cpu_sparc_init(cpu_model); | |
770 | if (cpu == NULL) { | |
62724a37 BS |
771 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); |
772 | exit(1); | |
773 | } | |
8ebdf9dc | 774 | env = &cpu->env; |
20c9f095 | 775 | |
8f4efc55 IK |
776 | env->tick = cpu_timer_create("tick", env, tick_irq, |
777 | tick_frequency, TICK_NPT_MASK); | |
778 | ||
779 | env->stick = cpu_timer_create("stick", env, stick_irq, | |
780 | stick_frequency, TICK_INT_DIS); | |
20c9f095 | 781 | |
8f4efc55 IK |
782 | env->hstick = cpu_timer_create("hstick", env, hstick_irq, |
783 | hstick_frequency, TICK_INT_DIS); | |
e87231d4 | 784 | |
7267c094 | 785 | reset_info = g_malloc0(sizeof(ResetData)); |
403d7a2d | 786 | reset_info->cpu = cpu; |
44a99354 | 787 | reset_info->prom_addr = hwdef->prom_addr; |
a08d4367 | 788 | qemu_register_reset(main_cpu_reset, reset_info); |
c68ea704 | 789 | |
f9d1465f | 790 | return cpu; |
7b833f5b BS |
791 | } |
792 | ||
38bc50f7 RH |
793 | static void sun4uv_init(MemoryRegion *address_space_mem, |
794 | ram_addr_t RAM_size, | |
7b833f5b BS |
795 | const char *boot_devices, |
796 | const char *kernel_filename, const char *kernel_cmdline, | |
797 | const char *initrd_filename, const char *cpu_model, | |
798 | const struct hwdef *hwdef) | |
799 | { | |
f9d1465f | 800 | SPARCCPU *cpu; |
98cec4a2 | 801 | CPUSPARCState *env; |
43a34704 | 802 | M48t59State *nvram; |
7b833f5b | 803 | unsigned int i; |
5f2bf0fe | 804 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
7b833f5b | 805 | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
48a18b3c | 806 | ISABus *isa_bus; |
361dea40 | 807 | qemu_irq *ivec_irqs, *pbm_irqs; |
f455e98c | 808 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 809 | DriveInfo *fd[MAX_FD]; |
7b833f5b BS |
810 | void *fw_cfg; |
811 | ||
7b833f5b | 812 | /* init CPUs */ |
f9d1465f AF |
813 | cpu = cpu_devinit(cpu_model, hwdef); |
814 | env = &cpu->env; | |
7b833f5b | 815 | |
bda42033 BS |
816 | /* set up devices */ |
817 | ram_init(0, RAM_size); | |
3475187d | 818 | |
1baffa46 | 819 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 820 | |
361dea40 BS |
821 | ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, env, IVEC_MAX); |
822 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, | |
823 | &pci_bus3, &pbm_irqs); | |
78895427 | 824 | pci_vga_init(pci_bus); |
83469015 | 825 | |
c190ea07 | 826 | // XXX Should be pci_bus3 |
361dea40 | 827 | isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs); |
c190ea07 | 828 | |
e87231d4 BS |
829 | i = 0; |
830 | if (hwdef->console_serial_base) { | |
38bc50f7 | 831 | serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, |
39186d8a | 832 | NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); |
e87231d4 BS |
833 | i++; |
834 | } | |
835 | for(; i < MAX_SERIAL_PORTS; i++) { | |
83469015 | 836 | if (serial_hds[i]) { |
48a18b3c | 837 | serial_isa_init(isa_bus, i, serial_hds[i]); |
83469015 FB |
838 | } |
839 | } | |
840 | ||
841 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
842 | if (parallel_hds[i]) { | |
48a18b3c | 843 | parallel_init(isa_bus, i, parallel_hds[i]); |
83469015 FB |
844 | } |
845 | } | |
846 | ||
cb457d76 | 847 | for(i = 0; i < nb_nics; i++) |
07caea31 | 848 | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
83469015 | 849 | |
75717903 | 850 | ide_drive_get(hd, MAX_IDE_BUS); |
e4bcb14c | 851 | |
3b898dda BS |
852 | pci_cmd646_ide_init(pci_bus, hd, 1); |
853 | ||
48a18b3c | 854 | isa_create_simple(isa_bus, "i8042"); |
e4bcb14c | 855 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 856 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 857 | } |
48a18b3c HP |
858 | fdctrl_init_isa(isa_bus, fd); |
859 | nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); | |
636aa70a BS |
860 | |
861 | initrd_size = 0; | |
5f2bf0fe | 862 | initrd_addr = 0; |
636aa70a | 863 | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
5f2bf0fe BS |
864 | ram_size, &initrd_size, &initrd_addr, |
865 | &kernel_addr, &kernel_entry); | |
636aa70a | 866 | |
22548760 | 867 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices, |
5f2bf0fe | 868 | kernel_addr, kernel_size, |
0d31cb99 | 869 | kernel_cmdline, |
5f2bf0fe | 870 | initrd_addr, initrd_size, |
0d31cb99 BS |
871 | /* XXX: need an option to load a NVRAM image */ |
872 | 0, | |
873 | graphic_width, graphic_height, graphic_depth, | |
874 | (uint8_t *)&nd_table[0].macaddr); | |
83469015 | 875 | |
3cce6243 BS |
876 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
877 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 BS |
878 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
879 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
5f2bf0fe BS |
880 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
881 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
513f789f | 882 | if (kernel_cmdline) { |
9c9b0512 BS |
883 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
884 | strlen(kernel_cmdline) + 1); | |
6bb4ca57 BS |
885 | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
886 | (uint8_t*)strdup(kernel_cmdline), | |
887 | strlen(kernel_cmdline) + 1); | |
513f789f | 888 | } else { |
9c9b0512 | 889 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f | 890 | } |
5f2bf0fe BS |
891 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
892 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
513f789f | 893 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]); |
7589690c BS |
894 | |
895 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
896 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
897 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
898 | ||
513f789f | 899 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
900 | } |
901 | ||
905fdcb5 BS |
902 | enum { |
903 | sun4u_id = 0, | |
904 | sun4v_id = 64, | |
e87231d4 | 905 | niagara_id, |
905fdcb5 BS |
906 | }; |
907 | ||
c7ba218d BS |
908 | static const struct hwdef hwdefs[] = { |
909 | /* Sun4u generic PC-like machine */ | |
910 | { | |
5910b047 | 911 | .default_cpu_model = "TI UltraSparc IIi", |
905fdcb5 | 912 | .machine_id = sun4u_id, |
e87231d4 BS |
913 | .prom_addr = 0x1fff0000000ULL, |
914 | .console_serial_base = 0, | |
c7ba218d BS |
915 | }, |
916 | /* Sun4v generic PC-like machine */ | |
917 | { | |
918 | .default_cpu_model = "Sun UltraSparc T1", | |
905fdcb5 | 919 | .machine_id = sun4v_id, |
e87231d4 BS |
920 | .prom_addr = 0x1fff0000000ULL, |
921 | .console_serial_base = 0, | |
922 | }, | |
923 | /* Sun4v generic Niagara machine */ | |
924 | { | |
925 | .default_cpu_model = "Sun UltraSparc T1", | |
926 | .machine_id = niagara_id, | |
927 | .prom_addr = 0xfff0000000ULL, | |
928 | .console_serial_base = 0xfff0c2c000ULL, | |
c7ba218d BS |
929 | }, |
930 | }; | |
931 | ||
932 | /* Sun4u hardware initialisation */ | |
c227f099 | 933 | static void sun4u_init(ram_addr_t RAM_size, |
3023f332 | 934 | const char *boot_devices, |
c7ba218d BS |
935 | const char *kernel_filename, const char *kernel_cmdline, |
936 | const char *initrd_filename, const char *cpu_model) | |
937 | { | |
38bc50f7 | 938 | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
c7ba218d BS |
939 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]); |
940 | } | |
941 | ||
942 | /* Sun4v hardware initialisation */ | |
c227f099 | 943 | static void sun4v_init(ram_addr_t RAM_size, |
3023f332 | 944 | const char *boot_devices, |
c7ba218d BS |
945 | const char *kernel_filename, const char *kernel_cmdline, |
946 | const char *initrd_filename, const char *cpu_model) | |
947 | { | |
38bc50f7 | 948 | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
c7ba218d BS |
949 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]); |
950 | } | |
951 | ||
e87231d4 | 952 | /* Niagara hardware initialisation */ |
c227f099 | 953 | static void niagara_init(ram_addr_t RAM_size, |
3023f332 | 954 | const char *boot_devices, |
e87231d4 BS |
955 | const char *kernel_filename, const char *kernel_cmdline, |
956 | const char *initrd_filename, const char *cpu_model) | |
957 | { | |
38bc50f7 | 958 | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
e87231d4 BS |
959 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]); |
960 | } | |
961 | ||
f80f9ec9 | 962 | static QEMUMachine sun4u_machine = { |
66de733b BS |
963 | .name = "sun4u", |
964 | .desc = "Sun4u platform", | |
965 | .init = sun4u_init, | |
1bcee014 | 966 | .max_cpus = 1, // XXX for now |
0c257437 | 967 | .is_default = 1, |
3475187d | 968 | }; |
c7ba218d | 969 | |
f80f9ec9 | 970 | static QEMUMachine sun4v_machine = { |
66de733b BS |
971 | .name = "sun4v", |
972 | .desc = "Sun4v platform", | |
973 | .init = sun4v_init, | |
1bcee014 | 974 | .max_cpus = 1, // XXX for now |
c7ba218d | 975 | }; |
e87231d4 | 976 | |
f80f9ec9 | 977 | static QEMUMachine niagara_machine = { |
e87231d4 BS |
978 | .name = "Niagara", |
979 | .desc = "Sun4v platform, Niagara", | |
980 | .init = niagara_init, | |
1bcee014 | 981 | .max_cpus = 1, // XXX for now |
e87231d4 | 982 | }; |
f80f9ec9 | 983 | |
83f7d43a AF |
984 | static void sun4u_register_types(void) |
985 | { | |
986 | type_register_static(&ebus_info); | |
987 | type_register_static(&prom_info); | |
988 | type_register_static(&ram_info); | |
989 | } | |
990 | ||
f80f9ec9 AL |
991 | static void sun4u_machine_init(void) |
992 | { | |
993 | qemu_register_machine(&sun4u_machine); | |
994 | qemu_register_machine(&sun4v_machine); | |
995 | qemu_register_machine(&niagara_machine); | |
996 | } | |
997 | ||
83f7d43a | 998 | type_init(sun4u_register_types) |
f80f9ec9 | 999 | machine_init(sun4u_machine_init); |