]> git.proxmox.com Git - mirror_qemu.git/blame - target/i386/kvm.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i386/cpu/hyperv: support over 64 vcpus for windows guests
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c
AS		 29#include "hyperv.h"
30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
022c62cb 42#include "exec/ioport.h"
73aa529a 43#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 44#include "hw/pci/pci.h"
15eafc2e 45#include "hw/pci/msi.h"
fd563564 46#include "hw/pci/msix.h"
795c40b8 47#include "migration/blocker.h"
4c663752 48#include "exec/memattrs.h"
8b5ed7df 49#include "trace.h"
05330448
AL		 50
51//#define DEBUG_KVM
52
53#ifdef DEBUG_KVM
8c0d577e 54#define DPRINTF(fmt, ...) \
05330448
AL		 55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56#else
8c0d577e 57#define DPRINTF(fmt, ...) \
05330448
AL		 58 do { } while (0)
59#endif
60
1a03675d
GC		 61#define MSR_KVM_WALL_CLOCK 0x11
62#define MSR_KVM_SYSTEM_TIME 0x12
63
d1138251
EH		 64/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66#define MSR_BUF_SIZE 4096
d71b62a1 67
94a8d39a
JK		 68const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73};
25d2e361 74
c3a3a7d3
JK		 75static bool has_msr_star;
76static bool has_msr_hsave_pa;
c9b8f6b6 77static bool has_msr_tsc_aux;
f28558d3 78static bool has_msr_tsc_adjust;
aa82ba54 79static bool has_msr_tsc_deadline;
df67696e 80static bool has_msr_feature_control;
21e87c46 81static bool has_msr_misc_enable;
fc12d72e 82static bool has_msr_smbase;
79e9ebeb 83static bool has_msr_bndcfgs;
25d2e361 84static int lm_capable_kernel;
7bc3d711 85static bool has_msr_hv_hypercall;
f2a53c9e 86static bool has_msr_hv_crash;
744b8a94 87static bool has_msr_hv_reset;
8c145d7c 88static bool has_msr_hv_vpindex;
46eb8f98 89static bool has_msr_hv_runtime;
866eea9a 90static bool has_msr_hv_synic;
ff99aa64 91static bool has_msr_hv_stimer;
d72bc7f6 92static bool has_msr_hv_frequencies;
18cd2c17 93static bool has_msr_xss;
b827df58 94
0d894367
PB		 95static bool has_msr_architectural_pmu;
96static uint32_t num_architectural_pmu_counters;
97
28143b40
TH		 98static int has_xsave;
99static int has_xcrs;
100static int has_pit_state2;
101
87f8b626
AR		 102static bool has_msr_mcg_ext_ctl;
103
494e95e9
CP		 104static struct kvm_cpuid2 *cpuid_cache;
105
28143b40
TH		 106int kvm_has_pit_state2(void)
107{
108 return has_pit_state2;
109}
110
355023f2
PB		 111bool kvm_has_smm(void)
112{
113 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
114}
115
6053a86f
MT		 116bool kvm_has_adjust_clock_stable(void)
117{
118 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
119
120 return (ret == KVM_CLOCK_TSC_STABLE);
121}
122
1d31f66b
PM		 123bool kvm_allows_irq0_override(void)
124{
125 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
126}
127
fb506e70
RK		 128static bool kvm_x2apic_api_set_flags(uint64_t flags)
129{
130 KVMState *s = KVM_STATE(current_machine->accelerator);
131
132 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
133}
134
e391c009 135#define MEMORIZE(fn, _result) \
2a138ec3 136 ({ \
2a138ec3
RK		 137 static bool _memorized; \
138 \
139 if (_memorized) { \
140 return _result; \
141 } \
142 _memorized = true; \
143 _result = fn; \
144 })
145
e391c009
IM		 146static bool has_x2apic_api;
147
148bool kvm_has_x2apic_api(void)
149{
150 return has_x2apic_api;
151}
152
fb506e70
RK		 153bool kvm_enable_x2apic(void)
154{
2a138ec3
RK		 155 return MEMORIZE(
156 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 157 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
158 has_x2apic_api);
fb506e70
RK		 159}
160
0fd7e098
LL		 161static int kvm_get_tsc(CPUState *cs)
162{
163 X86CPU *cpu = X86_CPU(cs);
164 CPUX86State *env = &cpu->env;
165 struct {
166 struct kvm_msrs info;
167 struct kvm_msr_entry entries[1];
168 } msr_data;
169 int ret;
170
171 if (env->tsc_valid) {
172 return 0;
173 }
174
175 msr_data.info.nmsrs = 1;
176 msr_data.entries[0].index = MSR_IA32_TSC;
177 env->tsc_valid = !runstate_is_running();
178
179 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
180 if (ret < 0) {
181 return ret;
182 }
183
48e1a45c 184 assert(ret == 1);
0fd7e098
LL		 185 env->tsc = msr_data.entries[0].data;
186 return 0;
187}
188
14e6fe12 189static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 190{
0fd7e098
LL		 191 kvm_get_tsc(cpu);
192}
193
194void kvm_synchronize_all_tsc(void)
195{
196 CPUState *cpu;
197
198 if (kvm_enabled()) {
199 CPU_FOREACH(cpu) {
14e6fe12 200 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 201 }
202 }
203}
204
b827df58
AK		 205static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
206{
207 struct kvm_cpuid2 *cpuid;
208 int r, size;
209
210 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 211 cpuid = g_malloc0(size);
b827df58
AK		 212 cpuid->nent = max;
213 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 214 if (r == 0 && cpuid->nent >= max) {
215 r = -E2BIG;
216 }
b827df58
AK		 217 if (r < 0) {
218 if (r == -E2BIG) {
7267c094 219 g_free(cpuid);
b827df58
AK		 220 return NULL;
221 } else {
222 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
223 strerror(-r));
224 exit(1);
225 }
226 }
227 return cpuid;
228}
229
dd87f8a6
EH		 230/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
231 * for all entries.
232 */
233static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
234{
235 struct kvm_cpuid2 *cpuid;
236 int max = 1;
494e95e9
CP		 237
238 if (cpuid_cache != NULL) {
239 return cpuid_cache;
240 }
dd87f8a6
EH		 241 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
242 max *= 2;
243 }
494e95e9 244 cpuid_cache = cpuid;
dd87f8a6
EH		 245 return cpuid;
246}
247
a443bc34 248static const struct kvm_para_features {
0c31b744
GC		 249 int cap;
250 int feature;
251} para_features[] = {
252 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
253 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
254 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 255 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 256};
257
ba9bc59e 258static int get_para_features(KVMState *s)
0c31b744
GC		 259{
260 int i, features = 0;
261
8e03c100 262 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 263 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 264 features |= (1 << para_features[i].feature);
265 }
266 }
267
268 return features;
269}
0c31b744 270
40e80ee4
EH		 271static bool host_tsx_blacklisted(void)
272{
273 int family, model, stepping;\
274 char vendor[CPUID_VENDOR_SZ + 1];
275
276 host_vendor_fms(vendor, &family, &model, &stepping);
277
278 /* Check if we are running on a Haswell host known to have broken TSX */
279 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
280 (family == 6) &&
281 ((model == 63 && stepping < 4) ||
282 model == 60 || model == 69 || model == 70);
283}
0c31b744 284
829ae2f9
EH		 285/* Returns the value for a specific register on the cpuid entry
286 */
287static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
288{
289 uint32_t ret = 0;
290 switch (reg) {
291 case R_EAX:
292 ret = entry->eax;
293 break;
294 case R_EBX:
295 ret = entry->ebx;
296 break;
297 case R_ECX:
298 ret = entry->ecx;
299 break;
300 case R_EDX:
301 ret = entry->edx;
302 break;
303 }
304 return ret;
305}
306
4fb73f1d
EH		 307/* Find matching entry for function/index on kvm_cpuid2 struct
308 */
309static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
310 uint32_t function,
311 uint32_t index)
312{
313 int i;
314 for (i = 0; i < cpuid->nent; ++i) {
315 if (cpuid->entries[i].function == function &&
316 cpuid->entries[i].index == index) {
317 return &cpuid->entries[i];
318 }
319 }
320 /* not found: */
321 return NULL;
322}
323
ba9bc59e 324uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 325 uint32_t index, int reg)
b827df58
AK		 326{
327 struct kvm_cpuid2 *cpuid;
b827df58
AK		 328 uint32_t ret = 0;
329 uint32_t cpuid_1_edx;
8c723b79 330 bool found = false;
b827df58 331
dd87f8a6 332 cpuid = get_supported_cpuid(s);
b827df58 333
4fb73f1d
EH		 334 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
335 if (entry) {
336 found = true;
337 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 338 }
339
7b46e5ce
EH		 340 /* Fixups for the data returned by KVM, below */
341
c2acb022
EH		 342 if (function == 1 && reg == R_EDX) {
343 /* KVM before 2.6.30 misreports the following features */
344 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 345 } else if (function == 1 && reg == R_ECX) {
346 /* We can set the hypervisor flag, even if KVM does not return it on
347 * GET_SUPPORTED_CPUID
348 */
349 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 350 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
351 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
352 * and the irqchip is in the kernel.
353 */
354 if (kvm_irqchip_in_kernel() &&
355 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
356 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
357 }
41e5e76d
EH		 358
359 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
360 * without the in-kernel irqchip
361 */
362 if (!kvm_irqchip_in_kernel()) {
363 ret &= ~CPUID_EXT_X2APIC;
b827df58 364 }
28b8e4d0
JK		 365 } else if (function == 6 && reg == R_EAX) {
366 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 367 } else if (function == 7 && index == 0 && reg == R_EBX) {
368 if (host_tsx_blacklisted()) {
369 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
370 }
c2acb022
EH		 371 } else if (function == 0x80000001 && reg == R_EDX) {
372 /* On Intel, kvm returns cpuid according to the Intel spec,
373 * so add missing bits according to the AMD spec:
374 */
375 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
376 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 377 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
378 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
379 * be enabled without the in-kernel irqchip
380 */
381 if (!kvm_irqchip_in_kernel()) {
382 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
383 }
b827df58
AK		 384 }
385
0c31b744 386 /* fallback for older kernels */
8c723b79 387 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 388 ret = get_para_features(s);
b9bec74b 389 }
0c31b744
GC		 390
391 return ret;
bb0300dc 392}
bb0300dc 393
3c85e74f
HY		 394typedef struct HWPoisonPage {
395 ram_addr_t ram_addr;
396 QLIST_ENTRY(HWPoisonPage) list;
397} HWPoisonPage;
398
399static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
400 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
401
402static void kvm_unpoison_all(void *param)
403{
404 HWPoisonPage *page, *next_page;
405
406 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
407 QLIST_REMOVE(page, list);
408 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 409 g_free(page);
3c85e74f
HY		 410 }
411}
412
3c85e74f
HY		 413static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
414{
415 HWPoisonPage *page;
416
417 QLIST_FOREACH(page, &hwpoison_page_list, list) {
418 if (page->ram_addr == ram_addr) {
419 return;
420 }
421 }
ab3ad07f 422 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 423 page->ram_addr = ram_addr;
424 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
425}
426
e7701825
MT		 427static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
428 int *max_banks)
429{
430 int r;
431
14a09518 432 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 433 if (r > 0) {
434 *max_banks = r;
435 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
436 }
437 return -ENOSYS;
438}
439
bee615d4 440static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 441{
87f8b626 442 CPUState *cs = CPU(cpu);
bee615d4 443 CPUX86State *env = &cpu->env;
c34d440a
JK		 444 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
445 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
446 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 447 int flags = 0;
e7701825 448
c34d440a
JK		 449 if (code == BUS_MCEERR_AR) {
450 status |= MCI_STATUS_AR | 0x134;
451 mcg_status |= MCG_STATUS_EIPV;
452 } else {
453 status |= 0xc0;
454 mcg_status |= MCG_STATUS_RIPV;
419fb20a 455 }
87f8b626
AR		 456
457 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
458 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
459 * guest kernel back into env->mcg_ext_ctl.
460 */
461 cpu_synchronize_state(cs);
462 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
463 mcg_status |= MCG_STATUS_LMCE;
464 flags = 0;
465 }
466
8c5cf3b6 467 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 468 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 469}
419fb20a
JK		 470
471static void hardware_memory_error(void)
472{
473 fprintf(stderr, "Hardware memory error!\n");
474 exit(1);
475}
476
2ae41db2 477void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 478{
20d695a9
AF		 479 X86CPU *cpu = X86_CPU(c);
480 CPUX86State *env = &cpu->env;
419fb20a 481 ram_addr_t ram_addr;
a8170e5e 482 hwaddr paddr;
419fb20a 483
4d39892c
PB		 484 /* If we get an action required MCE, it has been injected by KVM
485 * while the VM was running. An action optional MCE instead should
486 * be coming from the main thread, which qemu_init_sigbus identifies
487 * as the "early kill" thread.
488 */
a16fc07e 489 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 490
20e0ff59 491 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 492 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 493 if (ram_addr != RAM_ADDR_INVALID &&
494 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
495 kvm_hwpoison_page_add(ram_addr);
496 kvm_mce_inject(cpu, paddr, code);
2ae41db2 497 return;
419fb20a 498 }
20e0ff59
PB		 499
500 fprintf(stderr, "Hardware memory error for memory used by "
501 "QEMU itself instead of guest system!\n");
419fb20a 502 }
20e0ff59
PB		 503
504 if (code == BUS_MCEERR_AR) {
505 hardware_memory_error();
506 }
507
508 /* Hope we are lucky for AO MCE */
419fb20a
JK		 509}
510
1bc22652 511static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 512{
1bc22652
AF		 513 CPUX86State *env = &cpu->env;
514
ab443475
JK		 515 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
516 unsigned int bank, bank_num = env->mcg_cap & 0xff;
517 struct kvm_x86_mce mce;
518
519 env->exception_injected = -1;
520
521 /*
522 * There must be at least one bank in use if an MCE is pending.
523 * Find it and use its values for the event injection.
524 */
525 for (bank = 0; bank < bank_num; bank++) {
526 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
527 break;
528 }
529 }
530 assert(bank < bank_num);
531
532 mce.bank = bank;
533 mce.status = env->mce_banks[bank * 4 + 1];
534 mce.mcg_status = env->mcg_status;
535 mce.addr = env->mce_banks[bank * 4 + 2];
536 mce.misc = env->mce_banks[bank * 4 + 3];
537
1bc22652 538 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 539 }
ab443475
JK		 540 return 0;
541}
542
1dfb4dd9 543static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 544{
317ac620 545 CPUX86State *env = opaque;
b8cc45d6
GC		 546
547 if (running) {
548 env->tsc_valid = false;
549 }
550}
551
83b17af5 552unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 553{
83b17af5 554 X86CPU *cpu = X86_CPU(cs);
7e72a45c 555 return cpu->apic_id;
b164e48e
EH		 556}
557
92067bf4
IM		 558#ifndef KVM_CPUID_SIGNATURE_NEXT
559#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
560#endif
561
562static bool hyperv_hypercall_available(X86CPU *cpu)
563{
564 return cpu->hyperv_vapic ||
565 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
566}
567
568static bool hyperv_enabled(X86CPU *cpu)
569{
7bc3d711
PB		 570 CPUState *cs = CPU(cpu);
571 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
572 (hyperv_hypercall_available(cpu) ||
48a5f3bc 573 cpu->hyperv_time ||
f2a53c9e 574 cpu->hyperv_relaxed_timing ||
744b8a94 575 cpu->hyperv_crash ||
8c145d7c 576 cpu->hyperv_reset ||
46eb8f98 577 cpu->hyperv_vpindex ||
866eea9a 578 cpu->hyperv_runtime ||
ff99aa64
AS		 579 cpu->hyperv_synic ||
580 cpu->hyperv_stimer);
92067bf4
IM		 581}
582
5031283d
HZ		 583static int kvm_arch_set_tsc_khz(CPUState *cs)
584{
585 X86CPU *cpu = X86_CPU(cs);
586 CPUX86State *env = &cpu->env;
587 int r;
588
589 if (!env->tsc_khz) {
590 return 0;
591 }
592
593 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
594 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
595 -ENOTSUP;
596 if (r < 0) {
597 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
598 * TSC frequency doesn't match the one we want.
599 */
600 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
601 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
602 -ENOTSUP;
603 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 604 warn_report("TSC frequency mismatch between "
605 "VM (%" PRId64 " kHz) and host (%d kHz), "
606 "and TSC scaling unavailable",
607 env->tsc_khz, cur_freq);
5031283d
HZ		 608 return r;
609 }
610 }
611
612 return 0;
613}
614
4bb95b82
LP		 615static bool tsc_is_stable_and_known(CPUX86State *env)
616{
617 if (!env->tsc_khz) {
618 return false;
619 }
620 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
621 || env->user_tsc_khz;
622}
623
c35bd19a
EY		 624static int hyperv_handle_properties(CPUState *cs)
625{
626 X86CPU *cpu = X86_CPU(cs);
627 CPUX86State *env = &cpu->env;
628
3ddcd2ed
EH		 629 if (cpu->hyperv_time &&
630 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
631 cpu->hyperv_time = false;
632 }
633
c35bd19a
EY		 634 if (cpu->hyperv_relaxed_timing) {
635 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
636 }
637 if (cpu->hyperv_vapic) {
638 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
639 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
c35bd19a 640 }
3ddcd2ed 641 if (cpu->hyperv_time) {
c35bd19a
EY		 642 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
643 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
d72bc7f6
LP		 644 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_REFERENCE_TSC_AVAILABLE;
645
646 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
647 env->features[FEAT_HYPERV_EAX] |= HV_X64_ACCESS_FREQUENCY_MSRS;
648 env->features[FEAT_HYPERV_EDX] |=
649 HV_FEATURE_FREQUENCY_MSRS_AVAILABLE;
650 }
c35bd19a
EY		 651 }
652 if (cpu->hyperv_crash && has_msr_hv_crash) {
653 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
654 }
655 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
656 if (cpu->hyperv_reset && has_msr_hv_reset) {
657 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
658 }
659 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
660 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
661 }
662 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
663 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
664 }
665 if (cpu->hyperv_synic) {
666 int sint;
667
668 if (!has_msr_hv_synic ||
669 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
670 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
671 return -ENOSYS;
672 }
673
674 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
675 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
676 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
677 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
678 }
679 }
680 if (cpu->hyperv_stimer) {
681 if (!has_msr_hv_stimer) {
682 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
683 return -ENOSYS;
684 }
685 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
686 }
687 return 0;
688}
689
68bfd0ad
MT		 690static Error *invtsc_mig_blocker;
691
f8bb0565 692#define KVM_MAX_CPUID_ENTRIES 100
0893d460 693
20d695a9 694int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 695{
696 struct {
486bd5a2 697 struct kvm_cpuid2 cpuid;
f8bb0565 698 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 699 } QEMU_PACKED cpuid_data;
20d695a9
AF		 700 X86CPU *cpu = X86_CPU(cs);
701 CPUX86State *env = &cpu->env;
486bd5a2 702 uint32_t limit, i, j, cpuid_i;
a33609ca 703 uint32_t unused;
bb0300dc 704 struct kvm_cpuid_entry2 *c;
bb0300dc 705 uint32_t signature[3];
234cc647 706 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 707 int r;
fe44dc91 708 Error *local_err = NULL;
05330448 709
ef4cbe14
SW		 710 memset(&cpuid_data, 0, sizeof(cpuid_data));
711
05330448
AL		 712 cpuid_i = 0;
713
ddb98b5a
LP		 714 r = kvm_arch_set_tsc_khz(cs);
715 if (r < 0) {
716 goto fail;
717 }
718
719 /* vcpu's TSC frequency is either specified by user, or following
720 * the value used by KVM if the former is not present. In the
721 * latter case, we query it from KVM and record in env->tsc_khz,
722 * so that vcpu's TSC frequency can be migrated later via this field.
723 */
724 if (!env->tsc_khz) {
725 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
726 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
727 -ENOTSUP;
728 if (r > 0) {
729 env->tsc_khz = r;
730 }
731 }
732
bb0300dc 733 /* Paravirtualization CPUIDs */
234cc647
PB		 734 if (hyperv_enabled(cpu)) {
735 c = &cpuid_data.entries[cpuid_i++];
736 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 737 if (!cpu->hyperv_vendor_id) {
738 memcpy(signature, "Microsoft Hv", 12);
739 } else {
740 size_t len = strlen(cpu->hyperv_vendor_id);
741
742 if (len > 12) {
743 error_report("hv-vendor-id truncated to 12 characters");
744 len = 12;
745 }
746 memset(signature, 0, 12);
747 memcpy(signature, cpu->hyperv_vendor_id, len);
748 }
eab70139 749 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 750 c->ebx = signature[0];
751 c->ecx = signature[1];
752 c->edx = signature[2];
0c31b744 753
234cc647
PB		 754 c = &cpuid_data.entries[cpuid_i++];
755 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 756 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
757 c->eax = signature[0];
234cc647
PB		 758 c->ebx = 0;
759 c->ecx = 0;
760 c->edx = 0;
eab70139
VR		 761
762 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 763 c->function = HYPERV_CPUID_VERSION;
764 c->eax = 0x00001bbc;
765 c->ebx = 0x00060001;
766
767 c = &cpuid_data.entries[cpuid_i++];
eab70139 768 c->function = HYPERV_CPUID_FEATURES;
c35bd19a
EY		 769 r = hyperv_handle_properties(cs);
770 if (r) {
771 return r;
46eb8f98 772 }
c35bd19a
EY		 773 c->eax = env->features[FEAT_HYPERV_EAX];
774 c->ebx = env->features[FEAT_HYPERV_EBX];
775 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 776
eab70139 777 c = &cpuid_data.entries[cpuid_i++];
eab70139 778 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 779 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 780 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
781 }
2d5aa872 782 if (cpu->hyperv_vapic) {
eab70139
VR		 783 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
784 }
92067bf4 785 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 786
787 c = &cpuid_data.entries[cpuid_i++];
eab70139 788 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 789
790 c->eax = cpu->hv_max_vps;
eab70139
VR		 791 c->ebx = 0x40;
792
234cc647 793 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 794 has_msr_hv_hypercall = true;
eab70139
VR		 795 }
796
f522d2ac
AW		 797 if (cpu->expose_kvm) {
798 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
799 c = &cpuid_data.entries[cpuid_i++];
800 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 801 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 802 c->ebx = signature[0];
803 c->ecx = signature[1];
804 c->edx = signature[2];
234cc647 805
f522d2ac
AW		 806 c = &cpuid_data.entries[cpuid_i++];
807 c->function = KVM_CPUID_FEATURES | kvm_base;
808 c->eax = env->features[FEAT_KVM];
f522d2ac 809 }
917367aa 810
a33609ca 811 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 812
813 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 814 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
815 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
816 abort();
817 }
bb0300dc 818 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 819
820 switch (i) {
a36b1029
AL		 821 case 2: {
822 /* Keep reading function 2 till all the input is received */
823 int times;
824
a36b1029 825 c->function = i;
a33609ca
AL		 826 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
827 KVM_CPUID_FLAG_STATE_READ_NEXT;
828 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
829 times = c->eax & 0xff;
a36b1029
AL		 830
831 for (j = 1; j < times; ++j) {
f8bb0565
IM		 832 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
833 fprintf(stderr, "cpuid_data is full, no space for "
834 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
835 abort();
836 }
a33609ca 837 c = &cpuid_data.entries[cpuid_i++];
a36b1029 838 c->function = i;
a33609ca
AL		 839 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
840 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 841 }
842 break;
843 }
486bd5a2
AL		 844 case 4:
845 case 0xb:
846 case 0xd:
847 for (j = 0; ; j++) {
31e8c696
AP		 848 if (i == 0xd && j == 64) {
849 break;
850 }
486bd5a2
AL		 851 c->function = i;
852 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
853 c->index = j;
a33609ca 854 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 855
b9bec74b 856 if (i == 4 && c->eax == 0) {
486bd5a2 857 break;
b9bec74b
JK		 858 }
859 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 860 break;
b9bec74b
JK		 861 }
862 if (i == 0xd && c->eax == 0) {
31e8c696 863 continue;
b9bec74b 864 }
f8bb0565
IM		 865 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
866 fprintf(stderr, "cpuid_data is full, no space for "
867 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
868 abort();
869 }
a33609ca 870 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 871 }
872 break;
873 default:
486bd5a2 874 c->function = i;
a33609ca
AL		 875 c->flags = 0;
876 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 877 break;
878 }
05330448 879 }
0d894367
PB		 880
881 if (limit >= 0x0a) {
882 uint32_t ver;
883
884 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
885 if ((ver & 0xff) > 0) {
886 has_msr_architectural_pmu = true;
887 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
888
889 /* Shouldn't be more than 32, since that's the number of bits
890 * available in EBX to tell us _which_ counters are available.
891 * Play it safe.
892 */
893 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
894 num_architectural_pmu_counters = MAX_GP_COUNTERS;
895 }
896 }
897 }
898
a33609ca 899 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 900
901 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 902 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
903 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
904 abort();
905 }
bb0300dc 906 c = &cpuid_data.entries[cpuid_i++];
05330448 907
05330448 908 c->function = i;
a33609ca
AL		 909 c->flags = 0;
910 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 911 }
912
b3baa152
BW		 913 /* Call Centaur's CPUID instructions they are supported. */
914 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 915 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
916
917 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 918 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
919 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
920 abort();
921 }
b3baa152
BW		 922 c = &cpuid_data.entries[cpuid_i++];
923
924 c->function = i;
925 c->flags = 0;
926 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
927 }
928 }
929
05330448
AL		 930 cpuid_data.cpuid.nent = cpuid_i;
931
e7701825 932 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 933 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 934 (CPUID_MCE | CPUID_MCA)
a60f24b5 935 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 936 uint64_t mcg_cap, unsupported_caps;
e7701825 937 int banks;
32a42024 938 int ret;
e7701825 939
a60f24b5 940 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 941 if (ret < 0) {
942 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
943 return ret;
e7701825 944 }
75d49497 945
2590f15b 946 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 947 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 948 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 949 return -ENOTSUP;
75d49497 950 }
49b69cbf 951
5120901a
EH		 952 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
953 if (unsupported_caps) {
87f8b626
AR		 954 if (unsupported_caps & MCG_LMCE_P) {
955 error_report("kvm: LMCE not supported");
956 return -ENOTSUP;
957 }
3dc6f869
AF		 958 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
959 unsupported_caps);
5120901a
EH		 960 }
961
2590f15b
EH		 962 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
963 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 964 if (ret < 0) {
965 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
966 return ret;
967 }
e7701825 968 }
e7701825 969
b8cc45d6
GC		 970 qemu_add_vm_change_state_handler(cpu_update_state, env);
971
df67696e
LJ		 972 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
973 if (c) {
974 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
975 !!(c->ecx & CPUID_EXT_SMX);
976 }
977
87f8b626
AR		 978 if (env->mcg_cap & MCG_LMCE_P) {
979 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
980 }
981
d99569d9
EH		 982 if (!env->user_tsc_khz) {
983 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
984 invtsc_mig_blocker == NULL) {
985 /* for migration */
986 error_setg(&invtsc_mig_blocker,
987 "State blocked by non-migratable CPU device"
988 " (invtsc flag)");
fe44dc91
AA		 989 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
990 if (local_err) {
991 error_report_err(local_err);
992 error_free(invtsc_mig_blocker);
993 goto fail;
994 }
d99569d9
EH		 995 /* for savevm */
996 vmstate_x86_cpu.unmigratable = 1;
997 }
68bfd0ad
MT		 998 }
999
9954a158
PDJ		 1000 if (cpu->vmware_cpuid_freq
1001 /* Guests depend on 0x40000000 to detect this feature, so only expose
1002 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1003 && cpu->expose_kvm
1004 && kvm_base == KVM_CPUID_SIGNATURE
1005 /* TSC clock must be stable and known for this feature. */
4bb95b82 1006 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1007
1008 c = &cpuid_data.entries[cpuid_i++];
1009 c->function = KVM_CPUID_SIGNATURE | 0x10;
1010 c->eax = env->tsc_khz;
1011 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1012 * APIC_BUS_CYCLE_NS */
1013 c->ebx = 1000000;
1014 c->ecx = c->edx = 0;
1015
1016 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1017 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1018 }
1019
1020 cpuid_data.cpuid.nent = cpuid_i;
1021
1022 cpuid_data.cpuid.padding = 0;
1023 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1024 if (r) {
1025 goto fail;
1026 }
1027
28143b40 1028 if (has_xsave) {
fabacc0f
JK		 1029 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1030 }
d71b62a1 1031 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1032
273c515c
PB		 1033 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1034 has_msr_tsc_aux = false;
1035 }
d1ae67f6 1036
e7429073 1037 return 0;
fe44dc91
AA		 1038
1039 fail:
1040 migrate_del_blocker(invtsc_mig_blocker);
1041 return r;
05330448
AL		 1042}
1043
50a2c6e5 1044void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1045{
20d695a9 1046 CPUX86State *env = &cpu->env;
dd673288 1047
e73223a5 1048 env->exception_injected = -1;
0e607a80 1049 env->interrupt_injected = -1;
1a5e9d2f 1050 env->xcr0 = 1;
ddced198 1051 if (kvm_irqchip_in_kernel()) {
dd673288 1052 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1053 KVM_MP_STATE_UNINITIALIZED;
1054 } else {
1055 env->mp_state = KVM_MP_STATE_RUNNABLE;
1056 }
caa5af0f
JK		 1057}
1058
e0723c45
PB		 1059void kvm_arch_do_init_vcpu(X86CPU *cpu)
1060{
1061 CPUX86State *env = &cpu->env;
1062
1063 /* APs get directly into wait-for-SIPI state. */
1064 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1065 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1066 }
1067}
1068
c3a3a7d3 1069static int kvm_get_supported_msrs(KVMState *s)
05330448 1070{
75b10c43 1071 static int kvm_supported_msrs;
c3a3a7d3 1072 int ret = 0;
05330448
AL		 1073
1074 /* first time */
75b10c43 1075 if (kvm_supported_msrs == 0) {
05330448
AL		 1076 struct kvm_msr_list msr_list, *kvm_msr_list;
1077
75b10c43 1078 kvm_supported_msrs = -1;
05330448
AL		 1079
1080 /* Obtain MSR list from KVM. These are the MSRs that we must
1081 * save/restore */
4c9f7372 1082 msr_list.nmsrs = 0;
c3a3a7d3 1083 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1084 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1085 return ret;
6fb6d245 1086 }
d9db889f
JK		 1087 /* Old kernel modules had a bug and could write beyond the provided
1088 memory. Allocate at least a safe amount of 1K. */
7267c094 1089 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1090 msr_list.nmsrs *
1091 sizeof(msr_list.indices[0])));
05330448 1092
55308450 1093 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1094 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1095 if (ret >= 0) {
1096 int i;
1097
1098 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1099 switch (kvm_msr_list->indices[i]) {
1100 case MSR_STAR:
c3a3a7d3 1101 has_msr_star = true;
1d268dec
LP		 1102 break;
1103 case MSR_VM_HSAVE_PA:
c3a3a7d3 1104 has_msr_hsave_pa = true;
1d268dec
LP		 1105 break;
1106 case MSR_TSC_AUX:
c9b8f6b6 1107 has_msr_tsc_aux = true;
1d268dec
LP		 1108 break;
1109 case MSR_TSC_ADJUST:
f28558d3 1110 has_msr_tsc_adjust = true;
1d268dec
LP		 1111 break;
1112 case MSR_IA32_TSCDEADLINE:
aa82ba54 1113 has_msr_tsc_deadline = true;
1d268dec
LP		 1114 break;
1115 case MSR_IA32_SMBASE:
fc12d72e 1116 has_msr_smbase = true;
1d268dec
LP		 1117 break;
1118 case MSR_IA32_MISC_ENABLE:
21e87c46 1119 has_msr_misc_enable = true;
1d268dec
LP		 1120 break;
1121 case MSR_IA32_BNDCFGS:
79e9ebeb 1122 has_msr_bndcfgs = true;
1d268dec
LP		 1123 break;
1124 case MSR_IA32_XSS:
18cd2c17 1125 has_msr_xss = true;
1d268dec
LP		 1126 break;;
1127 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1128 has_msr_hv_crash = true;
1d268dec
LP		 1129 break;
1130 case HV_X64_MSR_RESET:
744b8a94 1131 has_msr_hv_reset = true;
1d268dec
LP		 1132 break;
1133 case HV_X64_MSR_VP_INDEX:
8c145d7c 1134 has_msr_hv_vpindex = true;
1d268dec
LP		 1135 break;
1136 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1137 has_msr_hv_runtime = true;
1d268dec
LP		 1138 break;
1139 case HV_X64_MSR_SCONTROL:
866eea9a 1140 has_msr_hv_synic = true;
1d268dec
LP		 1141 break;
1142 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1143 has_msr_hv_stimer = true;
1d268dec 1144 break;
d72bc7f6
LP		 1145 case HV_X64_MSR_TSC_FREQUENCY:
1146 has_msr_hv_frequencies = true;
1147 break;
ff99aa64 1148 }
05330448
AL		 1149 }
1150 }
1151
7267c094 1152 g_free(kvm_msr_list);
05330448
AL		 1153 }
1154
c3a3a7d3 1155 return ret;
05330448
AL		 1156}
1157
6410848b
PB		 1158static Notifier smram_machine_done;
1159static KVMMemoryListener smram_listener;
1160static AddressSpace smram_address_space;
1161static MemoryRegion smram_as_root;
1162static MemoryRegion smram_as_mem;
1163
1164static void register_smram_listener(Notifier *n, void *unused)
1165{
1166 MemoryRegion *smram =
1167 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1168
1169 /* Outer container... */
1170 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1171 memory_region_set_enabled(&smram_as_root, true);
1172
1173 /* ... with two regions inside: normal system memory with low
1174 * priority, and...
1175 */
1176 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1177 get_system_memory(), 0, ~0ull);
1178 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1179 memory_region_set_enabled(&smram_as_mem, true);
1180
1181 if (smram) {
1182 /* ... SMRAM with higher priority */
1183 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1184 memory_region_set_enabled(smram, true);
1185 }
1186
1187 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1188 kvm_memory_listener_register(kvm_state, &smram_listener,
1189 &smram_address_space, 1);
1190}
1191
b16565b3 1192int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1193{
11076198 1194 uint64_t identity_base = 0xfffbc000;
39d6960a 1195 uint64_t shadow_mem;
20420430 1196 int ret;
25d2e361 1197 struct utsname utsname;
20420430 1198
28143b40
TH		 1199#ifdef KVM_CAP_XSAVE
1200 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1201#endif
1202
1203#ifdef KVM_CAP_XCRS
1204 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1205#endif
1206
1207#ifdef KVM_CAP_PIT_STATE2
1208 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1209#endif
1210
c3a3a7d3 1211 ret = kvm_get_supported_msrs(s);
20420430 1212 if (ret < 0) {
20420430
SY		 1213 return ret;
1214 }
25d2e361
MT		 1215
1216 uname(&utsname);
1217 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1218
4c5b10b7 1219 /*
11076198
JK		 1220 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1221 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1222 * Since these must be part of guest physical memory, we need to allocate
1223 * them, both by setting their start addresses in the kernel and by
1224 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1225 *
1226 * Older KVM versions may not support setting the identity map base. In
1227 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1228 * size.
4c5b10b7 1229 */
11076198
JK		 1230 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1231 /* Allows up to 16M BIOSes. */
1232 identity_base = 0xfeffc000;
1233
1234 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1235 if (ret < 0) {
1236 return ret;
1237 }
4c5b10b7 1238 }
e56ff191 1239
11076198
JK		 1240 /* Set TSS base one page after EPT identity map. */
1241 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1242 if (ret < 0) {
1243 return ret;
1244 }
1245
11076198
JK		 1246 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1247 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1248 if (ret < 0) {
11076198 1249 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1250 return ret;
1251 }
3c85e74f 1252 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1253
4689b77b 1254 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1255 if (shadow_mem != -1) {
1256 shadow_mem /= 4096;
1257 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1258 if (ret < 0) {
1259 return ret;
39d6960a
JK		 1260 }
1261 }
6410848b 1262
d870cfde
GA		 1263 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1264 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1265 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1266 smram_machine_done.notify = register_smram_listener;
1267 qemu_add_machine_init_done_notifier(&smram_machine_done);
1268 }
11076198 1269 return 0;
05330448 1270}
b9bec74b 1271
05330448
AL		 1272static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1273{
1274 lhs->selector = rhs->selector;
1275 lhs->base = rhs->base;
1276 lhs->limit = rhs->limit;
1277 lhs->type = 3;
1278 lhs->present = 1;
1279 lhs->dpl = 3;
1280 lhs->db = 0;
1281 lhs->s = 1;
1282 lhs->l = 0;
1283 lhs->g = 0;
1284 lhs->avl = 0;
1285 lhs->unusable = 0;
1286}
1287
1288static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1289{
1290 unsigned flags = rhs->flags;
1291 lhs->selector = rhs->selector;
1292 lhs->base = rhs->base;
1293 lhs->limit = rhs->limit;
1294 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1295 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1296 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1297 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1298 lhs->s = (flags & DESC_S_MASK) != 0;
1299 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1300 lhs->g = (flags & DESC_G_MASK) != 0;
1301 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1302 lhs->unusable = !lhs->present;
7e680753 1303 lhs->padding = 0;
05330448
AL		 1304}
1305
1306static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1307{
1308 lhs->selector = rhs->selector;
1309 lhs->base = rhs->base;
1310 lhs->limit = rhs->limit;
d45fc087
RP		 1311 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1312 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1313 (rhs->dpl << DESC_DPL_SHIFT) |
1314 (rhs->db << DESC_B_SHIFT) |
1315 (rhs->s * DESC_S_MASK) |
1316 (rhs->l << DESC_L_SHIFT) |
1317 (rhs->g * DESC_G_MASK) |
1318 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1319}
1320
1321static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1322{
b9bec74b 1323 if (set) {
05330448 1324 *kvm_reg = *qemu_reg;
b9bec74b 1325 } else {
05330448 1326 *qemu_reg = *kvm_reg;
b9bec74b 1327 }
05330448
AL		 1328}
1329
1bc22652 1330static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1331{
1bc22652 1332 CPUX86State *env = &cpu->env;
05330448
AL		 1333 struct kvm_regs regs;
1334 int ret = 0;
1335
1336 if (!set) {
1bc22652 1337 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1338 if (ret < 0) {
05330448 1339 return ret;
b9bec74b 1340 }
05330448
AL		 1341 }
1342
1343 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1344 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1345 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1346 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1347 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1348 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1349 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1350 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1351#ifdef TARGET_X86_64
1352 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1353 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1354 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1355 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1356 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1357 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1358 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1359 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1360#endif
1361
1362 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1363 kvm_getput_reg(&regs.rip, &env->eip, set);
1364
b9bec74b 1365 if (set) {
1bc22652 1366 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1367 }
05330448
AL		 1368
1369 return ret;
1370}
1371
1bc22652 1372static int kvm_put_fpu(X86CPU *cpu)
05330448 1373{
1bc22652 1374 CPUX86State *env = &cpu->env;
05330448
AL		 1375 struct kvm_fpu fpu;
1376 int i;
1377
1378 memset(&fpu, 0, sizeof fpu);
1379 fpu.fsw = env->fpus & ~(7 << 11);
1380 fpu.fsw |= (env->fpstt & 7) << 11;
1381 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1382 fpu.last_opcode = env->fpop;
1383 fpu.last_ip = env->fpip;
1384 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1385 for (i = 0; i < 8; ++i) {
1386 fpu.ftwx |= (!env->fptags[i]) << i;
1387 }
05330448 1388 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1389 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1390 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1391 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1392 }
05330448
AL		 1393 fpu.mxcsr = env->mxcsr;
1394
1bc22652 1395 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1396}
1397
6b42494b
JK		 1398#define XSAVE_FCW_FSW 0
1399#define XSAVE_FTW_FOP 1
f1665b21
SY		 1400#define XSAVE_CWD_RIP 2
1401#define XSAVE_CWD_RDP 4
1402#define XSAVE_MXCSR 6
1403#define XSAVE_ST_SPACE 8
1404#define XSAVE_XMM_SPACE 40
1405#define XSAVE_XSTATE_BV 128
1406#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1407#define XSAVE_BNDREGS 240
1408#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1409#define XSAVE_OPMASK 272
1410#define XSAVE_ZMM_Hi256 288
1411#define XSAVE_Hi16_ZMM 416
f74eefe0 1412#define XSAVE_PKRU 672
f1665b21 1413
b503717d
EH		 1414#define XSAVE_BYTE_OFFSET(word_offset) \
1415 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1416
1417#define ASSERT_OFFSET(word_offset, field) \
1418 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1419 offsetof(X86XSaveArea, field))
1420
1421ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1422ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1423ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1424ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1425ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1426ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1427ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1428ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1429ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1430ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1431ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1432ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1433ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1434ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1435ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1436
1bc22652 1437static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1438{
1bc22652 1439 CPUX86State *env = &cpu->env;
86cd2ea0 1440 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1441
28143b40 1442 if (!has_xsave) {
1bc22652 1443 return kvm_put_fpu(cpu);
b9bec74b 1444 }
86a57621 1445 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1446
9be38598 1447 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1448}
1449
1bc22652 1450static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1451{
1bc22652 1452 CPUX86State *env = &cpu->env;
bdfc8480 1453 struct kvm_xcrs xcrs = {};
f1665b21 1454
28143b40 1455 if (!has_xcrs) {
f1665b21 1456 return 0;
b9bec74b 1457 }
f1665b21
SY		 1458
1459 xcrs.nr_xcrs = 1;
1460 xcrs.flags = 0;
1461 xcrs.xcrs[0].xcr = 0;
1462 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1463 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1464}
1465
1bc22652 1466static int kvm_put_sregs(X86CPU *cpu)
05330448 1467{
1bc22652 1468 CPUX86State *env = &cpu->env;
05330448
AL		 1469 struct kvm_sregs sregs;
1470
0e607a80
JK		 1471 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1472 if (env->interrupt_injected >= 0) {
1473 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1474 (uint64_t)1 << (env->interrupt_injected % 64);
1475 }
05330448
AL		 1476
1477 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1478 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1479 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1480 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1481 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1482 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1483 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1484 } else {
b9bec74b
JK		 1485 set_seg(&sregs.cs, &env->segs[R_CS]);
1486 set_seg(&sregs.ds, &env->segs[R_DS]);
1487 set_seg(&sregs.es, &env->segs[R_ES]);
1488 set_seg(&sregs.fs, &env->segs[R_FS]);
1489 set_seg(&sregs.gs, &env->segs[R_GS]);
1490 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1491 }
1492
1493 set_seg(&sregs.tr, &env->tr);
1494 set_seg(&sregs.ldt, &env->ldt);
1495
1496 sregs.idt.limit = env->idt.limit;
1497 sregs.idt.base = env->idt.base;
7e680753 1498 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1499 sregs.gdt.limit = env->gdt.limit;
1500 sregs.gdt.base = env->gdt.base;
7e680753 1501 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1502
1503 sregs.cr0 = env->cr[0];
1504 sregs.cr2 = env->cr[2];
1505 sregs.cr3 = env->cr[3];
1506 sregs.cr4 = env->cr[4];
1507
02e51483
CF		 1508 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1509 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1510
1511 sregs.efer = env->efer;
1512
1bc22652 1513 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1514}
1515
d71b62a1
EH		 1516static void kvm_msr_buf_reset(X86CPU *cpu)
1517{
1518 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1519}
1520
9c600a84
EH		 1521static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1522{
1523 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1524 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1525 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1526
1527 assert((void *)(entry + 1) <= limit);
1528
1abc2cae
EH		 1529 entry->index = index;
1530 entry->reserved = 0;
1531 entry->data = value;
9c600a84
EH		 1532 msrs->nmsrs++;
1533}
1534
73e1b8f2
PB		 1535static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1536{
1537 kvm_msr_buf_reset(cpu);
1538 kvm_msr_entry_add(cpu, index, value);
1539
1540 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1541}
1542
f8d9ccf8
DDAG		 1543void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1544{
1545 int ret;
1546
1547 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1548 assert(ret == 1);
1549}
1550
7477cd38
MT		 1551static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1552{
1553 CPUX86State *env = &cpu->env;
48e1a45c 1554 int ret;
7477cd38
MT		 1555
1556 if (!has_msr_tsc_deadline) {
1557 return 0;
1558 }
1559
73e1b8f2 1560 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1561 if (ret < 0) {
1562 return ret;
1563 }
1564
1565 assert(ret == 1);
1566 return 0;
7477cd38
MT		 1567}
1568
6bdf863d
JK		 1569/*
1570 * Provide a separate write service for the feature control MSR in order to
1571 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1572 * before writing any other state because forcibly leaving nested mode
1573 * invalidates the VCPU state.
1574 */
1575static int kvm_put_msr_feature_control(X86CPU *cpu)
1576{
48e1a45c
PB		 1577 int ret;
1578
1579 if (!has_msr_feature_control) {
1580 return 0;
1581 }
6bdf863d 1582
73e1b8f2
PB		 1583 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1584 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1585 if (ret < 0) {
1586 return ret;
1587 }
1588
1589 assert(ret == 1);
1590 return 0;
6bdf863d
JK		 1591}
1592
1bc22652 1593static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1594{
1bc22652 1595 CPUX86State *env = &cpu->env;
9c600a84 1596 int i;
48e1a45c 1597 int ret;
05330448 1598
d71b62a1
EH		 1599 kvm_msr_buf_reset(cpu);
1600
9c600a84
EH		 1601 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1602 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1603 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1604 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1605 if (has_msr_star) {
9c600a84 1606 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1607 }
c3a3a7d3 1608 if (has_msr_hsave_pa) {
9c600a84 1609 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1610 }
c9b8f6b6 1611 if (has_msr_tsc_aux) {
9c600a84 1612 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1613 }
f28558d3 1614 if (has_msr_tsc_adjust) {
9c600a84 1615 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1616 }
21e87c46 1617 if (has_msr_misc_enable) {
9c600a84 1618 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1619 env->msr_ia32_misc_enable);
1620 }
fc12d72e 1621 if (has_msr_smbase) {
9c600a84 1622 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1623 }
439d19f2 1624 if (has_msr_bndcfgs) {
9c600a84 1625 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1626 }
18cd2c17 1627 if (has_msr_xss) {
9c600a84 1628 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1629 }
05330448 1630#ifdef TARGET_X86_64
25d2e361 1631 if (lm_capable_kernel) {
9c600a84
EH		 1632 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1633 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1634 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1635 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1636 }
05330448 1637#endif
ff5c186b 1638 /*
0d894367
PB		 1639 * The following MSRs have side effects on the guest or are too heavy
1640 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1641 */
1642 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1643 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1644 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1645 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1646 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1647 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1648 }
55c911a5 1649 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1650 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1651 }
55c911a5 1652 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1653 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1654 }
0d894367
PB		 1655 if (has_msr_architectural_pmu) {
1656 /* Stop the counter. */
9c600a84
EH		 1657 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1658 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1659
1660 /* Set the counter values. */
1661 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1662 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1663 env->msr_fixed_counters[i]);
1664 }
1665 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1666 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1667 env->msr_gp_counters[i]);
9c600a84 1668 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1669 env->msr_gp_evtsel[i]);
1670 }
9c600a84 1671 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1672 env->msr_global_status);
9c600a84 1673 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1674 env->msr_global_ovf_ctrl);
1675
1676 /* Now start the PMU. */
9c600a84 1677 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1678 env->msr_fixed_ctr_ctrl);
9c600a84 1679 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1680 env->msr_global_ctrl);
1681 }
7bc3d711 1682 if (has_msr_hv_hypercall) {
9c600a84 1683 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1684 env->msr_hv_guest_os_id);
9c600a84 1685 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1686 env->msr_hv_hypercall);
eab70139 1687 }
2d5aa872 1688 if (cpu->hyperv_vapic) {
9c600a84 1689 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1690 env->msr_hv_vapic);
eab70139 1691 }
3ddcd2ed 1692 if (cpu->hyperv_time) {
9c600a84 1693 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1694 }
f2a53c9e
AS		 1695 if (has_msr_hv_crash) {
1696 int j;
1697
1698 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
9c600a84 1699 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1700 env->msr_hv_crash_params[j]);
1701
9c600a84 1702 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
f2a53c9e
AS		 1703 HV_X64_MSR_CRASH_CTL_NOTIFY);
1704 }
46eb8f98 1705 if (has_msr_hv_runtime) {
9c600a84 1706 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1707 }
866eea9a
AS		 1708 if (cpu->hyperv_synic) {
1709 int j;
1710
9c600a84 1711 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1712 env->msr_hv_synic_control);
9c600a84 1713 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1714 env->msr_hv_synic_version);
9c600a84 1715 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1716 env->msr_hv_synic_evt_page);
9c600a84 1717 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1718 env->msr_hv_synic_msg_page);
1719
1720 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1721 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1722 env->msr_hv_synic_sint[j]);
1723 }
1724 }
ff99aa64
AS		 1725 if (has_msr_hv_stimer) {
1726 int j;
1727
1728 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1729 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1730 env->msr_hv_stimer_config[j]);
1731 }
1732
1733 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1734 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1735 env->msr_hv_stimer_count[j]);
1736 }
1737 }
1eabfce6 1738 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1739 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1740
9c600a84
EH		 1741 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1742 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1743 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1744 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1745 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1746 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1747 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1748 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1749 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1750 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1751 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1752 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1753 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1754 /* The CPU GPs if we write to a bit above the physical limit of
1755 * the host CPU (and KVM emulates that)
1756 */
1757 uint64_t mask = env->mtrr_var[i].mask;
1758 mask &= phys_mask;
1759
9c600a84
EH		 1760 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1761 env->mtrr_var[i].base);
112dad69 1762 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1763 }
1764 }
6bdf863d
JK		 1765
1766 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1767 * kvm_put_msr_feature_control. */
ea643051 1768 }
57780495 1769 if (env->mcg_cap) {
d8da8574 1770 int i;
b9bec74b 1771
9c600a84
EH		 1772 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1773 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1774 if (has_msr_mcg_ext_ctl) {
1775 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1776 }
c34d440a 1777 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1778 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1779 }
1780 }
1a03675d 1781
d71b62a1 1782 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1783 if (ret < 0) {
1784 return ret;
1785 }
05330448 1786
c70b11d1
EH		 1787 if (ret < cpu->kvm_msr_buf->nmsrs) {
1788 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1789 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1790 (uint32_t)e->index, (uint64_t)e->data);
1791 }
1792
9c600a84 1793 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1794 return 0;
05330448
AL		 1795}
1796
1797
1bc22652 1798static int kvm_get_fpu(X86CPU *cpu)
05330448 1799{
1bc22652 1800 CPUX86State *env = &cpu->env;
05330448
AL		 1801 struct kvm_fpu fpu;
1802 int i, ret;
1803
1bc22652 1804 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1805 if (ret < 0) {
05330448 1806 return ret;
b9bec74b 1807 }
05330448
AL		 1808
1809 env->fpstt = (fpu.fsw >> 11) & 7;
1810 env->fpus = fpu.fsw;
1811 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1812 env->fpop = fpu.last_opcode;
1813 env->fpip = fpu.last_ip;
1814 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1815 for (i = 0; i < 8; ++i) {
1816 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1817 }
05330448 1818 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1819 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1820 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1821 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1822 }
05330448
AL		 1823 env->mxcsr = fpu.mxcsr;
1824
1825 return 0;
1826}
1827
1bc22652 1828static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1829{
1bc22652 1830 CPUX86State *env = &cpu->env;
86cd2ea0 1831 X86XSaveArea *xsave = env->kvm_xsave_buf;
86a57621 1832 int ret;
f1665b21 1833
28143b40 1834 if (!has_xsave) {
1bc22652 1835 return kvm_get_fpu(cpu);
b9bec74b 1836 }
f1665b21 1837
1bc22652 1838 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1839 if (ret < 0) {
f1665b21 1840 return ret;
0f53994f 1841 }
86a57621 1842 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 1843
f1665b21 1844 return 0;
f1665b21
SY		 1845}
1846
1bc22652 1847static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1848{
1bc22652 1849 CPUX86State *env = &cpu->env;
f1665b21
SY		 1850 int i, ret;
1851 struct kvm_xcrs xcrs;
1852
28143b40 1853 if (!has_xcrs) {
f1665b21 1854 return 0;
b9bec74b 1855 }
f1665b21 1856
1bc22652 1857 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1858 if (ret < 0) {
f1665b21 1859 return ret;
b9bec74b 1860 }
f1665b21 1861
b9bec74b 1862 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1863 /* Only support xcr0 now */
0fd53fec
PB		 1864 if (xcrs.xcrs[i].xcr == 0) {
1865 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1866 break;
1867 }
b9bec74b 1868 }
f1665b21 1869 return 0;
f1665b21
SY		 1870}
1871
1bc22652 1872static int kvm_get_sregs(X86CPU *cpu)
05330448 1873{
1bc22652 1874 CPUX86State *env = &cpu->env;
05330448
AL		 1875 struct kvm_sregs sregs;
1876 uint32_t hflags;
0e607a80 1877 int bit, i, ret;
05330448 1878
1bc22652 1879 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1880 if (ret < 0) {
05330448 1881 return ret;
b9bec74b 1882 }
05330448 1883
0e607a80
JK		 1884 /* There can only be one pending IRQ set in the bitmap at a time, so try
1885 to find it and save its number instead (-1 for none). */
1886 env->interrupt_injected = -1;
1887 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1888 if (sregs.interrupt_bitmap[i]) {
1889 bit = ctz64(sregs.interrupt_bitmap[i]);
1890 env->interrupt_injected = i * 64 + bit;
1891 break;
1892 }
1893 }
05330448
AL		 1894
1895 get_seg(&env->segs[R_CS], &sregs.cs);
1896 get_seg(&env->segs[R_DS], &sregs.ds);
1897 get_seg(&env->segs[R_ES], &sregs.es);
1898 get_seg(&env->segs[R_FS], &sregs.fs);
1899 get_seg(&env->segs[R_GS], &sregs.gs);
1900 get_seg(&env->segs[R_SS], &sregs.ss);
1901
1902 get_seg(&env->tr, &sregs.tr);
1903 get_seg(&env->ldt, &sregs.ldt);
1904
1905 env->idt.limit = sregs.idt.limit;
1906 env->idt.base = sregs.idt.base;
1907 env->gdt.limit = sregs.gdt.limit;
1908 env->gdt.base = sregs.gdt.base;
1909
1910 env->cr[0] = sregs.cr0;
1911 env->cr[2] = sregs.cr2;
1912 env->cr[3] = sregs.cr3;
1913 env->cr[4] = sregs.cr4;
1914
05330448 1915 env->efer = sregs.efer;
cce47516
JK		 1916
1917 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1918
b9bec74b
JK		 1919#define HFLAG_COPY_MASK \
1920 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1921 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1922 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1923 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1924
19dc85db
RH		 1925 hflags = env->hflags & HFLAG_COPY_MASK;
1926 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1927 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1928 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1929 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 1930 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 1931
1932 if (env->cr[4] & CR4_OSFXSR_MASK) {
1933 hflags |= HF_OSFXSR_MASK;
1934 }
05330448
AL		 1935
1936 if (env->efer & MSR_EFER_LMA) {
1937 hflags |= HF_LMA_MASK;
1938 }
1939
1940 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1941 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1942 } else {
1943 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1944 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1945 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1946 (DESC_B_SHIFT - HF_SS32_SHIFT);
1947 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1948 !(hflags & HF_CS32_MASK)) {
1949 hflags |= HF_ADDSEG_MASK;
1950 } else {
1951 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1952 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1953 }
05330448 1954 }
19dc85db 1955 env->hflags = hflags;
05330448
AL		 1956
1957 return 0;
1958}
1959
1bc22652 1960static int kvm_get_msrs(X86CPU *cpu)
05330448 1961{
1bc22652 1962 CPUX86State *env = &cpu->env;
d71b62a1 1963 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 1964 int ret, i;
fcc35e7c 1965 uint64_t mtrr_top_bits;
05330448 1966
d71b62a1
EH		 1967 kvm_msr_buf_reset(cpu);
1968
9c600a84
EH		 1969 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1970 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1971 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1972 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 1973 if (has_msr_star) {
9c600a84 1974 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 1975 }
c3a3a7d3 1976 if (has_msr_hsave_pa) {
9c600a84 1977 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 1978 }
c9b8f6b6 1979 if (has_msr_tsc_aux) {
9c600a84 1980 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 1981 }
f28558d3 1982 if (has_msr_tsc_adjust) {
9c600a84 1983 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 1984 }
aa82ba54 1985 if (has_msr_tsc_deadline) {
9c600a84 1986 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 1987 }
21e87c46 1988 if (has_msr_misc_enable) {
9c600a84 1989 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 1990 }
fc12d72e 1991 if (has_msr_smbase) {
9c600a84 1992 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 1993 }
df67696e 1994 if (has_msr_feature_control) {
9c600a84 1995 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 1996 }
79e9ebeb 1997 if (has_msr_bndcfgs) {
9c600a84 1998 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 1999 }
18cd2c17 2000 if (has_msr_xss) {
9c600a84 2001 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 2002 }
2003
b8cc45d6
GC		 2004
2005 if (!env->tsc_valid) {
9c600a84 2006 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2007 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2008 }
2009
05330448 2010#ifdef TARGET_X86_64
25d2e361 2011 if (lm_capable_kernel) {
9c600a84
EH		 2012 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2013 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2014 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2015 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2016 }
05330448 2017#endif
9c600a84
EH		 2018 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2019 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2020 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2021 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2022 }
55c911a5 2023 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2024 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2025 }
55c911a5 2026 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2027 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2028 }
0d894367 2029 if (has_msr_architectural_pmu) {
9c600a84
EH		 2030 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2031 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2032 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2033 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2034 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2035 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2036 }
2037 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2038 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2039 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2040 }
2041 }
1a03675d 2042
57780495 2043 if (env->mcg_cap) {
9c600a84
EH		 2044 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2045 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2046 if (has_msr_mcg_ext_ctl) {
2047 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2048 }
b9bec74b 2049 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2050 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2051 }
57780495 2052 }
57780495 2053
1c90ef26 2054 if (has_msr_hv_hypercall) {
9c600a84
EH		 2055 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2056 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2057 }
2d5aa872 2058 if (cpu->hyperv_vapic) {
9c600a84 2059 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2060 }
3ddcd2ed 2061 if (cpu->hyperv_time) {
9c600a84 2062 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2063 }
f2a53c9e
AS		 2064 if (has_msr_hv_crash) {
2065 int j;
2066
2067 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
9c600a84 2068 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2069 }
2070 }
46eb8f98 2071 if (has_msr_hv_runtime) {
9c600a84 2072 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2073 }
866eea9a
AS		 2074 if (cpu->hyperv_synic) {
2075 uint32_t msr;
2076
9c600a84
EH		 2077 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2078 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2079 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2080 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2081 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2082 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2083 }
2084 }
ff99aa64
AS		 2085 if (has_msr_hv_stimer) {
2086 uint32_t msr;
2087
2088 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2089 msr++) {
9c600a84 2090 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2091 }
2092 }
1eabfce6 2093 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2094 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2095 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2096 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2097 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2098 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2099 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2100 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2101 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2102 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2103 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2104 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2105 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2106 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2107 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2108 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2109 }
2110 }
5ef68987 2111
d71b62a1 2112 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2113 if (ret < 0) {
05330448 2114 return ret;
b9bec74b 2115 }
05330448 2116
c70b11d1
EH		 2117 if (ret < cpu->kvm_msr_buf->nmsrs) {
2118 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2119 error_report("error: failed to get MSR 0x%" PRIx32,
2120 (uint32_t)e->index);
2121 }
2122
9c600a84 2123 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2124 /*
2125 * MTRR masks: Each mask consists of 5 parts
2126 * a 10..0: must be zero
2127 * b 11 : valid bit
2128 * c n-1.12: actual mask bits
2129 * d 51..n: reserved must be zero
2130 * e 63.52: reserved must be zero
2131 *
2132 * 'n' is the number of physical bits supported by the CPU and is
2133 * apparently always <= 52. We know our 'n' but don't know what
2134 * the destinations 'n' is; it might be smaller, in which case
2135 * it masks (c) on loading. It might be larger, in which case
2136 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2137 * we're migrating to.
2138 */
2139
2140 if (cpu->fill_mtrr_mask) {
2141 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2142 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2143 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2144 } else {
2145 mtrr_top_bits = 0;
2146 }
2147
05330448 2148 for (i = 0; i < ret; i++) {
0d894367
PB		 2149 uint32_t index = msrs[i].index;
2150 switch (index) {
05330448
AL		 2151 case MSR_IA32_SYSENTER_CS:
2152 env->sysenter_cs = msrs[i].data;
2153 break;
2154 case MSR_IA32_SYSENTER_ESP:
2155 env->sysenter_esp = msrs[i].data;
2156 break;
2157 case MSR_IA32_SYSENTER_EIP:
2158 env->sysenter_eip = msrs[i].data;
2159 break;
0c03266a
JK		 2160 case MSR_PAT:
2161 env->pat = msrs[i].data;
2162 break;
05330448
AL		 2163 case MSR_STAR:
2164 env->star = msrs[i].data;
2165 break;
2166#ifdef TARGET_X86_64
2167 case MSR_CSTAR:
2168 env->cstar = msrs[i].data;
2169 break;
2170 case MSR_KERNELGSBASE:
2171 env->kernelgsbase = msrs[i].data;
2172 break;
2173 case MSR_FMASK:
2174 env->fmask = msrs[i].data;
2175 break;
2176 case MSR_LSTAR:
2177 env->lstar = msrs[i].data;
2178 break;
2179#endif
2180 case MSR_IA32_TSC:
2181 env->tsc = msrs[i].data;
2182 break;
c9b8f6b6
AS		 2183 case MSR_TSC_AUX:
2184 env->tsc_aux = msrs[i].data;
2185 break;
f28558d3
WA		 2186 case MSR_TSC_ADJUST:
2187 env->tsc_adjust = msrs[i].data;
2188 break;
aa82ba54
LJ		 2189 case MSR_IA32_TSCDEADLINE:
2190 env->tsc_deadline = msrs[i].data;
2191 break;
aa851e36
MT		 2192 case MSR_VM_HSAVE_PA:
2193 env->vm_hsave = msrs[i].data;
2194 break;
1a03675d
GC		 2195 case MSR_KVM_SYSTEM_TIME:
2196 env->system_time_msr = msrs[i].data;
2197 break;
2198 case MSR_KVM_WALL_CLOCK:
2199 env->wall_clock_msr = msrs[i].data;
2200 break;
57780495
MT		 2201 case MSR_MCG_STATUS:
2202 env->mcg_status = msrs[i].data;
2203 break;
2204 case MSR_MCG_CTL:
2205 env->mcg_ctl = msrs[i].data;
2206 break;
87f8b626
AR		 2207 case MSR_MCG_EXT_CTL:
2208 env->mcg_ext_ctl = msrs[i].data;
2209 break;
21e87c46
AK		 2210 case MSR_IA32_MISC_ENABLE:
2211 env->msr_ia32_misc_enable = msrs[i].data;
2212 break;
fc12d72e
PB		 2213 case MSR_IA32_SMBASE:
2214 env->smbase = msrs[i].data;
2215 break;
0779caeb
ACL		 2216 case MSR_IA32_FEATURE_CONTROL:
2217 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2218 break;
79e9ebeb
LJ		 2219 case MSR_IA32_BNDCFGS:
2220 env->msr_bndcfgs = msrs[i].data;
2221 break;
18cd2c17
WL		 2222 case MSR_IA32_XSS:
2223 env->xss = msrs[i].data;
2224 break;
57780495 2225 default:
57780495
MT		 2226 if (msrs[i].index >= MSR_MC0_CTL &&
2227 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2228 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2229 }
d8da8574 2230 break;
f6584ee2
GN		 2231 case MSR_KVM_ASYNC_PF_EN:
2232 env->async_pf_en_msr = msrs[i].data;
2233 break;
bc9a839d
MT		 2234 case MSR_KVM_PV_EOI_EN:
2235 env->pv_eoi_en_msr = msrs[i].data;
2236 break;
917367aa
MT		 2237 case MSR_KVM_STEAL_TIME:
2238 env->steal_time_msr = msrs[i].data;
2239 break;
0d894367
PB		 2240 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2241 env->msr_fixed_ctr_ctrl = msrs[i].data;
2242 break;
2243 case MSR_CORE_PERF_GLOBAL_CTRL:
2244 env->msr_global_ctrl = msrs[i].data;
2245 break;
2246 case MSR_CORE_PERF_GLOBAL_STATUS:
2247 env->msr_global_status = msrs[i].data;
2248 break;
2249 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2250 env->msr_global_ovf_ctrl = msrs[i].data;
2251 break;
2252 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2253 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2254 break;
2255 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2256 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2257 break;
2258 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2259 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2260 break;
1c90ef26
VR		 2261 case HV_X64_MSR_HYPERCALL:
2262 env->msr_hv_hypercall = msrs[i].data;
2263 break;
2264 case HV_X64_MSR_GUEST_OS_ID:
2265 env->msr_hv_guest_os_id = msrs[i].data;
2266 break;
5ef68987
VR		 2267 case HV_X64_MSR_APIC_ASSIST_PAGE:
2268 env->msr_hv_vapic = msrs[i].data;
2269 break;
48a5f3bc
VR		 2270 case HV_X64_MSR_REFERENCE_TSC:
2271 env->msr_hv_tsc = msrs[i].data;
2272 break;
f2a53c9e
AS		 2273 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2274 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2275 break;
46eb8f98
AS		 2276 case HV_X64_MSR_VP_RUNTIME:
2277 env->msr_hv_runtime = msrs[i].data;
2278 break;
866eea9a
AS		 2279 case HV_X64_MSR_SCONTROL:
2280 env->msr_hv_synic_control = msrs[i].data;
2281 break;
2282 case HV_X64_MSR_SVERSION:
2283 env->msr_hv_synic_version = msrs[i].data;
2284 break;
2285 case HV_X64_MSR_SIEFP:
2286 env->msr_hv_synic_evt_page = msrs[i].data;
2287 break;
2288 case HV_X64_MSR_SIMP:
2289 env->msr_hv_synic_msg_page = msrs[i].data;
2290 break;
2291 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2292 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2293 break;
2294 case HV_X64_MSR_STIMER0_CONFIG:
2295 case HV_X64_MSR_STIMER1_CONFIG:
2296 case HV_X64_MSR_STIMER2_CONFIG:
2297 case HV_X64_MSR_STIMER3_CONFIG:
2298 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2299 msrs[i].data;
2300 break;
2301 case HV_X64_MSR_STIMER0_COUNT:
2302 case HV_X64_MSR_STIMER1_COUNT:
2303 case HV_X64_MSR_STIMER2_COUNT:
2304 case HV_X64_MSR_STIMER3_COUNT:
2305 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2306 msrs[i].data;
866eea9a 2307 break;
d1ae67f6
AW		 2308 case MSR_MTRRdefType:
2309 env->mtrr_deftype = msrs[i].data;
2310 break;
2311 case MSR_MTRRfix64K_00000:
2312 env->mtrr_fixed[0] = msrs[i].data;
2313 break;
2314 case MSR_MTRRfix16K_80000:
2315 env->mtrr_fixed[1] = msrs[i].data;
2316 break;
2317 case MSR_MTRRfix16K_A0000:
2318 env->mtrr_fixed[2] = msrs[i].data;
2319 break;
2320 case MSR_MTRRfix4K_C0000:
2321 env->mtrr_fixed[3] = msrs[i].data;
2322 break;
2323 case MSR_MTRRfix4K_C8000:
2324 env->mtrr_fixed[4] = msrs[i].data;
2325 break;
2326 case MSR_MTRRfix4K_D0000:
2327 env->mtrr_fixed[5] = msrs[i].data;
2328 break;
2329 case MSR_MTRRfix4K_D8000:
2330 env->mtrr_fixed[6] = msrs[i].data;
2331 break;
2332 case MSR_MTRRfix4K_E0000:
2333 env->mtrr_fixed[7] = msrs[i].data;
2334 break;
2335 case MSR_MTRRfix4K_E8000:
2336 env->mtrr_fixed[8] = msrs[i].data;
2337 break;
2338 case MSR_MTRRfix4K_F0000:
2339 env->mtrr_fixed[9] = msrs[i].data;
2340 break;
2341 case MSR_MTRRfix4K_F8000:
2342 env->mtrr_fixed[10] = msrs[i].data;
2343 break;
2344 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2345 if (index & 1) {
fcc35e7c
DDAG		 2346 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2347 mtrr_top_bits;
d1ae67f6
AW		 2348 } else {
2349 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2350 }
2351 break;
05330448
AL		 2352 }
2353 }
2354
2355 return 0;
2356}
2357
1bc22652 2358static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2359{
1bc22652 2360 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2361
1bc22652 2362 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2363}
2364
23d02d9b 2365static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2366{
259186a7 2367 CPUState *cs = CPU(cpu);
23d02d9b 2368 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2369 struct kvm_mp_state mp_state;
2370 int ret;
2371
259186a7 2372 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2373 if (ret < 0) {
2374 return ret;
2375 }
2376 env->mp_state = mp_state.mp_state;
c14750e8 2377 if (kvm_irqchip_in_kernel()) {
259186a7 2378 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2379 }
9bdbe550
HB		 2380 return 0;
2381}
2382
1bc22652 2383static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2384{
02e51483 2385 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2386 struct kvm_lapic_state kapic;
2387 int ret;
2388
3d4b2649 2389 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2390 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2391 if (ret < 0) {
2392 return ret;
2393 }
2394
2395 kvm_get_apic_state(apic, &kapic);
2396 }
2397 return 0;
2398}
2399
1bc22652 2400static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2401{
fc12d72e 2402 CPUState *cs = CPU(cpu);
1bc22652 2403 CPUX86State *env = &cpu->env;
076796f8 2404 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2405
2406 if (!kvm_has_vcpu_events()) {
2407 return 0;
2408 }
2409
31827373
JK		 2410 events.exception.injected = (env->exception_injected >= 0);
2411 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2412 events.exception.has_error_code = env->has_error_code;
2413 events.exception.error_code = env->error_code;
7e680753 2414 events.exception.pad = 0;
a0fb002c
JK		 2415
2416 events.interrupt.injected = (env->interrupt_injected >= 0);
2417 events.interrupt.nr = env->interrupt_injected;
2418 events.interrupt.soft = env->soft_interrupt;
2419
2420 events.nmi.injected = env->nmi_injected;
2421 events.nmi.pending = env->nmi_pending;
2422 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2423 events.nmi.pad = 0;
a0fb002c
JK		 2424
2425 events.sipi_vector = env->sipi_vector;
68c6efe0 2426 events.flags = 0;
a0fb002c 2427
fc12d72e
PB		 2428 if (has_msr_smbase) {
2429 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2430 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2431 if (kvm_irqchip_in_kernel()) {
2432 /* As soon as these are moved to the kernel, remove them
2433 * from cs->interrupt_request.
2434 */
2435 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2436 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2437 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2438 } else {
2439 /* Keep these in cs->interrupt_request. */
2440 events.smi.pending = 0;
2441 events.smi.latched_init = 0;
2442 }
fc3a1fd7
DDAG		 2443 /* Stop SMI delivery on old machine types to avoid a reboot
2444 * on an inward migration of an old VM.
2445 */
2446 if (!cpu->kvm_no_smi_migration) {
2447 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2448 }
fc12d72e
PB		 2449 }
2450
ea643051 2451 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2452 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2453 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2454 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2455 }
ea643051 2456 }
aee028b9 2457
1bc22652 2458 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2459}
2460
1bc22652 2461static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2462{
1bc22652 2463 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2464 struct kvm_vcpu_events events;
2465 int ret;
2466
2467 if (!kvm_has_vcpu_events()) {
2468 return 0;
2469 }
2470
fc12d72e 2471 memset(&events, 0, sizeof(events));
1bc22652 2472 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2473 if (ret < 0) {
2474 return ret;
2475 }
31827373 2476 env->exception_injected =
a0fb002c
JK		 2477 events.exception.injected ? events.exception.nr : -1;
2478 env->has_error_code = events.exception.has_error_code;
2479 env->error_code = events.exception.error_code;
2480
2481 env->interrupt_injected =
2482 events.interrupt.injected ? events.interrupt.nr : -1;
2483 env->soft_interrupt = events.interrupt.soft;
2484
2485 env->nmi_injected = events.nmi.injected;
2486 env->nmi_pending = events.nmi.pending;
2487 if (events.nmi.masked) {
2488 env->hflags2 |= HF2_NMI_MASK;
2489 } else {
2490 env->hflags2 &= ~HF2_NMI_MASK;
2491 }
2492
fc12d72e
PB		 2493 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2494 if (events.smi.smm) {
2495 env->hflags |= HF_SMM_MASK;
2496 } else {
2497 env->hflags &= ~HF_SMM_MASK;
2498 }
2499 if (events.smi.pending) {
2500 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2501 } else {
2502 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2503 }
2504 if (events.smi.smm_inside_nmi) {
2505 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2506 } else {
2507 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2508 }
2509 if (events.smi.latched_init) {
2510 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2511 } else {
2512 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2513 }
2514 }
2515
a0fb002c 2516 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2517
2518 return 0;
2519}
2520
1bc22652 2521static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2522{
ed2803da 2523 CPUState *cs = CPU(cpu);
1bc22652 2524 CPUX86State *env = &cpu->env;
b0b1d690 2525 int ret = 0;
b0b1d690
JK		 2526 unsigned long reinject_trap = 0;
2527
2528 if (!kvm_has_vcpu_events()) {
2529 if (env->exception_injected == 1) {
2530 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2531 } else if (env->exception_injected == 3) {
2532 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2533 }
2534 env->exception_injected = -1;
2535 }
2536
2537 /*
2538 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2539 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2540 * by updating the debug state once again if single-stepping is on.
2541 * Another reason to call kvm_update_guest_debug here is a pending debug
2542 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2543 * reinject them via SET_GUEST_DEBUG.
2544 */
2545 if (reinject_trap ||
ed2803da 2546 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2547 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2548 }
b0b1d690
JK		 2549 return ret;
2550}
2551
1bc22652 2552static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2553{
1bc22652 2554 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2555 struct kvm_debugregs dbgregs;
2556 int i;
2557
2558 if (!kvm_has_debugregs()) {
2559 return 0;
2560 }
2561
2562 for (i = 0; i < 4; i++) {
2563 dbgregs.db[i] = env->dr[i];
2564 }
2565 dbgregs.dr6 = env->dr[6];
2566 dbgregs.dr7 = env->dr[7];
2567 dbgregs.flags = 0;
2568
1bc22652 2569 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2570}
2571
1bc22652 2572static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2573{
1bc22652 2574 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2575 struct kvm_debugregs dbgregs;
2576 int i, ret;
2577
2578 if (!kvm_has_debugregs()) {
2579 return 0;
2580 }
2581
1bc22652 2582 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2583 if (ret < 0) {
b9bec74b 2584 return ret;
ff44f1a3
JK		 2585 }
2586 for (i = 0; i < 4; i++) {
2587 env->dr[i] = dbgregs.db[i];
2588 }
2589 env->dr[4] = env->dr[6] = dbgregs.dr6;
2590 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2591
2592 return 0;
2593}
2594
20d695a9 2595int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2596{
20d695a9 2597 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2598 int ret;
2599
2fa45344 2600 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2601
48e1a45c 2602 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2603 ret = kvm_put_msr_feature_control(x86_cpu);
2604 if (ret < 0) {
2605 return ret;
2606 }
2607 }
2608
36f96c4b
HZ		 2609 if (level == KVM_PUT_FULL_STATE) {
2610 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2611 * because TSC frequency mismatch shouldn't abort migration,
2612 * unless the user explicitly asked for a more strict TSC
2613 * setting (e.g. using an explicit "tsc-freq" option).
2614 */
2615 kvm_arch_set_tsc_khz(cpu);
2616 }
2617
1bc22652 2618 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2619 if (ret < 0) {
05330448 2620 return ret;
b9bec74b 2621 }
1bc22652 2622 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2623 if (ret < 0) {
f1665b21 2624 return ret;
b9bec74b 2625 }
1bc22652 2626 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2627 if (ret < 0) {
05330448 2628 return ret;
b9bec74b 2629 }
1bc22652 2630 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2631 if (ret < 0) {
05330448 2632 return ret;
b9bec74b 2633 }
ab443475 2634 /* must be before kvm_put_msrs */
1bc22652 2635 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2636 if (ret < 0) {
2637 return ret;
2638 }
1bc22652 2639 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2640 if (ret < 0) {
05330448 2641 return ret;
b9bec74b 2642 }
4fadfa00
PH		 2643 ret = kvm_put_vcpu_events(x86_cpu, level);
2644 if (ret < 0) {
2645 return ret;
2646 }
ea643051 2647 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2648 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2649 if (ret < 0) {
680c1c6f
JK		 2650 return ret;
2651 }
ea643051 2652 }
7477cd38
MT		 2653
2654 ret = kvm_put_tscdeadline_msr(x86_cpu);
2655 if (ret < 0) {
2656 return ret;
2657 }
1bc22652 2658 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2659 if (ret < 0) {
b0b1d690 2660 return ret;
b9bec74b 2661 }
b0b1d690 2662 /* must be last */
1bc22652 2663 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2664 if (ret < 0) {
ff44f1a3 2665 return ret;
b9bec74b 2666 }
05330448
AL		 2667 return 0;
2668}
2669
20d695a9 2670int kvm_arch_get_registers(CPUState *cs)
05330448 2671{
20d695a9 2672 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2673 int ret;
2674
20d695a9 2675 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2676
4fadfa00 2677 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2678 if (ret < 0) {
f4f1110e 2679 goto out;
b9bec74b 2680 }
4fadfa00
PH		 2681 /*
2682 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2683 * KVM_GET_REGS and KVM_GET_SREGS.
2684 */
2685 ret = kvm_get_mp_state(cpu);
b9bec74b 2686 if (ret < 0) {
f4f1110e 2687 goto out;
b9bec74b 2688 }
4fadfa00 2689 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2690 if (ret < 0) {
f4f1110e 2691 goto out;
b9bec74b 2692 }
4fadfa00 2693 ret = kvm_get_xsave(cpu);
b9bec74b 2694 if (ret < 0) {
f4f1110e 2695 goto out;
b9bec74b 2696 }
4fadfa00 2697 ret = kvm_get_xcrs(cpu);
b9bec74b 2698 if (ret < 0) {
f4f1110e 2699 goto out;
b9bec74b 2700 }
4fadfa00 2701 ret = kvm_get_sregs(cpu);
b9bec74b 2702 if (ret < 0) {
f4f1110e 2703 goto out;
b9bec74b 2704 }
4fadfa00 2705 ret = kvm_get_msrs(cpu);
680c1c6f 2706 if (ret < 0) {
f4f1110e 2707 goto out;
680c1c6f 2708 }
4fadfa00 2709 ret = kvm_get_apic(cpu);
b9bec74b 2710 if (ret < 0) {
f4f1110e 2711 goto out;
b9bec74b 2712 }
1bc22652 2713 ret = kvm_get_debugregs(cpu);
b9bec74b 2714 if (ret < 0) {
f4f1110e 2715 goto out;
b9bec74b 2716 }
f4f1110e
RH		 2717 ret = 0;
2718 out:
2719 cpu_sync_bndcs_hflags(&cpu->env);
2720 return ret;
05330448
AL		 2721}
2722
20d695a9 2723void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2724{
20d695a9
AF		 2725 X86CPU *x86_cpu = X86_CPU(cpu);
2726 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2727 int ret;
2728
276ce815 2729 /* Inject NMI */
fc12d72e
PB		 2730 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2731 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2732 qemu_mutex_lock_iothread();
2733 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2734 qemu_mutex_unlock_iothread();
2735 DPRINTF("injected NMI\n");
2736 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2737 if (ret < 0) {
2738 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2739 strerror(-ret));
2740 }
2741 }
2742 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2743 qemu_mutex_lock_iothread();
2744 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2745 qemu_mutex_unlock_iothread();
2746 DPRINTF("injected SMI\n");
2747 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2748 if (ret < 0) {
2749 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2750 strerror(-ret));
2751 }
ce377af3 2752 }
276ce815
LJ		 2753 }
2754
15eafc2e 2755 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2756 qemu_mutex_lock_iothread();
2757 }
2758
e0723c45
PB		 2759 /* Force the VCPU out of its inner loop to process any INIT requests
2760 * or (for userspace APIC, but it is cheap to combine the checks here)
2761 * pending TPR access reports.
2762 */
2763 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2764 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2765 !(env->hflags & HF_SMM_MASK)) {
2766 cpu->exit_request = 1;
2767 }
2768 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2769 cpu->exit_request = 1;
2770 }
e0723c45 2771 }
05330448 2772
15eafc2e 2773 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2774 /* Try to inject an interrupt if the guest can accept it */
2775 if (run->ready_for_interrupt_injection &&
259186a7 2776 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2777 (env->eflags & IF_MASK)) {
2778 int irq;
2779
259186a7 2780 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2781 irq = cpu_get_pic_interrupt(env);
2782 if (irq >= 0) {
2783 struct kvm_interrupt intr;
2784
2785 intr.irq = irq;
db1669bc 2786 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2787 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2788 if (ret < 0) {
2789 fprintf(stderr,
2790 "KVM: injection failed, interrupt lost (%s)\n",
2791 strerror(-ret));
2792 }
db1669bc
JK		 2793 }
2794 }
05330448 2795
db1669bc
JK		 2796 /* If we have an interrupt but the guest is not ready to receive an
2797 * interrupt, request an interrupt window exit. This will
2798 * cause a return to userspace as soon as the guest is ready to
2799 * receive interrupts. */
259186a7 2800 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2801 run->request_interrupt_window = 1;
2802 } else {
2803 run->request_interrupt_window = 0;
2804 }
2805
2806 DPRINTF("setting tpr\n");
02e51483 2807 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2808
2809 qemu_mutex_unlock_iothread();
db1669bc 2810 }
05330448
AL		 2811}
2812
4c663752 2813MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2814{
20d695a9
AF		 2815 X86CPU *x86_cpu = X86_CPU(cpu);
2816 CPUX86State *env = &x86_cpu->env;
2817
fc12d72e
PB		 2818 if (run->flags & KVM_RUN_X86_SMM) {
2819 env->hflags |= HF_SMM_MASK;
2820 } else {
f5c052b9 2821 env->hflags &= ~HF_SMM_MASK;
fc12d72e 2822 }
b9bec74b 2823 if (run->if_flag) {
05330448 2824 env->eflags |= IF_MASK;
b9bec74b 2825 } else {
05330448 2826 env->eflags &= ~IF_MASK;
b9bec74b 2827 }
4b8523ee
JK		 2828
2829 /* We need to protect the apic state against concurrent accesses from
2830 * different threads in case the userspace irqchip is used. */
2831 if (!kvm_irqchip_in_kernel()) {
2832 qemu_mutex_lock_iothread();
2833 }
02e51483
CF		 2834 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2835 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2836 if (!kvm_irqchip_in_kernel()) {
2837 qemu_mutex_unlock_iothread();
2838 }
f794aa4a 2839 return cpu_get_mem_attrs(env);
05330448
AL		 2840}
2841
20d695a9 2842int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2843{
20d695a9
AF		 2844 X86CPU *cpu = X86_CPU(cs);
2845 CPUX86State *env = &cpu->env;
232fc23b 2846
259186a7 2847 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2848 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2849 assert(env->mcg_cap);
2850
259186a7 2851 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2852
dd1750d7 2853 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2854
2855 if (env->exception_injected == EXCP08_DBLE) {
2856 /* this means triple fault */
cf83f140 2857 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 2858 cs->exit_request = 1;
ab443475
JK		 2859 return 0;
2860 }
2861 env->exception_injected = EXCP12_MCHK;
2862 env->has_error_code = 0;
2863
259186a7 2864 cs->halted = 0;
ab443475
JK		 2865 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2866 env->mp_state = KVM_MP_STATE_RUNNABLE;
2867 }
2868 }
2869
fc12d72e
PB		 2870 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2871 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2872 kvm_cpu_synchronize_state(cs);
2873 do_cpu_init(cpu);
2874 }
2875
db1669bc
JK		 2876 if (kvm_irqchip_in_kernel()) {
2877 return 0;
2878 }
2879
259186a7
AF		 2880 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2881 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2882 apic_poll_irq(cpu->apic_state);
5d62c43a 2883 }
259186a7 2884 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2885 (env->eflags & IF_MASK)) ||
259186a7
AF		 2886 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2887 cs->halted = 0;
6792a57b 2888 }
259186a7 2889 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2890 kvm_cpu_synchronize_state(cs);
232fc23b 2891 do_cpu_sipi(cpu);
0af691d7 2892 }
259186a7
AF		 2893 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2894 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2895 kvm_cpu_synchronize_state(cs);
02e51483 2896 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2897 env->tpr_access_type);
2898 }
0af691d7 2899
259186a7 2900 return cs->halted;
0af691d7
MT		 2901}
2902
839b5630 2903static int kvm_handle_halt(X86CPU *cpu)
05330448 2904{
259186a7 2905 CPUState *cs = CPU(cpu);
839b5630
AF		 2906 CPUX86State *env = &cpu->env;
2907
259186a7 2908 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2909 (env->eflags & IF_MASK)) &&
259186a7
AF		 2910 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2911 cs->halted = 1;
bb4ea393 2912 return EXCP_HLT;
05330448
AL		 2913 }
2914
bb4ea393 2915 return 0;
05330448
AL		 2916}
2917
f7575c96 2918static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2919{
f7575c96
AF		 2920 CPUState *cs = CPU(cpu);
2921 struct kvm_run *run = cs->kvm_run;
d362e757 2922
02e51483 2923 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2924 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2925 : TPR_ACCESS_READ);
2926 return 1;
2927}
2928
f17ec444 2929int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2930{
38972938 2931 static const uint8_t int3 = 0xcc;
64bf3f4e 2932
f17ec444
AF		 2933 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2934 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2935 return -EINVAL;
b9bec74b 2936 }
e22a25c9
AL		 2937 return 0;
2938}
2939
f17ec444 2940int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2941{
2942 uint8_t int3;
2943
f17ec444
AF		 2944 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2945 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2946 return -EINVAL;
b9bec74b 2947 }
e22a25c9
AL		 2948 return 0;
2949}
2950
2951static struct {
2952 target_ulong addr;
2953 int len;
2954 int type;
2955} hw_breakpoint[4];
2956
2957static int nb_hw_breakpoint;
2958
2959static int find_hw_breakpoint(target_ulong addr, int len, int type)
2960{
2961 int n;
2962
b9bec74b 2963 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2964 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2965 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2966 return n;
b9bec74b
JK		 2967 }
2968 }
e22a25c9
AL		 2969 return -1;
2970}
2971
2972int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2973 target_ulong len, int type)
2974{
2975 switch (type) {
2976 case GDB_BREAKPOINT_HW:
2977 len = 1;
2978 break;
2979 case GDB_WATCHPOINT_WRITE:
2980 case GDB_WATCHPOINT_ACCESS:
2981 switch (len) {
2982 case 1:
2983 break;
2984 case 2:
2985 case 4:
2986 case 8:
b9bec74b 2987 if (addr & (len - 1)) {
e22a25c9 2988 return -EINVAL;
b9bec74b 2989 }
e22a25c9
AL		 2990 break;
2991 default:
2992 return -EINVAL;
2993 }
2994 break;
2995 default:
2996 return -ENOSYS;
2997 }
2998
b9bec74b 2999 if (nb_hw_breakpoint == 4) {
e22a25c9 3000 return -ENOBUFS;
b9bec74b
JK		 3001 }
3002 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3003 return -EEXIST;
b9bec74b 3004 }
e22a25c9
AL		 3005 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3006 hw_breakpoint[nb_hw_breakpoint].len = len;
3007 hw_breakpoint[nb_hw_breakpoint].type = type;
3008 nb_hw_breakpoint++;
3009
3010 return 0;
3011}
3012
3013int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3014 target_ulong len, int type)
3015{
3016 int n;
3017
3018 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3019 if (n < 0) {
e22a25c9 3020 return -ENOENT;
b9bec74b 3021 }
e22a25c9
AL		 3022 nb_hw_breakpoint--;
3023 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3024
3025 return 0;
3026}
3027
3028void kvm_arch_remove_all_hw_breakpoints(void)
3029{
3030 nb_hw_breakpoint = 0;
3031}
3032
3033static CPUWatchpoint hw_watchpoint;
3034
a60f24b5 3035static int kvm_handle_debug(X86CPU *cpu,
48405526 3036 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3037{
ed2803da 3038 CPUState *cs = CPU(cpu);
a60f24b5 3039 CPUX86State *env = &cpu->env;
f2574737 3040 int ret = 0;
e22a25c9
AL		 3041 int n;
3042
3043 if (arch_info->exception == 1) {
3044 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3045 if (cs->singlestep_enabled) {
f2574737 3046 ret = EXCP_DEBUG;
b9bec74b 3047 }
e22a25c9 3048 } else {
b9bec74b
JK		 3049 for (n = 0; n < 4; n++) {
3050 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3051 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3052 case 0x0:
f2574737 3053 ret = EXCP_DEBUG;
e22a25c9
AL		 3054 break;
3055 case 0x1:
f2574737 3056 ret = EXCP_DEBUG;
ff4700b0 3057 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3058 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3059 hw_watchpoint.flags = BP_MEM_WRITE;
3060 break;
3061 case 0x3:
f2574737 3062 ret = EXCP_DEBUG;
ff4700b0 3063 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3064 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3065 hw_watchpoint.flags = BP_MEM_ACCESS;
3066 break;
3067 }
b9bec74b
JK		 3068 }
3069 }
e22a25c9 3070 }
ff4700b0 3071 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3072 ret = EXCP_DEBUG;
b9bec74b 3073 }
f2574737 3074 if (ret == 0) {
ff4700b0 3075 cpu_synchronize_state(cs);
48405526 3076 assert(env->exception_injected == -1);
b0b1d690 3077
f2574737 3078 /* pass to guest */
48405526
BS		 3079 env->exception_injected = arch_info->exception;
3080 env->has_error_code = 0;
b0b1d690 3081 }
e22a25c9 3082
f2574737 3083 return ret;
e22a25c9
AL		 3084}
3085
20d695a9 3086void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3087{
3088 const uint8_t type_code[] = {
3089 [GDB_BREAKPOINT_HW] = 0x0,
3090 [GDB_WATCHPOINT_WRITE] = 0x1,
3091 [GDB_WATCHPOINT_ACCESS] = 0x3
3092 };
3093 const uint8_t len_code[] = {
3094 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3095 };
3096 int n;
3097
a60f24b5 3098 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3099 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3100 }
e22a25c9
AL		 3101 if (nb_hw_breakpoint > 0) {
3102 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3103 dbg->arch.debugreg[7] = 0x0600;
3104 for (n = 0; n < nb_hw_breakpoint; n++) {
3105 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3106 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3107 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3108 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3109 }
3110 }
3111}
4513d923 3112
2a4dac83
JK		 3113static bool host_supports_vmx(void)
3114{
3115 uint32_t ecx, unused;
3116
3117 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3118 return ecx & CPUID_EXT_VMX;
3119}
3120
3121#define VMX_INVALID_GUEST_STATE 0x80000021
3122
20d695a9 3123int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3124{
20d695a9 3125 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3126 uint64_t code;
3127 int ret;
3128
3129 switch (run->exit_reason) {
3130 case KVM_EXIT_HLT:
3131 DPRINTF("handle_hlt\n");
4b8523ee 3132 qemu_mutex_lock_iothread();
839b5630 3133 ret = kvm_handle_halt(cpu);
4b8523ee 3134 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3135 break;
3136 case KVM_EXIT_SET_TPR:
3137 ret = 0;
3138 break;
d362e757 3139 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3140 qemu_mutex_lock_iothread();
f7575c96 3141 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3142 qemu_mutex_unlock_iothread();
d362e757 3143 break;
2a4dac83
JK		 3144 case KVM_EXIT_FAIL_ENTRY:
3145 code = run->fail_entry.hardware_entry_failure_reason;
3146 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3147 code);
3148 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3149 fprintf(stderr,
12619721 3150 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3151 "unrestricted mode\n"
3152 "support, the failure can be most likely due to the guest "
3153 "entering an invalid\n"
3154 "state for Intel VT. For example, the guest maybe running "
3155 "in big real mode\n"
3156 "which is not supported on less recent Intel processors."
3157 "\n\n");
3158 }
3159 ret = -1;
3160 break;
3161 case KVM_EXIT_EXCEPTION:
3162 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3163 run->ex.exception, run->ex.error_code);
3164 ret = -1;
3165 break;
f2574737
JK		 3166 case KVM_EXIT_DEBUG:
3167 DPRINTF("kvm_exit_debug\n");
4b8523ee 3168 qemu_mutex_lock_iothread();
a60f24b5 3169 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3170 qemu_mutex_unlock_iothread();
f2574737 3171 break;
50efe82c
AS		 3172 case KVM_EXIT_HYPERV:
3173 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3174 break;
15eafc2e
PB		 3175 case KVM_EXIT_IOAPIC_EOI:
3176 ioapic_eoi_broadcast(run->eoi.vector);
3177 ret = 0;
3178 break;
2a4dac83
JK		 3179 default:
3180 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3181 ret = -1;
3182 break;
3183 }
3184
3185 return ret;
3186}
3187
20d695a9 3188bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3189{
20d695a9
AF		 3190 X86CPU *cpu = X86_CPU(cs);
3191 CPUX86State *env = &cpu->env;
3192
dd1750d7 3193 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3194 return !(env->cr[0] & CR0_PE_MASK) ||
3195 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3196}
84b058d7
JK		 3197
3198void kvm_arch_init_irq_routing(KVMState *s)
3199{
3200 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3201 /* If kernel can't do irq routing, interrupt source
3202 * override 0->2 cannot be set up as required by HPET.
3203 * So we have to disable it.
3204 */
3205 no_hpet = 1;
3206 }
cc7e0ddf 3207 /* We know at this point that we're using the in-kernel
614e41bc 3208 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3209 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3210 */
614e41bc 3211 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3212 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3213
3214 if (kvm_irqchip_is_split()) {
3215 int i;
3216
3217 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3218 MSI routes for signaling interrupts to the local apics. */
3219 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3220 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3221 error_report("Could not enable split IRQ mode.");
3222 exit(1);
3223 }
3224 }
3225 }
3226}
3227
3228int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3229{
3230 int ret;
3231 if (machine_kernel_irqchip_split(ms)) {
3232 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3233 if (ret) {
df3c286c 3234 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3235 strerror(-ret));
3236 exit(1);
3237 } else {
3238 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3239 kvm_split_irqchip = true;
3240 return 1;
3241 }
3242 } else {
3243 return 0;
3244 }
84b058d7 3245}
b139bd30
JK		 3246
3247/* Classic KVM device assignment interface. Will remain x86 only. */
3248int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3249 uint32_t flags, uint32_t *dev_id)
3250{
3251 struct kvm_assigned_pci_dev dev_data = {
3252 .segnr = dev_addr->domain,
3253 .busnr = dev_addr->bus,
3254 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3255 .flags = flags,
3256 };
3257 int ret;
3258
3259 dev_data.assigned_dev_id =
3260 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3261
3262 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3263 if (ret < 0) {
3264 return ret;
3265 }
3266
3267 *dev_id = dev_data.assigned_dev_id;
3268
3269 return 0;
3270}
3271
3272int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3273{
3274 struct kvm_assigned_pci_dev dev_data = {
3275 .assigned_dev_id = dev_id,
3276 };
3277
3278 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3279}
3280
3281static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3282 uint32_t irq_type, uint32_t guest_irq)
3283{
3284 struct kvm_assigned_irq assigned_irq = {
3285 .assigned_dev_id = dev_id,
3286 .guest_irq = guest_irq,
3287 .flags = irq_type,
3288 };
3289
3290 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3291 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3292 } else {
3293 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3294 }
3295}
3296
3297int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3298 uint32_t guest_irq)
3299{
3300 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3301 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3302
3303 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3304}
3305
3306int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3307{
3308 struct kvm_assigned_pci_dev dev_data = {
3309 .assigned_dev_id = dev_id,
3310 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3311 };
3312
3313 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3314}
3315
3316static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3317 uint32_t type)
3318{
3319 struct kvm_assigned_irq assigned_irq = {
3320 .assigned_dev_id = dev_id,
3321 .flags = type,
3322 };
3323
3324 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3325}
3326
3327int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3328{
3329 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3330 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3331}
3332
3333int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3334{
3335 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3336 KVM_DEV_IRQ_GUEST_MSI, virq);
3337}
3338
3339int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3340{
3341 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3342 KVM_DEV_IRQ_HOST_MSI);
3343}
3344
3345bool kvm_device_msix_supported(KVMState *s)
3346{
3347 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3348 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3349 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3350}
3351
3352int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3353 uint32_t nr_vectors)
3354{
3355 struct kvm_assigned_msix_nr msix_nr = {
3356 .assigned_dev_id = dev_id,
3357 .entry_nr = nr_vectors,
3358 };
3359
3360 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3361}
3362
3363int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3364 int virq)
3365{
3366 struct kvm_assigned_msix_entry msix_entry = {
3367 .assigned_dev_id = dev_id,
3368 .gsi = virq,
3369 .entry = vector,
3370 };
3371
3372 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3373}
3374
3375int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3376{
3377 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3378 KVM_DEV_IRQ_GUEST_MSIX, 0);
3379}
3380
3381int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3382{
3383 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3384 KVM_DEV_IRQ_HOST_MSIX);
3385}
9e03a040
FB		 3386
3387int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3388 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3389{
8b5ed7df
PX		 3390 X86IOMMUState *iommu = x86_iommu_get_default();
3391
3392 if (iommu) {
3393 int ret;
3394 MSIMessage src, dst;
3395 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3396
3397 src.address = route->u.msi.address_hi;
3398 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3399 src.address |= route->u.msi.address_lo;
3400 src.data = route->u.msi.data;
3401
3402 ret = class->int_remap(iommu, &src, &dst, dev ? \
3403 pci_requester_id(dev) : \
3404 X86_IOMMU_SID_INVALID);
3405 if (ret) {
3406 trace_kvm_x86_fixup_msi_error(route->gsi);
3407 return 1;
3408 }
3409
3410 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3411 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3412 route->u.msi.data = dst.data;
3413 }
3414
9e03a040
FB		 3415 return 0;
3416}
1850b6b7 3417
38d87493
PX		 3418typedef struct MSIRouteEntry MSIRouteEntry;
3419
3420struct MSIRouteEntry {
3421 PCIDevice *dev; /* Device pointer */
3422 int vector; /* MSI/MSIX vector index */
3423 int virq; /* Virtual IRQ index */
3424 QLIST_ENTRY(MSIRouteEntry) list;
3425};
3426
3427/* List of used GSI routes */
3428static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3429 QLIST_HEAD_INITIALIZER(msi_route_list);
3430
e1d4fb2d
PX		 3431static void kvm_update_msi_routes_all(void *private, bool global,
3432 uint32_t index, uint32_t mask)
3433{
3434 int cnt = 0;
3435 MSIRouteEntry *entry;
3436 MSIMessage msg;
fd563564
PX		 3437 PCIDevice *dev;
3438
e1d4fb2d
PX		 3439 /* TODO: explicit route update */
3440 QLIST_FOREACH(entry, &msi_route_list, list) {
3441 cnt++;
fd563564
PX		 3442 dev = entry->dev;
3443 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3444 continue;
3445 }
3446 msg = pci_get_msi_message(dev, entry->vector);
3447 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3448 }
3f1fea0f 3449 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3450 trace_kvm_x86_update_msi_routes(cnt);
3451}
3452
38d87493
PX		 3453int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3454 int vector, PCIDevice *dev)
3455{
e1d4fb2d 3456 static bool notify_list_inited = false;
38d87493
PX		 3457 MSIRouteEntry *entry;
3458
3459 if (!dev) {
3460 /* These are (possibly) IOAPIC routes only used for split
3461 * kernel irqchip mode, while what we are housekeeping are
3462 * PCI devices only. */
3463 return 0;
3464 }
3465
3466 entry = g_new0(MSIRouteEntry, 1);
3467 entry->dev = dev;
3468 entry->vector = vector;
3469 entry->virq = route->gsi;
3470 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3471
3472 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3473
3474 if (!notify_list_inited) {
3475 /* For the first time we do add route, add ourselves into
3476 * IOMMU's IEC notify list if needed. */
3477 X86IOMMUState *iommu = x86_iommu_get_default();
3478 if (iommu) {
3479 x86_iommu_iec_register_notifier(iommu,
3480 kvm_update_msi_routes_all,
3481 NULL);
3482 }
3483 notify_list_inited = true;
3484 }
38d87493
PX		 3485 return 0;
3486}
3487
3488int kvm_arch_release_virq_post(int virq)
3489{
3490 MSIRouteEntry *entry, *next;
3491 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3492 if (entry->virq == virq) {
3493 trace_kvm_x86_remove_msi_route(virq);
3494 QLIST_REMOVE(entry, list);
3495 break;
3496 }
3497 }
9e03a040
FB		 3498 return 0;
3499}
1850b6b7
EA		 3500
3501int kvm_arch_msi_data_to_gsi(uint32_t data)
3502{
3503 abort();
3504}
QEMU mirror