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target-i386: Don't set any KVM flag by default if KVM is disabled
[qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
c6dc6f63 26
1de7afc9
PB		 27#include "qemu/option.h"
28#include "qemu/config-file.h"
7b1b5d19 29#include "qapi/qmp/qerror.h"
c6dc6f63 30
7b1b5d19 31#include "qapi/visitor.h"
9c17d615 32#include "sysemu/arch_init.h"
71ad61d3 33
28f52cc0
VR		 34#include "hyperv.h"
35
65dee380 36#include "hw/hw.h"
b834b508 37#if defined(CONFIG_KVM)
ef8621b1 38#include <linux/kvm_para.h>
b834b508 39#endif
65dee380 40
9c17d615 41#include "sysemu/sysemu.h"
bdeec802
IM		 42#ifndef CONFIG_USER_ONLY
43#include "hw/xen.h"
44#include "hw/sysbus.h"
449994eb 45#include "hw/apic_internal.h"
bdeec802
IM		 46#endif
47
c6dc6f63
AP		 48/* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61};
62static const char *ext_feature_name[] = {
f370be3c 63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 64 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 65 "tm2", "ssse3", "cid", NULL,
e117f772 66 "fma", "cx16", "xtpr", "pdcm",
434acb81 67 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 69 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 70 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 71};
3b671a40
EH		 72/* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
c6dc6f63 77static const char *ext2_feature_name[] = {
3b671a40
EH		 78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 85 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 86};
87static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 90 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 95 NULL, NULL, NULL, NULL,
96};
97
89e49c8b
EH		 98static const char *ext4_feature_name[] = {
99 NULL, NULL, "xstore", "xstore-en",
100 NULL, NULL, "xcrypt", "xcrypt-en",
101 "ace2", "ace2-en", "phe", "phe-en",
102 "pmm", "pmm-en", NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107};
108
c6dc6f63 109static const char *kvm_feature_name[] = {
c3d39807
DS		 110 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
111 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
112 NULL, NULL, NULL, NULL,
113 NULL, NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 118};
119
296acb64
JR		 120static const char *svm_feature_name[] = {
121 "npt", "lbrv", "svm_lock", "nrip_save",
122 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
123 NULL, NULL, "pause_filter", NULL,
124 "pfthreshold", NULL, NULL, NULL,
125 NULL, NULL, NULL, NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129};
130
a9321a4d 131static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 132 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
133 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 134 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 135 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
136};
137
5ef57876
EH		 138typedef struct FeatureWordInfo {
139 const char **feat_names;
bffd67b0
EH		 140 uint32_t cpuid_eax; /* Input EAX for CPUID */
141 int cpuid_reg; /* R_* register constant */
5ef57876
EH		 142} FeatureWordInfo;
143
144static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 145 [FEAT_1_EDX] = {
146 .feat_names = feature_name,
147 .cpuid_eax = 1, .cpuid_reg = R_EDX,
148 },
149 [FEAT_1_ECX] = {
150 .feat_names = ext_feature_name,
151 .cpuid_eax = 1, .cpuid_reg = R_ECX,
152 },
153 [FEAT_8000_0001_EDX] = {
154 .feat_names = ext2_feature_name,
155 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
156 },
157 [FEAT_8000_0001_ECX] = {
158 .feat_names = ext3_feature_name,
159 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
160 },
89e49c8b
EH		 161 [FEAT_C000_0001_EDX] = {
162 .feat_names = ext4_feature_name,
163 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
164 },
bffd67b0
EH		 165 [FEAT_KVM] = {
166 .feat_names = kvm_feature_name,
167 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
168 },
169 [FEAT_SVM] = {
170 .feat_names = svm_feature_name,
171 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
172 },
173 [FEAT_7_0_EBX] = {
174 .feat_names = cpuid_7_0_ebx_feature_name,
175 .cpuid_eax = 7, .cpuid_reg = R_EBX,
176 },
5ef57876
EH		 177};
178
8b4beddc
EH		 179const char *get_register_name_32(unsigned int reg)
180{
181 static const char *reg_names[CPU_NB_REGS32] = {
182 [R_EAX] = "EAX",
183 [R_ECX] = "ECX",
184 [R_EDX] = "EDX",
185 [R_EBX] = "EBX",
186 [R_ESP] = "ESP",
187 [R_EBP] = "EBP",
188 [R_ESI] = "ESI",
189 [R_EDI] = "EDI",
190 };
191
192 if (reg > CPU_NB_REGS32) {
193 return NULL;
194 }
195 return reg_names[reg];
196}
197
c6dc6f63
AP		 198/* collects per-function cpuid data
199 */
200typedef struct model_features_t {
201 uint32_t *guest_feat;
202 uint32_t *host_feat;
bffd67b0 203 FeatureWord feat_word;
8b4beddc 204} model_features_t;
c6dc6f63
AP		 205
206int check_cpuid = 0;
207int enforce_cpuid = 0;
208
dc59944b
MT		 209static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
210 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 211 (1 << KVM_FEATURE_CLOCKSOURCE2) |
212 (1 << KVM_FEATURE_ASYNC_PF) |
213 (1 << KVM_FEATURE_STEAL_TIME) |
214 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
dc59944b
MT		 215
216void enable_kvm_pv_eoi(void)
217{
aa87d458 218 kvm_default_features |= (1UL << KVM_FEATURE_PV_EOI);
dc59944b
MT		 219}
220
bb44e0d1
JK		 221void host_cpuid(uint32_t function, uint32_t count,
222 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 223{
224#if defined(CONFIG_KVM)
a1fd24af
AL		 225 uint32_t vec[4];
226
227#ifdef __x86_64__
228 asm volatile("cpuid"
229 : "=a"(vec[0]), "=b"(vec[1]),
230 "=c"(vec[2]), "=d"(vec[3])
231 : "0"(function), "c"(count) : "cc");
232#else
233 asm volatile("pusha \n\t"
234 "cpuid \n\t"
235 "mov %%eax, 0(%2) \n\t"
236 "mov %%ebx, 4(%2) \n\t"
237 "mov %%ecx, 8(%2) \n\t"
238 "mov %%edx, 12(%2) \n\t"
239 "popa"
240 : : "a"(function), "c"(count), "S"(vec)
241 : "memory", "cc");
242#endif
243
bdde476a 244 if (eax)
a1fd24af 245 *eax = vec[0];
bdde476a 246 if (ebx)
a1fd24af 247 *ebx = vec[1];
bdde476a 248 if (ecx)
a1fd24af 249 *ecx = vec[2];
bdde476a 250 if (edx)
a1fd24af 251 *edx = vec[3];
bdde476a
AP		 252#endif
253}
c6dc6f63
AP		 254
255#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
256
257/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
258 * a substring. ex if !NULL points to the first char after a substring,
259 * otherwise the string is assumed to sized by a terminating nul.
260 * Return lexical ordering of *s1:*s2.
261 */
262static int sstrcmp(const char *s1, const char *e1, const char *s2,
263 const char *e2)
264{
265 for (;;) {
266 if (!*s1 || !*s2 || *s1 != *s2)
267 return (*s1 - *s2);
268 ++s1, ++s2;
269 if (s1 == e1 && s2 == e2)
270 return (0);
271 else if (s1 == e1)
272 return (*s2);
273 else if (s2 == e2)
274 return (*s1);
275 }
276}
277
278/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
279 * '|' delimited (possibly empty) strings in which case search for a match
280 * within the alternatives proceeds left to right. Return 0 for success,
281 * non-zero otherwise.
282 */
283static int altcmp(const char *s, const char *e, const char *altstr)
284{
285 const char *p, *q;
286
287 for (q = p = altstr; ; ) {
288 while (*p && *p != '|')
289 ++p;
290 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
291 return (0);
292 if (!*p)
293 return (1);
294 else
295 q = ++p;
296 }
297}
298
299/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 300 * *pval and return true, otherwise return false
c6dc6f63 301 */
e41e0fc6
JK		 302static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
303 const char **featureset)
c6dc6f63
AP		 304{
305 uint32_t mask;
306 const char **ppc;
e41e0fc6 307 bool found = false;
c6dc6f63 308
e41e0fc6 309 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 310 if (*ppc && !altcmp(s, e, *ppc)) {
311 *pval |= mask;
e41e0fc6 312 found = true;
c6dc6f63 313 }
e41e0fc6
JK		 314 }
315 return found;
c6dc6f63
AP		 316}
317
5ef57876
EH		 318static void add_flagname_to_bitmaps(const char *flagname,
319 FeatureWordArray words)
c6dc6f63 320{
5ef57876
EH		 321 FeatureWord w;
322 for (w = 0; w < FEATURE_WORDS; w++) {
323 FeatureWordInfo *wi = &feature_word_info[w];
324 if (wi->feat_names &&
325 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
326 break;
327 }
328 }
329 if (w == FEATURE_WORDS) {
330 fprintf(stderr, "CPU feature %s not found\n", flagname);
331 }
c6dc6f63
AP		 332}
333
334typedef struct x86_def_t {
335 struct x86_def_t *next;
336 const char *name;
337 uint32_t level;
338 uint32_t vendor1, vendor2, vendor3;
339 int family;
340 int model;
341 int stepping;
b862d1fe 342 int tsc_khz;
296acb64
JR		 343 uint32_t features, ext_features, ext2_features, ext3_features;
344 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 345 uint32_t xlevel;
346 char model_id[48];
347 int vendor_override;
b3baa152 348 /* Store the results of Centaur's CPUID instructions */
349 uint32_t ext4_features;
350 uint32_t xlevel2;
13526728
EH		 351 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
352 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 353} x86_def_t;
354
355#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
356#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
357 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
358#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
359 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
360 CPUID_PSE36 | CPUID_FXSR)
361#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
362#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
363 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
364 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
365 CPUID_PAE | CPUID_SEP | CPUID_APIC)
366
551a2dec
AP		 367#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
368 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
369 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
370 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
371 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 372 /* partly implemented:
373 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
374 CPUID_PSE36 (needed for Solaris) */
375 /* missing:
376 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 377#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
a0a70681 378 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 379 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 380 /* missing:
381 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 382 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 383#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 384 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
385 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 386 /* missing:
387 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 388#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
389 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 390#define TCG_SVM_FEATURES 0
a9321a4d 391#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
551a2dec 392
c6dc6f63
AP		 393/* maintains list of cpu model definitions
394 */
395static x86_def_t *x86_defs = {NULL};
396
397/* built-in cpu model definitions (deprecated)
398 */
399static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 400 {
401 .name = "qemu64",
402 .level = 4,
403 .vendor1 = CPUID_VENDOR_AMD_1,
404 .vendor2 = CPUID_VENDOR_AMD_2,
405 .vendor3 = CPUID_VENDOR_AMD_3,
406 .family = 6,
407 .model = 2,
408 .stepping = 3,
409 .features = PPRO_FEATURES |
c6dc6f63 410 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 411 CPUID_PSE36,
412 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 413 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 414 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
415 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
416 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
417 .xlevel = 0x8000000A,
c6dc6f63
AP		 418 },
419 {
420 .name = "phenom",
421 .level = 5,
422 .vendor1 = CPUID_VENDOR_AMD_1,
423 .vendor2 = CPUID_VENDOR_AMD_2,
424 .vendor3 = CPUID_VENDOR_AMD_3,
425 .family = 16,
426 .model = 2,
427 .stepping = 3,
c6dc6f63
AP		 428 .features = PPRO_FEATURES |
429 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 430 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 431 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
432 CPUID_EXT_POPCNT,
60032ac0 433 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 434 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
435 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 436 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 437 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
438 CPUID_EXT3_CR8LEG,
439 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
440 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
441 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
442 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 443 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 444 .xlevel = 0x8000001A,
445 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
446 },
447 {
448 .name = "core2duo",
449 .level = 10,
ebe8b9c6
IM		 450 .vendor1 = CPUID_VENDOR_INTEL_1,
451 .vendor2 = CPUID_VENDOR_INTEL_2,
452 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 453 .family = 6,
454 .model = 15,
455 .stepping = 11,
c6dc6f63
AP		 456 .features = PPRO_FEATURES |
457 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 458 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
459 CPUID_HT | CPUID_TM | CPUID_PBE,
460 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
461 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
462 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 463 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
464 .ext3_features = CPUID_EXT3_LAHF_LM,
465 .xlevel = 0x80000008,
466 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
467 },
468 {
469 .name = "kvm64",
470 .level = 5,
471 .vendor1 = CPUID_VENDOR_INTEL_1,
472 .vendor2 = CPUID_VENDOR_INTEL_2,
473 .vendor3 = CPUID_VENDOR_INTEL_3,
474 .family = 15,
475 .model = 6,
476 .stepping = 1,
477 /* Missing: CPUID_VME, CPUID_HT */
478 .features = PPRO_FEATURES |
479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
480 CPUID_PSE36,
481 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
482 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
483 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 484 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 485 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
486 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
487 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
488 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
489 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
490 .ext3_features = 0,
491 .xlevel = 0x80000008,
492 .model_id = "Common KVM processor"
493 },
c6dc6f63
AP		 494 {
495 .name = "qemu32",
496 .level = 4,
ebe8b9c6
IM		 497 .vendor1 = CPUID_VENDOR_INTEL_1,
498 .vendor2 = CPUID_VENDOR_INTEL_2,
499 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 500 .family = 6,
501 .model = 3,
502 .stepping = 3,
503 .features = PPRO_FEATURES,
504 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 505 .xlevel = 0x80000004,
c6dc6f63 506 },
eafaf1e5
AP		 507 {
508 .name = "kvm32",
509 .level = 5,
ebe8b9c6
IM		 510 .vendor1 = CPUID_VENDOR_INTEL_1,
511 .vendor2 = CPUID_VENDOR_INTEL_2,
512 .vendor3 = CPUID_VENDOR_INTEL_3,
eafaf1e5
AP		 513 .family = 15,
514 .model = 6,
515 .stepping = 1,
516 .features = PPRO_FEATURES |
517 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
518 .ext_features = CPUID_EXT_SSE3,
60032ac0 519 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 520 .ext3_features = 0,
521 .xlevel = 0x80000008,
522 .model_id = "Common 32-bit KVM processor"
523 },
c6dc6f63
AP		 524 {
525 .name = "coreduo",
526 .level = 10,
ebe8b9c6
IM		 527 .vendor1 = CPUID_VENDOR_INTEL_1,
528 .vendor2 = CPUID_VENDOR_INTEL_2,
529 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 530 .family = 6,
531 .model = 14,
532 .stepping = 8,
c6dc6f63 533 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 534 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
535 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
536 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
537 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 538 .ext2_features = CPUID_EXT2_NX,
539 .xlevel = 0x80000008,
540 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
541 },
542 {
543 .name = "486",
58012d66 544 .level = 1,
ebe8b9c6
IM		 545 .vendor1 = CPUID_VENDOR_INTEL_1,
546 .vendor2 = CPUID_VENDOR_INTEL_2,
547 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 548 .family = 4,
549 .model = 0,
550 .stepping = 0,
551 .features = I486_FEATURES,
552 .xlevel = 0,
553 },
554 {
555 .name = "pentium",
556 .level = 1,
ebe8b9c6
IM		 557 .vendor1 = CPUID_VENDOR_INTEL_1,
558 .vendor2 = CPUID_VENDOR_INTEL_2,
559 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 560 .family = 5,
561 .model = 4,
562 .stepping = 3,
563 .features = PENTIUM_FEATURES,
564 .xlevel = 0,
565 },
566 {
567 .name = "pentium2",
568 .level = 2,
ebe8b9c6
IM		 569 .vendor1 = CPUID_VENDOR_INTEL_1,
570 .vendor2 = CPUID_VENDOR_INTEL_2,
571 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 572 .family = 6,
573 .model = 5,
574 .stepping = 2,
575 .features = PENTIUM2_FEATURES,
576 .xlevel = 0,
577 },
578 {
579 .name = "pentium3",
580 .level = 2,
ebe8b9c6
IM		 581 .vendor1 = CPUID_VENDOR_INTEL_1,
582 .vendor2 = CPUID_VENDOR_INTEL_2,
583 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 584 .family = 6,
585 .model = 7,
586 .stepping = 3,
587 .features = PENTIUM3_FEATURES,
588 .xlevel = 0,
589 },
590 {
591 .name = "athlon",
592 .level = 2,
593 .vendor1 = CPUID_VENDOR_AMD_1,
594 .vendor2 = CPUID_VENDOR_AMD_2,
595 .vendor3 = CPUID_VENDOR_AMD_3,
596 .family = 6,
597 .model = 2,
598 .stepping = 3,
60032ac0
EH		 599 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
600 CPUID_MCA,
601 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
602 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 603 .xlevel = 0x80000008,
c6dc6f63
AP		 604 },
605 {
606 .name = "n270",
607 /* original is on level 10 */
608 .level = 5,
ebe8b9c6
IM		 609 .vendor1 = CPUID_VENDOR_INTEL_1,
610 .vendor2 = CPUID_VENDOR_INTEL_2,
611 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 612 .family = 6,
613 .model = 28,
614 .stepping = 2,
615 .features = PPRO_FEATURES |
8560efed
AJ		 616 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
617 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 618 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 619 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
620 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 621 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
622 CPUID_EXT2_NX,
8560efed 623 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 624 .xlevel = 0x8000000A,
625 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
626 },
3eca4642
EH		 627 {
628 .name = "Conroe",
629 .level = 2,
630 .vendor1 = CPUID_VENDOR_INTEL_1,
631 .vendor2 = CPUID_VENDOR_INTEL_2,
632 .vendor3 = CPUID_VENDOR_INTEL_3,
633 .family = 6,
634 .model = 2,
635 .stepping = 3,
636 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
637 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
638 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
639 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
640 CPUID_DE | CPUID_FP87,
641 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
642 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
643 .ext3_features = CPUID_EXT3_LAHF_LM,
644 .xlevel = 0x8000000A,
645 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
646 },
647 {
648 .name = "Penryn",
649 .level = 2,
650 .vendor1 = CPUID_VENDOR_INTEL_1,
651 .vendor2 = CPUID_VENDOR_INTEL_2,
652 .vendor3 = CPUID_VENDOR_INTEL_3,
653 .family = 6,
654 .model = 2,
655 .stepping = 3,
656 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
657 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
658 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
659 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
660 CPUID_DE | CPUID_FP87,
661 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
662 CPUID_EXT_SSE3,
663 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
664 .ext3_features = CPUID_EXT3_LAHF_LM,
665 .xlevel = 0x8000000A,
666 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
667 },
668 {
669 .name = "Nehalem",
670 .level = 2,
671 .vendor1 = CPUID_VENDOR_INTEL_1,
672 .vendor2 = CPUID_VENDOR_INTEL_2,
673 .vendor3 = CPUID_VENDOR_INTEL_3,
674 .family = 6,
675 .model = 2,
676 .stepping = 3,
677 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
678 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
679 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
680 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
681 CPUID_DE | CPUID_FP87,
682 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
683 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
684 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
685 .ext3_features = CPUID_EXT3_LAHF_LM,
686 .xlevel = 0x8000000A,
687 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
688 },
689 {
690 .name = "Westmere",
691 .level = 11,
692 .vendor1 = CPUID_VENDOR_INTEL_1,
693 .vendor2 = CPUID_VENDOR_INTEL_2,
694 .vendor3 = CPUID_VENDOR_INTEL_3,
695 .family = 6,
696 .model = 44,
697 .stepping = 1,
698 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
699 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
700 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
701 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
702 CPUID_DE | CPUID_FP87,
703 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
704 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
705 CPUID_EXT_SSE3,
706 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
707 .ext3_features = CPUID_EXT3_LAHF_LM,
708 .xlevel = 0x8000000A,
709 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
710 },
711 {
712 .name = "SandyBridge",
713 .level = 0xd,
714 .vendor1 = CPUID_VENDOR_INTEL_1,
715 .vendor2 = CPUID_VENDOR_INTEL_2,
716 .vendor3 = CPUID_VENDOR_INTEL_3,
717 .family = 6,
718 .model = 42,
719 .stepping = 1,
720 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
721 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
722 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
723 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
724 CPUID_DE | CPUID_FP87,
725 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
726 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
727 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
728 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
729 CPUID_EXT_SSE3,
730 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
731 CPUID_EXT2_SYSCALL,
732 .ext3_features = CPUID_EXT3_LAHF_LM,
733 .xlevel = 0x8000000A,
734 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
735 },
37507094
EH		 736 {
737 .name = "Haswell",
738 .level = 0xd,
739 .vendor1 = CPUID_VENDOR_INTEL_1,
740 .vendor2 = CPUID_VENDOR_INTEL_2,
741 .vendor3 = CPUID_VENDOR_INTEL_3,
742 .family = 6,
743 .model = 60,
744 .stepping = 1,
745 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
746 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 747 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 748 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
749 CPUID_DE | CPUID_FP87,
750 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
751 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
752 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
753 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
754 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
755 CPUID_EXT_PCID,
80ae4160
EH		 756 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
757 CPUID_EXT2_SYSCALL,
37507094
EH		 758 .ext3_features = CPUID_EXT3_LAHF_LM,
759 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
760 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
761 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
762 CPUID_7_0_EBX_RTM,
763 .xlevel = 0x8000000A,
764 .model_id = "Intel Core Processor (Haswell)",
765 },
3eca4642
EH		 766 {
767 .name = "Opteron_G1",
768 .level = 5,
769 .vendor1 = CPUID_VENDOR_AMD_1,
770 .vendor2 = CPUID_VENDOR_AMD_2,
771 .vendor3 = CPUID_VENDOR_AMD_3,
772 .family = 15,
773 .model = 6,
774 .stepping = 1,
775 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
776 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
777 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
778 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
779 CPUID_DE | CPUID_FP87,
780 .ext_features = CPUID_EXT_SSE3,
781 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
782 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
783 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
784 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
785 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
786 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
787 .xlevel = 0x80000008,
788 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
789 },
790 {
791 .name = "Opteron_G2",
792 .level = 5,
793 .vendor1 = CPUID_VENDOR_AMD_1,
794 .vendor2 = CPUID_VENDOR_AMD_2,
795 .vendor3 = CPUID_VENDOR_AMD_3,
796 .family = 15,
797 .model = 6,
798 .stepping = 1,
799 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
800 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
801 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
802 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
803 CPUID_DE | CPUID_FP87,
804 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
805 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
806 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
807 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
808 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
809 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
810 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
811 CPUID_EXT2_DE | CPUID_EXT2_FPU,
812 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
813 .xlevel = 0x80000008,
814 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
815 },
816 {
817 .name = "Opteron_G3",
818 .level = 5,
819 .vendor1 = CPUID_VENDOR_AMD_1,
820 .vendor2 = CPUID_VENDOR_AMD_2,
821 .vendor3 = CPUID_VENDOR_AMD_3,
822 .family = 15,
823 .model = 6,
824 .stepping = 1,
825 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
826 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
827 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
828 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
829 CPUID_DE | CPUID_FP87,
830 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
831 CPUID_EXT_SSE3,
832 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
833 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
834 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
835 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
836 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
837 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
838 CPUID_EXT2_DE | CPUID_EXT2_FPU,
839 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
840 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
841 .xlevel = 0x80000008,
842 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
843 },
844 {
845 .name = "Opteron_G4",
846 .level = 0xd,
847 .vendor1 = CPUID_VENDOR_AMD_1,
848 .vendor2 = CPUID_VENDOR_AMD_2,
849 .vendor3 = CPUID_VENDOR_AMD_3,
850 .family = 21,
851 .model = 1,
852 .stepping = 2,
853 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
854 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
855 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
856 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
857 CPUID_DE | CPUID_FP87,
858 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
859 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
860 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
861 CPUID_EXT_SSE3,
862 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
863 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
864 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
865 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
866 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
867 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
868 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
869 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
870 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
871 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
872 CPUID_EXT3_LAHF_LM,
873 .xlevel = 0x8000001A,
874 .model_id = "AMD Opteron 62xx class CPU",
875 },
021941b9
AP		 876 {
877 .name = "Opteron_G5",
878 .level = 0xd,
879 .vendor1 = CPUID_VENDOR_AMD_1,
880 .vendor2 = CPUID_VENDOR_AMD_2,
881 .vendor3 = CPUID_VENDOR_AMD_3,
882 .family = 21,
883 .model = 2,
884 .stepping = 0,
885 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
886 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
887 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
888 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
889 CPUID_DE | CPUID_FP87,
890 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
891 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
892 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
893 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
894 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
895 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
896 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
897 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
898 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
899 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
900 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
901 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
902 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
903 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
904 CPUID_EXT3_LAHF_LM,
905 .xlevel = 0x8000001A,
906 .model_id = "AMD Opteron 63xx class CPU",
907 },
c6dc6f63
AP		 908};
909
e4ab0d6b 910#ifdef CONFIG_KVM
c6dc6f63
AP		 911static int cpu_x86_fill_model_id(char *str)
912{
913 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
914 int i;
915
916 for (i = 0; i < 3; i++) {
917 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
918 memcpy(str + i * 16 + 0, &eax, 4);
919 memcpy(str + i * 16 + 4, &ebx, 4);
920 memcpy(str + i * 16 + 8, &ecx, 4);
921 memcpy(str + i * 16 + 12, &edx, 4);
922 }
923 return 0;
924}
e4ab0d6b 925#endif
c6dc6f63 926
6e746f30
EH		 927/* Fill a x86_def_t struct with information about the host CPU, and
928 * the CPU features supported by the host hardware + host kernel
929 *
930 * This function may be called only if KVM is enabled.
931 */
932static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 933{
e4ab0d6b 934#ifdef CONFIG_KVM
12869995 935 KVMState *s = kvm_state;
c6dc6f63
AP		 936 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
937
6e746f30
EH		 938 assert(kvm_enabled());
939
c6dc6f63
AP		 940 x86_cpu_def->name = "host";
941 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
c6dc6f63
AP		 942 x86_cpu_def->vendor1 = ebx;
943 x86_cpu_def->vendor2 = edx;
944 x86_cpu_def->vendor3 = ecx;
945
946 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
947 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
948 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
949 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 950
12869995
EH		 951 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
952 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
953 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 954
6e746f30 955 if (x86_cpu_def->level >= 7) {
12869995
EH		 956 x86_cpu_def->cpuid_7_0_ebx_features =
957 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728
EH		 958 } else {
959 x86_cpu_def->cpuid_7_0_ebx_features = 0;
960 }
961
12869995
EH		 962 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
963 x86_cpu_def->ext2_features =
964 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
965 x86_cpu_def->ext3_features =
966 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 967
c6dc6f63
AP		 968 cpu_x86_fill_model_id(x86_cpu_def->model_id);
969 x86_cpu_def->vendor_override = 0;
970
b3baa152 971 /* Call Centaur's CPUID instruction. */
972 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
973 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
974 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
975 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 976 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152 977 if (eax >= 0xC0000001) {
978 /* Support VIA max extended level */
979 x86_cpu_def->xlevel2 = eax;
980 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
12869995
EH		 981 x86_cpu_def->ext4_features =
982 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152 983 }
984 }
296acb64 985
fcb93c03
EH		 986 /* Other KVM-specific feature fields: */
987 x86_cpu_def->svm_features =
988 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
bd004bef
EH		 989 x86_cpu_def->kvm_features =
990 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 991
e4ab0d6b 992#endif /* CONFIG_KVM */
c6dc6f63
AP		 993}
994
bffd67b0 995static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 996{
997 int i;
998
999 for (i = 0; i < 32; ++i)
1000 if (1 << i & mask) {
bffd67b0 1001 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1002 assert(reg);
1003 fprintf(stderr, "warning: host doesn't support requested feature: "
1004 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1005 f->cpuid_eax, reg,
1006 f->feat_names[i] ? "." : "",
1007 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1008 break;
1009 }
1010 return 0;
1011}
1012
07ca5945
EH		 1013/* Check if all requested cpu flags are making their way to the guest
1014 *
1015 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1016 *
1017 * This function may be called only if KVM is enabled.
c6dc6f63 1018 */
5ec01c2e 1019static int kvm_check_features_against_host(X86CPU *cpu)
c6dc6f63 1020{
5ec01c2e 1021 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 1022 x86_def_t host_def;
1023 uint32_t mask;
1024 int rv, i;
1025 struct model_features_t ft[] = {
5ec01c2e 1026 {&env->cpuid_features, &host_def.features,
bffd67b0 1027 FEAT_1_EDX },
5ec01c2e 1028 {&env->cpuid_ext_features, &host_def.ext_features,
bffd67b0 1029 FEAT_1_ECX },
5ec01c2e 1030 {&env->cpuid_ext2_features, &host_def.ext2_features,
bffd67b0 1031 FEAT_8000_0001_EDX },
5ec01c2e 1032 {&env->cpuid_ext3_features, &host_def.ext3_features,
bffd67b0 1033 FEAT_8000_0001_ECX },
5ec01c2e 1034 {&env->cpuid_ext4_features, &host_def.ext4_features,
07ca5945 1035 FEAT_C000_0001_EDX },
5ec01c2e 1036 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
07ca5945 1037 FEAT_7_0_EBX },
5ec01c2e 1038 {&env->cpuid_svm_features, &host_def.svm_features,
07ca5945 1039 FEAT_SVM },
5ec01c2e 1040 {&env->cpuid_kvm_features, &host_def.kvm_features,
07ca5945 1041 FEAT_KVM },
8b4beddc 1042 };
c6dc6f63 1043
6e746f30
EH		 1044 assert(kvm_enabled());
1045
1046 kvm_cpu_fill_host(&host_def);
bffd67b0
EH		 1047 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1048 FeatureWord w = ft[i].feat_word;
1049 FeatureWordInfo *wi = &feature_word_info[w];
1050 for (mask = 1; mask; mask <<= 1) {
e8beac00 1051 if (*ft[i].guest_feat & mask &&
c6dc6f63 1052 !(*ft[i].host_feat & mask)) {
bffd67b0
EH		 1053 unavailable_host_feature(wi, mask);
1054 rv = 1;
1055 }
1056 }
1057 }
c6dc6f63
AP		 1058 return rv;
1059}
1060
95b8519d
AF		 1061static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1062 const char *name, Error **errp)
1063{
1064 X86CPU *cpu = X86_CPU(obj);
1065 CPUX86State *env = &cpu->env;
1066 int64_t value;
1067
1068 value = (env->cpuid_version >> 8) & 0xf;
1069 if (value == 0xf) {
1070 value += (env->cpuid_version >> 20) & 0xff;
1071 }
1072 visit_type_int(v, &value, name, errp);
1073}
1074
71ad61d3
AF		 1075static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1076 const char *name, Error **errp)
ed5e1ec3 1077{
71ad61d3
AF		 1078 X86CPU *cpu = X86_CPU(obj);
1079 CPUX86State *env = &cpu->env;
1080 const int64_t min = 0;
1081 const int64_t max = 0xff + 0xf;
1082 int64_t value;
1083
1084 visit_type_int(v, &value, name, errp);
1085 if (error_is_set(errp)) {
1086 return;
1087 }
1088 if (value < min || value > max) {
1089 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1090 name ? name : "null", value, min, max);
1091 return;
1092 }
1093
ed5e1ec3 1094 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1095 if (value > 0x0f) {
1096 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1097 } else {
71ad61d3 1098 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1099 }
1100}
1101
67e30c83
AF		 1102static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1103 const char *name, Error **errp)
1104{
1105 X86CPU *cpu = X86_CPU(obj);
1106 CPUX86State *env = &cpu->env;
1107 int64_t value;
1108
1109 value = (env->cpuid_version >> 4) & 0xf;
1110 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1111 visit_type_int(v, &value, name, errp);
1112}
1113
c5291a4f
AF		 1114static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1115 const char *name, Error **errp)
b0704cbd 1116{
c5291a4f
AF		 1117 X86CPU *cpu = X86_CPU(obj);
1118 CPUX86State *env = &cpu->env;
1119 const int64_t min = 0;
1120 const int64_t max = 0xff;
1121 int64_t value;
1122
1123 visit_type_int(v, &value, name, errp);
1124 if (error_is_set(errp)) {
1125 return;
1126 }
1127 if (value < min || value > max) {
1128 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1129 name ? name : "null", value, min, max);
1130 return;
1131 }
1132
b0704cbd 1133 env->cpuid_version &= ~0xf00f0;
c5291a4f 1134 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1135}
1136
35112e41
AF		 1137static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1138 void *opaque, const char *name,
1139 Error **errp)
1140{
1141 X86CPU *cpu = X86_CPU(obj);
1142 CPUX86State *env = &cpu->env;
1143 int64_t value;
1144
1145 value = env->cpuid_version & 0xf;
1146 visit_type_int(v, &value, name, errp);
1147}
1148
036e2222
AF		 1149static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1150 void *opaque, const char *name,
1151 Error **errp)
38c3dc46 1152{
036e2222
AF		 1153 X86CPU *cpu = X86_CPU(obj);
1154 CPUX86State *env = &cpu->env;
1155 const int64_t min = 0;
1156 const int64_t max = 0xf;
1157 int64_t value;
1158
1159 visit_type_int(v, &value, name, errp);
1160 if (error_is_set(errp)) {
1161 return;
1162 }
1163 if (value < min || value > max) {
1164 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1165 name ? name : "null", value, min, max);
1166 return;
1167 }
1168
38c3dc46 1169 env->cpuid_version &= ~0xf;
036e2222 1170 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1171}
1172
8e1898bf
AF		 1173static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1174 const char *name, Error **errp)
1175{
1176 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1177
fa029887 1178 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1179}
1180
1181static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1182 const char *name, Error **errp)
1183{
1184 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1185
fa029887 1186 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1187}
1188
16b93aa8
AF		 1189static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1190 const char *name, Error **errp)
1191{
1192 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1193
fa029887 1194 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1195}
1196
1197static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1198 const char *name, Error **errp)
1199{
1200 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1201
fa029887 1202 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1203}
1204
d480e1af
AF		 1205static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1206{
1207 X86CPU *cpu = X86_CPU(obj);
1208 CPUX86State *env = &cpu->env;
1209 char *value;
1210 int i;
1211
9df694ee 1212 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
d480e1af
AF		 1213 for (i = 0; i < 4; i++) {
1214 value[i ] = env->cpuid_vendor1 >> (8 * i);
1215 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1216 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1217 }
9df694ee 1218 value[CPUID_VENDOR_SZ] = '\0';
d480e1af
AF		 1219 return value;
1220}
1221
1222static void x86_cpuid_set_vendor(Object *obj, const char *value,
1223 Error **errp)
1224{
1225 X86CPU *cpu = X86_CPU(obj);
1226 CPUX86State *env = &cpu->env;
1227 int i;
1228
9df694ee 1229 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1230 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1231 "vendor", value);
1232 return;
1233 }
1234
1235 env->cpuid_vendor1 = 0;
1236 env->cpuid_vendor2 = 0;
1237 env->cpuid_vendor3 = 0;
1238 for (i = 0; i < 4; i++) {
1239 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1240 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1241 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1242 }
1243 env->cpuid_vendor_override = 1;
1244}
1245
63e886eb
AF		 1246static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1247{
1248 X86CPU *cpu = X86_CPU(obj);
1249 CPUX86State *env = &cpu->env;
1250 char *value;
1251 int i;
1252
1253 value = g_malloc(48 + 1);
1254 for (i = 0; i < 48; i++) {
1255 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1256 }
1257 value[48] = '\0';
1258 return value;
1259}
1260
938d4c25
AF		 1261static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1262 Error **errp)
dcce6675 1263{
938d4c25
AF		 1264 X86CPU *cpu = X86_CPU(obj);
1265 CPUX86State *env = &cpu->env;
dcce6675
AF		 1266 int c, len, i;
1267
1268 if (model_id == NULL) {
1269 model_id = "";
1270 }
1271 len = strlen(model_id);
d0a6acf4 1272 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1273 for (i = 0; i < 48; i++) {
1274 if (i >= len) {
1275 c = '\0';
1276 } else {
1277 c = (uint8_t)model_id[i];
1278 }
1279 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1280 }
1281}
1282
89e48965
AF		 1283static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1284 const char *name, Error **errp)
1285{
1286 X86CPU *cpu = X86_CPU(obj);
1287 int64_t value;
1288
1289 value = cpu->env.tsc_khz * 1000;
1290 visit_type_int(v, &value, name, errp);
1291}
1292
1293static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1294 const char *name, Error **errp)
1295{
1296 X86CPU *cpu = X86_CPU(obj);
1297 const int64_t min = 0;
2e84849a 1298 const int64_t max = INT64_MAX;
89e48965
AF		 1299 int64_t value;
1300
1301 visit_type_int(v, &value, name, errp);
1302 if (error_is_set(errp)) {
1303 return;
1304 }
1305 if (value < min || value > max) {
1306 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1307 name ? name : "null", value, min, max);
1308 return;
1309 }
1310
1311 cpu->env.tsc_khz = value / 1000;
1312}
1313
8f961357 1314static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
c6dc6f63 1315{
c6dc6f63
AP		 1316 x86_def_t *def;
1317
9f3fb565
EH		 1318 for (def = x86_defs; def; def = def->next) {
1319 if (name && !strcmp(name, def->name)) {
c6dc6f63 1320 break;
9f3fb565
EH		 1321 }
1322 }
04c5b17a 1323 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
6e746f30 1324 kvm_cpu_fill_host(x86_cpu_def);
c6dc6f63 1325 } else if (!def) {
8f961357 1326 return -1;
c6dc6f63
AP		 1327 } else {
1328 memcpy(x86_cpu_def, def, sizeof(*def));
1329 }
1330
8f961357
EH		 1331 return 0;
1332}
1333
1334/* Parse "+feature,-feature,feature=foo" CPU feature string
1335 */
1336static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1337{
1338 unsigned int i;
1339 char *featurestr; /* Single 'key=value" string being parsed */
1340 /* Features to be added */
077c68c3 1341 FeatureWordArray plus_features = { 0 };
8f961357 1342 /* Features to be removed */
5ef57876 1343 FeatureWordArray minus_features = { 0 };
8f961357
EH		 1344 uint32_t numvalue;
1345
8f961357 1346 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1347
1348 while (featurestr) {
1349 char *val;
1350 if (featurestr[0] == '+') {
5ef57876 1351 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1352 } else if (featurestr[0] == '-') {
5ef57876 1353 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1354 } else if ((val = strchr(featurestr, '='))) {
1355 *val = 0; val++;
1356 if (!strcmp(featurestr, "family")) {
1357 char *err;
1358 numvalue = strtoul(val, &err, 0);
a88a677f 1359 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1360 fprintf(stderr, "bad numerical value %s\n", val);
1361 goto error;
1362 }
1363 x86_cpu_def->family = numvalue;
1364 } else if (!strcmp(featurestr, "model")) {
1365 char *err;
1366 numvalue = strtoul(val, &err, 0);
1367 if (!*val || *err || numvalue > 0xff) {
1368 fprintf(stderr, "bad numerical value %s\n", val);
1369 goto error;
1370 }
1371 x86_cpu_def->model = numvalue;
1372 } else if (!strcmp(featurestr, "stepping")) {
1373 char *err;
1374 numvalue = strtoul(val, &err, 0);
1375 if (!*val || *err || numvalue > 0xf) {
1376 fprintf(stderr, "bad numerical value %s\n", val);
1377 goto error;
1378 }
1379 x86_cpu_def->stepping = numvalue ;
1380 } else if (!strcmp(featurestr, "level")) {
1381 char *err;
1382 numvalue = strtoul(val, &err, 0);
1383 if (!*val || *err) {
1384 fprintf(stderr, "bad numerical value %s\n", val);
1385 goto error;
1386 }
1387 x86_cpu_def->level = numvalue;
1388 } else if (!strcmp(featurestr, "xlevel")) {
1389 char *err;
1390 numvalue = strtoul(val, &err, 0);
1391 if (!*val || *err) {
1392 fprintf(stderr, "bad numerical value %s\n", val);
1393 goto error;
1394 }
1395 if (numvalue < 0x80000000) {
2f7a21c4 1396 numvalue += 0x80000000;
c6dc6f63
AP		 1397 }
1398 x86_cpu_def->xlevel = numvalue;
1399 } else if (!strcmp(featurestr, "vendor")) {
1400 if (strlen(val) != 12) {
1401 fprintf(stderr, "vendor string must be 12 chars long\n");
1402 goto error;
1403 }
1404 x86_cpu_def->vendor1 = 0;
1405 x86_cpu_def->vendor2 = 0;
1406 x86_cpu_def->vendor3 = 0;
1407 for(i = 0; i < 4; i++) {
1408 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1409 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1410 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1411 }
1412 x86_cpu_def->vendor_override = 1;
1413 } else if (!strcmp(featurestr, "model_id")) {
1414 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1415 val);
b862d1fe
JR		 1416 } else if (!strcmp(featurestr, "tsc_freq")) {
1417 int64_t tsc_freq;
1418 char *err;
1419
1420 tsc_freq = strtosz_suffix_unit(val, &err,
1421 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1422 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1423 fprintf(stderr, "bad numerical value %s\n", val);
1424 goto error;
1425 }
1426 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1427 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1428 char *err;
1429 numvalue = strtoul(val, &err, 0);
1430 if (!*val || *err) {
1431 fprintf(stderr, "bad numerical value %s\n", val);
1432 goto error;
1433 }
1434 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1435 } else {
1436 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1437 goto error;
1438 }
1439 } else if (!strcmp(featurestr, "check")) {
1440 check_cpuid = 1;
1441 } else if (!strcmp(featurestr, "enforce")) {
1442 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1443 } else if (!strcmp(featurestr, "hv_relaxed")) {
1444 hyperv_enable_relaxed_timing(true);
1445 } else if (!strcmp(featurestr, "hv_vapic")) {
1446 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1447 } else {
1448 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1449 goto error;
1450 }
1451 featurestr = strtok(NULL, ",");
1452 }
5ef57876
EH		 1453 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1454 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1455 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1456 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
89e49c8b 1457 x86_cpu_def->ext4_features |= plus_features[FEAT_C000_0001_EDX];
5ef57876
EH		 1458 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1459 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1460 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1461 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1462 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1463 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1464 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
89e49c8b 1465 x86_cpu_def->ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
5ef57876
EH		 1466 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1467 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1468 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63
AP		 1469 return 0;
1470
1471error:
c6dc6f63
AP		 1472 return -1;
1473}
1474
1475/* generate a composite string into buf of all cpuid names in featureset
1476 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1477 * if flags, suppress names undefined in featureset.
1478 */
1479static void listflags(char *buf, int bufsize, uint32_t fbits,
1480 const char **featureset, uint32_t flags)
1481{
1482 const char **p = &featureset[31];
1483 char *q, *b, bit;
1484 int nc;
1485
1486 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1487 *buf = '\0';
1488 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1489 if (fbits & 1 << bit && (*p || !flags)) {
1490 if (*p)
1491 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1492 else
1493 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1494 if (bufsize <= nc) {
1495 if (b) {
1496 memcpy(b, "...", sizeof("..."));
1497 }
1498 return;
1499 }
1500 q += nc;
1501 bufsize -= nc;
1502 }
1503}
1504
e916cbf8
PM		 1505/* generate CPU information. */
1506void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1507{
c6dc6f63
AP		 1508 x86_def_t *def;
1509 char buf[256];
1510
c6dc6f63 1511 for (def = x86_defs; def; def = def->next) {
c04321b3 1512 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1513 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1514 }
ed2c54d4
AP		 1515 if (kvm_enabled()) {
1516 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1517 }
6cdf8854
PM		 1518 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1519 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
4a19e505 1520 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1521 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
4a19e505 1522 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1523 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
4a19e505 1524 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1525 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
4a19e505 1526 (*cpu_fprintf)(f, " %s\n", buf);
c6dc6f63
AP		 1527}
1528
76b64a7a 1529CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1530{
1531 CpuDefinitionInfoList *cpu_list = NULL;
1532 x86_def_t *def;
1533
1534 for (def = x86_defs; def; def = def->next) {
1535 CpuDefinitionInfoList *entry;
1536 CpuDefinitionInfo *info;
1537
1538 info = g_malloc0(sizeof(*info));
1539 info->name = g_strdup(def->name);
1540
1541 entry = g_malloc0(sizeof(*entry));
1542 entry->value = info;
1543 entry->next = cpu_list;
1544 cpu_list = entry;
1545 }
1546
1547 return cpu_list;
1548}
1549
bc74b7db
EH		 1550#ifdef CONFIG_KVM
1551static void filter_features_for_kvm(X86CPU *cpu)
1552{
1553 CPUX86State *env = &cpu->env;
1554 KVMState *s = kvm_state;
1555
b8091f24
EH		 1556 env->cpuid_features &=
1557 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1558 env->cpuid_ext_features &=
1559 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1560 env->cpuid_ext2_features &=
1561 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1562 env->cpuid_ext3_features &=
1563 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1564 env->cpuid_svm_features &=
1565 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
ffa8c11f
EH		 1566 env->cpuid_7_0_ebx_features &=
1567 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
bc74b7db 1568 env->cpuid_kvm_features &=
b8091f24
EH		 1569 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1570 env->cpuid_ext4_features &=
1571 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
bc74b7db
EH		 1572
1573}
1574#endif
1575
61dcd775 1576int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1577{
61dcd775 1578 CPUX86State *env = &cpu->env;
c6dc6f63 1579 x86_def_t def1, *def = &def1;
71ad61d3 1580 Error *error = NULL;
8f961357
EH		 1581 char *name, *features;
1582 gchar **model_pieces;
c6dc6f63 1583
db0ad1ba
JR		 1584 memset(def, 0, sizeof(*def));
1585
8f961357
EH		 1586 model_pieces = g_strsplit(cpu_model, ",", 2);
1587 if (!model_pieces[0]) {
fa2db3c4
IM		 1588 error_setg(&error, "Invalid/empty CPU model name");
1589 goto out;
8f961357
EH		 1590 }
1591 name = model_pieces[0];
1592 features = model_pieces[1];
1593
1594 if (cpu_x86_find_by_name(def, name) < 0) {
fa2db3c4
IM		 1595 error_setg(&error, "Unable to find CPU definition: %s", name);
1596 goto out;
8f961357
EH		 1597 }
1598
aa87d458
EH		 1599 if (kvm_enabled()) {
1600 def->kvm_features |= kvm_default_features;
1601 }
077c68c3
IM		 1602 def->ext_features |= CPUID_EXT_HYPERVISOR;
1603
8f961357 1604 if (cpu_x86_parse_featurestr(def, features) < 0) {
fa2db3c4
IM		 1605 error_setg(&error, "Invalid cpu_model string format: %s", cpu_model);
1606 goto out;
8f961357 1607 }
ebe8b9c6
IM		 1608 assert(def->vendor1);
1609 env->cpuid_vendor1 = def->vendor1;
1610 env->cpuid_vendor2 = def->vendor2;
1611 env->cpuid_vendor3 = def->vendor3;
c6dc6f63 1612 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1613 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1614 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1615 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1616 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1617 env->cpuid_features = def->features;
c6dc6f63
AP		 1618 env->cpuid_ext_features = def->ext_features;
1619 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1620 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1621 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1622 env->cpuid_kvm_features = def->kvm_features;
296acb64 1623 env->cpuid_svm_features = def->svm_features;
b3baa152 1624 env->cpuid_ext4_features = def->ext4_features;
a9321a4d 1625 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
b3baa152 1626 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1627 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1628 "tsc-frequency", &error);
3b671a40 1629
938d4c25 1630 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
fa2db3c4
IM		 1631
1632out:
1633 g_strfreev(model_pieces);
18eb473f
IM		 1634 if (error) {
1635 fprintf(stderr, "%s\n", error_get_pretty(error));
71ad61d3 1636 error_free(error);
fa2db3c4 1637 return -1;
71ad61d3 1638 }
c6dc6f63
AP		 1639 return 0;
1640}
1641
1642#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1643
0e26b7b8
BS		 1644void cpu_clear_apic_feature(CPUX86State *env)
1645{
1646 env->cpuid_features &= ~CPUID_APIC;
1647}
1648
c6dc6f63
AP		 1649#endif /* !CONFIG_USER_ONLY */
1650
c04321b3 1651/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1652 */
1653void x86_cpudef_setup(void)
1654{
93bfef4c
CV		 1655 int i, j;
1656 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1657
1658 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291
EH		 1659 x86_def_t *def = &builtin_x86_defs[i];
1660 def->next = x86_defs;
93bfef4c
CV		 1661
1662 /* Look for specific "cpudef" models that */
09faecf2 1663 /* have the QEMU version in .model_id */
93bfef4c 1664 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1665 if (strcmp(model_with_versions[j], def->name) == 0) {
1666 pstrcpy(def->model_id, sizeof(def->model_id),
1667 "QEMU Virtual CPU version ");
1668 pstrcat(def->model_id, sizeof(def->model_id),
1669 qemu_get_version());
93bfef4c
CV		 1670 break;
1671 }
1672 }
1673
bc3e1291 1674 x86_defs = def;
c6dc6f63 1675 }
c6dc6f63
AP		 1676}
1677
c6dc6f63
AP		 1678static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1679 uint32_t *ecx, uint32_t *edx)
1680{
1681 *ebx = env->cpuid_vendor1;
1682 *edx = env->cpuid_vendor2;
1683 *ecx = env->cpuid_vendor3;
1684
1685 /* sysenter isn't supported on compatibility mode on AMD, syscall
1686 * isn't supported in compatibility mode on Intel.
1687 * Normally we advertise the actual cpu vendor, but you can override
1688 * this if you want to use KVM's sysenter/syscall emulation
1689 * in compatibility mode and when doing cross vendor migration
1690 */
89354998 1691 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1692 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1693 }
1694}
1695
1696void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1697 uint32_t *eax, uint32_t *ebx,
1698 uint32_t *ecx, uint32_t *edx)
1699{
a60f24b5
AF		 1700 X86CPU *cpu = x86_env_get_cpu(env);
1701 CPUState *cs = CPU(cpu);
1702
c6dc6f63
AP		 1703 /* test if maximum index reached */
1704 if (index & 0x80000000) {
b3baa152 1705 if (index > env->cpuid_xlevel) {
1706 if (env->cpuid_xlevel2 > 0) {
1707 /* Handle the Centaur's CPUID instruction. */
1708 if (index > env->cpuid_xlevel2) {
1709 index = env->cpuid_xlevel2;
1710 } else if (index < 0xC0000000) {
1711 index = env->cpuid_xlevel;
1712 }
1713 } else {
57f26ae7
EH		 1714 /* Intel documentation states that invalid EAX input will
1715 * return the same information as EAX=cpuid_level
1716 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1717 */
1718 index = env->cpuid_level;
b3baa152 1719 }
1720 }
c6dc6f63
AP		 1721 } else {
1722 if (index > env->cpuid_level)
1723 index = env->cpuid_level;
1724 }
1725
1726 switch(index) {
1727 case 0:
1728 *eax = env->cpuid_level;
1729 get_cpuid_vendor(env, ebx, ecx, edx);
1730 break;
1731 case 1:
1732 *eax = env->cpuid_version;
1733 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1734 *ecx = env->cpuid_ext_features;
1735 *edx = env->cpuid_features;
ce3960eb
AF		 1736 if (cs->nr_cores * cs->nr_threads > 1) {
1737 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 1738 *edx |= 1 << 28; /* HTT bit */
1739 }
1740 break;
1741 case 2:
1742 /* cache info: needed for Pentium Pro compatibility */
1743 *eax = 1;
1744 *ebx = 0;
1745 *ecx = 0;
1746 *edx = 0x2c307d;
1747 break;
1748 case 4:
1749 /* cache info: needed for Core compatibility */
ce3960eb
AF		 1750 if (cs->nr_cores > 1) {
1751 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 1752 } else {
2f7a21c4 1753 *eax = 0;
c6dc6f63
AP		 1754 }
1755 switch (count) {
1756 case 0: /* L1 dcache info */
1757 *eax |= 0x0000121;
1758 *ebx = 0x1c0003f;
1759 *ecx = 0x000003f;
1760 *edx = 0x0000001;
1761 break;
1762 case 1: /* L1 icache info */
1763 *eax |= 0x0000122;
1764 *ebx = 0x1c0003f;
1765 *ecx = 0x000003f;
1766 *edx = 0x0000001;
1767 break;
1768 case 2: /* L2 cache info */
1769 *eax |= 0x0000143;
ce3960eb
AF		 1770 if (cs->nr_threads > 1) {
1771 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63
AP		 1772 }
1773 *ebx = 0x3c0003f;
1774 *ecx = 0x0000fff;
1775 *edx = 0x0000001;
1776 break;
1777 default: /* end of info */
1778 *eax = 0;
1779 *ebx = 0;
1780 *ecx = 0;
1781 *edx = 0;
1782 break;
1783 }
1784 break;
1785 case 5:
1786 /* mwait info: needed for Core compatibility */
1787 *eax = 0; /* Smallest monitor-line size in bytes */
1788 *ebx = 0; /* Largest monitor-line size in bytes */
1789 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1790 *edx = 0;
1791 break;
1792 case 6:
1793 /* Thermal and Power Leaf */
1794 *eax = 0;
1795 *ebx = 0;
1796 *ecx = 0;
1797 *edx = 0;
1798 break;
f7911686 1799 case 7:
13526728
EH		 1800 /* Structured Extended Feature Flags Enumeration Leaf */
1801 if (count == 0) {
1802 *eax = 0; /* Maximum ECX value for sub-leaves */
a9321a4d 1803 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
13526728
EH		 1804 *ecx = 0; /* Reserved */
1805 *edx = 0; /* Reserved */
f7911686
YW		 1806 } else {
1807 *eax = 0;
1808 *ebx = 0;
1809 *ecx = 0;
1810 *edx = 0;
1811 }
1812 break;
c6dc6f63
AP		 1813 case 9:
1814 /* Direct Cache Access Information Leaf */
1815 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1816 *ebx = 0;
1817 *ecx = 0;
1818 *edx = 0;
1819 break;
1820 case 0xA:
1821 /* Architectural Performance Monitoring Leaf */
a0fa8208 1822 if (kvm_enabled()) {
a60f24b5 1823 KVMState *s = cs->kvm_state;
a0fa8208
GN		 1824
1825 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1826 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1827 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1828 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1829 } else {
1830 *eax = 0;
1831 *ebx = 0;
1832 *ecx = 0;
1833 *edx = 0;
1834 }
c6dc6f63 1835 break;
51e49430
SY		 1836 case 0xD:
1837 /* Processor Extended State */
1838 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1839 *eax = 0;
1840 *ebx = 0;
1841 *ecx = 0;
1842 *edx = 0;
1843 break;
1844 }
1845 if (kvm_enabled()) {
a60f24b5 1846 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 1847
1848 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1849 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1850 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1851 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1852 } else {
1853 *eax = 0;
1854 *ebx = 0;
1855 *ecx = 0;
1856 *edx = 0;
1857 }
1858 break;
c6dc6f63
AP		 1859 case 0x80000000:
1860 *eax = env->cpuid_xlevel;
1861 *ebx = env->cpuid_vendor1;
1862 *edx = env->cpuid_vendor2;
1863 *ecx = env->cpuid_vendor3;
1864 break;
1865 case 0x80000001:
1866 *eax = env->cpuid_version;
1867 *ebx = 0;
1868 *ecx = env->cpuid_ext3_features;
1869 *edx = env->cpuid_ext2_features;
1870
1871 /* The Linux kernel checks for the CMPLegacy bit and
1872 * discards multiple thread information if it is set.
1873 * So dont set it here for Intel to make Linux guests happy.
1874 */
ce3960eb 1875 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 1876 uint32_t tebx, tecx, tedx;
1877 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1878 if (tebx != CPUID_VENDOR_INTEL_1 ||
1879 tedx != CPUID_VENDOR_INTEL_2 ||
1880 tecx != CPUID_VENDOR_INTEL_3) {
1881 *ecx |= 1 << 1; /* CmpLegacy bit */
1882 }
1883 }
c6dc6f63
AP		 1884 break;
1885 case 0x80000002:
1886 case 0x80000003:
1887 case 0x80000004:
1888 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1889 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1890 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1891 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1892 break;
1893 case 0x80000005:
1894 /* cache info (L1 cache) */
1895 *eax = 0x01ff01ff;
1896 *ebx = 0x01ff01ff;
1897 *ecx = 0x40020140;
1898 *edx = 0x40020140;
1899 break;
1900 case 0x80000006:
1901 /* cache info (L2 cache) */
1902 *eax = 0;
1903 *ebx = 0x42004200;
1904 *ecx = 0x02008140;
1905 *edx = 0;
1906 break;
1907 case 0x80000008:
1908 /* virtual & phys address size in low 2 bytes. */
1909/* XXX: This value must match the one used in the MMU code. */
1910 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1911 /* 64 bit processor */
1912/* XXX: The physical address space is limited to 42 bits in exec.c. */
1913 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1914 } else {
1915 if (env->cpuid_features & CPUID_PSE36)
1916 *eax = 0x00000024; /* 36 bits physical */
1917 else
1918 *eax = 0x00000020; /* 32 bits physical */
1919 }
1920 *ebx = 0;
1921 *ecx = 0;
1922 *edx = 0;
ce3960eb
AF		 1923 if (cs->nr_cores * cs->nr_threads > 1) {
1924 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 1925 }
1926 break;
1927 case 0x8000000A:
9f3fb565
EH		 1928 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1929 *eax = 0x00000001; /* SVM Revision */
1930 *ebx = 0x00000010; /* nr of ASIDs */
1931 *ecx = 0;
1932 *edx = env->cpuid_svm_features; /* optional features */
1933 } else {
1934 *eax = 0;
1935 *ebx = 0;
1936 *ecx = 0;
1937 *edx = 0;
1938 }
c6dc6f63 1939 break;
b3baa152 1940 case 0xC0000000:
1941 *eax = env->cpuid_xlevel2;
1942 *ebx = 0;
1943 *ecx = 0;
1944 *edx = 0;
1945 break;
1946 case 0xC0000001:
1947 /* Support for VIA CPU's CPUID instruction */
1948 *eax = env->cpuid_version;
1949 *ebx = 0;
1950 *ecx = 0;
1951 *edx = env->cpuid_ext4_features;
1952 break;
1953 case 0xC0000002:
1954 case 0xC0000003:
1955 case 0xC0000004:
1956 /* Reserved for the future, and now filled with zero */
1957 *eax = 0;
1958 *ebx = 0;
1959 *ecx = 0;
1960 *edx = 0;
1961 break;
c6dc6f63
AP		 1962 default:
1963 /* reserved values: zero */
1964 *eax = 0;
1965 *ebx = 0;
1966 *ecx = 0;
1967 *edx = 0;
1968 break;
1969 }
1970}
5fd2087a
AF		 1971
1972/* CPUClass::reset() */
1973static void x86_cpu_reset(CPUState *s)
1974{
1975 X86CPU *cpu = X86_CPU(s);
1976 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1977 CPUX86State *env = &cpu->env;
c1958aea
AF		 1978 int i;
1979
1980 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 1981 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
6fd2a026 1982 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
c1958aea 1983 }
5fd2087a
AF		 1984
1985 xcc->parent_reset(s);
1986
c1958aea
AF		 1987
1988 memset(env, 0, offsetof(CPUX86State, breakpoints));
1989
1990 tlb_flush(env, 1);
1991
1992 env->old_exception = -1;
1993
1994 /* init to reset state */
1995
1996#ifdef CONFIG_SOFTMMU
1997 env->hflags |= HF_SOFTMMU_MASK;
1998#endif
1999 env->hflags2 |= HF2_GIF_MASK;
2000
2001 cpu_x86_update_cr0(env, 0x60000010);
2002 env->a20_mask = ~0x0;
2003 env->smbase = 0x30000;
2004
2005 env->idt.limit = 0xffff;
2006 env->gdt.limit = 0xffff;
2007 env->ldt.limit = 0xffff;
2008 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2009 env->tr.limit = 0xffff;
2010 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2011
2012 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2013 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2014 DESC_R_MASK | DESC_A_MASK);
2015 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2016 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2017 DESC_A_MASK);
2018 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2019 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2020 DESC_A_MASK);
2021 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2022 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2023 DESC_A_MASK);
2024 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2025 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2026 DESC_A_MASK);
2027 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2028 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2029 DESC_A_MASK);
2030
2031 env->eip = 0xfff0;
2032 env->regs[R_EDX] = env->cpuid_version;
2033
2034 env->eflags = 0x2;
2035
2036 /* FPU init */
2037 for (i = 0; i < 8; i++) {
2038 env->fptags[i] = 1;
2039 }
2040 env->fpuc = 0x37f;
2041
2042 env->mxcsr = 0x1f80;
2043
2044 env->pat = 0x0007040600070406ULL;
2045 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2046
2047 memset(env->dr, 0, sizeof(env->dr));
2048 env->dr[6] = DR6_FIXED_1;
2049 env->dr[7] = DR7_FIXED_1;
2050 cpu_breakpoint_remove_all(env, BP_CPU);
2051 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 2052
2053#if !defined(CONFIG_USER_ONLY)
2054 /* We hard-wire the BSP to the first CPU. */
55e5c285 2055 if (s->cpu_index == 0) {
dd673288
IM		 2056 apic_designate_bsp(env->apic_state);
2057 }
2058
2059 env->halted = !cpu_is_bsp(cpu);
2060#endif
5fd2087a
AF		 2061}
2062
dd673288
IM		 2063#ifndef CONFIG_USER_ONLY
2064bool cpu_is_bsp(X86CPU *cpu)
2065{
2066 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2067}
65dee380
IM		 2068
2069/* TODO: remove me, when reset over QOM tree is implemented */
2070static void x86_cpu_machine_reset_cb(void *opaque)
2071{
2072 X86CPU *cpu = opaque;
2073 cpu_reset(CPU(cpu));
2074}
dd673288
IM		 2075#endif
2076
de024815
AF		 2077static void mce_init(X86CPU *cpu)
2078{
2079 CPUX86State *cenv = &cpu->env;
2080 unsigned int bank;
2081
2082 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2083 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2084 (CPUID_MCE | CPUID_MCA)) {
2085 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2086 cenv->mcg_ctl = ~(uint64_t)0;
2087 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2088 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2089 }
2090 }
2091}
2092
bdeec802
IM		 2093#define MSI_ADDR_BASE 0xfee00000
2094
2095#ifndef CONFIG_USER_ONLY
2096static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2097{
2098 static int apic_mapped;
2099 CPUX86State *env = &cpu->env;
449994eb 2100 APICCommonState *apic;
bdeec802
IM		 2101 const char *apic_type = "apic";
2102
2103 if (kvm_irqchip_in_kernel()) {
2104 apic_type = "kvm-apic";
2105 } else if (xen_enabled()) {
2106 apic_type = "xen-apic";
2107 }
2108
2109 env->apic_state = qdev_try_create(NULL, apic_type);
2110 if (env->apic_state == NULL) {
2111 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2112 return;
2113 }
2114
2115 object_property_add_child(OBJECT(cpu), "apic",
2116 OBJECT(env->apic_state), NULL);
2117 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2118 /* TODO: convert to link<> */
449994eb 2119 apic = APIC_COMMON(env->apic_state);
60671e58 2120 apic->cpu = cpu;
bdeec802
IM		 2121
2122 if (qdev_init(env->apic_state)) {
2123 error_setg(errp, "APIC device '%s' could not be initialized",
2124 object_get_typename(OBJECT(env->apic_state)));
2125 return;
2126 }
2127
2128 /* XXX: mapping more APICs at the same memory location */
2129 if (apic_mapped == 0) {
2130 /* NOTE: the APIC is directly connected to the CPU - it is not
2131 on the global memory bus. */
2132 /* XXX: what if the base changes? */
1356b98d 2133 sysbus_mmio_map(SYS_BUS_DEVICE(env->apic_state), 0, MSI_ADDR_BASE);
bdeec802
IM		 2134 apic_mapped = 1;
2135 }
2136}
2137#endif
2138
7a059953
AF		 2139void x86_cpu_realize(Object *obj, Error **errp)
2140{
2141 X86CPU *cpu = X86_CPU(obj);
b34d12d1
IM		 2142 CPUX86State *env = &cpu->env;
2143
2144 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2145 env->cpuid_level = 7;
2146 }
7a059953 2147
9b15cd9e
IM		 2148 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2149 * CPUID[1].EDX.
2150 */
2151 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2152 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2153 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2154 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2155 env->cpuid_ext2_features |= (env->cpuid_features
2156 & CPUID_EXT2_AMD_ALIASES);
2157 }
2158
4586f157
IM		 2159 if (!kvm_enabled()) {
2160 env->cpuid_features &= TCG_FEATURES;
2161 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2162 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2163#ifdef TARGET_X86_64
2164 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2165#endif
2166 );
2167 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2168 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2169 } else {
2170#ifdef CONFIG_KVM
2171 filter_features_for_kvm(cpu);
2172#endif
5ec01c2e
IM		 2173 if (check_cpuid && kvm_check_features_against_host(cpu)
2174 && enforce_cpuid) {
2175 error_setg(errp, "Host's CPU doesn't support requested features");
2176 return;
2177 }
4586f157
IM		 2178 }
2179
65dee380
IM		 2180#ifndef CONFIG_USER_ONLY
2181 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802
IM		 2182
2183 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2184 x86_cpu_apic_init(cpu, errp);
2185 if (error_is_set(errp)) {
2186 return;
2187 }
2188 }
65dee380
IM		 2189#endif
2190
7a059953
AF		 2191 mce_init(cpu);
2192 qemu_init_vcpu(&cpu->env);
65dee380 2193 cpu_reset(CPU(cpu));
7a059953
AF		 2194}
2195
de024815
AF		 2196static void x86_cpu_initfn(Object *obj)
2197{
55e5c285 2198 CPUState *cs = CPU(obj);
de024815
AF		 2199 X86CPU *cpu = X86_CPU(obj);
2200 CPUX86State *env = &cpu->env;
d65e9815 2201 static int inited;
de024815
AF		 2202
2203 cpu_exec_init(env);
71ad61d3
AF		 2204
2205 object_property_add(obj, "family", "int",
95b8519d 2206 x86_cpuid_version_get_family,
71ad61d3 2207 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2208 object_property_add(obj, "model", "int",
67e30c83 2209 x86_cpuid_version_get_model,
c5291a4f 2210 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2211 object_property_add(obj, "stepping", "int",
35112e41 2212 x86_cpuid_version_get_stepping,
036e2222 2213 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2214 object_property_add(obj, "level", "int",
2215 x86_cpuid_get_level,
2216 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2217 object_property_add(obj, "xlevel", "int",
2218 x86_cpuid_get_xlevel,
2219 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2220 object_property_add_str(obj, "vendor",
2221 x86_cpuid_get_vendor,
2222 x86_cpuid_set_vendor, NULL);
938d4c25 2223 object_property_add_str(obj, "model-id",
63e886eb 2224 x86_cpuid_get_model_id,
938d4c25 2225 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2226 object_property_add(obj, "tsc-frequency", "int",
2227 x86_cpuid_get_tsc_freq,
2228 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 2229
55e5c285 2230 env->cpuid_apic_id = cs->cpu_index;
d65e9815
IM		 2231
2232 /* init various static tables used in TCG mode */
2233 if (tcg_enabled() && !inited) {
2234 inited = 1;
2235 optimize_flags_init();
2236#ifndef CONFIG_USER_ONLY
2237 cpu_set_debug_excp_handler(breakpoint_handler);
2238#endif
2239 }
de024815
AF		 2240}
2241
5fd2087a
AF		 2242static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2243{
2244 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2245 CPUClass *cc = CPU_CLASS(oc);
2246
2247 xcc->parent_reset = cc->reset;
2248 cc->reset = x86_cpu_reset;
2249}
2250
2251static const TypeInfo x86_cpu_type_info = {
2252 .name = TYPE_X86_CPU,
2253 .parent = TYPE_CPU,
2254 .instance_size = sizeof(X86CPU),
de024815 2255 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2256 .abstract = false,
2257 .class_size = sizeof(X86CPUClass),
2258 .class_init = x86_cpu_common_class_init,
2259};
2260
2261static void x86_cpu_register_types(void)
2262{
2263 type_register_static(&x86_cpu_type_info);
2264}
2265
2266type_init(x86_cpu_register_types)
Qemu copy for testing