- // send nop\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_NOP);\r
- // pre-charge all\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
-\r
- // delay\r
- for (i = 0; i < 10; i++) {\r
- val32 = DmcReadReg(DMC_STATUS_REG);\r
- }\r
-\r
- // set (EMR2) extended mode register 2\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, \r
- DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
- DMC_DIRECT_CMD_BANKADDR(2) | \r
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
- // set (EMR3) extended mode register 3\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, \r
- DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
- DMC_DIRECT_CMD_BANKADDR(3) | \r
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
-\r
- // =================================\r
- // set (EMR) Extended Mode Register\r
- // ==================================\r
- // Put into OCD default state\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, \r
- DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
- DMC_DIRECT_CMD_BANKADDR(1) | \r
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
-\r
- // =========================================================== \r
- // set (MR) mode register - With DLL reset\r
- // ===========================================================\r
- // Burst Length = 4 (010)\r
- // Burst Type = Seq (0)\r
- // Latency = 4 (100)\r
- // Test mode = Off (0)\r
- // DLL reset = Yes (1)\r
- // Wr Recovery = 4 (011) \r
- // PD = Normal (0)\r
+\s\s// send nop\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_NOP);\r
+\s\s// pre-charge all\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
+\r
+\s\s// delay\r
+\s\sfor (i = 0; i < 10; i++) {\r
+\s\s val32 = DmcReadReg(DMC_STATUS_REG);\r
+\s\s}\r
+\r
+\s\s// set (EMR2) extended mode register 2\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, \r
+\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
+\s\s\s\s DMC_DIRECT_CMD_BANKADDR(2) | \r
+\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\s\s// set (EMR3) extended mode register 3\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, \r
+\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
+\s\s\s\s DMC_DIRECT_CMD_BANKADDR(3) | \r
+\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+\s\s// =================================\r
+\s\s// set (EMR) Extended Mode Register\r
+\s\s// ==================================\r
+\s\s// Put into OCD default state\r
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, \r
+\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) | \r
+\s\s\s\s DMC_DIRECT_CMD_BANKADDR(1) | \r
+\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+\s\s// =========================================================== \r
+\s\s// set (MR) mode register - With DLL reset\r
+\s\s// ===========================================================\r
+\s\s// Burst Length = 4 (010)\r
+\s\s// Burst Type = Seq (0)\r
+\s\s// Latency = 4 (100)\r
+\s\s// Test mode = Off (0)\r
+\s\s// DLL reset = Yes (1)\r
+\s\s// Wr Recovery = 4 (011) \r
+\s\s// PD = Normal (0)\r