\r
--*/\r
\r
-#ifndef __ARM_GIC_DXE_H__\r
-#define __ARM_GIC_DXE_H__\r
+#ifndef ARM_GIC_DXE_H_\r
+#define ARM_GIC_DXE_H_\r
\r
#include <Library/ArmGicLib.h>\r
#include <Library/ArmLib.h>\r
OUT UINTN *Config1Bit\r
);\r
\r
-#endif\r
+#endif // ARM_GIC_DXE_H_\r
\r
**/\r
\r
-#ifndef __CPU_DXE_ARM_EXCEPTION_H__\r
-#define __CPU_DXE_ARM_EXCEPTION_H__\r
+#ifndef CPU_DXE_H_\r
+#define CPU_DXE_H_\r
\r
#include <Uefi.h>\r
\r
IN UINT64 Attributes\r
);\r
\r
-#endif // __CPU_DXE_ARM_EXCEPTION_H__\r
+#endif // CPU_DXE_H_\r
* SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
-#ifndef __GENERIC_WATCHDOG_H__\r
-#define __GENERIC_WATCHDOG_H__\r
+#ifndef GENERIC_WATCHDOG_H_\r
+#define GENERIC_WATCHDOG_H_\r
\r
// Refresh Frame:\r
#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)\r
#define GENERIC_WDOG_ENABLED 1\r
#define GENERIC_WDOG_DISABLED 0\r
\r
-#endif // __GENERIC_WATCHDOG_H__\r
+#endif // GENERIC_WATCHDOG_H_\r
\r
**/\r
\r
-#ifndef __SEMIHOST_FS_H__\r
-#define __SEMIHOST_FS_H__\r
+#ifndef SEMIHOST_FS_H_\r
+#define SEMIHOST_FS_H_\r
\r
EFI_STATUS\r
VolumeOpen (\r
IN EFI_FILE *File\r
);\r
\r
-#endif // __SEMIHOST_FS_H__\r
+#endif // SEMIHOST_FS_H_\r
\r
**/\r
\r
\r
-#ifndef __MACRO_IO_LIB_H__\r
-#define __MACRO_IO_LIB_H__\r
+#ifndef ASM_MACRO_IO_LIB_H_\r
+#define ASM_MACRO_IO_LIB_H_\r
\r
#define _ASM_FUNC(Name, Section) \\r
.global Name ; \\r
movt Reg, #:upper16:(Sym) - (. + 12) ; \\r
ldr Reg, [pc, Reg]\r
\r
-#endif\r
+#endif // ASM_MACRO_IO_LIB_H_\r
**/\r
\r
\r
-#ifndef __MACRO_IO_LIBV8_H__\r
-#define __MACRO_IO_LIBV8_H__\r
+#ifndef ASM_MACRO_IO_LIBV8_H_\r
+#define ASM_MACRO_IO_LIBV8_H_\r
\r
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1\r
// This only selects between EL1 and EL2, else we die.\r
movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \\r
movk Reg, (Val) & 0xffff\r
\r
-#endif // __MACRO_IO_LIBV8_H__\r
+#endif // ASM_MACRO_IO_LIBV8_H_\r
\r
**/\r
\r
-#ifndef __AARCH64_H__\r
-#define __AARCH64_H__\r
+#ifndef AARCH64_H_\r
+#define AARCH64_H_\r
\r
#include <Chipset/AArch64Mmu.h>\r
\r
IN UINT32 CntHctl\r
);\r
\r
-#endif // __AARCH64_H__\r
+#endif // AARCH64_H_\r
*\r
**/\r
\r
-#ifndef __AARCH64_MMU_H_\r
-#define __AARCH64_MMU_H_\r
+#ifndef AARCH64_MMU_H_\r
+#define AARCH64_MMU_H_\r
\r
//\r
// Memory Attribute Indirection register Definitions\r
\r
// Uses LPAE Page Table format\r
\r
-#endif // __AARCH64_MMU_H_\r
+#endif // AARCH64_MMU_H_\r
\r
\r
**/\r
\r
-#ifndef __ARM_CORTEX_A9_H__\r
-#define __ARM_CORTEX_A9_H__\r
+#ifndef ARM_CORTEX_A9_H_\r
+#define ARM_CORTEX_A9_H_\r
\r
#include <Chipset/ArmV7.h>\r
\r
VOID\r
);\r
\r
-#endif\r
+#endif // ARM_CORTEX_A9_H_\r
\r
\r
**/\r
\r
-#ifndef __ARM_V7_H__\r
-#define __ARM_V7_H__\r
+#ifndef ARM_V7_H_\r
+#define ARM_V7_H_\r
\r
#include <Chipset/ArmV7Mmu.h>\r
\r
IN UINT32 Nsacr\r
);\r
\r
-#endif // __ARM_V7_H__\r
+#endif // ARM_V7_H_\r
*\r
**/\r
\r
-#ifndef __ARMV7_MMU_H_\r
-#define __ARMV7_MMU_H_\r
+#ifndef ARMV7_MMU_H_\r
+#define ARMV7_MMU_H_\r
\r
#define TTBR_NOT_OUTER_SHAREABLE BIT5\r
#define TTBR_RGN_OUTER_NON_CACHEABLE 0\r
IN BOOLEAN IsLargePage\r
);\r
\r
-#endif\r
+#endif // ARMV7_MMU_H_\r
*\r
**/\r
\r
-#ifndef __ARM_MP_CORE_INFO_GUID_H_\r
-#define __ARM_MP_CORE_INFO_GUID_H_\r
+#ifndef ARM_MP_CORE_INFO_GUID_H_\r
+#define ARM_MP_CORE_INFO_GUID_H_\r
\r
#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04\r
#define SCU_CONFIG_REG_OFFSET 0x04\r
\r
extern EFI_GUID gArmMpCoreInfoGuid;\r
\r
-#endif /* MPCOREINFO_H_ */\r
+#endif /* ARM_MP_CORE_INFO_GUID_H_ */\r
*\r
**/\r
\r
-#ifndef __ARM_MM_SVC_H__\r
-#define __ARM_MM_SVC_H__\r
+#ifndef ARM_MM_SVC_H_\r
+#define ARM_MM_SVC_H_\r
\r
/*\r
* SVC IDs to allow the MM secure partition to initialise itself, handle\r
#define SPM_MAJOR_VERSION 0\r
#define SPM_MINOR_VERSION 1\r
\r
-#endif\r
+#endif // ARM_MM_SVC_H_\r
* (https://developer.arm.com/documentation/den0028/c/?lang=en)\r
**/\r
\r
-#ifndef __ARM_STD_SMC_H__\r
-#define __ARM_STD_SMC_H__\r
+#ifndef ARM_STD_SMC_H_\r
+#define ARM_STD_SMC_H_\r
\r
/*\r
* SMC function IDs for Standard Service queries\r
/* 0xbf00ff02 is reserved */\r
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03\r
\r
-#endif\r
+#endif // ARM_STD_SMC_H_\r
\r
**/\r
\r
-#ifndef __ARM_DISASSEBLER_LIB_H__\r
-#define __ARM_DISASSEBLER_LIB_H__\r
+#ifndef ARM_DISASSEMBLER_LIB_H_\r
+#define ARM_DISASSEMBLER_LIB_H_\r
\r
/**\r
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to\r
OUT UINTN Size\r
);\r
\r
-#endif\r
+#endif // ARM_DISASSEMBLER_LIB_H_\r
\r
**/\r
\r
-#ifndef __ARM_GENERIC_TIMER_COUNTER_LIB_H__\r
-#define __ARM_GENERIC_TIMER_COUNTER_LIB_H__\r
+#ifndef ARM_GENERIC_TIMER_COUNTER_LIB_H_\r
+#define ARM_GENERIC_TIMER_COUNTER_LIB_H_\r
\r
VOID\r
EFIAPI\r
IN UINT64 Value\r
);\r
\r
-#endif\r
+#endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_\r
*\r
**/\r
\r
-#ifndef __ARM_GIC_ARCH_LIB_H__\r
-#define __ARM_GIC_ARCH_LIB_H__\r
+#ifndef ARM_GIC_ARCH_LIB_H_\r
+#define ARM_GIC_ARCH_LIB_H_\r
\r
//\r
// GIC definitions\r
VOID\r
);\r
\r
-#endif\r
+#endif // ARM_GIC_ARCH_LIB_H_\r
*\r
**/\r
\r
-#ifndef __ARM_HVC_LIB__\r
-#define __ARM_HVC_LIB__\r
+#ifndef ARM_HVC_LIB_H_\r
+#define ARM_HVC_LIB_H_\r
\r
/**\r
* The size of the HVC arguments are different between AArch64 and AArch32.\r
IN OUT ARM_HVC_ARGS *Args\r
);\r
\r
-#endif\r
+#endif // ARM_HVC_LIB_H_\r
\r
**/\r
\r
-#ifndef __ARM_LIB__\r
-#define __ARM_LIB__\r
+#ifndef ARM_LIB_H_\r
+#define ARM_LIB_H_\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
);\r
#endif // MDE_CPU_ARM\r
\r
-#endif // __ARM_LIB__\r
+#endif // ARM_LIB_H_\r
\r
**/\r
\r
-#ifndef __ARM_MMU_LIB__\r
-#define __ARM_MMU_LIB__\r
+#ifndef ARM_MMU_LIB_H_\r
+#define ARM_MMU_LIB_H_\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
IN UINT64 Attributes\r
);\r
\r
-#endif\r
+#endif // ARM_MMU_LIB_H_\r
*\r
**/\r
\r
-#ifndef __ARM_SMC_LIB__\r
-#define __ARM_SMC_LIB__\r
+#ifndef ARM_SMC_LIB_H_\r
+#define ARM_SMC_LIB_H_\r
\r
/**\r
* The size of the SMC arguments are different between AArch64 and AArch32.\r
IN OUT ARM_SMC_ARGS *Args\r
);\r
\r
-#endif\r
+#endif // ARM_SMC_LIB_H_\r
*\r
**/\r
\r
-#ifndef __ARM_SVC_LIB__\r
-#define __ARM_SVC_LIB__\r
+#ifndef ARM_SVC_LIB_H_\r
+#define ARM_SVC_LIB_H_\r
\r
/**\r
* The size of the SVC arguments are different between AArch64 and AArch32.\r
IN OUT ARM_SVC_ARGS *Args\r
);\r
\r
-#endif\r
+#endif // ARM_SVC_LIB_H_\r
\r
**/\r
\r
-#ifndef __DEFAULT_EXCEPTION_HANDLER_LIB_H__\r
-#define __DEFAULT_EXCEPTION_HANDLER_LIB_H__\r
+#ifndef DEFAULT_EXCEPTION_HANDLER_LIB_H_\r
+#define DEFAULT_EXCEPTION_HANDLER_LIB_H_\r
\r
/**\r
This is the default action to take on an unexpected exception\r
IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
);\r
\r
-#endif\r
+#endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_\r
\r
**/\r
\r
-#ifndef _OPTEE_H_\r
-#define _OPTEE_H_\r
+#ifndef OPTEE_LIB_H_\r
+#define OPTEE_LIB_H_\r
\r
/*\r
* The 'Trusted OS Call UID' is supposed to return the following UUID for\r
IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg\r
);\r
\r
-#endif\r
+#endif // OPTEE_LIB_H_\r
\r
**/\r
\r
-#ifndef __SEMIHOSTING_H__\r
-#define __SEMIHOSTING_H__\r
+#ifndef SEMIHOSTING_LIB_H_\r
+#define SEMIHOSTING_LIB_H_\r
\r
/*\r
*\r
IN CHAR8 *CommandLine\r
);\r
\r
-#endif // __SEMIHOSTING_H__\r
+#endif // SEMIHOSTING_LIB_H_\r
\r
**/\r
\r
-#ifndef __STANDALONEMM_MMU_LIB__\r
-#define __STANDALONEMM_MMU_LIB__\r
+#ifndef STANDALONE_MM_MMU_LIB_\r
+#define STANDALONE_MM_MMU_LIB_\r
\r
EFI_STATUS\r
ArmSetMemoryRegionNoExec (\r
IN UINT64 Length\r
);\r
\r
-#endif /* __STANDALONEMM_MMU_LIB__ */\r
+#endif /* STANDALONE_MM_MMU_LIB_ */\r
*\r
**/\r
\r
-#ifndef __ARM_MP_CORE_INFO_PPI_H__\r
-#define __ARM_MP_CORE_INFO_PPI_H__\r
+#ifndef ARM_MP_CORE_INFO_PPI_H_\r
+#define ARM_MP_CORE_INFO_PPI_H_\r
\r
#include <Guid/ArmMpCoreInfo.h>\r
\r
extern EFI_GUID gArmMpCoreInfoPpiGuid;\r
extern EFI_GUID gArmMpCoreInfoGuid;\r
\r
-#endif\r
+#endif // ARM_MP_CORE_INFO_PPI_H_\r
\r
**/\r
\r
-#ifndef __AARCH64_LIB_H__\r
-#define __AARCH64_LIB_H__\r
+#ifndef AARCH64_LIB_H_\r
+#define AARCH64_LIB_H_\r
\r
typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);\r
\r
VOID\r
);\r
\r
-#endif // __AARCH64_LIB_H__\r
+#endif // AARCH64_LIB_H_\r
\r
\r
**/\r
\r
-#ifndef __ARM_V7_LIB_H__\r
-#define __ARM_V7_LIB_H__\r
+#ifndef ARM_V7_LIB_H_\r
+#define ARM_V7_LIB_H_\r
\r
#define ID_MMFR0_SHARELVL_SHIFT 12\r
#define ID_MMFR0_SHARELVL_MASK 0xf\r
VOID\r
);\r
\r
-#endif // __ARM_V7_LIB_H__\r
+#endif // ARM_V7_LIB_H_\r
\r
\r
**/\r
\r
-#ifndef __ARM_LIB_PRIVATE_H__\r
-#define __ARM_LIB_PRIVATE_H__\r
+#ifndef ARM_LIB_PRIVATE_H_\r
+#define ARM_LIB_PRIVATE_H_\r
\r
#define CACHE_SIZE_4_KB (3UL)\r
#define CACHE_SIZE_8_KB (4UL)\r
VOID\r
);\r
\r
-#endif // __ARM_LIB_PRIVATE_H__\r
+#endif // ARM_LIB_PRIVATE_H_\r
\r
**/\r
\r
-#ifndef _OPTEE_SMC_H_\r
-#define _OPTEE_SMC_H_\r
+#ifndef OPTEE_SMC_H_\r
+#define OPTEE_SMC_H_\r
\r
/* Returned in Arg0 only from Trusted OS functions */\r
#define OPTEE_SMC_RETURN_OK 0x0\r
UINT8 Data4[8];\r
} RFC4122_UUID;\r
\r
-#endif\r
+#endif // OPTEE_SMC_H_\r
\r
**/\r
\r
-#ifndef _PLATFORM_BM_H_\r
-#define _PLATFORM_BM_H_\r
+#ifndef PLATFORM_BM_H_\r
+#define PLATFORM_BM_H_\r
\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
VOID\r
);\r
\r
-#endif // _PLATFORM_BM_H_\r
+#endif // PLATFORM_BM_H_\r
\r
**/\r
\r
-#ifndef __SEMIHOST_PRIVATE_H__\r
-#define __SEMIHOST_PRIVATE_H__\r
+#ifndef SEMIHOST_PRIVATE_H_\r
+#define SEMIHOST_PRIVATE_H_\r
\r
typedef struct {\r
CHAR8 *FileName;\r
\r
#endif // __CC_ARM\r
\r
-#endif //__SEMIHOST_PRIVATE_H__\r
+#endif // SEMIHOST_PRIVATE_H_\r