SmmS3ResumeState->SmmS3StackSize = 0;\r
}\r
\r
- SmmS3ResumeState->SmmS3Cr0 = gSmmCr0;\r
+ SmmS3ResumeState->SmmS3Cr0 = mSmmCr0;\r
SmmS3ResumeState->SmmS3Cr3 = Cr3;\r
SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;\r
\r
\r
global ASM_PFX(gPatchSmmCr3)\r
global ASM_PFX(gPatchSmmCr4)\r
-global ASM_PFX(gSmmCr0)\r
+global ASM_PFX(gPatchSmmCr0)\r
global ASM_PFX(gSmmJmpAddr)\r
global ASM_PFX(gSmmInitStack)\r
global ASM_PFX(gcSmiInitGdtr)\r
rdmsr\r
or eax, ebx ; set NXE bit if NX is available\r
wrmsr\r
- DB 0x66, 0xb8 ; mov eax, imm32\r
-ASM_PFX(gSmmCr0): DD 0\r
+ mov eax, strict dword 0 ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr0):\r
mov di, PROTECT_MODE_DS\r
mov cr0, eax\r
DB 0x66, 0xea ; jmp far [ptr48]\r
//\r
// Control register contents saved for SMM S3 resume state initialization.\r
//\r
+UINT32 mSmmCr0;\r
UINT32 mSmmCr4;\r
\r
/**\r
//\r
// Patch ASM code template with current CR0, CR3, and CR4 values\r
//\r
- gSmmCr0 = (UINT32)AsmReadCr0 ();\r
+ mSmmCr0 = (UINT32)AsmReadCr0 ();\r
+ PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);\r
PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
mSmmCr4 = (UINT32)AsmReadCr4 ();\r
PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r
\r
extern CONST UINT8 gcSmmInitTemplate[];\r
extern CONST UINT16 gcSmmInitSize;\r
-extern UINT32 gSmmCr0;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0;\r
+extern UINT32 mSmmCr0;\r
X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;\r
extern UINT32 mSmmCr4;\r
X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;\r
\r
global ASM_PFX(gPatchSmmCr3)\r
global ASM_PFX(gPatchSmmCr4)\r
-global ASM_PFX(gSmmCr0)\r
+global ASM_PFX(gPatchSmmCr0)\r
global ASM_PFX(gSmmJmpAddr)\r
global ASM_PFX(gSmmInitStack)\r
global ASM_PFX(gcSmiInitGdtr)\r
or ah, BIT3 ; set NXE bit\r
.1:\r
wrmsr\r
- DB 0x66, 0xb8 ; mov eax, imm32\r
-ASM_PFX(gSmmCr0): DD 0\r
+ mov eax, strict dword 0 ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr0):\r
mov cr0, eax ; enable protected mode & paging\r
DB 0x66, 0xea ; far jmp to long mode\r
ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode\r