projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 11c20f4e | 1 | //\r |
| bebda7ce | 2 | // Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
| 11c20f4e | 3 | //\r |
| 3402aac7 RC |
4 | // This program and the accompanying materials\r |
| 5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
| 6 | // which accompanies this distribution. The full text of the license may be found at\r | |
| 7 | // http://opensource.org/licenses/bsd-license.php\r | |
| 8 | //\r | |
| 9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 11c20f4e | 11 | //\r |
| 12 | //\r | |
| 13 | \r | |
| 14 | #include <AsmMacroIoLib.h>\r | |
| 15 | #include <Base.h>\r | |
| 16 | #include <Library/PcdLib.h>\r | |
| 17 | #include <AutoGen.h>\r | |
| 18 | \r | |
| 19 | .text\r | |
| 20 | .align 3\r | |
| 21 | \r | |
| 11c20f4e | 22 | GCC_ASM_IMPORT(CEntryPoint)\r |
| 2d45f194 | 23 | GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r |
| bebda7ce | 24 | GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r |
| 0787bc61 | 25 | GCC_ASM_IMPORT(ArmReadMpidr)\r |
| b5a57223 | 26 | GCC_ASM_IMPORT(ArmPlatformPeiBootAction)\r |
| 11c20f4e | 27 | GCC_ASM_EXPORT(_ModuleEntryPoint)\r |
| 28 | \r | |
| 0787bc61 | 29 | StartupAddr: .word CEntryPoint\r |
| 11c20f4e | 30 | \r |
| 31 | ASM_PFX(_ModuleEntryPoint):\r | |
| b5a57223 | 32 | // Do early platform specific actions\r |
| 33 | bl ASM_PFX(ArmPlatformPeiBootAction)\r | |
| 34 | \r | |
| 2dbcb8f0 | 35 | // Identify CPU ID\r |
| 0787bc61 | 36 | bl ASM_PFX(ArmReadMpidr)\r |
| bebda7ce | 37 | // Keep a copy of the MpId register value\r |
| 38 | mov r5, r0\r | |
| 39 | \r | |
| 40 | // Is it the Primary Core ?\r | |
| 41 | bl ASM_PFX(ArmPlatformIsPrimaryCore)\r | |
| 42 | \r | |
| 1377db63 | 43 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
| 2dbcb8f0 | 44 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r |
| 45 | LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r | |
| 1377db63 | 46 | add r1, r1, r2\r |
| 2dbcb8f0 | 47 | \r |
| bebda7ce | 48 | // r0 is equal to 1 if I am the primary core\r |
| 49 | cmp r0, #1\r | |
| 2dbcb8f0 | 50 | beq _SetupPrimaryCoreStack\r |
| 51 | \r | |
| 52 | _SetupSecondaryCoreStack:\r | |
| 1377db63 | 53 | // r1 contains the base of the secondary stacks\r |
| 2dbcb8f0 | 54 | \r |
| 2d45f194 | 55 | // Get the Core Position\r |
| 56 | mov r6, r1 // Save base of the secondary stacks\r | |
| 57 | mov r0, r5\r | |
| 58 | bl ASM_PFX(ArmPlatformGetCorePosition)\r | |
| 2dbcb8f0 | 59 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r |
| 1377db63 | 60 | add r0, r0, #1\r |
| 2dbcb8f0 | 61 | \r |
| 2dbcb8f0 | 62 | // StackOffset = CorePos * StackSize\r |
| 1377db63 | 63 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2)\r |
| 64 | mul r0, r0, r2\r | |
| 2dbcb8f0 | 65 | // SP = StackBase + StackOffset\r |
| 2d45f194 | 66 | add sp, r6, r0\r |
| 11c20f4e | 67 | \r |
| 68 | _PrepareArguments:\r | |
| 2dbcb8f0 | 69 | // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r |
| f92b93c9 | 70 | LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)\r |
| 11c20f4e | 71 | add r2, r2, #4\r |
| 72 | ldr r1, [r2]\r | |
| 73 | \r | |
| 1377db63 | 74 | // Move sec startup address into a data register\r |
| 75 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
| 76 | ldr r3, StartupAddr\r | |
| 3402aac7 | 77 | \r |
| 1377db63 | 78 | // Jump to PrePeiCore C code\r |
| 2dbcb8f0 | 79 | // r0 = mp_id\r |
| 80 | // r1 = pei_core_address\r | |
| 1377db63 | 81 | mov r0, r5\r |
| 82 | blx r3\r | |
| 83 | \r | |
| 84 | _SetupPrimaryCoreStack:\r | |
| 3707dee3 | 85 | mov sp, r1\r |
| 1377db63 | 86 | b _PrepareArguments\r |
| 2dbcb8f0 | 87 | \r |
| 88 | _NeverReturn:\r | |
| 89 | b _NeverReturn\r |