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1d5d0ae9 | 1 | /** @file |
009f583f | 2 | * Main file supporting the SEC Phase on ARM Platforms |
1d5d0ae9 | 3 | * |
8cc852f7 | 4 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved. |
1d5d0ae9 | 5 | * |
6 | * This program and the accompanying materials | |
7 | * are licensed and made available under the terms and conditions of the BSD License | |
8 | * which accompanies this distribution. The full text of the license may be found at | |
9 | * http://opensource.org/licenses/bsd-license.php | |
10 | * | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
13 | * | |
14 | **/ | |
15 | ||
8cc852f7 | 16 | #include <Library/ArmTrustedMonitorLib.h> |
a6caee65 | 17 | #include <Library/DebugAgentLib.h> |
2637d1ef | 18 | #include <Library/PrintLib.h> |
1d5d0ae9 | 19 | #include <Library/BaseMemoryLib.h> |
1d5d0ae9 | 20 | #include <Library/SerialPortLib.h> |
55a0d64b | 21 | #include <Library/ArmGicLib.h> |
90d6a1bb | 22 | #include <Library/ArmCpuLib.h> |
0620eec9 | 23 | |
009f583f | 24 | #include "SecInternal.h" |
25 | ||
e862cd50 | 26 | #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1); |
2637d1ef | 27 | |
1d5d0ae9 | 28 | VOID |
29 | CEntryPoint ( | |
0787bc61 | 30 | IN UINTN MpId |
1d5d0ae9 | 31 | ) |
32 | { | |
2637d1ef | 33 | CHAR8 Buffer[100]; |
34 | UINTN CharCount; | |
a6caee65 | 35 | UINTN JumpAddress; |
2637d1ef | 36 | |
710b8acb | 37 | // Invalidate the data cache. Doesn't have to do the Data cache clean. |
38 | ArmInvalidateDataCache(); | |
39 | ||
40 | // Invalidate Instruction Cache | |
41 | ArmInvalidateInstructionCache(); | |
42 | ||
43 | // Invalidate I & D TLBs | |
44 | ArmInvalidateInstructionAndDataTlb(); | |
45 | ||
46 | // CPU specific settings | |
47 | ArmCpuSetup (MpId); | |
48 | ||
82344416 | 49 | // Enable Floating Point Coprocessor if supported by the platform |
50 | if (FixedPcdGet32 (PcdVFPEnabled)) { | |
51 | ArmEnableVFP(); | |
52 | } | |
53 | ||
1d5d0ae9 | 54 | // Primary CPU clears out the SCU tag RAMs, secondaries wait |
0787bc61 | 55 | if (IS_PRIMARY_CORE(MpId)) { |
90d6a1bb | 56 | if (ArmIsMpCore()) { |
57 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT); | |
1d5d0ae9 | 58 | } |
59 | ||
60 | // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib | |
61 | // In non SEC modules the init call is in autogenerated code. | |
62 | SerialPortInitialize (); | |
2637d1ef | 63 | |
1d5d0ae9 | 64 | // Start talking |
2637d1ef | 65 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__); |
66 | SerialPortWrite ((UINT8 *) Buffer, CharCount); | |
1d5d0ae9 | 67 | |
a6caee65 | 68 | // Initialize the Debug Agent for Source Level Debugging |
69 | InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); | |
70 | SaveAndSetDebugTimerInterrupt (TRUE); | |
71 | ||
1d5d0ae9 | 72 | // Now we've got UART, make the check: |
73 | // - The Vector table must be 32-byte aligned | |
74 | ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0); | |
90d6a1bb | 75 | |
76 | // Enable the GIC distributor and CPU Interface | |
77 | // - no other Interrupts are enabled, doesn't have to worry about the priority. | |
78 | // - all the cores are in secure state, use secure SGI's | |
79 | ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase)); | |
80 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
81 | } else { | |
82 | // Enable the GIC CPU Interface | |
83 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
1d5d0ae9 | 84 | } |
85 | ||
1d5d0ae9 | 86 | // Enable Full Access to CoProcessors |
87 | ArmWriteCPACR (CPACR_CP_FULL_ACCESS); | |
88 | ||
0787bc61 | 89 | if (IS_PRIMARY_CORE(MpId)) { |
8e06b586 | 90 | // Initialize peripherals that must be done at the early stage |
91 | // Example: Some L2x0 controllers must be initialized in Secure World | |
aa01abaa | 92 | ArmPlatformSecInitialize (); |
1d5d0ae9 | 93 | |
94 | // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase. | |
95 | // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM | |
90d6a1bb | 96 | if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) { |
1d5d0ae9 | 97 | // Initialize system memory (DRAM) |
1ad14bc8 | 98 | ArmPlatformInitializeSystemMemory (); |
1d5d0ae9 | 99 | } |
1d5d0ae9 | 100 | } |
101 | ||
102 | // Test if Trustzone is supported on this platform | |
12c5ae23 | 103 | if (FixedPcdGetBool (PcdTrustzoneSupport)) { |
009f583f | 104 | // Ensure the Monitor Stack Base & Size have been set |
105 | ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0); | |
106 | ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0); | |
107 | ||
90d6a1bb | 108 | if (ArmIsMpCore()) { |
1d5d0ae9 | 109 | // Setup SMP in Non Secure world |
90d6a1bb | 110 | ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId)); |
1d5d0ae9 | 111 | } |
112 | ||
113 | // Enter Monitor Mode | |
fab5507a | 114 | enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1)))); |
1d5d0ae9 | 115 | |
8cc852f7 | 116 | //-------------------- Monitor Mode --------------------- |
117 | ||
118 | // Set up Monitor World (Vector Table, etc) | |
119 | ArmSecureMonitorWorldInitialize (); | |
1d5d0ae9 | 120 | |
0620eec9 | 121 | // Setup the Trustzone Chipsets |
0787bc61 | 122 | if (IS_PRIMARY_CORE(MpId)) { |
009f583f | 123 | ArmPlatformTrustzoneInit (); |
1d5d0ae9 | 124 | |
90d6a1bb | 125 | // Waiting for the Primary Core to have finished to initialize the Secure World |
126 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT); | |
1d5d0ae9 | 127 | } else { |
128 | // The secondary cores need to wait until the Trustzone chipsets configuration is done | |
0620eec9 | 129 | // before switching to Non Secure World |
1d5d0ae9 | 130 | |
90d6a1bb | 131 | // Waiting for the Primary Core to have finished to initialize the Secure World |
132 | ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT); | |
1d5d0ae9 | 133 | } |
134 | ||
135 | // Transfer the interrupt to Non-secure World | |
90d6a1bb | 136 | ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase)); |
1d5d0ae9 | 137 | |
513aa349 | 138 | // Write to CP15 Non-secure Access Control Register |
139 | ArmWriteNsacr (PcdGet32 (PcdArmNsacr)); | |
140 | ||
141 | // CP15 Secure Configuration Register | |
142 | ArmWriteScr (PcdGet32 (PcdArmScr)); | |
1d5d0ae9 | 143 | } else { |
0787bc61 | 144 | if (IS_PRIMARY_CORE(MpId)) { |
2637d1ef | 145 | SerialPrint ("Trust Zone Configuration is disabled\n\r"); |
1d5d0ae9 | 146 | } |
147 | ||
1d5d0ae9 | 148 | // With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). |
149 | // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program | |
150 | // Status Register as the the current one (CPSR). | |
a6caee65 | 151 | copy_cpsr_into_spsr (); |
1d5d0ae9 | 152 | } |
153 | ||
f92b93c9 | 154 | JumpAddress = PcdGet32 (PcdFvBaseAddress); |
0787bc61 | 155 | ArmPlatformSecExtraAction (MpId, &JumpAddress); |
64e03133 | 156 | |
513aa349 | 157 | // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition |
158 | // By not set, the mode for Non Secure World is SVC | |
159 | if (PcdGet32 (PcdArmNonSecModeTransition) != 0) { | |
160 | set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition)); | |
161 | } | |
162 | ||
a6caee65 | 163 | return_from_exception (JumpAddress); |
1d5d0ae9 | 164 | //-------------------- Non Secure Mode --------------------- |
165 | ||
166 | // PEI Core should always load and never return | |
167 | ASSERT (FALSE); | |
168 | } | |
169 | ||
2637d1ef | 170 | VOID |
171 | SecCommonExceptionEntry ( | |
172 | IN UINT32 Entry, | |
173 | IN UINT32 LR | |
174 | ) | |
175 | { | |
176 | CHAR8 Buffer[100]; | |
177 | UINTN CharCount; | |
178 | ||
1d5d0ae9 | 179 | switch (Entry) { |
180 | case 0: | |
2637d1ef | 181 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 182 | break; |
183 | case 1: | |
2637d1ef | 184 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 185 | break; |
186 | case 2: | |
2637d1ef | 187 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 188 | break; |
189 | case 3: | |
2637d1ef | 190 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 191 | break; |
192 | case 4: | |
2637d1ef | 193 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 194 | break; |
195 | case 5: | |
2637d1ef | 196 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 197 | break; |
198 | case 6: | |
2637d1ef | 199 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 200 | break; |
201 | case 7: | |
2637d1ef | 202 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 203 | break; |
204 | default: | |
2637d1ef | 205 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 206 | break; |
207 | } | |
2637d1ef | 208 | SerialPortWrite ((UINT8 *) Buffer, CharCount); |
1d5d0ae9 | 209 | while(1); |
210 | } |