[mirror_edk2.git] / UefiCpuPkg / UefiCpuPkg.dec

## @file  UefiCpuPkg.dec\r
# This Package provides UEFI compatible CPU modules and libraries.\r
#\r
# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = UefiCpuPkg\r
  PACKAGE_UNI_FILE               = UefiCpuPkg.uni\r
  PACKAGE_GUID                   = 2171df9b-0d39-45aa-ac37-2de190010d23\r
  PACKAGE_VERSION                = 0.90\r
\r
[Includes]\r
  Include\r
\r
[LibraryClasses]\r
  ##  @libraryclass  Defines some routines that are generic for IA32 family CPU\r
  ##                 to be UEFI specification compliant.\r
  ##\r
  UefiCpuLib|Include/Library/UefiCpuLib.h\r
\r
  ##  @libraryclass  Defines some routines that are used to register/manage/program\r
  ##                 CPU features.\r
  ##\r
  RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h\r
\r
[LibraryClasses.IA32, LibraryClasses.X64]\r
  ##  @libraryclass  Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r
  ##\r
  MtrrLib|Include/Library/MtrrLib.h\r
\r
  ##  @libraryclass  Provides functions to manage the Local APIC on IA32 and X64 CPUs.\r
  ##\r
  LocalApicLib|Include/Library/LocalApicLib.h\r
\r
  ##  @libraryclass  Provides platform specific initialization functions in the SEC phase.\r
  ##\r
  PlatformSecLib|Include/Library/PlatformSecLib.h\r
\r
  ##  @libraryclass  Public include file for the SMM CPU Platform Hook Library.\r
  ##\r
  SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h\r
\r
  ##  @libraryclass  Provides the CPU specific programming for PiSmmCpuDxeSmm module.\r
  ##\r
  SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h\r
\r
  ##  @libraryclass  Provides functions to support MP services on CpuMpPei and CpuDxe module.\r
  ##\r
  MpInitLib|Include/Library/MpInitLib.h\r
\r
[Guids]\r
  gUefiCpuPkgTokenSpaceGuid      = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
  gMsegSmramGuid                 = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
\r
  ## Include/Guid/CpuFeaturesSetDone.h\r
  gEdkiiCpuFeaturesSetDoneGuid   = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r
\r
  ## Include/Guid/CpuFeaturesInitDone.h\r
  gEdkiiCpuFeaturesInitDoneGuid  = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
\r
[Protocols]\r
  ## Include/Protocol/SmmCpuService.h\r
  gEfiSmmCpuServiceProtocolGuid  = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
\r
  ## Include/Protocol/SmMonitorInit.h\r
  gEfiSmMonitorInitProtocolGuid  = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r
\r
#\r
# [Error.gUefiCpuPkgTokenSpaceGuid]\r
#   0x80000001 | Invalid value provided.\r
#\r
\r
[PcdsFeatureFlag]\r
  ## Indicates if SMM Profile will be enabled.\r
  #  If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
  #  It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).\r
  #  This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
  #   TRUE  - SMM Profile will be enabled.<BR>\r
  #   FALSE - SMM Profile will be disabled.<BR>\r
  # @Prompt Enable SMM Profile.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109\r
\r
  ## Indicates if the SMM profile log buffer is a ring buffer.\r
  #  If disabled, no additional log can be done when the buffer is full.<BR><BR>\r
  #   TRUE  - the SMM profile log buffer is a ring buffer.<BR>\r
  #   FALSE - the SMM profile log buffer is a normal buffer.<BR>\r
  # @Prompt The SMM profile log buffer is a ring buffer.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a\r
\r
  ## Indicates if SMM Startup AP in a blocking fashion.\r
  #   TRUE  - SMM Startup AP in a blocking fashion.<BR>\r
  #   FALSE - SMM Startup AP in a non-blocking fashion.<BR>\r
  # @Prompt SMM Startup AP in a blocking fashion.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108\r
\r
  ## Indicates if SMM Stack Guard will be enabled.\r
  #  If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r
  #   TRUE  - SMM Stack Guard will be enabled.<BR>\r
  #   FALSE - SMM Stack Guard will be disabled.<BR>\r
  # @Prompt Enable SMM Stack Guard.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C\r
\r
  ## Indicates if BSP election in SMM will be enabled.\r
  #  If enabled, a BSP will be dynamically elected among all processors in each SMI.\r
  #  Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>\r
  #   TRUE  - BSP election in SMM will be enabled.<BR>\r
  #   FALSE - BSP election in SMM will be disabled.<BR>\r
  # @Prompt Enable BSP election in SMM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106\r
\r
  ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>\r
  #   TRUE  - SMM CPU hot-plug will be enabled.<BR>\r
  #   FALSE - SMM CPU hot-plug will be disabled.<BR>\r
  # @Prompt SMM CPU hot-plug.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C\r
\r
  ## Indicates if SMM Debug will be enabled.\r
  #  If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>\r
  #   TRUE  - SMM Debug will be enabled.<BR>\r
  #   FALSE - SMM Debug will be disabled.<BR>\r
  # @Prompt Enable SMM Debug.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B\r
\r
  ## Indicates if lock SMM Feature Control MSR.<BR><BR>\r
  #   TRUE  - SMM Feature Control MSR will be locked.<BR>\r
  #   FALSE - SMM Feature Control MSR will not be locked.<BR>\r
  # @Prompt Lock SMM Feature Control MSR.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
\r
[PcdsFixedAtBuild]\r
  ## List of exception vectors which need switching stack.\r
  #  This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
  #  By default exception #DD(8), #PF(14) are supported.\r
  # @Prompt Specify exception vectors which need switching stack.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000\r
\r
  ## Size of good stack for an exception.\r
  #  This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
  # @Prompt Specify size of good stack of exception which need switching stack.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r
\r
[PcdsFixedAtBuild, PcdsPatchableInModule]\r
  ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
  # @Prompt Configure base address of CPU Local APIC\r
  # @Expression  0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001\r
\r
  ## Specifies delay value in microseconds after sending out an INIT IPI.\r
  # @Prompt Configure delay value after send an INIT IPI\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r
\r
  ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r
  ## aligns the address on a 4-KByte boundary.\r
  # @Prompt Configure stack size for Application Processor (AP)\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003\r
\r
  ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r
  # @Prompt Stack size in the temporary RAM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003\r
\r
  ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r
  # @Prompt SMM profile data buffer size.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107\r
\r
  ## Specifies stack size in bytes for each processor in SMM.\r
  # @Prompt Processor stack size in SMM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r
\r
  ## Specifies shadow stack size in bytes for each processor in SMM.\r
  # @Prompt Processor shadow stack size in SMM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E\r
\r
  ## Indicates if SMM Code Access Check is enabled.\r
  #  If enabled, the SMM handler cannot execute the code outside SMM regions.\r
  #  This PCD is suggested to TRUE in production image.<BR><BR>\r
  #   TRUE  - SMM Code Access Check will be enabled.<BR>\r
  #   FALSE - SMM Code Access Check will be disabled.<BR>\r
  # @Prompt SMM Code Access Check.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r
\r
  ## Specifies the number of variable MTRRs reserved for OS use. The default number of\r
  #  MTRRs reserved for OS use is 2.\r
  # @Prompt Number of reserved variable MTRRs.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r
\r
  ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r
  # @Prompt STM exception stack size.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111\r
\r
  ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r
  # @Prompt MSEG size.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r
\r
  ## Specifies the supported CPU features bit in array.\r
  # @Prompt Supported CPU features.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r
\r
  ## Specifies if CPU features will be initialized after SMM relocation.\r
  # @Prompt If CPU features will be initialized after SMM relocation.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r
\r
  ## Specifies if CPU features will be initialized during S3 resume.\r
  # @Prompt If CPU features will be initialized during S3 resume.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
\r
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
  ## Specifies max supported number of Logical Processors.\r
  # @Prompt Configure max supported number of Logical Processors\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r
  ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
  # @Prompt Timeout for the BSP to detect all APs for the first time.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
  ## Specifies the base address of the first microcode Patch in the microcode Region.\r
  # @Prompt Microcode Region base address.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r
  ## Specifies the size of the microcode Region.\r
  # @Prompt Microcode Region size.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r
  ## Specifies the AP wait loop state during POST phase.\r
  #  The value is defined as below.<BR><BR>\r
  #  1: Place AP in the Hlt-Loop state.<BR>\r
  #  2: Place AP in the Mwait-Loop state.<BR>\r
  #  3: Place AP in the Run-Loop state.<BR>\r
  # @Prompt The AP wait loop state.\r
  # @ValidRange  0x80000001 | 1 - 3\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r
  ## Specifies the AP target C-state for Mwait during POST phase.\r
  #  The default value 0 means C1 state.\r
  #  The value is defined as below.<BR><BR>\r
  # @Prompt The specified AP target C-state for Mwait.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
\r
  ## Indicates if SMM uses static page table.\r
  #  If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.\r
  #  This flag only impacts X64 build, because SMM always builds static page table for IA32.\r
  #  It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
  #  It could not be enabled also at the same time with heap guard feature for SMM\r
  #  (PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>\r
  #   TRUE  - SMM uses static page table for all memory.<BR>\r
  #   FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
  # @Prompt Use static page table for all memory in SMM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D\r
\r
  ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
  # @Prompt AP synchronization timeout value in SMM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
\r
  ## Indicates the CPU synchronization method used when processing an SMI.\r
  #   0x00  - Traditional CPU synchronization method.<BR>\r
  #   0x01  - Relaxed CPU synchronization method.<BR>\r
  # @Prompt SMM CPU Synchronization Method.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
\r
  ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r
  # @Prompt The encoded values for target duty cycle modulation.\r
  # @ValidRange  0x80000001 | 0 - 15\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A\r
\r
  ## Indicates if the current boot is a power-on reset.<BR><BR>\r
  #   TRUE  - Current boot is a power-on reset.<BR>\r
  #   FALSE - Current boot is not a power-on reset.<BR>\r
  # @Prompt Current boot is a power-on reset.\r
  gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
\r
[PcdsDynamic, PcdsDynamicEx]\r
  ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
  # @Prompt The pointer to a CPU S3 data buffer.\r
  # @ValidList   0x80000001 | 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010\r
\r
  ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r
  # @Prompt The pointer to CPU Hot Plug Data.\r
  # @ValidList   0x80000001 | 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r
\r
  ## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r
  # @Prompt Processor feature capabilities.\r
  # @ValidList   0x80000001 | 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r
\r
  ## As input, specifies user's desired settings for enabling/disabling processor features.\r
  ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.\r
  # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.\r
  # @ValidList   0x80000001 | 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r
\r
  ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r
  #  Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
  #  This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
  #  Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r
  #  0x0  -  4K.<BR>\r
  #  0x1  -  8K.<BR>\r
  #  0x2  -  16K.<BR>\r
  #  0x3  -  32K.<BR>\r
  #  0x4  -  64K.<BR>\r
  #  0x5  -  128K.<BR>\r
  #  0x6  -  256K.<BR>\r
  #  0x7  -  512K.<BR>\r
  #  0x8  -  1M.<BR>\r
  #  0x9  -  2M.<BR>\r
  #  0xA  -  4M.<BR>\r
  #  0xB  -  8M.<BR>\r
  #  0xC  -  16M.<BR>\r
  #  0xD  -  32M.<BR>\r
  #  0xE  -  64M.<BR>\r
  #  0xF  -  128M.<BR>\r
  # @Prompt The memory size used for processor trace if processor trace is enabled.\r
  # @ValidRange  0x80000001 | 0 - 0xF\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r
\r
  ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r
  #  Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
  #  This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
  #  Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r
  #  0 - Single Range output scheme.<BR>\r
  #  1 - ToPA(Table of physical address) scheme.<BR>\r
  # @Prompt The processor trace output scheme used when processor trace is enabled.\r
  # @ValidRange  0x80000001 | 0 - 1\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
\r
[UserExtensions.TianoCore."ExtraFiles"]\r
  UefiCpuPkgExtra.uni\r
Commit	Line	Data
7798fb83	1	## @file UefiCpuPkg.dec\r
7798fb83 HT	2	# This Package provides UEFI compatible CPU modules and libraries.\r
7798fb83 HT	3	#\r
3eb69b08	4	# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
7798fb83	5	#\r
0acd8697	6	# SPDX-License-Identifier: BSD-2-Clause-Patent\r
7798fb83 HT	7	#\r
	8	##\r
	9	\r
	10	[Defines]\r
	11	DEC_SPECIFICATION = 0x00010005\r
	12	PACKAGE_NAME = UefiCpuPkg\r
abae030a	13	PACKAGE_UNI_FILE = UefiCpuPkg.uni\r
7798fb83	14	PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r
30142a32	15	PACKAGE_VERSION = 0.90\r
7798fb83 HT	16	\r
	17	[Includes]\r
	18	Include\r
	19	\r
	20	[LibraryClasses]\r
	21	## @libraryclass Defines some routines that are generic for IA32 family CPU\r
	22	## to be UEFI specification compliant.\r
	23	##\r
	24	UefiCpuLib\|Include/Library/UefiCpuLib.h\r
	25	\r
548013c0 JF	26	## @libraryclass Defines some routines that are used to register/manage/program\r
	27	## CPU features.\r
	28	##\r
245e98bf	29	RegisterCpuFeaturesLib\|Include/Library/RegisterCpuFeaturesLib.h\r
548013c0	30	\r
7798fb83 HT	31	[LibraryClasses.IA32, LibraryClasses.X64]\r
	32	## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r
	33	##\r
	34	MtrrLib\|Include/Library/MtrrLib.h\r
	35	\r
	36	## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.\r
	37	##\r
	38	LocalApicLib\|Include/Library/LocalApicLib.h\r
d947a4cc MK	39	\r
	40	## @libraryclass Provides platform specific initialization functions in the SEC phase.\r
	41	##\r
	42	PlatformSecLib\|Include/Library/PlatformSecLib.h\r
529a5a86	43	\r
406c7200 MK	44	## @libraryclass Public include file for the SMM CPU Platform Hook Library.\r
	45	##\r
	46	SmmCpuPlatformHookLib\|Include/Library/SmmCpuPlatformHookLib.h\r
529a5a86	47	\r
406c7200 MK	48	## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.\r
	49	##\r
	50	SmmCpuFeaturesLib\|Include/Library/SmmCpuFeaturesLib.h\r
	51	\r
87896d03 JF	52	## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.\r
	53	##\r
	54	MpInitLib\|Include/Library/MpInitLib.h\r
	55	\r
7798fb83 HT	56	[Guids]\r
7798fb83 HT	57	gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
f7c11c53	58	gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
7798fb83	59	\r
98f4a565 JF	60	## Include/Guid/CpuFeaturesSetDone.h\r
	61	gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r
	62	\r
e000e774 JF	63	## Include/Guid/CpuFeaturesInitDone.h\r
	64	gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
	65	\r
406c7200 MK	66	[Protocols]\r
	67	## Include/Protocol/SmmCpuService.h\r
	68	gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
529a5a86	69	\r
f7c11c53 MK	70	## Include/Protocol/SmMonitorInit.h\r
	71	gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r
	72	\r
abae030a LG	73	#\r
	74	# [Error.gUefiCpuPkgTokenSpaceGuid]\r
	75	# 0x80000001 \| Invalid value provided.\r
	76	#\r
	77	\r
529a5a86 MK	78	[PcdsFeatureFlag]\r
	79	## Indicates if SMM Profile will be enabled.\r
	80	# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
1015fb3c	81	# It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).\r
529a5a86 MK	82	# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
	83	# TRUE - SMM Profile will be enabled.<BR>\r
	84	# FALSE - SMM Profile will be disabled.<BR>\r
	85	# @Prompt Enable SMM Profile.\r
	86	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable\|FALSE\|BOOLEAN\|0x32132109\r
	87	\r
	88	## Indicates if the SMM profile log buffer is a ring buffer.\r
	89	# If disabled, no additional log can be done when the buffer is full.<BR><BR>\r
	90	# TRUE - the SMM profile log buffer is a ring buffer.<BR>\r
	91	# FALSE - the SMM profile log buffer is a normal buffer.<BR>\r
	92	# @Prompt The SMM profile log buffer is a ring buffer.\r
	93	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer\|FALSE\|BOOLEAN\|0x3213210a\r
	94	\r
	95	## Indicates if SMM Startup AP in a blocking fashion.\r
	96	# TRUE - SMM Startup AP in a blocking fashion.<BR>\r
	97	# FALSE - SMM Startup AP in a non-blocking fashion.<BR>\r
	98	# @Prompt SMM Startup AP in a blocking fashion.\r
	99	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp\|FALSE\|BOOLEAN\|0x32132108\r
	100	\r
	101	## Indicates if SMM Stack Guard will be enabled.\r
509f8425	102	# If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r
529a5a86 MK	103	# TRUE - SMM Stack Guard will be enabled.<BR>\r
	104	# FALSE - SMM Stack Guard will be disabled.<BR>\r
	105	# @Prompt Enable SMM Stack Guard.\r
509f8425	106	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard\|TRUE\|BOOLEAN\|0x1000001C\r
529a5a86 MK	107	\r
	108	## Indicates if BSP election in SMM will be enabled.\r
	109	# If enabled, a BSP will be dynamically elected among all processors in each SMI.\r
	110	# Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>\r
	111	# TRUE - BSP election in SMM will be enabled.<BR>\r
	112	# FALSE - BSP election in SMM will be disabled.<BR>\r
	113	# @Prompt Enable BSP election in SMM.\r
	114	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection\|TRUE\|BOOLEAN\|0x32132106\r
	115	\r
	116	## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>\r
	117	# TRUE - SMM CPU hot-plug will be enabled.<BR>\r
	118	# FALSE - SMM CPU hot-plug will be disabled.<BR>\r
	119	# @Prompt SMM CPU hot-plug.\r
	120	gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport\|FALSE\|BOOLEAN\|0x3213210C\r
	121	\r
	122	## Indicates if SMM Debug will be enabled.\r
	123	# If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>\r
	124	# TRUE - SMM Debug will be enabled.<BR>\r
	125	# FALSE - SMM Debug will be disabled.<BR>\r
	126	# @Prompt Enable SMM Debug.\r
	127	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug\|FALSE\|BOOLEAN\|0x1000001B\r
	128	\r
	129	## Indicates if lock SMM Feature Control MSR.<BR><BR>\r
	130	# TRUE - SMM Feature Control MSR will be locked.<BR>\r
	131	# FALSE - SMM Feature Control MSR will not be locked.<BR>\r
	132	# @Prompt Lock SMM Feature Control MSR.\r
	133	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock\|TRUE\|BOOLEAN\|0x3213210B\r
	134	\r
adb9f50e JW	135	[PcdsFixedAtBuild]\r
	136	## List of exception vectors which need switching stack.\r
	137	# This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
	138	# By default exception #DD(8), #PF(14) are supported.\r
	139	# @Prompt Specify exception vectors which need switching stack.\r
	140	gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList\|{0x08, 0x0E}\|VOID*\|0x30002000\r
	141	\r
	142	## Size of good stack for an exception.\r
	143	# This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
	144	# @Prompt Specify size of good stack of exception which need switching stack.\r
	145	gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize\|2048\|UINT32\|0x30002001\r
	146	\r
7798fb83	147	[PcdsFixedAtBuild, PcdsPatchableInModule]\r
529a5a86 MK	148	## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
529a5a86 MK	149	# @Prompt Configure base address of CPU Local APIC\r
abae030a	150	# @Expression 0x80000001 \| (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0\r
7798fb83	151	gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress\|0xfee00000\|UINT32\|0x00000001\r
529a5a86	152	\r
abae030a LG	153	## Specifies delay value in microseconds after sending out an INIT IPI.\r
abae030a LG	154	# @Prompt Configure delay value after send an INIT IPI\r
cf1eb6e6	155	gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds\|10000\|UINT32\|0x30000002\r
529a5a86	156	\r
6a26a597 CF	157	## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r
	158	## aligns the address on a 4-KByte boundary.\r
	159	# @Prompt Configure stack size for Application Processor (AP)\r
	160	gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize\|0x8000\|UINT32\|0x00000003\r
7798fb83	161	\r
d947a4cc MK	162	## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r
	163	# @Prompt Stack size in the temporary RAM.\r
	164	gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize\|0\|UINT32\|0x10001003\r
	165	\r
529a5a86 MK	166	## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r
	167	# @Prompt SMM profile data buffer size.\r
	168	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize\|0x200000\|UINT32\|0x32132107\r
	169	\r
	170	## Specifies stack size in bytes for each processor in SMM.\r
	171	# @Prompt Processor stack size in SMM.\r
	172	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize\|0x2000\|UINT32\|0x32132105\r
	173	\r
3eb69b08 JY	174	## Specifies shadow stack size in bytes for each processor in SMM.\r
	175	# @Prompt Processor shadow stack size in SMM.\r
	176	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize\|0x2000\|UINT32\|0x3213210E\r
	177	\r
529a5a86 MK	178	## Indicates if SMM Code Access Check is enabled.\r
	179	# If enabled, the SMM handler cannot execute the code outside SMM regions.\r
	180	# This PCD is suggested to TRUE in production image.<BR><BR>\r
	181	# TRUE - SMM Code Access Check will be enabled.<BR>\r
	182	# FALSE - SMM Code Access Check will be disabled.<BR>\r
	183	# @Prompt SMM Code Access Check.\r
	184	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable\|TRUE\|BOOLEAN\|0x60000013\r
	185	\r
46309b11 JF	186	## Specifies the number of variable MTRRs reserved for OS use. The default number of\r
	187	# MTRRs reserved for OS use is 2.\r
	188	# @Prompt Number of reserved variable MTRRs.\r
	189	gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs\|0x2\|UINT32\|0x00000015\r
	190	\r
f7c11c53 MK	191	## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r
	192	# @Prompt STM exception stack size.\r
	193	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize\|0x1000\|UINT32\|0x32132111\r
	194	\r
	195	## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r
	196	# @Prompt MSEG size.\r
	197	gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize\|0x200000\|UINT32\|0x32132112\r
	198	\r
98eb0095 JF	199	## Specifies the supported CPU features bit in array.\r
98eb0095 JF	200	# @Prompt Supported CPU features.\r
7eee4e1e JF	201	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport\|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}\|VOID*\|0x00000016\r
7eee4e1e JF	202	\r
98eb0095 JF	203	## Specifies if CPU features will be initialized after SMM relocation.\r
98eb0095 JF	204	# @Prompt If CPU features will be initialized after SMM relocation.\r
82e75ac6 JF	205	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation\|FALSE\|BOOLEAN\|0x0000001C\r
82e75ac6 JF	206	\r
98eb0095 JF	207	## Specifies if CPU features will be initialized during S3 resume.\r
98eb0095 JF	208	# @Prompt If CPU features will be initialized during S3 resume.\r
82e75ac6 JF	209	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume\|FALSE\|BOOLEAN\|0x0000001D\r
82e75ac6 JF	210	\r
f79fcf45	211	[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
b1e01bd4 JF	212	## Specifies max supported number of Logical Processors.\r
	213	# @Prompt Configure max supported number of Logical Processors\r
	214	gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber\|64\|UINT32\|0x00000002\r
f79fcf45 JF	215	## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
	216	# @Prompt Timeout for the BSP to detect all APs for the first time.\r
	217	gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds\|50000\|UINT32\|0x00000004\r
30314463 JF	218	## Specifies the base address of the first microcode Patch in the microcode Region.\r
	219	# @Prompt Microcode Region base address.\r
	220	gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress\|0x0\|UINT64\|0x00000005\r
	221	## Specifies the size of the microcode Region.\r
	222	# @Prompt Microcode Region size.\r
	223	gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize\|0x0\|UINT64\|0x00000006\r
54a3e8c9 JF	224	## Specifies the AP wait loop state during POST phase.\r
	225	# The value is defined as below.<BR><BR>\r
	226	# 1: Place AP in the Hlt-Loop state.<BR>\r
	227	# 2: Place AP in the Mwait-Loop state.<BR>\r
	228	# 3: Place AP in the Run-Loop state.<BR>\r
	229	# @Prompt The AP wait loop state.\r
	230	# @ValidRange 0x80000001 \| 1 - 3\r
	231	gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode\|1\|UINT8\|0x60008006\r
9d39ed93 JF	232	## Specifies the AP target C-state for Mwait during POST phase.\r
	233	# The default value 0 means C1 state.\r
	234	# The value is defined as below.<BR><BR>\r
	235	# @Prompt The specified AP target C-state for Mwait.\r
	236	gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate\|0\|UINT8\|0x00000007\r
f79fcf45	237	\r
28b020b5	238	## Indicates if SMM uses static page table.\r
1015fb3c SZ	239	# If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.\r
	240	# This flag only impacts X64 build, because SMM always builds static page table for IA32.\r
	241	# It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
	242	# It could not be enabled also at the same time with heap guard feature for SMM\r
	243	# (PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>\r
28b020b5 JY	244	# TRUE - SMM uses static page table for all memory.<BR>\r
	245	# FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
	246	# @Prompt Use static page table for all memory in SMM.\r
	247	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable\|TRUE\|BOOLEAN\|0x3213210D\r
	248	\r
b43dd229 LE	249	## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
	250	# @Prompt AP synchronization timeout value in SMM.\r
	251	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout\|1000000\|UINT64\|0x32132104\r
	252	\r
	253	## Indicates the CPU synchronization method used when processing an SMI.\r
	254	# 0x00 - Traditional CPU synchronization method.<BR>\r
	255	# 0x01 - Relaxed CPU synchronization method.<BR>\r
	256	# @Prompt SMM CPU Synchronization Method.\r
	257	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode\|0x00\|UINT8\|0x60000014\r
	258	\r
0a70d1c3 JF	259	## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r
	260	# @Prompt The encoded values for target duty cycle modulation.\r
	261	# @ValidRange 0x80000001 \| 0 - 15\r
	262	gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle\|0x0\|UINT8\|0x0000001A\r
	263	\r
	264	## Indicates if the current boot is a power-on reset.<BR><BR>\r
	265	# TRUE - Current boot is a power-on reset.<BR>\r
	266	# FALSE - Current boot is not a power-on reset.<BR>\r
	267	# @Prompt Current boot is a power-on reset.\r
	268	gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset\|FALSE\|BOOLEAN\|0x0000001B\r
	269	\r
529a5a86 MK	270	[PcdsDynamic, PcdsDynamicEx]\r
	271	## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
	272	# @Prompt The pointer to a CPU S3 data buffer.\r
	273	# @ValidList 0x80000001 \| 0\r
	274	gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress\|0x0\|UINT64\|0x60000010\r
	275	\r
	276	## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r
	277	# @Prompt The pointer to CPU Hot Plug Data.\r
	278	# @ValidList 0x80000001 \| 0\r
	279	gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress\|0x0\|UINT64\|0x60000011\r
	280	\r
7eee4e1e JF	281	## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r
	282	# @Prompt Processor feature capabilities.\r
	283	# @ValidList 0x80000001 \| 0\r
	284	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability\|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\|VOID*\|0x00000018\r
	285	\r
6214ffb4 ED	286	## As input, specifies user's desired settings for enabling/disabling processor features.\r
	287	## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.\r
	288	# @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.\r
7eee4e1e JF	289	# @ValidList 0x80000001 \| 0\r
	290	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting\|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\|VOID*\|0x00000019\r
	291	\r
234d4c5f	292	## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r
34b6a0e2 ED	293	# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
	294	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
	295	# Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r
234d4c5f ED	296	# 0x0 - 4K.<BR>\r
	297	# 0x1 - 8K.<BR>\r
	298	# 0x2 - 16K.<BR>\r
	299	# 0x3 - 32K.<BR>\r
	300	# 0x4 - 64K.<BR>\r
	301	# 0x5 - 128K.<BR>\r
	302	# 0x6 - 256K.<BR>\r
	303	# 0x7 - 512K.<BR>\r
	304	# 0x8 - 1M.<BR>\r
	305	# 0x9 - 2M.<BR>\r
	306	# 0xA - 4M.<BR>\r
	307	# 0xB - 8M.<BR>\r
	308	# 0xC - 16M.<BR>\r
	309	# 0xD - 32M.<BR>\r
	310	# 0xE - 64M.<BR>\r
	311	# 0xF - 128M.<BR>\r
34b6a0e2 ED	312	# @Prompt The memory size used for processor trace if processor trace is enabled.\r
	313	# @ValidRange 0x80000001 \| 0 - 0xF\r
	314	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize\|0x0\|UINT32\|0x60000012\r
c7399a0c	315	\r
234d4c5f	316	## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r
34b6a0e2 ED	317	# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
	318	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
	319	# Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r
234d4c5f ED	320	# 0 - Single Range output scheme.<BR>\r
234d4c5f ED	321	# 1 - ToPA(Table of physical address) scheme.<BR>\r
34b6a0e2 ED	322	# @Prompt The processor trace output scheme used when processor trace is enabled.\r
	323	# @ValidRange 0x80000001 \| 0 - 1\r
	324	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme\|0x0\|UINT8\|0x60000015\r
c7399a0c	325	\r
abae030a LG	326	[UserExtensions.TianoCore."ExtraFiles"]\r
abae030a LG	327	UefiCpuPkgExtra.uni\r