2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
7 Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
8 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #include "SdMmcPciHcDxe.h"
22 Dump the content of SD/MMC host controller's Capability Register.
24 @param[in] Slot The slot number of the SD card to send the command to.
25 @param[in] Capability The buffer to store the capability data.
31 IN SD_MMC_HC_SLOT_CAP
*Capability
35 // Dump Capability Data
37 DEBUG ((DEBUG_INFO
, " == Slot [%d] Capability is 0x%x ==\n", Slot
, Capability
));
38 DEBUG ((DEBUG_INFO
, " Timeout Clk Freq %d%a\n", Capability
->TimeoutFreq
, (Capability
->TimeoutUnit
) ? "MHz" : "KHz"));
39 DEBUG ((DEBUG_INFO
, " Base Clk Freq %dMHz\n", Capability
->BaseClkFreq
));
40 DEBUG ((DEBUG_INFO
, " Max Blk Len %dbytes\n", 512 * (1 << Capability
->MaxBlkLen
)));
41 DEBUG ((DEBUG_INFO
, " 8-bit Support %a\n", Capability
->BusWidth8
? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO
, " ADMA2 Support %a\n", Capability
->Adma2
? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO
, " HighSpeed Support %a\n", Capability
->HighSpeed
? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO
, " SDMA Support %a\n", Capability
->Sdma
? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO
, " Suspend/Resume %a\n", Capability
->SuspRes
? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO
, " Voltage 3.3 %a\n", Capability
->Voltage33
? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO
, " Voltage 3.0 %a\n", Capability
->Voltage30
? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO
, " Voltage 1.8 %a\n", Capability
->Voltage18
? "TRUE" : "FALSE"));
49 DEBUG ((DEBUG_INFO
, " V4 64-bit Sys Bus %a\n", Capability
->SysBus64V4
? "TRUE" : "FALSE"));
50 DEBUG ((DEBUG_INFO
, " V3 64-bit Sys Bus %a\n", Capability
->SysBus64V3
? "TRUE" : "FALSE"));
51 DEBUG ((DEBUG_INFO
, " Async Interrupt %a\n", Capability
->AsyncInt
? "TRUE" : "FALSE"));
52 DEBUG ((DEBUG_INFO
, " SlotType "));
53 if (Capability
->SlotType
== 0x00) {
54 DEBUG ((DEBUG_INFO
, "%a\n", "Removable Slot"));
55 } else if (Capability
->SlotType
== 0x01) {
56 DEBUG ((DEBUG_INFO
, "%a\n", "Embedded Slot"));
57 } else if (Capability
->SlotType
== 0x02) {
58 DEBUG ((DEBUG_INFO
, "%a\n", "Shared Bus Slot"));
60 DEBUG ((DEBUG_INFO
, "%a\n", "Reserved"));
62 DEBUG ((DEBUG_INFO
, " SDR50 Support %a\n", Capability
->Sdr50
? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO
, " SDR104 Support %a\n", Capability
->Sdr104
? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO
, " DDR50 Support %a\n", Capability
->Ddr50
? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO
, " Driver Type A %a\n", Capability
->DriverTypeA
? "TRUE" : "FALSE"));
66 DEBUG ((DEBUG_INFO
, " Driver Type C %a\n", Capability
->DriverTypeC
? "TRUE" : "FALSE"));
67 DEBUG ((DEBUG_INFO
, " Driver Type D %a\n", Capability
->DriverTypeD
? "TRUE" : "FALSE"));
68 DEBUG ((DEBUG_INFO
, " Driver Type 4 %a\n", Capability
->DriverType4
? "TRUE" : "FALSE"));
69 if (Capability
->TimerCount
== 0) {
70 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt Disabled\n", 2 * (Capability
->TimerCount
- 1)));
72 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt %dseconds\n", 2 * (Capability
->TimerCount
- 1)));
74 DEBUG ((DEBUG_INFO
, " SDR50 Tuning %a\n", Capability
->TuningSDR50
? "TRUE" : "FALSE"));
75 DEBUG ((DEBUG_INFO
, " Retuning Mode Mode %d\n", Capability
->RetuningMod
+ 1));
76 DEBUG ((DEBUG_INFO
, " Clock Multiplier M = %d\n", Capability
->ClkMultiplier
+ 1));
77 DEBUG ((DEBUG_INFO
, " HS 400 %a\n", Capability
->Hs400
? "TRUE" : "FALSE"));
82 Read SlotInfo register from SD/MMC host controller pci config space.
84 @param[in] PciIo The PCI IO protocol instance.
85 @param[out] FirstBar The buffer to store the first BAR value.
86 @param[out] SlotNum The buffer to store the supported slot number.
88 @retval EFI_SUCCESS The operation succeeds.
89 @retval Others The operation fails.
95 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
101 SD_MMC_HC_SLOT_INFO SlotInfo
;
103 Status
= PciIo
->Pci
.Read (
106 SD_MMC_HC_SLOT_OFFSET
,
110 if (EFI_ERROR (Status
)) {
114 *FirstBar
= SlotInfo
.FirstBar
;
115 *SlotNum
= SlotInfo
.SlotNum
+ 1;
116 ASSERT ((*FirstBar
+ *SlotNum
) < SD_MMC_HC_MAX_SLOT
);
121 Read/Write specified SD/MMC host controller mmio register.
123 @param[in] PciIo The PCI IO protocol instance.
124 @param[in] BarIndex The BAR index of the standard PCI Configuration
125 header to use as the base address for the memory
126 operation to perform.
127 @param[in] Offset The offset within the selected BAR to start the
129 @param[in] Read A boolean to indicate it's read or write operation.
130 @param[in] Count The width of the mmio register in bytes.
131 Must be 1, 2 , 4 or 8 bytes.
132 @param[in, out] Data For read operations, the destination buffer to store
133 the results. For write operations, the source buffer
134 to write data from. The caller is responsible for
135 having ownership of the data buffer and ensuring its
136 size not less than Count bytes.
138 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
139 @retval EFI_SUCCESS The read/write operation succeeds.
140 @retval Others The read/write operation fails.
146 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
156 if ((PciIo
== NULL
) || (Data
== NULL
)) {
157 return EFI_INVALID_PARAMETER
;
160 if ((Count
!= 1) && (Count
!= 2) && (Count
!= 4) && (Count
!= 8)) {
161 return EFI_INVALID_PARAMETER
;
165 Status
= PciIo
->Mem
.Read (
174 Status
= PciIo
->Mem
.Write (
188 Do OR operation with the value of the specified SD/MMC host controller mmio register.
190 @param[in] PciIo The PCI IO protocol instance.
191 @param[in] BarIndex The BAR index of the standard PCI Configuration
192 header to use as the base address for the memory
193 operation to perform.
194 @param[in] Offset The offset within the selected BAR to start the
196 @param[in] Count The width of the mmio register in bytes.
197 Must be 1, 2 , 4 or 8 bytes.
198 @param[in] OrData The pointer to the data used to do OR operation.
199 The caller is responsible for having ownership of
200 the data buffer and ensuring its size not less than
203 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
204 @retval EFI_SUCCESS The OR operation succeeds.
205 @retval Others The OR operation fails.
211 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
222 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
223 if (EFI_ERROR (Status
)) {
228 Or
= *(UINT8
*) OrData
;
229 } else if (Count
== 2) {
230 Or
= *(UINT16
*) OrData
;
231 } else if (Count
== 4) {
232 Or
= *(UINT32
*) OrData
;
233 } else if (Count
== 8) {
234 Or
= *(UINT64
*) OrData
;
236 return EFI_INVALID_PARAMETER
;
240 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
246 Do AND operation with the value of the specified SD/MMC host controller mmio register.
248 @param[in] PciIo The PCI IO protocol instance.
249 @param[in] BarIndex The BAR index of the standard PCI Configuration
250 header to use as the base address for the memory
251 operation to perform.
252 @param[in] Offset The offset within the selected BAR to start the
254 @param[in] Count The width of the mmio register in bytes.
255 Must be 1, 2 , 4 or 8 bytes.
256 @param[in] AndData The pointer to the data used to do AND operation.
257 The caller is responsible for having ownership of
258 the data buffer and ensuring its size not less than
261 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
262 @retval EFI_SUCCESS The AND operation succeeds.
263 @retval Others The AND operation fails.
269 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
280 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
281 if (EFI_ERROR (Status
)) {
286 And
= *(UINT8
*) AndData
;
287 } else if (Count
== 2) {
288 And
= *(UINT16
*) AndData
;
289 } else if (Count
== 4) {
290 And
= *(UINT32
*) AndData
;
291 } else if (Count
== 8) {
292 And
= *(UINT64
*) AndData
;
294 return EFI_INVALID_PARAMETER
;
298 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
304 Wait for the value of the specified MMIO register set to the test value.
306 @param[in] PciIo The PCI IO protocol instance.
307 @param[in] BarIndex The BAR index of the standard PCI Configuration
308 header to use as the base address for the memory
309 operation to perform.
310 @param[in] Offset The offset within the selected BAR to start the
312 @param[in] Count The width of the mmio register in bytes.
313 Must be 1, 2, 4 or 8 bytes.
314 @param[in] MaskValue The mask value of memory.
315 @param[in] TestValue The test value of memory.
317 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
318 @retval EFI_SUCCESS The MMIO register has expected value.
319 @retval Others The MMIO operation fails.
324 SdMmcHcCheckMmioSet (
325 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
337 // Access PCI MMIO space to see if the value is the tested one.
340 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Value
);
341 if (EFI_ERROR (Status
)) {
347 if (Value
== TestValue
) {
351 return EFI_NOT_READY
;
355 Wait for the value of the specified MMIO register set to the test value.
357 @param[in] PciIo The PCI IO protocol instance.
358 @param[in] BarIndex The BAR index of the standard PCI Configuration
359 header to use as the base address for the memory
360 operation to perform.
361 @param[in] Offset The offset within the selected BAR to start the
363 @param[in] Count The width of the mmio register in bytes.
364 Must be 1, 2, 4 or 8 bytes.
365 @param[in] MaskValue The mask value of memory.
366 @param[in] TestValue The test value of memory.
367 @param[in] Timeout The time out value for wait memory set, uses 1
368 microsecond as a unit.
370 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
372 @retval EFI_SUCCESS The MMIO register has expected value.
373 @retval Others The MMIO operation fails.
379 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
389 BOOLEAN InfiniteWait
;
394 InfiniteWait
= FALSE
;
397 while (InfiniteWait
|| (Timeout
> 0)) {
398 Status
= SdMmcHcCheckMmioSet (
406 if (Status
!= EFI_NOT_READY
) {
411 // Stall for 1 microsecond.
422 Get the controller version information from the specified slot.
424 @param[in] PciIo The PCI IO protocol instance.
425 @param[in] Slot The slot number of the SD card to send the command to.
426 @param[out] Version The buffer to store the version information.
428 @retval EFI_SUCCESS The operation executes successfully.
429 @retval Others The operation fails.
433 SdMmcHcGetControllerVersion (
434 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
441 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CTRL_VER
, TRUE
, sizeof (UINT16
), Version
);
442 if (EFI_ERROR (Status
)) {
452 Software reset the specified SD/MMC host controller and enable all interrupts.
454 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
455 @param[in] Slot The slot number of the SD card to send the command to.
457 @retval EFI_SUCCESS The software reset executes successfully.
458 @retval Others The software reset fails.
463 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
469 EFI_PCI_IO_PROTOCOL
*PciIo
;
472 // Notify the SD/MMC override protocol that we are about to reset
473 // the SD/MMC host controller.
475 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
476 Status
= mOverride
->NotifyPhase (
477 Private
->ControllerHandle
,
481 if (EFI_ERROR (Status
)) {
483 "%a: SD/MMC pre reset notifier callback failed - %r\n",
484 __FUNCTION__
, Status
));
489 PciIo
= Private
->PciIo
;
491 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_SW_RST
, sizeof (SwReset
), &SwReset
);
493 if (EFI_ERROR (Status
)) {
494 DEBUG ((DEBUG_ERROR
, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status
));
498 Status
= SdMmcHcWaitMmioSet (
505 SD_MMC_HC_GENERIC_TIMEOUT
507 if (EFI_ERROR (Status
)) {
508 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: reset done with %r\n", Status
));
513 // Enable all interrupt after reset all.
515 Status
= SdMmcHcEnableInterrupt (PciIo
, Slot
);
516 if (EFI_ERROR (Status
)) {
517 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
523 // Notify the SD/MMC override protocol that we have just reset
524 // the SD/MMC host controller.
526 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
527 Status
= mOverride
->NotifyPhase (
528 Private
->ControllerHandle
,
532 if (EFI_ERROR (Status
)) {
534 "%a: SD/MMC post reset notifier callback failed - %r\n",
535 __FUNCTION__
, Status
));
543 Set all interrupt status bits in Normal and Error Interrupt Status Enable
546 @param[in] PciIo The PCI IO protocol instance.
547 @param[in] Slot The slot number of the SD card to send the command to.
549 @retval EFI_SUCCESS The operation executes successfully.
550 @retval Others The operation fails.
554 SdMmcHcEnableInterrupt (
555 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
563 // Enable all bits in Error Interrupt Status Enable Register
566 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_ERR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
567 if (EFI_ERROR (Status
)) {
571 // Enable all bits in Normal Interrupt Status Enable Register
574 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
580 Get the capability data from the specified slot.
582 @param[in] PciIo The PCI IO protocol instance.
583 @param[in] Slot The slot number of the SD card to send the command to.
584 @param[out] Capability The buffer to store the capability data.
586 @retval EFI_SUCCESS The operation executes successfully.
587 @retval Others The operation fails.
591 SdMmcHcGetCapability (
592 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
594 OUT SD_MMC_HC_SLOT_CAP
*Capability
600 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CAP
, TRUE
, sizeof (Cap
), &Cap
);
601 if (EFI_ERROR (Status
)) {
605 CopyMem (Capability
, &Cap
, sizeof (Cap
));
611 Get the maximum current capability data from the specified slot.
613 @param[in] PciIo The PCI IO protocol instance.
614 @param[in] Slot The slot number of the SD card to send the command to.
615 @param[out] MaxCurrent The buffer to store the maximum current capability data.
617 @retval EFI_SUCCESS The operation executes successfully.
618 @retval Others The operation fails.
622 SdMmcHcGetMaxCurrent (
623 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
625 OUT UINT64
*MaxCurrent
630 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_MAX_CURRENT_CAP
, TRUE
, sizeof (UINT64
), MaxCurrent
);
636 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
639 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
641 @param[in] PciIo The PCI IO protocol instance.
642 @param[in] Slot The slot number of the SD card to send the command to.
643 @param[out] MediaPresent The pointer to the media present boolean value.
645 @retval EFI_SUCCESS There is no media change happened.
646 @retval EFI_MEDIA_CHANGED There is media change happened.
647 @retval Others The detection fails.
652 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
654 OUT BOOLEAN
*MediaPresent
662 // Check Present State Register to see if there is a card presented.
664 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_PRESENT_STATE
, TRUE
, sizeof (PresentState
), &PresentState
);
665 if (EFI_ERROR (Status
)) {
669 if ((PresentState
& BIT16
) != 0) {
670 *MediaPresent
= TRUE
;
672 *MediaPresent
= FALSE
;
676 // Check Normal Interrupt Status Register
678 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, TRUE
, sizeof (Data
), &Data
);
679 if (EFI_ERROR (Status
)) {
683 if ((Data
& (BIT6
| BIT7
)) != 0) {
685 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
688 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data
), &Data
);
689 if (EFI_ERROR (Status
)) {
693 return EFI_MEDIA_CHANGED
;
700 Stop SD/MMC card clock.
702 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
704 @param[in] PciIo The PCI IO protocol instance.
705 @param[in] Slot The slot number of the SD card to send the command to.
707 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
708 @retval Others Fail to stop SD/MMC clock.
713 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
722 // Ensure no SD transactions are occurring on the SD Bus by
723 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
724 // in the Present State register to be 0.
726 Status
= SdMmcHcWaitMmioSet (
729 SD_MMC_HC_PRESENT_STATE
,
730 sizeof (PresentState
),
733 SD_MMC_HC_GENERIC_TIMEOUT
735 if (EFI_ERROR (Status
)) {
740 // Set SD Clock Enable in the Clock Control register to 0
742 ClockCtrl
= (UINT16
)~BIT2
;
743 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
749 SD/MMC card clock supply.
751 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
753 @param[in] PciIo The PCI IO protocol instance.
754 @param[in] Slot The slot number of the SD card to send the command to.
755 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
756 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
757 @param[in] ControllerVer The version of host controller.
759 @retval EFI_SUCCESS The clock is supplied successfully.
760 @retval Others The clock isn't supplied successfully.
765 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
768 IN UINT32 BaseClkFreq
,
769 IN UINT16 ControllerVer
779 // Calculate a divisor for SD clock frequency
781 ASSERT (BaseClkFreq
!= 0);
783 if (ClockFreq
== 0) {
784 return EFI_INVALID_PARAMETER
;
787 if (ClockFreq
> (BaseClkFreq
* 1000)) {
788 ClockFreq
= BaseClkFreq
* 1000;
792 // Calculate the divisor of base frequency.
795 SettingFreq
= BaseClkFreq
* 1000;
796 while (ClockFreq
< SettingFreq
) {
799 SettingFreq
= (BaseClkFreq
* 1000) / (2 * Divisor
);
800 Remainder
= (BaseClkFreq
* 1000) % (2 * Divisor
);
801 if ((ClockFreq
== SettingFreq
) && (Remainder
== 0)) {
804 if ((ClockFreq
== SettingFreq
) && (Remainder
!= 0)) {
809 DEBUG ((DEBUG_INFO
, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq
, Divisor
, ClockFreq
));
812 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
814 if ((ControllerVer
>= SD_MMC_HC_CTRL_VER_300
) &&
815 (ControllerVer
<= SD_MMC_HC_CTRL_VER_420
)) {
816 ASSERT (Divisor
<= 0x3FF);
817 ClockCtrl
= ((Divisor
& 0xFF) << 8) | ((Divisor
& 0x300) >> 2);
818 } else if ((ControllerVer
== SD_MMC_HC_CTRL_VER_100
) ||
819 (ControllerVer
== SD_MMC_HC_CTRL_VER_200
)) {
821 // Only the most significant bit can be used as divisor.
823 if (((Divisor
- 1) & Divisor
) != 0) {
824 Divisor
= 1 << (HighBitSet32 (Divisor
) + 1);
826 ASSERT (Divisor
<= 0x80);
827 ClockCtrl
= (Divisor
& 0xFF) << 8;
829 DEBUG ((DEBUG_ERROR
, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer
));
830 return EFI_UNSUPPORTED
;
834 // Stop bus clock at first
836 Status
= SdMmcHcStopClock (PciIo
, Slot
);
837 if (EFI_ERROR (Status
)) {
842 // Supply clock frequency with specified divisor
845 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, FALSE
, sizeof (ClockCtrl
), &ClockCtrl
);
846 if (EFI_ERROR (Status
)) {
847 DEBUG ((DEBUG_ERROR
, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
852 // Wait Internal Clock Stable in the Clock Control register to be 1
854 Status
= SdMmcHcWaitMmioSet (
857 SD_MMC_HC_CLOCK_CTRL
,
861 SD_MMC_HC_GENERIC_TIMEOUT
863 if (EFI_ERROR (Status
)) {
868 // Set SD Clock Enable in the Clock Control register to 1
871 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
877 SD/MMC bus power control.
879 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
881 @param[in] PciIo The PCI IO protocol instance.
882 @param[in] Slot The slot number of the SD card to send the command to.
883 @param[in] PowerCtrl The value setting to the power control register.
885 @retval TRUE There is a SD/MMC card attached.
886 @retval FALSE There is no a SD/MMC card attached.
890 SdMmcHcPowerControl (
891 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
901 PowerCtrl
&= (UINT8
)~BIT0
;
902 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
903 if (EFI_ERROR (Status
)) {
908 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
911 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
917 Set the SD/MMC bus width.
919 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
921 @param[in] PciIo The PCI IO protocol instance.
922 @param[in] Slot The slot number of the SD card to send the command to.
923 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
925 @retval EFI_SUCCESS The bus width is set successfully.
926 @retval Others The bus width isn't set successfully.
931 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
940 HostCtrl1
= (UINT8
)~(BIT5
| BIT1
);
941 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
942 } else if (BusWidth
== 4) {
943 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
944 if (EFI_ERROR (Status
)) {
948 HostCtrl1
&= (UINT8
)~BIT5
;
949 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
950 } else if (BusWidth
== 8) {
951 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
952 if (EFI_ERROR (Status
)) {
955 HostCtrl1
&= (UINT8
)~BIT1
;
957 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
960 return EFI_INVALID_PARAMETER
;
967 Configure V4 controller enhancements at initialization.
969 @param[in] PciIo The PCI IO protocol instance.
970 @param[in] Slot The slot number of the SD card to send the command to.
971 @param[in] Capability The capability of the slot.
972 @param[in] ControllerVer The version of host controller.
974 @retval EFI_SUCCESS The clock is supplied successfully.
978 SdMmcHcInitV4Enhancements (
979 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
981 IN SD_MMC_HC_SLOT_CAP Capability
,
982 IN UINT16 ControllerVer
989 // Check if controller version V4 or higher
991 if (ControllerVer
>= SD_MMC_HC_CTRL_VER_400
) {
992 HostCtrl2
= SD_MMC_HC_V4_EN
;
994 // Check if V4 64bit support is available
996 if (Capability
.SysBus64V4
!= 0) {
997 HostCtrl2
|= SD_MMC_HC_64_ADDR_EN
;
998 DEBUG ((DEBUG_INFO
, "Enabled V4 64 bit system bus support\n"));
1001 // Check if controller version V4.10 or higher
1003 if (ControllerVer
>= SD_MMC_HC_CTRL_VER_410
) {
1004 HostCtrl2
|= SD_MMC_HC_26_DATA_LEN_ADMA_EN
;
1005 DEBUG ((DEBUG_INFO
, "Enabled V4 26 bit data length ADMA support\n"));
1007 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1008 if (EFI_ERROR (Status
)) {
1017 Supply SD/MMC card with lowest clock frequency at initialization.
1019 @param[in] PciIo The PCI IO protocol instance.
1020 @param[in] Slot The slot number of the SD card to send the command to.
1021 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
1022 @param[in] ControllerVer The version of host controller.
1024 @retval EFI_SUCCESS The clock is supplied successfully.
1025 @retval Others The clock isn't supplied successfully.
1029 SdMmcHcInitClockFreq (
1030 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1032 IN UINT32 BaseClkFreq
,
1033 IN UINT16 ControllerVer
1040 // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
1041 // the Capability Register 1 can be zero, which means a need for obtaining
1042 // the clock frequency via another method. Fail in case it is not updated
1043 // by SW at this point.
1045 if (BaseClkFreq
== 0) {
1047 // Don't support get Base Clock Frequency information via another method
1049 return EFI_UNSUPPORTED
;
1052 // Supply 400KHz clock frequency at initialization phase.
1055 Status
= SdMmcHcClockSupply (PciIo
, Slot
, InitFreq
, BaseClkFreq
, ControllerVer
);
1060 Supply SD/MMC card with maximum voltage at initialization.
1062 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1064 @param[in] PciIo The PCI IO protocol instance.
1065 @param[in] Slot The slot number of the SD card to send the command to.
1066 @param[in] Capability The capability of the slot.
1068 @retval EFI_SUCCESS The voltage is supplied successfully.
1069 @retval Others The voltage isn't supplied successfully.
1073 SdMmcHcInitPowerVoltage (
1074 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1076 IN SD_MMC_HC_SLOT_CAP Capability
1084 // Calculate supported maximum voltage according to SD Bus Voltage Select
1086 if (Capability
.Voltage33
!= 0) {
1091 } else if (Capability
.Voltage30
!= 0) {
1096 } else if (Capability
.Voltage18
!= 0) {
1102 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1104 if (EFI_ERROR (Status
)) {
1109 return EFI_DEVICE_ERROR
;
1113 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1115 Status
= SdMmcHcPowerControl (PciIo
, Slot
, MaxVoltage
);
1121 Initialize the Timeout Control register with most conservative value at initialization.
1123 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1125 @param[in] PciIo The PCI IO protocol instance.
1126 @param[in] Slot The slot number of the SD card to send the command to.
1128 @retval EFI_SUCCESS The timeout control register is configured successfully.
1129 @retval Others The timeout control register isn't configured successfully.
1133 SdMmcHcInitTimeoutCtrl (
1134 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1142 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_TIMEOUT_CTRL
, FALSE
, sizeof (Timeout
), &Timeout
);
1148 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1151 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1152 @param[in] Slot The slot number of the SD card to send the command to.
1154 @retval EFI_SUCCESS The host controller is initialized successfully.
1155 @retval Others The host controller isn't initialized successfully.
1160 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1165 EFI_PCI_IO_PROTOCOL
*PciIo
;
1166 SD_MMC_HC_SLOT_CAP Capability
;
1169 // Notify the SD/MMC override protocol that we are about to initialize
1170 // the SD/MMC host controller.
1172 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1173 Status
= mOverride
->NotifyPhase (
1174 Private
->ControllerHandle
,
1176 EdkiiSdMmcInitHostPre
,
1178 if (EFI_ERROR (Status
)) {
1180 "%a: SD/MMC pre init notifier callback failed - %r\n",
1181 __FUNCTION__
, Status
));
1186 PciIo
= Private
->PciIo
;
1187 Capability
= Private
->Capability
[Slot
];
1189 Status
= SdMmcHcInitV4Enhancements (PciIo
, Slot
, Capability
, Private
->ControllerVersion
[Slot
]);
1190 if (EFI_ERROR (Status
)) {
1194 Status
= SdMmcHcInitClockFreq (PciIo
, Slot
, Private
->BaseClkFreq
[Slot
], Private
->ControllerVersion
[Slot
]);
1195 if (EFI_ERROR (Status
)) {
1199 Status
= SdMmcHcInitPowerVoltage (PciIo
, Slot
, Capability
);
1200 if (EFI_ERROR (Status
)) {
1204 Status
= SdMmcHcInitTimeoutCtrl (PciIo
, Slot
);
1205 if (EFI_ERROR (Status
)) {
1210 // Notify the SD/MMC override protocol that we are have just initialized
1211 // the SD/MMC host controller.
1213 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1214 Status
= mOverride
->NotifyPhase (
1215 Private
->ControllerHandle
,
1217 EdkiiSdMmcInitHostPost
,
1219 if (EFI_ERROR (Status
)) {
1221 "%a: SD/MMC post init notifier callback failed - %r\n",
1222 __FUNCTION__
, Status
));
1229 Set SD Host Controler control 2 registry according to selected speed.
1231 @param[in] ControllerHandle The handle of the controller.
1232 @param[in] PciIo The PCI IO protocol instance.
1233 @param[in] Slot The slot number of the SD card to send the command to.
1234 @param[in] Timing The timing to select.
1236 @retval EFI_SUCCESS The timing is set successfully.
1237 @retval Others The timing isn't set successfully.
1240 SdMmcHcUhsSignaling (
1241 IN EFI_HANDLE ControllerHandle
,
1242 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1244 IN SD_MMC_BUS_MODE Timing
1250 HostCtrl2
= (UINT8
)~SD_MMC_HC_CTRL_UHS_MASK
;
1251 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1252 if (EFI_ERROR (Status
)) {
1258 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR12
;
1261 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR25
;
1264 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR50
;
1266 case SdMmcUhsSdr104
:
1267 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR104
;
1270 HostCtrl2
= SD_MMC_HC_CTRL_UHS_DDR50
;
1272 case SdMmcMmcLegacy
:
1273 HostCtrl2
= SD_MMC_HC_CTRL_MMC_LEGACY
;
1276 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_SDR
;
1279 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_DDR
;
1282 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS200
;
1285 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS400
;
1291 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1292 if (EFI_ERROR (Status
)) {
1296 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1297 Status
= mOverride
->NotifyPhase (
1300 EdkiiSdMmcUhsSignaling
,
1303 if (EFI_ERROR (Status
)) {
1306 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1320 @param[in] PciIo The PCI IO protocol instance.
1321 @param[in] Slot The slot number of the SD card to send the command to.
1322 @param[in] On The boolean to turn on/off LED.
1324 @retval EFI_SUCCESS The LED is turned on/off successfully.
1325 @retval Others The LED isn't turned on/off successfully.
1330 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1340 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1342 HostCtrl1
= (UINT8
)~BIT0
;
1343 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1350 Build ADMA descriptor table for transfer.
1352 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1354 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1355 @param[in] ControllerVer The version of host controller.
1357 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1358 @retval Others The ADMA descriptor table isn't created successfully.
1362 BuildAdmaDescTable (
1363 IN SD_MMC_HC_TRB
*Trb
,
1364 IN UINT16 ControllerVer
1367 EFI_PHYSICAL_ADDRESS Data
;
1374 EFI_PCI_IO_PROTOCOL
*PciIo
;
1377 BOOLEAN AddressingMode64
;
1378 BOOLEAN DataLength26
;
1379 UINT32 AdmaMaxDataPerLine
;
1383 AddressingMode64
= FALSE
;
1384 DataLength26
= FALSE
;
1385 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_16B
;
1386 DescSize
= sizeof (SD_MMC_HC_ADMA_32_DESC_LINE
);
1389 Data
= Trb
->DataPhy
;
1390 DataLen
= Trb
->DataLen
;
1391 PciIo
= Trb
->Private
->PciIo
;
1394 // Detect whether 64bit addressing is supported.
1396 if (ControllerVer
>= SD_MMC_HC_CTRL_VER_400
) {
1397 Status
= SdMmcHcCheckMmioSet(PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof(UINT16
),
1398 SD_MMC_HC_V4_EN
|SD_MMC_HC_64_ADDR_EN
, SD_MMC_HC_V4_EN
|SD_MMC_HC_64_ADDR_EN
);
1399 if (!EFI_ERROR (Status
)) {
1400 AddressingMode64
= TRUE
;
1401 DescSize
= sizeof (SD_MMC_HC_ADMA_64_DESC_LINE
);
1405 // Check for valid ranges in 32bit ADMA Descriptor Table
1407 if (!AddressingMode64
&&
1408 ((Data
>= 0x100000000ul
) || ((Data
+ DataLen
) > 0x100000000ul
))) {
1409 return EFI_INVALID_PARAMETER
;
1412 // Check address field alignment
1414 if (AddressingMode64
) {
1416 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1418 if ((Data
& (BIT0
| BIT1
| BIT2
)) != 0) {
1419 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data
));
1423 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1425 if ((Data
& (BIT0
| BIT1
)) != 0) {
1426 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data
));
1430 // Detect whether 26bit data length is supported.
1432 Status
= SdMmcHcCheckMmioSet(PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof(UINT16
),
1433 SD_MMC_HC_26_DATA_LEN_ADMA_EN
, SD_MMC_HC_26_DATA_LEN_ADMA_EN
);
1434 if (!EFI_ERROR (Status
)) {
1435 DataLength26
= TRUE
;
1436 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_26B
;
1439 Entries
= DivU64x32 ((DataLen
+ AdmaMaxDataPerLine
- 1), AdmaMaxDataPerLine
);
1440 TableSize
= (UINTN
)MultU64x32 (Entries
, DescSize
);
1441 Trb
->AdmaPages
= (UINT32
)EFI_SIZE_TO_PAGES (TableSize
);
1442 Status
= PciIo
->AllocateBuffer (
1445 EfiBootServicesData
,
1446 EFI_SIZE_TO_PAGES (TableSize
),
1450 if (EFI_ERROR (Status
)) {
1451 return EFI_OUT_OF_RESOURCES
;
1453 ZeroMem (AdmaDesc
, TableSize
);
1455 Status
= PciIo
->Map (
1457 EfiPciIoOperationBusMasterCommonBuffer
,
1464 if (EFI_ERROR (Status
) || (Bytes
!= TableSize
)) {
1466 // Map error or unable to map the whole RFis buffer into a contiguous region.
1470 EFI_SIZE_TO_PAGES (TableSize
),
1473 return EFI_OUT_OF_RESOURCES
;
1476 if ((!AddressingMode64
) &&
1477 (UINT64
)(UINTN
)Trb
->AdmaDescPhy
> 0x100000000ul
) {
1479 // The ADMA doesn't support 64bit addressing.
1487 EFI_SIZE_TO_PAGES (TableSize
),
1490 return EFI_DEVICE_ERROR
;
1493 Remaining
= DataLen
;
1495 if (!AddressingMode64
) {
1496 Trb
->Adma32Desc
= AdmaDesc
;
1497 Trb
->Adma64Desc
= NULL
;
1499 Trb
->Adma64Desc
= AdmaDesc
;
1500 Trb
->Adma32Desc
= NULL
;
1502 for (Index
= 0; Index
< Entries
; Index
++) {
1503 if (!AddressingMode64
) {
1504 if (Remaining
<= AdmaMaxDataPerLine
) {
1505 Trb
->Adma32Desc
[Index
].Valid
= 1;
1506 Trb
->Adma32Desc
[Index
].Act
= 2;
1508 Trb
->Adma32Desc
[Index
].UpperLength
= (UINT16
)(Remaining
>> 16);
1510 Trb
->Adma32Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1511 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1514 Trb
->Adma32Desc
[Index
].Valid
= 1;
1515 Trb
->Adma32Desc
[Index
].Act
= 2;
1517 Trb
->Adma32Desc
[Index
].UpperLength
= 0;
1519 Trb
->Adma32Desc
[Index
].LowerLength
= 0;
1520 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1523 if (Remaining
<= AdmaMaxDataPerLine
) {
1524 Trb
->Adma64Desc
[Index
].Valid
= 1;
1525 Trb
->Adma64Desc
[Index
].Act
= 2;
1527 Trb
->Adma64Desc
[Index
].UpperLength
= (UINT16
)(Remaining
>> 16);
1529 Trb
->Adma64Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1530 Trb
->Adma64Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1531 Trb
->Adma64Desc
[Index
].UpperAddress
= (UINT32
)(Address
>> 32);
1534 Trb
->Adma64Desc
[Index
].Valid
= 1;
1535 Trb
->Adma64Desc
[Index
].Act
= 2;
1537 Trb
->Adma64Desc
[Index
].UpperLength
= 0;
1539 Trb
->Adma64Desc
[Index
].LowerLength
= 0;
1540 Trb
->Adma64Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1541 Trb
->Adma64Desc
[Index
].UpperAddress
= (UINT32
)(Address
>> 32);
1545 Remaining
-= AdmaMaxDataPerLine
;
1546 Address
+= AdmaMaxDataPerLine
;
1550 // Set the last descriptor line as end of descriptor table
1552 AddressingMode64
? (Trb
->Adma64Desc
[Index
].End
= 1) : (Trb
->Adma32Desc
[Index
].End
= 1);
1557 Create a new TRB for the SD/MMC cmd request.
1559 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1560 @param[in] Slot The slot number of the SD card to send the command to.
1561 @param[in] Packet A pointer to the SD command data structure.
1562 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1563 not NULL, then nonblocking I/O is performed, and Event
1564 will be signaled when the Packet completes.
1566 @return Created Trb or NULL.
1571 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1573 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
,
1580 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
1581 EFI_PCI_IO_PROTOCOL
*PciIo
;
1584 Trb
= AllocateZeroPool (sizeof (SD_MMC_HC_TRB
));
1589 Trb
->Signature
= SD_MMC_HC_TRB_SIG
;
1591 Trb
->BlockSize
= 0x200;
1592 Trb
->Packet
= Packet
;
1594 Trb
->Started
= FALSE
;
1595 Trb
->Timeout
= Packet
->Timeout
;
1596 Trb
->Private
= Private
;
1598 if ((Packet
->InTransferLength
!= 0) && (Packet
->InDataBuffer
!= NULL
)) {
1599 Trb
->Data
= Packet
->InDataBuffer
;
1600 Trb
->DataLen
= Packet
->InTransferLength
;
1602 } else if ((Packet
->OutTransferLength
!= 0) && (Packet
->OutDataBuffer
!= NULL
)) {
1603 Trb
->Data
= Packet
->OutDataBuffer
;
1604 Trb
->DataLen
= Packet
->OutTransferLength
;
1606 } else if ((Packet
->InTransferLength
== 0) && (Packet
->OutTransferLength
== 0)) {
1613 if ((Trb
->DataLen
!= 0) && (Trb
->DataLen
< Trb
->BlockSize
)) {
1614 Trb
->BlockSize
= (UINT16
)Trb
->DataLen
;
1617 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1618 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1619 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1620 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1621 Trb
->Mode
= SdMmcPioMode
;
1624 Flag
= EfiPciIoOperationBusMasterWrite
;
1626 Flag
= EfiPciIoOperationBusMasterRead
;
1629 PciIo
= Private
->PciIo
;
1630 if (Trb
->DataLen
!= 0) {
1631 MapLength
= Trb
->DataLen
;
1632 Status
= PciIo
->Map (
1640 if (EFI_ERROR (Status
) || (Trb
->DataLen
!= MapLength
)) {
1641 Status
= EFI_BAD_BUFFER_SIZE
;
1646 if (Trb
->DataLen
== 0) {
1647 Trb
->Mode
= SdMmcNoData
;
1648 } else if (Private
->Capability
[Slot
].Adma2
!= 0) {
1649 Trb
->Mode
= SdMmcAdmaMode
;
1650 Status
= BuildAdmaDescTable (Trb
, Private
->ControllerVersion
[Slot
]);
1651 if (EFI_ERROR (Status
)) {
1652 PciIo
->Unmap (PciIo
, Trb
->DataMap
);
1655 } else if (Private
->Capability
[Slot
].Sdma
!= 0) {
1656 Trb
->Mode
= SdMmcSdmaMode
;
1658 Trb
->Mode
= SdMmcPioMode
;
1662 if (Event
!= NULL
) {
1663 OldTpl
= gBS
->RaiseTPL (TPL_NOTIFY
);
1664 InsertTailList (&Private
->Queue
, &Trb
->TrbList
);
1665 gBS
->RestoreTPL (OldTpl
);
1676 Free the resource used by the TRB.
1678 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1683 IN SD_MMC_HC_TRB
*Trb
1686 EFI_PCI_IO_PROTOCOL
*PciIo
;
1688 PciIo
= Trb
->Private
->PciIo
;
1690 if (Trb
->AdmaMap
!= NULL
) {
1696 if (Trb
->Adma32Desc
!= NULL
) {
1703 if (Trb
->Adma64Desc
!= NULL
) {
1710 if (Trb
->DataMap
!= NULL
) {
1721 Check if the env is ready for execute specified TRB.
1723 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1724 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1726 @retval EFI_SUCCESS The env is ready for TRB execution.
1727 @retval EFI_NOT_READY The env is not ready for TRB execution.
1728 @retval Others Some erros happen.
1733 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1734 IN SD_MMC_HC_TRB
*Trb
1738 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1739 EFI_PCI_IO_PROTOCOL
*PciIo
;
1740 UINT32 PresentState
;
1742 Packet
= Trb
->Packet
;
1744 if ((Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) ||
1745 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR1b
) ||
1746 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR5b
)) {
1748 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1749 // the Present State register to be 0
1751 PresentState
= BIT0
| BIT1
;
1754 // Wait Command Inhibit (CMD) in the Present State register
1757 PresentState
= BIT0
;
1760 PciIo
= Private
->PciIo
;
1761 Status
= SdMmcHcCheckMmioSet (
1764 SD_MMC_HC_PRESENT_STATE
,
1765 sizeof (PresentState
),
1774 Wait for the env to be ready for execute specified TRB.
1776 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1777 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1779 @retval EFI_SUCCESS The env is ready for TRB execution.
1780 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1781 @retval Others Some erros happen.
1786 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1787 IN SD_MMC_HC_TRB
*Trb
1791 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1793 BOOLEAN InfiniteWait
;
1796 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1798 Packet
= Trb
->Packet
;
1799 Timeout
= Packet
->Timeout
;
1801 InfiniteWait
= TRUE
;
1803 InfiniteWait
= FALSE
;
1806 while (InfiniteWait
|| (Timeout
> 0)) {
1808 // Check Trb execution result by reading Normal Interrupt Status register.
1810 Status
= SdMmcCheckTrbEnv (Private
, Trb
);
1811 if (Status
!= EFI_NOT_READY
) {
1815 // Stall for 1 microsecond.
1826 Execute the specified TRB.
1828 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1829 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1831 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1832 @retval Others Some erros happen when sending this request to the host controller.
1837 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1838 IN SD_MMC_HC_TRB
*Trb
1842 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1843 EFI_PCI_IO_PROTOCOL
*PciIo
;
1853 BOOLEAN AddressingMode64
;
1855 AddressingMode64
= FALSE
;
1857 Packet
= Trb
->Packet
;
1858 PciIo
= Trb
->Private
->PciIo
;
1860 // Clear all bits in Error Interrupt Status Register
1863 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ERR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1864 if (EFI_ERROR (Status
)) {
1868 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1871 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1872 if (EFI_ERROR (Status
)) {
1876 // Set Host Control 1 register DMA Select field
1878 if (Trb
->Mode
== SdMmcAdmaMode
) {
1880 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1881 if (EFI_ERROR (Status
)) {
1886 SdMmcHcLedOnOff (PciIo
, Trb
->Slot
, TRUE
);
1888 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
1889 Status
= SdMmcHcCheckMmioSet(PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof(UINT16
),
1890 SD_MMC_HC_V4_EN
|SD_MMC_HC_64_ADDR_EN
, SD_MMC_HC_V4_EN
|SD_MMC_HC_64_ADDR_EN
);
1891 if (!EFI_ERROR (Status
)) {
1892 AddressingMode64
= TRUE
;
1896 if (Trb
->Mode
== SdMmcSdmaMode
) {
1897 if ((!AddressingMode64
) &&
1898 ((UINT64
)(UINTN
)Trb
->DataPhy
>= 0x100000000ul
)) {
1899 return EFI_INVALID_PARAMETER
;
1902 SdmaAddr
= (UINT64
)(UINTN
)Trb
->DataPhy
;
1904 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
1905 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (UINT64
), &SdmaAddr
);
1907 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &SdmaAddr
);
1910 if (EFI_ERROR (Status
)) {
1913 } else if (Trb
->Mode
== SdMmcAdmaMode
) {
1914 AdmaAddr
= (UINT64
)(UINTN
)Trb
->AdmaDescPhy
;
1915 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (AdmaAddr
), &AdmaAddr
);
1916 if (EFI_ERROR (Status
)) {
1921 BlkSize
= Trb
->BlockSize
;
1922 if (Trb
->Mode
== SdMmcSdmaMode
) {
1924 // Set SDMA boundary to be 512K bytes.
1929 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_SIZE
, FALSE
, sizeof (BlkSize
), &BlkSize
);
1930 if (EFI_ERROR (Status
)) {
1935 if (Trb
->Mode
!= SdMmcNoData
) {
1937 // Calcuate Block Count.
1939 BlkCount
= (Trb
->DataLen
/ Trb
->BlockSize
);
1941 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_410
) {
1942 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &BlkCount
);
1944 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_COUNT
, FALSE
, sizeof (UINT16
), &BlkCount
);
1946 if (EFI_ERROR (Status
)) {
1950 Argument
= Packet
->SdMmcCmdBlk
->CommandArgument
;
1951 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ARG1
, FALSE
, sizeof (Argument
), &Argument
);
1952 if (EFI_ERROR (Status
)) {
1957 if (Trb
->Mode
!= SdMmcNoData
) {
1958 if (Trb
->Mode
!= SdMmcPioMode
) {
1965 TransMode
|= BIT5
| BIT1
;
1968 // Only SD memory card needs to use AUTO CMD12 feature.
1970 if (Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) {
1977 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_TRANS_MOD
, FALSE
, sizeof (TransMode
), &TransMode
);
1978 if (EFI_ERROR (Status
)) {
1982 Cmd
= (UINT16
)LShiftU64(Packet
->SdMmcCmdBlk
->CommandIndex
, 8);
1983 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) {
1987 // Convert ResponseType to value
1989 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
1990 switch (Packet
->SdMmcCmdBlk
->ResponseType
) {
1991 case SdMmcResponseTypeR1
:
1992 case SdMmcResponseTypeR5
:
1993 case SdMmcResponseTypeR6
:
1994 case SdMmcResponseTypeR7
:
1995 Cmd
|= (BIT1
| BIT3
| BIT4
);
1997 case SdMmcResponseTypeR2
:
1998 Cmd
|= (BIT0
| BIT3
);
2000 case SdMmcResponseTypeR3
:
2001 case SdMmcResponseTypeR4
:
2004 case SdMmcResponseTypeR1b
:
2005 case SdMmcResponseTypeR5b
:
2006 Cmd
|= (BIT0
| BIT1
| BIT3
| BIT4
);
2016 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_COMMAND
, FALSE
, sizeof (Cmd
), &Cmd
);
2021 Check the TRB execution result.
2023 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2024 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2026 @retval EFI_SUCCESS The TRB is executed successfully.
2027 @retval EFI_NOT_READY The TRB is not completed for execution.
2028 @retval Others Some erros happen when executing this request.
2032 SdMmcCheckTrbResult (
2033 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2034 IN SD_MMC_HC_TRB
*Trb
2038 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2047 Packet
= Trb
->Packet
;
2049 // Check Trb execution result by reading Normal Interrupt Status register.
2051 Status
= SdMmcHcRwMmio (
2054 SD_MMC_HC_NOR_INT_STS
,
2059 if (EFI_ERROR (Status
)) {
2063 // Check Transfer Complete bit is set or not.
2065 if ((IntStatus
& BIT1
) == BIT1
) {
2066 if ((IntStatus
& BIT15
) == BIT15
) {
2068 // Read Error Interrupt Status register to check if the error is
2069 // Data Timeout Error.
2070 // If yes, treat it as success as Transfer Complete has higher
2071 // priority than Data Timeout Error.
2073 Status
= SdMmcHcRwMmio (
2076 SD_MMC_HC_ERR_INT_STS
,
2081 if (!EFI_ERROR (Status
)) {
2082 if ((IntStatus
& BIT4
) == BIT4
) {
2083 Status
= EFI_SUCCESS
;
2085 Status
= EFI_DEVICE_ERROR
;
2093 // Check if there is a error happened during cmd execution.
2094 // If yes, then do error recovery procedure to follow SD Host Controller
2095 // Simplified Spec 3.0 section 3.10.1.
2097 if ((IntStatus
& BIT15
) == BIT15
) {
2098 Status
= SdMmcHcRwMmio (
2101 SD_MMC_HC_ERR_INT_STS
,
2106 if (EFI_ERROR (Status
)) {
2109 if ((IntStatus
& 0x0F) != 0) {
2112 if ((IntStatus
& 0xF0) != 0) {
2116 Status
= SdMmcHcRwMmio (
2124 if (EFI_ERROR (Status
)) {
2127 Status
= SdMmcHcWaitMmioSet (
2134 SD_MMC_HC_GENERIC_TIMEOUT
2136 if (EFI_ERROR (Status
)) {
2140 Status
= EFI_DEVICE_ERROR
;
2144 // Check if DMA interrupt is signalled for the SDMA transfer.
2146 if ((Trb
->Mode
== SdMmcSdmaMode
) && ((IntStatus
& BIT3
) == BIT3
)) {
2148 // Clear DMA interrupt bit.
2151 Status
= SdMmcHcRwMmio (
2154 SD_MMC_HC_NOR_INT_STS
,
2159 if (EFI_ERROR (Status
)) {
2163 // Update SDMA Address register.
2165 SdmaAddr
= SD_MMC_SDMA_ROUND_UP ((UINTN
)Trb
->DataPhy
, SD_MMC_SDMA_BOUNDARY
);
2167 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2168 Status
= SdMmcHcRwMmio (
2171 SD_MMC_HC_ADMA_SYS_ADDR
,
2177 Status
= SdMmcHcRwMmio (
2180 SD_MMC_HC_SDMA_ADDR
,
2187 if (EFI_ERROR (Status
)) {
2190 Trb
->DataPhy
= (UINT64
)(UINTN
)SdmaAddr
;
2193 if ((Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeAdtc
) &&
2194 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR1b
) &&
2195 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR5b
)) {
2196 if ((IntStatus
& BIT0
) == BIT0
) {
2197 Status
= EFI_SUCCESS
;
2202 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
2203 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
2204 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
2205 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
2207 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2208 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2209 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2211 if ((IntStatus
& BIT5
) == BIT5
) {
2213 // Clear Buffer Read Ready interrupt at first.
2216 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
2218 // Read data out from Buffer Port register
2220 for (PioLength
= 0; PioLength
< Trb
->DataLen
; PioLength
+= 4) {
2221 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_BUF_DAT_PORT
, TRUE
, 4, (UINT8
*)Trb
->Data
+ PioLength
);
2223 Status
= EFI_SUCCESS
;
2228 Status
= EFI_NOT_READY
;
2231 // Get response data when the cmd is executed successfully.
2233 if (!EFI_ERROR (Status
)) {
2234 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
2235 for (Index
= 0; Index
< 4; Index
++) {
2236 Status
= SdMmcHcRwMmio (
2239 SD_MMC_HC_RESPONSE
+ Index
* 4,
2244 if (EFI_ERROR (Status
)) {
2245 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
2249 CopyMem (Packet
->SdMmcStatusBlk
, Response
, sizeof (Response
));
2253 if (Status
!= EFI_NOT_READY
) {
2254 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
2261 Wait for the TRB execution result.
2263 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2264 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2266 @retval EFI_SUCCESS The TRB is executed successfully.
2267 @retval Others Some erros happen when executing this request.
2271 SdMmcWaitTrbResult (
2272 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2273 IN SD_MMC_HC_TRB
*Trb
2277 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2279 BOOLEAN InfiniteWait
;
2281 Packet
= Trb
->Packet
;
2283 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2285 Timeout
= Packet
->Timeout
;
2287 InfiniteWait
= TRUE
;
2289 InfiniteWait
= FALSE
;
2292 while (InfiniteWait
|| (Timeout
> 0)) {
2294 // Check Trb execution result by reading Normal Interrupt Status register.
2296 Status
= SdMmcCheckTrbResult (Private
, Trb
);
2297 if (Status
!= EFI_NOT_READY
) {
2301 // Stall for 1 microsecond.