;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
\r
ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint\r
ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint\r
+\r
+global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress)\r
+ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress):\r
+ ret\r
/** @file\r
SMM STM support functions\r
\r
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
BOOLEAN mStmConfigurationTableInitialized = FALSE;\r
\r
-\r
/**\r
The constructor function\r
\r
EFI_HOB_GUID_TYPE *GuidHob;\r
EFI_SMRAM_DESCRIPTOR *SmramDescriptor;\r
\r
+ //\r
+ // Initialize address fixup\r
+ //\r
+ SmmCpuFeaturesLibStmSmiEntryFixupAddress ();\r
+\r
//\r
// Call the common constructor function\r
//\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
mov cr0, rbx\r
retf\r
@LongMode: ; long mode (64-bit code) starts here\r
- mov rax, ASM_PFX(gStmSmiHandlerIdtr)\r
+ mov rax, strict qword 0 ; mov rax, ASM_PFX(gStmSmiHandlerIdtr)\r
+StmSmiEntrySmiHandlerIdtrAbsAddr:\r
lidt [rax]\r
lea ebx, [rdi + DSC_OFFSET]\r
mov ax, [rbx + DSC_DS]\r
mov gs, eax\r
mov ax, [rbx + DSC_SS]\r
mov ss, eax\r
-\r
+ mov rax, strict qword 0 ; mov rax, CommonHandler\r
+StmSmiEntryCommonHandlerAbsAddr:\r
+ jmp rax\r
CommonHandler:\r
mov rbx, [rsp + 0x08] ; rbx <- CpuIndex\r
\r
add rsp, -0x20\r
\r
mov rcx, rbx\r
- mov rax, ASM_PFX(CpuSmmDebugEntry)\r
- call rax\r
+ call ASM_PFX(CpuSmmDebugEntry)\r
\r
mov rcx, rbx\r
- mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of SmiRedezvous\r
- call rax\r
+ call ASM_PFX(SmiRendezvous)\r
\r
mov rcx, rbx\r
- mov rax, ASM_PFX(CpuSmmDebugExit)\r
- call rax\r
+ call ASM_PFX(CpuSmmDebugExit)\r
\r
add rsp, 0x20\r
\r
\r
add rsp, 0x200\r
\r
- mov rax, ASM_PFX(gStmXdSupported)\r
+ lea rax, [ASM_PFX(gStmXdSupported)]\r
mov al, [rax]\r
cmp al, 0\r
jz .1\r
; Check XD disable bit\r
;\r
xor r8, r8\r
- mov rax, ASM_PFX(gStmXdSupported)\r
+ lea rax, [ASM_PFX(gStmXdSupported)]\r
mov al, [rax]\r
cmp al, 0\r
jz @StmXdDone\r
\r
; below step is needed, because STM does not run above code.\r
; we have to run below code to set IDT/CR0/CR4\r
-\r
- mov rax, ASM_PFX(gStmSmiHandlerIdtr)\r
+ mov rax, strict qword 0 ; mov rax, ASM_PFX(gStmSmiHandlerIdtr)\r
+StmSmiHandlerIdtrAbsAddr:\r
lidt [rax]\r
\r
mov rax, cr0\r
\r
ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint\r
ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint\r
+\r
+global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress)\r
+ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress):\r
+ lea rax, [ASM_PFX(gStmSmiHandlerIdtr)]\r
+ lea rcx, [StmSmiEntrySmiHandlerIdtrAbsAddr]\r
+ mov qword [rcx - 8], rax\r
+ lea rcx, [StmSmiHandlerIdtrAbsAddr]\r
+ mov qword [rcx - 8], rax\r
+\r
+ lea rax, [CommonHandler]\r
+ lea rcx, [StmSmiEntryCommonHandlerAbsAddr]\r
+ mov qword [rcx - 8], rax\r
+ ret\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; Check XD disable bit\r
;\r
xor r8, r8\r
- mov rax, ASM_PFX(gStmXdSupported)\r
+ lea rax, [ASM_PFX(gStmXdSupported)]\r
mov al, [rax]\r
cmp al, 0\r
jz @StmXdDone1\r
call ASM_PFX(SmmStmSetup)\r
add rsp, 0x20\r
\r
- mov rax, ASM_PFX(gStmXdSupported)\r
+ lea rax, [ASM_PFX(gStmXdSupported)]\r
mov al, [rax]\r
cmp al, 0\r
jz .11\r
; Check XD disable bit\r
;\r
xor r8, r8\r
- mov rax, ASM_PFX(gStmXdSupported)\r
+ lea rax, [ASM_PFX(gStmXdSupported)]\r
mov al, [rax]\r
cmp al, 0\r
jz @StmXdDone2\r
call ASM_PFX(SmmStmTeardown)\r
add rsp, 0x20\r
\r
- mov rax, ASM_PFX(gStmXdSupported)\r
+ lea rax, [ASM_PFX(gStmXdSupported)]\r
mov al, [rax]\r
cmp al, 0\r
jz .12\r