-typedef enum {\r
- //\r
- // Capability register offset\r
- //\r
- EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset\r
- EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h\r
- EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset\r
-\r
- //\r
- // Capability register bit definition\r
- //\r
- HCSP_NPORTS = 0x0F, // Number of root hub port\r
- HCCP_64BIT = 0x01, // 64-bit addressing capability\r
-\r
- //\r
- // Operational register offset\r
- //\r
- EHC_USBCMD_OFFSET = 0x0, // USB command register offset\r
- EHC_USBSTS_OFFSET = 0x04, // Statue register offset\r
- EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset\r
- EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset\r
- EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset\r
- EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset\r
- EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset\r
- EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset\r
- EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset\r
-\r
- EHC_FRAME_LEN = 1024,\r
-\r
- //\r
- // Register bit definition\r
- //\r
- CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC\r
-\r
- USBCMD_RUN = 0x01, // Run/stop\r
- USBCMD_RESET = 0x02, // Start the host controller reset\r
- USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule\r
- USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule\r
- USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell\r
-\r
- USBSTS_IAA = 0x20, // Interrupt on async advance\r
- USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status\r
- USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status\r
- USBSTS_HALT = 0x1000, // Host controller halted\r
- USBSTS_SYS_ERROR = 0x10, // Host system error\r
- USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC\r
- // (write clean) bits in USBSTS register\r
-\r
- PORTSC_CONN = 0x01, // Current Connect Status\r
- PORTSC_CONN_CHANGE = 0x02, // Connect Status Change\r
- PORTSC_ENABLED = 0x04, // Port Enable / Disable\r
- PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change\r
- PORTSC_OVERCUR = 0x10, // Over current Active\r
- PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change\r
- PORSTSC_RESUME = 0x40, // Force Port Resume\r
- PORTSC_SUSPEND = 0x80, // Port Suspend State\r
- PORTSC_RESET = 0x100, // Port Reset\r
- PORTSC_LINESTATE_K = 0x400, // Line Status K-state\r
- PORTSC_LINESTATE_J = 0x800, // Line Status J-state\r
- PORTSC_POWER = 0x1000, // Port Power\r
- PORTSC_OWNER = 0x2000, // Port Owner\r
- PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,\r
- // they are WC (write clean)\r
- //\r
- // PCI Configuration Registers\r
- //\r
- EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */\r
-}EHCI_REGISTER_OFFSET;\r
+//\r
+// Register bit definition\r
+//\r
+#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r
+\r
+#define USBCMD_RUN 0x01 // Run/stop\r
+#define USBCMD_RESET 0x02 // Start the host controller reset\r
+#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r
+#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r
+#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r
+\r
+#define USBSTS_IAA 0x20 // Interrupt on async advance\r
+#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r
+#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r
+#define USBSTS_HALT 0x1000 // Host controller halted\r
+#define USBSTS_SYS_ERROR 0x10 // Host system error\r
+#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r
+ // (write clean) bits in USBSTS register\r
+\r
+#define PORTSC_CONN 0x01 // Current Connect Status\r
+#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r
+#define PORTSC_ENABLED 0x04 // Port Enable / Disable\r
+#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r
+#define PORTSC_OVERCUR 0x10 // Over current Active\r
+#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r
+#define PORSTSC_RESUME 0x40 // Force Port Resume\r
+#define PORTSC_SUSPEND 0x80 // Port Suspend State\r
+#define PORTSC_RESET 0x100 // Port Reset\r
+#define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r
+#define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r
+#define PORTSC_POWER 0x1000 // Port Power\r
+#define PORTSC_OWNER 0x2000 // Port Owner\r
+#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r
+ // they are WC (write clean)\r
+//\r
+// PCI Configuration Registers\r
+//\r
+#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r