# buffer overflow, integer overflow.\r
#\r
# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions\r
[Pcd.IA32]\r
gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleCoalesceFile ## SOMETIMES_CONSUMES\r
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ## CONSUMES\r
\r
[FeaturePcd.IA32]\r
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode ## CONSUMES\r
Common header file.\r
\r
Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
#define EXTRA_PAGE_TABLE_PAGES 8\r
\r
+#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
+\r
//\r
// This capsule PEIM puts its private data at the start of the\r
// coalesced capsule. Here's the structure definition.\r
EFI_PHYSICAL_ADDRESS MemoryBase64Ptr;\r
EFI_PHYSICAL_ADDRESS MemorySize64Ptr;\r
BOOLEAN Page1GSupport;\r
+ UINT64 AddressEncMask;\r
} SWITCH_32_TO_64_CONTEXT;\r
\r
typedef struct {\r
Capsule update PEIM for UEFI2.0\r
\r
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
(UINTN) mGdtEntries\r
};\r
\r
+\r
/**\r
The function will check if 1G page is supported.\r
\r
PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
UINTN BigPageAddress;\r
PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;\r
+ UINT64 AddressEncMask;\r
+\r
+ //\r
+ // Make sure AddressEncMask is contained to smallest supported address field.\r
+ //\r
+ AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
\r
//\r
// Create 4G page table by default,\r
//\r
// Make a PML4 Entry\r
//\r
- PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
+ PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;\r
PageMapLevel4Entry->Bits.ReadWrite = 1;\r
PageMapLevel4Entry->Bits.Present = 1;\r
\r
//\r
// Fill in the Page Directory entries\r
//\r
- PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;\r
+ PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r
PageDirectory1GEntry->Bits.ReadWrite = 1;\r
PageDirectory1GEntry->Bits.Present = 1;\r
PageDirectory1GEntry->Bits.MustBe1 = 1;\r
//\r
// Fill in a Page Directory Pointer Entries\r
//\r
- PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
+ PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;\r
PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
PageDirectoryPointerEntry->Bits.Present = 1;\r
\r
//\r
// Fill in the Page Directory entries\r
//\r
- PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
+ PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r
PageDirectoryEntry->Bits.ReadWrite = 1;\r
PageDirectoryEntry->Bits.Present = 1;\r
PageDirectoryEntry->Bits.MustBe1 = 1;\r
Context.MemoryBase64Ptr = (EFI_PHYSICAL_ADDRESS)(UINTN)&MemoryBase64;\r
Context.MemorySize64Ptr = (EFI_PHYSICAL_ADDRESS)(UINTN)&MemorySize64;\r
Context.Page1GSupport = Page1GSupport;\r
+ Context.AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
\r
//\r
// Prepare data for return back\r
The X64 entrypoint is used to process capsule in long mode.\r
\r
Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINT64 PhyMask;\r
UINTN PageFaultBuffer;\r
UINTN PageFaultIndex;\r
+ UINT64 AddressEncMask;\r
//\r
// Store the uplink information for each page being used.\r
//\r
)\r
{\r
UINTN Address;\r
+ UINT64 AddressEncMask;\r
\r
Address = PageFaultContext->PageFaultBuffer + EFI_PAGES_TO_SIZE (PageFaultContext->PageFaultIndex);\r
ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));\r
\r
+ AddressEncMask = PageFaultContext->AddressEncMask;\r
+\r
//\r
// Cut the previous uplink if it exists and wasn't overwritten.\r
//\r
- if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] != NULL) && ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] & PageFaultContext->PhyMask) == Address)) {\r
+ if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] != NULL) &&\r
+ ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] & ~AddressEncMask & PageFaultContext->PhyMask) == Address)) {\r
*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = 0;\r
}\r
\r
//\r
// Link & Record the current uplink.\r
//\r
- *Uplink = Address | IA32_PG_P | IA32_PG_RW;\r
+ *Uplink = Address | AddressEncMask | IA32_PG_P | IA32_PG_RW;\r
PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = Uplink;\r
\r
PageFaultContext->PageFaultIndex = (PageFaultContext->PageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r
UINT64 *PageTable;\r
UINT64 PFAddress;\r
UINTN PTIndex;\r
+ UINT64 AddressEncMask;\r
\r
//\r
// Get the IDT Descriptor.\r
//\r
PageFaultContext = (PAGE_FAULT_CONTEXT *) (UINTN) (Idtr.Base - sizeof (PAGE_FAULT_CONTEXT));\r
PhyMask = PageFaultContext->PhyMask;\r
+ AddressEncMask = PageFaultContext->AddressEncMask;\r
\r
PFAddress = AsmReadCr2 ();\r
DEBUG ((EFI_D_ERROR, "CapsuleX64 - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
AcquirePage (PageFaultContext, &PageTable[PTIndex]);\r
}\r
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask);\r
+ PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~AddressEncMask & PhyMask);\r
PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
// PDPTE\r
if (PageFaultContext->Page1GSupport) {\r
- PageTable[PTIndex] = (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
+ PageTable[PTIndex] = ((PFAddress | AddressEncMask) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
} else {\r
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
AcquirePage (PageFaultContext, &PageTable[PTIndex]);\r
}\r
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask);\r
+ PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~AddressEncMask & PhyMask);\r
PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
// PD\r
- PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
+ PageTable[PTIndex] = ((PFAddress | AddressEncMask) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
}\r
\r
return NULL;\r
// Hook page fault handler to handle >4G request.\r
//\r
PageFaultIdtTable.PageFaultContext.Page1GSupport = EntrypointContext->Page1GSupport;\r
+ PageFaultIdtTable.PageFaultContext.AddressEncMask = EntrypointContext->AddressEncMask;\r
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) (X64Idtr.Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
HookPageFaultHandler (IdtEntry, &(PageFaultIdtTable.PageFaultContext));\r
\r
//\r
ASSERT (FALSE);\r
return EFI_SUCCESS;\r
-}
\ No newline at end of file
+}\r